Style: Revert uncrustify for portable directories (#122)
* Style: revert uncrustify portable directories
* Style: Uncrustify Some Portable files
Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 3f39bc3..8bf1ac1 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -22,7 +22,6 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
- * 1 tab == 4 spaces!
*/
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
@@ -55,13 +54,13 @@
* on the secure side. The following are the valid configuration seetings:
*
* 1. Run FreeRTOS on the Secure Side:
- * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
*
* 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
*
* 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
*/
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
@@ -612,7 +611,7 @@
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
- #else /* if defined( __ARMCC_VERSION ) */
+ #else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
@@ -802,22 +801,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
- }
- #else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0 );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@@ -835,21 +834,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -876,19 +875,20 @@
}
}
/*-----------------------------------------------------------*/
-
+/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
- BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+ BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
- void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@@ -1051,7 +1051,9 @@
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
+
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1079,8 +1081,8 @@
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
- if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
- ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
@@ -1089,7 +1091,7 @@
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
diff --git a/portable/BCC/16BitDOS/Flsh186/port.c b/portable/BCC/16BitDOS/Flsh186/port.c
index e42366a..45bf893 100644
--- a/portable/BCC/16BitDOS/Flsh186/port.c
+++ b/portable/BCC/16BitDOS/Flsh186/port.c
@@ -26,22 +26,22 @@
*/
/*
- * Changes from V1.00:
- *
- + Call to taskYIELD() from within tick ISR has been replaced by the more
- + efficient portSWITCH_CONTEXT().
- + ISR function definitions renamed to include the prv prefix.
- +
- + Changes from V2.6.1
- +
- + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
- + macro to be consistent with the later ports.
- */
+Changes from V1.00:
+
+ + Call to taskYIELD() from within tick ISR has been replaced by the more
+ efficient portSWITCH_CONTEXT().
+ + ISR function definitions renamed to include the prv prefix.
+
+Changes from V2.6.1
+
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+ macro to be consistent with the later ports.
+*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Flashlite 186
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Flashlite 186
+ * port.
+ *----------------------------------------------------------*/
#include <dos.h>
#include <stdlib.h>
@@ -53,13 +53,13 @@
/*lint -e950 Non ANSI reserved words okay in this file only. */
-#define portTIMER_EOI_TYPE ( 8 )
-#define portRESET_PIC() portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
-#define portTIMER_INT_NUMBER 0x12
+#define portTIMER_EOI_TYPE ( 8 )
+#define portRESET_PIC() portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
+#define portTIMER_INT_NUMBER 0x12
-#define portTIMER_1_CONTROL_REGISTER ( ( uint16_t ) 0xff5e )
-#define portTIMER_0_CONTROL_REGISTER ( ( uint16_t ) 0xff56 )
-#define portTIMER_INTERRUPT_ENABLE ( ( uint16_t ) 0x2000 )
+#define portTIMER_1_CONTROL_REGISTER ( ( uint16_t ) 0xff5e )
+#define portTIMER_0_CONTROL_REGISTER ( ( uint16_t ) 0xff56 )
+#define portTIMER_INTERRUPT_ENABLE ( ( uint16_t ) 0x2000 )
/* Setup the hardware to generate the required tick frequency. */
static void prvSetTickFrequency( uint32_t ulTickRateHz );
@@ -68,17 +68,15 @@
static void prvExitFunction( void );
/* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
- static void __interrupt __far prvPreemptiveTick( void );
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+ /* Tick service routine used by the scheduler when preemptive scheduling is
+ being used. */
+ static void __interrupt __far prvPreemptiveTick( void );
#else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
- static void __interrupt __far prvNonPreemptiveTick( void );
+ /* Tick service routine used by the scheduler when cooperative scheduling is
+ being used. */
+ static void __interrupt __far prvNonPreemptiveTick( void );
#endif
/* Trap routine used by taskYIELD() to manually cause a context switch. */
@@ -90,9 +88,9 @@
static BaseType_t xSchedulerRunning = pdFALSE;
/* Points to the original routine installed on the vector we use for manual
- * context switches. This is then used to restore the original routine during
- * prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISR )();
+context switches. This is then used to restore the original routine during
+prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISR )();
/* Used to restore the original DOS context when the scheduler is ended. */
static jmp_buf xJumpBuf;
@@ -102,145 +100,145 @@
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* This is called with interrupts already disabled. */
+ /* This is called with interrupts already disabled. */
- /* Remember what was on the interrupts we are going to use
- * so we can put them back later if required. */
- pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+ /* Remember what was on the interrupts we are going to use
+ so we can put them back later if required. */
+ pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
- /* Put our manual switch (yield) function on a known
- * vector. */
- _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+ /* Put our manual switch (yield) function on a known
+ vector. */
+ _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
- #if ( configUSE_PREEMPTION == 1 )
- {
- /* Put our tick switch function on the timer interrupt. */
- _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
- }
- #else
- {
- /* We want the timer interrupt to just increment the tick count. */
- _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
- }
- #endif
+ #if( configUSE_PREEMPTION == 1 )
+ {
+ /* Put our tick switch function on the timer interrupt. */
+ _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+ }
+ #else
+ {
+ /* We want the timer interrupt to just increment the tick count. */
+ _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+ }
+ #endif
- prvSetTickFrequency( configTICK_RATE_HZ );
+ prvSetTickFrequency( configTICK_RATE_HZ );
- /* Clean up function if we want to return to DOS. */
- if( setjmp( xJumpBuf ) != 0 )
- {
- prvExitFunction();
- xSchedulerRunning = pdFALSE;
- }
- else
- {
- xSchedulerRunning = pdTRUE;
+ /* Clean up function if we want to return to DOS. */
+ if( setjmp( xJumpBuf ) != 0 )
+ {
+ prvExitFunction();
+ xSchedulerRunning = pdFALSE;
+ }
+ else
+ {
+ xSchedulerRunning = pdTRUE;
- /* Kick off the scheduler by setting up the context of the first task. */
- portFIRST_CONTEXT();
- }
+ /* Kick off the scheduler by setting up the context of the first task. */
+ portFIRST_CONTEXT();
+ }
- return xSchedulerRunning;
+ return xSchedulerRunning;
}
/*-----------------------------------------------------------*/
/* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
- static void __interrupt __far prvPreemptiveTick( void )
- {
- /* Get the scheduler to update the task states following the tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Switch in the context of the next task to be run. */
- portSWITCH_CONTEXT();
- }
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+ static void __interrupt __far prvPreemptiveTick( void )
+ {
+ /* Get the scheduler to update the task states following the tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Switch in the context of the next task to be run. */
+ portSWITCH_CONTEXT();
+ }
- /* Reset the PIC ready for the next time. */
- portRESET_PIC();
- }
-#else /* if ( configUSE_PREEMPTION == 1 ) */
- static void __interrupt __far prvNonPreemptiveTick( void )
- {
- /* Same as preemptive tick, but the cooperative scheduler is being used
- * so we don't have to switch in the context of the next task. */
- xTaskIncrementTick();
- portRESET_PIC();
- }
-#endif /* if ( configUSE_PREEMPTION == 1 ) */
+ /* Reset the PIC ready for the next time. */
+ portRESET_PIC();
+ }
+#else
+ static void __interrupt __far prvNonPreemptiveTick( void )
+ {
+ /* Same as preemptive tick, but the cooperative scheduler is being used
+ so we don't have to switch in the context of the next task. */
+ xTaskIncrementTick();
+ portRESET_PIC();
+ }
+#endif
/*-----------------------------------------------------------*/
static void __interrupt __far prvYieldProcessor( void )
{
- /* Switch in the context of the next task to be run. */
- portSWITCH_CONTEXT();
+ /* Switch in the context of the next task to be run. */
+ portSWITCH_CONTEXT();
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Jump back to the processor state prior to starting the
- * scheduler. This means we are not going to be using a
- * task stack frame so the task can be deleted. */
- longjmp( xJumpBuf, 1 );
+ /* Jump back to the processor state prior to starting the
+ scheduler. This means we are not going to be using a
+ task stack frame so the task can be deleted. */
+ longjmp( xJumpBuf, 1 );
}
/*-----------------------------------------------------------*/
static void prvExitFunction( void )
{
- const uint16_t usTimerDisable = 0x0000;
- uint16_t usTimer0Control;
+const uint16_t usTimerDisable = 0x0000;
+uint16_t usTimer0Control;
- /* Interrupts should be disabled here anyway - but no
- * harm in making sure. */
- portDISABLE_INTERRUPTS();
+ /* Interrupts should be disabled here anyway - but no
+ harm in making sure. */
+ portDISABLE_INTERRUPTS();
+ if( xSchedulerRunning == pdTRUE )
+ {
+ /* Put back the switch interrupt routines that was in place
+ before the scheduler started. */
+ _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+ }
- if( xSchedulerRunning == pdTRUE )
- {
- /* Put back the switch interrupt routines that was in place
- * before the scheduler started. */
- _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
- }
+ /* Disable the timer used for the tick to ensure the scheduler is
+ not called before restoring interrupts. There was previously nothing
+ on this timer so there is no old ISR to restore. */
+ portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
- /* Disable the timer used for the tick to ensure the scheduler is
- * not called before restoring interrupts. There was previously nothing
- * on this timer so there is no old ISR to restore. */
- portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
-
- /* Restart the DOS tick. */
- usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
- usTimer0Control |= portTIMER_INTERRUPT_ENABLE;
- portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+ /* Restart the DOS tick. */
+ usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+ usTimer0Control |= portTIMER_INTERRUPT_ENABLE;
+ portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
- portENABLE_INTERRUPTS();
+ portENABLE_INTERRUPTS();
}
/*-----------------------------------------------------------*/
static void prvSetTickFrequency( uint32_t ulTickRateHz )
{
- const uint16_t usMaxCountRegister = 0xff5a;
- const uint16_t usTimerPriorityRegister = 0xff32;
- const uint16_t usTimerEnable = 0xC000;
- const uint16_t usRetrigger = 0x0001;
- const uint16_t usTimerHighPriority = 0x0000;
- uint16_t usTimer0Control;
+const uint16_t usMaxCountRegister = 0xff5a;
+const uint16_t usTimerPriorityRegister = 0xff32;
+const uint16_t usTimerEnable = 0xC000;
+const uint16_t usRetrigger = 0x0001;
+const uint16_t usTimerHighPriority = 0x0000;
+uint16_t usTimer0Control;
/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
- const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL;
+const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL;
- uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
+uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
- portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
- portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
- portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );
+ portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
+ portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
+ portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );
- /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */
- usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
- usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;
- portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+ /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */
+ usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+ usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;
+ portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
}
/*lint +e950 */
+
diff --git a/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/portable/BCC/16BitDOS/Flsh186/prtmacro.h
index cfd36e1..e96ac83 100644
--- a/portable/BCC/16BitDOS/Flsh186/prtmacro.h
+++ b/portable/BCC/16BitDOS/Flsh186/prtmacro.h
@@ -39,59 +39,59 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE long
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint16_t
-#define portBASE_TYPE portSHORT
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE long
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE portSHORT
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Critical section handling. */
-#define portENTER_CRITICAL() \
- __asm{ pushf } \
- __asm{ cli } \
+#define portENTER_CRITICAL() __asm{ pushf } \
+ __asm{ cli } \
-#define portEXIT_CRITICAL() __asm{ popf }
+#define portEXIT_CRITICAL() __asm{ popf }
-#define portDISABLE_INTERRUPTS() __asm{ cli }
+#define portDISABLE_INTERRUPTS() __asm{ cli }
-#define portENABLE_INTERRUPTS() __asm{ sti }
+#define portENABLE_INTERRUPTS() __asm{ sti }
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portNOP() __asm{ nop }
-#define portSTACK_GROWTH ( -1 )
-#define portSWITCH_INT_NUMBER 0x80
-#define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 2
-#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
+#define portNOP() __asm{ nop }
+#define portSTACK_GROWTH ( -1 )
+#define portSWITCH_INT_NUMBER 0x80
+#define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
/*-----------------------------------------------------------*/
/* Compiler specifics. */
-#define portINPUT_BYTE( xAddr ) inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr ) inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr ) inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr ) inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void * pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
#endif /* PORTMACRO_H */
+
diff --git a/portable/BCC/16BitDOS/PC/port.c b/portable/BCC/16BitDOS/PC/port.c
index da84dd8..70ae70c 100644
--- a/portable/BCC/16BitDOS/PC/port.c
+++ b/portable/BCC/16BitDOS/PC/port.c
@@ -26,16 +26,16 @@
*/
/*
- * Changes from V2.6.1
- *
- + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
- + macro to be consistent with the later ports.
- +
- + Changes from V4.0.1
- +
- + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
- + its proper value when the scheduler exits.
- */
+Changes from V2.6.1
+
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+ macro to be consistent with the later ports.
+
+Changes from V4.0.1
+
+ + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+ its proper value when the scheduler exits.
+*/
#include <stdlib.h>
#include <dos.h>
@@ -46,13 +46,13 @@
#include "portasm.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the industrial
-* PC port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the industrial
+ * PC port.
+ *----------------------------------------------------------*/
/*lint -e950 Non ANSI reserved words okay in this file only. */
-#define portTIMER_INT_NUMBER 0x08
+#define portTIMER_INT_NUMBER 0x08
/* Setup hardware for required tick interrupt rate. */
static void prvSetTickFrequency( uint32_t ulTickRateHz );
@@ -61,29 +61,27 @@
static void prvExitFunction( void );
/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
- * directly. We chain to the DOS tick as close as possible to the standard DOS
- * tick rate. */
+directly. We chain to the DOS tick as close as possible to the standard DOS
+tick rate. */
static void prvPortResetPIC( void );
/* The ISR used depends on whether the preemptive or cooperative
- * scheduler is being used. */
-#if ( configUSE_PREEMPTION == 1 )
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
- static void __interrupt __far prvPreemptiveTick( void );
+scheduler is being used. */
+#if( configUSE_PREEMPTION == 1 )
+ /* Tick service routine used by the scheduler when preemptive scheduling is
+ being used. */
+ static void __interrupt __far prvPreemptiveTick( void );
#else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
- static void __interrupt __far prvNonPreemptiveTick( void );
+ /* Tick service routine used by the scheduler when cooperative scheduling is
+ being used. */
+ static void __interrupt __far prvNonPreemptiveTick( void );
#endif
/* Trap routine used by taskYIELD() to manually cause a context switch. */
static void __interrupt __far prvYieldProcessor( void );
/* Set the tick frequency back so the floppy drive works correctly when the
- * scheduler exits. */
+scheduler exits. */
static void prvSetTickFrequencyDefault( void );
/*lint -e956 File scopes necessary here. */
@@ -92,13 +90,13 @@
static int16_t sDOSTickCounter;
/* Set true when the vectors are set so the scheduler will service the tick. */
-static BaseType_t xSchedulerRunning = pdFALSE;
+static BaseType_t xSchedulerRunning = pdFALSE;
/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISR )();
+static void ( __interrupt __far *pxOldSwitchISR )();
/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISRPlus1 )();
+static void ( __interrupt __far *pxOldSwitchISRPlus1 )();
/* Used to restore the original DOS context when the scheduler is ended. */
static jmp_buf xJumpBuf;
@@ -108,187 +106,183 @@
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- pxISR pxOriginalTickISR;
+pxISR pxOriginalTickISR;
+
+ /* This is called with interrupts already disabled. */
- /* This is called with interrupts already disabled. */
+ /* Remember what was on the interrupts we are going to use
+ so we can put them back later if required. */
+ pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+ pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
+ pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
- /* Remember what was on the interrupts we are going to use
- * so we can put them back later if required. */
- pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
- pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
- pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+ prvSetTickFrequency( configTICK_RATE_HZ );
- prvSetTickFrequency( configTICK_RATE_HZ );
+ /* Put our manual switch (yield) function on a known
+ vector. */
+ _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
- /* Put our manual switch (yield) function on a known
- * vector. */
- _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+ /* Put the old tick on a different interrupt number so we can
+ call it when we want. */
+ _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
- /* Put the old tick on a different interrupt number so we can
- * call it when we want. */
- _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
-
- /* The ISR used depends on whether the preemptive or cooperative
- * scheduler is being used. */
- #if ( configUSE_PREEMPTION == 1 )
- {
- /* Put our tick switch function on the timer interrupt. */
- _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
- }
- #else
- {
- /* We want the timer interrupt to just increment the tick count. */
- _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
- }
+ /* The ISR used depends on whether the preemptive or cooperative
+ scheduler is being used. */
+ #if( configUSE_PREEMPTION == 1 )
+ {
+ /* Put our tick switch function on the timer interrupt. */
+ _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+ }
+ #else
+ {
+ /* We want the timer interrupt to just increment the tick count. */
+ _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+ }
#endif
- /* Setup a counter that is used to call the DOS interrupt as close
- * to it's original frequency as can be achieved given our chosen tick
- * frequency. */
- sDOSTickCounter = portTICKS_PER_DOS_TICK;
+ /* Setup a counter that is used to call the DOS interrupt as close
+ to it's original frequency as can be achieved given our chosen tick
+ frequency. */
+ sDOSTickCounter = portTICKS_PER_DOS_TICK;
- /* Clean up function if we want to return to DOS. */
- if( setjmp( xJumpBuf ) != 0 )
- {
- prvExitFunction();
- xSchedulerRunning = pdFALSE;
- }
- else
- {
- xSchedulerRunning = pdTRUE;
+ /* Clean up function if we want to return to DOS. */
+ if( setjmp( xJumpBuf ) != 0 )
+ {
+ prvExitFunction();
+ xSchedulerRunning = pdFALSE;
+ }
+ else
+ {
+ xSchedulerRunning = pdTRUE;
- /* Kick off the scheduler by setting up the context of the first task. */
- portFIRST_CONTEXT();
- }
+ /* Kick off the scheduler by setting up the context of the first task. */
+ portFIRST_CONTEXT();
+ }
- return xSchedulerRunning;
+ return xSchedulerRunning;
}
/*-----------------------------------------------------------*/
/* The ISR used depends on whether the preemptive or cooperative
- * scheduler is being used. */
-#if ( configUSE_PREEMPTION == 1 )
- static void __interrupt __far prvPreemptiveTick( void )
- {
- /* Get the scheduler to update the task states following the tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Switch in the context of the next task to be run. */
- portSWITCH_CONTEXT();
- }
+scheduler is being used. */
+#if( configUSE_PREEMPTION == 1 )
+ static void __interrupt __far prvPreemptiveTick( void )
+ {
+ /* Get the scheduler to update the task states following the tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Switch in the context of the next task to be run. */
+ portSWITCH_CONTEXT();
+ }
- /* Reset the PIC ready for the next time. */
- prvPortResetPIC();
- }
-#else /* if ( configUSE_PREEMPTION == 1 ) */
- static void __interrupt __far prvNonPreemptiveTick( void )
- {
- /* Same as preemptive tick, but the cooperative scheduler is being used
- * so we don't have to switch in the context of the next task. */
- xTaskIncrementTick();
- prvPortResetPIC();
- }
-#endif /* if ( configUSE_PREEMPTION == 1 ) */
+ /* Reset the PIC ready for the next time. */
+ prvPortResetPIC();
+ }
+#else
+ static void __interrupt __far prvNonPreemptiveTick( void )
+ {
+ /* Same as preemptive tick, but the cooperative scheduler is being used
+ so we don't have to switch in the context of the next task. */
+ xTaskIncrementTick();
+ prvPortResetPIC();
+ }
+#endif
/*-----------------------------------------------------------*/
static void __interrupt __far prvYieldProcessor( void )
{
- /* Switch in the context of the next task to be run. */
- portSWITCH_CONTEXT();
+ /* Switch in the context of the next task to be run. */
+ portSWITCH_CONTEXT();
}
/*-----------------------------------------------------------*/
static void prvPortResetPIC( void )
{
- /* We are going to call the DOS tick interrupt at as close a
- * frequency to the normal DOS tick as possible. */
+ /* We are going to call the DOS tick interrupt at as close a
+ frequency to the normal DOS tick as possible. */
- /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
- --sDOSTickCounter;
-
- if( sDOSTickCounter <= 0 )
- {
- sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
- __asm {
- int portSWITCH_INT_NUMBER + 1
- };
- }
- else
- {
- /* Reset the PIC as the DOS tick is not being called to
- * do it. */
- __asm
- {
- mov al, 20H
- out 20H, al
- };
- }
+ /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
+ --sDOSTickCounter;
+ if( sDOSTickCounter <= 0 )
+ {
+ sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
+ __asm{ int portSWITCH_INT_NUMBER + 1 };
+ }
+ else
+ {
+ /* Reset the PIC as the DOS tick is not being called to
+ do it. */
+ __asm
+ {
+ mov al, 20H
+ out 20H, al
+ };
+ }
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Jump back to the processor state prior to starting the
- * scheduler. This means we are not going to be using a
- * task stack frame so the task can be deleted. */
- longjmp( xJumpBuf, 1 );
+ /* Jump back to the processor state prior to starting the
+ scheduler. This means we are not going to be using a
+ task stack frame so the task can be deleted. */
+ longjmp( xJumpBuf, 1 );
}
/*-----------------------------------------------------------*/
static void prvExitFunction( void )
{
- void( __interrupt __far * pxOriginalTickISR )();
+void ( __interrupt __far *pxOriginalTickISR )();
- /* Interrupts should be disabled here anyway - but no
- * harm in making sure. */
- portDISABLE_INTERRUPTS();
+ /* Interrupts should be disabled here anyway - but no
+ harm in making sure. */
+ portDISABLE_INTERRUPTS();
+ if( xSchedulerRunning == pdTRUE )
+ {
+ /* Set the DOS tick back onto the timer ticker. */
+ pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+ _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );
+ prvSetTickFrequencyDefault();
- if( xSchedulerRunning == pdTRUE )
- {
- /* Set the DOS tick back onto the timer ticker. */
- pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
- _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );
- prvSetTickFrequencyDefault();
-
- /* Put back the switch interrupt routines that was in place
- * before the scheduler started. */
- _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
- _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
- }
-
- /* The tick timer is back how DOS wants it. We can re-enable
- * interrupts without the scheduler being called. */
- portENABLE_INTERRUPTS();
+ /* Put back the switch interrupt routines that was in place
+ before the scheduler started. */
+ _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+ _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
+ }
+ /* The tick timer is back how DOS wants it. We can re-enable
+ interrupts without the scheduler being called. */
+ portENABLE_INTERRUPTS();
}
/*-----------------------------------------------------------*/
static void prvSetTickFrequency( uint32_t ulTickRateHz )
{
- const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
- const uint16_t usPIT0 = ( uint16_t ) 0x40;
- const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL;
- const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
- uint32_t ulOutput;
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+uint32_t ulOutput;
- /* Setup the 8245 to tick at the wanted frequency. */
- portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
- ulOutput = ulPIT_CONST / ulTickRateHz;
- portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
- ulOutput >>= 8;
- portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
+ /* Setup the 8245 to tick at the wanted frequency. */
+ portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+ ulOutput = ulPIT_CONST / ulTickRateHz;
+ portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
+ ulOutput >>= 8;
+ portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
}
/*-----------------------------------------------------------*/
static void prvSetTickFrequencyDefault( void )
{
- const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
- const uint16_t usPIT0 = ( uint16_t ) 0x40;
- const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
- portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
- portOUTPUT_BYTE( usPIT0, 0 );
- portOUTPUT_BYTE( usPIT0, 0 );
+ portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+ portOUTPUT_BYTE( usPIT0,0 );
+ portOUTPUT_BYTE( usPIT0,0 );
}
/*lint +e950 */
+
diff --git a/portable/BCC/16BitDOS/PC/prtmacro.h b/portable/BCC/16BitDOS/PC/prtmacro.h
index f94ec23..cfc74f3 100644
--- a/portable/BCC/16BitDOS/PC/prtmacro.h
+++ b/portable/BCC/16BitDOS/PC/prtmacro.h
@@ -39,59 +39,59 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT long
-#define portDOUBLE long
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint16_t
-#define portBASE_TYPE portSHORT
+#define portCHAR char
+#define portFLOAT long
+#define portDOUBLE long
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE portSHORT
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Critical section management. */
-#define portENTER_CRITICAL() \
- __asm{ pushf } \
- __asm{ cli } \
+#define portENTER_CRITICAL() __asm{ pushf } \
+ __asm{ cli } \
-#define portEXIT_CRITICAL() __asm{ popf }
+#define portEXIT_CRITICAL() __asm{ popf }
-#define portDISABLE_INTERRUPTS() __asm{ cli }
+#define portDISABLE_INTERRUPTS() __asm{ cli }
-#define portENABLE_INTERRUPTS() __asm{ sti }
+#define portENABLE_INTERRUPTS() __asm{ sti }
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portNOP() __asm{ nop }
-#define portSTACK_GROWTH ( -1 )
-#define portSWITCH_INT_NUMBER 0x80
-#define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
-#define portDOS_TICK_RATE ( 18.20648 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portTICKS_PER_DOS_TICK ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
-#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
-#define portBYTE_ALIGNMENT ( 2 )
+#define portNOP() __asm{ nop }
+#define portSTACK_GROWTH ( -1 )
+#define portSWITCH_INT_NUMBER 0x80
+#define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
+#define portDOS_TICK_RATE ( 18.20648 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICKS_PER_DOS_TICK ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
+#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
+#define portBYTE_ALIGNMENT ( 2 )
/*-----------------------------------------------------------*/
/* Compiler specifics. */
-#define portINPUT_BYTE( xAddr ) inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
+#define portINPUT_BYTE( xAddr ) inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void * pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
#endif /* PORTMACRO_H */
+
diff --git a/portable/BCC/16BitDOS/common/portasm.h b/portable/BCC/16BitDOS/common/portasm.h
index 45d1302..2b199c6 100644
--- a/portable/BCC/16BitDOS/common/portasm.h
+++ b/portable/BCC/16BitDOS/common/portasm.h
@@ -47,40 +47,41 @@
void portFIRST_CONTEXT( void );
/* There are slightly different versions depending on whether you are building
- * to include debugger information. If debugger information is used then there
- * are a couple of extra bytes left of the ISR stack (presumably for use by the
- * debugger). The true stack pointer is then stored in the bp register. We add
- * 2 to the stack pointer to remove the extra bytes before we restore our context. */
+to include debugger information. If debugger information is used then there
+are a couple of extra bytes left of the ISR stack (presumably for use by the
+debugger). The true stack pointer is then stored in the bp register. We add
+2 to the stack pointer to remove the extra bytes before we restore our context. */
-#define portSWITCH_CONTEXT() \
- asm { mov ax, seg pxCurrentTCB } \
- asm { mov ds, ax } \
- asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \
- asm { mov es : 0x2[ bx ], ss } \
- asm { mov es:[ bx ], sp } \
- asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \
- asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \
- asm { mov ds, ax } \
- asm { les bx, dword ptr pxCurrentTCB } \
- asm { mov ss, es:[ bx + 2 ] } \
- asm { mov sp, es:[ bx ] }
+#define portSWITCH_CONTEXT() \
+ asm { mov ax, seg pxCurrentTCB } \
+ asm { mov ds, ax } \
+ asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \
+ asm { mov es:0x2[ bx ], ss } \
+ asm { mov es:[ bx ], sp } \
+ asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \
+ asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \
+ asm { mov ds, ax } \
+ asm { les bx, dword ptr pxCurrentTCB } \
+ asm { mov ss, es:[ bx + 2 ] } \
+ asm { mov sp, es:[ bx ] }
-#define portFIRST_CONTEXT() \
- __asm { mov ax, seg pxCurrentTCB } \
- __asm { mov ds, ax } \
- __asm { les bx, dword ptr pxCurrentTCB } \
- __asm { mov ss, es:[ bx + 2 ] } \
- __asm { mov sp, es:[ bx ] } \
- __asm { pop bp } \
- __asm { pop di } \
- __asm { pop si } \
- __asm { pop ds } \
- __asm { pop es } \
- __asm { pop dx } \
- __asm { pop cx } \
- __asm { pop bx } \
- __asm { pop ax } \
- __asm { iret }
+#define portFIRST_CONTEXT() \
+ __asm { mov ax, seg pxCurrentTCB } \
+ __asm { mov ds, ax } \
+ __asm { les bx, dword ptr pxCurrentTCB } \
+ __asm { mov ss, es:[ bx + 2 ] } \
+ __asm { mov sp, es:[ bx ] } \
+ __asm { pop bp } \
+ __asm { pop di } \
+ __asm { pop si } \
+ __asm { pop ds } \
+ __asm { pop es } \
+ __asm { pop dx } \
+ __asm { pop cx } \
+ __asm { pop bx } \
+ __asm { pop ax } \
+ __asm { iret }
-#endif /* ifndef PORT_ASM_H */
+#endif
+
diff --git a/portable/BCC/16BitDOS/common/portcomn.c b/portable/BCC/16BitDOS/common/portcomn.c
index 593cf38..c230b14 100644
--- a/portable/BCC/16BitDOS/common/portcomn.c
+++ b/portable/BCC/16BitDOS/common/portcomn.c
@@ -26,16 +26,16 @@
*/
/*
- * Changes from V1.00:
- *
- + pxPortInitialiseStack() now initialises the stack of new tasks to the
- + same format used by the compiler. This allows the compiler generated
- + interrupt mechanism to be used for context switches.
- +
- + Changes from V2.6.1
- +
- + Move usPortCheckFreeStackSpace() to tasks.c.
- */
+Changes from V1.00:
+
+ + pxPortInitialiseStack() now initialises the stack of new tasks to the
+ same format used by the compiler. This allows the compiler generated
+ interrupt mechanism to be used for context switches.
+
+Changes from V2.6.1
+
+ + Move usPortCheckFreeStackSpace() to tasks.c.
+*/
#include <dos.h>
@@ -45,79 +45,76 @@
/*-----------------------------------------------------------*/
/* See header file for description. */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t DS_Reg = 0;
+StackType_t DS_Reg = 0;
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging. */
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
- *pxTopOfStack = 0x1111;
- pxTopOfStack--;
- *pxTopOfStack = 0x2222;
- pxTopOfStack--;
- *pxTopOfStack = 0x3333;
- pxTopOfStack--;
- *pxTopOfStack = 0x4444;
- pxTopOfStack--;
- *pxTopOfStack = 0x5555;
- pxTopOfStack--;
+ *pxTopOfStack = 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x3333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x4444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x5555;
+ pxTopOfStack--;
- /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
- /* We are going to start the scheduler using a return from interrupt
- * instruction to load the program counter, so first there would be the
- * function call with parameters preamble. */
+ /* We are going to start the scheduler using a return from interrupt
+ instruction to load the program counter, so first there would be the
+ function call with parameters preamble. */
+
+ *pxTopOfStack = FP_SEG( pvParameters );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pvParameters );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_SEG( pxCode );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pxCode );
+ pxTopOfStack--;
- *pxTopOfStack = FP_SEG( pvParameters );
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pvParameters );
- pxTopOfStack--;
- *pxTopOfStack = FP_SEG( pxCode );
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pxCode );
- pxTopOfStack--;
+ /* Next the status register and interrupt return address. */
+ *pxTopOfStack = portINITIAL_SW;
+ pxTopOfStack--;
+ *pxTopOfStack = FP_SEG( pxCode );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pxCode );
+ pxTopOfStack--;
- /* Next the status register and interrupt return address. */
- *pxTopOfStack = portINITIAL_SW;
- pxTopOfStack--;
- *pxTopOfStack = FP_SEG( pxCode );
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pxCode );
- pxTopOfStack--;
+ /* The remaining registers would be pushed on the stack by our context
+ switch function. These are loaded with values simply to make debugging
+ easier. */
+ *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */
+ pxTopOfStack--;
- /* The remaining registers would be pushed on the stack by our context
- * switch function. These are loaded with values simply to make debugging
- * easier. */
- *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */
- pxTopOfStack--;
+ /* We need the true data segment. */
+ __asm{ MOV DS_Reg, DS };
- /* We need the true data segment. */
- __asm {
- MOV DS_Reg, DS
- };
+ *pxTopOfStack = DS_Reg; /* DS */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */
- *pxTopOfStack = DS_Reg; /* DS */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */
+ /*lint +e950 +e611 +e923 */
- /*lint +e950 +e611 +e923 */
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
+
diff --git a/portable/CCS/ARM_Cortex-R4/port.c b/portable/CCS/ARM_Cortex-R4/port.c
index 1f3f31c..972150b 100644
--- a/portable/CCS/ARM_Cortex-R4/port.c
+++ b/portable/CCS/ARM_Cortex-R4/port.c
@@ -37,28 +37,28 @@
/*-----------------------------------------------------------*/
/* Registers required to configure the RTI. */
-#define portRTI_GCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC00 ) )
-#define portRTI_TBCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC04 ) )
-#define portRTI_COMPCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC0C ) )
-#define portRTI_CNT0_FRC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC10 ) )
-#define portRTI_CNT0_UC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC14 ) )
-#define portRTI_CNT0_CPUC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC18 ) )
-#define portRTI_CNT0_COMP0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC50 ) )
-#define portRTI_CNT0_UDCP0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC54 ) )
-#define portRTI_SETINTENA_REG ( *( ( volatile uint32_t * ) 0xFFFFFC80 ) )
-#define portRTI_CLEARINTENA_REG ( *( ( volatile uint32_t * ) 0xFFFFFC84 ) )
-#define portRTI_INTFLAG_REG ( *( ( volatile uint32_t * ) 0xFFFFFC88 ) )
+#define portRTI_GCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) )
+#define portRTI_TBCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) )
+#define portRTI_COMPCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) )
+#define portRTI_CNT0_FRC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) )
+#define portRTI_CNT0_UC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) )
+#define portRTI_CNT0_CPUC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) )
+#define portRTI_CNT0_COMP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) )
+#define portRTI_CNT0_UDCP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) )
+#define portRTI_SETINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) )
+#define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) )
+#define portRTI_INTFLAG_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) )
/* Constants required to set up the initial stack of each task. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1F )
-#define portINITIAL_FPSCR ( ( StackType_t ) 0x00 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 0x04 )
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1F )
+#define portINITIAL_FPSCR ( ( StackType_t ) 0x00 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 0x04 )
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
/* The number of words on the stack frame between the saved Top Of Stack and
- * R0 (in which the parameters are passed. */
-#define portSPACE_BETWEEN_TOS_AND_PARAMETERS ( 12 )
+R0 (in which the parameters are passed. */
+#define portSPACE_BETWEEN_TOS_AND_PARAMETERS ( 12 )
/*-----------------------------------------------------------*/
@@ -68,7 +68,7 @@
/*-----------------------------------------------------------*/
/* Saved as part of the task context. Set to pdFALSE if the task does not
- * require an FPU context. */
+require an FPU context. */
uint32_t ulTaskHasFPUContext = 0;
/*-----------------------------------------------------------*/
@@ -77,183 +77,181 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
- #if __TI_VFP_SUPPORT__
- {
- /* Ensure the stack is correctly aligned on exit. */
- pxTopOfStack--;
- }
- #endif
+ #if __TI_VFP_SUPPORT__
+ {
+ /* Ensure the stack is correctly aligned on exit. */
+ pxTopOfStack--;
+ }
+ #endif
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First on the stack is the return address - which is the start of the as
- * the task has not executed yet. The offset is added to make the return
- * address appear as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which is the start of the as
+ the task has not executed yet. The offset is added to make the return
+ address appear as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
- #ifdef portPRELOAD_TASK_REGISTERS
- {
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- }
- #else /* ifdef portPRELOAD_TASK_REGISTERS */
- {
- pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
- }
- #endif /* ifdef portPRELOAD_TASK_REGISTERS */
+ #ifdef portPRELOAD_TASK_REGISTERS
+ {
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
+ }
+ #endif
- /* Function parameters are passed in R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* Function parameters are passed in R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* Set the status register for system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );
+ /* Set the status register for system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );
- if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
- {
- /* The task will start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+ {
+ /* The task will start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
- #ifdef __TI_VFP_SUPPORT__
- {
- pxTopOfStack--;
+ #ifdef __TI_VFP_SUPPORT__
+ {
+ pxTopOfStack--;
- /* The last thing on the stack is the tasks ulUsingFPU value, which by
- * default is set to indicate that the stack frame does not include FPU
- * registers. */
- *pxTopOfStack = pdFALSE;
- }
- #endif
+ /* The last thing on the stack is the tasks ulUsingFPU value, which by
+ default is set to indicate that the stack frame does not include FPU
+ registers. */
+ *pxTopOfStack = pdFALSE;
+ }
+ #endif
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
-static void prvSetupTimerInterrupt( void )
+static void prvSetupTimerInterrupt(void)
{
- /* Disable timer 0. */
- portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
+ /* Disable timer 0. */
+ portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
- /* Use the internal counter. */
- portRTI_TBCTRL_REG = 0x00000000U;
+ /* Use the internal counter. */
+ portRTI_TBCTRL_REG = 0x00000000U;
- /* COMPSEL0 will use the RTIFRC0 counter. */
- portRTI_COMPCTRL_REG = 0x00000000U;
+ /* COMPSEL0 will use the RTIFRC0 counter. */
+ portRTI_COMPCTRL_REG = 0x00000000U;
- /* Initialise the counter and the prescale counter registers. */
- portRTI_CNT0_UC0_REG = 0x00000000U;
- portRTI_CNT0_FRC0_REG = 0x00000000U;
+ /* Initialise the counter and the prescale counter registers. */
+ portRTI_CNT0_UC0_REG = 0x00000000U;
+ portRTI_CNT0_FRC0_REG = 0x00000000U;
- /* Set Prescalar for RTI clock. */
- portRTI_CNT0_CPUC0_REG = 0x00000001U;
- portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
- portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
+ /* Set Prescalar for RTI clock. */
+ portRTI_CNT0_CPUC0_REG = 0x00000001U;
+ portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
+ portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
- /* Clear interrupts. */
- portRTI_INTFLAG_REG = 0x0007000FU;
- portRTI_CLEARINTENA_REG = 0x00070F0FU;
+ /* Clear interrupts. */
+ portRTI_INTFLAG_REG = 0x0007000FU;
+ portRTI_CLEARINTENA_REG = 0x00070F0FU;
- /* Enable the compare 0 interrupt. */
- portRTI_SETINTENA_REG = 0x00000001U;
- portRTI_GCTRL_REG |= 0x00000001U;
+ /* Enable the compare 0 interrupt. */
+ portRTI_SETINTENA_REG = 0x00000001U;
+ portRTI_GCTRL_REG |= 0x00000001U;
}
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-BaseType_t xPortStartScheduler( void )
+BaseType_t xPortStartScheduler(void)
{
- /* Start the timer that generates the tick ISR. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. */
+ prvSetupTimerInterrupt();
- /* Reset the critical section nesting count read to execute the first task. */
- ulCriticalNesting = 0;
+ /* Reset the critical section nesting count read to execute the first task. */
+ ulCriticalNesting = 0;
- /* Start the first task. This is done from portASM.asm as ARM mode must be
- * used. */
- vPortStartFirstTask();
+ /* Start the first task. This is done from portASM.asm as ARM mode must be
+ used. */
+ vPortStartFirstTask();
- /* Should not get here! */
- return pdFAIL;
+ /* Should not get here! */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-void vPortEndScheduler( void )
+void vPortEndScheduler(void)
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 0
-/* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick. */
- __interrupt void vPortNonPreemptiveTick( void )
- {
- /* clear clock interrupt flag */
- portRTI_INTFLAG_REG = 0x00000001;
+ /* The cooperative scheduler requires a normal IRQ service routine to
+ * simply increment the system tick. */
+ __interrupt void vPortNonPreemptiveTick( void )
+ {
+ /* clear clock interrupt flag */
+ portRTI_INTFLAG_REG = 0x00000001;
- /* Increment the tick count - this may make a delaying task ready
- * to run - but a context switch is not performed. */
- xTaskIncrementTick();
- }
+ /* Increment the tick count - this may make a delaying task ready
+ to run - but a context switch is not performed. */
+ xTaskIncrementTick();
+ }
-#else /* if configUSE_PREEMPTION == 0 */
+ #else
-/*
- **************************************************************************
- * The preemptive scheduler ISR is written in assembler and can be found
- * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
- * is set to 1 in portmacro.h
- **************************************************************************
- */
- void vPortPreemptiveTick( void );
+ /*
+ **************************************************************************
+ * The preemptive scheduler ISR is written in assembler and can be found
+ * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
+ * is set to 1 in portmacro.h
+ **************************************************************************
+ */
+ void vPortPreemptiveTick( void );
-#endif /* if configUSE_PREEMPTION == 0 */
+#endif
/*-----------------------------------------------------------*/
@@ -262,13 +260,13 @@
*/
void vPortEnterCritical( void )
{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- portDISABLE_INTERRUPTS();
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ portDISABLE_INTERRUPTS();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
@@ -278,36 +276,37 @@
*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > 0 )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > 0 )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == 0 )
- {
- /* Enable interrupts as per portENABLE_INTERRUPTS(). */
- portENABLE_INTERRUPTS();
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == 0 )
+ {
+ /* Enable interrupts as per portENABLE_INTERRUPTS(). */
+ portENABLE_INTERRUPTS();
+ }
+ }
}
/*-----------------------------------------------------------*/
#if __TI_VFP_SUPPORT__
- void vPortTaskUsesFPU( void )
- {
- extern void vPortInitialiseFPSCR( void );
+ void vPortTaskUsesFPU( void )
+ {
+ extern void vPortInitialiseFPSCR( void );
- /* A task is registering the fact that it needs an FPU context. Set the
- * FPU flag (saved as part of the task context. */
- ulTaskHasFPUContext = pdTRUE;
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (saved as part of the task context. */
+ ulTaskHasFPUContext = pdTRUE;
- /* Initialise the floating point status register. */
- vPortInitialiseFPSCR();
- }
+ /* Initialise the floating point status register. */
+ vPortInitialiseFPSCR();
+ }
#endif /* __TI_VFP_SUPPORT__ */
/*-----------------------------------------------------------*/
+
diff --git a/portable/CCS/ARM_Cortex-R4/portmacro.h b/portable/CCS/ARM_Cortex-R4/portmacro.h
index 1536b0f..d8a9a4c 100644
--- a/portable/CCS/ARM_Cortex-R4/portmacro.h
+++ b/portable/CCS/ARM_Cortex-R4/portmacro.h
@@ -39,78 +39,79 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xFFFF
+#if (configUSE_16_BIT_TICKS == 1)
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY (TickType_t) 0xFFFF
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xFFFFFFFFF
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY (TickType_t) 0xFFFFFFFFF
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
#endif
/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH (-1)
+#define portTICK_PERIOD_MS ((TickType_t) 1000 / configTICK_RATE_HZ)
+#define portBYTE_ALIGNMENT 8
/* Critical section handling. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portENTER_CRITICAL() vPortEnterCritical()
-#define portEXIT_CRITICAL() vPortExitCritical()
-#define portDISABLE_INTERRUPTS() asm ( " CPSID I" )
-#define portENABLE_INTERRUPTS() asm ( " CPSIE I" )
+extern void vPortEnterCritical(void);
+extern void vPortExitCritical(void);
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() asm( " CPSID I" )
+#define portENABLE_INTERRUPTS() asm( " CPSIE I" )
/* Scheduler utilities. */
#pragma SWI_ALIAS( vPortYield, 0 )
extern void vPortYield( void );
-#define portYIELD() vPortYield()
-#define portSYS_SSIR1_REG ( *( ( volatile uint32_t * ) 0xFFFFFFB0 ) )
-#define portSYS_SSIR1_SSKEY ( 0x7500UL )
-#define portYIELD_WITHIN_API() { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY; asm ( " DSB " ); asm ( " ISB " ); }
-#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY; ( void ) portSYS_SSIR1_REG; }
+#define portYIELD() vPortYield()
+#define portSYS_SSIR1_REG ( * ( ( volatile uint32_t * ) 0xFFFFFFB0 ) )
+#define portSYS_SSIR1_SSKEY ( 0x7500UL )
+#define portYIELD_WITHIN_API() { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY; asm( " DSB " ); asm( " ISB " ); }
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ){ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY; ( void ) portSYS_SSIR1_REG; }
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
/* Architecture specific optimisations. */
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)
+#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
#endif /* __PORTMACRO_H__ */
+
diff --git a/portable/CCS/MSP430X/data_model.h b/portable/CCS/MSP430X/data_model.h
index 6a0787c..fcfcfab 100644
--- a/portable/CCS/MSP430X/data_model.h
+++ b/portable/CCS/MSP430X/data_model.h
@@ -1,48 +1,53 @@
-; /*
- * ; * FreeRTOS Kernel V10.3.1
- * ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * ; *
- * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * ; * this software and associated documentation files (the "Software"), to deal in
- * ; * the Software without restriction, including without limitation the rights to
- * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * ; * the Software, and to permit persons to whom the Software is furnished to do so,
- * ; * subject to the following conditions:
- * ; *
- * ; * The above copyright notice and this permission notice shall be included in all
- * ; * copies or substantial portions of the Software.
- * ; *
- * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * ; *
- * ; * http://www.FreeRTOS.org
- * ; * http://aws.amazon.com/freertos
- * ; *
- * ; * 1 tab == 4 spaces!
- * ; */
+;/*
+; * FreeRTOS Kernel V10.3.1
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
-.if $DEFINED( __LARGE_DATA_MODEL__ )
- .define "pushm.a", pushm_x
- .define "popm.a", popm_x
- .define "push.a", push_x
- .define "pop.a", pop_x
- .define "mov.a", mov_x
- .else
- .define "pushm.w", pushm_x
- .define "popm.w", popm_x
- .define "push.w", push_x
- .define "pop.w", pop_x
- .define "mov.w", mov_x
- .endif
+ .if $DEFINED( __LARGE_DATA_MODEL__ )
+ .define "pushm.a", pushm_x
+ .define "popm.a", popm_x
+ .define "push.a", push_x
+ .define "pop.a", pop_x
+ .define "mov.a", mov_x
+ .else
+ .define "pushm.w", pushm_x
+ .define "popm.w", popm_x
+ .define "push.w", push_x
+ .define "pop.w", pop_x
+ .define "mov.w", mov_x
+ .endif
- .if $DEFINED( __LARGE_CODE_MODEL__ )
- .define "calla", call_x
- .define "reta", ret_x
- .else
- .define "call", call_x
- .define "ret", ret_x
- .endif
+ .if $DEFINED( __LARGE_CODE_MODEL__ )
+ .define "calla", call_x
+ .define "reta", ret_x
+ .else
+ .define "call", call_x
+ .define "ret", ret_x
+ .endif
+
+
+
+
+
diff --git a/portable/CCS/MSP430X/port.c b/portable/CCS/MSP430X/port.c
index 6e0d857..c6abced 100644
--- a/portable/CCS/MSP430X/port.c
+++ b/portable/CCS/MSP430X/port.c
@@ -30,28 +30,28 @@
#include "task.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the MSP430X port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the MSP430X port.
+ *----------------------------------------------------------*/
/* Constants required for hardware setup. The tick ISR runs off the ACLK,
- * not the MCLK. */
-#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/* Each task maintains a count of the critical section nesting depth. Each
- * time a critical section is entered the count is incremented. Each time a
- * critical section is exited the count is decremented - with interrupts only
- * being re-enabled if the count is zero.
- *
- * usCriticalNesting will get set to zero when the scheduler starts, but must
- * not be initialised to zero as this will cause problems during the startup
- * sequence. */
+time a critical section is entered the count is incremented. Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@@ -69,96 +69,94 @@
*
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint16_t * pusTopOfStack;
- uint32_t * pulTopOfStack, ulTemp;
+uint16_t *pusTopOfStack;
+uint32_t *pulTopOfStack, ulTemp;
- /*
- * Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging and can be included if required.
- *
- * pxTopOfStack = ( StackType_t ) 0x1111;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x2222;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x3333;
- * pxTopOfStack--;
- */
+ /*
+ Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging and can be included if required.
- /* Data types are need either 16 bits or 32 bits depending on the data
- * and code model used. */
- if( sizeof( pxCode ) == sizeof( uint16_t ) )
- {
- pusTopOfStack = ( uint16_t * ) pxTopOfStack;
- ulTemp = ( uint32_t ) pxCode;
- *pusTopOfStack = ( uint16_t ) ulTemp;
- }
- else
- {
- /* Make room for a 20 bit value stored as a 32 bit value. */
- pusTopOfStack = ( uint16_t * ) pxTopOfStack;
- pusTopOfStack--;
- pulTopOfStack = ( uint32_t * ) pusTopOfStack;
- *pulTopOfStack = ( uint32_t ) pxCode;
- }
+ *pxTopOfStack = ( StackType_t ) 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x3333;
+ pxTopOfStack--;
+ */
- pusTopOfStack--;
- *pusTopOfStack = portFLAGS_INT_ENABLED;
- pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
+ /* Data types are need either 16 bits or 32 bits depending on the data
+ and code model used. */
+ if( sizeof( pxCode ) == sizeof( uint16_t ) )
+ {
+ pusTopOfStack = ( uint16_t * ) pxTopOfStack;
+ ulTemp = ( uint32_t ) pxCode;
+ *pusTopOfStack = ( uint16_t ) ulTemp;
+ }
+ else
+ {
+ /* Make room for a 20 bit value stored as a 32 bit value. */
+ pusTopOfStack = ( uint16_t * ) pxTopOfStack;
+ pusTopOfStack--;
+ pulTopOfStack = ( uint32_t * ) pusTopOfStack;
+ *pulTopOfStack = ( uint32_t ) pxCode;
+ }
- /* From here on the size of stacked items depends on the memory model. */
- pxTopOfStack = ( StackType_t * ) pusTopOfStack;
+ pusTopOfStack--;
+ *pusTopOfStack = portFLAGS_INT_ENABLED;
+ pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
+
+ /* From here on the size of stacked items depends on the memory model. */
+ pxTopOfStack = ( StackType_t * ) pusTopOfStack;
- /* Next the general purpose registers. */
- #ifdef PRELOAD_REGISTER_VALUES
- *pxTopOfStack = ( StackType_t ) 0xffff;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xeeee;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xdddd;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xbbbb;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaa;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x9999;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x8888;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x5555;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x6666;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x5555;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x4444;
- pxTopOfStack--;
- #else /* ifdef PRELOAD_REGISTER_VALUES */
- pxTopOfStack -= 3;
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack -= 9;
- #endif /* ifdef PRELOAD_REGISTER_VALUES */
+ /* Next the general purpose registers. */
+ #ifdef PRELOAD_REGISTER_VALUES
+ *pxTopOfStack = ( StackType_t ) 0xffff;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xdddd;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x9999;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x8888;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x5555;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x6666;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x5555;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x4444;
+ pxTopOfStack--;
+ #else
+ pxTopOfStack -= 3;
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack -= 9;
+ #endif
- /* A variable is used to keep track of the critical section nesting.
- * This variable has to be stored as part of the task context and is
- * initially set to zero. */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+ /* A variable is used to keep track of the critical section nesting.
+ This variable has to be stored as part of the task context and is
+ initially set to zero. */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
- /* Return a pointer to the top of the stack we have generated so this can
- * be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* Return a pointer to the top of the stack we have generated so this can
+ be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the MSP430 port will get stopped. If required simply
- * disable the tick interrupt here. */
+ /* It is unlikely that the MSP430 port will get stopped. If required simply
+ disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@@ -167,21 +165,23 @@
*/
void vPortSetupTimerInterrupt( void )
{
- vApplicationSetupTimerInterrupt();
+ vApplicationSetupTimerInterrupt();
}
/*-----------------------------------------------------------*/
#pragma vector=configTICK_VECTOR
interrupt void vTickISREntry( void )
{
- extern void vPortTickISR( void );
+extern void vPortTickISR( void );
- __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
- #if configUSE_PREEMPTION == 1
- extern void vPortPreemptiveTickISR( void );
- vPortPreemptiveTickISR();
- #else
- extern void vPortCooperativeTickISR( void );
- vPortCooperativeTickISR();
- #endif
+ __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
+ #if configUSE_PREEMPTION == 1
+ extern void vPortPreemptiveTickISR( void );
+ vPortPreemptiveTickISR();
+ #else
+ extern void vPortCooperativeTickISR( void );
+ vPortCooperativeTickISR();
+ #endif
}
+
+
diff --git a/portable/CCS/MSP430X/portmacro.h b/portable/CCS/MSP430X/portmacro.h
index 78612e3..ca2f02f 100644
--- a/portable/CCS/MSP430X/portmacro.h
+++ b/portable/CCS/MSP430X/portmacro.h
@@ -42,72 +42,72 @@
#include "msp430.h"
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portBASE_TYPE portSHORT
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portBASE_TYPE portSHORT
/* The stack type changes depending on the data model. */
#ifdef __LARGE_DATA_MODEL__
- #define portSTACK_TYPE uint32_t
+ #define portSTACK_TYPE uint32_t
#else
- #define portSTACK_TYPE uint16_t
- #define portPOINTER_SIZE_TYPE uint16_t
+ #define portSTACK_TYPE uint16_t
+ #define portPOINTER_SIZE_TYPE uint16_t
#endif
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() _disable_interrupt(); _nop()
-#define portENABLE_INTERRUPTS() _enable_interrupt(); _nop()
+#define portDISABLE_INTERRUPTS() _disable_interrupt(); _nop()
+#define portENABLE_INTERRUPTS() _enable_interrupt(); _nop()
/*-----------------------------------------------------------*/
/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
-#define portENTER_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled usCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled usCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
-#define portEXIT_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
@@ -116,27 +116,28 @@
* Manual context switch called by portYIELD or taskYIELD.
*/
extern void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD() vPortYield()
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 2
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() __no_operation()
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __no_operation()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
+#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
void vApplicationSetupTimerInterrupt( void );
/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
- * run time stats information is to be displayed. */
+run time stats information is to be displayed. */
#define portLU_PRINTF_SPECIFIER_REQUIRED
#endif /* PORTMACRO_H */
+
diff --git a/portable/CodeWarrior/ColdFire_V1/port.c b/portable/CodeWarrior/ColdFire_V1/port.c
index 21ebf14..24cdf8b 100644
--- a/portable/CodeWarrior/ColdFire_V1/port.c
+++ b/portable/CodeWarrior/ColdFire_V1/port.c
@@ -30,158 +30,154 @@
#include "task.h"
-#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 )
+#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 )
/* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000 )
+#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000)
/* The clock prescale into the timer peripheral. */
-#define portPRESCALE_VALUE ( ( uint8_t ) 10 )
+#define portPRESCALE_VALUE ( ( uint8_t ) 10 )
/* The clock frequency into the RTC. */
-#define portRTC_CLOCK_HZ ( ( uint32_t ) 1000 )
+#define portRTC_CLOCK_HZ ( ( uint32_t ) 1000 )
asm void interrupt VectorNumber_VL1swi vPortYieldISR( void );
static void prvSetupTimerInterrupt( void );
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
- * will be set to 0 prior to the first task being started. */
+will be set to 0 prior to the first task being started. */
static uint32_t ulCriticalNesting = 0x9999UL;
/*-----------------------------------------------------------*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint32_t ulOriginalA5;
- __asm {
- MOVE.L A5, ulOriginalA5
- };
+uint32_t ulOriginalA5;
+
+ __asm{ MOVE.L A5, ulOriginalA5 };
- *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+ pxTopOfStack--;
- /* Exception stack frame starts with the return address. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
+ /* Exception stack frame starts with the return address. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
- *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
- pxTopOfStack--;
+ *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
- pxTopOfStack -= 14; /* A5 to D0. */
+ *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
+ pxTopOfStack -= 14; /* A5 to D0. */
- /* Parameter in A0. */
- *( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters;
+ /* Parameter in A0. */
+ *( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters;
- /* A5 must be maintained as it is resurved by the compiler. */
- *( pxTopOfStack + 13 ) = ulOriginalA5;
+ /* A5 must be maintained as it is resurved by the compiler. */
+ *( pxTopOfStack + 13 ) = ulOriginalA5;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
- ulCriticalNesting = 0UL;
+ ulCriticalNesting = 0UL;
- /* Configure a timer to generate the tick interrupt. */
- prvSetupTimerInterrupt();
+ /* Configure a timer to generate the tick interrupt. */
+ prvSetupTimerInterrupt();
- /* Start the first task executing. */
- vPortStartFirstTask();
+ /* Start the first task executing. */
+ vPortStartFirstTask();
- return pdFALSE;
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
-{
- /* Prescale by 1 - ie no prescale. */
- RTCSC |= 8;
-
- /* Compare match value. */
- RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ;
-
- /* Enable the RTC to generate interrupts - interrupts are already disabled
- * when this code executes. */
- RTCSC_RTIE = 1;
+{
+ /* Prescale by 1 - ie no prescale. */
+ RTCSC |= 8;
+
+ /* Compare match value. */
+ RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ;
+
+ /* Enable the RTC to generate interrupts - interrupts are already disabled
+ when this code executes. */
+ RTCSC_RTIE = 1;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented as there is nothing to return to. */
+ /* Not implemented as there is nothing to return to. */
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- if( ulCriticalNesting == 0UL )
- {
- /* Guard against context switches being pended simultaneously with a
- * critical section being entered. */
- do
- {
- portDISABLE_INTERRUPTS();
+ if( ulCriticalNesting == 0UL )
+ {
+ /* Guard against context switches being pended simultaneously with a
+ critical section being entered. */
+ do
+ {
+ portDISABLE_INTERRUPTS();
+ if( INTC_FRC == 0UL )
+ {
+ break;
+ }
- if( INTC_FRC == 0UL )
- {
- break;
- }
+ portENABLE_INTERRUPTS();
- portENABLE_INTERRUPTS();
- } while( 1 );
- }
-
- ulCriticalNesting++;
+ } while( 1 );
+ }
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- ulCriticalNesting--;
-
- if( ulCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
+ ulCriticalNesting--;
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
}
/*-----------------------------------------------------------*/
void vPortYieldHandler( void )
{
- uint32_t ulSavedInterruptMask;
+uint32_t ulSavedInterruptMask;
- ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- /* Note this will clear all forced interrupts - this is done for speed. */
- INTC_CFRC = 0x3E;
- vTaskSwitchContext();
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Note this will clear all forced interrupts - this is done for speed. */
+ INTC_CFRC = 0x3E;
+ vTaskSwitchContext();
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}
/*-----------------------------------------------------------*/
void interrupt VectorNumber_Vrtc vPortTickISR( void )
{
- uint32_t ulSavedInterruptMask;
+uint32_t ulSavedInterruptMask;
- /* Clear the interrupt. */
- RTCSC |= RTCSC_RTIF_MASK;
+ /* Clear the interrupt. */
+ RTCSC |= RTCSC_RTIF_MASK;
- /* Increment the RTOS tick. */
- ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+ /* Increment the RTOS tick. */
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}
+
diff --git a/portable/CodeWarrior/ColdFire_V1/portmacro.h b/portable/CodeWarrior/ColdFire_V1/portmacro.h
index e5d783d..efb1dca 100644
--- a/portable/CodeWarrior/ColdFire_V1/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V1/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,73 +43,73 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 4
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
- uint32_t ulPortSetIPL( uint32_t );
- #define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
+uint32_t ulPortSetIPL( uint32_t );
+#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
- extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
- extern void vPortClearInterruptMaskFromISR( UBaseType_t );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portNOP() asm volatile ( "nop" )
+#define portNOP() asm volatile ( "nop" )
/* Context switches are requested using the force register. */
- #define portYIELD() INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
+#define portYIELD() INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- if( xSwitchRequired != pdFALSE ) \
- { \
- portYIELD(); \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) \
+ { \
+ portYIELD(); \
+ }
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/CodeWarrior/ColdFire_V2/port.c b/portable/CodeWarrior/ColdFire_V2/port.c
index 8616098..eefccd6 100644
--- a/portable/CodeWarrior/ColdFire_V2/port.c
+++ b/portable/CodeWarrior/ColdFire_V2/port.c
@@ -30,52 +30,50 @@
#include "task.h"
-#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 )
+#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 )
/* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000 )
+#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000)
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
- * will be set to 0 prior to the first task being started. */
+will be set to 0 prior to the first task being started. */
static uint32_t ulCriticalNesting = 0x9999UL;
-#define portSAVE_CONTEXT() \
- lea.l( -60, % sp ), % sp; \
- movem.l % d0 - % fp, ( % sp ); \
- move.l pxCurrentTCB, % a0; \
- move.l % sp, ( % a0 );
+#define portSAVE_CONTEXT() \
+ lea.l (-60, %sp), %sp; \
+ movem.l %d0-%fp, (%sp); \
+ move.l pxCurrentTCB, %a0; \
+ move.l %sp, (%a0);
-#define portRESTORE_CONTEXT() \
- move.l pxCurrentTCB, % a0; \
- move.l( % a0 ), % sp; \
- movem.l( % sp ), % d0 - % fp; \
- lea.l % sp@( 60 ), % sp; \
- rte
+#define portRESTORE_CONTEXT() \
+ move.l pxCurrentTCB, %a0; \
+ move.l (%a0), %sp; \
+ movem.l (%sp), %d0-%fp; \
+ lea.l %sp@(60), %sp; \
+ rte
/*-----------------------------------------------------------*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+ pxTopOfStack--;
- /* Exception stack frame starts with the return address. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
+ /* Exception stack frame starts with the return address. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
- *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
- pxTopOfStack--;
+ *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
- pxTopOfStack -= 14; /* A5 to D0. */
+ *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
+ pxTopOfStack -= 14; /* A5 to D0. */
return pxTopOfStack;
}
@@ -83,68 +81,67 @@
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
- ulCriticalNesting = 0UL;
+ ulCriticalNesting = 0UL;
- /* Configure the interrupts used by this port. */
- vApplicationSetupInterrupts();
+ /* Configure the interrupts used by this port. */
+ vApplicationSetupInterrupts();
- /* Start the first task executing. */
- vPortStartFirstTask();
+ /* Start the first task executing. */
+ vPortStartFirstTask();
- return pdFALSE;
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented as there is nothing to return to. */
+ /* Not implemented as there is nothing to return to. */
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- if( ulCriticalNesting == 0UL )
- {
- /* Guard against context switches being pended simultaneously with a
- * critical section being entered. */
- do
- {
- portDISABLE_INTERRUPTS();
+ if( ulCriticalNesting == 0UL )
+ {
+ /* Guard against context switches being pended simultaneously with a
+ critical section being entered. */
+ do
+ {
+ portDISABLE_INTERRUPTS();
+ if( MCF_INTC0_INTFRCH == 0UL )
+ {
+ break;
+ }
- if( MCF_INTC0_INTFRCH == 0UL )
- {
- break;
- }
+ portENABLE_INTERRUPTS();
- portENABLE_INTERRUPTS();
- } while( 1 );
- }
-
- ulCriticalNesting++;
+ } while( 1 );
+ }
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- ulCriticalNesting--;
-
- if( ulCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
+ ulCriticalNesting--;
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
}
/*-----------------------------------------------------------*/
void vPortYieldHandler( void )
{
- uint32_t ulSavedInterruptMask;
+uint32_t ulSavedInterruptMask;
- ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
- /* Note this will clear all forced interrupts - this is done for speed. */
- MCF_INTC0_INTFRCL = 0;
- vTaskSwitchContext();
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* Note this will clear all forced interrupts - this is done for speed. */
+ MCF_INTC0_INTFRCL = 0;
+ vTaskSwitchContext();
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}
/*-----------------------------------------------------------*/
+
diff --git a/portable/CodeWarrior/ColdFire_V2/portmacro.h b/portable/CodeWarrior/ColdFire_V2/portmacro.h
index e2eb0af..9ba19da 100644
--- a/portable/CodeWarrior/ColdFire_V2/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V2/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,72 +43,72 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 4
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
- uint32_t ulPortSetIPL( uint32_t );
- #define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
+uint32_t ulPortSetIPL( uint32_t );
+#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
- extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
- extern void vPortClearInterruptMaskFromISR( UBaseType_t );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portNOP() asm volatile ( "nop" )
+#define portNOP() asm volatile ( "nop" )
/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
- #define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /* -32 as we are using the high word of the 64bit mask. */
+#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /* -32 as we are using the high word of the 64bit mask. */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- if( xSwitchRequired != pdFALSE ) \
- { \
- portYIELD(); \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) \
+ { \
+ portYIELD(); \
+ }
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/CodeWarrior/HCS12/port.c b/portable/CodeWarrior/HCS12/port.c
index 9069850..d6d0294 100644
--- a/portable/CodeWarrior/HCS12/port.c
+++ b/portable/CodeWarrior/HCS12/port.c
@@ -31,139 +31,137 @@
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the HCS12 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the HCS12 port.
+ *----------------------------------------------------------*/
/*
- * Configure a timer to generate the RTOS tick at the frequency specified
+ * Configure a timer to generate the RTOS tick at the frequency specified
* within FreeRTOSConfig.h.
*/
static void prvSetupTimerInterrupt( void );
/* Interrupt service routines have to be in non-banked memory - as does the
- * scheduler startup function. */
+scheduler startup function. */
#pragma CODE_SEG __NEAR_SEG NON_BANKED
-/* Manual context switch function. This is the SWI ISR. */
-void interrupt vPortYield( void );
+ /* Manual context switch function. This is the SWI ISR. */
+ void interrupt vPortYield( void );
-/* Tick context switch function. This is the timer ISR. */
-void interrupt vPortTickInterrupt( void );
-
-/* Simply called by xPortStartScheduler(). xPortStartScheduler() does not
- * start the scheduler directly because the header file containing the
- * xPortStartScheduler() prototype is part of the common kernel code, and
- * therefore cannot use the CODE_SEG pragma. */
-static BaseType_t xBankedStartScheduler( void );
+ /* Tick context switch function. This is the timer ISR. */
+ void interrupt vPortTickInterrupt( void );
+
+ /* Simply called by xPortStartScheduler(). xPortStartScheduler() does not
+ start the scheduler directly because the header file containing the
+ xPortStartScheduler() prototype is part of the common kernel code, and
+ therefore cannot use the CODE_SEG pragma. */
+ static BaseType_t xBankedStartScheduler( void );
#pragma CODE_SEG DEFAULT
-/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
- * critical section should not be left (i.e. interrupts should not be re-enabled)
- * until the nesting depth reaches 0. This variable simply tracks the nesting
- * depth. Each task maintains it's own critical nesting depth variable so
- * uxCriticalNesting is saved and restored from the task stack during a context
- * switch. */
+/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
+critical section should not be left (i.e. interrupts should not be re-enabled)
+until the nesting depth reaches 0. This variable simply tracks the nesting
+depth. Each task maintains it's own critical nesting depth variable so
+uxCriticalNesting is saved and restored from the task stack during a context
+switch. */
volatile UBaseType_t uxCriticalNesting = 0xff;
/*-----------------------------------------------------------*/
-/*
- * See header file for description.
+/*
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /*
- * Place a few bytes of known values on the bottom of the stack.
- * This can be uncommented to provide useful stack markers when debugging.
- *
- * pxTopOfStack = ( StackType_t ) 0x11;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x22;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x33;
- * pxTopOfStack--;
- */
+ /*
+ Place a few bytes of known values on the bottom of the stack.
+ This can be uncommented to provide useful stack markers when debugging.
+
+ *pxTopOfStack = ( StackType_t ) 0x11;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x22;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x33;
+ pxTopOfStack--;
+ */
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. In this case the stack as
- * expected by the HCS12 RTI instruction. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. In this case the stack as
+ expected by the HCS12 RTI instruction. */
- /* The address of the task function is placed in the stack byte at a time. */
- *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 1 );
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 0 );
- pxTopOfStack--;
+ /* The address of the task function is placed in the stack byte at a time. */
+ *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
+ pxTopOfStack--;
- /* Next are all the registers that form part of the task context. */
+ /* Next are all the registers that form part of the task context. */
- /* Y register */
- *pxTopOfStack = ( StackType_t ) 0xff;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xee;
- pxTopOfStack--;
+ /* Y register */
+ *pxTopOfStack = ( StackType_t ) 0xff;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xee;
+ pxTopOfStack--;
- /* X register */
- *pxTopOfStack = ( StackType_t ) 0xdd;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xcc;
- pxTopOfStack--;
+ /* X register */
+ *pxTopOfStack = ( StackType_t ) 0xdd;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xcc;
+ pxTopOfStack--;
+
+ /* A register contains parameter high byte. */
+ *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
+ pxTopOfStack--;
- /* A register contains parameter high byte. */
- *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 0 );
- pxTopOfStack--;
+ /* B register contains parameter low byte. */
+ *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
+ pxTopOfStack--;
- /* B register contains parameter low byte. */
- *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 );
- pxTopOfStack--;
+ /* CCR: Note that when the task starts interrupts will be enabled since
+ "I" bit of CCR is cleared */
+ *pxTopOfStack = ( StackType_t ) 0x00;
+ pxTopOfStack--;
+
+ #ifdef BANKED_MODEL
+ /* The page of the task. */
+ *pxTopOfStack = ( StackType_t ) ( ( int ) pxCode );
+ pxTopOfStack--;
+ #endif
+
+ /* Finally the critical nesting depth is initialised with 0 (not within
+ a critical section). */
+ *pxTopOfStack = ( StackType_t ) 0x00;
- /* CCR: Note that when the task starts interrupts will be enabled since
- * "I" bit of CCR is cleared */
- *pxTopOfStack = ( StackType_t ) 0x00;
- pxTopOfStack--;
-
- #ifdef BANKED_MODEL
- /* The page of the task. */
- *pxTopOfStack = ( StackType_t ) ( ( int ) pxCode );
- pxTopOfStack--;
- #endif
-
- /* Finally the critical nesting depth is initialised with 0 (not within
- * a critical section). */
- *pxTopOfStack = ( StackType_t ) 0x00;
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the HCS12 port will get stopped. */
+ /* It is unlikely that the HCS12 port will get stopped. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- TickTimer_SetFreqHz( configTICK_RATE_HZ );
- TickTimer_Enable();
+ TickTimer_SetFreqHz( configTICK_RATE_HZ );
+ TickTimer_Enable();
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* xPortStartScheduler() does not start the scheduler directly because
- * the header file containing the xPortStartScheduler() prototype is part
- * of the common kernel code, and therefore cannot use the CODE_SEG pragma.
- * Instead it simply calls the locally defined xBankedStartScheduler() -
- * which does use the CODE_SEG pragma. */
+ /* xPortStartScheduler() does not start the scheduler directly because
+ the header file containing the xPortStartScheduler() prototype is part
+ of the common kernel code, and therefore cannot use the CODE_SEG pragma.
+ Instead it simply calls the locally defined xBankedStartScheduler() -
+ which does use the CODE_SEG pragma. */
- return xBankedStartScheduler();
+ return xBankedStartScheduler();
}
/*-----------------------------------------------------------*/
@@ -171,18 +169,18 @@
static BaseType_t xBankedStartScheduler( void )
{
- /* Configure the timer that will generate the RTOS tick. Interrupts are
- * disabled when this function is called. */
- prvSetupTimerInterrupt();
+ /* Configure the timer that will generate the RTOS tick. Interrupts are
+ disabled when this function is called. */
+ prvSetupTimerInterrupt();
- /* Restore the context of the first task. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the first task. */
+ portRESTORE_CONTEXT();
- /* Simulate the end of an interrupt to start the scheduler off. */
- __asm( "rti" );
+ /* Simulate the end of an interrupt to start the scheduler off. */
+ __asm( "rti" );
- /* Should not get here! */
- return pdFALSE;
+ /* Should not get here! */
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
@@ -196,42 +194,44 @@
*/
void interrupt vPortYield( void )
{
- portSAVE_CONTEXT();
- vTaskSwitchContext();
- portRESTORE_CONTEXT();
+ portSAVE_CONTEXT();
+ vTaskSwitchContext();
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
/*
- * RTOS tick interrupt service routine. If the cooperative scheduler is
- * being used then this simply increments the tick count. If the
+ * RTOS tick interrupt service routine. If the cooperative scheduler is
+ * being used then this simply increments the tick count. If the
* preemptive scheduler is being used a context switch can occur.
*/
void interrupt vPortTickInterrupt( void )
{
- #if configUSE_PREEMPTION == 1
- {
- /* A context switch might happen so save the context. */
- portSAVE_CONTEXT();
+ #if configUSE_PREEMPTION == 1
+ {
+ /* A context switch might happen so save the context. */
+ portSAVE_CONTEXT();
- /* Increment the tick ... */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
+ /* Increment the tick ... */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
- TFLG1 = 1;
+ TFLG1 = 1;
- /* Restore the context of a task - which may be a different task
- * to that interrupted. */
- portRESTORE_CONTEXT();
- }
- #else /* if configUSE_PREEMPTION == 1 */
- {
- xTaskIncrementTick();
- TFLG1 = 1;
- }
- #endif /* if configUSE_PREEMPTION == 1 */
+ /* Restore the context of a task - which may be a different task
+ to that interrupted. */
+ portRESTORE_CONTEXT();
+ }
+ #else
+ {
+ xTaskIncrementTick();
+ TFLG1 = 1;
+ }
+ #endif
}
#pragma CODE_SEG DEFAULT
+
+
diff --git a/portable/CodeWarrior/HCS12/portmacro.h b/portable/CodeWarrior/HCS12/portmacro.h
index 05fa65e..f4be256 100644
--- a/portable/CodeWarrior/HCS12/portmacro.h
+++ b/portable/CodeWarrior/HCS12/portmacro.h
@@ -40,38 +40,38 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint8_t
-#define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 1
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portYIELD() __asm( "swi" );
-#define portNOP() __asm( "nop" );
+#define portBYTE_ALIGNMENT 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD() __asm( "swi" );
+#define portNOP() __asm( "nop" );
/*-----------------------------------------------------------*/
/* Critical section handling. */
-#define portENABLE_INTERRUPTS() __asm( "cli" )
-#define portDISABLE_INTERRUPTS() __asm( "sei" )
+#define portENABLE_INTERRUPTS() __asm( "cli" )
+#define portDISABLE_INTERRUPTS() __asm( "sei" )
/*
* Disable interrupts before incrementing the count of critical section nesting.
@@ -79,29 +79,29 @@
* re-enabled. Once interrupts are disabled the nesting count can be accessed
* directly. Each task maintains its own nesting count.
*/
-#define portENTER_CRITICAL() \
- { \
- extern volatile UBaseType_t uxCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- uxCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ uxCriticalNesting++; \
+}
/*
* Interrupts are disabled so we can access the nesting count directly. If the
* nesting is found to be 0 (no nesting) then we are leaving the critical
* section and interrupts can be re-enabled.
*/
-#define portEXIT_CRITICAL() \
- { \
- extern volatile UBaseType_t uxCriticalNesting; \
- \
- uxCriticalNesting--; \
- if( uxCriticalNesting == 0 ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ \
+ uxCriticalNesting--; \
+ if( uxCriticalNesting == 0 ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
@@ -117,71 +117,70 @@
*/
#ifdef BANKED_MODEL
+ /*
+ * Load the stack pointer for the task, then pull the critical nesting
+ * count and PPAGE register from the stack. The remains of the
+ * context are restored by the RTI instruction.
+ */
+ #define portRESTORE_CONTEXT() \
+ { \
+ extern volatile void * pxCurrentTCB; \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ \
+ __asm( "ldx pxCurrentTCB" ); \
+ __asm( "lds 0, x" ); \
+ __asm( "pula" ); \
+ __asm( "staa uxCriticalNesting" ); \
+ __asm( "pula" ); \
+ __asm( "staa 0x30" ); /* 0x30 = PPAGE */ \
+ }
-/*
- * Load the stack pointer for the task, then pull the critical nesting
- * count and PPAGE register from the stack. The remains of the
- * context are restored by the RTI instruction.
- */
- #define portRESTORE_CONTEXT() \
- { \
- extern volatile void * pxCurrentTCB; \
- extern volatile UBaseType_t uxCriticalNesting; \
- \
- __asm( "ldx pxCurrentTCB" ); \
- __asm( "lds 0, x" ); \
- __asm( "pula" ); \
- __asm( "staa uxCriticalNesting" ); \
- __asm( "pula" ); \
- __asm( "staa 0x30" ); /* 0x30 = PPAGE */ \
- }
+ /*
+ * By the time this macro is called the processor has already stacked the
+ * registers. Simply stack the nesting count and PPAGE value, then save
+ * the task stack pointer.
+ */
+ #define portSAVE_CONTEXT() \
+ { \
+ extern volatile void * pxCurrentTCB; \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ \
+ __asm( "ldaa 0x30" ); /* 0x30 = PPAGE */ \
+ __asm( "psha" ); \
+ __asm( "ldaa uxCriticalNesting" ); \
+ __asm( "psha" ); \
+ __asm( "ldx pxCurrentTCB" ); \
+ __asm( "sts 0, x" ); \
+ }
+#else
-/*
- * By the time this macro is called the processor has already stacked the
- * registers. Simply stack the nesting count and PPAGE value, then save
- * the task stack pointer.
- */
- #define portSAVE_CONTEXT() \
- { \
- extern volatile void * pxCurrentTCB; \
- extern volatile UBaseType_t uxCriticalNesting; \
- \
- __asm( "ldaa 0x30" ); /* 0x30 = PPAGE */ \
- __asm( "psha" ); \
- __asm( "ldaa uxCriticalNesting" ); \
- __asm( "psha" ); \
- __asm( "ldx pxCurrentTCB" ); \
- __asm( "sts 0, x" ); \
- }
-#else /* ifdef BANKED_MODEL */
+ /*
+ * These macros are as per the BANKED versions above, but without saving
+ * and restoring the PPAGE register.
+ */
-/*
- * These macros are as per the BANKED versions above, but without saving
- * and restoring the PPAGE register.
- */
+ #define portRESTORE_CONTEXT() \
+ { \
+ extern volatile void * pxCurrentTCB; \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ \
+ __asm( "ldx pxCurrentTCB" ); \
+ __asm( "lds 0, x" ); \
+ __asm( "pula" ); \
+ __asm( "staa uxCriticalNesting" ); \
+ }
- #define portRESTORE_CONTEXT() \
- { \
- extern volatile void * pxCurrentTCB; \
- extern volatile UBaseType_t uxCriticalNesting; \
- \
- __asm( "ldx pxCurrentTCB" ); \
- __asm( "lds 0, x" ); \
- __asm( "pula" ); \
- __asm( "staa uxCriticalNesting" ); \
- }
-
- #define portSAVE_CONTEXT() \
- { \
- extern volatile void * pxCurrentTCB; \
- extern volatile UBaseType_t uxCriticalNesting; \
- \
- __asm( "ldaa uxCriticalNesting" ); \
- __asm( "psha" ); \
- __asm( "ldx pxCurrentTCB" ); \
- __asm( "sts 0, x" ); \
- }
-#endif /* ifdef BANKED_MODEL */
+ #define portSAVE_CONTEXT() \
+ { \
+ extern volatile void * pxCurrentTCB; \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ \
+ __asm( "ldaa uxCriticalNesting" ); \
+ __asm( "psha" ); \
+ __asm( "ldx pxCurrentTCB" ); \
+ __asm( "sts 0, x" ); \
+ }
+#endif
/*
* Utility macro to call macros above in correct order in order to perform a
@@ -189,14 +188,15 @@
* the ISR does not use any local (stack) variables. If the ISR uses stack
* variables portYIELD() should be used in it's place.
*/
-#define portTASK_SWITCH_FROM_ISR() \
- portSAVE_CONTEXT(); \
- vTaskSwitchContext(); \
- portRESTORE_CONTEXT();
+#define portTASK_SWITCH_FROM_ISR() \
+ portSAVE_CONTEXT(); \
+ vTaskSwitchContext(); \
+ portRESTORE_CONTEXT();
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/ARM7_AT91FR40008/port.c b/portable/GCC/ARM7_AT91FR40008/port.c
index 4697b4e..804134a 100644
--- a/portable/GCC/ARM7_AT91FR40008/port.c
+++ b/portable/GCC/ARM7_AT91FR40008/port.c
@@ -27,13 +27,13 @@
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Atmel AT91R40008
-* port.
-*
-* Components that can be compiled to either ARM or THUMB mode are
-* contained in this file. The ISR routines, which can only be compiled
-* to ARM mode are contained in portISR.c.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Atmel AT91R40008
+ * port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file. The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
/* Standard includes. */
#include <stdlib.h>
@@ -49,126 +49,124 @@
#include "tc.h"
/* Constants required to setup the task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
-#define portTICK_PRIORITY_6 ( 6 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+#define portTICK_PRIORITY_6 ( 6 )
/*-----------------------------------------------------------*/
/* Setup the timer to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
-/*
- * The scheduler can only be started from ARM mode, so
- * vPortISRStartFirstSTask() is defined in portISR.c.
+/*
+ * The scheduler can only be started from ARM mode, so
+ * vPortISRStartFirstSTask() is defined in portISR.c.
*/
extern void vPortISRStartFirstTask( void );
/*-----------------------------------------------------------*/
-/*
- * Initialise the stack of a task to look exactly as if a call to
+/*
+ * Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
- * See header file for description.
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
+
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* The last thing onto the stack is the status register, which is set for
+ system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- /* The last thing onto the stack is the status register, which is set for
- * system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ #ifdef THUMB_INTERWORK
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+ #endif
- #ifdef THUMB_INTERWORK
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
- #endif
+ pxTopOfStack--;
- pxTopOfStack--;
+ /* Some optimisation levels use the stack differently to others. This
+ means the interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
- /* Some optimisation levels use the stack differently to others. This
- * means the interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortISRStartFirstTask();
+ /* Start the first task. */
+ vPortISRStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
@@ -177,63 +175,64 @@
*/
static void prvSetupTimerInterrupt( void )
{
- volatile uint32_t ulDummy;
+volatile uint32_t ulDummy;
- /* Enable clock to the tick timer... */
- AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
+ /* Enable clock to the tick timer... */
+ AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
- /* Stop the tick timer... */
- portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
+ /* Stop the tick timer... */
+ portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
- /* Start with tick timer interrupts disabled... */
- portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
+ /* Start with tick timer interrupts disabled... */
+ portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
- /* Clear any pending tick timer interrupts... */
- ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
+ /* Clear any pending tick timer interrupts... */
+ ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
- /* Store interrupt handler function address in tick timer vector register...
- * The ISR installed depends on whether the preemptive or cooperative
- * scheduler is being used. */
- #if configUSE_PREEMPTION == 1
- {
- extern void( vPreemptiveTick )( void );
- AT91C_BASE_AIC->AIC_SVR[ portTIMER_AIC_CHANNEL ] = ( uint32_t ) vPreemptiveTick;
- }
- #else // else use cooperative scheduler
- {
- extern void( vNonPreemptiveTick )( void );
- AT91C_BASE_AIC->AIC_SVR[ portTIMER_AIC_CHANNEL ] = ( uint32_t ) vNonPreemptiveTick;
- }
- #endif
+ /* Store interrupt handler function address in tick timer vector register...
+ The ISR installed depends on whether the preemptive or cooperative
+ scheduler is being used. */
+ #if configUSE_PREEMPTION == 1
+ {
+ extern void ( vPreemptiveTick )( void );
+ AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick;
+ }
+ #else // else use cooperative scheduler
+ {
+ extern void ( vNonPreemptiveTick )( void );
+ AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick;
+ }
+ #endif
- /* Tick timer interrupt level-sensitive, priority 6... */
- AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
+ /* Tick timer interrupt level-sensitive, priority 6... */
+ AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
- /* Enable the tick timer interrupt...
- *
- * First at timer level */
- portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
+ /* Enable the tick timer interrupt...
- /* Then at the AIC level. */
- AT91C_BASE_AIC->AIC_IECR = ( 1 << portTIMER_AIC_CHANNEL );
+ First at timer level */
+ portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
- /* Calculate timer compare value to achieve the desired tick rate... */
- if( ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 ) ) <= 0xFFFF )
- {
- /* The tick rate is fast enough for us to use the faster timer input
- * clock (main clock / 2). */
- portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
- portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 );
- }
- else
- {
- /* We must use a slower timer input clock (main clock / 8) because the
- * tick rate is too slow for the faster input clock. */
- portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
- portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 8 );
- }
+ /* Then at the AIC level. */
+ AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
- /* Start tick timer... */
- portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
+ /* Calculate timer compare value to achieve the desired tick rate... */
+ if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
+ {
+ /* The tick rate is fast enough for us to use the faster timer input
+ clock (main clock / 2). */
+ portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
+ portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
+ }
+ else
+ {
+ /* We must use a slower timer input clock (main clock / 8) because the
+ tick rate is too slow for the faster input clock. */
+ portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
+ portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
+ }
+
+ /* Start tick timer... */
+ portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
}
/*-----------------------------------------------------------*/
+
diff --git a/portable/GCC/ARM7_AT91FR40008/portISR.c b/portable/GCC/ARM7_AT91FR40008/portISR.c
index 7f4bb42..11c46d0 100644
--- a/portable/GCC/ARM7_AT91FR40008/portISR.c
+++ b/portable/GCC/ARM7_AT91FR40008/portISR.c
@@ -27,17 +27,17 @@
/*-----------------------------------------------------------
-* Components that can be compiled to either ARM or THUMB mode are
-* contained in port.c The ISR routines, which can only be compiled
-* to ARM mode, are contained in this file.
-*----------------------------------------------------------*/
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
/*
- * Changes from V3.2.4
- *
- + The assembler statements are now included in a single asm block rather
- + than each line having its own asm block.
- */
+ Changes from V3.2.4
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+*/
/* Scheduler includes. */
@@ -45,18 +45,18 @@
#include "task.h"
/* Constants required to handle interrupts. */
-#define portCLEAR_AIC_INTERRUPT ( ( uint32_t ) 0 )
+#define portCLEAR_AIC_INTERRUPT ( ( uint32_t ) 0 )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
volatile uint32_t ulCriticalNesting = 9999UL;
/*-----------------------------------------------------------*/
/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
-/*
+/*
* The scheduler can only be started from ARM mode, hence the inclusion of this
* function here.
*/
@@ -65,93 +65,93 @@
void vPortISRStartFirstTask( void )
{
- /* Simply start the scheduler. This is included here as it can only be
- * called from ARM mode. */
- portRESTORE_CONTEXT();
+ /* Simply start the scheduler. This is included here as it can only be
+ called from ARM mode. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
/*
* Called by portYIELD() or taskYIELD() to manually force a context switch.
*
- * When a context switch is performed from the task level the saved task
+ * When a context switch is performed from the task level the saved task
* context is made to look as if it occurred from within the tick ISR. This
* way the same restore context function can be used when restoring the context
* saved from the ISR or that saved from a call to vPortYieldProcessor.
*/
void vPortYieldProcessor( void )
{
- /* Within an IRQ ISR the link register has an offset from the true return
- * address, but an SWI ISR does not. Add the offset manually so the same
- * ISR return code can be used in both cases. */
- asm volatile ( "ADD LR, LR, #4");
+ /* Within an IRQ ISR the link register has an offset from the true return
+ address, but an SWI ISR does not. Add the offset manually so the same
+ ISR return code can be used in both cases. */
+ asm volatile ( "ADD LR, LR, #4" );
- /* Perform the context switch. First save the context of the current task. */
- portSAVE_CONTEXT();
+ /* Perform the context switch. First save the context of the current task. */
+ portSAVE_CONTEXT();
- /* Find the highest priority task that is ready to run. */
- vTaskSwitchContext();
+ /* Find the highest priority task that is ready to run. */
+ vTaskSwitchContext();
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
-/*
+/*
* The ISR used for the scheduler tick depends on whether the cooperative or
* the preemptive scheduler is being used.
*/
#if configUSE_PREEMPTION == 0
-/* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick. */
- void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
- void vNonPreemptiveTick( void )
- {
- static volatile uint32_t ulDummy;
+ /* The cooperative scheduler requires a normal IRQ service routine to
+ simply increment the system tick. */
+ void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+ void vNonPreemptiveTick( void )
+ {
+ static volatile uint32_t ulDummy;
- /* Clear tick timer interrupt indication. */
- ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
+ /* Clear tick timer interrupt indication. */
+ ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
- xTaskIncrementTick();
+ xTaskIncrementTick();
- /* Acknowledge the interrupt at AIC level... */
- AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
- }
+ /* Acknowledge the interrupt at AIC level... */
+ AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
+ }
-#else /* else preemption is turned on */
+#else /* else preemption is turned on */
-/* The preemptive scheduler is defined as "naked" as the full context is
- * saved on entry as part of the context switch. */
- void vPreemptiveTick( void ) __attribute__( ( naked ) );
- void vPreemptiveTick( void )
- {
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
+ /* The preemptive scheduler is defined as "naked" as the full context is
+ saved on entry as part of the context switch. */
+ void vPreemptiveTick( void ) __attribute__((naked));
+ void vPreemptiveTick( void )
+ {
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
- /* WARNING - Do not use local (stack) variables here. Use globals
- * if you must! */
- static volatile uint32_t ulDummy;
+ /* WARNING - Do not use local (stack) variables here. Use globals
+ if you must! */
+ static volatile uint32_t ulDummy;
- /* Clear tick timer interrupt indication. */
- ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
+ /* Clear tick timer interrupt indication. */
+ ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
- /* Increment the RTOS tick count, then look for the highest priority
- * task that is ready to run. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
+ /* Increment the RTOS tick count, then look for the highest priority
+ task that is ready to run. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
- /* Acknowledge the interrupt at AIC level... */
- AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
+ /* Acknowledge the interrupt at AIC level... */
+ AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
- }
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+ }
-#endif /* if configUSE_PREEMPTION == 0 */
+#endif
/*-----------------------------------------------------------*/
/*
@@ -162,71 +162,72 @@
*/
#ifdef THUMB_INTERWORK
- void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
- void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
- void vPortDisableInterruptsFromThumb( void )
- {
- asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0} \n\t"/* Pop R0. */
- "BX R14"); /* Return back to thumb. */
- }
-
- void vPortEnableInterruptsFromThumb( void )
- {
- asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0} \n\t"/* Pop R0. */
- "BX R14"); /* Return back to thumb. */
- }
+ void vPortDisableInterruptsFromThumb( void )
+ {
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+ void vPortEnableInterruptsFromThumb( void )
+ {
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
#endif /* THUMB_INTERWORK */
/* The code generated by the GCC compiler uses the stack in different ways at
- * different optimisation levels. The interrupt flags can therefore not always
- * be saved to the stack. Instead the critical section nesting level is stored
- * in a variable, which is then saved as part of the stack context. */
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0}"); /* Pop R0. */
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0}"); /* Pop R0. */
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+ }
+ }
}
+
diff --git a/portable/GCC/ARM7_AT91FR40008/portmacro.h b/portable/GCC/ARM7_AT91FR40008/portmacro.h
index 6eedc16..f9b529f 100644
--- a/portable/GCC/ARM7_AT91FR40008/portmacro.h
+++ b/portable/GCC/ARM7_AT91FR40008/portmacro.h
@@ -26,34 +26,34 @@
*/
/*
- * Changes from V3.2.3
- *
- + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
- +
- + Changes from V3.2.4
- +
- + Removed the use of the %0 parameter within the assembler macros and
- + replaced them with hard coded registers. This will ensure the
- + assembler does not select the link register as the temp register as
- + was occasionally happening previously.
- +
- + The assembler statements are now included in a single asm block rather
- + than each line having its own asm block.
- +
- + Changes from V4.5.0
- +
- + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
- + and replaced them with portYIELD_FROM_ISR() macro. Application code
- + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
- + macros as per the V4.5.1 demo code.
- */
+ Changes from V3.2.3
+
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+ Changes from V3.2.4
+
+ + Removed the use of the %0 parameter within the assembler macros and
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
+ + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
+*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -66,42 +66,42 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portYIELD() asm volatile ( "SWI 0" )
- #define portNOP() asm volatile ( "NOP" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portYIELD() asm volatile ( "SWI 0" )
+#define portNOP() asm volatile ( "NOP" )
/*
* These define the timer to use for generating the tick interrupt.
* They are put in this file so they can be shared between "port.c"
* and "portisr.c".
*/
- #define portTIMER_REG_BASE_PTR AT91C_BASE_TC0
- #define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0
- #define portTIMER_AIC_CHANNEL ( ( uint32_t ) 4 )
+#define portTIMER_REG_BASE_PTR AT91C_BASE_TC0
+#define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0
+#define portTIMER_AIC_CHANNEL ( ( uint32_t ) 4 )
/*-----------------------------------------------------------*/
/* Task utilities. */
@@ -113,90 +113,90 @@
* THUMB mode code will result in a compile time error.
*/
- #define portRESTORE_CONTEXT() \
- { \
- extern volatile void * volatile pxCurrentTCB; \
- extern volatile uint32_t ulCriticalNesting; \
- \
- /* Set the LR to the task stack. */ \
- asm volatile ( \
- "LDR R0, =pxCurrentTCB \n\t"\
- "LDR R0, [R0] \n\t"\
- "LDR LR, [R0] \n\t"\
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting \n\t"\
- "LDMFD LR!, {R1} \n\t"\
- "STR R1, [R0] \n\t"\
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0} \n\t"\
- "MSR SPSR, R0 \n\t"\
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^ \n\t"\
- "NOP \n\t"\
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60] \n\t"\
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4 \n\t"\
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
- }
+#define portRESTORE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Set the LR to the task stack. */ \
+ asm volatile ( \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "LDR LR, [R0] \n\t" \
+ \
+ /* The critical nesting depth is the first item on the stack. */ \
+ /* Load it into the ulCriticalNesting variable. */ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDMFD LR!, {R1} \n\t" \
+ "STR R1, [R0] \n\t" \
+ \
+ /* Get the SPSR from the stack. */ \
+ "LDMFD LR!, {R0} \n\t" \
+ "MSR SPSR, R0 \n\t" \
+ \
+ /* Restore all system mode registers for the task. */ \
+ "LDMFD LR, {R0-R14}^ \n\t" \
+ "NOP \n\t" \
+ \
+ /* Restore the return address. */ \
+ "LDR LR, [LR, #+60] \n\t" \
+ \
+ /* And return - correcting the offset in the LR to obtain the */ \
+ /* correct address. */ \
+ "SUBS PC, LR, #4 \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
/*-----------------------------------------------------------*/
- #define portSAVE_CONTEXT() \
- { \
- extern volatile void * volatile pxCurrentTCB; \
- extern volatile uint32_t ulCriticalNesting; \
- \
- /* Push R0 as we are going to use the register. */ \
- asm volatile ( \
- "STMDB SP!, {R0} \n\t"\
- \
- /* Set R0 to point to the task stack pointer. */ \
- "STMDB SP,{SP}^ \n\t"\
- "NOP \n\t"\
- "SUB SP, SP, #4 \n\t"\
- "LDMIA SP!,{R0} \n\t"\
- \
- /* Push the return address onto the stack. */ \
- "STMDB R0!, {LR} \n\t"\
- \
- /* Now we have saved LR we can use it instead of R0. */ \
- "MOV LR, R0 \n\t"\
- \
- /* Pop R0 so we can save it onto the system mode stack. */ \
- "LDMIA SP!, {R0} \n\t"\
- \
- /* Push all the system mode registers onto the task stack. */ \
- "STMDB LR,{R0-LR}^ \n\t"\
- "NOP \n\t"\
- "SUB LR, LR, #60 \n\t"\
- \
- /* Push the SPSR onto the task stack. */ \
- "MRS R0, SPSR \n\t"\
- "STMDB LR!, {R0} \n\t"\
- \
- "LDR R0, =ulCriticalNesting \n\t"\
- "LDR R0, [R0] \n\t"\
- "STMDB LR!, {R0} \n\t"\
- \
- /* Store the new top of stack for the task. */ \
- "LDR R0, =pxCurrentTCB \n\t"\
- "LDR R0, [R0] \n\t"\
- "STR LR, [R0] \n\t"\
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
- }
+#define portSAVE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Push R0 as we are going to use the register. */ \
+ asm volatile ( \
+ "STMDB SP!, {R0} \n\t" \
+ \
+ /* Set R0 to point to the task stack pointer. */ \
+ "STMDB SP,{SP}^ \n\t" \
+ "NOP \n\t" \
+ "SUB SP, SP, #4 \n\t" \
+ "LDMIA SP!,{R0} \n\t" \
+ \
+ /* Push the return address onto the stack. */ \
+ "STMDB R0!, {LR} \n\t" \
+ \
+ /* Now we have saved LR we can use it instead of R0. */ \
+ "MOV LR, R0 \n\t" \
+ \
+ /* Pop R0 so we can save it onto the system mode stack. */ \
+ "LDMIA SP!, {R0} \n\t" \
+ \
+ /* Push all the system mode registers onto the task stack. */ \
+ "STMDB LR,{R0-LR}^ \n\t" \
+ "NOP \n\t" \
+ "SUB LR, LR, #60 \n\t" \
+ \
+ /* Push the SPSR onto the task stack. */ \
+ "MRS R0, SPSR \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ /* Store the new top of stack for the task. */ \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STR LR, [R0] \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
- #define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
/* Critical section handling. */
@@ -207,48 +207,49 @@
* defined then the utilities are defined as macros here - as per other ports.
*/
- #ifdef THUMB_INTERWORK
+#ifdef THUMB_INTERWORK
- extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
- extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
- #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
- #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
- #else
+#else
- #define portDISABLE_INTERRUPTS() \
- asm volatile ( \
- "STMDB SP!, {R0} \n\t"/* Push R0. */\
- "MRS R0, CPSR \n\t"/* Get CPSR. */\
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
- "MSR CPSR, R0 \n\t"/* Write back modified value. */\
- "LDMIA SP!, {R0} ") /* Pop R0. */
+ #define portDISABLE_INTERRUPTS() \
+ asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
- #define portENABLE_INTERRUPTS() \
- asm volatile ( \
- "STMDB SP!, {R0} \n\t"/* Push R0. */\
- "MRS R0, CPSR \n\t"/* Get CPSR. */\
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
- "MSR CPSR, R0 \n\t"/* Write back modified value. */\
- "LDMIA SP!, {R0} ") /* Pop R0. */
+ #define portENABLE_INTERRUPTS() \
+ asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
- #endif /* THUMB_INTERWORK */
+#endif /* THUMB_INTERWORK */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
index 51d5fca..a14279e 100644
--- a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
@@ -1,2759 +1,2731 @@
-/* ---------------------------------------------------------------------------- */
-/* ATMEL Microcontroller Software Support - ROUSSET - */
-/* ---------------------------------------------------------------------------- */
-/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* ---------------------------------------------------------------------------- */
-/* File Name : AT91SAM7X256.h */
-/* Object : AT91SAM7X256 definitions */
-/* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */
-/* */
-/* CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */
-/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */
-/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
-/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */
-/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */
-/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
-/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
-/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
-/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */
-/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */
-/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */
-/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */
-/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */
-/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */
-/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
-/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
-/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
-/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
-/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
-/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
-/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */
-/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */
-/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
-/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */
-/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
-/* ---------------------------------------------------------------------------- */
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM7X256.h
+// Object : AT91SAM7X256 definitions
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+//
+// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// ----------------------------------------------------------------------------
#ifndef AT91SAM7X256_H
#define AT91SAM7X256_H
-typedef volatile unsigned int AT91_REG; /* Hardware register definition */
+typedef volatile unsigned int AT91_REG;// Hardware register definition
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR System Peripherals */
-/* ***************************************************************************** */
-typedef struct _AT91S_SYS
-{
- AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
- AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
- AT91_REG AIC_IVR; /* IRQ Vector Register */
- AT91_REG AIC_FVR; /* FIQ Vector Register */
- AT91_REG AIC_ISR; /* Interrupt Status Register */
- AT91_REG AIC_IPR; /* Interrupt Pending Register */
- AT91_REG AIC_IMR; /* Interrupt Mask Register */
- AT91_REG AIC_CISR; /* Core Interrupt Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
- AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
- AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
- AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
- AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
- AT91_REG AIC_SPU; /* Spurious Vector Register */
- AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
- AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
- AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
- AT91_REG Reserved2[ 45 ]; /* */
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved3[ 7 ]; /* */
- AT91_REG DBGU_CIDR; /* Chip ID Register */
- AT91_REG DBGU_EXID; /* Chip ID Extension Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved4[ 45 ]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
- AT91_REG Reserved5[ 54 ]; /* */
- AT91_REG PIOA_PER; /* PIO Enable Register */
- AT91_REG PIOA_PDR; /* PIO Disable Register */
- AT91_REG PIOA_PSR; /* PIO Status Register */
- AT91_REG Reserved6[ 1 ]; /* */
- AT91_REG PIOA_OER; /* Output Enable Register */
- AT91_REG PIOA_ODR; /* Output Disable Registerr */
- AT91_REG PIOA_OSR; /* Output Status Register */
- AT91_REG Reserved7[ 1 ]; /* */
- AT91_REG PIOA_IFER; /* Input Filter Enable Register */
- AT91_REG PIOA_IFDR; /* Input Filter Disable Register */
- AT91_REG PIOA_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved8[ 1 ]; /* */
- AT91_REG PIOA_SODR; /* Set Output Data Register */
- AT91_REG PIOA_CODR; /* Clear Output Data Register */
- AT91_REG PIOA_ODSR; /* Output Data Status Register */
- AT91_REG PIOA_PDSR; /* Pin Data Status Register */
- AT91_REG PIOA_IER; /* Interrupt Enable Register */
- AT91_REG PIOA_IDR; /* Interrupt Disable Register */
- AT91_REG PIOA_IMR; /* Interrupt Mask Register */
- AT91_REG PIOA_ISR; /* Interrupt Status Register */
- AT91_REG PIOA_MDER; /* Multi-driver Enable Register */
- AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIOA_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved9[ 1 ]; /* */
- AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIOA_PPUER; /* Pull-up Enable Register */
- AT91_REG PIOA_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved10[ 1 ]; /* */
- AT91_REG PIOA_ASR; /* Select A Register */
- AT91_REG PIOA_BSR; /* Select B Register */
- AT91_REG PIOA_ABSR; /* AB Select Status Register */
- AT91_REG Reserved11[ 9 ]; /* */
- AT91_REG PIOA_OWER; /* Output Write Enable Register */
- AT91_REG PIOA_OWDR; /* Output Write Disable Register */
- AT91_REG PIOA_OWSR; /* Output Write Status Register */
- AT91_REG Reserved12[ 85 ]; /* */
- AT91_REG PIOB_PER; /* PIO Enable Register */
- AT91_REG PIOB_PDR; /* PIO Disable Register */
- AT91_REG PIOB_PSR; /* PIO Status Register */
- AT91_REG Reserved13[ 1 ]; /* */
- AT91_REG PIOB_OER; /* Output Enable Register */
- AT91_REG PIOB_ODR; /* Output Disable Registerr */
- AT91_REG PIOB_OSR; /* Output Status Register */
- AT91_REG Reserved14[ 1 ]; /* */
- AT91_REG PIOB_IFER; /* Input Filter Enable Register */
- AT91_REG PIOB_IFDR; /* Input Filter Disable Register */
- AT91_REG PIOB_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved15[ 1 ]; /* */
- AT91_REG PIOB_SODR; /* Set Output Data Register */
- AT91_REG PIOB_CODR; /* Clear Output Data Register */
- AT91_REG PIOB_ODSR; /* Output Data Status Register */
- AT91_REG PIOB_PDSR; /* Pin Data Status Register */
- AT91_REG PIOB_IER; /* Interrupt Enable Register */
- AT91_REG PIOB_IDR; /* Interrupt Disable Register */
- AT91_REG PIOB_IMR; /* Interrupt Mask Register */
- AT91_REG PIOB_ISR; /* Interrupt Status Register */
- AT91_REG PIOB_MDER; /* Multi-driver Enable Register */
- AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIOB_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved16[ 1 ]; /* */
- AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIOB_PPUER; /* Pull-up Enable Register */
- AT91_REG PIOB_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved17[ 1 ]; /* */
- AT91_REG PIOB_ASR; /* Select A Register */
- AT91_REG PIOB_BSR; /* Select B Register */
- AT91_REG PIOB_ABSR; /* AB Select Status Register */
- AT91_REG Reserved18[ 9 ]; /* */
- AT91_REG PIOB_OWER; /* Output Write Enable Register */
- AT91_REG PIOB_OWDR; /* Output Write Disable Register */
- AT91_REG PIOB_OWSR; /* Output Write Status Register */
- AT91_REG Reserved19[ 341 ]; /* */
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved20[ 1 ]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved21[ 1 ]; /* */
- AT91_REG PMC_MOR; /* Main Oscillator Register */
- AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved22[ 1 ]; /* */
- AT91_REG PMC_PLLR; /* PLL Register */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved23[ 3 ]; /* */
- AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */
- AT91_REG Reserved24[ 4 ]; /* */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved25[ 36 ]; /* */
- AT91_REG RSTC_RCR; /* Reset Control Register */
- AT91_REG RSTC_RSR; /* Reset Status Register */
- AT91_REG RSTC_RMR; /* Reset Mode Register */
- AT91_REG Reserved26[ 5 ]; /* */
- AT91_REG RTTC_RTMR; /* Real-time Mode Register */
- AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
- AT91_REG RTTC_RTVR; /* Real-time Value Register */
- AT91_REG RTTC_RTSR; /* Real-time Status Register */
- AT91_REG PITC_PIMR; /* Period Interval Mode Register */
- AT91_REG PITC_PISR; /* Period Interval Status Register */
- AT91_REG PITC_PIVR; /* Period Interval Value Register */
- AT91_REG PITC_PIIR; /* Period Interval Image Register */
- AT91_REG WDTC_WDCR; /* Watchdog Control Register */
- AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
- AT91_REG WDTC_WDSR; /* Watchdog Status Register */
- AT91_REG Reserved27[ 5 ]; /* */
- AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
-} AT91S_SYS, * AT91PS_SYS;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved2[45]; //
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved3[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved4[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved5[54]; //
+ AT91_REG PIOA_PER; // PIO Enable Register
+ AT91_REG PIOA_PDR; // PIO Disable Register
+ AT91_REG PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved6[1]; //
+ AT91_REG PIOA_OER; // Output Enable Register
+ AT91_REG PIOA_ODR; // Output Disable Registerr
+ AT91_REG PIOA_OSR; // Output Status Register
+ AT91_REG Reserved7[1]; //
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved8[1]; //
+ AT91_REG PIOA_SODR; // Set Output Data Register
+ AT91_REG PIOA_CODR; // Clear Output Data Register
+ AT91_REG PIOA_ODSR; // Output Data Status Register
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
+ AT91_REG PIOA_IER; // Interrupt Enable Register
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
+ AT91_REG PIOA_ISR; // Interrupt Status Register
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved9[1]; //
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved10[1]; //
+ AT91_REG PIOA_ASR; // Select A Register
+ AT91_REG PIOA_BSR; // Select B Register
+ AT91_REG PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved11[9]; //
+ AT91_REG PIOA_OWER; // Output Write Enable Register
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
+ AT91_REG PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved12[85]; //
+ AT91_REG PIOB_PER; // PIO Enable Register
+ AT91_REG PIOB_PDR; // PIO Disable Register
+ AT91_REG PIOB_PSR; // PIO Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG PIOB_OER; // Output Enable Register
+ AT91_REG PIOB_ODR; // Output Disable Registerr
+ AT91_REG PIOB_OSR; // Output Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG PIOB_IFER; // Input Filter Enable Register
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register
+ AT91_REG PIOB_IFSR; // Input Filter Status Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG PIOB_SODR; // Set Output Data Register
+ AT91_REG PIOB_CODR; // Clear Output Data Register
+ AT91_REG PIOB_ODSR; // Output Data Status Register
+ AT91_REG PIOB_PDSR; // Pin Data Status Register
+ AT91_REG PIOB_IER; // Interrupt Enable Register
+ AT91_REG PIOB_IDR; // Interrupt Disable Register
+ AT91_REG PIOB_IMR; // Interrupt Mask Register
+ AT91_REG PIOB_ISR; // Interrupt Status Register
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved16[1]; //
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved17[1]; //
+ AT91_REG PIOB_ASR; // Select A Register
+ AT91_REG PIOB_BSR; // Select B Register
+ AT91_REG PIOB_ABSR; // AB Select Status Register
+ AT91_REG Reserved18[9]; //
+ AT91_REG PIOB_OWER; // Output Write Enable Register
+ AT91_REG PIOB_OWDR; // Output Write Disable Register
+ AT91_REG PIOB_OWSR; // Output Write Status Register
+ AT91_REG Reserved19[341]; //
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved20[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved21[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved22[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved23[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved24[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved25[36]; //
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved26[5]; //
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved27[5]; //
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_AIC
-{
- AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
- AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
- AT91_REG AIC_IVR; /* IRQ Vector Register */
- AT91_REG AIC_FVR; /* FIQ Vector Register */
- AT91_REG AIC_ISR; /* Interrupt Status Register */
- AT91_REG AIC_IPR; /* Interrupt Pending Register */
- AT91_REG AIC_IMR; /* Interrupt Mask Register */
- AT91_REG AIC_CISR; /* Core Interrupt Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
- AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
- AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
- AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
- AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
- AT91_REG AIC_SPU; /* Spurious Vector Register */
- AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
- AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
- AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
-} AT91S_AIC, * AT91PS_AIC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
-/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
-#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
-#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */
-#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */
-#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
-/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
-#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
-#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
-/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
-#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
-#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_PDC
-{
- AT91_REG PDC_RPR; /* Receive Pointer Register */
- AT91_REG PDC_RCR; /* Receive Counter Register */
- AT91_REG PDC_TPR; /* Transmit Pointer Register */
- AT91_REG PDC_TCR; /* Transmit Counter Register */
- AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
- AT91_REG PDC_RNCR; /* Receive Next Counter Register */
- AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
- AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
- AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
-} AT91S_PDC, * AT91PS_PDC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/* ***************************************************************************** */
-typedef struct _AT91S_DBGU
-{
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved0[ 7 ]; /* */
- AT91_REG DBGU_CIDR; /* Chip ID Register */
- AT91_REG DBGU_EXID; /* Chip ID Extension Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved1[ 45 ]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
-} AT91S_DBGU, * AT91PS_DBGU;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */
-#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */
-/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */
-#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */
-#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */
-#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */
-#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */
-#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
-#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
-#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
-#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
-#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
-/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
-/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
-#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PIO
-{
- AT91_REG PIO_PER; /* PIO Enable Register */
- AT91_REG PIO_PDR; /* PIO Disable Register */
- AT91_REG PIO_PSR; /* PIO Status Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG PIO_OER; /* Output Enable Register */
- AT91_REG PIO_ODR; /* Output Disable Registerr */
- AT91_REG PIO_OSR; /* Output Status Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG PIO_IFER; /* Input Filter Enable Register */
- AT91_REG PIO_IFDR; /* Input Filter Disable Register */
- AT91_REG PIO_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG PIO_SODR; /* Set Output Data Register */
- AT91_REG PIO_CODR; /* Clear Output Data Register */
- AT91_REG PIO_ODSR; /* Output Data Status Register */
- AT91_REG PIO_PDSR; /* Pin Data Status Register */
- AT91_REG PIO_IER; /* Interrupt Enable Register */
- AT91_REG PIO_IDR; /* Interrupt Disable Register */
- AT91_REG PIO_IMR; /* Interrupt Mask Register */
- AT91_REG PIO_ISR; /* Interrupt Status Register */
- AT91_REG PIO_MDER; /* Multi-driver Enable Register */
- AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIO_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved3[ 1 ]; /* */
- AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIO_PPUER; /* Pull-up Enable Register */
- AT91_REG PIO_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved4[ 1 ]; /* */
- AT91_REG PIO_ASR; /* Select A Register */
- AT91_REG PIO_BSR; /* Select B Register */
- AT91_REG PIO_ABSR; /* AB Select Status Register */
- AT91_REG Reserved5[ 9 ]; /* */
- AT91_REG PIO_OWER; /* Output Write Enable Register */
- AT91_REG PIO_OWDR; /* Output Write Disable Register */
- AT91_REG PIO_OWSR; /* Output Write Status Register */
-} AT91S_PIO, * AT91PS_PIO;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_CKGR
-{
- AT91_REG CKGR_MOR; /* Main Oscillator Register */
- AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG CKGR_PLLR; /* PLL Register */
-} AT91S_CKGR, * AT91PS_CKGR;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG CKGR_PLLR; // PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */
-#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */
-/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */
-#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */
-#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
-#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */
-#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */
-#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */
-#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PMC
-{
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG PMC_MOR; /* Main Oscillator Register */
- AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG PMC_PLLR; /* PLL Register */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved3[ 3 ]; /* */
- AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */
- AT91_REG Reserved4[ 4 ]; /* */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
-} AT91S_PMC, * AT91PS_PMC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved3[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved4[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
-/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
-#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
-/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
-/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
-/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
-/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
-/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
-/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
-#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */
-#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
-/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
-/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
-#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
-/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
-/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Reset Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_RSTC
-{
- AT91_REG RSTC_RCR; /* Reset Control Register */
- AT91_REG RSTC_RSR; /* Reset Status Register */
- AT91_REG RSTC_RMR; /* Reset Mode Register */
-} AT91S_RSTC, * AT91PS_RSTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
-/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
-#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */
-#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */
-#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */
-#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
-/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
-#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */
-#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */
-#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */
-#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occured. */
-#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */
-#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */
-#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occured. */
-#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */
-#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */
-/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
-#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */
-#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_RTTC
-{
- AT91_REG RTTC_RTMR; /* Real-time Mode Register */
- AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
- AT91_REG RTTC_RTVR; /* Real-time Value Register */
- AT91_REG RTTC_RTSR; /* Real-time Status Register */
-} AT91S_RTTC, * AT91PS_RTTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
-/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
-#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
-#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */
-#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */
-#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */
-/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
-#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */
-/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
-#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */
-/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
-#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */
-#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PITC
-{
- AT91_REG PITC_PIMR; /* Period Interval Mode Register */
- AT91_REG PITC_PISR; /* Period Interval Status Register */
- AT91_REG PITC_PIVR; /* Period Interval Value Register */
- AT91_REG PITC_PIIR; /* Period Interval Image Register */
-} AT91S_PITC, * AT91PS_PITC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
-/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
-#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
-#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */
-#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */
-/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
-#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */
-/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
-#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
-#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */
-/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_WDTC
-{
- AT91_REG WDTC_WDCR; /* Watchdog Control Register */
- AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
- AT91_REG WDTC_WDSR; /* Watchdog Status Register */
-} AT91S_WDTC, * AT91PS_WDTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
-/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
-#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */
-#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */
-/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
-#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */
-#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */
-#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */
-#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
-#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */
-#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */
-/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
-#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */
-#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_VREG
-{
- AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
-} AT91S_VREG, * AT91PS_VREG;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
-/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
-#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Memory Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_MC
-{
- AT91_REG MC_RCR; /* MC Remap Control Register */
- AT91_REG MC_ASR; /* MC Abort Status Register */
- AT91_REG MC_AASR; /* MC Abort Address Status Register */
- AT91_REG Reserved0[ 21 ]; /* */
- AT91_REG MC_FMR; /* MC Flash Mode Register */
- AT91_REG MC_FCR; /* MC Flash Command Register */
- AT91_REG MC_FSR; /* MC Flash Status Register */
-} AT91S_MC, * AT91PS_MC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved0[21]; //
+ AT91_REG MC_FMR; // MC Flash Mode Register
+ AT91_REG MC_FCR; // MC Flash Command Register
+ AT91_REG MC_FSR; // MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
-/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
-#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
-/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
-#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
-#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
-#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
-#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */
-#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */
-#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */
-#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */
-#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */
-#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */
-#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */
-#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */
-#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */
-/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
-#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */
-#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */
-#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */
-#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */
-#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */
-#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */
-#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */
-#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
-/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
-#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */
-#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */
-#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
-#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
-#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */
-#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */
-#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */
-#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
-#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
-/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
-#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */
-#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */
-#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */
-#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */
-#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */
-#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */
-#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */
-#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */
-#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SPI
-{
- AT91_REG SPI_CR; /* Control Register */
- AT91_REG SPI_MR; /* Mode Register */
- AT91_REG SPI_RDR; /* Receive Data Register */
- AT91_REG SPI_TDR; /* Transmit Data Register */
- AT91_REG SPI_SR; /* Status Register */
- AT91_REG SPI_IER; /* Interrupt Enable Register */
- AT91_REG SPI_IDR; /* Interrupt Disable Register */
- AT91_REG SPI_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved0[ 4 ]; /* */
- AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */
- AT91_REG Reserved1[ 48 ]; /* */
- AT91_REG SPI_RPR; /* Receive Pointer Register */
- AT91_REG SPI_RCR; /* Receive Counter Register */
- AT91_REG SPI_TPR; /* Transmit Pointer Register */
- AT91_REG SPI_TCR; /* Transmit Counter Register */
- AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
- AT91_REG SPI_RNCR; /* Receive Next Counter Register */
- AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
- AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
- AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
-} AT91S_SPI, * AT91PS_SPI;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */
-#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */
-#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */
-#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */
-#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */
-#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */
-#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Usart */
-/* ***************************************************************************** */
-typedef struct _AT91S_USART
-{
- AT91_REG US_CR; /* Control Register */
- AT91_REG US_MR; /* Mode Register */
- AT91_REG US_IER; /* Interrupt Enable Register */
- AT91_REG US_IDR; /* Interrupt Disable Register */
- AT91_REG US_IMR; /* Interrupt Mask Register */
- AT91_REG US_CSR; /* Channel Status Register */
- AT91_REG US_RHR; /* Receiver Holding Register */
- AT91_REG US_THR; /* Transmitter Holding Register */
- AT91_REG US_BRGR; /* Baud Rate Generator Register */
- AT91_REG US_RTOR; /* Receiver Time-out Register */
- AT91_REG US_TTGR; /* Transmitter Time-guard Register */
- AT91_REG Reserved0[ 5 ]; /* */
- AT91_REG US_FIDI; /* FI_DI_Ratio Register */
- AT91_REG US_NER; /* Nb Errors Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG US_IF; /* IRDA_FILTER Register */
- AT91_REG Reserved2[ 44 ]; /* */
- AT91_REG US_RPR; /* Receive Pointer Register */
- AT91_REG US_RCR; /* Receive Counter Register */
- AT91_REG US_TPR; /* Transmit Pointer Register */
- AT91_REG US_TCR; /* Transmit Counter Register */
- AT91_REG US_RNPR; /* Receive Next Pointer Register */
- AT91_REG US_RNCR; /* Receive Next Counter Register */
- AT91_REG US_TNPR; /* Transmit Next Pointer Register */
- AT91_REG US_TNCR; /* Transmit Next Counter Register */
- AT91_REG US_PTCR; /* PDC Transfer Control Register */
- AT91_REG US_PTSR; /* PDC Transfer Status Register */
-} AT91S_USART, * AT91PS_USART;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
-/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */
-#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
-#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
-#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
-#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
-#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
-#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
-#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
-#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
-#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
-#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
-/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */
-#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */
-#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */
-#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */
-#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */
-#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */
-#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */
-#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */
-#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */
-#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */
-#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */
-#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
-#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
-#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
-#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
-#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
-#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
-#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
-#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
-#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
-#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
-/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */
-#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */
-#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
-#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
-#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
-#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
-#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
-#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
-/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
-#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */
-#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */
-#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */
-#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SSC
-{
- AT91_REG SSC_CR; /* Control Register */
- AT91_REG SSC_CMR; /* Clock Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */
- AT91_REG SSC_RFMR; /* Receive Frame Mode Register */
- AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */
- AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */
- AT91_REG SSC_RHR; /* Receive Holding Register */
- AT91_REG SSC_THR; /* Transmit Holding Register */
- AT91_REG Reserved1[ 2 ]; /* */
- AT91_REG SSC_RSHR; /* Receive Sync Holding Register */
- AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */
- AT91_REG Reserved2[ 2 ]; /* */
- AT91_REG SSC_SR; /* Status Register */
- AT91_REG SSC_IER; /* Interrupt Enable Register */
- AT91_REG SSC_IDR; /* Interrupt Disable Register */
- AT91_REG SSC_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved3[ 44 ]; /* */
- AT91_REG SSC_RPR; /* Receive Pointer Register */
- AT91_REG SSC_RCR; /* Receive Counter Register */
- AT91_REG SSC_TPR; /* Transmit Pointer Register */
- AT91_REG SSC_TCR; /* Transmit Counter Register */
- AT91_REG SSC_RNPR; /* Receive Next Pointer Register */
- AT91_REG SSC_RNCR; /* Receive Next Counter Register */
- AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SSC_TNCR; /* Transmit Next Counter Register */
- AT91_REG SSC_PTCR; /* PDC Transfer Control Register */
- AT91_REG SSC_PTSR; /* PDC Transfer Status Register */
-} AT91S_SSC, * AT91PS_SSC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved3[44]; //
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
-/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
-#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */
-#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */
-#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */
-#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */
-/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
-#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */
-#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */
-#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */
-#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */
-#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */
-#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
-#define AT91C_SSC_CKO_CONTINOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
-#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
-#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */
-#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */
-#define AT91C_SSC_START_CONTINOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
-#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */
-#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */
-#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */
-#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */
-#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */
-#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */
-#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */
-#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */
-#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
-#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
-/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
-#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */
-#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */
-#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */
-#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */
-#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */
-#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */
-#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
-#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
-#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
-#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
-#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
-#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
-#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */
-/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
-/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
-#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */
-#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
-/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
-#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */
-#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */
-#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */
-#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */
-#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */
-#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */
-#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */
-#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */
-#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
-#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
-#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
-/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
-/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TWI
-{
- AT91_REG TWI_CR; /* Control Register */
- AT91_REG TWI_MMR; /* Master Mode Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG TWI_IADR; /* Internal Address Register */
- AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
- AT91_REG Reserved1[ 3 ]; /* */
- AT91_REG TWI_SR; /* Status Register */
- AT91_REG TWI_IER; /* Interrupt Enable Register */
- AT91_REG TWI_IDR; /* Interrupt Disable Register */
- AT91_REG TWI_IMR; /* Interrupt Mask Register */
- AT91_REG TWI_RHR; /* Receive Holding Register */
- AT91_REG TWI_THR; /* Transmit Holding Register */
-} AT91S_TWI, * AT91PS_TWI;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved1[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
-/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
-#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */
-#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */
-#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */
-#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */
-#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
-#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */
-#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */
-#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */
-#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */
-#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */
-#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */
-#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
-#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */
-#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */
-#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
-#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */
-#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */
-#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */
-#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */
-#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */
-#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */
-/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
-/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PWMC_CH
-{
- AT91_REG PWMC_CMR; /* Channel Mode Register */
- AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */
- AT91_REG PWMC_CPRDR; /* Channel Period Register */
- AT91_REG PWMC_CCNTR; /* Channel Counter Register */
- AT91_REG PWMC_CUPDR; /* Channel Update Register */
- AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
-} AT91S_PWMC_CH, * AT91PS_PWMC_CH;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+ AT91_REG PWMC_CMR; // Channel Mode Register
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
+ AT91_REG PWMC_CPRDR; // Channel Period Register
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
+ AT91_REG PWMC_CUPDR; // Channel Update Register
+ AT91_REG PWMC_Reserved[3]; // Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
-#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
-#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */
-#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */
-#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */
-#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
-/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
-#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */
-/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
-#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */
-/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
-#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */
-/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
-#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PWMC
-{
- AT91_REG PWMC_MR; /* PWMC Mode Register */
- AT91_REG PWMC_ENA; /* PWMC Enable Register */
- AT91_REG PWMC_DIS; /* PWMC Disable Register */
- AT91_REG PWMC_SR; /* PWMC Status Register */
- AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */
- AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */
- AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */
- AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */
- AT91_REG Reserved0[ 55 ]; /* */
- AT91_REG PWMC_VR; /* PWMC Version Register */
- AT91_REG Reserved1[ 64 ]; /* */
- AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */
-} AT91S_PWMC, * AT91PS_PWMC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+ AT91_REG PWMC_MR; // PWMC Mode Register
+ AT91_REG PWMC_ENA; // PWMC Enable Register
+ AT91_REG PWMC_DIS; // PWMC Disable Register
+ AT91_REG PWMC_SR; // PWMC Status Register
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
+ AT91_REG Reserved0[55]; //
+ AT91_REG PWMC_VR; // PWMC Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
-/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
-#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */
-#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */
-#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */
-#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
-#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */
-#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */
-/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
-#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
-#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
-#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
-#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
-/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
-/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
-/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
-/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
-/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
-/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR USB Device Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_UDP
-{
- AT91_REG UDP_NUM; /* Frame Number Register */
- AT91_REG UDP_GLBSTATE; /* Global State Register */
- AT91_REG UDP_FADDR; /* Function Address Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG UDP_IER; /* Interrupt Enable Register */
- AT91_REG UDP_IDR; /* Interrupt Disable Register */
- AT91_REG UDP_IMR; /* Interrupt Mask Register */
- AT91_REG UDP_ISR; /* Interrupt Status Register */
- AT91_REG UDP_ICR; /* Interrupt Clear Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG UDP_RSTEP; /* Reset Endpoint Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */
- AT91_REG Reserved3[ 2 ]; /* */
- AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */
- AT91_REG Reserved4[ 3 ]; /* */
- AT91_REG UDP_TXVC; /* Transceiver Control Register */
-} AT91S_UDP, * AT91PS_UDP;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
+ AT91_REG Reserved4[3]; //
+ AT91_REG UDP_TXVC; // Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
-/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
-#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
-#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */
-#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */
-/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
-#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */
-#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */
-#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */
-#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */
-#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */
-/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
-#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */
-#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */
-/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
-#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
-#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */
-#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */
-#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */
-#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */
-#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */
-#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */
-#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */
-#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */
-/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
-/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
-/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
-#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
-/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
-/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
-#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */
-#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */
-#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */
-#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */
-#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */
-#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */
-/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
-#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */
-#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */
-#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */
-#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */
-#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */
-#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
-#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
-#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */
-#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */
-#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */
-#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */
-#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */
-#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */
-#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */
-#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */
-#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */
-#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */
-#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */
-#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
-/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
-#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */
-#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TC
-{
- AT91_REG TC_CCR; /* Channel Control Register */
- AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG TC_CV; /* Counter Value */
- AT91_REG TC_RA; /* Register A */
- AT91_REG TC_RB; /* Register B */
- AT91_REG TC_RC; /* Register C */
- AT91_REG TC_SR; /* Status Register */
- AT91_REG TC_IER; /* Interrupt Enable Register */
- AT91_REG TC_IDR; /* Interrupt Disable Register */
- AT91_REG TC_IMR; /* Interrupt Mask Register */
-} AT91S_TC, * AT91PS_TC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
-/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
-#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */
-#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */
-/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
-#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */
-#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */
-#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */
-#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */
-#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */
-#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */
-#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */
-#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */
-#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */
-#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */
-#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */
-#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */
-#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */
-#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */
-#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */
-#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
-#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
-#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
-#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
-#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
-#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
-#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */
-#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
-#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
-#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
-#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
-#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
-#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
-#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
-#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
-#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
-#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
-#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
-#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
-#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
-#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
-#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
-#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
-#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
-#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
-#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
-#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
-#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
-#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
-#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
-#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
-#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
-#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
-#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
-/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
-#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */
-#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */
-#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */
-#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */
-#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */
-#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */
-#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */
-#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */
-#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
-#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
-#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
-/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
-/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
-/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TCB
-{
- AT91S_TC TCB_TC0; /* TC Channel 0 */
- AT91_REG Reserved0[ 4 ]; /* */
- AT91S_TC TCB_TC1; /* TC Channel 1 */
- AT91_REG Reserved1[ 4 ]; /* */
- AT91S_TC TCB_TC2; /* TC Channel 2 */
- AT91_REG Reserved2[ 4 ]; /* */
- AT91_REG TCB_BCR; /* TC Block Control Register */
- AT91_REG TCB_BMR; /* TC Block Mode Register */
-} AT91S_TCB, * AT91PS_TCB;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
-/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
-#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
-/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
-#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
-#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */
-#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
-#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
-#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
-#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_CAN_MB
-{
- AT91_REG CAN_MB_MMR; /* MailBox Mode Register */
- AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */
- AT91_REG CAN_MB_MID; /* MailBox ID Register */
- AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
- AT91_REG CAN_MB_MSR; /* MailBox Status Register */
- AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */
- AT91_REG CAN_MB_MDH; /* MailBox Data High Register */
- AT91_REG CAN_MB_MCR; /* MailBox Control Register */
-} AT91S_CAN_MB, * AT91PS_CAN_MB;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
+ AT91_REG CAN_MB_MID; // MailBox ID Register
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register
+ AT91_REG CAN_MB_MSR; // MailBox Status Register
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register
+ AT91_REG CAN_MB_MCR; // MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
-/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
-#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */
-#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */
-#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */
-#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */
-/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
-#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
-#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */
-#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */
-/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
-/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
-/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
-#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
-#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */
-#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */
-#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */
-#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */
-#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */
-/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
-/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
-/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
-#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
-#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_CAN
-{
- AT91_REG CAN_MR; /* Mode Register */
- AT91_REG CAN_IER; /* Interrupt Enable Register */
- AT91_REG CAN_IDR; /* Interrupt Disable Register */
- AT91_REG CAN_IMR; /* Interrupt Mask Register */
- AT91_REG CAN_SR; /* Status Register */
- AT91_REG CAN_BR; /* Baudrate Register */
- AT91_REG CAN_TIM; /* Timer Register */
- AT91_REG CAN_TIMESTP; /* Time Stamp Register */
- AT91_REG CAN_ECR; /* Error Counter Register */
- AT91_REG CAN_TCR; /* Transfer Command Register */
- AT91_REG CAN_ACR; /* Abort Command Register */
- AT91_REG Reserved0[ 52 ]; /* */
- AT91_REG CAN_VR; /* Version Register */
- AT91_REG Reserved1[ 64 ]; /* */
- AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */
- AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */
- AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */
- AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */
- AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */
- AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */
- AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */
- AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */
- AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */
- AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */
- AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */
- AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */
- AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */
- AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */
- AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */
- AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */
-} AT91S_CAN, * AT91PS_CAN;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+ AT91_REG CAN_MR; // Mode Register
+ AT91_REG CAN_IER; // Interrupt Enable Register
+ AT91_REG CAN_IDR; // Interrupt Disable Register
+ AT91_REG CAN_IMR; // Interrupt Mask Register
+ AT91_REG CAN_SR; // Status Register
+ AT91_REG CAN_BR; // Baudrate Register
+ AT91_REG CAN_TIM; // Timer Register
+ AT91_REG CAN_TIMESTP; // Time Stamp Register
+ AT91_REG CAN_ECR; // Error Counter Register
+ AT91_REG CAN_TCR; // Transfer Command Register
+ AT91_REG CAN_ACR; // Abort Command Register
+ AT91_REG Reserved0[52]; //
+ AT91_REG CAN_VR; // Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
-/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
-#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */
-#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */
-#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */
-#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */
-#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */
-#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */
-#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */
-#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */
-/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
-#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */
-#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */
-#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */
-#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */
-#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */
-#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */
-#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */
-#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */
-#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */
-#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */
-#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
-#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
-#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
-#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
-#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
-#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
-#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
-#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */
-#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
-#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
-#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */
-#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */
-#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
-#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */
-#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */
-#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */
-#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */
-#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */
-#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */
-/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
-/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
-/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
-#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */
-#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */
-#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */
-/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
-#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */
-#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */
-#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */
-#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */
-#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */
-#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */
-/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
-#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */
-/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
-/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
-#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */
-#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */
-/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
-#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */
-/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
-/* ***************************************************************************** */
-typedef struct _AT91S_EMAC
-{
- AT91_REG EMAC_NCR; /* Network Control Register */
- AT91_REG EMAC_NCFGR; /* Network Configuration Register */
- AT91_REG EMAC_NSR; /* Network Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG EMAC_TSR; /* Transmit Status Register */
- AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
- AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */
- AT91_REG EMAC_RSR; /* Receive Status Register */
- AT91_REG EMAC_ISR; /* Interrupt Status Register */
- AT91_REG EMAC_IER; /* Interrupt Enable Register */
- AT91_REG EMAC_IDR; /* Interrupt Disable Register */
- AT91_REG EMAC_IMR; /* Interrupt Mask Register */
- AT91_REG EMAC_MAN; /* PHY Maintenance Register */
- AT91_REG EMAC_PTR; /* Pause Time Register */
- AT91_REG EMAC_PFR; /* Pause Frames received Register */
- AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */
- AT91_REG EMAC_SCF; /* Single Collision Frame Register */
- AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */
- AT91_REG EMAC_FRO; /* Frames Received OK Register */
- AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */
- AT91_REG EMAC_ALE; /* Alignment Error Register */
- AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */
- AT91_REG EMAC_LCOL; /* Late Collision Register */
- AT91_REG EMAC_ECOL; /* Excessive Collision Register */
- AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
- AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
- AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
- AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
- AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
- AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
- AT91_REG EMAC_RJA; /* Receive Jabbers Register */
- AT91_REG EMAC_USF; /* Undersize Frames Register */
- AT91_REG EMAC_STE; /* SQE Test Error Register */
- AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */
- AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */
- AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */
- AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */
- AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */
- AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */
- AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */
- AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */
- AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */
- AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */
- AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */
- AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */
- AT91_REG EMAC_TID; /* Type ID Checking Register */
- AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */
- AT91_REG EMAC_USRIO; /* USER Input/Output Register */
- AT91_REG EMAC_WOL; /* Wake On LAN Register */
- AT91_REG Reserved1[ 13 ]; /* */
- AT91_REG EMAC_REV; /* Revision Register */
-} AT91S_EMAC, * AT91PS_EMAC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+ AT91_REG EMAC_NCR; // Network Control Register
+ AT91_REG EMAC_NCFGR; // Network Configuration Register
+ AT91_REG EMAC_NSR; // Network Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG EMAC_TSR; // Transmit Status Register
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
+ AT91_REG EMAC_RSR; // Receive Status Register
+ AT91_REG EMAC_ISR; // Interrupt Status Register
+ AT91_REG EMAC_IER; // Interrupt Enable Register
+ AT91_REG EMAC_IDR; // Interrupt Disable Register
+ AT91_REG EMAC_IMR; // Interrupt Mask Register
+ AT91_REG EMAC_MAN; // PHY Maintenance Register
+ AT91_REG EMAC_PTR; // Pause Time Register
+ AT91_REG EMAC_PFR; // Pause Frames received Register
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register
+ AT91_REG EMAC_SCF; // Single Collision Frame Register
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register
+ AT91_REG EMAC_FRO; // Frames Received OK Register
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
+ AT91_REG EMAC_ALE; // Alignment Error Register
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
+ AT91_REG EMAC_LCOL; // Late Collision Register
+ AT91_REG EMAC_ECOL; // Excessive Collision Register
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register
+ AT91_REG EMAC_RJA; // Receive Jabbers Register
+ AT91_REG EMAC_USF; // Undersize Frames Register
+ AT91_REG EMAC_STE; // SQE Test Error Register
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
+ AT91_REG EMAC_TID; // Type ID Checking Register
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
+ AT91_REG EMAC_USRIO; // USER Input/Output Register
+ AT91_REG EMAC_WOL; // Wake On LAN Register
+ AT91_REG Reserved1[13]; //
+ AT91_REG EMAC_REV; // Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
-/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */
-#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */
-#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */
-#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */
-#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */
-#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
-/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
-#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */
-#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */
-#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
-#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
-#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
-#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */
-#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
-/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
-#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
-#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */
-#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */
-#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
-/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
-#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */
-#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */
-#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
-#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */
-#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */
-#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */
-#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
-/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */
-#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */
-#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */
-#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */
-#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */
-/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
-#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */
-/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
-#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */
-#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */
-#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */
-#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */
-/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
-#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */
+// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
-/* ***************************************************************************** */
-typedef struct _AT91S_ADC
-{
- AT91_REG ADC_CR; /* ADC Control Register */
- AT91_REG ADC_MR; /* ADC Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG ADC_CHER; /* ADC Channel Enable Register */
- AT91_REG ADC_CHDR; /* ADC Channel Disable Register */
- AT91_REG ADC_CHSR; /* ADC Channel Status Register */
- AT91_REG ADC_SR; /* ADC Status Register */
- AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */
- AT91_REG ADC_IER; /* ADC Interrupt Enable Register */
- AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */
- AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */
- AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */
- AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */
- AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */
- AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */
- AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */
- AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */
- AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */
- AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */
- AT91_REG Reserved1[ 44 ]; /* */
- AT91_REG ADC_RPR; /* Receive Pointer Register */
- AT91_REG ADC_RCR; /* Receive Counter Register */
- AT91_REG ADC_TPR; /* Transmit Pointer Register */
- AT91_REG ADC_TCR; /* Transmit Counter Register */
- AT91_REG ADC_RNPR; /* Receive Next Pointer Register */
- AT91_REG ADC_RNCR; /* Receive Next Counter Register */
- AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG ADC_TNCR; /* Transmit Next Counter Register */
- AT91_REG ADC_PTCR; /* PDC Transfer Control Register */
- AT91_REG ADC_PTSR; /* PDC Transfer Status Register */
-} AT91S_ADC, * AT91PS_ADC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+ AT91_REG ADC_CR; // ADC Control Register
+ AT91_REG ADC_MR; // ADC Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
+ AT91_REG ADC_SR; // ADC Status Register
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
+ AT91_REG Reserved1[44]; //
+ AT91_REG ADC_RPR; // Receive Pointer Register
+ AT91_REG ADC_RCR; // Receive Counter Register
+ AT91_REG ADC_TPR; // Transmit Pointer Register
+ AT91_REG ADC_TCR; // Transmit Counter Register
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
-/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
-#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */
-#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */
-/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
-#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */
-#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software */
-#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
-#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */
-#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */
-#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */
-#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */
-#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */
-#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */
-#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */
-#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */
-#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */
-#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */
-#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */
-#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */
-#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */
-#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
-#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */
-/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
-#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */
-#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */
-#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */
-#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */
-#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */
-#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */
-#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */
-#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */
-/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
-/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
-/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
-#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */
-#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */
-#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */
-#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */
-/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
-#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
-/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
-/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
-/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
-/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
-#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */
-/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
-/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
-/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
-/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
-/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
-/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
-/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
-/* ***************************************************************************** */
-typedef struct _AT91S_AES
-{
- AT91_REG AES_CR; /* Control Register */
- AT91_REG AES_MR; /* Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AES_IER; /* Interrupt Enable Register */
- AT91_REG AES_IDR; /* Interrupt Disable Register */
- AT91_REG AES_IMR; /* Interrupt Mask Register */
- AT91_REG AES_ISR; /* Interrupt Status Register */
- AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */
- AT91_REG Reserved1[ 4 ]; /* */
- AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */
- AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */
- AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */
- AT91_REG Reserved2[ 35 ]; /* */
- AT91_REG AES_VR; /* AES Version Register */
- AT91_REG AES_RPR; /* Receive Pointer Register */
- AT91_REG AES_RCR; /* Receive Counter Register */
- AT91_REG AES_TPR; /* Transmit Pointer Register */
- AT91_REG AES_TCR; /* Transmit Counter Register */
- AT91_REG AES_RNPR; /* Receive Next Pointer Register */
- AT91_REG AES_RNCR; /* Receive Next Counter Register */
- AT91_REG AES_TNPR; /* Transmit Next Pointer Register */
- AT91_REG AES_TNCR; /* Transmit Next Counter Register */
- AT91_REG AES_PTCR; /* PDC Transfer Control Register */
- AT91_REG AES_PTSR; /* PDC Transfer Status Register */
-} AT91S_AES, * AT91PS_AES;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+ AT91_REG AES_CR; // Control Register
+ AT91_REG AES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AES_IER; // Interrupt Enable Register
+ AT91_REG AES_IDR; // Interrupt Disable Register
+ AT91_REG AES_IMR; // Interrupt Mask Register
+ AT91_REG AES_ISR; // Interrupt Status Register
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register
+ AT91_REG Reserved1[4]; //
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register
+ AT91_REG Reserved2[35]; //
+ AT91_REG AES_VR; // AES Version Register
+ AT91_REG AES_RPR; // Receive Pointer Register
+ AT91_REG AES_RCR; // Receive Counter Register
+ AT91_REG AES_TPR; // Transmit Pointer Register
+ AT91_REG AES_TCR; // Transmit Counter Register
+ AT91_REG AES_RNPR; // Receive Next Pointer Register
+ AT91_REG AES_RNCR; // Receive Next Counter Register
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register
+ AT91_REG AES_TNCR; // Transmit Next Counter Register
+ AT91_REG AES_PTCR; // PDC Transfer Control Register
+ AT91_REG AES_PTSR; // PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
-/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
-#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */
-#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */
-#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */
-/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
-#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */
-#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */
-#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */
-#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
-#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
-#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */
-#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */
-#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */
-#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */
-#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */
-#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */
-#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */
-#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */
-#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */
-#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */
-#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */
-#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */
-#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */
-#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */
-#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */
-#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */
-#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */
-#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */
-#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */
-#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */
-#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
-/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */
-#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */
-#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */
-#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */
-#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */
-#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */
-/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
-#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
-#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
-#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
-#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
-#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
-#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */
+// -------- AES_CR : (AES Offset: 0x0) Control Register --------
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
-/* ***************************************************************************** */
-typedef struct _AT91S_TDES
-{
- AT91_REG TDES_CR; /* Control Register */
- AT91_REG TDES_MR; /* Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG TDES_IER; /* Interrupt Enable Register */
- AT91_REG TDES_IDR; /* Interrupt Disable Register */
- AT91_REG TDES_IMR; /* Interrupt Mask Register */
- AT91_REG TDES_ISR; /* Interrupt Status Register */
- AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */
- AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */
- AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */
- AT91_REG Reserved1[ 2 ]; /* */
- AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */
- AT91_REG Reserved2[ 2 ]; /* */
- AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */
- AT91_REG Reserved3[ 2 ]; /* */
- AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */
- AT91_REG Reserved4[ 37 ]; /* */
- AT91_REG TDES_VR; /* TDES Version Register */
- AT91_REG TDES_RPR; /* Receive Pointer Register */
- AT91_REG TDES_RCR; /* Receive Counter Register */
- AT91_REG TDES_TPR; /* Transmit Pointer Register */
- AT91_REG TDES_TCR; /* Transmit Counter Register */
- AT91_REG TDES_RNPR; /* Receive Next Pointer Register */
- AT91_REG TDES_RNCR; /* Receive Next Counter Register */
- AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */
- AT91_REG TDES_TNCR; /* Transmit Next Counter Register */
- AT91_REG TDES_PTCR; /* PDC Transfer Control Register */
- AT91_REG TDES_PTSR; /* PDC Transfer Status Register */
-} AT91S_TDES, * AT91PS_TDES;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+ AT91_REG TDES_CR; // Control Register
+ AT91_REG TDES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG TDES_IER; // Interrupt Enable Register
+ AT91_REG TDES_IDR; // Interrupt Disable Register
+ AT91_REG TDES_IMR; // Interrupt Mask Register
+ AT91_REG TDES_ISR; // Interrupt Status Register
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
+ AT91_REG Reserved4[37]; //
+ AT91_REG TDES_VR; // TDES Version Register
+ AT91_REG TDES_RPR; // Receive Pointer Register
+ AT91_REG TDES_RCR; // Receive Counter Register
+ AT91_REG TDES_TPR; // Transmit Pointer Register
+ AT91_REG TDES_TCR; // Transmit Counter Register
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register
+ AT91_REG TDES_RNCR; // Receive Next Counter Register
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
-/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
-#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */
-#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */
-/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
-#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */
-#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */
-#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */
-#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */
-#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
-#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
-#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */
-#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */
-#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
-#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
-#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
-#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
-#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */
-#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
-#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */
-#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */
-#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */
-#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */
-/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */
-#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */
-#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */
-#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */
-#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */
-#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */
-/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
-#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
-#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
-#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
-#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-/* ***************************************************************************** */
-/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-/* ========== Register definition for SYS peripheral ========== */
-/* ========== Register definition for AIC peripheral ========== */
-#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
-#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
-#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
-#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
-#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
-#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
-#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
-#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
-#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
-#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
-#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
-#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
-#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
-#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
-#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
-#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
-#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
-#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
-/* ========== Register definition for PDC_DBGU peripheral ========== */
-#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
-#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
-#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
-#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
-#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
-#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
-#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
-#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
-#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
-#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
-/* ========== Register definition for DBGU peripheral ========== */
-#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
-#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
-#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
-#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
-#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */
-#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
-#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
-#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
-#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
-#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
-#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
-#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
-/* ========== Register definition for PIOA peripheral ========== */
-#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
-#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
-#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
-#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
-#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
-#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
-#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
-#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
-#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
-#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
-#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
-#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
-#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
-#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
-#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
-#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
-#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
-#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
-#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
-#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
-#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
-#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
-#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
-#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
-#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
-#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
-#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
-/* ========== Register definition for PIOB peripheral ========== */
-#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
-#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
-#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
-#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
-#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */
-#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
-#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */
-#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
-#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
-#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
-#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
-#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
-#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
-#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
-#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
-#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
-#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
-#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
-#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
-#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
-#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
-#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */
-#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
-#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
-#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */
-#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
-#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */
-#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
-/* ========== Register definition for CKGR peripheral ========== */
-#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
-#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
-#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */
-/* ========== Register definition for PMC peripheral ========== */
-#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
-#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
-#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
-#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
-#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
-#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
-#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
-#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
-#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
-#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */
-#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
-#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
-#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
-#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
-/* ========== Register definition for RSTC peripheral ========== */
-#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
-#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
-#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
-/* ========== Register definition for RTTC peripheral ========== */
-#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
-#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
-#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
-#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
-/* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
-#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
-#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
-#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
-/* ========== Register definition for WDTC peripheral ========== */
-#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
-#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
-#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
-/* ========== Register definition for VREG peripheral ========== */
-#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
-/* ========== Register definition for MC peripheral ========== */
-#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
-#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
-#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
-#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
-#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
-#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
-/* ========== Register definition for PDC_SPI1 peripheral ========== */
-#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
-#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
-#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
-#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
-#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
-#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
-#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
-#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
-#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
-#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
-/* ========== Register definition for SPI1 peripheral ========== */
-#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
-#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
-#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */
-#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */
-#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
-#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */
-#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */
-#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */
-#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */
-/* ========== Register definition for PDC_SPI0 peripheral ========== */
-#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
-#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
-#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
-#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
-#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
-#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
-#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
-#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
-#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
-#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
-/* ========== Register definition for SPI0 peripheral ========== */
-#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
-#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */
-#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
-#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */
-#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */
-#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
-#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */
-#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */
-#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */
-/* ========== Register definition for PDC_US1 peripheral ========== */
-#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
-#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
-#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
-#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
-#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
-#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
-#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
-#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
-#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
-#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
-/* ========== Register definition for US1 peripheral ========== */
-#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
-#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
-#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
-#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
-#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
-#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
-#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
-#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
-#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
-#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
-#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
-#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
-#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
-#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
-/* ========== Register definition for PDC_US0 peripheral ========== */
-#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
-#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
-#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
-#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
-#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
-#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
-#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
-#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
-#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
-#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
-/* ========== Register definition for US0 peripheral ========== */
-#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
-#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
-#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
-#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
-#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
-#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
-#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
-#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
-#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
-#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
-#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
-#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
-#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
-#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
-/* ========== Register definition for PDC_SSC peripheral ========== */
-#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
-#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
-#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
-#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
-#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
-#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
-#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
-#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
-#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
-#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
-/* ========== Register definition for SSC peripheral ========== */
-#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
-#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
-#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
-#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
-#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
-#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
-#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
-#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
-#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
-#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
-#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
-#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
-#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
-#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
-/* ========== Register definition for TWI peripheral ========== */
-#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
-#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
-#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
-#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
-#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
-#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
-#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
-#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
-#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
-#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
-/* ========== Register definition for PWMC_CH3 peripheral ========== */
-#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
-#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
-#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
-#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
-#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
-/* ========== Register definition for PWMC_CH2 peripheral ========== */
-#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
-#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
-#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
-#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
-#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
-#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH1 peripheral ========== */
-#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
-#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
-#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
-#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
-#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
-/* ========== Register definition for PWMC_CH0 peripheral ========== */
-#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
-#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
-#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
-#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
-#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
-/* ========== Register definition for PWMC peripheral ========== */
-#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
-#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
-#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
-#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
-#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
-#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
-#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
-#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
-#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
-/* ========== Register definition for UDP peripheral ========== */
-#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
-#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
-#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
-#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
-#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
-#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
-#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
-#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
-#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
-#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
-#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
-#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
-/* ========== Register definition for TC0 peripheral ========== */
-#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
-#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
-#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
-#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
-#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
-#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
-#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
-#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
-#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
-/* ========== Register definition for TC1 peripheral ========== */
-#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
-#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
-#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
-#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
-#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
-#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
-#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
-#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
-#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
-/* ========== Register definition for TC2 peripheral ========== */
-#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
-#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
-#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
-#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
-#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
-#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
-#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
-#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
-#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
-/* ========== Register definition for TCB peripheral ========== */
-#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
-#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
-/* ========== Register definition for CAN_MB0 peripheral ========== */
-#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
-#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
-#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
-#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
-#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
-#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
-#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
-/* ========== Register definition for CAN_MB1 peripheral ========== */
-#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
-#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
-#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
-#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
-#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
-#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
-#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
-/* ========== Register definition for CAN_MB2 peripheral ========== */
-#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
-#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
-#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
-#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
-#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
-#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
-#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
-/* ========== Register definition for CAN_MB3 peripheral ========== */
-#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
-#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
-#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
-#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
-#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
-#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
-#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
-/* ========== Register definition for CAN_MB4 peripheral ========== */
-#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
-#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
-#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
-#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
-#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
-#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
-#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
-#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB5 peripheral ========== */
-#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
-#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
-#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
-#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
-#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
-#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
-#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
-#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB6 peripheral ========== */
-#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
-#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
-#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
-#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
-#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
-#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
-#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
-/* ========== Register definition for CAN_MB7 peripheral ========== */
-#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
-#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
-#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
-#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
-#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
-#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
-#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
-/* ========== Register definition for CAN peripheral ========== */
-#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */
-#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
-#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
-#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */
-#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */
-#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */
-#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
-#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */
-#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */
-#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */
-#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */
-#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */
-/* ========== Register definition for EMAC peripheral ========== */
-#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
-#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
-#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
-#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
-#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */
-#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
-#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
-#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
-#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
-#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */
-#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
-#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */
-#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
-#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
-#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
-#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
-#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
-#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
-#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
-#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
-#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
-#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */
-#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
-#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
-#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
-#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
-#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
-#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
-#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
-#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
-#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
-#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
-#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
-#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
-#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
-#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */
-#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
-#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
-#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
-#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
-#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */
-#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
-#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
-#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
-#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
-#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
-#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
-#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
-/* ========== Register definition for PDC_ADC peripheral ========== */
-#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
-#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
-#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
-#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
-#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
-#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
-#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
-#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
-#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
-#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
-/* ========== Register definition for ADC peripheral ========== */
-#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
-#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
-#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
-#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
-#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
-#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
-#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
-#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
-#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
-#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
-#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
-#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
-#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
-#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
-#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
-#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
-#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
-#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
-/* ========== Register definition for PDC_AES peripheral ========== */
-#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
-#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
-#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
-#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
-#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
-#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
-#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
-#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
-#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
-#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
-/* ========== Register definition for AES peripheral ========== */
-#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
-#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */
-#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */
-#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */
-#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */
-#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */
-#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
-#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
-#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
-#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */
-#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */
-/* ========== Register definition for PDC_TDES peripheral ========== */
-#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
-#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
-#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
-#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
-#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
-#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
-#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
-#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
-#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
-#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
-/* ========== Register definition for TDES peripheral ========== */
-#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
-#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
-#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
-#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */
-#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
-#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */
-#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
-#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */
-#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */
-#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
-#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */
-#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */
-#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ==========
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ==========
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ==========
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ==========
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ==========
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ==========
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ==========
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ==========
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ==========
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ==========
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ==========
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ==========
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ==========
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ==========
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ==========
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ==========
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ==========
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ==========
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
-/* ***************************************************************************** */
-/* PIO DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */
-#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */
-#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */
-#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */
-#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */
-#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */
-#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */
-#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */
-#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */
-#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */
-#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */
-#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */
-#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */
-#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */
-#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */
-#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */
-#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */
-#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */
-#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */
-#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */
-#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */
-#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */
-#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */
-#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */
-#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */
-#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */
-#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */
-#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */
-#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */
-#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */
-#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */
-#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */
-#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */
-#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */
-#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */
-#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */
-#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */
-#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */
-#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */
-#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */
-#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */
-#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */
-#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */
-#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */
-#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */
-#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */
-#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */
-#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */
-#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */
-#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */
-#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */
-#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */
-#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */
-#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */
-#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */
-#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */
-#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */
-#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */
-#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */
-#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */
-#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */
-#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */
-#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */
-#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */
-#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */
-#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */
-#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */
-#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */
-#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */
-#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */
-#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */
-#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */
-#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */
-#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */
-#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */
-#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */
-#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */
-#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */
-#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */
-#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */
-#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */
-#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */
-#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */
-#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */
-#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */
-#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */
-#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */
-#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */
-#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */
-#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */
-#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */
-#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */
-#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */
-#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */
-#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */
-#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */
-#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */
-#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */
-#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */
-#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */
-#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */
-#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */
-#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */
-#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */
-#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */
-#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */
-#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */
-#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */
-#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */
-#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */
-#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */
-#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */
-#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */
-#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */
-#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */
-#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */
-#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */
-#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */
-#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */
-#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */
-#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */
-#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */
-#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */
-#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */
-#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-/* ***************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */
-#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */
-#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */
-#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */
-#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */
-#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */
-#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */
-#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */
-#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */
-#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */
-#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */
-#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */
-#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */
-#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */
-#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */
-#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */
-#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */
-#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */
-#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */
-#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */
-#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */
-#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */
-#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */
-#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */
-#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */
-#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */
-#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */
-#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */
-#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */
-#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-/* ***************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */
-#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */
-#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */
-#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */
-#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */
-#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */
-#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */
-#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */
-#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */
-#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */
-#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */
-#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */
-#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */
-#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */
-#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */
-#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */
-#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */
-#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */
-#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */
-#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */
-#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */
-#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */
-#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */
-#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */
-#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */
-#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
-#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
-#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
-#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
-#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */
-#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */
-#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */
-#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */
-#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */
-#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */
-#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */
-#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */
-#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */
-#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */
-#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */
-#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */
-#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */
-#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */
-#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */
-#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */
-#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */
-#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */
-#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */
-#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */
-#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */
-#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
-/* ***************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */
-#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */
-#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */
-#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
-#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \
- { \
- unsigned int mask; \
- \
- mask = 0x1 << irq_id; \
- /* Disable the interrupt on the interrupt controller */ \
- AT91C_BASE_AIC->AIC_IDCR = mask; \
- /* Save the interrupt handler routine pointer and the interrupt priority */ \
- AT91C_BASE_AIC->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; \
- /* Store the Source Mode Register */ \
- AT91C_BASE_AIC->AIC_SMR[ irq_id ] = src_type | priority; \
- /* Clear the interrupt on the interrupt controller */ \
- AT91C_BASE_AIC->AIC_ICCR = mask; \
- }
+#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \
+{ \
+ unsigned int mask ; \
+ \
+ mask = 0x1 << irq_id; \
+ /* Disable the interrupt on the interrupt controller */ \
+ AT91C_BASE_AIC->AIC_IDCR = mask ; \
+ /* Save the interrupt handler routine pointer and the interrupt priority */ \
+ AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \
+ /* Store the Source Mode Register */ \
+ AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority ; \
+ /* Clear the interrupt on the interrupt controller */ \
+ AT91C_BASE_AIC->AIC_ICCR = mask ; \
+}
-#endif /* ifndef AT91SAM7X256_H */
+#endif
diff --git a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
index 6548782..8ea721e 100644
--- a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
@@ -1,6346 +1,4697 @@
-/* - ---------------------------------------------------------------------------- */
-/* - ATMEL Microcontroller Software Support - ROUSSET - */
-/* - ---------------------------------------------------------------------------- */
-/* - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/* - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/* - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/* - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/* - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/* - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/* - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/* - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/* - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* - ---------------------------------------------------------------------------- */
-/* - File Name : AT91SAM7X256.h */
-/* - Object : AT91SAM7X256 definitions */
-/* - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */
-/* - */
-/* - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */
-/* - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */
-/* - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
-/* - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */
-/* - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */
-/* - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
-/* - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
-/* - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
-/* - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */
-/* - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */
-/* - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */
-/* - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */
-/* - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */
-/* - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */
-/* - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
-/* - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
-/* - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
-/* - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
-/* - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
-/* - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
-/* - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */
-/* - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */
-/* - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
-/* - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */
-/* - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
-/* - ---------------------------------------------------------------------------- */
+// - ----------------------------------------------------------------------------
+// - ATMEL Microcontroller Software Support - ROUSSET -
+// - ----------------------------------------------------------------------------
+// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// - ----------------------------------------------------------------------------
+// - File Name : AT91SAM7X256.h
+// - Object : AT91SAM7X256 definitions
+// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+// -
+// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
+// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
+// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
+// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
+// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
+// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
+// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// - ----------------------------------------------------------------------------
#ifndef AT91SAM7X256_H
#define AT91SAM7X256_H
-typedef volatile unsigned int AT91_REG; /* Hardware register definition */
+typedef volatile unsigned int AT91_REG;// Hardware register definition
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR System Peripherals */
-/* ***************************************************************************** */
-typedef struct _AT91S_SYS
-{
- AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
- AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
- AT91_REG AIC_IVR; /* IRQ Vector Register */
- AT91_REG AIC_FVR; /* FIQ Vector Register */
- AT91_REG AIC_ISR; /* Interrupt Status Register */
- AT91_REG AIC_IPR; /* Interrupt Pending Register */
- AT91_REG AIC_IMR; /* Interrupt Mask Register */
- AT91_REG AIC_CISR; /* Core Interrupt Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
- AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
- AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
- AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
- AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
- AT91_REG AIC_SPU; /* Spurious Vector Register */
- AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
- AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
- AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
- AT91_REG Reserved2[ 45 ]; /* */
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved3[ 7 ]; /* */
- AT91_REG DBGU_CIDR; /* Chip ID Register */
- AT91_REG DBGU_EXID; /* Chip ID Extension Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved4[ 45 ]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
- AT91_REG Reserved5[ 54 ]; /* */
- AT91_REG PIOA_PER; /* PIO Enable Register */
- AT91_REG PIOA_PDR; /* PIO Disable Register */
- AT91_REG PIOA_PSR; /* PIO Status Register */
- AT91_REG Reserved6[ 1 ]; /* */
- AT91_REG PIOA_OER; /* Output Enable Register */
- AT91_REG PIOA_ODR; /* Output Disable Registerr */
- AT91_REG PIOA_OSR; /* Output Status Register */
- AT91_REG Reserved7[ 1 ]; /* */
- AT91_REG PIOA_IFER; /* Input Filter Enable Register */
- AT91_REG PIOA_IFDR; /* Input Filter Disable Register */
- AT91_REG PIOA_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved8[ 1 ]; /* */
- AT91_REG PIOA_SODR; /* Set Output Data Register */
- AT91_REG PIOA_CODR; /* Clear Output Data Register */
- AT91_REG PIOA_ODSR; /* Output Data Status Register */
- AT91_REG PIOA_PDSR; /* Pin Data Status Register */
- AT91_REG PIOA_IER; /* Interrupt Enable Register */
- AT91_REG PIOA_IDR; /* Interrupt Disable Register */
- AT91_REG PIOA_IMR; /* Interrupt Mask Register */
- AT91_REG PIOA_ISR; /* Interrupt Status Register */
- AT91_REG PIOA_MDER; /* Multi-driver Enable Register */
- AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIOA_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved9[ 1 ]; /* */
- AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIOA_PPUER; /* Pull-up Enable Register */
- AT91_REG PIOA_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved10[ 1 ]; /* */
- AT91_REG PIOA_ASR; /* Select A Register */
- AT91_REG PIOA_BSR; /* Select B Register */
- AT91_REG PIOA_ABSR; /* AB Select Status Register */
- AT91_REG Reserved11[ 9 ]; /* */
- AT91_REG PIOA_OWER; /* Output Write Enable Register */
- AT91_REG PIOA_OWDR; /* Output Write Disable Register */
- AT91_REG PIOA_OWSR; /* Output Write Status Register */
- AT91_REG Reserved12[ 85 ]; /* */
- AT91_REG PIOB_PER; /* PIO Enable Register */
- AT91_REG PIOB_PDR; /* PIO Disable Register */
- AT91_REG PIOB_PSR; /* PIO Status Register */
- AT91_REG Reserved13[ 1 ]; /* */
- AT91_REG PIOB_OER; /* Output Enable Register */
- AT91_REG PIOB_ODR; /* Output Disable Registerr */
- AT91_REG PIOB_OSR; /* Output Status Register */
- AT91_REG Reserved14[ 1 ]; /* */
- AT91_REG PIOB_IFER; /* Input Filter Enable Register */
- AT91_REG PIOB_IFDR; /* Input Filter Disable Register */
- AT91_REG PIOB_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved15[ 1 ]; /* */
- AT91_REG PIOB_SODR; /* Set Output Data Register */
- AT91_REG PIOB_CODR; /* Clear Output Data Register */
- AT91_REG PIOB_ODSR; /* Output Data Status Register */
- AT91_REG PIOB_PDSR; /* Pin Data Status Register */
- AT91_REG PIOB_IER; /* Interrupt Enable Register */
- AT91_REG PIOB_IDR; /* Interrupt Disable Register */
- AT91_REG PIOB_IMR; /* Interrupt Mask Register */
- AT91_REG PIOB_ISR; /* Interrupt Status Register */
- AT91_REG PIOB_MDER; /* Multi-driver Enable Register */
- AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIOB_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved16[ 1 ]; /* */
- AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIOB_PPUER; /* Pull-up Enable Register */
- AT91_REG PIOB_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved17[ 1 ]; /* */
- AT91_REG PIOB_ASR; /* Select A Register */
- AT91_REG PIOB_BSR; /* Select B Register */
- AT91_REG PIOB_ABSR; /* AB Select Status Register */
- AT91_REG Reserved18[ 9 ]; /* */
- AT91_REG PIOB_OWER; /* Output Write Enable Register */
- AT91_REG PIOB_OWDR; /* Output Write Disable Register */
- AT91_REG PIOB_OWSR; /* Output Write Status Register */
- AT91_REG Reserved19[ 341 ]; /* */
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved20[ 1 ]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved21[ 1 ]; /* */
- AT91_REG PMC_MOR; /* Main Oscillator Register */
- AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved22[ 1 ]; /* */
- AT91_REG PMC_PLLR; /* PLL Register */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved23[ 3 ]; /* */
- AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */
- AT91_REG Reserved24[ 4 ]; /* */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved25[ 36 ]; /* */
- AT91_REG RSTC_RCR; /* Reset Control Register */
- AT91_REG RSTC_RSR; /* Reset Status Register */
- AT91_REG RSTC_RMR; /* Reset Mode Register */
- AT91_REG Reserved26[ 5 ]; /* */
- AT91_REG RTTC_RTMR; /* Real-time Mode Register */
- AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
- AT91_REG RTTC_RTVR; /* Real-time Value Register */
- AT91_REG RTTC_RTSR; /* Real-time Status Register */
- AT91_REG PITC_PIMR; /* Period Interval Mode Register */
- AT91_REG PITC_PISR; /* Period Interval Status Register */
- AT91_REG PITC_PIVR; /* Period Interval Value Register */
- AT91_REG PITC_PIIR; /* Period Interval Image Register */
- AT91_REG WDTC_WDCR; /* Watchdog Control Register */
- AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
- AT91_REG WDTC_WDSR; /* Watchdog Status Register */
- AT91_REG Reserved27[ 5 ]; /* */
- AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
-} AT91S_SYS, * AT91PS_SYS;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved2[45]; //
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved3[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved4[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved5[54]; //
+ AT91_REG PIOA_PER; // PIO Enable Register
+ AT91_REG PIOA_PDR; // PIO Disable Register
+ AT91_REG PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved6[1]; //
+ AT91_REG PIOA_OER; // Output Enable Register
+ AT91_REG PIOA_ODR; // Output Disable Registerr
+ AT91_REG PIOA_OSR; // Output Status Register
+ AT91_REG Reserved7[1]; //
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved8[1]; //
+ AT91_REG PIOA_SODR; // Set Output Data Register
+ AT91_REG PIOA_CODR; // Clear Output Data Register
+ AT91_REG PIOA_ODSR; // Output Data Status Register
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
+ AT91_REG PIOA_IER; // Interrupt Enable Register
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
+ AT91_REG PIOA_ISR; // Interrupt Status Register
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved9[1]; //
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved10[1]; //
+ AT91_REG PIOA_ASR; // Select A Register
+ AT91_REG PIOA_BSR; // Select B Register
+ AT91_REG PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved11[9]; //
+ AT91_REG PIOA_OWER; // Output Write Enable Register
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
+ AT91_REG PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved12[85]; //
+ AT91_REG PIOB_PER; // PIO Enable Register
+ AT91_REG PIOB_PDR; // PIO Disable Register
+ AT91_REG PIOB_PSR; // PIO Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG PIOB_OER; // Output Enable Register
+ AT91_REG PIOB_ODR; // Output Disable Registerr
+ AT91_REG PIOB_OSR; // Output Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG PIOB_IFER; // Input Filter Enable Register
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register
+ AT91_REG PIOB_IFSR; // Input Filter Status Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG PIOB_SODR; // Set Output Data Register
+ AT91_REG PIOB_CODR; // Clear Output Data Register
+ AT91_REG PIOB_ODSR; // Output Data Status Register
+ AT91_REG PIOB_PDSR; // Pin Data Status Register
+ AT91_REG PIOB_IER; // Interrupt Enable Register
+ AT91_REG PIOB_IDR; // Interrupt Disable Register
+ AT91_REG PIOB_IMR; // Interrupt Mask Register
+ AT91_REG PIOB_ISR; // Interrupt Status Register
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved16[1]; //
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved17[1]; //
+ AT91_REG PIOB_ASR; // Select A Register
+ AT91_REG PIOB_BSR; // Select B Register
+ AT91_REG PIOB_ABSR; // AB Select Status Register
+ AT91_REG Reserved18[9]; //
+ AT91_REG PIOB_OWER; // Output Write Enable Register
+ AT91_REG PIOB_OWDR; // Output Write Disable Register
+ AT91_REG PIOB_OWSR; // Output Write Status Register
+ AT91_REG Reserved19[341]; //
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved20[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved21[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved22[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved23[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved24[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved25[36]; //
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved26[5]; //
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved27[5]; //
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_AIC
-{
- AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
- AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
- AT91_REG AIC_IVR; /* IRQ Vector Register */
- AT91_REG AIC_FVR; /* FIQ Vector Register */
- AT91_REG AIC_ISR; /* Interrupt Status Register */
- AT91_REG AIC_IPR; /* Interrupt Pending Register */
- AT91_REG AIC_IMR; /* Interrupt Mask Register */
- AT91_REG AIC_CISR; /* Core Interrupt Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
- AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
- AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
- AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
- AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
- AT91_REG AIC_SPU; /* Spurious Vector Register */
- AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
- AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
- AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
-} AT91S_AIC, * AT91PS_AIC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
-/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
-#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
-#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */
-#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */
-#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
-/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
-#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
-#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
-/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
-#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
-#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_PDC
-{
- AT91_REG PDC_RPR; /* Receive Pointer Register */
- AT91_REG PDC_RCR; /* Receive Counter Register */
- AT91_REG PDC_TPR; /* Transmit Pointer Register */
- AT91_REG PDC_TCR; /* Transmit Counter Register */
- AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
- AT91_REG PDC_RNCR; /* Receive Next Counter Register */
- AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
- AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
- AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
-} AT91S_PDC, * AT91PS_PDC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/* ***************************************************************************** */
-typedef struct _AT91S_DBGU
-{
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved0[ 7 ]; /* */
- AT91_REG DBGU_CIDR; /* Chip ID Register */
- AT91_REG DBGU_EXID; /* Chip ID Extension Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved1[ 45 ]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
-} AT91S_DBGU, * AT91PS_DBGU;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */
-#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */
-/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */
-#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */
-#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */
-#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */
-#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */
-#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
-#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
-#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
-#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
-#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
-/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
-/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
-#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PIO
-{
- AT91_REG PIO_PER; /* PIO Enable Register */
- AT91_REG PIO_PDR; /* PIO Disable Register */
- AT91_REG PIO_PSR; /* PIO Status Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG PIO_OER; /* Output Enable Register */
- AT91_REG PIO_ODR; /* Output Disable Registerr */
- AT91_REG PIO_OSR; /* Output Status Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG PIO_IFER; /* Input Filter Enable Register */
- AT91_REG PIO_IFDR; /* Input Filter Disable Register */
- AT91_REG PIO_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG PIO_SODR; /* Set Output Data Register */
- AT91_REG PIO_CODR; /* Clear Output Data Register */
- AT91_REG PIO_ODSR; /* Output Data Status Register */
- AT91_REG PIO_PDSR; /* Pin Data Status Register */
- AT91_REG PIO_IER; /* Interrupt Enable Register */
- AT91_REG PIO_IDR; /* Interrupt Disable Register */
- AT91_REG PIO_IMR; /* Interrupt Mask Register */
- AT91_REG PIO_ISR; /* Interrupt Status Register */
- AT91_REG PIO_MDER; /* Multi-driver Enable Register */
- AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIO_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved3[ 1 ]; /* */
- AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIO_PPUER; /* Pull-up Enable Register */
- AT91_REG PIO_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved4[ 1 ]; /* */
- AT91_REG PIO_ASR; /* Select A Register */
- AT91_REG PIO_BSR; /* Select B Register */
- AT91_REG PIO_ABSR; /* AB Select Status Register */
- AT91_REG Reserved5[ 9 ]; /* */
- AT91_REG PIO_OWER; /* Output Write Enable Register */
- AT91_REG PIO_OWDR; /* Output Write Disable Register */
- AT91_REG PIO_OWSR; /* Output Write Status Register */
-} AT91S_PIO, * AT91PS_PIO;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_CKGR
-{
- AT91_REG CKGR_MOR; /* Main Oscillator Register */
- AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG CKGR_PLLR; /* PLL Register */
-} AT91S_CKGR, * AT91PS_CKGR;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG CKGR_PLLR; // PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */
-#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */
-/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */
-#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */
-#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
-#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */
-#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */
-#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */
-#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PMC
-{
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG PMC_MOR; /* Main Oscillator Register */
- AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG PMC_PLLR; /* PLL Register */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved3[ 3 ]; /* */
- AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */
- AT91_REG Reserved4[ 4 ]; /* */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
-} AT91S_PMC, * AT91PS_PMC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved3[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved4[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
-/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
-#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
-/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
-/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
-/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
-/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
-/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
-/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
-#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */
-#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
-/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
-/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
-#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
-/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
-/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Reset Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_RSTC
-{
- AT91_REG RSTC_RCR; /* Reset Control Register */
- AT91_REG RSTC_RSR; /* Reset Status Register */
- AT91_REG RSTC_RMR; /* Reset Mode Register */
-} AT91S_RSTC, * AT91PS_RSTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
-/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
-#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */
-#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */
-#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */
-#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
-/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
-#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */
-#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */
-#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */
-#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occured. */
-#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */
-#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */
-#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occured. */
-#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */
-#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */
-/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
-#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */
-#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_RTTC
-{
- AT91_REG RTTC_RTMR; /* Real-time Mode Register */
- AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
- AT91_REG RTTC_RTVR; /* Real-time Value Register */
- AT91_REG RTTC_RTSR; /* Real-time Status Register */
-} AT91S_RTTC, * AT91PS_RTTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
-/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
-#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
-#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */
-#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */
-#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */
-/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
-#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */
-/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
-#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */
-/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
-#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */
-#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PITC
-{
- AT91_REG PITC_PIMR; /* Period Interval Mode Register */
- AT91_REG PITC_PISR; /* Period Interval Status Register */
- AT91_REG PITC_PIVR; /* Period Interval Value Register */
- AT91_REG PITC_PIIR; /* Period Interval Image Register */
-} AT91S_PITC, * AT91PS_PITC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
-/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
-#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
-#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */
-#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */
-/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
-#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */
-/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
-#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
-#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */
-/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_WDTC
-{
- AT91_REG WDTC_WDCR; /* Watchdog Control Register */
- AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
- AT91_REG WDTC_WDSR; /* Watchdog Status Register */
-} AT91S_WDTC, * AT91PS_WDTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
-/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
-#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */
-#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */
-/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
-#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */
-#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */
-#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */
-#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
-#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */
-#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */
-/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
-#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */
-#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_VREG
-{
- AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
-} AT91S_VREG, * AT91PS_VREG;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
-/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
-#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Memory Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_MC
-{
- AT91_REG MC_RCR; /* MC Remap Control Register */
- AT91_REG MC_ASR; /* MC Abort Status Register */
- AT91_REG MC_AASR; /* MC Abort Address Status Register */
- AT91_REG Reserved0[ 21 ]; /* */
- AT91_REG MC_FMR; /* MC Flash Mode Register */
- AT91_REG MC_FCR; /* MC Flash Command Register */
- AT91_REG MC_FSR; /* MC Flash Status Register */
-} AT91S_MC, * AT91PS_MC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved0[21]; //
+ AT91_REG MC_FMR; // MC Flash Mode Register
+ AT91_REG MC_FCR; // MC Flash Command Register
+ AT91_REG MC_FSR; // MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
-/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
-#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
-/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
-#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
-#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
-#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
-#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */
-#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */
-#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */
-#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */
-#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */
-#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */
-#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */
-#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */
-#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */
-/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
-#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */
-#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */
-#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */
-#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */
-#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */
-#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */
-#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */
-#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
-/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
-#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */
-#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */
-#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
-#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
-#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */
-#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */
-#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */
-#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
-#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
-/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
-#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */
-#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */
-#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */
-#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */
-#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */
-#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */
-#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */
-#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */
-#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SPI
-{
- AT91_REG SPI_CR; /* Control Register */
- AT91_REG SPI_MR; /* Mode Register */
- AT91_REG SPI_RDR; /* Receive Data Register */
- AT91_REG SPI_TDR; /* Transmit Data Register */
- AT91_REG SPI_SR; /* Status Register */
- AT91_REG SPI_IER; /* Interrupt Enable Register */
- AT91_REG SPI_IDR; /* Interrupt Disable Register */
- AT91_REG SPI_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved0[ 4 ]; /* */
- AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */
- AT91_REG Reserved1[ 48 ]; /* */
- AT91_REG SPI_RPR; /* Receive Pointer Register */
- AT91_REG SPI_RCR; /* Receive Counter Register */
- AT91_REG SPI_TPR; /* Transmit Pointer Register */
- AT91_REG SPI_TCR; /* Transmit Counter Register */
- AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
- AT91_REG SPI_RNCR; /* Receive Next Counter Register */
- AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
- AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
- AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
-} AT91S_SPI, * AT91PS_SPI;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */
-#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */
-#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */
-#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */
-#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */
-#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */
-#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Usart */
-/* ***************************************************************************** */
-typedef struct _AT91S_USART
-{
- AT91_REG US_CR; /* Control Register */
- AT91_REG US_MR; /* Mode Register */
- AT91_REG US_IER; /* Interrupt Enable Register */
- AT91_REG US_IDR; /* Interrupt Disable Register */
- AT91_REG US_IMR; /* Interrupt Mask Register */
- AT91_REG US_CSR; /* Channel Status Register */
- AT91_REG US_RHR; /* Receiver Holding Register */
- AT91_REG US_THR; /* Transmitter Holding Register */
- AT91_REG US_BRGR; /* Baud Rate Generator Register */
- AT91_REG US_RTOR; /* Receiver Time-out Register */
- AT91_REG US_TTGR; /* Transmitter Time-guard Register */
- AT91_REG Reserved0[ 5 ]; /* */
- AT91_REG US_FIDI; /* FI_DI_Ratio Register */
- AT91_REG US_NER; /* Nb Errors Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG US_IF; /* IRDA_FILTER Register */
- AT91_REG Reserved2[ 44 ]; /* */
- AT91_REG US_RPR; /* Receive Pointer Register */
- AT91_REG US_RCR; /* Receive Counter Register */
- AT91_REG US_TPR; /* Transmit Pointer Register */
- AT91_REG US_TCR; /* Transmit Counter Register */
- AT91_REG US_RNPR; /* Receive Next Pointer Register */
- AT91_REG US_RNCR; /* Receive Next Counter Register */
- AT91_REG US_TNPR; /* Transmit Next Pointer Register */
- AT91_REG US_TNCR; /* Transmit Next Counter Register */
- AT91_REG US_PTCR; /* PDC Transfer Control Register */
- AT91_REG US_PTSR; /* PDC Transfer Status Register */
-} AT91S_USART, * AT91PS_USART;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
-/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */
-#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
-#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
-#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
-#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
-#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
-#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
-#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
-#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
-#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
-#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
-/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */
-#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */
-#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */
-#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */
-#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */
-#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */
-#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */
-#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */
-#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */
-#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */
-#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */
-#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
-#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
-#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
-#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
-#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
-#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
-#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
-#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
-#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
-#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
-/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */
-#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */
-#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
-#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
-#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
-#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
-#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
-#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
-/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
-#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */
-#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */
-#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */
-#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SSC
-{
- AT91_REG SSC_CR; /* Control Register */
- AT91_REG SSC_CMR; /* Clock Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */
- AT91_REG SSC_RFMR; /* Receive Frame Mode Register */
- AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */
- AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */
- AT91_REG SSC_RHR; /* Receive Holding Register */
- AT91_REG SSC_THR; /* Transmit Holding Register */
- AT91_REG Reserved1[ 2 ]; /* */
- AT91_REG SSC_RSHR; /* Receive Sync Holding Register */
- AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */
- AT91_REG Reserved2[ 2 ]; /* */
- AT91_REG SSC_SR; /* Status Register */
- AT91_REG SSC_IER; /* Interrupt Enable Register */
- AT91_REG SSC_IDR; /* Interrupt Disable Register */
- AT91_REG SSC_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved3[ 44 ]; /* */
- AT91_REG SSC_RPR; /* Receive Pointer Register */
- AT91_REG SSC_RCR; /* Receive Counter Register */
- AT91_REG SSC_TPR; /* Transmit Pointer Register */
- AT91_REG SSC_TCR; /* Transmit Counter Register */
- AT91_REG SSC_RNPR; /* Receive Next Pointer Register */
- AT91_REG SSC_RNCR; /* Receive Next Counter Register */
- AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SSC_TNCR; /* Transmit Next Counter Register */
- AT91_REG SSC_PTCR; /* PDC Transfer Control Register */
- AT91_REG SSC_PTSR; /* PDC Transfer Status Register */
-} AT91S_SSC, * AT91PS_SSC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved3[44]; //
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
-/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
-#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */
-#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */
-#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */
-#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */
-/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
-#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */
-#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */
-#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */
-#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */
-#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */
-#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
-#define AT91C_SSC_CKO_CONTINOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
-#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
-#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */
-#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */
-#define AT91C_SSC_START_CONTINOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
-#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */
-#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */
-#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */
-#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */
-#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */
-#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */
-#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */
-#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */
-#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
-#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
-/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
-#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */
-#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */
-#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */
-#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */
-#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */
-#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */
-#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
-#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
-#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
-#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
-#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
-#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
-#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */
-/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
-/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
-#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */
-#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
-/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
-#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */
-#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */
-#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */
-#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */
-#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */
-#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */
-#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */
-#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */
-#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
-#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
-#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
-/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
-/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TWI
-{
- AT91_REG TWI_CR; /* Control Register */
- AT91_REG TWI_MMR; /* Master Mode Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG TWI_IADR; /* Internal Address Register */
- AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
- AT91_REG Reserved1[ 3 ]; /* */
- AT91_REG TWI_SR; /* Status Register */
- AT91_REG TWI_IER; /* Interrupt Enable Register */
- AT91_REG TWI_IDR; /* Interrupt Disable Register */
- AT91_REG TWI_IMR; /* Interrupt Mask Register */
- AT91_REG TWI_RHR; /* Receive Holding Register */
- AT91_REG TWI_THR; /* Transmit Holding Register */
-} AT91S_TWI, * AT91PS_TWI;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved1[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
-/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
-#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */
-#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */
-#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */
-#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */
-#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
-#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */
-#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */
-#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */
-#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */
-#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */
-#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */
-#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
-#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */
-#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */
-#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
-#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */
-#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */
-#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */
-#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */
-#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */
-#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */
-/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
-/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PWMC_CH
-{
- AT91_REG PWMC_CMR; /* Channel Mode Register */
- AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */
- AT91_REG PWMC_CPRDR; /* Channel Period Register */
- AT91_REG PWMC_CCNTR; /* Channel Counter Register */
- AT91_REG PWMC_CUPDR; /* Channel Update Register */
- AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
-} AT91S_PWMC_CH, * AT91PS_PWMC_CH;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+ AT91_REG PWMC_CMR; // Channel Mode Register
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
+ AT91_REG PWMC_CPRDR; // Channel Period Register
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
+ AT91_REG PWMC_CUPDR; // Channel Update Register
+ AT91_REG PWMC_Reserved[3]; // Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
-#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
-#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */
-#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */
-#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */
-#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
-/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
-#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */
-/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
-#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */
-/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
-#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */
-/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
-#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PWMC
-{
- AT91_REG PWMC_MR; /* PWMC Mode Register */
- AT91_REG PWMC_ENA; /* PWMC Enable Register */
- AT91_REG PWMC_DIS; /* PWMC Disable Register */
- AT91_REG PWMC_SR; /* PWMC Status Register */
- AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */
- AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */
- AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */
- AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */
- AT91_REG Reserved0[ 55 ]; /* */
- AT91_REG PWMC_VR; /* PWMC Version Register */
- AT91_REG Reserved1[ 64 ]; /* */
- AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */
-} AT91S_PWMC, * AT91PS_PWMC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+ AT91_REG PWMC_MR; // PWMC Mode Register
+ AT91_REG PWMC_ENA; // PWMC Enable Register
+ AT91_REG PWMC_DIS; // PWMC Disable Register
+ AT91_REG PWMC_SR; // PWMC Status Register
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
+ AT91_REG Reserved0[55]; //
+ AT91_REG PWMC_VR; // PWMC Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
-/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
-#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */
-#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */
-#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */
-#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
-#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */
-#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */
-/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
-#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
-#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
-#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
-#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
-/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
-/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
-/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
-/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
-/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
-/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR USB Device Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_UDP
-{
- AT91_REG UDP_NUM; /* Frame Number Register */
- AT91_REG UDP_GLBSTATE; /* Global State Register */
- AT91_REG UDP_FADDR; /* Function Address Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG UDP_IER; /* Interrupt Enable Register */
- AT91_REG UDP_IDR; /* Interrupt Disable Register */
- AT91_REG UDP_IMR; /* Interrupt Mask Register */
- AT91_REG UDP_ISR; /* Interrupt Status Register */
- AT91_REG UDP_ICR; /* Interrupt Clear Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG UDP_RSTEP; /* Reset Endpoint Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */
- AT91_REG Reserved3[ 2 ]; /* */
- AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */
- AT91_REG Reserved4[ 3 ]; /* */
- AT91_REG UDP_TXVC; /* Transceiver Control Register */
-} AT91S_UDP, * AT91PS_UDP;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
+ AT91_REG Reserved4[3]; //
+ AT91_REG UDP_TXVC; // Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
-/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
-#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
-#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */
-#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */
-/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
-#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */
-#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */
-#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */
-#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */
-#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */
-/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
-#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */
-#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */
-/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
-#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
-#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */
-#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */
-#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */
-#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */
-#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */
-#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */
-#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */
-#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */
-/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
-/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
-/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
-#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
-/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
-/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
-#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */
-#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */
-#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */
-#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */
-#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */
-#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */
-/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
-#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */
-#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */
-#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */
-#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */
-#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */
-#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
-#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
-#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */
-#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */
-#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */
-#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */
-#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */
-#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */
-#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */
-#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */
-#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */
-#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */
-#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */
-#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
-/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
-#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */
-#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TC
-{
- AT91_REG TC_CCR; /* Channel Control Register */
- AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG TC_CV; /* Counter Value */
- AT91_REG TC_RA; /* Register A */
- AT91_REG TC_RB; /* Register B */
- AT91_REG TC_RC; /* Register C */
- AT91_REG TC_SR; /* Status Register */
- AT91_REG TC_IER; /* Interrupt Enable Register */
- AT91_REG TC_IDR; /* Interrupt Disable Register */
- AT91_REG TC_IMR; /* Interrupt Mask Register */
-} AT91S_TC, * AT91PS_TC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
-/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
-#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */
-#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */
-/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
-#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */
-#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */
-#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */
-#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */
-#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */
-#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */
-#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */
-#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */
-#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */
-#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */
-#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */
-#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */
-#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */
-#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */
-#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */
-#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
-#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
-#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
-#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
-#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
-#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
-#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */
-#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
-#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
-#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
-#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
-#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
-#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
-#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
-#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
-#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
-#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
-#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
-#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
-#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
-#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
-#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
-#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
-#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
-#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
-#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
-#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
-#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
-#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
-#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
-#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
-#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
-#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
-#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
-/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
-#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */
-#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */
-#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */
-#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */
-#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */
-#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */
-#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */
-#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */
-#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
-#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
-#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
-/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
-/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
-/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TCB
-{
- AT91S_TC TCB_TC0; /* TC Channel 0 */
- AT91_REG Reserved0[ 4 ]; /* */
- AT91S_TC TCB_TC1; /* TC Channel 1 */
- AT91_REG Reserved1[ 4 ]; /* */
- AT91S_TC TCB_TC2; /* TC Channel 2 */
- AT91_REG Reserved2[ 4 ]; /* */
- AT91_REG TCB_BCR; /* TC Block Control Register */
- AT91_REG TCB_BMR; /* TC Block Mode Register */
-} AT91S_TCB, * AT91PS_TCB;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
-/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
-#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
-/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
-#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
-#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */
-#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
-#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
-#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
-#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_CAN_MB
-{
- AT91_REG CAN_MB_MMR; /* MailBox Mode Register */
- AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */
- AT91_REG CAN_MB_MID; /* MailBox ID Register */
- AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
- AT91_REG CAN_MB_MSR; /* MailBox Status Register */
- AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */
- AT91_REG CAN_MB_MDH; /* MailBox Data High Register */
- AT91_REG CAN_MB_MCR; /* MailBox Control Register */
-} AT91S_CAN_MB, * AT91PS_CAN_MB;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
+ AT91_REG CAN_MB_MID; // MailBox ID Register
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register
+ AT91_REG CAN_MB_MSR; // MailBox Status Register
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register
+ AT91_REG CAN_MB_MCR; // MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
-/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
-#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */
-#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */
-#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */
-#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */
-/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
-#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
-#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */
-#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */
-/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
-/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
-/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
-#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
-#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */
-#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */
-#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */
-#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */
-#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */
-/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
-/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
-/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
-#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
-#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_CAN
-{
- AT91_REG CAN_MR; /* Mode Register */
- AT91_REG CAN_IER; /* Interrupt Enable Register */
- AT91_REG CAN_IDR; /* Interrupt Disable Register */
- AT91_REG CAN_IMR; /* Interrupt Mask Register */
- AT91_REG CAN_SR; /* Status Register */
- AT91_REG CAN_BR; /* Baudrate Register */
- AT91_REG CAN_TIM; /* Timer Register */
- AT91_REG CAN_TIMESTP; /* Time Stamp Register */
- AT91_REG CAN_ECR; /* Error Counter Register */
- AT91_REG CAN_TCR; /* Transfer Command Register */
- AT91_REG CAN_ACR; /* Abort Command Register */
- AT91_REG Reserved0[ 52 ]; /* */
- AT91_REG CAN_VR; /* Version Register */
- AT91_REG Reserved1[ 64 ]; /* */
- AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */
- AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */
- AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */
- AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */
- AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */
- AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */
- AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */
- AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */
- AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */
- AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */
- AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */
- AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */
- AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */
- AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */
- AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */
- AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */
-} AT91S_CAN, * AT91PS_CAN;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+ AT91_REG CAN_MR; // Mode Register
+ AT91_REG CAN_IER; // Interrupt Enable Register
+ AT91_REG CAN_IDR; // Interrupt Disable Register
+ AT91_REG CAN_IMR; // Interrupt Mask Register
+ AT91_REG CAN_SR; // Status Register
+ AT91_REG CAN_BR; // Baudrate Register
+ AT91_REG CAN_TIM; // Timer Register
+ AT91_REG CAN_TIMESTP; // Time Stamp Register
+ AT91_REG CAN_ECR; // Error Counter Register
+ AT91_REG CAN_TCR; // Transfer Command Register
+ AT91_REG CAN_ACR; // Abort Command Register
+ AT91_REG Reserved0[52]; //
+ AT91_REG CAN_VR; // Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
-/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
-#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */
-#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */
-#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */
-#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */
-#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */
-#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */
-#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */
-#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */
-/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
-#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */
-#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */
-#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */
-#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */
-#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */
-#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */
-#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */
-#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */
-#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */
-#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */
-#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
-#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
-#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
-#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
-#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
-#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
-#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
-#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */
-#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
-#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
-#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */
-#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */
-#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
-#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */
-#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */
-#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */
-#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */
-#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */
-#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */
-/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
-/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
-/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
-#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */
-#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */
-#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */
-/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
-#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */
-#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */
-#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */
-#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */
-#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */
-#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */
-/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
-#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */
-/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
-/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
-#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */
-#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */
-/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
-#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */
-/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
-/* ***************************************************************************** */
-typedef struct _AT91S_EMAC
-{
- AT91_REG EMAC_NCR; /* Network Control Register */
- AT91_REG EMAC_NCFGR; /* Network Configuration Register */
- AT91_REG EMAC_NSR; /* Network Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG EMAC_TSR; /* Transmit Status Register */
- AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
- AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */
- AT91_REG EMAC_RSR; /* Receive Status Register */
- AT91_REG EMAC_ISR; /* Interrupt Status Register */
- AT91_REG EMAC_IER; /* Interrupt Enable Register */
- AT91_REG EMAC_IDR; /* Interrupt Disable Register */
- AT91_REG EMAC_IMR; /* Interrupt Mask Register */
- AT91_REG EMAC_MAN; /* PHY Maintenance Register */
- AT91_REG EMAC_PTR; /* Pause Time Register */
- AT91_REG EMAC_PFR; /* Pause Frames received Register */
- AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */
- AT91_REG EMAC_SCF; /* Single Collision Frame Register */
- AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */
- AT91_REG EMAC_FRO; /* Frames Received OK Register */
- AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */
- AT91_REG EMAC_ALE; /* Alignment Error Register */
- AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */
- AT91_REG EMAC_LCOL; /* Late Collision Register */
- AT91_REG EMAC_ECOL; /* Excessive Collision Register */
- AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
- AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
- AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
- AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
- AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
- AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
- AT91_REG EMAC_RJA; /* Receive Jabbers Register */
- AT91_REG EMAC_USF; /* Undersize Frames Register */
- AT91_REG EMAC_STE; /* SQE Test Error Register */
- AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */
- AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */
- AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */
- AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */
- AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */
- AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */
- AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */
- AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */
- AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */
- AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */
- AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */
- AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */
- AT91_REG EMAC_TID; /* Type ID Checking Register */
- AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */
- AT91_REG EMAC_USRIO; /* USER Input/Output Register */
- AT91_REG EMAC_WOL; /* Wake On LAN Register */
- AT91_REG Reserved1[ 13 ]; /* */
- AT91_REG EMAC_REV; /* Revision Register */
-} AT91S_EMAC, * AT91PS_EMAC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+ AT91_REG EMAC_NCR; // Network Control Register
+ AT91_REG EMAC_NCFGR; // Network Configuration Register
+ AT91_REG EMAC_NSR; // Network Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG EMAC_TSR; // Transmit Status Register
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
+ AT91_REG EMAC_RSR; // Receive Status Register
+ AT91_REG EMAC_ISR; // Interrupt Status Register
+ AT91_REG EMAC_IER; // Interrupt Enable Register
+ AT91_REG EMAC_IDR; // Interrupt Disable Register
+ AT91_REG EMAC_IMR; // Interrupt Mask Register
+ AT91_REG EMAC_MAN; // PHY Maintenance Register
+ AT91_REG EMAC_PTR; // Pause Time Register
+ AT91_REG EMAC_PFR; // Pause Frames received Register
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register
+ AT91_REG EMAC_SCF; // Single Collision Frame Register
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register
+ AT91_REG EMAC_FRO; // Frames Received OK Register
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
+ AT91_REG EMAC_ALE; // Alignment Error Register
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
+ AT91_REG EMAC_LCOL; // Late Collision Register
+ AT91_REG EMAC_ECOL; // Excessive Collision Register
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register
+ AT91_REG EMAC_RJA; // Receive Jabbers Register
+ AT91_REG EMAC_USF; // Undersize Frames Register
+ AT91_REG EMAC_STE; // SQE Test Error Register
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
+ AT91_REG EMAC_TID; // Type ID Checking Register
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
+ AT91_REG EMAC_USRIO; // USER Input/Output Register
+ AT91_REG EMAC_WOL; // Wake On LAN Register
+ AT91_REG Reserved1[13]; //
+ AT91_REG EMAC_REV; // Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
-/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */
-#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */
-#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */
-#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */
-#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */
-#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
-/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
-#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */
-#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */
-#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
-#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
-#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
-#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */
-#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
-/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
-#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
-#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */
-#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */
-#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
-/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
-#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */
-#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */
-#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
-#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */
-#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */
-#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */
-#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
-/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */
-#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */
-#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */
-#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */
-#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */
-/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
-#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */
-/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
-#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */
-#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */
-#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */
-#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */
-/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
-#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */
+// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
-/* ***************************************************************************** */
-typedef struct _AT91S_ADC
-{
- AT91_REG ADC_CR; /* ADC Control Register */
- AT91_REG ADC_MR; /* ADC Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG ADC_CHER; /* ADC Channel Enable Register */
- AT91_REG ADC_CHDR; /* ADC Channel Disable Register */
- AT91_REG ADC_CHSR; /* ADC Channel Status Register */
- AT91_REG ADC_SR; /* ADC Status Register */
- AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */
- AT91_REG ADC_IER; /* ADC Interrupt Enable Register */
- AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */
- AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */
- AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */
- AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */
- AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */
- AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */
- AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */
- AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */
- AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */
- AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */
- AT91_REG Reserved1[ 44 ]; /* */
- AT91_REG ADC_RPR; /* Receive Pointer Register */
- AT91_REG ADC_RCR; /* Receive Counter Register */
- AT91_REG ADC_TPR; /* Transmit Pointer Register */
- AT91_REG ADC_TCR; /* Transmit Counter Register */
- AT91_REG ADC_RNPR; /* Receive Next Pointer Register */
- AT91_REG ADC_RNCR; /* Receive Next Counter Register */
- AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG ADC_TNCR; /* Transmit Next Counter Register */
- AT91_REG ADC_PTCR; /* PDC Transfer Control Register */
- AT91_REG ADC_PTSR; /* PDC Transfer Status Register */
-} AT91S_ADC, * AT91PS_ADC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+ AT91_REG ADC_CR; // ADC Control Register
+ AT91_REG ADC_MR; // ADC Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
+ AT91_REG ADC_SR; // ADC Status Register
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
+ AT91_REG Reserved1[44]; //
+ AT91_REG ADC_RPR; // Receive Pointer Register
+ AT91_REG ADC_RCR; // Receive Counter Register
+ AT91_REG ADC_TPR; // Transmit Pointer Register
+ AT91_REG ADC_TCR; // Transmit Counter Register
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
-/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
-#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */
-#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */
-/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
-#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */
-#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software */
-#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
-#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */
-#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */
-#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */
-#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */
-#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */
-#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */
-#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */
-#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */
-#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */
-#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */
-#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */
-#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */
-#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */
-#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
-#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */
-/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
-#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */
-#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */
-#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */
-#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */
-#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */
-#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */
-#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */
-#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */
-/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
-/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
-/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
-#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */
-#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */
-#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */
-#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */
-/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
-#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
-/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
-/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
-/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
-/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
-#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */
-/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
-/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
-/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
-/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
-/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
-/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
-/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
-/* ***************************************************************************** */
-typedef struct _AT91S_AES
-{
- AT91_REG AES_CR; /* Control Register */
- AT91_REG AES_MR; /* Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AES_IER; /* Interrupt Enable Register */
- AT91_REG AES_IDR; /* Interrupt Disable Register */
- AT91_REG AES_IMR; /* Interrupt Mask Register */
- AT91_REG AES_ISR; /* Interrupt Status Register */
- AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */
- AT91_REG Reserved1[ 4 ]; /* */
- AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */
- AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */
- AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */
- AT91_REG Reserved2[ 35 ]; /* */
- AT91_REG AES_VR; /* AES Version Register */
- AT91_REG AES_RPR; /* Receive Pointer Register */
- AT91_REG AES_RCR; /* Receive Counter Register */
- AT91_REG AES_TPR; /* Transmit Pointer Register */
- AT91_REG AES_TCR; /* Transmit Counter Register */
- AT91_REG AES_RNPR; /* Receive Next Pointer Register */
- AT91_REG AES_RNCR; /* Receive Next Counter Register */
- AT91_REG AES_TNPR; /* Transmit Next Pointer Register */
- AT91_REG AES_TNCR; /* Transmit Next Counter Register */
- AT91_REG AES_PTCR; /* PDC Transfer Control Register */
- AT91_REG AES_PTSR; /* PDC Transfer Status Register */
-} AT91S_AES, * AT91PS_AES;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+ AT91_REG AES_CR; // Control Register
+ AT91_REG AES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AES_IER; // Interrupt Enable Register
+ AT91_REG AES_IDR; // Interrupt Disable Register
+ AT91_REG AES_IMR; // Interrupt Mask Register
+ AT91_REG AES_ISR; // Interrupt Status Register
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register
+ AT91_REG Reserved1[4]; //
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register
+ AT91_REG Reserved2[35]; //
+ AT91_REG AES_VR; // AES Version Register
+ AT91_REG AES_RPR; // Receive Pointer Register
+ AT91_REG AES_RCR; // Receive Counter Register
+ AT91_REG AES_TPR; // Transmit Pointer Register
+ AT91_REG AES_TCR; // Transmit Counter Register
+ AT91_REG AES_RNPR; // Receive Next Pointer Register
+ AT91_REG AES_RNCR; // Receive Next Counter Register
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register
+ AT91_REG AES_TNCR; // Transmit Next Counter Register
+ AT91_REG AES_PTCR; // PDC Transfer Control Register
+ AT91_REG AES_PTSR; // PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
-/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
-#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */
-#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */
-#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */
-/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
-#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */
-#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */
-#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */
-#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
-#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
-#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */
-#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */
-#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */
-#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */
-#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */
-#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */
-#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */
-#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */
-#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */
-#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */
-#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */
-#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */
-#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */
-#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */
-#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */
-#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */
-#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */
-#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */
-#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */
-#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */
-#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
-/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */
-#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */
-#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */
-#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */
-#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */
-#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */
-/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
-#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
-#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
-#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
-#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
-#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
-#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */
+// -------- AES_CR : (AES Offset: 0x0) Control Register --------
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
-/* ***************************************************************************** */
-typedef struct _AT91S_TDES
-{
- AT91_REG TDES_CR; /* Control Register */
- AT91_REG TDES_MR; /* Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG TDES_IER; /* Interrupt Enable Register */
- AT91_REG TDES_IDR; /* Interrupt Disable Register */
- AT91_REG TDES_IMR; /* Interrupt Mask Register */
- AT91_REG TDES_ISR; /* Interrupt Status Register */
- AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */
- AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */
- AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */
- AT91_REG Reserved1[ 2 ]; /* */
- AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */
- AT91_REG Reserved2[ 2 ]; /* */
- AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */
- AT91_REG Reserved3[ 2 ]; /* */
- AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */
- AT91_REG Reserved4[ 37 ]; /* */
- AT91_REG TDES_VR; /* TDES Version Register */
- AT91_REG TDES_RPR; /* Receive Pointer Register */
- AT91_REG TDES_RCR; /* Receive Counter Register */
- AT91_REG TDES_TPR; /* Transmit Pointer Register */
- AT91_REG TDES_TCR; /* Transmit Counter Register */
- AT91_REG TDES_RNPR; /* Receive Next Pointer Register */
- AT91_REG TDES_RNCR; /* Receive Next Counter Register */
- AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */
- AT91_REG TDES_TNCR; /* Transmit Next Counter Register */
- AT91_REG TDES_PTCR; /* PDC Transfer Control Register */
- AT91_REG TDES_PTSR; /* PDC Transfer Status Register */
-} AT91S_TDES, * AT91PS_TDES;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+ AT91_REG TDES_CR; // Control Register
+ AT91_REG TDES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG TDES_IER; // Interrupt Enable Register
+ AT91_REG TDES_IDR; // Interrupt Disable Register
+ AT91_REG TDES_IMR; // Interrupt Mask Register
+ AT91_REG TDES_ISR; // Interrupt Status Register
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
+ AT91_REG Reserved4[37]; //
+ AT91_REG TDES_VR; // TDES Version Register
+ AT91_REG TDES_RPR; // Receive Pointer Register
+ AT91_REG TDES_RCR; // Receive Counter Register
+ AT91_REG TDES_TPR; // Transmit Pointer Register
+ AT91_REG TDES_TCR; // Transmit Counter Register
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register
+ AT91_REG TDES_RNCR; // Receive Next Counter Register
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
-/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
-#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */
-#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */
-/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
-#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */
-#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */
-#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */
-#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */
-#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
-#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
-#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */
-#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */
-#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
-#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
-#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
-#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
-#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */
-#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
-#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */
-#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */
-#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */
-#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */
-/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */
-#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */
-#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */
-#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */
-#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */
-#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */
-/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
-#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
-#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
-#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
-#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-/* ***************************************************************************** */
-/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-/* ========== Register definition for SYS peripheral ========== */
-/* ========== Register definition for AIC peripheral ========== */
-#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
-#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
-#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
-#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
-#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
-#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
-#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
-#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
-#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
-#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
-#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
-#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
-#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
-#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
-#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
-#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
-#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
-#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
-/* ========== Register definition for PDC_DBGU peripheral ========== */
-#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
-#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
-#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
-#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
-#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
-#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
-#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
-#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
-#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
-#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
-/* ========== Register definition for DBGU peripheral ========== */
-#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
-#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
-#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
-#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
-#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */
-#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
-#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
-#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
-#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
-#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
-#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
-#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
-/* ========== Register definition for PIOA peripheral ========== */
-#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
-#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
-#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
-#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
-#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
-#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
-#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
-#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
-#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
-#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
-#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
-#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
-#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
-#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
-#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
-#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
-#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
-#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
-#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
-#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
-#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
-#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
-#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
-#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
-#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
-#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
-#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
-/* ========== Register definition for PIOB peripheral ========== */
-#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
-#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
-#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
-#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
-#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */
-#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
-#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */
-#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
-#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
-#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
-#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
-#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
-#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
-#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
-#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
-#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
-#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
-#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
-#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
-#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
-#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
-#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */
-#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
-#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
-#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */
-#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
-#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */
-#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
-/* ========== Register definition for CKGR peripheral ========== */
-#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
-#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
-#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */
-/* ========== Register definition for PMC peripheral ========== */
-#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
-#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
-#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
-#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
-#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
-#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
-#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
-#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
-#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
-#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */
-#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
-#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
-#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
-#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
-/* ========== Register definition for RSTC peripheral ========== */
-#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
-#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
-#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
-/* ========== Register definition for RTTC peripheral ========== */
-#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
-#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
-#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
-#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
-/* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
-#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
-#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
-#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
-/* ========== Register definition for WDTC peripheral ========== */
-#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
-#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
-#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
-/* ========== Register definition for VREG peripheral ========== */
-#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
-/* ========== Register definition for MC peripheral ========== */
-#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
-#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
-#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
-#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
-#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
-#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
-/* ========== Register definition for PDC_SPI1 peripheral ========== */
-#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
-#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
-#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
-#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
-#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
-#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
-#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
-#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
-#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
-#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
-/* ========== Register definition for SPI1 peripheral ========== */
-#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
-#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
-#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */
-#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */
-#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
-#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */
-#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */
-#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */
-#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */
-/* ========== Register definition for PDC_SPI0 peripheral ========== */
-#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
-#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
-#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
-#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
-#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
-#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
-#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
-#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
-#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
-#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
-/* ========== Register definition for SPI0 peripheral ========== */
-#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
-#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */
-#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
-#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */
-#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */
-#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
-#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */
-#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */
-#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */
-/* ========== Register definition for PDC_US1 peripheral ========== */
-#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
-#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
-#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
-#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
-#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
-#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
-#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
-#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
-#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
-#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
-/* ========== Register definition for US1 peripheral ========== */
-#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
-#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
-#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
-#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
-#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
-#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
-#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
-#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
-#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
-#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
-#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
-#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
-#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
-#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
-/* ========== Register definition for PDC_US0 peripheral ========== */
-#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
-#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
-#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
-#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
-#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
-#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
-#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
-#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
-#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
-#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
-/* ========== Register definition for US0 peripheral ========== */
-#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
-#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
-#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
-#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
-#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
-#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
-#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
-#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
-#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
-#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
-#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
-#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
-#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
-#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
-/* ========== Register definition for PDC_SSC peripheral ========== */
-#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
-#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
-#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
-#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
-#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
-#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
-#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
-#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
-#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
-#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
-/* ========== Register definition for SSC peripheral ========== */
-#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
-#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
-#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
-#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
-#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
-#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
-#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
-#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
-#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
-#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
-#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
-#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
-#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
-#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
-/* ========== Register definition for TWI peripheral ========== */
-#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
-#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
-#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
-#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
-#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
-#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
-#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
-#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
-#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
-#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
-/* ========== Register definition for PWMC_CH3 peripheral ========== */
-#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
-#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
-#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
-#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
-#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
-/* ========== Register definition for PWMC_CH2 peripheral ========== */
-#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
-#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
-#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
-#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
-#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
-#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH1 peripheral ========== */
-#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
-#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
-#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
-#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
-#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
-/* ========== Register definition for PWMC_CH0 peripheral ========== */
-#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
-#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
-#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
-#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
-#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
-/* ========== Register definition for PWMC peripheral ========== */
-#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
-#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
-#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
-#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
-#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
-#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
-#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
-#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
-#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
-/* ========== Register definition for UDP peripheral ========== */
-#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
-#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
-#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
-#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
-#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
-#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
-#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
-#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
-#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
-#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
-#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
-#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
-/* ========== Register definition for TC0 peripheral ========== */
-#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
-#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
-#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
-#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
-#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
-#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
-#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
-#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
-#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
-/* ========== Register definition for TC1 peripheral ========== */
-#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
-#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
-#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
-#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
-#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
-#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
-#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
-#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
-#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
-/* ========== Register definition for TC2 peripheral ========== */
-#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
-#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
-#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
-#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
-#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
-#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
-#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
-#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
-#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
-/* ========== Register definition for TCB peripheral ========== */
-#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
-#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
-/* ========== Register definition for CAN_MB0 peripheral ========== */
-#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
-#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
-#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
-#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
-#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
-#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
-#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
-/* ========== Register definition for CAN_MB1 peripheral ========== */
-#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
-#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
-#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
-#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
-#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
-#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
-#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
-/* ========== Register definition for CAN_MB2 peripheral ========== */
-#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
-#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
-#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
-#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
-#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
-#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
-#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
-/* ========== Register definition for CAN_MB3 peripheral ========== */
-#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
-#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
-#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
-#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
-#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
-#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
-#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
-/* ========== Register definition for CAN_MB4 peripheral ========== */
-#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
-#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
-#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
-#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
-#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
-#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
-#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
-#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB5 peripheral ========== */
-#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
-#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
-#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
-#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
-#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
-#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
-#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
-#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB6 peripheral ========== */
-#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
-#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
-#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
-#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
-#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
-#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
-#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
-/* ========== Register definition for CAN_MB7 peripheral ========== */
-#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
-#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
-#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
-#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
-#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
-#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
-#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
-/* ========== Register definition for CAN peripheral ========== */
-#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */
-#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
-#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
-#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */
-#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */
-#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */
-#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
-#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */
-#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */
-#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */
-#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */
-#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */
-/* ========== Register definition for EMAC peripheral ========== */
-#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
-#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
-#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
-#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
-#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */
-#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
-#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
-#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
-#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
-#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */
-#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
-#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */
-#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
-#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
-#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
-#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
-#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
-#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
-#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
-#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
-#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
-#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */
-#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
-#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
-#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
-#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
-#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
-#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
-#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
-#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
-#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
-#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
-#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
-#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
-#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
-#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */
-#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
-#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
-#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
-#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
-#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */
-#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
-#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
-#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
-#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
-#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
-#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
-#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
-/* ========== Register definition for PDC_ADC peripheral ========== */
-#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
-#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
-#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
-#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
-#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
-#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
-#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
-#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
-#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
-#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
-/* ========== Register definition for ADC peripheral ========== */
-#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
-#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
-#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
-#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
-#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
-#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
-#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
-#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
-#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
-#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
-#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
-#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
-#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
-#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
-#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
-#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
-#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
-#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
-/* ========== Register definition for PDC_AES peripheral ========== */
-#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
-#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
-#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
-#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
-#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
-#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
-#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
-#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
-#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
-#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
-/* ========== Register definition for AES peripheral ========== */
-#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
-#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */
-#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */
-#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */
-#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */
-#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */
-#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
-#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
-#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
-#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */
-#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */
-/* ========== Register definition for PDC_TDES peripheral ========== */
-#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
-#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
-#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
-#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
-#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
-#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
-#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
-#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
-#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
-#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
-/* ========== Register definition for TDES peripheral ========== */
-#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
-#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
-#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
-#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */
-#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
-#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */
-#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
-#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */
-#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */
-#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
-#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */
-#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */
-#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ==========
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ==========
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ==========
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ==========
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ==========
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ==========
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ==========
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ==========
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ==========
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ==========
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ==========
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ==========
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ==========
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ==========
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ==========
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ==========
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ==========
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ==========
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
-/* ***************************************************************************** */
-/* PIO DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */
-#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */
-#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */
-#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */
-#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */
-#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */
-#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */
-#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */
-#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */
-#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */
-#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */
-#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */
-#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */
-#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */
-#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */
-#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */
-#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */
-#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */
-#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */
-#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */
-#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */
-#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */
-#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */
-#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */
-#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */
-#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */
-#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */
-#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */
-#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */
-#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */
-#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */
-#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */
-#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */
-#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */
-#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */
-#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */
-#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */
-#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */
-#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */
-#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */
-#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */
-#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */
-#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */
-#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */
-#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */
-#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */
-#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */
-#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */
-#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */
-#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */
-#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */
-#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */
-#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */
-#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */
-#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */
-#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */
-#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */
-#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */
-#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */
-#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */
-#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */
-#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */
-#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */
-#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */
-#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */
-#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */
-#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */
-#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */
-#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */
-#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */
-#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */
-#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */
-#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */
-#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */
-#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */
-#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */
-#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */
-#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */
-#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */
-#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */
-#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */
-#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */
-#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */
-#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */
-#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */
-#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */
-#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */
-#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */
-#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */
-#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */
-#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */
-#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */
-#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */
-#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */
-#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */
-#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */
-#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */
-#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */
-#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */
-#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */
-#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */
-#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */
-#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */
-#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */
-#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */
-#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */
-#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */
-#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */
-#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */
-#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */
-#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */
-#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */
-#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */
-#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */
-#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */
-#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */
-#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */
-#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */
-#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */
-#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */
-#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */
-#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */
-#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */
-#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */
-#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-/* ***************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */
-#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */
-#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */
-#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */
-#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */
-#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */
-#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */
-#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */
-#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */
-#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */
-#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */
-#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */
-#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */
-#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */
-#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */
-#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */
-#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */
-#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */
-#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */
-#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */
-#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */
-#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */
-#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */
-#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */
-#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */
-#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */
-#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */
-#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */
-#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */
-#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-/* ***************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */
-#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */
-#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */
-#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */
-#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */
-#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */
-#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */
-#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */
-#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */
-#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */
-#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */
-#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */
-#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */
-#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */
-#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */
-#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */
-#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */
-#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */
-#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */
-#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */
-#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */
-#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */
-#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */
-#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */
-#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */
-#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
-#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
-#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
-#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
-#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */
-#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */
-#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */
-#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */
-#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */
-#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */
-#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */
-#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */
-#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */
-#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */
-#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */
-#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */
-#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */
-#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */
-#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */
-#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */
-#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */
-#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */
-#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */
-#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */
-#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */
-#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
-/* ***************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */
-#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */
-#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */
-#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
-/* - Hardware register definition */
+// - Hardware register definition
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR System Peripherals */
-/* - ***************************************************************************** */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR System Peripherals
+// - *****************************************************************************
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
-/* - ***************************************************************************** */
-/* - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// - *****************************************************************************
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#if 0 /*_RB_*/
- AT91C_AIC_PRIOR EQU( 0x7 << 0 );
- - ( AIC ) Priority Level
- AT91C_AIC_PRIOR_LOWEST EQU( 0x0 );
- - ( AIC ) Lowest priority level
- AT91C_AIC_PRIOR_HIGHEST EQU( 0x7 );
- - ( AIC ) Highest priority level
- AT91C_AIC_SRCTYPE EQU( 0x3 << 5 );
- - ( AIC ) Interrupt Source Type
- AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU( 0x0 << 5 );
- - ( AIC ) Internal Sources Code Label High - level Sensitive
- AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU( 0x0 << 5 );
- - ( AIC ) External Sources Code Label Low - level Sensitive
- AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU( 0x1 << 5 );
- - ( AIC ) Internal Sources Code Label Positive Edge triggered
- AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU( 0x1 << 5 );
- - ( AIC ) External Sources Code Label Negative Edge triggered
- AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU( 0x2 << 5 );
- - ( AIC ) Internal Or External Sources Code Label High - level Sensitive
- AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU( 0x3 << 5 );
- - ( AIC ) Internal Or External Sources Code Label Positive Edge triggered
-/* - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
- AT91C_AIC_NFIQ EQU( 0x1 << 0 );
- - ( AIC ) NFIQ Status
- AT91C_AIC_NIRQ EQU( 0x1 << 1 );
- - ( AIC ) NIRQ Status
-/* - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
- AT91C_AIC_DCR_PROT EQU( 0x1 << 0 );
- - ( AIC ) Protection Mode
- AT91C_AIC_DCR_GMSK EQU( 0x1 << 1 );
- - ( AIC ) General Mask
-#endif /* if 0 */
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
-/* - ***************************************************************************** */
-/* - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-AT91C_PDC_RXTEN EQU( 0x1 << 0 );
-- ( PDC ) Receiver Transfer Enable
- AT91C_PDC_RXTDIS EQU( 0x1 << 1 );
-- ( PDC ) Receiver Transfer Disable
- AT91C_PDC_TXTEN EQU( 0x1 << 8 );
-- ( PDC ) Transmitter Transfer Enable
- AT91C_PDC_TXTDIS EQU( 0x1 << 9 );
-- ( PDC ) Transmitter Transfer Disable
-/* - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level
+AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
+AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
+AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status
+AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode
+AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask
+#endif
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// - *****************************************************************************
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable
+AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable
+AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable
+AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Debug Unit */
-/* - ***************************************************************************** */
-/* - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
- AT91C_US_RSTRX EQU( 0x1 << 2 );
-- ( DBGU ) Reset Receiver
- AT91C_US_RSTTX EQU( 0x1 << 3 );
-- ( DBGU ) Reset Transmitter
- AT91C_US_RXEN EQU( 0x1 << 4 );
-- ( DBGU ) Receiver Enable
- AT91C_US_RXDIS EQU( 0x1 << 5 );
-- ( DBGU ) Receiver Disable
- AT91C_US_TXEN EQU( 0x1 << 6 );
-- ( DBGU ) Transmitter Enable
- AT91C_US_TXDIS EQU( 0x1 << 7 );
-- ( DBGU ) Transmitter Disable
- AT91C_US_RSTSTA EQU( 0x1 << 8 );
-- ( DBGU ) Reset Status Bits
-/* - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
- AT91C_US_PAR EQU( 0x7 << 9 );
-- ( DBGU ) Parity type
- AT91C_US_PAR_EVEN EQU( 0x0 << 9 );
-- ( DBGU ) Even Parity
- AT91C_US_PAR_ODD EQU( 0x1 << 9 );
-- ( DBGU ) Odd Parity
- AT91C_US_PAR_SPACE EQU( 0x2 << 9 );
-- ( DBGU ) Parity forced to 0 ( Space )
- AT91C_US_PAR_MARK EQU( 0x3 << 9 );
-- ( DBGU ) Parity forced to 1 ( Mark )
- AT91C_US_PAR_NONE EQU( 0x4 << 9 );
-- ( DBGU ) No Parity
- AT91C_US_PAR_MULTI_DROP EQU( 0x6 << 9 );
-- ( DBGU ) Multi - drop mode
- AT91C_US_CHMODE EQU( 0x3 << 14 );
-- ( DBGU ) Channel Mode
- AT91C_US_CHMODE_NORMAL EQU( 0x0 << 14 );
-- ( DBGU ) Normal Mode: The USART channel operates as an RX / TX USART.
- AT91C_US_CHMODE_AUTO EQU( 0x1 << 14 );
-- ( DBGU ) Automatic Echo: Receiver Data Input is connected to the TXD pin.
- AT91C_US_CHMODE_LOCAL EQU( 0x2 << 14 );
-- ( DBGU ) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
- AT91C_US_CHMODE_REMOTE EQU( 0x3 << 14 );
-- ( DBGU ) Remote Loopback: RXD pin is internally connected to TXD pin.
-/* - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
- AT91C_US_RXRDY EQU( 0x1 << 0 );
-- ( DBGU ) RXRDY Interrupt
- AT91C_US_TXRDY EQU( 0x1 << 1 );
-- ( DBGU ) TXRDY Interrupt
- AT91C_US_ENDRX EQU( 0x1 << 3 );
-- ( DBGU ) End of Receive Transfer Interrupt
- AT91C_US_ENDTX EQU( 0x1 << 4 );
-- ( DBGU ) End of Transmit Interrupt
- AT91C_US_OVRE EQU( 0x1 << 5 );
-- ( DBGU ) Overrun Interrupt
- AT91C_US_FRAME EQU( 0x1 << 6 );
-- ( DBGU ) Framing Error Interrupt
- AT91C_US_PARE EQU( 0x1 << 7 );
-- ( DBGU ) Parity Error Interrupt
- AT91C_US_TXEMPTY EQU( 0x1 << 9 );
-- ( DBGU ) TXEMPTY Interrupt
- AT91C_US_TXBUFE EQU( 0x1 << 11 );
-- ( DBGU ) TXBUFE Interrupt
- AT91C_US_RXBUFF EQU( 0x1 << 12 );
-- ( DBGU ) RXBUFF Interrupt
- AT91C_US_COMM_TX EQU( 0x1 << 30 );
-- ( DBGU ) COMM_TX Interrupt
- AT91C_US_COMM_RX EQU( 0x1 << 31 );
-- ( DBGU ) COMM_RX Interrupt
-/* - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
-/* - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
- AT91C_US_FORCE_NTRST EQU( 0x1 << 0 );
-- ( DBGU ) Force NTRST in JTAG
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Debug Unit
+// - *****************************************************************************
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver
+AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter
+AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable
+AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable
+AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable
+AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable
+AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type
+AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity
+AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity
+AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space)
+AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark)
+AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity
+AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode
+AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode
+AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt
+AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt
+AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt
+AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt
+AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt
+AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt
+AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt
+AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt
+AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
+AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
+AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
+AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* - ***************************************************************************** */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// - *****************************************************************************
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/* - ***************************************************************************** */
-/* - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
- AT91C_CKGR_MOSCEN EQU( 0x1 << 0 );
-- ( CKGR ) Main Oscillator Enable
- AT91C_CKGR_OSCBYPASS EQU( 0x1 << 1 );
-- ( CKGR ) Main Oscillator Bypass
- AT91C_CKGR_OSCOUNT EQU( 0xFF << 8 );
-- ( CKGR ) Main Oscillator Start - up Time
-/* - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
- AT91C_CKGR_MAINF EQU( 0xFFFF << 0 );
-- ( CKGR ) Main Clock Frequency
- AT91C_CKGR_MAINRDY EQU( 0x1 << 16 );
-- ( CKGR ) Main Clock Ready
-/* - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
- AT91C_CKGR_DIV EQU( 0xFF << 0 );
-- ( CKGR ) Divider Selected
- AT91C_CKGR_DIV_0 EQU( 0x0 );
-- ( CKGR ) Divider output is 0
- AT91C_CKGR_DIV_BYPASS EQU( 0x1 );
-- ( CKGR ) Divider is bypassed
- AT91C_CKGR_PLLCOUNT EQU( 0x3F << 8 );
-- ( CKGR ) PLL Counter
- AT91C_CKGR_OUT EQU( 0x3 << 14 );
-- ( CKGR ) PLL Output Frequency Range
- AT91C_CKGR_OUT_0 EQU( 0x0 << 14 );
-- ( CKGR ) Please refer to the PLL datasheet
- AT91C_CKGR_OUT_1 EQU( 0x1 << 14 );
-- ( CKGR ) Please refer to the PLL datasheet
- AT91C_CKGR_OUT_2 EQU( 0x2 << 14 );
-- ( CKGR ) Please refer to the PLL datasheet
- AT91C_CKGR_OUT_3 EQU( 0x3 << 14 );
-- ( CKGR ) Please refer to the PLL datasheet
- AT91C_CKGR_MUL EQU( 0x7FF << 16 );
-- ( CKGR ) PLL Multiplier
- AT91C_CKGR_USBDIV EQU( 0x3 << 28 );
-- ( CKGR ) Divider for USB Clocks
- AT91C_CKGR_USBDIV_0 EQU( 0x0 << 28 );
-- ( CKGR ) Divider output is PLL clock output
- AT91C_CKGR_USBDIV_1 EQU( 0x1 << 28 );
-- ( CKGR ) Divider output is PLL clock output divided by 2
- AT91C_CKGR_USBDIV_2 EQU( 0x2 << 28 );
-- ( CKGR ) Divider output is PLL clock output divided by 4
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Clock Generator Controler
+// - *****************************************************************************
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable
+AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass
+AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency
+AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected
+AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0
+AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed
+AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter
+AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
+AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
+AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
+AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
+AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
+AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Power Management Controler */
-/* - ***************************************************************************** */
-/* - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
- AT91C_PMC_PCK EQU( 0x1 << 0 );
-- ( PMC ) Processor Clock
- AT91C_PMC_UDP EQU( 0x1 << 7 );
-- ( PMC ) USB Device Port Clock
- AT91C_PMC_PCK0 EQU( 0x1 << 8 );
-- ( PMC ) Programmable Clock Output
- AT91C_PMC_PCK1 EQU( 0x1 << 9 );
-- ( PMC ) Programmable Clock Output
- AT91C_PMC_PCK2 EQU( 0x1 << 10 );
-- ( PMC ) Programmable Clock Output
- AT91C_PMC_PCK3 EQU( 0x1 << 11 );
-- ( PMC ) Programmable Clock Output
-/* - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
-/* - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
-/* - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
-/* - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
-/* - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
-/* - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
- AT91C_PMC_CSS EQU( 0x3 << 0 );
-- ( PMC ) Programmable Clock Selection
- AT91C_PMC_CSS_SLOW_CLK EQU( 0x0 );
-- ( PMC ) Slow Clock is selected
- AT91C_PMC_CSS_MAIN_CLK EQU( 0x1 );
-- ( PMC ) Main Clock is selected
- AT91C_PMC_CSS_PLL_CLK EQU( 0x3 );
-- ( PMC ) Clock from PLL is selected
- AT91C_PMC_PRES EQU( 0x7 << 2 );
-- ( PMC ) Programmable Clock Prescaler
- AT91C_PMC_PRES_CLK EQU( 0x0 << 2 );
-- ( PMC ) Selected clock
- AT91C_PMC_PRES_CLK_2 EQU( 0x1 << 2 );
-- ( PMC ) Selected clock divided by 2
- AT91C_PMC_PRES_CLK_4 EQU( 0x2 << 2 );
-- ( PMC ) Selected clock divided by 4
- AT91C_PMC_PRES_CLK_8 EQU( 0x3 << 2 );
-- ( PMC ) Selected clock divided by 8
- AT91C_PMC_PRES_CLK_16 EQU( 0x4 << 2 );
-- ( PMC ) Selected clock divided by 16
- AT91C_PMC_PRES_CLK_32 EQU( 0x5 << 2 );
-- ( PMC ) Selected clock divided by 32
- AT91C_PMC_PRES_CLK_64 EQU( 0x6 << 2 );
-- ( PMC ) Selected clock divided by 64
-/* - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
-/* - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
- AT91C_PMC_MOSCS EQU( 0x1 << 0 );
-- ( PMC ) MOSC Status / Enable / Disable / Mask
- AT91C_PMC_LOCK EQU( 0x1 << 2 );
-- ( PMC ) PLL Status / Enable / Disable / Mask
- AT91C_PMC_MCKRDY EQU( 0x1 << 3 );
-- ( PMC ) MCK_RDY Status / Enable / Disable / Mask
- AT91C_PMC_PCK0RDY EQU( 0x1 << 8 );
-- ( PMC ) PCK0_RDY Status / Enable / Disable / Mask
- AT91C_PMC_PCK1RDY EQU( 0x1 << 9 );
-- ( PMC ) PCK1_RDY Status / Enable / Disable / Mask
- AT91C_PMC_PCK2RDY EQU( 0x1 << 10 );
-- ( PMC ) PCK2_RDY Status / Enable / Disable / Mask
- AT91C_PMC_PCK3RDY EQU( 0x1 << 11 );
-- ( PMC ) PCK3_RDY Status / Enable / Disable / Mask
-/* - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
-/* - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
-/* - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Power Management Controler
+// - *****************************************************************************
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock
+AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock
+AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection
+AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected
+AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected
+AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected
+AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler
+AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock
+AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2
+AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4
+AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8
+AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16
+AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32
+AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask
+AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask
+AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Reset Controller Interface */
-/* - ***************************************************************************** */
-/* - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
- AT91C_RSTC_PROCRST EQU( 0x1 << 0 );
-- ( RSTC ) Processor Reset
- AT91C_RSTC_PERRST EQU( 0x1 << 2 );
-- ( RSTC ) Peripheral Reset
- AT91C_RSTC_EXTRST EQU( 0x1 << 3 );
-- ( RSTC ) External Reset
- AT91C_RSTC_KEY EQU( 0xFF << 24 );
-- ( RSTC ) Password
-/* - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
- AT91C_RSTC_URSTS EQU( 0x1 << 0 );
-- ( RSTC ) User Reset Status
- AT91C_RSTC_BODSTS EQU( 0x1 << 1 );
-- ( RSTC ) Brownout Detection Status
- AT91C_RSTC_RSTTYP EQU( 0x7 << 8 );
-- ( RSTC ) Reset Type
- AT91C_RSTC_RSTTYP_POWERUP EQU( 0x0 << 8 );
-- ( RSTC ) Power - up Reset.VDDCORE rising.
- AT91C_RSTC_RSTTYP_WAKEUP EQU( 0x1 << 8 );
-- ( RSTC ) WakeUp Reset.VDDCORE rising.
- AT91C_RSTC_RSTTYP_WATCHDOG EQU( 0x2 << 8 );
-- ( RSTC ) Watchdog Reset.Watchdog overflow occured.
- AT91C_RSTC_RSTTYP_SOFTWARE EQU( 0x3 << 8 );
-- ( RSTC ) Software Reset.Processor reset required by the software.
- AT91C_RSTC_RSTTYP_USER EQU( 0x4 << 8 );
-- ( RSTC ) User Reset.NRST pin detected low.
- AT91C_RSTC_RSTTYP_BROWNOUT EQU( 0x5 << 8 );
-- ( RSTC ) Brownout Reset occured.
- AT91C_RSTC_NRSTL EQU( 0x1 << 16 );
-- ( RSTC ) NRST pin level
- AT91C_RSTC_SRCMP EQU( 0x1 << 17 );
-- ( RSTC ) Software Reset Command in Progress.
-/* - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
- AT91C_RSTC_URSTEN EQU( 0x1 << 0 );
-- ( RSTC ) User Reset Enable
- AT91C_RSTC_URSTIEN EQU( 0x1 << 4 );
-- ( RSTC ) User Reset Interrupt Enable
- AT91C_RSTC_ERSTL EQU( 0xF << 8 );
-- ( RSTC ) User Reset Enable
- AT91C_RSTC_BODIEN EQU( 0x1 << 16 );
-- ( RSTC ) Brownout Detection Interrupt Enable
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Reset Controller Interface
+// - *****************************************************************************
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset
+AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset
+AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset
+AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status
+AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status
+AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software.
+AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low.
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured.
+AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level
+AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable
+AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable
+AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable
+AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
-/* - ***************************************************************************** */
-/* - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
- AT91C_RTTC_RTPRES EQU( 0xFFFF << 0 );
-- ( RTTC ) Real - time Timer Prescaler Value
- AT91C_RTTC_ALMIEN EQU( 0x1 << 16 );
-- ( RTTC ) Alarm Interrupt Enable
- AT91C_RTTC_RTTINCIEN EQU( 0x1 << 17 );
-- ( RTTC ) Real Time Timer Increment Interrupt Enable
- AT91C_RTTC_RTTRST EQU( 0x1 << 18 );
-- ( RTTC ) Real Time Timer Restart
-/* - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
- AT91C_RTTC_ALMV EQU( 0x0 << 0 );
-- ( RTTC ) Alarm Value
-/* - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
- AT91C_RTTC_CRTV EQU( 0x0 << 0 );
-- ( RTTC ) Current Real - time Value
-/* - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
- AT91C_RTTC_ALMS EQU( 0x1 << 0 );
-- ( RTTC ) Real - time Alarm Status
- AT91C_RTTC_RTTINC EQU( 0x1 << 1 );
-- ( RTTC ) Real - time Timer Increment
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// - *****************************************************************************
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value
+AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
+AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
+AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status
+AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
-/* - ***************************************************************************** */
-/* - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
- AT91C_PITC_PIV EQU( 0xFFFFF << 0 );
-- ( PITC ) Periodic Interval Value
- AT91C_PITC_PITEN EQU( 0x1 << 24 );
-- ( PITC ) Periodic Interval Timer Enabled
- AT91C_PITC_PITIEN EQU( 0x1 << 25 );
-- ( PITC ) Periodic Interval Timer Interrupt Enable
-/* - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
- AT91C_PITC_PITS EQU( 0x1 << 0 );
-- ( PITC ) Periodic Interval Timer Status
-/* - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
- AT91C_PITC_CPIV EQU( 0xFFFFF << 0 );
-- ( PITC ) Current Periodic Interval Value
- AT91C_PITC_PICNT EQU( 0xFFF << 20 );
-- ( PITC ) Periodic Interval Counter
-/* - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// - *****************************************************************************
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value
+AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
+AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value
+AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
-/* - ***************************************************************************** */
-/* - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
- AT91C_WDTC_WDRSTT EQU( 0x1 << 0 );
-- ( WDTC ) Watchdog Restart
- AT91C_WDTC_KEY EQU( 0xFF << 24 );
-- ( WDTC ) Watchdog KEY Password
-/* - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
- AT91C_WDTC_WDV EQU( 0xFFF << 0 );
-- ( WDTC ) Watchdog Timer Restart
- AT91C_WDTC_WDFIEN EQU( 0x1 << 12 );
-- ( WDTC ) Watchdog Fault Interrupt Enable
- AT91C_WDTC_WDRSTEN EQU( 0x1 << 13 );
-- ( WDTC ) Watchdog Reset Enable
- AT91C_WDTC_WDRPROC EQU( 0x1 << 14 );
-- ( WDTC ) Watchdog Timer Restart
- AT91C_WDTC_WDDIS EQU( 0x1 << 15 );
-- ( WDTC ) Watchdog Disable
- AT91C_WDTC_WDD EQU( 0xFFF << 16 );
-- ( WDTC ) Watchdog Delta Value
- AT91C_WDTC_WDDBGHLT EQU( 0x1 << 28 );
-- ( WDTC ) Watchdog Debug Halt
- AT91C_WDTC_WDIDLEHLT EQU( 0x1 << 29 );
-- ( WDTC ) Watchdog Idle Halt
-/* - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
- AT91C_WDTC_WDUNF EQU( 0x1 << 0 );
-- ( WDTC ) Watchdog Underflow
- AT91C_WDTC_WDERR EQU( 0x1 << 1 );
-- ( WDTC ) Watchdog Error
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// - *****************************************************************************
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart
+AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
+AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
+AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
+AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
+AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
+AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow
+AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */
-/* - ***************************************************************************** */
-/* - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
- AT91C_VREG_PSTDBY EQU( 0x1 << 0 );
-- ( VREG ) Voltage Regulator Power Standby Mode
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// - *****************************************************************************
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Memory Controller Interface */
-/* - ***************************************************************************** */
-/* - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
- AT91C_MC_RCB EQU( 0x1 << 0 );
-- ( MC ) Remap Command Bit
-/* - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
- AT91C_MC_UNDADD EQU( 0x1 << 0 );
-- ( MC ) Undefined Addess Abort Status
- AT91C_MC_MISADD EQU( 0x1 << 1 );
-- ( MC ) Misaligned Addess Abort Status
- AT91C_MC_ABTSZ EQU( 0x3 << 8 );
-- ( MC ) Abort Size Status
- AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 );
-- ( MC ) Byte
- AT91C_MC_ABTSZ_HWORD EQU( 0x1 << 8 );
-- ( MC ) Half - word
- AT91C_MC_ABTSZ_WORD EQU( 0x2 << 8 );
-- ( MC ) Word
- AT91C_MC_ABTTYP EQU( 0x3 << 10 );
-- ( MC ) Abort Type Status
- AT91C_MC_ABTTYP_DATAR EQU( 0x0 << 10 );
-- ( MC ) Data Read
- AT91C_MC_ABTTYP_DATAW EQU( 0x1 << 10 );
-- ( MC ) Data Write
- AT91C_MC_ABTTYP_FETCH EQU( 0x2 << 10 );
-- ( MC ) Code Fetch
- AT91C_MC_MST0 EQU( 0x1 << 16 );
-- ( MC ) Master 0 Abort Source
- AT91C_MC_MST1 EQU( 0x1 << 17 );
-- ( MC ) Master 1 Abort Source
- AT91C_MC_SVMST0 EQU( 0x1 << 24 );
-- ( MC ) Saved Master 0 Abort Source
- AT91C_MC_SVMST1 EQU( 0x1 << 25 );
-- ( MC ) Saved Master 1 Abort Source
-/* - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
- AT91C_MC_FRDY EQU( 0x1 << 0 );
-- ( MC ) Flash Ready
- AT91C_MC_LOCKE EQU( 0x1 << 2 );
-- ( MC ) Lock Error
- AT91C_MC_PROGE EQU( 0x1 << 3 );
-- ( MC ) Programming Error
- AT91C_MC_NEBP EQU( 0x1 << 7 );
-- ( MC ) No Erase Before Programming
- AT91C_MC_FWS EQU( 0x3 << 8 );
-- ( MC ) Flash Wait State
- AT91C_MC_FWS_0FWS EQU( 0x0 << 8 );
-- ( MC ) 1 cycle for Read, 2 for Write operations
- AT91C_MC_FWS_1FWS EQU( 0x1 << 8 );
-- ( MC ) 2 cycles for Read, 3 for Write operations
- AT91C_MC_FWS_2FWS EQU( 0x2 << 8 );
-- ( MC ) 3 cycles for Read, 4 for Write operations
- AT91C_MC_FWS_3FWS EQU( 0x3 << 8 );
-- ( MC ) 4 cycles for Read, 4 for Write operations
- AT91C_MC_FMCN EQU( 0xFF << 16 );
-- ( MC ) Flash Microsecond Cycle Number
-/* - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
- AT91C_MC_FCMD EQU( 0xF << 0 );
-- ( MC ) Flash Command
- AT91C_MC_FCMD_START_PROG EQU( 0x1 );
-- ( MC ) Starts the programming of th epage specified by PAGEN.
- AT91C_MC_FCMD_LOCK EQU( 0x2 );
-- ( MC ) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
- AT91C_MC_FCMD_PROG_AND_LOCK EQU( 0x3 );
-- ( MC ) The lock sequence automatically happens after the programming sequence is completed.
- AT91C_MC_FCMD_UNLOCK EQU( 0x4 );
-- ( MC ) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
- AT91C_MC_FCMD_ERASE_ALL EQU( 0x8 );
-- ( MC ) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
- AT91C_MC_FCMD_SET_GP_NVM EQU( 0xB );
-- ( MC ) Set General Purpose NVM bits.
- AT91C_MC_FCMD_CLR_GP_NVM EQU( 0xD );
-- ( MC ) Clear General Purpose NVM bits.
- AT91C_MC_FCMD_SET_SECURITY EQU( 0xF );
-- ( MC ) Set Security Bit.
- AT91C_MC_PAGEN EQU( 0x3FF << 8 );
-- ( MC ) Page Number
- AT91C_MC_KEY EQU( 0xFF << 24 );
-- ( MC ) Writing Protect Key
-/* - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
- AT91C_MC_SECURITY EQU( 0x1 << 4 );
-- ( MC ) Security Bit Status
- AT91C_MC_GPNVM0 EQU( 0x1 << 8 );
-- ( MC ) Sector 0 Lock Status
- AT91C_MC_GPNVM1 EQU( 0x1 << 9 );
-- ( MC ) Sector 1 Lock Status
- AT91C_MC_GPNVM2 EQU( 0x1 << 10 );
-- ( MC ) Sector 2 Lock Status
- AT91C_MC_GPNVM3 EQU( 0x1 << 11 );
-- ( MC ) Sector 3 Lock Status
- AT91C_MC_GPNVM4 EQU( 0x1 << 12 );
-- ( MC ) Sector 4 Lock Status
- AT91C_MC_GPNVM5 EQU( 0x1 << 13 );
-- ( MC ) Sector 5 Lock Status
- AT91C_MC_GPNVM6 EQU( 0x1 << 14 );
-- ( MC ) Sector 6 Lock Status
- AT91C_MC_GPNVM7 EQU( 0x1 << 15 );
-- ( MC ) Sector 7 Lock Status
- AT91C_MC_LOCKS0 EQU( 0x1 << 16 );
-- ( MC ) Sector 0 Lock Status
- AT91C_MC_LOCKS1 EQU( 0x1 << 17 );
-- ( MC ) Sector 1 Lock Status
- AT91C_MC_LOCKS2 EQU( 0x1 << 18 );
-- ( MC ) Sector 2 Lock Status
- AT91C_MC_LOCKS3 EQU( 0x1 << 19 );
-- ( MC ) Sector 3 Lock Status
- AT91C_MC_LOCKS4 EQU( 0x1 << 20 );
-- ( MC ) Sector 4 Lock Status
- AT91C_MC_LOCKS5 EQU( 0x1 << 21 );
-- ( MC ) Sector 5 Lock Status
- AT91C_MC_LOCKS6 EQU( 0x1 << 22 );
-- ( MC ) Sector 6 Lock Status
- AT91C_MC_LOCKS7 EQU( 0x1 << 23 );
-- ( MC ) Sector 7 Lock Status
- AT91C_MC_LOCKS8 EQU( 0x1 << 24 );
-- ( MC ) Sector 8 Lock Status
- AT91C_MC_LOCKS9 EQU( 0x1 << 25 );
-- ( MC ) Sector 9 Lock Status
- AT91C_MC_LOCKS10 EQU( 0x1 << 26 );
-- ( MC ) Sector 10 Lock Status
- AT91C_MC_LOCKS11 EQU( 0x1 << 27 );
-- ( MC ) Sector 11 Lock Status
- AT91C_MC_LOCKS12 EQU( 0x1 << 28 );
-- ( MC ) Sector 12 Lock Status
- AT91C_MC_LOCKS13 EQU( 0x1 << 29 );
-- ( MC ) Sector 13 Lock Status
- AT91C_MC_LOCKS14 EQU( 0x1 << 30 );
-- ( MC ) Sector 14 Lock Status
- AT91C_MC_LOCKS15 EQU( 0x1 << 31 );
-- ( MC ) Sector 15 Lock Status
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Memory Controller Interface
+// - *****************************************************************************
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status
+AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status
+AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status
+AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte
+AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word
+AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word
+AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status
+AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read
+AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write
+AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch
+AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
+AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
+AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
+AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready
+AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error
+AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error
+AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming
+AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State
+AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations
+AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations
+AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations
+AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations
+AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command
+AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
+AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
+AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.
+AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
+AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number
+AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status
+AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status
+AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status
+AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
+AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
+AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
+AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
+AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
+AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
+AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
+AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
+AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
+AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
+AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
+AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
+AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
+AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
+AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
+AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
+AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
+AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
+AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
+AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/* - ***************************************************************************** */
-/* - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
- AT91C_SPI_SPIEN EQU( 0x1 << 0 );
-- ( SPI ) SPI Enable
- AT91C_SPI_SPIDIS EQU( 0x1 << 1 );
-- ( SPI ) SPI Disable
- AT91C_SPI_SWRST EQU( 0x1 << 7 );
-- ( SPI ) SPI Software reset
- AT91C_SPI_LASTXFER EQU( 0x1 << 24 );
-- ( SPI ) SPI Last Transfer
-/* - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
- AT91C_SPI_MSTR EQU( 0x1 << 0 );
-- ( SPI ) Master / Slave Mode
- AT91C_SPI_PS EQU( 0x1 << 1 );
-- ( SPI ) Peripheral Select
- AT91C_SPI_PS_FIXED EQU( 0x0 << 1 );
-- ( SPI ) Fixed Peripheral Select
- AT91C_SPI_PS_VARIABLE EQU( 0x1 << 1 );
-- ( SPI ) Variable Peripheral Select
- AT91C_SPI_PCSDEC EQU( 0x1 << 2 );
-- ( SPI ) Chip Select Decode
- AT91C_SPI_FDIV EQU( 0x1 << 3 );
-- ( SPI ) Clock Selection
- AT91C_SPI_MODFDIS EQU( 0x1 << 4 );
-- ( SPI ) Mode Fault Detection
- AT91C_SPI_LLB EQU( 0x1 << 7 );
-- ( SPI ) Clock Selection
- AT91C_SPI_PCS EQU( 0xF << 16 );
-- ( SPI ) Peripheral Chip Select
- AT91C_SPI_DLYBCS EQU( 0xFF << 24 );
-- ( SPI ) Delay Between Chip Selects
-/* - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
- AT91C_SPI_RD EQU( 0xFFFF << 0 );
-- ( SPI ) Receive Data
- AT91C_SPI_RPCS EQU( 0xF << 16 );
-- ( SPI ) Peripheral Chip Select Status
-/* - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
- AT91C_SPI_TD EQU( 0xFFFF << 0 );
-- ( SPI ) Transmit Data
- AT91C_SPI_TPCS EQU( 0xF << 16 );
-- ( SPI ) Peripheral Chip Select Status
-/* - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
- AT91C_SPI_RDRF EQU( 0x1 << 0 );
-- ( SPI ) Receive Data Register Full
- AT91C_SPI_TDRE EQU( 0x1 << 1 );
-- ( SPI ) Transmit Data Register Empty
- AT91C_SPI_MODF EQU( 0x1 << 2 );
-- ( SPI ) Mode Fault Error
- AT91C_SPI_OVRES EQU( 0x1 << 3 );
-- ( SPI ) Overrun Error Status
- AT91C_SPI_ENDRX EQU( 0x1 << 4 );
-- ( SPI ) End of Receiver Transfer
- AT91C_SPI_ENDTX EQU( 0x1 << 5 );
-- ( SPI ) End of Receiver Transfer
- AT91C_SPI_RXBUFF EQU( 0x1 << 6 );
-- ( SPI ) RXBUFF Interrupt
- AT91C_SPI_TXBUFE EQU( 0x1 << 7 );
-- ( SPI ) TXBUFE Interrupt
- AT91C_SPI_NSSR EQU( 0x1 << 8 );
-- ( SPI ) NSSR Interrupt
- AT91C_SPI_TXEMPTY EQU( 0x1 << 9 );
-- ( SPI ) TXEMPTY Interrupt
- AT91C_SPI_SPIENS EQU( 0x1 << 16 );
-- ( SPI ) Enable Status
-/* - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-/* - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
- AT91C_SPI_CPOL EQU( 0x1 << 0 );
-- ( SPI ) Clock Polarity
- AT91C_SPI_NCPHA EQU( 0x1 << 1 );
-- ( SPI ) Clock Phase
- AT91C_SPI_CSAAT EQU( 0x1 << 3 );
-- ( SPI ) Chip Select Active After Transfer
- AT91C_SPI_BITS EQU( 0xF << 4 );
-- ( SPI ) Bits Per Transfer
- AT91C_SPI_BITS_8 EQU( 0x0 << 4 );
-- ( SPI ) 8 Bits Per transfer
- AT91C_SPI_BITS_9 EQU( 0x1 << 4 );
-- ( SPI ) 9 Bits Per transfer
- AT91C_SPI_BITS_10 EQU( 0x2 << 4 );
-- ( SPI ) 10 Bits Per transfer
- AT91C_SPI_BITS_11 EQU( 0x3 << 4 );
-- ( SPI ) 11 Bits Per transfer
- AT91C_SPI_BITS_12 EQU( 0x4 << 4 );
-- ( SPI ) 12 Bits Per transfer
- AT91C_SPI_BITS_13 EQU( 0x5 << 4 );
-- ( SPI ) 13 Bits Per transfer
- AT91C_SPI_BITS_14 EQU( 0x6 << 4 );
-- ( SPI ) 14 Bits Per transfer
- AT91C_SPI_BITS_15 EQU( 0x7 << 4 );
-- ( SPI ) 15 Bits Per transfer
- AT91C_SPI_BITS_16 EQU( 0x8 << 4 );
-- ( SPI ) 16 Bits Per transfer
- AT91C_SPI_SCBR EQU( 0xFF << 8 );
-- ( SPI ) Serial Clock Baud Rate
- AT91C_SPI_DLYBS EQU( 0xFF << 16 );
-- ( SPI ) Delay Before SPCK
- AT91C_SPI_DLYBCT EQU( 0xFF << 24 );
-- ( SPI ) Delay Between Consecutive Transfers
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// - *****************************************************************************
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable
+AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable
+AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset
+AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode
+AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select
+AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select
+AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select
+AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode
+AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection
+AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection
+AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection
+AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
+AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data
+AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data
+AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full
+AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty
+AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error
+AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status
+AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt
+AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt
+AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt
+AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt
+AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity
+AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase
+AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer
+AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer
+AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer
+AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer
+AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer
+AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer
+AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer
+AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer
+AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer
+AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer
+AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer
+AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate
+AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
+AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Usart */
-/* - ***************************************************************************** */
-/* - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
- AT91C_US_STTBRK EQU( 0x1 << 9 );
-- ( USART ) Start Break
- AT91C_US_STPBRK EQU( 0x1 << 10 );
-- ( USART ) Stop Break
- AT91C_US_STTTO EQU( 0x1 << 11 );
-- ( USART ) Start Time - out
- AT91C_US_SENDA EQU( 0x1 << 12 );
-- ( USART ) Send Address
- AT91C_US_RSTIT EQU( 0x1 << 13 );
-- ( USART ) Reset Iterations
- AT91C_US_RSTNACK EQU( 0x1 << 14 );
-- ( USART ) Reset Non Acknowledge
- AT91C_US_RETTO EQU( 0x1 << 15 );
-- ( USART ) Rearm Time - out
- AT91C_US_DTREN EQU( 0x1 << 16 );
-- ( USART ) Data Terminal ready Enable
- AT91C_US_DTRDIS EQU( 0x1 << 17 );
-- ( USART ) Data Terminal ready Disable
- AT91C_US_RTSEN EQU( 0x1 << 18 );
-- ( USART ) Request to Send enable
- AT91C_US_RTSDIS EQU( 0x1 << 19 );
-- ( USART ) Request to Send Disable
-/* - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
- AT91C_US_USMODE EQU( 0xF << 0 );
-- ( USART ) Usart mode
- AT91C_US_USMODE_NORMAL EQU( 0x0 );
-- ( USART ) Normal
- AT91C_US_USMODE_RS485 EQU( 0x1 );
-- ( USART ) RS485
- AT91C_US_USMODE_HWHSH EQU( 0x2 );
-- ( USART ) Hardware Handshaking
- AT91C_US_USMODE_MODEM EQU( 0x3 );
-- ( USART ) Modem
- AT91C_US_USMODE_ISO7816_0 EQU( 0x4 );
-- ( USART ) ISO7816 protocol: T = 0
- AT91C_US_USMODE_ISO7816_1 EQU( 0x6 );
-- ( USART ) ISO7816 protocol: T = 1
- AT91C_US_USMODE_IRDA EQU( 0x8 );
-- ( USART ) IrDA
- AT91C_US_USMODE_SWHSH EQU( 0xC );
-- ( USART ) Software Handshaking
- AT91C_US_CLKS EQU( 0x3 << 4 );
-- ( USART ) Clock Selection ( Baud Rate generator Input Clock
- AT91C_US_CLKS_CLOCK EQU( 0x0 << 4 );
- -( USART ) Clock
- AT91C_US_CLKS_FDIV1 EQU( 0x1 << 4 );
- -( USART ) fdiv1
- AT91C_US_CLKS_SLOW EQU( 0x2 << 4 );
- -( USART ) slow_clock( ARM )
- AT91C_US_CLKS_EXT EQU( 0x3 << 4 );
- -( USART ) External( SCK )
- AT91C_US_CHRL EQU( 0x3 << 6 );
- -( USART ) Clock Selection ( Baud Rate generator Input Clock
- AT91C_US_CHRL_5_BITS EQU( 0x0 << 6 );
- -( USART ) Character Length : 5 bits
- AT91C_US_CHRL_6_BITS EQU( 0x1 << 6 );
- -( USART ) Character Length : 6 bits
- AT91C_US_CHRL_7_BITS EQU( 0x2 << 6 );
- -( USART ) Character Length : 7 bits
- AT91C_US_CHRL_8_BITS EQU( 0x3 << 6 );
- -( USART ) Character Length : 8 bits
- AT91C_US_SYNC EQU( 0x1 << 8 );
- -( USART ) Synchronous Mode Select
- AT91C_US_NBSTOP EQU( 0x3 << 12 );
- -( USART ) Number of Stop bits
- AT91C_US_NBSTOP_1_BIT EQU( 0x0 << 12 );
- -( USART ) 1 stop bit
- AT91C_US_NBSTOP_15_BIT EQU( 0x1 << 12 );
- -( USART ) Asynchronous( SYNC = 0 ) 2 stop bits Synchronous( SYNC = 1 ) 2 stop bits
- AT91C_US_NBSTOP_2_BIT EQU( 0x2 << 12 );
- -( USART ) 2 stop bits
- AT91C_US_MSBF EQU( 0x1 << 16 );
- -( USART ) Bit Order
- AT91C_US_MODE9 EQU( 0x1 << 17 );
- -( USART ) 9 - bit Character length
- AT91C_US_CKLO EQU( 0x1 << 18 );
- -( USART ) Clock Output Select
- AT91C_US_OVER EQU( 0x1 << 19 );
- -( USART ) Over Sampling Mode
- AT91C_US_INACK EQU( 0x1 << 20 );
- -( USART ) Inhibit Non Acknowledge
- AT91C_US_DSNACK EQU( 0x1 << 21 );
- -( USART ) Disable Successive NACK
- AT91C_US_MAX_ITER EQU( 0x1 << 24 );
- -( USART ) Number of Repetitions
- AT91C_US_FILTER EQU( 0x1 << 28 );
- -( USART ) Receive Line Filter
-/* - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
- AT91C_US_RXBRK EQU( 0x1 << 2 );
- -( USART ) Break Received / End of Break
- AT91C_US_TIMEOUT EQU( 0x1 << 8 );
- -( USART ) Receiver Time - out
- AT91C_US_ITERATION EQU( 0x1 << 10 );
- -( USART ) Max number of Repetitions Reached
- AT91C_US_NACK EQU( 0x1 << 13 );
- -( USART ) Non Acknowledge
- AT91C_US_RIIC EQU( 0x1 << 16 );
- -( USART ) Ring INdicator Input Change Flag
- AT91C_US_DSRIC EQU( 0x1 << 17 );
- -( USART ) Data Set Ready Input Change Flag
- AT91C_US_DCDIC EQU( 0x1 << 18 );
- -( USART ) Data Carrier Flag
- AT91C_US_CTSIC EQU( 0x1 << 19 );
- -( USART ) Clear To Send Input Change Flag
-/* - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
- AT91C_US_RI EQU( 0x1 << 20 );
- -( USART ) Image of RI Input
- AT91C_US_DSR EQU( 0x1 << 21 );
- -( USART ) Image of DSR Input
- AT91C_US_DCD EQU( 0x1 << 22 );
- -( USART ) Image of DCD Input
- AT91C_US_CTS EQU( 0x1 << 23 );
- -( USART ) Image of CTS Input
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Usart
+// - *****************************************************************************
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break
+AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break
+AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out
+AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address
+AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations
+AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
+AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out
+AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
+AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
+AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable
+AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode
+AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
+AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
+AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
+AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
+AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
+AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
+AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock
+AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1
+AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM)
+AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK)
+AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits
+AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits
+AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits
+AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits
+AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select
+AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits
+AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit
+AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits
+AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order
+AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length
+AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select
+AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode
+AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
+AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK
+AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions
+AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break
+AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out
+AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
+AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge
+AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
+AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
+AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag
+AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input
+AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input
+AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input
+AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
-/* - ***************************************************************************** */
-/* - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
- AT91C_SSC_RXEN EQU( 0x1 << 0 );
- -( SSC ) Receive Enable
- AT91C_SSC_RXDIS EQU( 0x1 << 1 );
- -( SSC ) Receive Disable
- AT91C_SSC_TXEN EQU( 0x1 << 8 );
- -( SSC ) Transmit Enable
- AT91C_SSC_TXDIS EQU( 0x1 << 9 );
- -( SSC ) Transmit Disable
- AT91C_SSC_SWRST EQU( 0x1 << 15 );
- -( SSC ) Software Reset
-/* - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
- AT91C_SSC_CKS EQU( 0x3 << 0 );
- -( SSC ) Receive / Transmit Clock Selection
- AT91C_SSC_CKS_DIV EQU( 0x0 );
- -( SSC ) Divided Clock
- AT91C_SSC_CKS_TK EQU( 0x1 );
- -( SSC ) TK Clock signal
- AT91C_SSC_CKS_RK EQU( 0x2 );
- -( SSC ) RK pin
- AT91C_SSC_CKO EQU( 0x7 << 2 );
- -( SSC ) Receive / Transmit Clock Output Mode Selection
- AT91C_SSC_CKO_NONE EQU( 0x0 << 2 );
- -( SSC ) Receive / Transmit Clock Output Mode:None RK pin: Input - only
- AT91C_SSC_CKO_CONTINOUS EQU( 0x1 << 2 );
- -( SSC ) Continuous Receive / Transmit Clock RK pin:Output
- AT91C_SSC_CKO_DATA_TX EQU( 0x2 << 2 );
- -( SSC ) Receive / Transmit Clock only during data transfers RK pin:Output
- AT91C_SSC_CKI EQU( 0x1 << 5 );
- -( SSC ) Receive / Transmit Clock Inversion
- AT91C_SSC_START EQU( 0xF << 8 );
- -( SSC ) Receive / Transmit Start Selection
- AT91C_SSC_START_CONTINOUS EQU( 0x0 << 8 );
- -( SSC ) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
- AT91C_SSC_START_TX EQU( 0x1 << 8 );
- -( SSC ) Transmit / Receive start
- AT91C_SSC_START_LOW_RF EQU( 0x2 << 8 );
- -( SSC ) Detection of a low level on RF input
- AT91C_SSC_START_HIGH_RF EQU( 0x3 << 8 );
- -( SSC ) Detection of a high level on RF input
- AT91C_SSC_START_FALL_RF EQU( 0x4 << 8 );
- -( SSC ) Detection of a falling edge on RF input
- AT91C_SSC_START_RISE_RF EQU( 0x5 << 8 );
- -( SSC ) Detection of a rising edge on RF input
- AT91C_SSC_START_LEVEL_RF EQU( 0x6 << 8 );
- -( SSC ) Detection of any level change on RF input
- AT91C_SSC_START_EDGE_RF EQU( 0x7 << 8 );
- -( SSC ) Detection of any edge on RF input
- AT91C_SSC_START_0 EQU( 0x8 << 8 );
- -( SSC ) Compare 0
- AT91C_SSC_STTDLY EQU( 0xFF << 16 );
- -( SSC ) Receive / Transmit Start Delay
- AT91C_SSC_PERIOD EQU( 0xFF << 24 );
- -( SSC ) Receive / Transmit Period Divider Selection
-/* - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
- AT91C_SSC_DATLEN EQU( 0x1F << 0 );
- -( SSC ) Data Length
- AT91C_SSC_LOOP EQU( 0x1 << 5 );
- -( SSC ) Loop Mode
- AT91C_SSC_MSBF EQU( 0x1 << 7 );
- -( SSC ) Most Significant Bit First
- AT91C_SSC_DATNB EQU( 0xF << 8 );
- -( SSC ) Data Number per Frame
- AT91C_SSC_FSLEN EQU( 0xF << 16 );
- -( SSC ) Receive / Transmit Frame Sync length
- AT91C_SSC_FSOS EQU( 0x7 << 20 );
- -( SSC ) Receive / Transmit Frame Sync Output Selection
- AT91C_SSC_FSOS_NONE EQU( 0x0 << 20 );
- -( SSC ) Selected Receive / Transmit Frame Sync Signal:None RK pin Input - only
- AT91C_SSC_FSOS_NEGATIVE EQU( 0x1 << 20 );
- -( SSC ) Selected Receive / Transmit Frame Sync Signal:Negative Pulse
- AT91C_SSC_FSOS_POSITIVE EQU( 0x2 << 20 );
- -( SSC ) Selected Receive / Transmit Frame Sync Signal:Positive Pulse
- AT91C_SSC_FSOS_LOW EQU( 0x3 << 20 );
- -( SSC ) Selected Receive / Transmit Frame Sync Signal:Driver Low during data transfer
- AT91C_SSC_FSOS_HIGH EQU( 0x4 << 20 );
- -( SSC ) Selected Receive / Transmit Frame Sync Signal:Driver High during data transfer
- AT91C_SSC_FSOS_TOGGLE EQU( 0x5 << 20 );
- -( SSC ) Selected Receive / Transmit Frame Sync Signal:Toggling at each start of data transfer
- AT91C_SSC_FSEDGE EQU( 0x1 << 24 );
- -( SSC ) Frame Sync Edge Detection
-/* - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
-/* - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
- AT91C_SSC_DATDEF EQU( 0x1 << 5 );
- -( SSC ) Data Default Value
- AT91C_SSC_FSDEN EQU( 0x1 << 23 );
- -( SSC ) Frame Sync Data Enable
-/* - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
- AT91C_SSC_TXRDY EQU( 0x1 << 0 );
- -( SSC ) Transmit Ready
- AT91C_SSC_TXEMPTY EQU( 0x1 << 1 );
- -( SSC ) Transmit Empty
- AT91C_SSC_ENDTX EQU( 0x1 << 2 );
- -( SSC ) End Of Transmission
- AT91C_SSC_TXBUFE EQU( 0x1 << 3 );
- -( SSC ) Transmit Buffer Empty
- AT91C_SSC_RXRDY EQU( 0x1 << 4 );
- -( SSC ) Receive Ready
- AT91C_SSC_OVRUN EQU( 0x1 << 5 );
- -( SSC ) Receive Overrun
- AT91C_SSC_ENDRX EQU( 0x1 << 6 );
- -( SSC ) End of Reception
- AT91C_SSC_RXBUFF EQU( 0x1 << 7 );
- -( SSC ) Receive Buffer Full
- AT91C_SSC_TXSYN EQU( 0x1 << 10 );
- -( SSC ) Transmit Sync
- AT91C_SSC_RXSYN EQU( 0x1 << 11 );
- -( SSC ) Receive Sync
- AT91C_SSC_TXENA EQU( 0x1 << 16 );
- -( SSC ) Transmit Enable
- AT91C_SSC_RXENA EQU( 0x1 << 17 );
- -( SSC ) Receive Enable
-/* - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
-/* - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
-/* - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// - *****************************************************************************
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable
+AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable
+AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable
+AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable
+AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection
+AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock
+AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal
+AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin
+AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
+AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
+AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion
+AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection
+AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start
+AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input
+AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input
+AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input
+AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input
+AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input
+AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input
+AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0
+AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
+AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length
+AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode
+AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First
+AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame
+AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
+AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
+AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value
+AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready
+AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty
+AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission
+AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty
+AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready
+AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun
+AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception
+AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full
+AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync
+AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync
+AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable
+AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* - ***************************************************************************** */
-/* - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
- AT91C_TWI_START EQU( 0x1 << 0 );
- -( TWI ) Send a START Condition
- AT91C_TWI_STOP EQU( 0x1 << 1 );
- -( TWI ) Send a STOP Condition
- AT91C_TWI_MSEN EQU( 0x1 << 2 );
- -( TWI ) TWI Master Transfer Enabled
- AT91C_TWI_MSDIS EQU( 0x1 << 3 );
- -( TWI ) TWI Master Transfer Disabled
- AT91C_TWI_SWRST EQU( 0x1 << 7 );
- -( TWI ) Software Reset
-/* - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
- AT91C_TWI_IADRSZ EQU( 0x3 << 8 );
- -( TWI ) Internal Device Address Size
- AT91C_TWI_IADRSZ_NO EQU( 0x0 << 8 );
- -( TWI ) No internal device address
- AT91C_TWI_IADRSZ_1_BYTE EQU( 0x1 << 8 );
- -( TWI ) One - byte internal device address
- AT91C_TWI_IADRSZ_2_BYTE EQU( 0x2 << 8 );
- -( TWI ) Two - byte internal device address
- AT91C_TWI_IADRSZ_3_BYTE EQU( 0x3 << 8 );
- -( TWI ) Three - byte internal device address
- AT91C_TWI_MREAD EQU( 0x1 << 12 );
- -( TWI ) Master Read Direction
- AT91C_TWI_DADR EQU( 0x7F << 16 );
- -( TWI ) Device Address
-/* - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
- AT91C_TWI_CLDIV EQU( 0xFF << 0 );
- -( TWI ) Clock Low Divider
- AT91C_TWI_CHDIV EQU( 0xFF << 8 );
- -( TWI ) Clock High Divider
- AT91C_TWI_CKDIV EQU( 0x7 << 16 );
- -( TWI ) Clock Divider
-/* - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
- AT91C_TWI_TXCOMP EQU( 0x1 << 0 );
- -( TWI ) Transmission Completed
- AT91C_TWI_RXRDY EQU( 0x1 << 1 );
- -( TWI ) Receive holding register ReaDY
- AT91C_TWI_TXRDY EQU( 0x1 << 2 );
- -( TWI ) Transmit holding register ReaDY
- AT91C_TWI_OVRE EQU( 0x1 << 6 );
- -( TWI ) Overrun Error
- AT91C_TWI_UNRE EQU( 0x1 << 7 );
- -( TWI ) Underrun Error
- AT91C_TWI_NACK EQU( 0x1 << 8 );
- -( TWI ) Not Acknowledged
-/* - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
-/* - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Two-wire Interface
+// - *****************************************************************************
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition
+AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition
+AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled
+AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled
+AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size
+AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address
+AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address
+AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address
+AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address
+AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction
+AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider
+AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider
+AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed
+AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY
+AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY
+AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error
+AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error
+AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR PWMC Channel Interface */
-/* - ***************************************************************************** */
-/* - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
- AT91C_PWMC_CPRE EQU( 0xF << 0 );
- -( PWMC_CH ) Channel Pre - scaler:PWMC_CLKx
- AT91C_PWMC_CPRE_MCK EQU( 0x0 );
- -( PWMC_CH )
- AT91C_PWMC_CPRE_MCKA EQU( 0xB );
- -( PWMC_CH )
- AT91C_PWMC_CPRE_MCKB EQU( 0xC );
- -( PWMC_CH )
- AT91C_PWMC_CALG EQU( 0x1 << 8 );
- -( PWMC_CH ) Channel Alignment
- AT91C_PWMC_CPOL EQU( 0x1 << 9 );
- -( PWMC_CH ) Channel Polarity
- AT91C_PWMC_CPD EQU( 0x1 << 10 );
- -( PWMC_CH ) Channel Update Period
-/* - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
- AT91C_PWMC_CDTY EQU( 0x0 << 0 );
- -( PWMC_CH ) Channel Duty Cycle
-/* - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
- AT91C_PWMC_CPRD EQU( 0x0 << 0 );
- -( PWMC_CH ) Channel Period
-/* - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
- AT91C_PWMC_CCNT EQU( 0x0 << 0 );
- -( PWMC_CH ) Channel Counter
-/* - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
- AT91C_PWMC_CUPD EQU( 0x0 << 0 );
- -( PWMC_CH ) Channel Update
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// - *****************************************************************************
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH)
+AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH)
+AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH)
+AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment
+AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity
+AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
-/* - ***************************************************************************** */
-/* - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
- AT91C_PWMC_DIVA EQU( 0xFF << 0 );
- -( PWMC ) CLKA divide factor.
- AT91C_PWMC_PREA EQU( 0xF << 8 );
- -( PWMC ) Divider Input Clock Prescaler A
- AT91C_PWMC_PREA_MCK EQU( 0x0 << 8 );
- -( PWMC )
- AT91C_PWMC_DIVB EQU( 0xFF << 16 );
- -( PWMC ) CLKB divide factor.
- AT91C_PWMC_PREB EQU( 0xF << 24 );
- -( PWMC ) Divider Input Clock Prescaler B
- AT91C_PWMC_PREB_MCK EQU( 0x0 << 24 );
- -( PWMC )
-/* - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
- AT91C_PWMC_CHID0 EQU( 0x1 << 0 );
- -( PWMC ) Channel ID 0
- AT91C_PWMC_CHID1 EQU( 0x1 << 1 );
- -( PWMC ) Channel ID 1
- AT91C_PWMC_CHID2 EQU( 0x1 << 2 );
- -( PWMC ) Channel ID 2
- AT91C_PWMC_CHID3 EQU( 0x1 << 3 );
- -( PWMC ) Channel ID 3
-/* - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
-/* - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
-/* - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
-/* - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
-/* - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
-/* - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// - *****************************************************************************
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor.
+AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A
+AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC)
+AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
+AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
+AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC)
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0
+AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1
+AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2
+AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR USB Device Interface */
-/* - ***************************************************************************** */
-/* - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
- AT91C_UDP_FRM_NUM EQU( 0x7FF << 0 );
- -( UDP ) Frame Number as Defined in the Packet Field Formats
- AT91C_UDP_FRM_ERR EQU( 0x1 << 16 );
- -( UDP ) Frame Error
- AT91C_UDP_FRM_OK EQU( 0x1 << 17 );
- -( UDP ) Frame OK
-/* - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
- AT91C_UDP_FADDEN EQU( 0x1 << 0 );
- -( UDP ) Function Address Enable
- AT91C_UDP_CONFG EQU( 0x1 << 1 );
- -( UDP ) Configured
- AT91C_UDP_ESR EQU( 0x1 << 2 );
- -( UDP ) Enable Send Resume
- AT91C_UDP_RSMINPR EQU( 0x1 << 3 );
- -( UDP ) A Resume Has Been Sent to the Host
- AT91C_UDP_RMWUPE EQU( 0x1 << 4 );
- -( UDP ) Remote Wake Up Enable
-/* - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
- AT91C_UDP_FADD EQU( 0xFF << 0 );
- -( UDP ) Function Address Value
- AT91C_UDP_FEN EQU( 0x1 << 8 );
- -( UDP ) Function Enable
-/* - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
- AT91C_UDP_EPINT0 EQU( 0x1 << 0 );
- -( UDP ) Endpoint 0 Interrupt
- AT91C_UDP_EPINT1 EQU( 0x1 << 1 );
- -( UDP ) Endpoint 0 Interrupt
- AT91C_UDP_EPINT2 EQU( 0x1 << 2 );
- -( UDP ) Endpoint 2 Interrupt
- AT91C_UDP_EPINT3 EQU( 0x1 << 3 );
- -( UDP ) Endpoint 3 Interrupt
- AT91C_UDP_EPINT4 EQU( 0x1 << 4 );
- -( UDP ) Endpoint 4 Interrupt
- AT91C_UDP_EPINT5 EQU( 0x1 << 5 );
- -( UDP ) Endpoint 5 Interrupt
- AT91C_UDP_RXSUSP EQU( 0x1 << 8 );
- -( UDP ) USB Suspend Interrupt
- AT91C_UDP_RXRSM EQU( 0x1 << 9 );
- -( UDP ) USB Resume Interrupt
- AT91C_UDP_EXTRSM EQU( 0x1 << 10 );
- -( UDP ) USB External Resume Interrupt
- AT91C_UDP_SOFINT EQU( 0x1 << 11 );
- -( UDP ) USB Start Of frame Interrupt
- AT91C_UDP_WAKEUP EQU( 0x1 << 13 );
- -( UDP ) USB Resume Interrupt
-/* - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
-/* - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
-/* - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
- AT91C_UDP_ENDBUSRES EQU( 0x1 << 12 );
- -( UDP ) USB End Of Bus Reset Interrupt
-/* - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
-/* - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
- AT91C_UDP_EP0 EQU( 0x1 << 0 );
- -( UDP ) Reset Endpoint 0
- AT91C_UDP_EP1 EQU( 0x1 << 1 );
- -( UDP ) Reset Endpoint 1
- AT91C_UDP_EP2 EQU( 0x1 << 2 );
- -( UDP ) Reset Endpoint 2
- AT91C_UDP_EP3 EQU( 0x1 << 3 );
- -( UDP ) Reset Endpoint 3
- AT91C_UDP_EP4 EQU( 0x1 << 4 );
- -( UDP ) Reset Endpoint 4
- AT91C_UDP_EP5 EQU( 0x1 << 5 );
- -( UDP ) Reset Endpoint 5
-/* - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
- AT91C_UDP_TXCOMP EQU( 0x1 << 0 );
- -( UDP ) Generates an IN packet with data previously written in the DPR
- AT91C_UDP_RX_DATA_BK0 EQU( 0x1 << 1 );
- -( UDP ) Receive Data Bank 0
- AT91C_UDP_RXSETUP EQU( 0x1 << 2 );
- -( UDP ) Sends STALL to the Host( Control endpoints )
- AT91C_UDP_ISOERROR EQU( 0x1 << 3 );
- -( UDP ) Isochronous error( Isochronous endpoints )
- AT91C_UDP_TXPKTRDY EQU( 0x1 << 4 );
- -( UDP ) Transmit Packet Ready
- AT91C_UDP_FORCESTALL EQU( 0x1 << 5 );
- -( UDP ) Force Stall( used by Control, Bulk and Isochronous endpoints ).
- AT91C_UDP_RX_DATA_BK1 EQU( 0x1 << 6 );
- -( UDP ) Receive Data Bank 1 ( only used by endpoints with ping - pong attributes ).
- AT91C_UDP_DIR EQU( 0x1 << 7 );
- -( UDP ) Transfer Direction
- AT91C_UDP_EPTYPE EQU( 0x7 << 8 );
- -( UDP ) Endpoint type
- AT91C_UDP_EPTYPE_CTRL EQU( 0x0 << 8 );
- -( UDP ) Control
- AT91C_UDP_EPTYPE_ISO_OUT EQU( 0x1 << 8 );
- -( UDP ) Isochronous OUT
- AT91C_UDP_EPTYPE_BULK_OUT EQU( 0x2 << 8 );
- -( UDP ) Bulk OUT
- AT91C_UDP_EPTYPE_INT_OUT EQU( 0x3 << 8 );
- -( UDP ) Interrupt OUT
- AT91C_UDP_EPTYPE_ISO_IN EQU( 0x5 << 8 );
- -( UDP ) Isochronous IN
- AT91C_UDP_EPTYPE_BULK_IN EQU( 0x6 << 8 );
- -( UDP ) Bulk IN
- AT91C_UDP_EPTYPE_INT_IN EQU( 0x7 << 8 );
- -( UDP ) Interrupt IN
- AT91C_UDP_DTGLE EQU( 0x1 << 11 );
- -( UDP ) Data Toggle
- AT91C_UDP_EPEDS EQU( 0x1 << 15 );
- -( UDP ) Endpoint Enable Disable
- AT91C_UDP_RXBYTECNT EQU( 0x7FF << 16 );
- -( UDP ) Number Of Bytes Available in the FIFO
-/* - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
- AT91C_UDP_TXVDIS EQU( 0x1 << 8 );
- -( UDP )
- AT91C_UDP_PUON EQU( 0x1 << 9 );
- -( UDP ) Pull - up ON
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR USB Device Interface
+// - *****************************************************************************
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
+AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error
+AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable
+AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured
+AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume
+AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host
+AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value
+AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt
+AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt
+AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt
+AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt
+AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt
+AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt
+AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
+AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
+AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0
+AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1
+AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2
+AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3
+AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4
+AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR
+AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0
+AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints)
+AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints)
+AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready
+AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction
+AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type
+AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control
+AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT
+AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT
+AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN
+AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN
+AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN
+AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle
+AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
+AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP)
+AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* - ***************************************************************************** */
-/* - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
- AT91C_TC_CLKEN EQU( 0x1 << 0 );
- -( TC ) Counter Clock Enable Command
- AT91C_TC_CLKDIS EQU( 0x1 << 1 );
- -( TC ) Counter Clock Disable Command
- AT91C_TC_SWTRG EQU( 0x1 << 2 );
- -( TC ) Software Trigger Command
-/* - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
- AT91C_TC_CLKS EQU( 0x7 << 0 );
- -( TC ) Clock Selection
- AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU( 0x0 );
- -( TC ) Clock selected:TIMER_DIV1_CLOCK
- AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU( 0x1 );
- -( TC ) Clock selected:TIMER_DIV2_CLOCK
- AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU( 0x2 );
- -( TC ) Clock selected:TIMER_DIV3_CLOCK
- AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU( 0x3 );
- -( TC ) Clock selected:TIMER_DIV4_CLOCK
- AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU( 0x4 );
- -( TC ) Clock selected:TIMER_DIV5_CLOCK
- AT91C_TC_CLKS_XC0 EQU( 0x5 );
- -( TC ) Clock selected:XC0
- AT91C_TC_CLKS_XC1 EQU( 0x6 );
- -( TC ) Clock selected:XC1
- AT91C_TC_CLKS_XC2 EQU( 0x7 );
- -( TC ) Clock selected:XC2
- AT91C_TC_CLKI EQU( 0x1 << 3 );
- -( TC ) Clock Invert
- AT91C_TC_BURST EQU( 0x3 << 4 );
- -( TC ) Burst Signal Selection
- AT91C_TC_BURST_NONE EQU( 0x0 << 4 );
- -( TC ) The clock is not gated by an external signal
- AT91C_TC_BURST_XC0 EQU( 0x1 << 4 );
- -( TC ) XC0 is ANDed with the selected clock
- AT91C_TC_BURST_XC1 EQU( 0x2 << 4 );
- -( TC ) XC1 is ANDed with the selected clock
- AT91C_TC_BURST_XC2 EQU( 0x3 << 4 );
- -( TC ) XC2 is ANDed with the selected clock
- AT91C_TC_CPCSTOP EQU( 0x1 << 6 );
- -( TC ) Counter Clock Stopped with RC Compare
- AT91C_TC_LDBSTOP EQU( 0x1 << 6 );
- -( TC ) Counter Clock Stopped with RB Loading
- AT91C_TC_CPCDIS EQU( 0x1 << 7 );
- -( TC ) Counter Clock Disable with RC Compare
- AT91C_TC_LDBDIS EQU( 0x1 << 7 );
- -( TC ) Counter Clock Disabled with RB Loading
- AT91C_TC_ETRGEDG EQU( 0x3 << 8 );
- -( TC ) External Trigger Edge Selection
- AT91C_TC_ETRGEDG_NONE EQU( 0x0 << 8 );
- -( TC ) Edge:None
- AT91C_TC_ETRGEDG_RISING EQU( 0x1 << 8 );
- -( TC ) Edge:rising edge
- AT91C_TC_ETRGEDG_FALLING EQU( 0x2 << 8 );
- -( TC ) Edge:falling edge
- AT91C_TC_ETRGEDG_BOTH EQU( 0x3 << 8 );
- -( TC ) Edge:each edge
- AT91C_TC_EEVTEDG EQU( 0x3 << 8 );
- -( TC ) External Event Edge Selection
- AT91C_TC_EEVTEDG_NONE EQU( 0x0 << 8 );
- -( TC ) Edge:None
- AT91C_TC_EEVTEDG_RISING EQU( 0x1 << 8 );
- -( TC ) Edge:rising edge
- AT91C_TC_EEVTEDG_FALLING EQU( 0x2 << 8 );
- -( TC ) Edge:falling edge
- AT91C_TC_EEVTEDG_BOTH EQU( 0x3 << 8 );
- -( TC ) Edge:each edge
- AT91C_TC_EEVT EQU( 0x3 << 10 );
- -( TC ) External Event Selection
- AT91C_TC_EEVT_TIOB EQU( 0x0 << 10 );
- -( TC ) Signal selected as external event:TIOB TIOB direction: input
- AT91C_TC_EEVT_XC0 EQU( 0x1 << 10 );
- -( TC ) Signal selected as external event:XC0 TIOB direction: output
- AT91C_TC_EEVT_XC1 EQU( 0x2 << 10 );
- -( TC ) Signal selected as external event:XC1 TIOB direction: output
- AT91C_TC_EEVT_XC2 EQU( 0x3 << 10 );
- -( TC ) Signal selected as external event:XC2 TIOB direction: output
- AT91C_TC_ABETRG EQU( 0x1 << 10 );
- -( TC ) TIOA or TIOB External Trigger Selection
- AT91C_TC_ENETRG EQU( 0x1 << 12 );
- -( TC ) External Event Trigger enable
- AT91C_TC_WAVESEL EQU( 0x3 << 13 );
- -( TC ) Waveform Selection
- AT91C_TC_WAVESEL_UP EQU( 0x0 << 13 );
- -( TC ) UP mode without atomatic trigger on RC Compare
- AT91C_TC_WAVESEL_UPDOWN EQU( 0x1 << 13 );
- -( TC ) UPDOWN mode without automatic trigger on RC Compare
- AT91C_TC_WAVESEL_UP_AUTO EQU( 0x2 << 13 );
- -( TC ) UP mode with automatic trigger on RC Compare
- AT91C_TC_WAVESEL_UPDOWN_AUTO EQU( 0x3 << 13 );
- -( TC ) UPDOWN mode with automatic trigger on RC Compare
- AT91C_TC_CPCTRG EQU( 0x1 << 14 );
- -( TC ) RC Compare Trigger Enable
- AT91C_TC_WAVE EQU( 0x1 << 15 );
- -( TC )
- AT91C_TC_ACPA EQU( 0x3 << 16 );
- -( TC ) RA Compare Effect on TIOA
- AT91C_TC_ACPA_NONE EQU( 0x0 << 16 );
- -( TC ) Effect:none
- AT91C_TC_ACPA_SET EQU( 0x1 << 16 );
- -( TC ) Effect:set
- AT91C_TC_ACPA_CLEAR EQU( 0x2 << 16 );
- -( TC ) Effect:clear
- AT91C_TC_ACPA_TOGGLE EQU( 0x3 << 16 );
- -( TC ) Effect:toggle
- AT91C_TC_LDRA EQU( 0x3 << 16 );
- -( TC ) RA Loading Selection
- AT91C_TC_LDRA_NONE EQU( 0x0 << 16 );
- -( TC ) Edge:None
- AT91C_TC_LDRA_RISING EQU( 0x1 << 16 );
- -( TC ) Edge:rising edge of TIOA
- AT91C_TC_LDRA_FALLING EQU( 0x2 << 16 );
- -( TC ) Edge:falling edge of TIOA
- AT91C_TC_LDRA_BOTH EQU( 0x3 << 16 );
- -( TC ) Edge:each edge of TIOA
- AT91C_TC_ACPC EQU( 0x3 << 18 );
- -( TC ) RC Compare Effect on TIOA
- AT91C_TC_ACPC_NONE EQU( 0x0 << 18 );
- -( TC ) Effect:none
- AT91C_TC_ACPC_SET EQU( 0x1 << 18 );
- -( TC ) Effect:set
- AT91C_TC_ACPC_CLEAR EQU( 0x2 << 18 );
- -( TC ) Effect:clear
- AT91C_TC_ACPC_TOGGLE EQU( 0x3 << 18 );
- -( TC ) Effect:toggle
- AT91C_TC_LDRB EQU( 0x3 << 18 );
- -( TC ) RB Loading Selection
- AT91C_TC_LDRB_NONE EQU( 0x0 << 18 );
- -( TC ) Edge:None
- AT91C_TC_LDRB_RISING EQU( 0x1 << 18 );
- -( TC ) Edge:rising edge of TIOA
- AT91C_TC_LDRB_FALLING EQU( 0x2 << 18 );
- -( TC ) Edge:falling edge of TIOA
- AT91C_TC_LDRB_BOTH EQU( 0x3 << 18 );
- -( TC ) Edge:each edge of TIOA
- AT91C_TC_AEEVT EQU( 0x3 << 20 );
- -( TC ) External Event Effect on TIOA
- AT91C_TC_AEEVT_NONE EQU( 0x0 << 20 );
- -( TC ) Effect:none
- AT91C_TC_AEEVT_SET EQU( 0x1 << 20 );
- -( TC ) Effect:set
- AT91C_TC_AEEVT_CLEAR EQU( 0x2 << 20 );
- -( TC ) Effect:clear
- AT91C_TC_AEEVT_TOGGLE EQU( 0x3 << 20 );
- -( TC ) Effect:toggle
- AT91C_TC_ASWTRG EQU( 0x3 << 22 );
- -( TC ) Software Trigger Effect on TIOA
- AT91C_TC_ASWTRG_NONE EQU( 0x0 << 22 );
- -( TC ) Effect:none
- AT91C_TC_ASWTRG_SET EQU( 0x1 << 22 );
- -( TC ) Effect:set
- AT91C_TC_ASWTRG_CLEAR EQU( 0x2 << 22 );
- -( TC ) Effect:clear
- AT91C_TC_ASWTRG_TOGGLE EQU( 0x3 << 22 );
- -( TC ) Effect:toggle
- AT91C_TC_BCPB EQU( 0x3 << 24 );
- -( TC ) RB Compare Effect on TIOB
- AT91C_TC_BCPB_NONE EQU( 0x0 << 24 );
- -( TC ) Effect:none
- AT91C_TC_BCPB_SET EQU( 0x1 << 24 );
- -( TC ) Effect:set
- AT91C_TC_BCPB_CLEAR EQU( 0x2 << 24 );
- -( TC ) Effect:clear
- AT91C_TC_BCPB_TOGGLE EQU( 0x3 << 24 );
- -( TC ) Effect:toggle
- AT91C_TC_BCPC EQU( 0x3 << 26 );
- -( TC ) RC Compare Effect on TIOB
- AT91C_TC_BCPC_NONE EQU( 0x0 << 26 );
- -( TC ) Effect:none
- AT91C_TC_BCPC_SET EQU( 0x1 << 26 );
- -( TC ) Effect:set
- AT91C_TC_BCPC_CLEAR EQU( 0x2 << 26 );
- -( TC ) Effect:clear
- AT91C_TC_BCPC_TOGGLE EQU( 0x3 << 26 );
- -( TC ) Effect:toggle
- AT91C_TC_BEEVT EQU( 0x3 << 28 );
- -( TC ) External Event Effect on TIOB
- AT91C_TC_BEEVT_NONE EQU( 0x0 << 28 );
- -( TC ) Effect:none
- AT91C_TC_BEEVT_SET EQU( 0x1 << 28 );
- -( TC ) Effect:set
- AT91C_TC_BEEVT_CLEAR EQU( 0x2 << 28 );
- -( TC ) Effect:clear
- AT91C_TC_BEEVT_TOGGLE EQU( 0x3 << 28 );
- -( TC ) Effect:toggle
- AT91C_TC_BSWTRG EQU( 0x3 << 30 );
- -( TC ) Software Trigger Effect on TIOB
- AT91C_TC_BSWTRG_NONE EQU( 0x0 << 30 );
- -( TC ) Effect:none
- AT91C_TC_BSWTRG_SET EQU( 0x1 << 30 );
- -( TC ) Effect:set
- AT91C_TC_BSWTRG_CLEAR EQU( 0x2 << 30 );
- -( TC ) Effect:clear
- AT91C_TC_BSWTRG_TOGGLE EQU( 0x3 << 30 );
- -( TC ) Effect:toggle
-/* - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
- AT91C_TC_COVFS EQU( 0x1 << 0 );
- -( TC ) Counter Overflow
- AT91C_TC_LOVRS EQU( 0x1 << 1 );
- -( TC ) Load Overrun
- AT91C_TC_CPAS EQU( 0x1 << 2 );
- -( TC ) RA Compare
- AT91C_TC_CPBS EQU( 0x1 << 3 );
- -( TC ) RB Compare
- AT91C_TC_CPCS EQU( 0x1 << 4 );
- -( TC ) RC Compare
- AT91C_TC_LDRAS EQU( 0x1 << 5 );
- -( TC ) RA Loading
- AT91C_TC_LDRBS EQU( 0x1 << 6 );
- -( TC ) RB Loading
- AT91C_TC_ETRGS EQU( 0x1 << 7 );
- -( TC ) External Trigger
- AT91C_TC_CLKSTA EQU( 0x1 << 16 );
- -( TC ) Clock Enabling
- AT91C_TC_MTIOA EQU( 0x1 << 17 );
- -( TC ) TIOA Mirror
- AT91C_TC_MTIOB EQU( 0x1 << 18 );
- -( TC ) TIOA Mirror
-/* - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
-/* - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
-/* - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// - *****************************************************************************
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command
+AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command
+AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
+AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0
+AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1
+AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2
+AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert
+AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection
+AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal
+AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock
+AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock
+AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock
+AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare
+AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading
+AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare
+AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading
+AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection
+AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None
+AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge
+AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge
+AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge
+AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection
+AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None
+AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge
+AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge
+AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge
+AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection
+AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
+AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
+AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
+AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
+AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
+AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable
+AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection
+AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
+AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
+AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC)
+AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
+AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none
+AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set
+AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear
+AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle
+AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection
+AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None
+AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
+AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none
+AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set
+AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear
+AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle
+AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection
+AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None
+AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
+AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none
+AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set
+AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear
+AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle
+AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
+AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none
+AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set
+AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear
+AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle
+AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
+AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none
+AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set
+AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear
+AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle
+AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
+AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none
+AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set
+AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear
+AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle
+AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
+AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none
+AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set
+AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear
+AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle
+AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
+AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none
+AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set
+AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear
+AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow
+AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun
+AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare
+AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare
+AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare
+AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading
+AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading
+AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger
+AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling
+AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror
+AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Timer Counter Interface */
-/* - ***************************************************************************** */
-/* - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
- AT91C_TCB_SYNC EQU( 0x1 << 0 );
- -( TCB ) Synchro Command
-/* - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
- AT91C_TCB_TC0XC0S EQU( 0x3 << 0 );
- -( TCB ) External Clock Signal 0 Selection
- AT91C_TCB_TC0XC0S_TCLK0 EQU( 0x0 );
- -( TCB ) TCLK0 connected to XC0
- AT91C_TCB_TC0XC0S_NONE EQU( 0x1 );
- -( TCB ) None signal connected to XC0
- AT91C_TCB_TC0XC0S_TIOA1 EQU( 0x2 );
- -( TCB ) TIOA1 connected to XC0
- AT91C_TCB_TC0XC0S_TIOA2 EQU( 0x3 );
- -( TCB ) TIOA2 connected to XC0
- AT91C_TCB_TC1XC1S EQU( 0x3 << 2 );
- -( TCB ) External Clock Signal 1 Selection
- AT91C_TCB_TC1XC1S_TCLK1 EQU( 0x0 << 2 );
- -( TCB ) TCLK1 connected to XC1
- AT91C_TCB_TC1XC1S_NONE EQU( 0x1 << 2 );
- -( TCB ) None signal connected to XC1
- AT91C_TCB_TC1XC1S_TIOA0 EQU( 0x2 << 2 );
- -( TCB ) TIOA0 connected to XC1
- AT91C_TCB_TC1XC1S_TIOA2 EQU( 0x3 << 2 );
- -( TCB ) TIOA2 connected to XC1
- AT91C_TCB_TC2XC2S EQU( 0x3 << 4 );
- -( TCB ) External Clock Signal 2 Selection
- AT91C_TCB_TC2XC2S_TCLK2 EQU( 0x0 << 4 );
- -( TCB ) TCLK2 connected to XC2
- AT91C_TCB_TC2XC2S_NONE EQU( 0x1 << 4 );
- -( TCB ) None signal connected to XC2
- AT91C_TCB_TC2XC2S_TIOA0 EQU( 0x2 << 4 );
- -( TCB ) TIOA0 connected to XC2
- AT91C_TCB_TC2XC2S_TIOA1 EQU( 0x3 << 4 );
- -( TCB ) TIOA2 connected to XC2
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Timer Counter Interface
+// - *****************************************************************************
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection
+AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0
+AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0
+AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0
+AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0
+AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection
+AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1
+AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1
+AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1
+AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1
+AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection
+AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2
+AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2
+AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2
+AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */
-/* - ***************************************************************************** */
-/* - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
- AT91C_CAN_MTIMEMARK EQU( 0xFFFF << 0 );
- -( CAN_MB ) Mailbox Timemark
- AT91C_CAN_PRIOR EQU( 0xF << 16 );
- -( CAN_MB ) Mailbox Priority
- AT91C_CAN_MOT EQU( 0x7 << 24 );
- -( CAN_MB ) Mailbox Object Type
- AT91C_CAN_MOT_DIS EQU( 0x0 << 24 );
- -( CAN_MB )
- AT91C_CAN_MOT_RX EQU( 0x1 << 24 );
- -( CAN_MB )
- AT91C_CAN_MOT_RXOVERWRITE EQU( 0x2 << 24 );
- -( CAN_MB )
- AT91C_CAN_MOT_TX EQU( 0x3 << 24 );
- -( CAN_MB )
- AT91C_CAN_MOT_CONSUMER EQU( 0x4 << 24 );
- -( CAN_MB )
- AT91C_CAN_MOT_PRODUCER EQU( 0x5 << 24 );
- -( CAN_MB )
-/* - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
- AT91C_CAN_MIDvB EQU( 0x3FFFF << 0 );
- -( CAN_MB ) Complementary bits for identifier in extended mode
- AT91C_CAN_MIDvA EQU( 0x7FF << 18 );
- -( CAN_MB ) Identifier for standard frame mode
- AT91C_CAN_MIDE EQU( 0x1 << 29 );
- -( CAN_MB ) Identifier Version
-/* - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
-/* - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
-/* - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
- AT91C_CAN_MTIMESTAMP EQU( 0xFFFF << 0 );
- -( CAN_MB ) Timer Value
- AT91C_CAN_MDLC EQU( 0xF << 16 );
- -( CAN_MB ) Mailbox Data Length Code
- AT91C_CAN_MRTR EQU( 0x1 << 20 );
- -( CAN_MB ) Mailbox Remote Transmission Request
- AT91C_CAN_MABT EQU( 0x1 << 22 );
- -( CAN_MB ) Mailbox Message Abort
- AT91C_CAN_MRDY EQU( 0x1 << 23 );
- -( CAN_MB ) Mailbox Ready
- AT91C_CAN_MMI EQU( 0x1 << 24 );
- -( CAN_MB ) Mailbox Message Ignored
-/* - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
-/* - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
-/* - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
- AT91C_CAN_MACR EQU( 0x1 << 22 );
- -( CAN_MB ) Abort Request for Mailbox
- AT91C_CAN_MTCR EQU( 0x1 << 23 );
- -( CAN_MB ) Mailbox Transfer Command
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
+// - *****************************************************************************
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
+AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark
+AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
+AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
+AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB)
+AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB)
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB)
+AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB)
+AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB)
+AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB)
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
+AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode
+AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
+AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
+AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value
+AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
+AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
+AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
+AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
+AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
+AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
+AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Control Area Network Interface */
-/* - ***************************************************************************** */
-/* - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
- AT91C_CAN_CANEN EQU( 0x1 << 0 );
- -( CAN ) CAN Controller Enable
- AT91C_CAN_LPM EQU( 0x1 << 1 );
- -( CAN ) Disable / Enable Low Power Mode
- AT91C_CAN_ABM EQU( 0x1 << 2 );
- -( CAN ) Disable / Enable Autobaud / Listen Mode
- AT91C_CAN_OVL EQU( 0x1 << 3 );
- -( CAN ) Disable / Enable Overload Frame
- AT91C_CAN_TEOF EQU( 0x1 << 4 );
- -( CAN ) Time Stamp messages at each end of Frame
- AT91C_CAN_TTM EQU( 0x1 << 5 );
- -( CAN ) Disable / Enable Time Trigger Mode
- AT91C_CAN_TIMFRZ EQU( 0x1 << 6 );
- -( CAN ) Enable Timer Freeze
- AT91C_CAN_DRPT EQU( 0x1 << 7 );
- -( CAN ) Disable Repeat
-/* - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
- AT91C_CAN_MB0 EQU( 0x1 << 0 );
- -( CAN ) Mailbox 0 Flag
- AT91C_CAN_MB1 EQU( 0x1 << 1 );
- -( CAN ) Mailbox 1 Flag
- AT91C_CAN_MB2 EQU( 0x1 << 2 );
- -( CAN ) Mailbox 2 Flag
- AT91C_CAN_MB3 EQU( 0x1 << 3 );
- -( CAN ) Mailbox 3 Flag
- AT91C_CAN_MB4 EQU( 0x1 << 4 );
- -( CAN ) Mailbox 4 Flag
- AT91C_CAN_MB5 EQU( 0x1 << 5 );
- -( CAN ) Mailbox 5 Flag
- AT91C_CAN_MB6 EQU( 0x1 << 6 );
- -( CAN ) Mailbox 6 Flag
- AT91C_CAN_MB7 EQU( 0x1 << 7 );
- -( CAN ) Mailbox 7 Flag
- AT91C_CAN_MB8 EQU( 0x1 << 8 );
- -( CAN ) Mailbox 8 Flag
- AT91C_CAN_MB9 EQU( 0x1 << 9 );
- -( CAN ) Mailbox 9 Flag
- AT91C_CAN_MB10 EQU( 0x1 << 10 );
- -( CAN ) Mailbox 10 Flag
- AT91C_CAN_MB11 EQU( 0x1 << 11 );
- -( CAN ) Mailbox 11 Flag
- AT91C_CAN_MB12 EQU( 0x1 << 12 );
- -( CAN ) Mailbox 12 Flag
- AT91C_CAN_MB13 EQU( 0x1 << 13 );
- -( CAN ) Mailbox 13 Flag
- AT91C_CAN_MB14 EQU( 0x1 << 14 );
- -( CAN ) Mailbox 14 Flag
- AT91C_CAN_MB15 EQU( 0x1 << 15 );
- -( CAN ) Mailbox 15 Flag
- AT91C_CAN_ERRA EQU( 0x1 << 16 );
- -( CAN ) Error Active Mode Flag
- AT91C_CAN_WARN EQU( 0x1 << 17 );
- -( CAN ) Warning Limit Flag
- AT91C_CAN_ERRP EQU( 0x1 << 18 );
- -( CAN ) Error Passive Mode Flag
- AT91C_CAN_BOFF EQU( 0x1 << 19 );
- -( CAN ) Bus Off Mode Flag
- AT91C_CAN_SLEEP EQU( 0x1 << 20 );
- -( CAN ) Sleep Flag
- AT91C_CAN_WAKEUP EQU( 0x1 << 21 );
- -( CAN ) Wakeup Flag
- AT91C_CAN_TOVF EQU( 0x1 << 22 );
- -( CAN ) Timer Overflow Flag
- AT91C_CAN_TSTP EQU( 0x1 << 23 );
- -( CAN ) Timestamp Flag
- AT91C_CAN_CERR EQU( 0x1 << 24 );
- -( CAN ) CRC Error
- AT91C_CAN_SERR EQU( 0x1 << 25 );
- -( CAN ) Stuffing Error
- AT91C_CAN_AERR EQU( 0x1 << 26 );
- -( CAN ) Acknowledgment Error
- AT91C_CAN_FERR EQU( 0x1 << 27 );
- -( CAN ) Form Error
- AT91C_CAN_BERR EQU( 0x1 << 28 );
- -( CAN ) Bit Error
-/* - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
-/* - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
-/* - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
- AT91C_CAN_RBSY EQU( 0x1 << 29 );
- -( CAN ) Receiver Busy
- AT91C_CAN_TBSY EQU( 0x1 << 30 );
- -( CAN ) Transmitter Busy
- AT91C_CAN_OVLY EQU( 0x1 << 31 );
- -( CAN ) Overload Busy
-/* - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
- AT91C_CAN_PHASE2 EQU( 0x7 << 0 );
- -( CAN ) Phase 2 segment
- AT91C_CAN_PHASE1 EQU( 0x7 << 4 );
- -( CAN ) Phase 1 segment
- AT91C_CAN_PROPAG EQU( 0x7 << 8 );
- -( CAN ) Programmation time segment
- AT91C_CAN_SYNC EQU( 0x3 << 12 );
- -( CAN ) Re - synchronization jump width segment
- AT91C_CAN_BRP EQU( 0x7F << 16 );
- -( CAN ) Baudrate Prescaler
- AT91C_CAN_SMP EQU( 0x1 << 24 );
- -( CAN ) Sampling mode
-/* - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
- AT91C_CAN_TIMER EQU( 0xFFFF << 0 );
- -( CAN ) Timer field
-/* - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
-/* - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
- AT91C_CAN_REC EQU( 0xFF << 0 );
- -( CAN ) Receive Error Counter
- AT91C_CAN_TEC EQU( 0xFF << 16 );
- -( CAN ) Transmit Error Counter
-/* - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
- AT91C_CAN_TIMRST EQU( 0x1 << 31 );
- -( CAN ) Timer Reset Field
-/* - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Control Area Network Interface
+// - *****************************************************************************
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
+AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable
+AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode
+AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
+AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame
+AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame
+AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode
+AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze
+AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
+AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag
+AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag
+AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag
+AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag
+AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag
+AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag
+AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag
+AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag
+AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag
+AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag
+AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
+AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
+AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
+AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
+AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
+AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
+AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
+AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
+AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
+AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
+AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag
+AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag
+AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
+AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag
+AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error
+AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error
+AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
+AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error
+AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
+AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy
+AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy
+AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
+AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment
+AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment
+AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment
+AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
+AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
+AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
+AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
+AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter
+AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
+AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
-/* - ***************************************************************************** */
-/* - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */
- AT91C_EMAC_LB EQU( 0x1 << 0 );
- -( EMAC ) Loopback.Optional.When set, loopback signal is at high level.
- AT91C_EMAC_LLB EQU( 0x1 << 1 );
- -( EMAC ) Loopback local.
- AT91C_EMAC_RE EQU( 0x1 << 2 );
- -( EMAC ) Receive enable.
- AT91C_EMAC_TE EQU( 0x1 << 3 );
- -( EMAC ) Transmit enable.
- AT91C_EMAC_MPE EQU( 0x1 << 4 );
- -( EMAC ) Management port enable.
- AT91C_EMAC_CLRSTAT EQU( 0x1 << 5 );
- -( EMAC ) Clear statistics registers.
- AT91C_EMAC_INCSTAT EQU( 0x1 << 6 );
- -( EMAC ) Increment statistics registers.
- AT91C_EMAC_WESTAT EQU( 0x1 << 7 );
- -( EMAC ) Write enable for statistics registers.
- AT91C_EMAC_BP EQU( 0x1 << 8 );
- -( EMAC ) Back pressure.
- AT91C_EMAC_TSTART EQU( 0x1 << 9 );
- -( EMAC ) Start Transmission.
- AT91C_EMAC_THALT EQU( 0x1 << 10 );
- -( EMAC ) Transmission Halt.
- AT91C_EMAC_TPFR EQU( 0x1 << 11 );
- -( EMAC ) Transmit pause frame
- AT91C_EMAC_TZQ EQU( 0x1 << 12 );
- -( EMAC ) Transmit zero quantum pause frame
-/* - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
- AT91C_EMAC_SPD EQU( 0x1 << 0 );
- -( EMAC ) Speed.
- AT91C_EMAC_FD EQU( 0x1 << 1 );
- -( EMAC ) Full duplex.
- AT91C_EMAC_JFRAME EQU( 0x1 << 3 );
- -( EMAC ) Jumbo Frames.
- AT91C_EMAC_CAF EQU( 0x1 << 4 );
- -( EMAC ) Copy all frames.
- AT91C_EMAC_NBC EQU( 0x1 << 5 );
- -( EMAC ) No broadcast.
- AT91C_EMAC_MTI EQU( 0x1 << 6 );
- -( EMAC ) Multicast hash event enable
- AT91C_EMAC_UNI EQU( 0x1 << 7 );
- -( EMAC ) Unicast hash enable.
- AT91C_EMAC_BIG EQU( 0x1 << 8 );
- -( EMAC ) Receive 1522 bytes.
- AT91C_EMAC_EAE EQU( 0x1 << 9 );
- -( EMAC ) External address match enable.
- AT91C_EMAC_CLK EQU( 0x3 << 10 );
- -( EMAC )
- AT91C_EMAC_CLK_HCLK_8 EQU( 0x0 << 10 );
- -( EMAC ) HCLK divided by 8
- AT91C_EMAC_CLK_HCLK_16 EQU( 0x1 << 10 );
- -( EMAC ) HCLK divided by 16
- AT91C_EMAC_CLK_HCLK_32 EQU( 0x2 << 10 );
- -( EMAC ) HCLK divided by 32
- AT91C_EMAC_CLK_HCLK_64 EQU( 0x3 << 10 );
- -( EMAC ) HCLK divided by 64
- AT91C_EMAC_RTY EQU( 0x1 << 12 );
- -( EMAC )
- AT91C_EMAC_PAE EQU( 0x1 << 13 );
- -( EMAC )
- AT91C_EMAC_RBOF EQU( 0x3 << 14 );
- -( EMAC )
- AT91C_EMAC_RBOF_OFFSET_0 EQU( 0x0 << 14 );
- -( EMAC ) no offset from start of receive buffer
- AT91C_EMAC_RBOF_OFFSET_1 EQU( 0x1 << 14 );
- -( EMAC ) one byte offset from start of receive buffer
- AT91C_EMAC_RBOF_OFFSET_2 EQU( 0x2 << 14 );
- -( EMAC ) two bytes offset from start of receive buffer
- AT91C_EMAC_RBOF_OFFSET_3 EQU( 0x3 << 14 );
- -( EMAC ) three bytes offset from start of receive buffer
- AT91C_EMAC_RLCE EQU( 0x1 << 16 );
- -( EMAC ) Receive Length field Checking Enable
- AT91C_EMAC_DRFCS EQU( 0x1 << 17 );
- -( EMAC ) Discard Receive FCS
- AT91C_EMAC_EFRHD EQU( 0x1 << 18 );
- -( EMAC )
- AT91C_EMAC_IRXFCS EQU( 0x1 << 19 );
- -( EMAC ) Ignore RX FCS
-/* - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
- AT91C_EMAC_LINKR EQU( 0x1 << 0 );
- -( EMAC )
- AT91C_EMAC_MDIO EQU( 0x1 << 1 );
- -( EMAC )
- AT91C_EMAC_IDLE EQU( 0x1 << 2 );
- -( EMAC )
-/* - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
- AT91C_EMAC_UBR EQU( 0x1 << 0 );
- -( EMAC )
- AT91C_EMAC_COL EQU( 0x1 << 1 );
- -( EMAC )
- AT91C_EMAC_RLES EQU( 0x1 << 2 );
- -( EMAC )
- AT91C_EMAC_TGO EQU( 0x1 << 3 );
- -( EMAC ) Transmit Go
- AT91C_EMAC_BEX EQU( 0x1 << 4 );
- -( EMAC ) Buffers exhausted mid frame
- AT91C_EMAC_COMP EQU( 0x1 << 5 );
- -( EMAC )
- AT91C_EMAC_UND EQU( 0x1 << 6 );
- -( EMAC )
-/* - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
- AT91C_EMAC_BNA EQU( 0x1 << 0 );
- -( EMAC )
- AT91C_EMAC_REC EQU( 0x1 << 1 );
- -( EMAC )
- AT91C_EMAC_OVR EQU( 0x1 << 2 );
- -( EMAC )
-/* - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
- AT91C_EMAC_MFD EQU( 0x1 << 0 );
- -( EMAC )
- AT91C_EMAC_RCOMP EQU( 0x1 << 1 );
- -( EMAC )
- AT91C_EMAC_RXUBR EQU( 0x1 << 2 );
- -( EMAC )
- AT91C_EMAC_TXUBR EQU( 0x1 << 3 );
- -( EMAC )
- AT91C_EMAC_TUNDR EQU( 0x1 << 4 );
- -( EMAC )
- AT91C_EMAC_RLEX EQU( 0x1 << 5 );
- -( EMAC )
- AT91C_EMAC_TXERR EQU( 0x1 << 6 );
- -( EMAC )
- AT91C_EMAC_TCOMP EQU( 0x1 << 7 );
- -( EMAC )
- AT91C_EMAC_LINK EQU( 0x1 << 9 );
- -( EMAC )
- AT91C_EMAC_ROVR EQU( 0x1 << 10 );
- -( EMAC )
- AT91C_EMAC_HRESP EQU( 0x1 << 11 );
- -( EMAC )
- AT91C_EMAC_PFRE EQU( 0x1 << 12 );
- -( EMAC )
- AT91C_EMAC_PTZ EQU( 0x1 << 13 );
- -( EMAC )
-/* - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
-/* - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
-/* - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
- AT91C_EMAC_DATA EQU( 0xFFFF << 0 );
- -( EMAC )
- AT91C_EMAC_CODE EQU( 0x3 << 16 );
- -( EMAC )
- AT91C_EMAC_REGA EQU( 0x1F << 18 );
- -( EMAC )
- AT91C_EMAC_PHYA EQU( 0x1F << 23 );
- -( EMAC )
- AT91C_EMAC_RW EQU( 0x3 << 28 );
- -( EMAC )
- AT91C_EMAC_SOF EQU( 0x3 << 30 );
- -( EMAC )
-/* - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
- AT91C_EMAC_RMII EQU( 0x1 << 0 );
- -( EMAC ) Reduce MII
-/* - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
- AT91C_EMAC_IP EQU( 0xFFFF << 0 );
- -( EMAC ) ARP request IP address
- AT91C_EMAC_MAG EQU( 0x1 << 16 );
- -( EMAC ) Magic packet event enable
- AT91C_EMAC_ARP EQU( 0x1 << 17 );
- -( EMAC ) ARP request event enable
- AT91C_EMAC_SA1 EQU( 0x1 << 18 );
- -( EMAC ) Specific address register 1 event enable
-/* - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
- AT91C_EMAC_REVREF EQU( 0xFFFF << 0 );
- -( EMAC )
- AT91C_EMAC_PARTREF EQU( 0xFFFF << 16 );
- -( EMAC )
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
+// - *****************************************************************************
+// - -------- EMAC_NCR : (EMAC Offset: 0x0) --------
+AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local.
+AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable.
+AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable.
+AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable.
+AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers.
+AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers.
+AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers.
+AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure.
+AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission.
+AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt.
+AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame
+AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
+AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed.
+AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex.
+AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames.
+AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames.
+AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast.
+AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable
+AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable.
+AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes.
+AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable.
+AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC)
+AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
+AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
+AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
+AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
+AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC)
+AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC)
+AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC)
+AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
+AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
+AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
+AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC)
+AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
+AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC)
+AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC)
+AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC)
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
+AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC)
+AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC)
+AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC)
+AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go
+AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame
+AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC)
+AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC)
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC)
+AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC)
+AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC)
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC)
+AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC)
+AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC)
+AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC)
+AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC)
+AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC)
+AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC)
+AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC)
+AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC)
+AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC)
+AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC)
+AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC)
+AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC)
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC)
+AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC)
+AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC)
+AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC)
+AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC)
+AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC)
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
+AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
+AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address
+AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
+AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable
+AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
+AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC)
+AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC)
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
-/* - ***************************************************************************** */
-/* - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
- AT91C_ADC_SWRST EQU( 0x1 << 0 );
- -( ADC ) Software Reset
- AT91C_ADC_START EQU( 0x1 << 1 );
- -( ADC ) Start Conversion
-/* - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
- AT91C_ADC_TRGEN EQU( 0x1 << 0 );
- -( ADC ) Trigger Enable
- AT91C_ADC_TRGEN_DIS EQU( 0x0 );
- -( ADC ) Hradware triggers are disabled.Starting a conversion is only possible by software
- AT91C_ADC_TRGEN_EN EQU( 0x1 );
- -( ADC ) Hardware trigger selected by TRGSEL field is enabled.
- AT91C_ADC_TRGSEL EQU( 0x7 << 1 );
- -( ADC ) Trigger Selection
- AT91C_ADC_TRGSEL_TIOA0 EQU( 0x0 << 1 );
- -( ADC ) Selected TRGSEL = TIAO0
- AT91C_ADC_TRGSEL_TIOA1 EQU( 0x1 << 1 );
- -( ADC ) Selected TRGSEL = TIAO1
- AT91C_ADC_TRGSEL_TIOA2 EQU( 0x2 << 1 );
- -( ADC ) Selected TRGSEL = TIAO2
- AT91C_ADC_TRGSEL_TIOA3 EQU( 0x3 << 1 );
- -( ADC ) Selected TRGSEL = TIAO3
- AT91C_ADC_TRGSEL_TIOA4 EQU( 0x4 << 1 );
- -( ADC ) Selected TRGSEL = TIAO4
- AT91C_ADC_TRGSEL_TIOA5 EQU( 0x5 << 1 );
- -( ADC ) Selected TRGSEL = TIAO5
- AT91C_ADC_TRGSEL_EXT EQU( 0x6 << 1 );
- -( ADC ) Selected TRGSEL = External Trigger
- AT91C_ADC_LOWRES EQU( 0x1 << 4 );
- -( ADC ) Resolution.
- AT91C_ADC_LOWRES_10_BIT EQU( 0x0 << 4 );
- -( ADC ) 10 - bit resolution
- AT91C_ADC_LOWRES_8_BIT EQU( 0x1 << 4 );
- -( ADC ) 8 - bit resolution
- AT91C_ADC_SLEEP EQU( 0x1 << 5 );
- -( ADC ) Sleep Mode
- AT91C_ADC_SLEEP_NORMAL_MODE EQU( 0x0 << 5 );
- -( ADC ) Normal Mode
- AT91C_ADC_SLEEP_MODE EQU( 0x1 << 5 );
- -( ADC ) Sleep Mode
- AT91C_ADC_PRESCAL EQU( 0x3F << 8 );
- -( ADC ) Prescaler rate selection
- AT91C_ADC_STARTUP EQU( 0x1F << 16 );
- -( ADC ) Startup Time
- AT91C_ADC_SHTIM EQU( 0xF << 24 );
- -( ADC ) Sample & Hold Time
-/* - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
- AT91C_ADC_CH0 EQU( 0x1 << 0 );
- -( ADC ) Channel 0
- AT91C_ADC_CH1 EQU( 0x1 << 1 );
- -( ADC ) Channel 1
- AT91C_ADC_CH2 EQU( 0x1 << 2 );
- -( ADC ) Channel 2
- AT91C_ADC_CH3 EQU( 0x1 << 3 );
- -( ADC ) Channel 3
- AT91C_ADC_CH4 EQU( 0x1 << 4 );
- -( ADC ) Channel 4
- AT91C_ADC_CH5 EQU( 0x1 << 5 );
- -( ADC ) Channel 5
- AT91C_ADC_CH6 EQU( 0x1 << 6 );
- -( ADC ) Channel 6
- AT91C_ADC_CH7 EQU( 0x1 << 7 );
- -( ADC ) Channel 7
-/* - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
-/* - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
-/* - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
- AT91C_ADC_EOC0 EQU( 0x1 << 0 );
- -( ADC ) End of Conversion
- AT91C_ADC_EOC1 EQU( 0x1 << 1 );
- -( ADC ) End of Conversion
- AT91C_ADC_EOC2 EQU( 0x1 << 2 );
- -( ADC ) End of Conversion
- AT91C_ADC_EOC3 EQU( 0x1 << 3 );
- -( ADC ) End of Conversion
- AT91C_ADC_EOC4 EQU( 0x1 << 4 );
- -( ADC ) End of Conversion
- AT91C_ADC_EOC5 EQU( 0x1 << 5 );
- -( ADC ) End of Conversion
- AT91C_ADC_EOC6 EQU( 0x1 << 6 );
- -( ADC ) End of Conversion
- AT91C_ADC_EOC7 EQU( 0x1 << 7 );
- -( ADC ) End of Conversion
- AT91C_ADC_OVRE0 EQU( 0x1 << 8 );
- -( ADC ) Overrun Error
- AT91C_ADC_OVRE1 EQU( 0x1 << 9 );
- -( ADC ) Overrun Error
- AT91C_ADC_OVRE2 EQU( 0x1 << 10 );
- -( ADC ) Overrun Error
- AT91C_ADC_OVRE3 EQU( 0x1 << 11 );
- -( ADC ) Overrun Error
- AT91C_ADC_OVRE4 EQU( 0x1 << 12 );
- -( ADC ) Overrun Error
- AT91C_ADC_OVRE5 EQU( 0x1 << 13 );
- -( ADC ) Overrun Error
- AT91C_ADC_OVRE6 EQU( 0x1 << 14 );
- -( ADC ) Overrun Error
- AT91C_ADC_OVRE7 EQU( 0x1 << 15 );
- -( ADC ) Overrun Error
- AT91C_ADC_DRDY EQU( 0x1 << 16 );
- -( ADC ) Data Ready
- AT91C_ADC_GOVRE EQU( 0x1 << 17 );
- -( ADC ) General Overrun
- AT91C_ADC_ENDRX EQU( 0x1 << 18 );
- -( ADC ) End of Receiver Transfer
- AT91C_ADC_RXBUFF EQU( 0x1 << 19 );
- -( ADC ) RXBUFF Interrupt
-/* - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
- AT91C_ADC_LDATA EQU( 0x3FF << 0 );
- -( ADC ) Last Data Converted
-/* - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
-/* - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
-/* - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
-/* - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
- AT91C_ADC_DATA EQU( 0x3FF << 0 );
- -( ADC ) Converted Data
-/* - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
-/* - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
-/* - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
-/* - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
-/* - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
-/* - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
-/* - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// - *****************************************************************************
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset
+AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable
+AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
+AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection
+AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0
+AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1
+AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2
+AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3
+AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4
+AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5
+AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger
+AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution.
+AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution
+AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution
+AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode
+AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode
+AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection
+AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time
+AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time
+// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0
+AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1
+AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2
+AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3
+AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4
+AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5
+AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6
+AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7
+// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion
+AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion
+AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion
+AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion
+AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion
+AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion
+AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion
+AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion
+AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error
+AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready
+AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun
+AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
+AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
-/* - ***************************************************************************** */
-/* - -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
- AT91C_AES_START EQU( 0x1 << 0 );
- -( AES ) Starts Processing
- AT91C_AES_SWRST EQU( 0x1 << 8 );
- -( AES ) Software Reset
- AT91C_AES_LOADSEED EQU( 0x1 << 16 );
- -( AES ) Random Number Generator Seed Loading
-/* - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
- AT91C_AES_CIPHER EQU( 0x1 << 0 );
- -( AES ) Processing Mode
- AT91C_AES_PROCDLY EQU( 0xF << 4 );
- -( AES ) Processing Delay
- AT91C_AES_SMOD EQU( 0x3 << 8 );
- -( AES ) Start Mode
- AT91C_AES_SMOD_MANUAL EQU( 0x0 << 8 );
- -( AES ) Manual Mode:The START bit in register AES_CR must be set to begin encryption or decryption.
- AT91C_AES_SMOD_AUTO EQU( 0x1 << 8 );
- -( AES ) Auto Mode:no action in AES_CR is necessary( cf datasheet ).
- AT91C_AES_SMOD_PDC EQU( 0x2 << 8 );
- -( AES ) PDC Mode( cf datasheet ).
- AT91C_AES_OPMOD EQU( 0x7 << 12 );
- -( AES ) Operation Mode
- AT91C_AES_OPMOD_ECB EQU( 0x0 << 12 );
- -( AES ) ECB Electronic CodeBook mode.
- AT91C_AES_OPMOD_CBC EQU( 0x1 << 12 );
- -( AES ) CBC Cipher Block Chaining mode.
- AT91C_AES_OPMOD_OFB EQU( 0x2 << 12 );
- -( AES ) OFB Output Feedback mode.
- AT91C_AES_OPMOD_CFB EQU( 0x3 << 12 );
- -( AES ) CFB Cipher Feedback mode.
- AT91C_AES_OPMOD_CTR EQU( 0x4 << 12 );
- -( AES ) CTR Counter mode.
- AT91C_AES_LOD EQU( 0x1 << 15 );
- -( AES ) Last Output Data Mode
- AT91C_AES_CFBS EQU( 0x7 << 16 );
- -( AES ) Cipher Feedback Data Size
- AT91C_AES_CFBS_128_BIT EQU( 0x0 << 16 );
- -( AES ) 128 - bit.
- AT91C_AES_CFBS_64_BIT EQU( 0x1 << 16 );
- -( AES ) 64 - bit.
- AT91C_AES_CFBS_32_BIT EQU( 0x2 << 16 );
- -( AES ) 32 - bit.
- AT91C_AES_CFBS_16_BIT EQU( 0x3 << 16 );
- -( AES ) 16 - bit.
- AT91C_AES_CFBS_8_BIT EQU( 0x4 << 16 );
- -( AES ) 8 - bit.
- AT91C_AES_CKEY EQU( 0xF << 20 );
- -( AES ) Countermeasure Key
- AT91C_AES_CTYPE EQU( 0x1F << 24 );
- -( AES ) Countermeasure Type
- AT91C_AES_CTYPE_TYPE1_EN EQU( 0x1 << 24 );
- -( AES ) Countermeasure type 1 is enabled.
- AT91C_AES_CTYPE_TYPE2_EN EQU( 0x2 << 24 );
- -( AES ) Countermeasure type 2 is enabled.
- AT91C_AES_CTYPE_TYPE3_EN EQU( 0x4 << 24 );
- -( AES ) Countermeasure type 3 is enabled.
- AT91C_AES_CTYPE_TYPE4_EN EQU( 0x8 << 24 );
- -( AES ) Countermeasure type 4 is enabled.
- AT91C_AES_CTYPE_TYPE5_EN EQU( 0x10 << 24 );
- -( AES ) Countermeasure type 5 is enabled.
-/* - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
- AT91C_AES_DATRDY EQU( 0x1 << 0 );
- -( AES ) DATRDY
- AT91C_AES_ENDRX EQU( 0x1 << 1 );
- -( AES ) PDC Read Buffer End
- AT91C_AES_ENDTX EQU( 0x1 << 2 );
- -( AES ) PDC Write Buffer End
- AT91C_AES_RXBUFF EQU( 0x1 << 3 );
- -( AES ) PDC Read Buffer Full
- AT91C_AES_TXBUFE EQU( 0x1 << 4 );
- -( AES ) PDC Write Buffer Empty
- AT91C_AES_URAD EQU( 0x1 << 8 );
- -( AES ) Unspecified Register Access Detection
-/* - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
-/* - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
-/* - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
- AT91C_AES_URAT EQU( 0x7 << 12 );
- -( AES ) Unspecified Register Access Type Status
- AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU( 0x0 << 12 );
- -( AES ) Input data register written during the data processing in PDC mode.
- AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU( 0x1 << 12 );
- -( AES ) Output data register read during the data processing.
- AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU( 0x2 << 12 );
- -( AES ) Mode register written during the data processing.
- AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU( 0x3 << 12 );
- -( AES ) Output data register read during the sub - keys generation.
- AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU( 0x4 << 12 );
- -( AES ) Mode register written during the sub - keys generation.
- AT91C_AES_URAT_WO_REG_READ EQU( 0x5 << 12 );
- -( AES ) Write - only register read access.
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard
+// - *****************************************************************************
+// - -------- AES_CR : (AES Offset: 0x0) Control Register --------
+AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing
+AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset
+AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register --------
+AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode
+AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay
+AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode
+AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet).
+AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode
+AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
+AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
+AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
+AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
+AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode.
+AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode
+AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
+AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit.
+AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit.
+AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit.
+AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit.
+AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit.
+AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key
+AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type
+AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
+AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
+AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
+AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
+AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
+AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY
+AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End
+AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End
+AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full
+AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty
+AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
+AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
-/* - ***************************************************************************** */
-/* - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
-/* - ***************************************************************************** */
-/* - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
- AT91C_TDES_START EQU( 0x1 << 0 );
- -( TDES ) Starts Processing
- AT91C_TDES_SWRST EQU( 0x1 << 8 );
- -( TDES ) Software Reset
-/* - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
- AT91C_TDES_CIPHER EQU( 0x1 << 0 );
- -( TDES ) Processing Mode
- AT91C_TDES_TDESMOD EQU( 0x1 << 1 );
- -( TDES ) Single or Triple DES Mode
- AT91C_TDES_KEYMOD EQU( 0x1 << 4 );
- -( TDES ) Key Mode
- AT91C_TDES_SMOD EQU( 0x3 << 8 );
- -( TDES ) Start Mode
- AT91C_TDES_SMOD_MANUAL EQU( 0x0 << 8 );
- -( TDES ) Manual Mode:The START bit in register TDES_CR must be set to begin encryption or decryption.
- AT91C_TDES_SMOD_AUTO EQU( 0x1 << 8 );
- -( TDES ) Auto Mode:no action in TDES_CR is necessary( cf datasheet ).
- AT91C_TDES_SMOD_PDC EQU( 0x2 << 8 );
- -( TDES ) PDC Mode( cf datasheet ).
- AT91C_TDES_OPMOD EQU( 0x3 << 12 );
- -( TDES ) Operation Mode
- AT91C_TDES_OPMOD_ECB EQU( 0x0 << 12 );
- -( TDES ) ECB Electronic CodeBook mode.
- AT91C_TDES_OPMOD_CBC EQU( 0x1 << 12 );
- -( TDES ) CBC Cipher Block Chaining mode.
- AT91C_TDES_OPMOD_OFB EQU( 0x2 << 12 );
- -( TDES ) OFB Output Feedback mode.
- AT91C_TDES_OPMOD_CFB EQU( 0x3 << 12 );
- -( TDES ) CFB Cipher Feedback mode.
- AT91C_TDES_LOD EQU( 0x1 << 15 );
- -( TDES ) Last Output Data Mode
- AT91C_TDES_CFBS EQU( 0x3 << 16 );
- -( TDES ) Cipher Feedback Data Size
- AT91C_TDES_CFBS_64_BIT EQU( 0x0 << 16 );
- -( TDES ) 64 - bit.
- AT91C_TDES_CFBS_32_BIT EQU( 0x1 << 16 );
- -( TDES ) 32 - bit.
- AT91C_TDES_CFBS_16_BIT EQU( 0x2 << 16 );
- -( TDES ) 16 - bit.
- AT91C_TDES_CFBS_8_BIT EQU( 0x3 << 16 );
- -( TDES ) 8 - bit.
-/* - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
- AT91C_TDES_DATRDY EQU( 0x1 << 0 );
- -( TDES ) DATRDY
- AT91C_TDES_ENDRX EQU( 0x1 << 1 );
- -( TDES ) PDC Read Buffer End
- AT91C_TDES_ENDTX EQU( 0x1 << 2 );
- -( TDES ) PDC Write Buffer End
- AT91C_TDES_RXBUFF EQU( 0x1 << 3 );
- -( TDES ) PDC Read Buffer Full
- AT91C_TDES_TXBUFE EQU( 0x1 << 4 );
- -( TDES ) PDC Write Buffer Empty
- AT91C_TDES_URAD EQU( 0x1 << 8 );
- -( TDES ) Unspecified Register Access Detection
-/* - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
-/* - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
-/* - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
- AT91C_TDES_URAT EQU( 0x3 << 12 );
- -( TDES ) Unspecified Register Access Type Status
- AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU( 0x0 << 12 );
- -( TDES ) Input data register written during the data processing in PDC mode.
- AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU( 0x1 << 12 );
- -( TDES ) Output data register read during the data processing.
- AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU( 0x2 << 12 );
- -( TDES ) Mode register written during the data processing.
- AT91C_TDES_URAT_WO_REG_READ EQU( 0x3 << 12 );
- -( TDES ) Write - only register read access.
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
+// - *****************************************************************************
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
+AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing
+AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
+AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode
+AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode
+AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode
+AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode
+AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet).
+AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode
+AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
+AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
+AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
+AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
+AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
+AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
+AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit.
+AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit.
+AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit.
+AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit.
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
+AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY
+AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End
+AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End
+AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full
+AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty
+AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
+AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
-/* - ***************************************************************************** */
-/* - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
-/* - ***************************************************************************** */
-/* - ========== Register definition for SYS peripheral ========== */
-/* - ========== Register definition for AIC peripheral ========== */
- AT91C_AIC_IVR EQU( 0xFFFFF100 );
- -( AIC ) IRQ Vector Register
- AT91C_AIC_SMR EQU( 0xFFFFF000 );
- -( AIC ) Source Mode Register
- AT91C_AIC_FVR EQU( 0xFFFFF104 );
- -( AIC ) FIQ Vector Register
- AT91C_AIC_DCR EQU( 0xFFFFF138 );
- -( AIC ) Debug Control Register( Protect )
- AT91C_AIC_EOICR EQU( 0xFFFFF130 );
- -( AIC ) End of Interrupt Command Register
- AT91C_AIC_SVR EQU( 0xFFFFF080 );
- -( AIC ) Source Vector Register
- AT91C_AIC_FFSR EQU( 0xFFFFF148 );
- -( AIC ) Fast Forcing Status Register
- AT91C_AIC_ICCR EQU( 0xFFFFF128 );
- -( AIC ) Interrupt Clear Command Register
- AT91C_AIC_ISR EQU( 0xFFFFF108 );
- -( AIC ) Interrupt Status Register
- AT91C_AIC_IMR EQU( 0xFFFFF110 );
- -( AIC ) Interrupt Mask Register
- AT91C_AIC_IPR EQU( 0xFFFFF10C );
- -( AIC ) Interrupt Pending Register
- AT91C_AIC_FFER EQU( 0xFFFFF140 );
- -( AIC ) Fast Forcing Enable Register
- AT91C_AIC_IECR EQU( 0xFFFFF120 );
- -( AIC ) Interrupt Enable Command Register
- AT91C_AIC_ISCR EQU( 0xFFFFF12C );
- -( AIC ) Interrupt Set Command Register
- AT91C_AIC_FFDR EQU( 0xFFFFF144 );
- -( AIC ) Fast Forcing Disable Register
- AT91C_AIC_CISR EQU( 0xFFFFF114 );
- -( AIC ) Core Interrupt Status Register
- AT91C_AIC_IDCR EQU( 0xFFFFF124 );
- -( AIC ) Interrupt Disable Command Register
- AT91C_AIC_SPU EQU( 0xFFFFF134 );
- -( AIC ) Spurious Vector Register
-/* - ========== Register definition for PDC_DBGU peripheral ========== */
- AT91C_DBGU_TCR EQU( 0xFFFFF30C );
- -( PDC_DBGU ) Transmit Counter Register
- AT91C_DBGU_RNPR EQU( 0xFFFFF310 );
- -( PDC_DBGU ) Receive Next Pointer Register
- AT91C_DBGU_TNPR EQU( 0xFFFFF318 );
- -( PDC_DBGU ) Transmit Next Pointer Register
- AT91C_DBGU_TPR EQU( 0xFFFFF308 );
- -( PDC_DBGU ) Transmit Pointer Register
- AT91C_DBGU_RPR EQU( 0xFFFFF300 );
- -( PDC_DBGU ) Receive Pointer Register
- AT91C_DBGU_RCR EQU( 0xFFFFF304 );
- -( PDC_DBGU ) Receive Counter Register
- AT91C_DBGU_RNCR EQU( 0xFFFFF314 );
- -( PDC_DBGU ) Receive Next Counter Register
- AT91C_DBGU_PTCR EQU( 0xFFFFF320 );
- -( PDC_DBGU ) PDC Transfer Control Register
- AT91C_DBGU_PTSR EQU( 0xFFFFF324 );
- -( PDC_DBGU ) PDC Transfer Status Register
- AT91C_DBGU_TNCR EQU( 0xFFFFF31C );
- -( PDC_DBGU ) Transmit Next Counter Register
-/* - ========== Register definition for DBGU peripheral ========== */
- AT91C_DBGU_EXID EQU( 0xFFFFF244 );
- -( DBGU ) Chip ID Extension Register
- AT91C_DBGU_BRGR EQU( 0xFFFFF220 );
- -( DBGU ) Baud Rate Generator Register
- AT91C_DBGU_IDR EQU( 0xFFFFF20C );
- -( DBGU ) Interrupt Disable Register
- AT91C_DBGU_CSR EQU( 0xFFFFF214 );
- -( DBGU ) Channel Status Register
- AT91C_DBGU_CIDR EQU( 0xFFFFF240 );
- -( DBGU ) Chip ID Register
- AT91C_DBGU_MR EQU( 0xFFFFF204 );
- -( DBGU ) Mode Register
- AT91C_DBGU_IMR EQU( 0xFFFFF210 );
- -( DBGU ) Interrupt Mask Register
- AT91C_DBGU_CR EQU( 0xFFFFF200 );
- -( DBGU ) Control Register
- AT91C_DBGU_FNTR EQU( 0xFFFFF248 );
- -( DBGU ) Force NTRST Register
- AT91C_DBGU_THR EQU( 0xFFFFF21C );
- -( DBGU ) Transmitter Holding Register
- AT91C_DBGU_RHR EQU( 0xFFFFF218 );
- -( DBGU ) Receiver Holding Register
- AT91C_DBGU_IER EQU( 0xFFFFF208 );
- -( DBGU ) Interrupt Enable Register
-/* - ========== Register definition for PIOA peripheral ========== */
- AT91C_PIOA_ODR EQU( 0xFFFFF414 );
- -( PIOA ) Output Disable Registerr
- AT91C_PIOA_SODR EQU( 0xFFFFF430 );
- -( PIOA ) Set Output Data Register
- AT91C_PIOA_ISR EQU( 0xFFFFF44C );
- -( PIOA ) Interrupt Status Register
- AT91C_PIOA_ABSR EQU( 0xFFFFF478 );
- -( PIOA ) AB Select Status Register
- AT91C_PIOA_IER EQU( 0xFFFFF440 );
- -( PIOA ) Interrupt Enable Register
- AT91C_PIOA_PPUDR EQU( 0xFFFFF460 );
- -( PIOA ) Pull - up Disable Register
- AT91C_PIOA_IMR EQU( 0xFFFFF448 );
- -( PIOA ) Interrupt Mask Register
- AT91C_PIOA_PER EQU( 0xFFFFF400 );
- -( PIOA ) PIO Enable Register
- AT91C_PIOA_IFDR EQU( 0xFFFFF424 );
- -( PIOA ) Input Filter Disable Register
- AT91C_PIOA_OWDR EQU( 0xFFFFF4A4 );
- -( PIOA ) Output Write Disable Register
- AT91C_PIOA_MDSR EQU( 0xFFFFF458 );
- -( PIOA ) Multi - driver Status Register
- AT91C_PIOA_IDR EQU( 0xFFFFF444 );
- -( PIOA ) Interrupt Disable Register
- AT91C_PIOA_ODSR EQU( 0xFFFFF438 );
- -( PIOA ) Output Data Status Register
- AT91C_PIOA_PPUSR EQU( 0xFFFFF468 );
- -( PIOA ) Pull - up Status Register
- AT91C_PIOA_OWSR EQU( 0xFFFFF4A8 );
- -( PIOA ) Output Write Status Register
- AT91C_PIOA_BSR EQU( 0xFFFFF474 );
- -( PIOA ) Select B Register
- AT91C_PIOA_OWER EQU( 0xFFFFF4A0 );
- -( PIOA ) Output Write Enable Register
- AT91C_PIOA_IFER EQU( 0xFFFFF420 );
- -( PIOA ) Input Filter Enable Register
- AT91C_PIOA_PDSR EQU( 0xFFFFF43C );
- -( PIOA ) Pin Data Status Register
- AT91C_PIOA_PPUER EQU( 0xFFFFF464 );
- -( PIOA ) Pull - up Enable Register
- AT91C_PIOA_OSR EQU( 0xFFFFF418 );
- -( PIOA ) Output Status Register
- AT91C_PIOA_ASR EQU( 0xFFFFF470 );
- -( PIOA ) Select A Register
- AT91C_PIOA_MDDR EQU( 0xFFFFF454 );
- -( PIOA ) Multi - driver Disable Register
- AT91C_PIOA_CODR EQU( 0xFFFFF434 );
- -( PIOA ) Clear Output Data Register
- AT91C_PIOA_MDER EQU( 0xFFFFF450 );
- -( PIOA ) Multi - driver Enable Register
- AT91C_PIOA_PDR EQU( 0xFFFFF404 );
- -( PIOA ) PIO Disable Register
- AT91C_PIOA_IFSR EQU( 0xFFFFF428 );
- -( PIOA ) Input Filter Status Register
- AT91C_PIOA_OER EQU( 0xFFFFF410 );
- -( PIOA ) Output Enable Register
- AT91C_PIOA_PSR EQU( 0xFFFFF408 );
- -( PIOA ) PIO Status Register
-/* - ========== Register definition for PIOB peripheral ========== */
- AT91C_PIOB_OWDR EQU( 0xFFFFF6A4 );
- -( PIOB ) Output Write Disable Register
- AT91C_PIOB_MDER EQU( 0xFFFFF650 );
- -( PIOB ) Multi - driver Enable Register
- AT91C_PIOB_PPUSR EQU( 0xFFFFF668 );
- -( PIOB ) Pull - up Status Register
- AT91C_PIOB_IMR EQU( 0xFFFFF648 );
- -( PIOB ) Interrupt Mask Register
- AT91C_PIOB_ASR EQU( 0xFFFFF670 );
- -( PIOB ) Select A Register
- AT91C_PIOB_PPUDR EQU( 0xFFFFF660 );
- -( PIOB ) Pull - up Disable Register
- AT91C_PIOB_PSR EQU( 0xFFFFF608 );
- -( PIOB ) PIO Status Register
- AT91C_PIOB_IER EQU( 0xFFFFF640 );
- -( PIOB ) Interrupt Enable Register
- AT91C_PIOB_CODR EQU( 0xFFFFF634 );
- -( PIOB ) Clear Output Data Register
- AT91C_PIOB_OWER EQU( 0xFFFFF6A0 );
- -( PIOB ) Output Write Enable Register
- AT91C_PIOB_ABSR EQU( 0xFFFFF678 );
- -( PIOB ) AB Select Status Register
- AT91C_PIOB_IFDR EQU( 0xFFFFF624 );
- -( PIOB ) Input Filter Disable Register
- AT91C_PIOB_PDSR EQU( 0xFFFFF63C );
- -( PIOB ) Pin Data Status Register
- AT91C_PIOB_IDR EQU( 0xFFFFF644 );
- -( PIOB ) Interrupt Disable Register
- AT91C_PIOB_OWSR EQU( 0xFFFFF6A8 );
- -( PIOB ) Output Write Status Register
- AT91C_PIOB_PDR EQU( 0xFFFFF604 );
- -( PIOB ) PIO Disable Register
- AT91C_PIOB_ODR EQU( 0xFFFFF614 );
- -( PIOB ) Output Disable Registerr
- AT91C_PIOB_IFSR EQU( 0xFFFFF628 );
- -( PIOB ) Input Filter Status Register
- AT91C_PIOB_PPUER EQU( 0xFFFFF664 );
- -( PIOB ) Pull - up Enable Register
- AT91C_PIOB_SODR EQU( 0xFFFFF630 );
- -( PIOB ) Set Output Data Register
- AT91C_PIOB_ISR EQU( 0xFFFFF64C );
- -( PIOB ) Interrupt Status Register
- AT91C_PIOB_ODSR EQU( 0xFFFFF638 );
- -( PIOB ) Output Data Status Register
- AT91C_PIOB_OSR EQU( 0xFFFFF618 );
- -( PIOB ) Output Status Register
- AT91C_PIOB_MDSR EQU( 0xFFFFF658 );
- -( PIOB ) Multi - driver Status Register
- AT91C_PIOB_IFER EQU( 0xFFFFF620 );
- -( PIOB ) Input Filter Enable Register
- AT91C_PIOB_BSR EQU( 0xFFFFF674 );
- -( PIOB ) Select B Register
- AT91C_PIOB_MDDR EQU( 0xFFFFF654 );
- -( PIOB ) Multi - driver Disable Register
- AT91C_PIOB_OER EQU( 0xFFFFF610 );
- -( PIOB ) Output Enable Register
- AT91C_PIOB_PER EQU( 0xFFFFF600 );
- -( PIOB ) PIO Enable Register
-/* - ========== Register definition for CKGR peripheral ========== */
- AT91C_CKGR_MOR EQU( 0xFFFFFC20 );
- -( CKGR ) Main Oscillator Register
- AT91C_CKGR_PLLR EQU( 0xFFFFFC2C );
- -( CKGR ) PLL Register
- AT91C_CKGR_MCFR EQU( 0xFFFFFC24 );
- -( CKGR ) Main Clock Frequency Register
-/* - ========== Register definition for PMC peripheral ========== */
- AT91C_PMC_IDR EQU( 0xFFFFFC64 );
- -( PMC ) Interrupt Disable Register
- AT91C_PMC_MOR EQU( 0xFFFFFC20 );
- -( PMC ) Main Oscillator Register
- AT91C_PMC_PLLR EQU( 0xFFFFFC2C );
- -( PMC ) PLL Register
- AT91C_PMC_PCER EQU( 0xFFFFFC10 );
- -( PMC ) Peripheral Clock Enable Register
- AT91C_PMC_PCKR EQU( 0xFFFFFC40 );
- -( PMC ) Programmable Clock Register
- AT91C_PMC_MCKR EQU( 0xFFFFFC30 );
- -( PMC ) Master Clock Register
- AT91C_PMC_SCDR EQU( 0xFFFFFC04 );
- -( PMC ) System Clock Disable Register
- AT91C_PMC_PCDR EQU( 0xFFFFFC14 );
- -( PMC ) Peripheral Clock Disable Register
- AT91C_PMC_SCSR EQU( 0xFFFFFC08 );
- -( PMC ) System Clock Status Register
- AT91C_PMC_PCSR EQU( 0xFFFFFC18 );
- -( PMC ) Peripheral Clock Status Register
- AT91C_PMC_MCFR EQU( 0xFFFFFC24 );
- -( PMC ) Main Clock Frequency Register
- AT91C_PMC_SCER EQU( 0xFFFFFC00 );
- -( PMC ) System Clock Enable Register
- AT91C_PMC_IMR EQU( 0xFFFFFC6C );
- -( PMC ) Interrupt Mask Register
- AT91C_PMC_IER EQU( 0xFFFFFC60 );
- -( PMC ) Interrupt Enable Register
- AT91C_PMC_SR EQU( 0xFFFFFC68 );
- -( PMC ) Status Register
-/* - ========== Register definition for RSTC peripheral ========== */
- AT91C_RSTC_RCR EQU( 0xFFFFFD00 );
- -( RSTC ) Reset Control Register
- AT91C_RSTC_RMR EQU( 0xFFFFFD08 );
- -( RSTC ) Reset Mode Register
- AT91C_RSTC_RSR EQU( 0xFFFFFD04 );
- -( RSTC ) Reset Status Register
-/* - ========== Register definition for RTTC peripheral ========== */
- AT91C_RTTC_RTSR EQU( 0xFFFFFD2C );
- -( RTTC ) Real - time Status Register
- AT91C_RTTC_RTMR EQU( 0xFFFFFD20 );
- -( RTTC ) Real - time Mode Register
- AT91C_RTTC_RTVR EQU( 0xFFFFFD28 );
- -( RTTC ) Real - time Value Register
- AT91C_RTTC_RTAR EQU( 0xFFFFFD24 );
- -( RTTC ) Real - time Alarm Register
-/* - ========== Register definition for PITC peripheral ========== */
- AT91C_PITC_PIVR EQU( 0xFFFFFD38 );
- -( PITC ) Period Interval Value Register
- AT91C_PITC_PISR EQU( 0xFFFFFD34 );
- -( PITC ) Period Interval Status Register
- AT91C_PITC_PIIR EQU( 0xFFFFFD3C );
- -( PITC ) Period Interval Image Register
- AT91C_PITC_PIMR EQU( 0xFFFFFD30 );
- -( PITC ) Period Interval Mode Register
-/* - ========== Register definition for WDTC peripheral ========== */
- AT91C_WDTC_WDCR EQU( 0xFFFFFD40 );
- -( WDTC ) Watchdog Control Register
- AT91C_WDTC_WDSR EQU( 0xFFFFFD48 );
- -( WDTC ) Watchdog Status Register
- AT91C_WDTC_WDMR EQU( 0xFFFFFD44 );
- -( WDTC ) Watchdog Mode Register
-/* - ========== Register definition for VREG peripheral ========== */
- AT91C_VREG_MR EQU( 0xFFFFFD60 );
- -( VREG ) Voltage Regulator Mode Register
-/* - ========== Register definition for MC peripheral ========== */
- AT91C_MC_ASR EQU( 0xFFFFFF04 );
- -( MC ) MC Abort Status Register
- AT91C_MC_RCR EQU( 0xFFFFFF00 );
- -( MC ) MC Remap Control Register
- AT91C_MC_FCR EQU( 0xFFFFFF64 );
- -( MC ) MC Flash Command Register
- AT91C_MC_AASR EQU( 0xFFFFFF08 );
- -( MC ) MC Abort Address Status Register
- AT91C_MC_FSR EQU( 0xFFFFFF68 );
- -( MC ) MC Flash Status Register
- AT91C_MC_FMR EQU( 0xFFFFFF60 );
- -( MC ) MC Flash Mode Register
-/* - ========== Register definition for PDC_SPI1 peripheral ========== */
- AT91C_SPI1_PTCR EQU( 0xFFFE4120 );
- -( PDC_SPI1 ) PDC Transfer Control Register
- AT91C_SPI1_RPR EQU( 0xFFFE4100 );
- -( PDC_SPI1 ) Receive Pointer Register
- AT91C_SPI1_TNCR EQU( 0xFFFE411C );
- -( PDC_SPI1 ) Transmit Next Counter Register
- AT91C_SPI1_TPR EQU( 0xFFFE4108 );
- -( PDC_SPI1 ) Transmit Pointer Register
- AT91C_SPI1_TNPR EQU( 0xFFFE4118 );
- -( PDC_SPI1 ) Transmit Next Pointer Register
- AT91C_SPI1_TCR EQU( 0xFFFE410C );
- -( PDC_SPI1 ) Transmit Counter Register
- AT91C_SPI1_RCR EQU( 0xFFFE4104 );
- -( PDC_SPI1 ) Receive Counter Register
- AT91C_SPI1_RNPR EQU( 0xFFFE4110 );
- -( PDC_SPI1 ) Receive Next Pointer Register
- AT91C_SPI1_RNCR EQU( 0xFFFE4114 );
- -( PDC_SPI1 ) Receive Next Counter Register
- AT91C_SPI1_PTSR EQU( 0xFFFE4124 );
- -( PDC_SPI1 ) PDC Transfer Status Register
-/* - ========== Register definition for SPI1 peripheral ========== */
- AT91C_SPI1_IMR EQU( 0xFFFE401C );
- -( SPI1 ) Interrupt Mask Register
- AT91C_SPI1_IER EQU( 0xFFFE4014 );
- -( SPI1 ) Interrupt Enable Register
- AT91C_SPI1_MR EQU( 0xFFFE4004 );
- -( SPI1 ) Mode Register
- AT91C_SPI1_RDR EQU( 0xFFFE4008 );
- -( SPI1 ) Receive Data Register
- AT91C_SPI1_IDR EQU( 0xFFFE4018 );
- -( SPI1 ) Interrupt Disable Register
- AT91C_SPI1_SR EQU( 0xFFFE4010 );
- -( SPI1 ) Status Register
- AT91C_SPI1_TDR EQU( 0xFFFE400C );
- -( SPI1 ) Transmit Data Register
- AT91C_SPI1_CR EQU( 0xFFFE4000 );
- -( SPI1 ) Control Register
- AT91C_SPI1_CSR EQU( 0xFFFE4030 );
- -( SPI1 ) Chip Select Register
-/* - ========== Register definition for PDC_SPI0 peripheral ========== */
- AT91C_SPI0_PTCR EQU( 0xFFFE0120 );
- -( PDC_SPI0 ) PDC Transfer Control Register
- AT91C_SPI0_TPR EQU( 0xFFFE0108 );
- -( PDC_SPI0 ) Transmit Pointer Register
- AT91C_SPI0_TCR EQU( 0xFFFE010C );
- -( PDC_SPI0 ) Transmit Counter Register
- AT91C_SPI0_RCR EQU( 0xFFFE0104 );
- -( PDC_SPI0 ) Receive Counter Register
- AT91C_SPI0_PTSR EQU( 0xFFFE0124 );
- -( PDC_SPI0 ) PDC Transfer Status Register
- AT91C_SPI0_RNPR EQU( 0xFFFE0110 );
- -( PDC_SPI0 ) Receive Next Pointer Register
- AT91C_SPI0_RPR EQU( 0xFFFE0100 );
- -( PDC_SPI0 ) Receive Pointer Register
- AT91C_SPI0_TNCR EQU( 0xFFFE011C );
- -( PDC_SPI0 ) Transmit Next Counter Register
- AT91C_SPI0_RNCR EQU( 0xFFFE0114 );
- -( PDC_SPI0 ) Receive Next Counter Register
- AT91C_SPI0_TNPR EQU( 0xFFFE0118 );
- -( PDC_SPI0 ) Transmit Next Pointer Register
-/* - ========== Register definition for SPI0 peripheral ========== */
- AT91C_SPI0_IER EQU( 0xFFFE0014 );
- -( SPI0 ) Interrupt Enable Register
- AT91C_SPI0_SR EQU( 0xFFFE0010 );
- -( SPI0 ) Status Register
- AT91C_SPI0_IDR EQU( 0xFFFE0018 );
- -( SPI0 ) Interrupt Disable Register
- AT91C_SPI0_CR EQU( 0xFFFE0000 );
- -( SPI0 ) Control Register
- AT91C_SPI0_MR EQU( 0xFFFE0004 );
- -( SPI0 ) Mode Register
- AT91C_SPI0_IMR EQU( 0xFFFE001C );
- -( SPI0 ) Interrupt Mask Register
- AT91C_SPI0_TDR EQU( 0xFFFE000C );
- -( SPI0 ) Transmit Data Register
- AT91C_SPI0_RDR EQU( 0xFFFE0008 );
- -( SPI0 ) Receive Data Register
- AT91C_SPI0_CSR EQU( 0xFFFE0030 );
- -( SPI0 ) Chip Select Register
-/* - ========== Register definition for PDC_US1 peripheral ========== */
- AT91C_US1_RNCR EQU( 0xFFFC4114 );
- -( PDC_US1 ) Receive Next Counter Register
- AT91C_US1_PTCR EQU( 0xFFFC4120 );
- -( PDC_US1 ) PDC Transfer Control Register
- AT91C_US1_TCR EQU( 0xFFFC410C );
- -( PDC_US1 ) Transmit Counter Register
- AT91C_US1_PTSR EQU( 0xFFFC4124 );
- -( PDC_US1 ) PDC Transfer Status Register
- AT91C_US1_TNPR EQU( 0xFFFC4118 );
- -( PDC_US1 ) Transmit Next Pointer Register
- AT91C_US1_RCR EQU( 0xFFFC4104 );
- -( PDC_US1 ) Receive Counter Register
- AT91C_US1_RNPR EQU( 0xFFFC4110 );
- -( PDC_US1 ) Receive Next Pointer Register
- AT91C_US1_RPR EQU( 0xFFFC4100 );
- -( PDC_US1 ) Receive Pointer Register
- AT91C_US1_TNCR EQU( 0xFFFC411C );
- -( PDC_US1 ) Transmit Next Counter Register
- AT91C_US1_TPR EQU( 0xFFFC4108 );
- -( PDC_US1 ) Transmit Pointer Register
-/* - ========== Register definition for US1 peripheral ========== */
- AT91C_US1_IF EQU( 0xFFFC404C );
- -( US1 ) IRDA_FILTER Register
- AT91C_US1_NER EQU( 0xFFFC4044 );
- -( US1 ) Nb Errors Register
- AT91C_US1_RTOR EQU( 0xFFFC4024 );
- -( US1 ) Receiver Time - out Register
- AT91C_US1_CSR EQU( 0xFFFC4014 );
- -( US1 ) Channel Status Register
- AT91C_US1_IDR EQU( 0xFFFC400C );
- -( US1 ) Interrupt Disable Register
- AT91C_US1_IER EQU( 0xFFFC4008 );
- -( US1 ) Interrupt Enable Register
- AT91C_US1_THR EQU( 0xFFFC401C );
- -( US1 ) Transmitter Holding Register
- AT91C_US1_TTGR EQU( 0xFFFC4028 );
- -( US1 ) Transmitter Time - guard Register
- AT91C_US1_RHR EQU( 0xFFFC4018 );
- -( US1 ) Receiver Holding Register
- AT91C_US1_BRGR EQU( 0xFFFC4020 );
- -( US1 ) Baud Rate Generator Register
- AT91C_US1_IMR EQU( 0xFFFC4010 );
- -( US1 ) Interrupt Mask Register
- AT91C_US1_FIDI EQU( 0xFFFC4040 );
- -( US1 ) FI_DI_Ratio Register
- AT91C_US1_CR EQU( 0xFFFC4000 );
- -( US1 ) Control Register
- AT91C_US1_MR EQU( 0xFFFC4004 );
- -( US1 ) Mode Register
-/* - ========== Register definition for PDC_US0 peripheral ========== */
- AT91C_US0_TNPR EQU( 0xFFFC0118 );
- -( PDC_US0 ) Transmit Next Pointer Register
- AT91C_US0_RNPR EQU( 0xFFFC0110 );
- -( PDC_US0 ) Receive Next Pointer Register
- AT91C_US0_TCR EQU( 0xFFFC010C );
- -( PDC_US0 ) Transmit Counter Register
- AT91C_US0_PTCR EQU( 0xFFFC0120 );
- -( PDC_US0 ) PDC Transfer Control Register
- AT91C_US0_PTSR EQU( 0xFFFC0124 );
- -( PDC_US0 ) PDC Transfer Status Register
- AT91C_US0_TNCR EQU( 0xFFFC011C );
- -( PDC_US0 ) Transmit Next Counter Register
- AT91C_US0_TPR EQU( 0xFFFC0108 );
- -( PDC_US0 ) Transmit Pointer Register
- AT91C_US0_RCR EQU( 0xFFFC0104 );
- -( PDC_US0 ) Receive Counter Register
- AT91C_US0_RPR EQU( 0xFFFC0100 );
- -( PDC_US0 ) Receive Pointer Register
- AT91C_US0_RNCR EQU( 0xFFFC0114 );
- -( PDC_US0 ) Receive Next Counter Register
-/* - ========== Register definition for US0 peripheral ========== */
- AT91C_US0_BRGR EQU( 0xFFFC0020 );
- -( US0 ) Baud Rate Generator Register
- AT91C_US0_NER EQU( 0xFFFC0044 );
- -( US0 ) Nb Errors Register
- AT91C_US0_CR EQU( 0xFFFC0000 );
- -( US0 ) Control Register
- AT91C_US0_IMR EQU( 0xFFFC0010 );
- -( US0 ) Interrupt Mask Register
- AT91C_US0_FIDI EQU( 0xFFFC0040 );
- -( US0 ) FI_DI_Ratio Register
- AT91C_US0_TTGR EQU( 0xFFFC0028 );
- -( US0 ) Transmitter Time - guard Register
- AT91C_US0_MR EQU( 0xFFFC0004 );
- -( US0 ) Mode Register
- AT91C_US0_RTOR EQU( 0xFFFC0024 );
- -( US0 ) Receiver Time - out Register
- AT91C_US0_CSR EQU( 0xFFFC0014 );
- -( US0 ) Channel Status Register
- AT91C_US0_RHR EQU( 0xFFFC0018 );
- -( US0 ) Receiver Holding Register
- AT91C_US0_IDR EQU( 0xFFFC000C );
- -( US0 ) Interrupt Disable Register
- AT91C_US0_THR EQU( 0xFFFC001C );
- -( US0 ) Transmitter Holding Register
- AT91C_US0_IF EQU( 0xFFFC004C );
- -( US0 ) IRDA_FILTER Register
- AT91C_US0_IER EQU( 0xFFFC0008 );
- -( US0 ) Interrupt Enable Register
-/* - ========== Register definition for PDC_SSC peripheral ========== */
- AT91C_SSC_TNCR EQU( 0xFFFD411C );
- -( PDC_SSC ) Transmit Next Counter Register
- AT91C_SSC_RPR EQU( 0xFFFD4100 );
- -( PDC_SSC ) Receive Pointer Register
- AT91C_SSC_RNCR EQU( 0xFFFD4114 );
- -( PDC_SSC ) Receive Next Counter Register
- AT91C_SSC_TPR EQU( 0xFFFD4108 );
- -( PDC_SSC ) Transmit Pointer Register
- AT91C_SSC_PTCR EQU( 0xFFFD4120 );
- -( PDC_SSC ) PDC Transfer Control Register
- AT91C_SSC_TCR EQU( 0xFFFD410C );
- -( PDC_SSC ) Transmit Counter Register
- AT91C_SSC_RCR EQU( 0xFFFD4104 );
- -( PDC_SSC ) Receive Counter Register
- AT91C_SSC_RNPR EQU( 0xFFFD4110 );
- -( PDC_SSC ) Receive Next Pointer Register
- AT91C_SSC_TNPR EQU( 0xFFFD4118 );
- -( PDC_SSC ) Transmit Next Pointer Register
- AT91C_SSC_PTSR EQU( 0xFFFD4124 );
- -( PDC_SSC ) PDC Transfer Status Register
-/* - ========== Register definition for SSC peripheral ========== */
- AT91C_SSC_RHR EQU( 0xFFFD4020 );
- -( SSC ) Receive Holding Register
- AT91C_SSC_RSHR EQU( 0xFFFD4030 );
- -( SSC ) Receive Sync Holding Register
- AT91C_SSC_TFMR EQU( 0xFFFD401C );
- -( SSC ) Transmit Frame Mode Register
- AT91C_SSC_IDR EQU( 0xFFFD4048 );
- -( SSC ) Interrupt Disable Register
- AT91C_SSC_THR EQU( 0xFFFD4024 );
- -( SSC ) Transmit Holding Register
- AT91C_SSC_RCMR EQU( 0xFFFD4010 );
- -( SSC ) Receive Clock ModeRegister
- AT91C_SSC_IER EQU( 0xFFFD4044 );
- -( SSC ) Interrupt Enable Register
- AT91C_SSC_TSHR EQU( 0xFFFD4034 );
- -( SSC ) Transmit Sync Holding Register
- AT91C_SSC_SR EQU( 0xFFFD4040 );
- -( SSC ) Status Register
- AT91C_SSC_CMR EQU( 0xFFFD4004 );
- -( SSC ) Clock Mode Register
- AT91C_SSC_TCMR EQU( 0xFFFD4018 );
- -( SSC ) Transmit Clock Mode Register
- AT91C_SSC_CR EQU( 0xFFFD4000 );
- -( SSC ) Control Register
- AT91C_SSC_IMR EQU( 0xFFFD404C );
- -( SSC ) Interrupt Mask Register
- AT91C_SSC_RFMR EQU( 0xFFFD4014 );
- -( SSC ) Receive Frame Mode Register
-/* - ========== Register definition for TWI peripheral ========== */
- AT91C_TWI_IER EQU( 0xFFFB8024 );
- -( TWI ) Interrupt Enable Register
- AT91C_TWI_CR EQU( 0xFFFB8000 );
- -( TWI ) Control Register
- AT91C_TWI_SR EQU( 0xFFFB8020 );
- -( TWI ) Status Register
- AT91C_TWI_IMR EQU( 0xFFFB802C );
- -( TWI ) Interrupt Mask Register
- AT91C_TWI_THR EQU( 0xFFFB8034 );
- -( TWI ) Transmit Holding Register
- AT91C_TWI_IDR EQU( 0xFFFB8028 );
- -( TWI ) Interrupt Disable Register
- AT91C_TWI_IADR EQU( 0xFFFB800C );
- -( TWI ) Internal Address Register
- AT91C_TWI_MMR EQU( 0xFFFB8004 );
- -( TWI ) Master Mode Register
- AT91C_TWI_CWGR EQU( 0xFFFB8010 );
- -( TWI ) Clock Waveform Generator Register
- AT91C_TWI_RHR EQU( 0xFFFB8030 );
- -( TWI ) Receive Holding Register
-/* - ========== Register definition for PWMC_CH3 peripheral ========== */
- AT91C_PWMC_CH3_CUPDR EQU( 0xFFFCC270 );
- -( PWMC_CH3 ) Channel Update Register
- AT91C_PWMC_CH3_Reserved EQU( 0xFFFCC274 );
- -( PWMC_CH3 ) Reserved
- AT91C_PWMC_CH3_CPRDR EQU( 0xFFFCC268 );
- -( PWMC_CH3 ) Channel Period Register
- AT91C_PWMC_CH3_CDTYR EQU( 0xFFFCC264 );
- -( PWMC_CH3 ) Channel Duty Cycle Register
- AT91C_PWMC_CH3_CCNTR EQU( 0xFFFCC26C );
- -( PWMC_CH3 ) Channel Counter Register
- AT91C_PWMC_CH3_CMR EQU( 0xFFFCC260 );
- -( PWMC_CH3 ) Channel Mode Register
-/* - ========== Register definition for PWMC_CH2 peripheral ========== */
- AT91C_PWMC_CH2_Reserved EQU( 0xFFFCC254 );
- -( PWMC_CH2 ) Reserved
- AT91C_PWMC_CH2_CMR EQU( 0xFFFCC240 );
- -( PWMC_CH2 ) Channel Mode Register
- AT91C_PWMC_CH2_CCNTR EQU( 0xFFFCC24C );
- -( PWMC_CH2 ) Channel Counter Register
- AT91C_PWMC_CH2_CPRDR EQU( 0xFFFCC248 );
- -( PWMC_CH2 ) Channel Period Register
- AT91C_PWMC_CH2_CUPDR EQU( 0xFFFCC250 );
- -( PWMC_CH2 ) Channel Update Register
- AT91C_PWMC_CH2_CDTYR EQU( 0xFFFCC244 );
- -( PWMC_CH2 ) Channel Duty Cycle Register
-/* - ========== Register definition for PWMC_CH1 peripheral ========== */
- AT91C_PWMC_CH1_Reserved EQU( 0xFFFCC234 );
- -( PWMC_CH1 ) Reserved
- AT91C_PWMC_CH1_CUPDR EQU( 0xFFFCC230 );
- -( PWMC_CH1 ) Channel Update Register
- AT91C_PWMC_CH1_CPRDR EQU( 0xFFFCC228 );
- -( PWMC_CH1 ) Channel Period Register
- AT91C_PWMC_CH1_CCNTR EQU( 0xFFFCC22C );
- -( PWMC_CH1 ) Channel Counter Register
- AT91C_PWMC_CH1_CDTYR EQU( 0xFFFCC224 );
- -( PWMC_CH1 ) Channel Duty Cycle Register
- AT91C_PWMC_CH1_CMR EQU( 0xFFFCC220 );
- -( PWMC_CH1 ) Channel Mode Register
-/* - ========== Register definition for PWMC_CH0 peripheral ========== */
- AT91C_PWMC_CH0_Reserved EQU( 0xFFFCC214 );
- -( PWMC_CH0 ) Reserved
- AT91C_PWMC_CH0_CPRDR EQU( 0xFFFCC208 );
- -( PWMC_CH0 ) Channel Period Register
- AT91C_PWMC_CH0_CDTYR EQU( 0xFFFCC204 );
- -( PWMC_CH0 ) Channel Duty Cycle Register
- AT91C_PWMC_CH0_CMR EQU( 0xFFFCC200 );
- -( PWMC_CH0 ) Channel Mode Register
- AT91C_PWMC_CH0_CUPDR EQU( 0xFFFCC210 );
- -( PWMC_CH0 ) Channel Update Register
- AT91C_PWMC_CH0_CCNTR EQU( 0xFFFCC20C );
- -( PWMC_CH0 ) Channel Counter Register
-/* - ========== Register definition for PWMC peripheral ========== */
- AT91C_PWMC_IDR EQU( 0xFFFCC014 );
- -( PWMC ) PWMC Interrupt Disable Register
- AT91C_PWMC_DIS EQU( 0xFFFCC008 );
- -( PWMC ) PWMC Disable Register
- AT91C_PWMC_IER EQU( 0xFFFCC010 );
- -( PWMC ) PWMC Interrupt Enable Register
- AT91C_PWMC_VR EQU( 0xFFFCC0FC );
- -( PWMC ) PWMC Version Register
- AT91C_PWMC_ISR EQU( 0xFFFCC01C );
- -( PWMC ) PWMC Interrupt Status Register
- AT91C_PWMC_SR EQU( 0xFFFCC00C );
- -( PWMC ) PWMC Status Register
- AT91C_PWMC_IMR EQU( 0xFFFCC018 );
- -( PWMC ) PWMC Interrupt Mask Register
- AT91C_PWMC_MR EQU( 0xFFFCC000 );
- -( PWMC ) PWMC Mode Register
- AT91C_PWMC_ENA EQU( 0xFFFCC004 );
- -( PWMC ) PWMC Enable Register
-/* - ========== Register definition for UDP peripheral ========== */
- AT91C_UDP_IMR EQU( 0xFFFB0018 );
- -( UDP ) Interrupt Mask Register
- AT91C_UDP_FADDR EQU( 0xFFFB0008 );
- -( UDP ) Function Address Register
- AT91C_UDP_NUM EQU( 0xFFFB0000 );
- -( UDP ) Frame Number Register
- AT91C_UDP_FDR EQU( 0xFFFB0050 );
- -( UDP ) Endpoint FIFO Data Register
- AT91C_UDP_ISR EQU( 0xFFFB001C );
- -( UDP ) Interrupt Status Register
- AT91C_UDP_CSR EQU( 0xFFFB0030 );
- -( UDP ) Endpoint Control and Status Register
- AT91C_UDP_IDR EQU( 0xFFFB0014 );
- -( UDP ) Interrupt Disable Register
- AT91C_UDP_ICR EQU( 0xFFFB0020 );
- -( UDP ) Interrupt Clear Register
- AT91C_UDP_RSTEP EQU( 0xFFFB0028 );
- -( UDP ) Reset Endpoint Register
- AT91C_UDP_TXVC EQU( 0xFFFB0074 );
- -( UDP ) Transceiver Control Register
- AT91C_UDP_GLBSTATE EQU( 0xFFFB0004 );
- -( UDP ) Global State Register
- AT91C_UDP_IER EQU( 0xFFFB0010 );
- -( UDP ) Interrupt Enable Register
-/* - ========== Register definition for TC0 peripheral ========== */
- AT91C_TC0_SR EQU( 0xFFFA0020 );
- -( TC0 ) Status Register
- AT91C_TC0_RC EQU( 0xFFFA001C );
- -( TC0 ) Register C
- AT91C_TC0_RB EQU( 0xFFFA0018 );
- -( TC0 ) Register B
- AT91C_TC0_CCR EQU( 0xFFFA0000 );
- -( TC0 ) Channel Control Register
- AT91C_TC0_CMR EQU( 0xFFFA0004 );
- -( TC0 ) Channel Mode Register( Capture Mode / Waveform Mode )
- AT91C_TC0_IER EQU( 0xFFFA0024 );
- -( TC0 ) Interrupt Enable Register
- AT91C_TC0_RA EQU( 0xFFFA0014 );
- -( TC0 ) Register A
- AT91C_TC0_IDR EQU( 0xFFFA0028 );
- -( TC0 ) Interrupt Disable Register
- AT91C_TC0_CV EQU( 0xFFFA0010 );
- -( TC0 ) Counter Value
- AT91C_TC0_IMR EQU( 0xFFFA002C );
- -( TC0 ) Interrupt Mask Register
-/* - ========== Register definition for TC1 peripheral ========== */
- AT91C_TC1_RB EQU( 0xFFFA0058 );
- -( TC1 ) Register B
- AT91C_TC1_CCR EQU( 0xFFFA0040 );
- -( TC1 ) Channel Control Register
- AT91C_TC1_IER EQU( 0xFFFA0064 );
- -( TC1 ) Interrupt Enable Register
- AT91C_TC1_IDR EQU( 0xFFFA0068 );
- -( TC1 ) Interrupt Disable Register
- AT91C_TC1_SR EQU( 0xFFFA0060 );
- -( TC1 ) Status Register
- AT91C_TC1_CMR EQU( 0xFFFA0044 );
- -( TC1 ) Channel Mode Register( Capture Mode / Waveform Mode )
- AT91C_TC1_RA EQU( 0xFFFA0054 );
- -( TC1 ) Register A
- AT91C_TC1_RC EQU( 0xFFFA005C );
- -( TC1 ) Register C
- AT91C_TC1_IMR EQU( 0xFFFA006C );
- -( TC1 ) Interrupt Mask Register
- AT91C_TC1_CV EQU( 0xFFFA0050 );
- -( TC1 ) Counter Value
-/* - ========== Register definition for TC2 peripheral ========== */
- AT91C_TC2_CMR EQU( 0xFFFA0084 );
- -( TC2 ) Channel Mode Register( Capture Mode / Waveform Mode )
- AT91C_TC2_CCR EQU( 0xFFFA0080 );
- -( TC2 ) Channel Control Register
- AT91C_TC2_CV EQU( 0xFFFA0090 );
- -( TC2 ) Counter Value
- AT91C_TC2_RA EQU( 0xFFFA0094 );
- -( TC2 ) Register A
- AT91C_TC2_RB EQU( 0xFFFA0098 );
- -( TC2 ) Register B
- AT91C_TC2_IDR EQU( 0xFFFA00A8 );
- -( TC2 ) Interrupt Disable Register
- AT91C_TC2_IMR EQU( 0xFFFA00AC );
- -( TC2 ) Interrupt Mask Register
- AT91C_TC2_RC EQU( 0xFFFA009C );
- -( TC2 ) Register C
- AT91C_TC2_IER EQU( 0xFFFA00A4 );
- -( TC2 ) Interrupt Enable Register
- AT91C_TC2_SR EQU( 0xFFFA00A0 );
- -( TC2 ) Status Register
-/* - ========== Register definition for TCB peripheral ========== */
- AT91C_TCB_BMR EQU( 0xFFFA00C4 );
- -( TCB ) TC Block Mode Register
- AT91C_TCB_BCR EQU( 0xFFFA00C0 );
- -( TCB ) TC Block Control Register
-/* - ========== Register definition for CAN_MB0 peripheral ========== */
- AT91C_CAN_MB0_MDL EQU( 0xFFFD0214 );
- -( CAN_MB0 ) MailBox Data Low Register
- AT91C_CAN_MB0_MAM EQU( 0xFFFD0204 );
- -( CAN_MB0 ) MailBox Acceptance Mask Register
- AT91C_CAN_MB0_MCR EQU( 0xFFFD021C );
- -( CAN_MB0 ) MailBox Control Register
- AT91C_CAN_MB0_MID EQU( 0xFFFD0208 );
- -( CAN_MB0 ) MailBox ID Register
- AT91C_CAN_MB0_MSR EQU( 0xFFFD0210 );
- -( CAN_MB0 ) MailBox Status Register
- AT91C_CAN_MB0_MFID EQU( 0xFFFD020C );
- -( CAN_MB0 ) MailBox Family ID Register
- AT91C_CAN_MB0_MDH EQU( 0xFFFD0218 );
- -( CAN_MB0 ) MailBox Data High Register
- AT91C_CAN_MB0_MMR EQU( 0xFFFD0200 );
- -( CAN_MB0 ) MailBox Mode Register
-/* - ========== Register definition for CAN_MB1 peripheral ========== */
- AT91C_CAN_MB1_MDL EQU( 0xFFFD0234 );
- -( CAN_MB1 ) MailBox Data Low Register
- AT91C_CAN_MB1_MID EQU( 0xFFFD0228 );
- -( CAN_MB1 ) MailBox ID Register
- AT91C_CAN_MB1_MMR EQU( 0xFFFD0220 );
- -( CAN_MB1 ) MailBox Mode Register
- AT91C_CAN_MB1_MSR EQU( 0xFFFD0230 );
- -( CAN_MB1 ) MailBox Status Register
- AT91C_CAN_MB1_MAM EQU( 0xFFFD0224 );
- -( CAN_MB1 ) MailBox Acceptance Mask Register
- AT91C_CAN_MB1_MDH EQU( 0xFFFD0238 );
- -( CAN_MB1 ) MailBox Data High Register
- AT91C_CAN_MB1_MCR EQU( 0xFFFD023C );
- -( CAN_MB1 ) MailBox Control Register
- AT91C_CAN_MB1_MFID EQU( 0xFFFD022C );
- -( CAN_MB1 ) MailBox Family ID Register
-/* - ========== Register definition for CAN_MB2 peripheral ========== */
- AT91C_CAN_MB2_MCR EQU( 0xFFFD025C );
- -( CAN_MB2 ) MailBox Control Register
- AT91C_CAN_MB2_MDH EQU( 0xFFFD0258 );
- -( CAN_MB2 ) MailBox Data High Register
- AT91C_CAN_MB2_MID EQU( 0xFFFD0248 );
- -( CAN_MB2 ) MailBox ID Register
- AT91C_CAN_MB2_MDL EQU( 0xFFFD0254 );
- -( CAN_MB2 ) MailBox Data Low Register
- AT91C_CAN_MB2_MMR EQU( 0xFFFD0240 );
- -( CAN_MB2 ) MailBox Mode Register
- AT91C_CAN_MB2_MAM EQU( 0xFFFD0244 );
- -( CAN_MB2 ) MailBox Acceptance Mask Register
- AT91C_CAN_MB2_MFID EQU( 0xFFFD024C );
- -( CAN_MB2 ) MailBox Family ID Register
- AT91C_CAN_MB2_MSR EQU( 0xFFFD0250 );
- -( CAN_MB2 ) MailBox Status Register
-/* - ========== Register definition for CAN_MB3 peripheral ========== */
- AT91C_CAN_MB3_MFID EQU( 0xFFFD026C );
- -( CAN_MB3 ) MailBox Family ID Register
- AT91C_CAN_MB3_MAM EQU( 0xFFFD0264 );
- -( CAN_MB3 ) MailBox Acceptance Mask Register
- AT91C_CAN_MB3_MID EQU( 0xFFFD0268 );
- -( CAN_MB3 ) MailBox ID Register
- AT91C_CAN_MB3_MCR EQU( 0xFFFD027C );
- -( CAN_MB3 ) MailBox Control Register
- AT91C_CAN_MB3_MMR EQU( 0xFFFD0260 );
- -( CAN_MB3 ) MailBox Mode Register
- AT91C_CAN_MB3_MSR EQU( 0xFFFD0270 );
- -( CAN_MB3 ) MailBox Status Register
- AT91C_CAN_MB3_MDL EQU( 0xFFFD0274 );
- -( CAN_MB3 ) MailBox Data Low Register
- AT91C_CAN_MB3_MDH EQU( 0xFFFD0278 );
- -( CAN_MB3 ) MailBox Data High Register
-/* - ========== Register definition for CAN_MB4 peripheral ========== */
- AT91C_CAN_MB4_MID EQU( 0xFFFD0288 );
- -( CAN_MB4 ) MailBox ID Register
- AT91C_CAN_MB4_MMR EQU( 0xFFFD0280 );
- -( CAN_MB4 ) MailBox Mode Register
- AT91C_CAN_MB4_MDH EQU( 0xFFFD0298 );
- -( CAN_MB4 ) MailBox Data High Register
- AT91C_CAN_MB4_MFID EQU( 0xFFFD028C );
- -( CAN_MB4 ) MailBox Family ID Register
- AT91C_CAN_MB4_MSR EQU( 0xFFFD0290 );
- -( CAN_MB4 ) MailBox Status Register
- AT91C_CAN_MB4_MCR EQU( 0xFFFD029C );
- -( CAN_MB4 ) MailBox Control Register
- AT91C_CAN_MB4_MDL EQU( 0xFFFD0294 );
- -( CAN_MB4 ) MailBox Data Low Register
- AT91C_CAN_MB4_MAM EQU( 0xFFFD0284 );
- -( CAN_MB4 ) MailBox Acceptance Mask Register
-/* - ========== Register definition for CAN_MB5 peripheral ========== */
- AT91C_CAN_MB5_MSR EQU( 0xFFFD02B0 );
- -( CAN_MB5 ) MailBox Status Register
- AT91C_CAN_MB5_MCR EQU( 0xFFFD02BC );
- -( CAN_MB5 ) MailBox Control Register
- AT91C_CAN_MB5_MFID EQU( 0xFFFD02AC );
- -( CAN_MB5 ) MailBox Family ID Register
- AT91C_CAN_MB5_MDH EQU( 0xFFFD02B8 );
- -( CAN_MB5 ) MailBox Data High Register
- AT91C_CAN_MB5_MID EQU( 0xFFFD02A8 );
- -( CAN_MB5 ) MailBox ID Register
- AT91C_CAN_MB5_MMR EQU( 0xFFFD02A0 );
- -( CAN_MB5 ) MailBox Mode Register
- AT91C_CAN_MB5_MDL EQU( 0xFFFD02B4 );
- -( CAN_MB5 ) MailBox Data Low Register
- AT91C_CAN_MB5_MAM EQU( 0xFFFD02A4 );
- -( CAN_MB5 ) MailBox Acceptance Mask Register
-/* - ========== Register definition for CAN_MB6 peripheral ========== */
- AT91C_CAN_MB6_MFID EQU( 0xFFFD02CC );
- -( CAN_MB6 ) MailBox Family ID Register
- AT91C_CAN_MB6_MID EQU( 0xFFFD02C8 );
- -( CAN_MB6 ) MailBox ID Register
- AT91C_CAN_MB6_MAM EQU( 0xFFFD02C4 );
- -( CAN_MB6 ) MailBox Acceptance Mask Register
- AT91C_CAN_MB6_MSR EQU( 0xFFFD02D0 );
- -( CAN_MB6 ) MailBox Status Register
- AT91C_CAN_MB6_MDL EQU( 0xFFFD02D4 );
- -( CAN_MB6 ) MailBox Data Low Register
- AT91C_CAN_MB6_MCR EQU( 0xFFFD02DC );
- -( CAN_MB6 ) MailBox Control Register
- AT91C_CAN_MB6_MDH EQU( 0xFFFD02D8 );
- -( CAN_MB6 ) MailBox Data High Register
- AT91C_CAN_MB6_MMR EQU( 0xFFFD02C0 );
- -( CAN_MB6 ) MailBox Mode Register
-/* - ========== Register definition for CAN_MB7 peripheral ========== */
- AT91C_CAN_MB7_MCR EQU( 0xFFFD02FC );
- -( CAN_MB7 ) MailBox Control Register
- AT91C_CAN_MB7_MDH EQU( 0xFFFD02F8 );
- -( CAN_MB7 ) MailBox Data High Register
- AT91C_CAN_MB7_MFID EQU( 0xFFFD02EC );
- -( CAN_MB7 ) MailBox Family ID Register
- AT91C_CAN_MB7_MDL EQU( 0xFFFD02F4 );
- -( CAN_MB7 ) MailBox Data Low Register
- AT91C_CAN_MB7_MID EQU( 0xFFFD02E8 );
- -( CAN_MB7 ) MailBox ID Register
- AT91C_CAN_MB7_MMR EQU( 0xFFFD02E0 );
- -( CAN_MB7 ) MailBox Mode Register
- AT91C_CAN_MB7_MAM EQU( 0xFFFD02E4 );
- -( CAN_MB7 ) MailBox Acceptance Mask Register
- AT91C_CAN_MB7_MSR EQU( 0xFFFD02F0 );
- -( CAN_MB7 ) MailBox Status Register
-/* - ========== Register definition for CAN peripheral ========== */
- AT91C_CAN_TCR EQU( 0xFFFD0024 );
- -( CAN ) Transfer Command Register
- AT91C_CAN_IMR EQU( 0xFFFD000C );
- -( CAN ) Interrupt Mask Register
- AT91C_CAN_IER EQU( 0xFFFD0004 );
- -( CAN ) Interrupt Enable Register
- AT91C_CAN_ECR EQU( 0xFFFD0020 );
- -( CAN ) Error Counter Register
- AT91C_CAN_TIMESTP EQU( 0xFFFD001C );
- -( CAN ) Time Stamp Register
- AT91C_CAN_MR EQU( 0xFFFD0000 );
- -( CAN ) Mode Register
- AT91C_CAN_IDR EQU( 0xFFFD0008 );
- -( CAN ) Interrupt Disable Register
- AT91C_CAN_ACR EQU( 0xFFFD0028 );
- -( CAN ) Abort Command Register
- AT91C_CAN_TIM EQU( 0xFFFD0018 );
- -( CAN ) Timer Register
- AT91C_CAN_SR EQU( 0xFFFD0010 );
- -( CAN ) Status Register
- AT91C_CAN_BR EQU( 0xFFFD0014 );
- -( CAN ) Baudrate Register
- AT91C_CAN_VR EQU( 0xFFFD00FC );
- -( CAN ) Version Register
-/* - ========== Register definition for EMAC peripheral ========== */
- AT91C_EMAC_ISR EQU( 0xFFFDC024 );
- -( EMAC ) Interrupt Status Register
- AT91C_EMAC_SA4H EQU( 0xFFFDC0B4 );
- -( EMAC ) Specific Address 4 Top, Last 2 bytes
- AT91C_EMAC_SA1L EQU( 0xFFFDC098 );
- -( EMAC ) Specific Address 1 Bottom, First 4 bytes
- AT91C_EMAC_ELE EQU( 0xFFFDC078 );
- -( EMAC ) Excessive Length Errors Register
- AT91C_EMAC_LCOL EQU( 0xFFFDC05C );
- -( EMAC ) Late Collision Register
- AT91C_EMAC_RLE EQU( 0xFFFDC088 );
- -( EMAC ) Receive Length Field Mismatch Register
- AT91C_EMAC_WOL EQU( 0xFFFDC0C4 );
- -( EMAC ) Wake On LAN Register
- AT91C_EMAC_DTF EQU( 0xFFFDC058 );
- -( EMAC ) Deferred Transmission Frame Register
- AT91C_EMAC_TUND EQU( 0xFFFDC064 );
- -( EMAC ) Transmit Underrun Error Register
- AT91C_EMAC_NCR EQU( 0xFFFDC000 );
- -( EMAC ) Network Control Register
- AT91C_EMAC_SA4L EQU( 0xFFFDC0B0 );
- -( EMAC ) Specific Address 4 Bottom, First 4 bytes
- AT91C_EMAC_RSR EQU( 0xFFFDC020 );
- -( EMAC ) Receive Status Register
- AT91C_EMAC_SA3L EQU( 0xFFFDC0A8 );
- -( EMAC ) Specific Address 3 Bottom, First 4 bytes
- AT91C_EMAC_TSR EQU( 0xFFFDC014 );
- -( EMAC ) Transmit Status Register
- AT91C_EMAC_IDR EQU( 0xFFFDC02C );
- -( EMAC ) Interrupt Disable Register
- AT91C_EMAC_RSE EQU( 0xFFFDC074 );
- -( EMAC ) Receive Symbol Errors Register
- AT91C_EMAC_ECOL EQU( 0xFFFDC060 );
- -( EMAC ) Excessive Collision Register
- AT91C_EMAC_TID EQU( 0xFFFDC0B8 );
- -( EMAC ) Type ID Checking Register
- AT91C_EMAC_HRB EQU( 0xFFFDC090 );
- -( EMAC ) Hash Address Bottom[ 31 : 0 ]
- AT91C_EMAC_TBQP EQU( 0xFFFDC01C );
- -( EMAC ) Transmit Buffer Queue Pointer
- AT91C_EMAC_USRIO EQU( 0xFFFDC0C0 );
- -( EMAC ) USER Input / Output Register
- AT91C_EMAC_PTR EQU( 0xFFFDC038 );
- -( EMAC ) Pause Time Register
- AT91C_EMAC_SA2H EQU( 0xFFFDC0A4 );
- -( EMAC ) Specific Address 2 Top, Last 2 bytes
- AT91C_EMAC_ROV EQU( 0xFFFDC070 );
- -( EMAC ) Receive Overrun Errors Register
- AT91C_EMAC_ALE EQU( 0xFFFDC054 );
- -( EMAC ) Alignment Error Register
- AT91C_EMAC_RJA EQU( 0xFFFDC07C );
- -( EMAC ) Receive Jabbers Register
- AT91C_EMAC_RBQP EQU( 0xFFFDC018 );
- -( EMAC ) Receive Buffer Queue Pointer
- AT91C_EMAC_TPF EQU( 0xFFFDC08C );
- -( EMAC ) Transmitted Pause Frames Register
- AT91C_EMAC_NCFGR EQU( 0xFFFDC004 );
- -( EMAC ) Network Configuration Register
- AT91C_EMAC_HRT EQU( 0xFFFDC094 );
- -( EMAC ) Hash Address Top[ 63 : 32 ]
- AT91C_EMAC_USF EQU( 0xFFFDC080 );
- -( EMAC ) Undersize Frames Register
- AT91C_EMAC_FCSE EQU( 0xFFFDC050 );
- -( EMAC ) Frame Check Sequence Error Register
- AT91C_EMAC_TPQ EQU( 0xFFFDC0BC );
- -( EMAC ) Transmit Pause Quantum Register
- AT91C_EMAC_MAN EQU( 0xFFFDC034 );
- -( EMAC ) PHY Maintenance Register
- AT91C_EMAC_FTO EQU( 0xFFFDC040 );
- -( EMAC ) Frames Transmitted OK Register
- AT91C_EMAC_REV EQU( 0xFFFDC0FC );
- -( EMAC ) Revision Register
- AT91C_EMAC_IMR EQU( 0xFFFDC030 );
- -( EMAC ) Interrupt Mask Register
- AT91C_EMAC_SCF EQU( 0xFFFDC044 );
- -( EMAC ) Single Collision Frame Register
- AT91C_EMAC_PFR EQU( 0xFFFDC03C );
- -( EMAC ) Pause Frames received Register
- AT91C_EMAC_MCF EQU( 0xFFFDC048 );
- -( EMAC ) Multiple Collision Frame Register
- AT91C_EMAC_NSR EQU( 0xFFFDC008 );
- -( EMAC ) Network Status Register
- AT91C_EMAC_SA2L EQU( 0xFFFDC0A0 );
- -( EMAC ) Specific Address 2 Bottom, First 4 bytes
- AT91C_EMAC_FRO EQU( 0xFFFDC04C );
- -( EMAC ) Frames Received OK Register
- AT91C_EMAC_IER EQU( 0xFFFDC028 );
- -( EMAC ) Interrupt Enable Register
- AT91C_EMAC_SA1H EQU( 0xFFFDC09C );
- -( EMAC ) Specific Address 1 Top, Last 2 bytes
- AT91C_EMAC_CSE EQU( 0xFFFDC068 );
- -( EMAC ) Carrier Sense Error Register
- AT91C_EMAC_SA3H EQU( 0xFFFDC0AC );
- -( EMAC ) Specific Address 3 Top, Last 2 bytes
- AT91C_EMAC_RRE EQU( 0xFFFDC06C );
- -( EMAC ) Receive Ressource Error Register
- AT91C_EMAC_STE EQU( 0xFFFDC084 );
- -( EMAC ) SQE Test Error Register
-/* - ========== Register definition for PDC_ADC peripheral ========== */
- AT91C_ADC_PTSR EQU( 0xFFFD8124 );
- -( PDC_ADC ) PDC Transfer Status Register
- AT91C_ADC_PTCR EQU( 0xFFFD8120 );
- -( PDC_ADC ) PDC Transfer Control Register
- AT91C_ADC_TNPR EQU( 0xFFFD8118 );
- -( PDC_ADC ) Transmit Next Pointer Register
- AT91C_ADC_TNCR EQU( 0xFFFD811C );
- -( PDC_ADC ) Transmit Next Counter Register
- AT91C_ADC_RNPR EQU( 0xFFFD8110 );
- -( PDC_ADC ) Receive Next Pointer Register
- AT91C_ADC_RNCR EQU( 0xFFFD8114 );
- -( PDC_ADC ) Receive Next Counter Register
- AT91C_ADC_RPR EQU( 0xFFFD8100 );
- -( PDC_ADC ) Receive Pointer Register
- AT91C_ADC_TCR EQU( 0xFFFD810C );
- -( PDC_ADC ) Transmit Counter Register
- AT91C_ADC_TPR EQU( 0xFFFD8108 );
- -( PDC_ADC ) Transmit Pointer Register
- AT91C_ADC_RCR EQU( 0xFFFD8104 );
- -( PDC_ADC ) Receive Counter Register
-/* - ========== Register definition for ADC peripheral ========== */
- AT91C_ADC_CDR2 EQU( 0xFFFD8038 );
- -( ADC ) ADC Channel Data Register 2
- AT91C_ADC_CDR3 EQU( 0xFFFD803C );
- -( ADC ) ADC Channel Data Register 3
- AT91C_ADC_CDR0 EQU( 0xFFFD8030 );
- -( ADC ) ADC Channel Data Register 0
- AT91C_ADC_CDR5 EQU( 0xFFFD8044 );
- -( ADC ) ADC Channel Data Register 5
- AT91C_ADC_CHDR EQU( 0xFFFD8014 );
- -( ADC ) ADC Channel Disable Register
- AT91C_ADC_SR EQU( 0xFFFD801C );
- -( ADC ) ADC Status Register
- AT91C_ADC_CDR4 EQU( 0xFFFD8040 );
- -( ADC ) ADC Channel Data Register 4
- AT91C_ADC_CDR1 EQU( 0xFFFD8034 );
- -( ADC ) ADC Channel Data Register 1
- AT91C_ADC_LCDR EQU( 0xFFFD8020 );
- -( ADC ) ADC Last Converted Data Register
- AT91C_ADC_IDR EQU( 0xFFFD8028 );
- -( ADC ) ADC Interrupt Disable Register
- AT91C_ADC_CR EQU( 0xFFFD8000 );
- -( ADC ) ADC Control Register
- AT91C_ADC_CDR7 EQU( 0xFFFD804C );
- -( ADC ) ADC Channel Data Register 7
- AT91C_ADC_CDR6 EQU( 0xFFFD8048 );
- -( ADC ) ADC Channel Data Register 6
- AT91C_ADC_IER EQU( 0xFFFD8024 );
- -( ADC ) ADC Interrupt Enable Register
- AT91C_ADC_CHER EQU( 0xFFFD8010 );
- -( ADC ) ADC Channel Enable Register
- AT91C_ADC_CHSR EQU( 0xFFFD8018 );
- -( ADC ) ADC Channel Status Register
- AT91C_ADC_MR EQU( 0xFFFD8004 );
- -( ADC ) ADC Mode Register
- AT91C_ADC_IMR EQU( 0xFFFD802C );
- -( ADC ) ADC Interrupt Mask Register
-/* - ========== Register definition for PDC_AES peripheral ========== */
- AT91C_AES_TPR EQU( 0xFFFA4108 );
- -( PDC_AES ) Transmit Pointer Register
- AT91C_AES_PTCR EQU( 0xFFFA4120 );
- -( PDC_AES ) PDC Transfer Control Register
- AT91C_AES_RNPR EQU( 0xFFFA4110 );
- -( PDC_AES ) Receive Next Pointer Register
- AT91C_AES_TNCR EQU( 0xFFFA411C );
- -( PDC_AES ) Transmit Next Counter Register
- AT91C_AES_TCR EQU( 0xFFFA410C );
- -( PDC_AES ) Transmit Counter Register
- AT91C_AES_RCR EQU( 0xFFFA4104 );
- -( PDC_AES ) Receive Counter Register
- AT91C_AES_RNCR EQU( 0xFFFA4114 );
- -( PDC_AES ) Receive Next Counter Register
- AT91C_AES_TNPR EQU( 0xFFFA4118 );
- -( PDC_AES ) Transmit Next Pointer Register
- AT91C_AES_RPR EQU( 0xFFFA4100 );
- -( PDC_AES ) Receive Pointer Register
- AT91C_AES_PTSR EQU( 0xFFFA4124 );
- -( PDC_AES ) PDC Transfer Status Register
-/* - ========== Register definition for AES peripheral ========== */
- AT91C_AES_IVxR EQU( 0xFFFA4060 );
- -( AES ) Initialization Vector x Register
- AT91C_AES_MR EQU( 0xFFFA4004 );
- -( AES ) Mode Register
- AT91C_AES_VR EQU( 0xFFFA40FC );
- -( AES ) AES Version Register
- AT91C_AES_ODATAxR EQU( 0xFFFA4050 );
- -( AES ) Output Data x Register
- AT91C_AES_IDATAxR EQU( 0xFFFA4040 );
- -( AES ) Input Data x Register
- AT91C_AES_CR EQU( 0xFFFA4000 );
- -( AES ) Control Register
- AT91C_AES_IDR EQU( 0xFFFA4014 );
- -( AES ) Interrupt Disable Register
- AT91C_AES_IMR EQU( 0xFFFA4018 );
- -( AES ) Interrupt Mask Register
- AT91C_AES_IER EQU( 0xFFFA4010 );
- -( AES ) Interrupt Enable Register
- AT91C_AES_KEYWxR EQU( 0xFFFA4020 );
- -( AES ) Key Word x Register
- AT91C_AES_ISR EQU( 0xFFFA401C );
- -( AES ) Interrupt Status Register
-/* - ========== Register definition for PDC_TDES peripheral ========== */
- AT91C_TDES_RNCR EQU( 0xFFFA8114 );
- -( PDC_TDES ) Receive Next Counter Register
- AT91C_TDES_TCR EQU( 0xFFFA810C );
- -( PDC_TDES ) Transmit Counter Register
- AT91C_TDES_RCR EQU( 0xFFFA8104 );
- -( PDC_TDES ) Receive Counter Register
- AT91C_TDES_TNPR EQU( 0xFFFA8118 );
- -( PDC_TDES ) Transmit Next Pointer Register
- AT91C_TDES_RNPR EQU( 0xFFFA8110 );
- -( PDC_TDES ) Receive Next Pointer Register
- AT91C_TDES_RPR EQU( 0xFFFA8100 );
- -( PDC_TDES ) Receive Pointer Register
- AT91C_TDES_TNCR EQU( 0xFFFA811C );
- -( PDC_TDES ) Transmit Next Counter Register
- AT91C_TDES_TPR EQU( 0xFFFA8108 );
- -( PDC_TDES ) Transmit Pointer Register
- AT91C_TDES_PTSR EQU( 0xFFFA8124 );
- -( PDC_TDES ) PDC Transfer Status Register
- AT91C_TDES_PTCR EQU( 0xFFFA8120 );
- -( PDC_TDES ) PDC Transfer Control Register
-/* - ========== Register definition for TDES peripheral ========== */
- AT91C_TDES_KEY2WxR EQU( 0xFFFA8028 );
- -( TDES ) Key 2 Word x Register
- AT91C_TDES_KEY3WxR EQU( 0xFFFA8030 );
- -( TDES ) Key 3 Word x Register
- AT91C_TDES_IDR EQU( 0xFFFA8014 );
- -( TDES ) Interrupt Disable Register
- AT91C_TDES_VR EQU( 0xFFFA80FC );
- -( TDES ) TDES Version Register
- AT91C_TDES_IVxR EQU( 0xFFFA8060 );
- -( TDES ) Initialization Vector x Register
- AT91C_TDES_ODATAxR EQU( 0xFFFA8050 );
- -( TDES ) Output Data x Register
- AT91C_TDES_IMR EQU( 0xFFFA8018 );
- -( TDES ) Interrupt Mask Register
- AT91C_TDES_MR EQU( 0xFFFA8004 );
- -( TDES ) Mode Register
- AT91C_TDES_CR EQU( 0xFFFA8000 );
- -( TDES ) Control Register
- AT91C_TDES_IER EQU( 0xFFFA8010 );
- -( TDES ) Interrupt Enable Register
- AT91C_TDES_ISR EQU( 0xFFFA801C );
- -( TDES ) Interrupt Status Register
- AT91C_TDES_IDATAxR EQU( 0xFFFA8040 );
- -( TDES ) Input Data x Register
- AT91C_TDES_KEY1WxR EQU( 0xFFFA8020 );
- -( TDES ) Key 1 Word x Register
+// - *****************************************************************************
+// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// - *****************************************************************************
+// - ========== Register definition for SYS peripheral ==========
+// - ========== Register definition for AIC peripheral ==========
+AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
+AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register
+AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
+AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
+AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
+AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register
+AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
+AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
+AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
+AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
+AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
+AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
+AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
+AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
+AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
+AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
+AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
+AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
+// - ========== Register definition for PDC_DBGU peripheral ==========
+AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
+AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
+AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
+AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
+AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
+AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
+AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
+AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
+AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
+AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
+// - ========== Register definition for DBGU peripheral ==========
+AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
+AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
+AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
+AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
+AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
+AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register
+AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
+AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register
+AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
+AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
+AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
+AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
+// - ========== Register definition for PIOA peripheral ==========
+AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
+AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
+AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
+AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
+AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
+AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
+AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
+AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
+AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
+AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
+AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
+AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
+AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
+AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
+AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
+AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register
+AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
+AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
+AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
+AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
+AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register
+AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register
+AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
+AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
+AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
+AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
+AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
+AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
+AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
+// - ========== Register definition for PIOB peripheral ==========
+AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
+AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
+AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
+AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
+AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register
+AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
+AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
+AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
+AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
+AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
+AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
+AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
+AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
+AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
+AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
+AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
+AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
+AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
+AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
+AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
+AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
+AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
+AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register
+AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
+AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
+AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register
+AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
+AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
+AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
+// - ========== Register definition for CKGR peripheral ==========
+AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
+AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
+AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register
+// - ========== Register definition for PMC peripheral ==========
+AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
+AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
+AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register
+AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
+AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
+AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
+AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
+AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
+AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
+AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
+AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register
+AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
+AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
+AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
+AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register
+// - ========== Register definition for RSTC peripheral ==========
+AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
+AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
+AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
+// - ========== Register definition for RTTC peripheral ==========
+AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
+AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
+AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
+AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
+// - ========== Register definition for PITC peripheral ==========
+AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
+AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
+AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
+AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
+// - ========== Register definition for WDTC peripheral ==========
+AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
+AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
+AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
+// - ========== Register definition for VREG peripheral ==========
+AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
+// - ========== Register definition for MC peripheral ==========
+AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
+AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
+AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
+AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
+AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
+AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
+// - ========== Register definition for PDC_SPI1 peripheral ==========
+AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
+AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
+AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
+AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
+AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
+AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
+AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
+AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
+AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
+AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
+// - ========== Register definition for SPI1 peripheral ==========
+AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
+AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
+AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register
+AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
+AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
+AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register
+AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
+AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register
+AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
+// - ========== Register definition for PDC_SPI0 peripheral ==========
+AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
+AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
+AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
+AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
+AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
+AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
+AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
+AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
+AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
+AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
+// - ========== Register definition for SPI0 peripheral ==========
+AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
+AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register
+AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
+AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register
+AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register
+AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
+AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
+AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
+AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
+// - ========== Register definition for PDC_US1 peripheral ==========
+AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
+AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
+AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
+AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
+AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
+AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
+AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
+AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
+AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
+AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
+// - ========== Register definition for US1 peripheral ==========
+AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
+AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register
+AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
+AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register
+AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
+AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
+AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
+AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
+AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
+AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
+AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
+AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
+AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register
+AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register
+// - ========== Register definition for PDC_US0 peripheral ==========
+AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
+AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
+AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
+AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
+AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
+AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
+AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
+AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
+AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
+AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
+// - ========== Register definition for US0 peripheral ==========
+AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
+AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register
+AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register
+AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
+AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
+AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
+AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register
+AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
+AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register
+AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
+AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
+AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
+AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
+AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
+// - ========== Register definition for PDC_SSC peripheral ==========
+AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
+AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
+AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
+AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
+AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
+AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
+AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
+AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
+AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
+AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
+// - ========== Register definition for SSC peripheral ==========
+AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
+AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
+AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
+AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
+AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
+AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
+AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
+AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
+AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register
+AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
+AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
+AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register
+AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
+AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
+// - ========== Register definition for TWI peripheral ==========
+AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
+AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register
+AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register
+AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
+AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
+AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
+AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register
+AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register
+AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
+AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
+// - ========== Register definition for PWMC_CH3 peripheral ==========
+AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
+AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
+AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
+AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
+AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
+AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
+// - ========== Register definition for PWMC_CH2 peripheral ==========
+AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
+AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
+AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
+AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
+AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
+AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
+// - ========== Register definition for PWMC_CH1 peripheral ==========
+AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
+AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
+AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
+AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
+AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
+AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
+// - ========== Register definition for PWMC_CH0 peripheral ==========
+AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
+AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
+AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
+AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
+AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
+AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
+// - ========== Register definition for PWMC peripheral ==========
+AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
+AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
+AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
+AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
+AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
+AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
+AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
+AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
+AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
+// - ========== Register definition for UDP peripheral ==========
+AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
+AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register
+AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register
+AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
+AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
+AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
+AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
+AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
+AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
+AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
+AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register
+AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
+// - ========== Register definition for TC0 peripheral ==========
+AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register
+AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C
+AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B
+AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register
+AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
+AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A
+AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
+AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value
+AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
+// - ========== Register definition for TC1 peripheral ==========
+AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B
+AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register
+AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
+AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
+AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register
+AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A
+AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C
+AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
+AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value
+// - ========== Register definition for TC2 peripheral ==========
+AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register
+AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value
+AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A
+AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B
+AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
+AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
+AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C
+AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
+AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register
+// - ========== Register definition for TCB peripheral ==========
+AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
+AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
+// - ========== Register definition for CAN_MB0 peripheral ==========
+AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
+AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
+AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
+AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
+AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
+AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
+AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
+AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
+// - ========== Register definition for CAN_MB1 peripheral ==========
+AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
+AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
+AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
+AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
+AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
+AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
+AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
+AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
+// - ========== Register definition for CAN_MB2 peripheral ==========
+AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
+AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
+AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
+AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
+AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
+AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
+AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
+AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
+// - ========== Register definition for CAN_MB3 peripheral ==========
+AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
+AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
+AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
+AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
+AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
+AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
+AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
+AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
+// - ========== Register definition for CAN_MB4 peripheral ==========
+AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
+AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
+AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
+AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
+AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
+AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
+AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
+AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB5 peripheral ==========
+AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
+AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
+AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
+AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
+AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
+AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
+AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
+AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB6 peripheral ==========
+AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
+AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
+AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
+AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
+AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
+AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
+AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
+AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
+// - ========== Register definition for CAN_MB7 peripheral ==========
+AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
+AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
+AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
+AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
+AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
+AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
+AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
+AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
+// - ========== Register definition for CAN peripheral ==========
+AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
+AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
+AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
+AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register
+AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
+AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register
+AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
+AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register
+AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register
+AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register
+AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register
+AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register
+// - ========== Register definition for EMAC peripheral ==========
+AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
+AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
+AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
+AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
+AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
+AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
+AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
+AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
+AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
+AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register
+AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
+AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
+AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
+AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
+AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
+AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
+AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
+AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
+AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
+AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
+AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
+AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
+AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
+AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
+AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
+AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
+AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
+AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
+AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
+AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
+AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
+AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
+AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
+AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
+AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
+AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
+AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
+AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
+AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
+AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
+AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register
+AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
+AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
+AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
+AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
+AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
+AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
+AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
+AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
+// - ========== Register definition for PDC_ADC peripheral ==========
+AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
+AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
+AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
+AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
+AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
+AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
+AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
+AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
+AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
+AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
+// - ========== Register definition for ADC peripheral ==========
+AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
+AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
+AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
+AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
+AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
+AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register
+AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
+AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
+AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
+AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
+AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register
+AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
+AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
+AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
+AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
+AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
+AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
+AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
+// - ========== Register definition for PDC_AES peripheral ==========
+AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
+AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
+AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
+AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
+AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
+AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
+AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
+AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
+AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
+AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
+// - ========== Register definition for AES peripheral ==========
+AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
+AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register
+AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register
+AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register
+AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register
+AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register
+AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
+AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
+AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
+AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register
+AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
+// - ========== Register definition for PDC_TDES peripheral ==========
+AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
+AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
+AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
+AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
+AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
+AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
+AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
+AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
+AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
+AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
+// - ========== Register definition for TDES peripheral ==========
+AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
+AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
+AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
+AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
+AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
+AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register
+AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
+AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register
+AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register
+AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
+AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
+AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register
+AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
-/* - ***************************************************************************** */
-/* - PIO DEFINITIONS FOR AT91SAM7X256 */
-/* - ***************************************************************************** */
- AT91C_PIO_PA0 EQU( 1 << 0 );
- -Pin Controlled by PA0
- AT91C_PA0_RXD0 EQU( AT91C_PIO_PA0 );
- -USART 0 Receive Data
- AT91C_PIO_PA1 EQU( 1 << 1 );
- -Pin Controlled by PA1
- AT91C_PA1_TXD0 EQU( AT91C_PIO_PA1 );
- -USART 0 Transmit Data
- AT91C_PIO_PA10 EQU( 1 << 10 );
- -Pin Controlled by PA10
- AT91C_PA10_TWD EQU( AT91C_PIO_PA10 );
- -TWI Two - wire Serial Data
- AT91C_PIO_PA11 EQU( 1 << 11 );
- -Pin Controlled by PA11
- AT91C_PA11_TWCK EQU( AT91C_PIO_PA11 );
- -TWI Two - wire Serial Clock
- AT91C_PIO_PA12 EQU( 1 << 12 );
- -Pin Controlled by PA12
- AT91C_PA12_NPCS00 EQU( AT91C_PIO_PA12 );
- -SPI 0 Peripheral Chip Select 0
- AT91C_PIO_PA13 EQU( 1 << 13 );
- -Pin Controlled by PA13
- AT91C_PA13_NPCS01 EQU( AT91C_PIO_PA13 );
- -SPI 0 Peripheral Chip Select 1
- AT91C_PA13_PCK1 EQU( AT91C_PIO_PA13 );
- -PMC Programmable Clock Output 1
- AT91C_PIO_PA14 EQU( 1 << 14 );
- -Pin Controlled by PA14
- AT91C_PA14_NPCS02 EQU( AT91C_PIO_PA14 );
- -SPI 0 Peripheral Chip Select 2
- AT91C_PA14_IRQ1 EQU( AT91C_PIO_PA14 );
- -External Interrupt 1
- AT91C_PIO_PA15 EQU( 1 << 15 );
- -Pin Controlled by PA15
- AT91C_PA15_NPCS03 EQU( AT91C_PIO_PA15 );
- -SPI 0 Peripheral Chip Select 3
- AT91C_PA15_TCLK2 EQU( AT91C_PIO_PA15 );
- -Timer Counter 2 external clock input
- AT91C_PIO_PA16 EQU( 1 << 16 );
- -Pin Controlled by PA16
- AT91C_PA16_MISO0 EQU( AT91C_PIO_PA16 );
- -SPI 0 Master In Slave
- AT91C_PIO_PA17 EQU( 1 << 17 );
- -Pin Controlled by PA17
- AT91C_PA17_MOSI0 EQU( AT91C_PIO_PA17 );
- -SPI 0 Master Out Slave
- AT91C_PIO_PA18 EQU( 1 << 18 );
- -Pin Controlled by PA18
- AT91C_PA18_SPCK0 EQU( AT91C_PIO_PA18 );
- -SPI 0 Serial Clock
- AT91C_PIO_PA19 EQU( 1 << 19 );
- -Pin Controlled by PA19
- AT91C_PA19_CANRX EQU( AT91C_PIO_PA19 );
- -CAN Receive
- AT91C_PIO_PA2 EQU( 1 << 2 );
- -Pin Controlled by PA2
- AT91C_PA2_SCK0 EQU( AT91C_PIO_PA2 );
- -USART 0 Serial Clock
- AT91C_PA2_NPCS11 EQU( AT91C_PIO_PA2 );
- -SPI 1 Peripheral Chip Select 1
- AT91C_PIO_PA20 EQU( 1 << 20 );
- -Pin Controlled by PA20
- AT91C_PA20_CANTX EQU( AT91C_PIO_PA20 );
- -CAN Transmit
- AT91C_PIO_PA21 EQU( 1 << 21 );
- -Pin Controlled by PA21
- AT91C_PA21_TF EQU( AT91C_PIO_PA21 );
- -SSC Transmit Frame Sync
- AT91C_PA21_NPCS10 EQU( AT91C_PIO_PA21 );
- -SPI 1 Peripheral Chip Select 0
- AT91C_PIO_PA22 EQU( 1 << 22 );
- -Pin Controlled by PA22
- AT91C_PA22_TK EQU( AT91C_PIO_PA22 );
- -SSC Transmit Clock
- AT91C_PA22_SPCK1 EQU( AT91C_PIO_PA22 );
- -SPI 1 Serial Clock
- AT91C_PIO_PA23 EQU( 1 << 23 );
- -Pin Controlled by PA23
- AT91C_PA23_TD EQU( AT91C_PIO_PA23 );
- -SSC Transmit data
- AT91C_PA23_MOSI1 EQU( AT91C_PIO_PA23 );
- -SPI 1 Master Out Slave
- AT91C_PIO_PA24 EQU( 1 << 24 );
- -Pin Controlled by PA24
- AT91C_PA24_RD EQU( AT91C_PIO_PA24 );
- -SSC Receive Data
- AT91C_PA24_MISO1 EQU( AT91C_PIO_PA24 );
- -SPI 1 Master In Slave
- AT91C_PIO_PA25 EQU( 1 << 25 );
- -Pin Controlled by PA25
- AT91C_PA25_RK EQU( AT91C_PIO_PA25 );
- -SSC Receive Clock
- AT91C_PA25_NPCS11 EQU( AT91C_PIO_PA25 );
- -SPI 1 Peripheral Chip Select 1
- AT91C_PIO_PA26 EQU( 1 << 26 );
- -Pin Controlled by PA26
- AT91C_PA26_RF EQU( AT91C_PIO_PA26 );
- -SSC Receive Frame Sync
- AT91C_PA26_NPCS12 EQU( AT91C_PIO_PA26 );
- -SPI 1 Peripheral Chip Select 2
- AT91C_PIO_PA27 EQU( 1 << 27 );
- -Pin Controlled by PA27
- AT91C_PA27_DRXD EQU( AT91C_PIO_PA27 );
- -DBGU Debug Receive Data
- AT91C_PA27_PCK3 EQU( AT91C_PIO_PA27 );
- -PMC Programmable Clock Output 3
- AT91C_PIO_PA28 EQU( 1 << 28 );
- -Pin Controlled by PA28
- AT91C_PA28_DTXD EQU( AT91C_PIO_PA28 );
- -DBGU Debug Transmit Data
- AT91C_PIO_PA29 EQU( 1 << 29 );
- -Pin Controlled by PA29
- AT91C_PA29_FIQ EQU( AT91C_PIO_PA29 );
- -AIC Fast Interrupt Input
- AT91C_PA29_NPCS13 EQU( AT91C_PIO_PA29 );
- -SPI 1 Peripheral Chip Select 3
- AT91C_PIO_PA3 EQU( 1 << 3 );
- -Pin Controlled by PA3
- AT91C_PA3_RTS0 EQU( AT91C_PIO_PA3 );
- -USART 0 Ready To Send
- AT91C_PA3_NPCS12 EQU( AT91C_PIO_PA3 );
- -SPI 1 Peripheral Chip Select 2
- AT91C_PIO_PA30 EQU( 1 << 30 );
- -Pin Controlled by PA30
- AT91C_PA30_IRQ0 EQU( AT91C_PIO_PA30 );
- -External Interrupt 0
- AT91C_PA30_PCK2 EQU( AT91C_PIO_PA30 );
- -PMC Programmable Clock Output 2
- AT91C_PIO_PA4 EQU( 1 << 4 );
- -Pin Controlled by PA4
- AT91C_PA4_CTS0 EQU( AT91C_PIO_PA4 );
- -USART 0 Clear To Send
- AT91C_PA4_NPCS13 EQU( AT91C_PIO_PA4 );
- -SPI 1 Peripheral Chip Select 3
- AT91C_PIO_PA5 EQU( 1 << 5 );
- -Pin Controlled by PA5
- AT91C_PA5_RXD1 EQU( AT91C_PIO_PA5 );
- -USART 1 Receive Data
- AT91C_PIO_PA6 EQU( 1 << 6 );
- -Pin Controlled by PA6
- AT91C_PA6_TXD1 EQU( AT91C_PIO_PA6 );
- -USART 1 Transmit Data
- AT91C_PIO_PA7 EQU( 1 << 7 );
- -Pin Controlled by PA7
- AT91C_PA7_SCK1 EQU( AT91C_PIO_PA7 );
- -USART 1 Serial Clock
- AT91C_PA7_NPCS01 EQU( AT91C_PIO_PA7 );
- -SPI 0 Peripheral Chip Select 1
- AT91C_PIO_PA8 EQU( 1 << 8 );
- -Pin Controlled by PA8
- AT91C_PA8_RTS1 EQU( AT91C_PIO_PA8 );
- -USART 1 Ready To Send
- AT91C_PA8_NPCS02 EQU( AT91C_PIO_PA8 );
- -SPI 0 Peripheral Chip Select 2
- AT91C_PIO_PA9 EQU( 1 << 9 );
- -Pin Controlled by PA9
- AT91C_PA9_CTS1 EQU( AT91C_PIO_PA9 );
- -USART 1 Clear To Send
- AT91C_PA9_NPCS03 EQU( AT91C_PIO_PA9 );
- -SPI 0 Peripheral Chip Select 3
- AT91C_PIO_PB0 EQU( 1 << 0 );
- -Pin Controlled by PB0
- AT91C_PB0_ETXCK_EREFCK EQU( AT91C_PIO_PB0 );
- -Ethernet MAC Transmit Clock / Reference Clock
- AT91C_PB0_PCK0 EQU( AT91C_PIO_PB0 );
- -PMC Programmable Clock Output 0
- AT91C_PIO_PB1 EQU( 1 << 1 );
- -Pin Controlled by PB1
- AT91C_PB1_ETXEN EQU( AT91C_PIO_PB1 );
- -Ethernet MAC Transmit Enable
- AT91C_PIO_PB10 EQU( 1 << 10 );
- -Pin Controlled by PB10
- AT91C_PB10_ETX2 EQU( AT91C_PIO_PB10 );
- -Ethernet MAC Transmit Data 2
- AT91C_PB10_NPCS11 EQU( AT91C_PIO_PB10 );
- -SPI 1 Peripheral Chip Select 1
- AT91C_PIO_PB11 EQU( 1 << 11 );
- -Pin Controlled by PB11
- AT91C_PB11_ETX3 EQU( AT91C_PIO_PB11 );
- -Ethernet MAC Transmit Data 3
- AT91C_PB11_NPCS12 EQU( AT91C_PIO_PB11 );
- -SPI 1 Peripheral Chip Select 2
- AT91C_PIO_PB12 EQU( 1 << 12 );
- -Pin Controlled by PB12
- AT91C_PB12_ETXER EQU( AT91C_PIO_PB12 );
- -Ethernet MAC Transmikt Coding Error
- AT91C_PB12_TCLK0 EQU( AT91C_PIO_PB12 );
- -Timer Counter 0 external clock input
- AT91C_PIO_PB13 EQU( 1 << 13 );
- -Pin Controlled by PB13
- AT91C_PB13_ERX2 EQU( AT91C_PIO_PB13 );
- -Ethernet MAC Receive Data 2
- AT91C_PB13_NPCS01 EQU( AT91C_PIO_PB13 );
- -SPI 0 Peripheral Chip Select 1
- AT91C_PIO_PB14 EQU( 1 << 14 );
- -Pin Controlled by PB14
- AT91C_PB14_ERX3 EQU( AT91C_PIO_PB14 );
- -Ethernet MAC Receive Data 3
- AT91C_PB14_NPCS02 EQU( AT91C_PIO_PB14 );
- -SPI 0 Peripheral Chip Select 2
- AT91C_PIO_PB15 EQU( 1 << 15 );
- -Pin Controlled by PB15
- AT91C_PB15_ERXDV EQU( AT91C_PIO_PB15 );
- -Ethernet MAC Receive Data Valid
- AT91C_PIO_PB16 EQU( 1 << 16 );
- -Pin Controlled by PB16
- AT91C_PB16_ECOL EQU( AT91C_PIO_PB16 );
- -Ethernet MAC Collision Detected
- AT91C_PB16_NPCS13 EQU( AT91C_PIO_PB16 );
- -SPI 1 Peripheral Chip Select 3
- AT91C_PIO_PB17 EQU( 1 << 17 );
- -Pin Controlled by PB17
- AT91C_PB17_ERXCK EQU( AT91C_PIO_PB17 );
- -Ethernet MAC Receive Clock
- AT91C_PB17_NPCS03 EQU( AT91C_PIO_PB17 );
- -SPI 0 Peripheral Chip Select 3
- AT91C_PIO_PB18 EQU( 1 << 18 );
- -Pin Controlled by PB18
- AT91C_PB18_EF100 EQU( AT91C_PIO_PB18 );
- -Ethernet MAC Force 100 Mbits / sec
- AT91C_PB18_ADTRG EQU( AT91C_PIO_PB18 );
- -ADC External Trigger
- AT91C_PIO_PB19 EQU( 1 << 19 );
- -Pin Controlled by PB19
- AT91C_PB19_PWM0 EQU( AT91C_PIO_PB19 );
- -PWM Channel 0
- AT91C_PB19_TCLK1 EQU( AT91C_PIO_PB19 );
- -Timer Counter 1 external clock input
- AT91C_PIO_PB2 EQU( 1 << 2 );
- -Pin Controlled by PB2
- AT91C_PB2_ETX0 EQU( AT91C_PIO_PB2 );
- -Ethernet MAC Transmit Data 0
- AT91C_PIO_PB20 EQU( 1 << 20 );
- -Pin Controlled by PB20
- AT91C_PB20_PWM1 EQU( AT91C_PIO_PB20 );
- -PWM Channel 1
- AT91C_PB20_PCK0 EQU( AT91C_PIO_PB20 );
- -PMC Programmable Clock Output 0
- AT91C_PIO_PB21 EQU( 1 << 21 );
- -Pin Controlled by PB21
- AT91C_PB21_PWM2 EQU( AT91C_PIO_PB21 );
- -PWM Channel 2
- AT91C_PB21_PCK1 EQU( AT91C_PIO_PB21 );
- -PMC Programmable Clock Output 1
- AT91C_PIO_PB22 EQU( 1 << 22 );
- -Pin Controlled by PB22
- AT91C_PB22_PWM3 EQU( AT91C_PIO_PB22 );
- -PWM Channel 3
- AT91C_PB22_PCK2 EQU( AT91C_PIO_PB22 );
- -PMC Programmable Clock Output 2
- AT91C_PIO_PB23 EQU( 1 << 23 );
- -Pin Controlled by PB23
- AT91C_PB23_TIOA0 EQU( AT91C_PIO_PB23 );
- -Timer Counter 0 Multipurpose Timer I / O Pin A
- AT91C_PB23_DCD1 EQU( AT91C_PIO_PB23 );
- -USART 1 Data Carrier Detect
- AT91C_PIO_PB24 EQU( 1 << 24 );
- -Pin Controlled by PB24
- AT91C_PB24_TIOB0 EQU( AT91C_PIO_PB24 );
- -Timer Counter 0 Multipurpose Timer I / O Pin B
- AT91C_PB24_DSR1 EQU( AT91C_PIO_PB24 );
- -USART 1 Data Set ready
- AT91C_PIO_PB25 EQU( 1 << 25 );
- -Pin Controlled by PB25
- AT91C_PB25_TIOA1 EQU( AT91C_PIO_PB25 );
- -Timer Counter 1 Multipurpose Timer I / O Pin A
- AT91C_PB25_DTR1 EQU( AT91C_PIO_PB25 );
- -USART 1 Data Terminal ready
- AT91C_PIO_PB26 EQU( 1 << 26 );
- -Pin Controlled by PB26
- AT91C_PB26_TIOB1 EQU( AT91C_PIO_PB26 );
- -Timer Counter 1 Multipurpose Timer I / O Pin B
- AT91C_PB26_RI1 EQU( AT91C_PIO_PB26 );
- -USART 1 Ring Indicator
- AT91C_PIO_PB27 EQU( 1 << 27 );
- -Pin Controlled by PB27
- AT91C_PB27_TIOA2 EQU( AT91C_PIO_PB27 );
- -Timer Counter 2 Multipurpose Timer I / O Pin A
- AT91C_PB27_PWM0 EQU( AT91C_PIO_PB27 );
- -PWM Channel 0
- AT91C_PIO_PB28 EQU( 1 << 28 );
- -Pin Controlled by PB28
- AT91C_PB28_TIOB2 EQU( AT91C_PIO_PB28 );
- -Timer Counter 2 Multipurpose Timer I / O Pin B
- AT91C_PB28_PWM1 EQU( AT91C_PIO_PB28 );
- -PWM Channel 1
- AT91C_PIO_PB29 EQU( 1 << 29 );
- -Pin Controlled by PB29
- AT91C_PB29_PCK1 EQU( AT91C_PIO_PB29 );
- -PMC Programmable Clock Output 1
- AT91C_PB29_PWM2 EQU( AT91C_PIO_PB29 );
- -PWM Channel 2
- AT91C_PIO_PB3 EQU( 1 << 3 );
- -Pin Controlled by PB3
- AT91C_PB3_ETX1 EQU( AT91C_PIO_PB3 );
- -Ethernet MAC Transmit Data 1
- AT91C_PIO_PB30 EQU( 1 << 30 );
- -Pin Controlled by PB30
- AT91C_PB30_PCK2 EQU( AT91C_PIO_PB30 );
- -PMC Programmable Clock Output 2
- AT91C_PB30_PWM3 EQU( AT91C_PIO_PB30 );
- -PWM Channel 3
- AT91C_PIO_PB4 EQU( 1 << 4 );
- -Pin Controlled by PB4
- AT91C_PB4_ECRS_ECRSDV EQU( AT91C_PIO_PB4 );
- -Ethernet MAC Carrier Sense / Carrier Sense and Data Valid
- AT91C_PIO_PB5 EQU( 1 << 5 );
- -Pin Controlled by PB5
- AT91C_PB5_ERX0 EQU( AT91C_PIO_PB5 );
- -Ethernet MAC Receive Data 0
- AT91C_PIO_PB6 EQU( 1 << 6 );
- -Pin Controlled by PB6
- AT91C_PB6_ERX1 EQU( AT91C_PIO_PB6 );
- -Ethernet MAC Receive Data 1
- AT91C_PIO_PB7 EQU( 1 << 7 );
- -Pin Controlled by PB7
- AT91C_PB7_ERXER EQU( AT91C_PIO_PB7 );
- -Ethernet MAC Receive Error
- AT91C_PIO_PB8 EQU( 1 << 8 );
- -Pin Controlled by PB8
- AT91C_PB8_EMDC EQU( AT91C_PIO_PB8 );
- -Ethernet MAC Management Data Clock
- AT91C_PIO_PB9 EQU( 1 << 9 );
- -Pin Controlled by PB9
- AT91C_PB9_EMDIO EQU( AT91C_PIO_PB9 );
- -Ethernet MAC Management Data Input / Output
+// - *****************************************************************************
+// - PIO DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0
+AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data
+AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1
+AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data
+AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10
+AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data
+AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11
+AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock
+AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12
+AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0
+AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13
+AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1
+AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1
+AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14
+AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2
+AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1
+AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15
+AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3
+AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input
+AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16
+AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave
+AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17
+AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave
+AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18
+AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock
+AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19
+AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive
+AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2
+AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock
+AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20
+AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit
+AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21
+AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync
+AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0
+AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22
+AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock
+AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock
+AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23
+AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data
+AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave
+AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24
+AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data
+AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave
+AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25
+AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock
+AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26
+AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync
+AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27
+AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data
+AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3
+AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28
+AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data
+AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29
+AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input
+AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3
+AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send
+AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30
+AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0
+AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2
+AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4
+AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send
+AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5
+AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data
+AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6
+AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data
+AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7
+AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock
+AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8
+AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send
+AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9
+AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send
+AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0
+AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock
+AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0
+AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1
+AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable
+AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10
+AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2
+AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11
+AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3
+AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12
+AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error
+AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input
+AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13
+AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2
+AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14
+AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3
+AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15
+AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid
+AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16
+AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected
+AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17
+AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock
+AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18
+AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec
+AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger
+AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19
+AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0
+AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input
+AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2
+AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0
+AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20
+AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1
+AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0
+AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21
+AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2
+AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1
+AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22
+AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3
+AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2
+AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23
+AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A
+AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect
+AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24
+AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B
+AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready
+AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25
+AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A
+AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready
+AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26
+AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B
+AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator
+AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27
+AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A
+AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0
+AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28
+AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B
+AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1
+AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29
+AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1
+AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2
+AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3
+AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1
+AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30
+AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2
+AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3
+AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4
+AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5
+AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0
+AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6
+AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1
+AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7
+AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error
+AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8
+AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock
+AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9
+AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output
-/* - ***************************************************************************** */
-/* - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
-/* - ***************************************************************************** */
- AT91C_ID_FIQ EQU( 0 );
- -Advanced Interrupt Controller( FIQ )
- AT91C_ID_SYS EQU( 1 );
- -System Peripheral
- AT91C_ID_PIOA EQU( 2 );
- -Parallel IO Controller A
- AT91C_ID_PIOB EQU( 3 );
- -Parallel IO Controller B
- AT91C_ID_SPI0 EQU( 4 );
- -Serial Peripheral Interface 0
- AT91C_ID_SPI1 EQU( 5 );
- -Serial Peripheral Interface 1
- AT91C_ID_US0 EQU( 6 );
- -USART 0
- AT91C_ID_US1 EQU( 7 );
- -USART 1
- AT91C_ID_SSC EQU( 8 );
- -Serial Synchronous Controller
- AT91C_ID_TWI EQU( 9 );
- -Two - Wire Interface
- AT91C_ID_PWMC EQU( 10 );
- -PWM Controller
- AT91C_ID_UDP EQU( 11 );
- -USB Device Port
- AT91C_ID_TC0 EQU( 12 );
- -Timer Counter 0
- AT91C_ID_TC1 EQU( 13 );
- -Timer Counter 1
- AT91C_ID_TC2 EQU( 14 );
- -Timer Counter 2
- AT91C_ID_CAN EQU( 15 );
- -Control Area Network Controller
- AT91C_ID_EMAC EQU( 16 );
- -Ethernet MAC
- AT91C_ID_ADC EQU( 17 );
- -Analog - to - Digital Converter
- AT91C_ID_AES EQU( 18 );
- -Advanced Encryption Standard 128 - bit
- AT91C_ID_TDES EQU( 19 );
- -Triple Data Encryption Standard
- AT91C_ID_20_Reserved EQU( 20 );
- -Reserved
- AT91C_ID_21_Reserved EQU( 21 );
- -Reserved
- AT91C_ID_22_Reserved EQU( 22 );
- -Reserved
- AT91C_ID_23_Reserved EQU( 23 );
- -Reserved
- AT91C_ID_24_Reserved EQU( 24 );
- -Reserved
- AT91C_ID_25_Reserved EQU( 25 );
- -Reserved
- AT91C_ID_26_Reserved EQU( 26 );
- -Reserved
- AT91C_ID_27_Reserved EQU( 27 );
- -Reserved
- AT91C_ID_28_Reserved EQU( 28 );
- -Reserved
- AT91C_ID_29_Reserved EQU( 29 );
- -Reserved
- AT91C_ID_IRQ0 EQU( 30 );
- -Advanced Interrupt Controller( IRQ0 )
- AT91C_ID_IRQ1 EQU( 31 );
- -Advanced Interrupt Controller( IRQ1 )
+// - *****************************************************************************
+// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
+AT91C_ID_SYS EQU ( 1) ;- System Peripheral
+AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A
+AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B
+AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0
+AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1
+AT91C_ID_US0 EQU ( 6) ;- USART 0
+AT91C_ID_US1 EQU ( 7) ;- USART 1
+AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller
+AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface
+AT91C_ID_PWMC EQU (10) ;- PWM Controller
+AT91C_ID_UDP EQU (11) ;- USB Device Port
+AT91C_ID_TC0 EQU (12) ;- Timer Counter 0
+AT91C_ID_TC1 EQU (13) ;- Timer Counter 1
+AT91C_ID_TC2 EQU (14) ;- Timer Counter 2
+AT91C_ID_CAN EQU (15) ;- Control Area Network Controller
+AT91C_ID_EMAC EQU (16) ;- Ethernet MAC
+AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter
+AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit
+AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard
+AT91C_ID_20_Reserved EQU (20) ;- Reserved
+AT91C_ID_21_Reserved EQU (21) ;- Reserved
+AT91C_ID_22_Reserved EQU (22) ;- Reserved
+AT91C_ID_23_Reserved EQU (23) ;- Reserved
+AT91C_ID_24_Reserved EQU (24) ;- Reserved
+AT91C_ID_25_Reserved EQU (25) ;- Reserved
+AT91C_ID_26_Reserved EQU (26) ;- Reserved
+AT91C_ID_27_Reserved EQU (27) ;- Reserved
+AT91C_ID_28_Reserved EQU (28) ;- Reserved
+AT91C_ID_29_Reserved EQU (29) ;- Reserved
+AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0)
+AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1)
-/* - ***************************************************************************** */
-/* - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
-/* - ***************************************************************************** */
- AT91C_BASE_SYS EQU( 0xFFFFF000 );
- -( SYS ) Base Address
- AT91C_BASE_AIC EQU( 0xFFFFF000 );
- -( AIC ) Base Address
- AT91C_BASE_PDC_DBGU EQU( 0xFFFFF300 );
- -( PDC_DBGU ) Base Address
- AT91C_BASE_DBGU EQU( 0xFFFFF200 );
- -( DBGU ) Base Address
- AT91C_BASE_PIOA EQU( 0xFFFFF400 );
- -( PIOA ) Base Address
- AT91C_BASE_PIOB EQU( 0xFFFFF600 );
- -( PIOB ) Base Address
- AT91C_BASE_CKGR EQU( 0xFFFFFC20 );
- -( CKGR ) Base Address
- AT91C_BASE_PMC EQU( 0xFFFFFC00 );
- -( PMC ) Base Address
- AT91C_BASE_RSTC EQU( 0xFFFFFD00 );
- -( RSTC ) Base Address
- AT91C_BASE_RTTC EQU( 0xFFFFFD20 );
- -( RTTC ) Base Address
- AT91C_BASE_PITC EQU( 0xFFFFFD30 );
- -( PITC ) Base Address
- AT91C_BASE_WDTC EQU( 0xFFFFFD40 );
- -( WDTC ) Base Address
- AT91C_BASE_VREG EQU( 0xFFFFFD60 );
- -( VREG ) Base Address
- AT91C_BASE_MC EQU( 0xFFFFFF00 );
- -( MC ) Base Address
- AT91C_BASE_PDC_SPI1 EQU( 0xFFFE4100 );
- -( PDC_SPI1 ) Base Address
- AT91C_BASE_SPI1 EQU( 0xFFFE4000 );
- -( SPI1 ) Base Address
- AT91C_BASE_PDC_SPI0 EQU( 0xFFFE0100 );
- -( PDC_SPI0 ) Base Address
- AT91C_BASE_SPI0 EQU( 0xFFFE0000 );
- -( SPI0 ) Base Address
- AT91C_BASE_PDC_US1 EQU( 0xFFFC4100 );
- -( PDC_US1 ) Base Address
- AT91C_BASE_US1 EQU( 0xFFFC4000 );
- -( US1 ) Base Address
- AT91C_BASE_PDC_US0 EQU( 0xFFFC0100 );
- -( PDC_US0 ) Base Address
- AT91C_BASE_US0 EQU( 0xFFFC0000 );
- -( US0 ) Base Address
- AT91C_BASE_PDC_SSC EQU( 0xFFFD4100 );
- -( PDC_SSC ) Base Address
- AT91C_BASE_SSC EQU( 0xFFFD4000 );
- -( SSC ) Base Address
- AT91C_BASE_TWI EQU( 0xFFFB8000 );
- -( TWI ) Base Address
- AT91C_BASE_PWMC_CH3 EQU( 0xFFFCC260 );
- -( PWMC_CH3 ) Base Address
- AT91C_BASE_PWMC_CH2 EQU( 0xFFFCC240 );
- -( PWMC_CH2 ) Base Address
- AT91C_BASE_PWMC_CH1 EQU( 0xFFFCC220 );
- -( PWMC_CH1 ) Base Address
- AT91C_BASE_PWMC_CH0 EQU( 0xFFFCC200 );
- -( PWMC_CH0 ) Base Address
- AT91C_BASE_PWMC EQU( 0xFFFCC000 );
- -( PWMC ) Base Address
- AT91C_BASE_UDP EQU( 0xFFFB0000 );
- -( UDP ) Base Address
- AT91C_BASE_TC0 EQU( 0xFFFA0000 );
- -( TC0 ) Base Address
- AT91C_BASE_TC1 EQU( 0xFFFA0040 );
- -( TC1 ) Base Address
- AT91C_BASE_TC2 EQU( 0xFFFA0080 );
- -( TC2 ) Base Address
- AT91C_BASE_TCB EQU( 0xFFFA0000 );
- -( TCB ) Base Address
- AT91C_BASE_CAN_MB0 EQU( 0xFFFD0200 );
- -( CAN_MB0 ) Base Address
- AT91C_BASE_CAN_MB1 EQU( 0xFFFD0220 );
- -( CAN_MB1 ) Base Address
- AT91C_BASE_CAN_MB2 EQU( 0xFFFD0240 );
- -( CAN_MB2 ) Base Address
- AT91C_BASE_CAN_MB3 EQU( 0xFFFD0260 );
- -( CAN_MB3 ) Base Address
- AT91C_BASE_CAN_MB4 EQU( 0xFFFD0280 );
- -( CAN_MB4 ) Base Address
- AT91C_BASE_CAN_MB5 EQU( 0xFFFD02A0 );
- -( CAN_MB5 ) Base Address
- AT91C_BASE_CAN_MB6 EQU( 0xFFFD02C0 );
- -( CAN_MB6 ) Base Address
- AT91C_BASE_CAN_MB7 EQU( 0xFFFD02E0 );
- -( CAN_MB7 ) Base Address
- AT91C_BASE_CAN EQU( 0xFFFD0000 );
- -( CAN ) Base Address
- AT91C_BASE_EMAC EQU( 0xFFFDC000 );
- -( EMAC ) Base Address
- AT91C_BASE_PDC_ADC EQU( 0xFFFD8100 );
- -( PDC_ADC ) Base Address
- AT91C_BASE_ADC EQU( 0xFFFD8000 );
- -( ADC ) Base Address
- AT91C_BASE_PDC_AES EQU( 0xFFFA4100 );
- -( PDC_AES ) Base Address
- AT91C_BASE_AES EQU( 0xFFFA4000 );
- -( AES ) Base Address
- AT91C_BASE_PDC_TDES EQU( 0xFFFA8100 );
- -( PDC_TDES ) Base Address
- AT91C_BASE_TDES EQU( 0xFFFA8000 );
- -( TDES ) Base Address
+// - *****************************************************************************
+// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address
+AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address
+AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
+AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address
+AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address
+AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address
+AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address
+AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address
+AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address
+AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address
+AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address
+AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address
+AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address
+AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address
+AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
+AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address
+AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
+AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address
+AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address
+AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address
+AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address
+AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address
+AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
+AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address
+AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address
+AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
+AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
+AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
+AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
+AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address
+AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address
+AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address
+AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address
+AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address
+AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address
+AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
+AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
+AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
+AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
+AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
+AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
+AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
+AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
+AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address
+AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address
+AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
+AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address
+AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address
+AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address
+AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
+AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address
-/* - ***************************************************************************** */
-/* - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
-/* - ***************************************************************************** */
- AT91C_ISRAM EQU( 0x00200000 );
- -Internal SRAM base address
- AT91C_ISRAM_SIZE EQU( 0x00010000 );
- -Internal SRAM size in byte( 64 Kbyte )
- AT91C_IFLASH EQU( 0x00100000 );
- -Internal ROM base address
- AT91C_IFLASH_SIZE EQU( 0x00040000 );
- -Internal ROM size in byte( 256 Kbyte )
+// - *****************************************************************************
+// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address
+AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)
+AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address
+AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)
diff --git a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
index 94fdd73..9cbd823 100644
--- a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
+++ b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
@@ -1,50 +1,51 @@
-/** ---------------------------------------------------------------------------- */
-/** ATMEL Microcontroller Software Support - ROUSSET - */
-/** ---------------------------------------------------------------------------- */
-/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/** ---------------------------------------------------------------------------- */
-/** File Name : lib_AT91SAM7X256.h */
-/** Object : AT91SAM7X256 inlined functions */
-/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */
-/** */
-/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
-/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */
-/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */
-/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */
-/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
-/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */
-/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
-/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */
-/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */
-/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */
-/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */
-/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */
-/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */
-/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */
-/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */
-/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */
-/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
-/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */
-/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
-/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */
-/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
-/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */
-/** ---------------------------------------------------------------------------- */
+//* ----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name : lib_AT91SAM7X256.h
+//* Object : AT91SAM7X256 inlined functions
+//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+//*
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
+//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
#include "AT91SAM7X256.h"
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_ConfigureIt */
-/** \brief Interrupt Handler Initialization */
-/**---------------------------------------------------------------------------- */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+
diff --git a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
index 3c4fd7d..e66b4e1 100644
--- a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
@@ -1,4332 +1,4558 @@
-/** ---------------------------------------------------------------------------- */
-/** ATMEL Microcontroller Software Support - ROUSSET - */
-/** ---------------------------------------------------------------------------- */
-/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/** ---------------------------------------------------------------------------- */
-/** File Name : lib_AT91SAM7X256.h */
-/** Object : AT91SAM7X256 inlined functions */
-/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */
-/** */
-/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
-/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */
-/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */
-/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */
-/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
-/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */
-/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
-/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */
-/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */
-/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */
-/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */
-/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */
-/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */
-/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */
-/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */
-/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */
-/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
-/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */
-/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
-/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */
-/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
-/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */
-/** ---------------------------------------------------------------------------- */
+//* ----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name : lib_AT91SAM7X256.h
+//* Object : AT91SAM7X256 inlined functions
+//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+//*
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
+//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
#ifndef lib_AT91SAM7X256_H
#define lib_AT91SAM7X256_H
/* *****************************************************************************
-* SOFTWARE API FOR AIC
-***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */
+ SOFTWARE API FOR AIC
+ ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_ConfigureIt */
-/** \brief Interrupt Handler Initialization */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id, /* \arg interrupt number to initialize */
- unsigned int priority, /* \arg priority to give to the interrupt */
- unsigned int src_type, /* \arg activation and sense of activation */
- void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id, // \arg interrupt number to initialize
+ unsigned int priority, // \arg priority to give to the interrupt
+ unsigned int src_type, // \arg activation and sense of activation
+ void (*newHandler) (void) ) // \arg address of the interrupt handler
{
- unsigned int oldHandler;
- unsigned int mask;
+ unsigned int oldHandler;
+ unsigned int mask ;
- oldHandler = pAic->AIC_SVR[ irq_id ];
+ oldHandler = pAic->AIC_SVR[irq_id];
- mask = 0x1 << irq_id;
- /** Disable the interrupt on the interrupt controller */
- pAic->AIC_IDCR = mask;
- /** Save the interrupt handler routine pointer and the interrupt priority */
- pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;
- /** Store the Source Mode Register */
- pAic->AIC_SMR[ irq_id ] = src_type | priority;
- /** Clear the interrupt on the interrupt controller */
- pAic->AIC_ICCR = mask;
+ mask = 0x1 << irq_id ;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Save the interrupt handler routine pointer and the interrupt priority
+ pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+ //* Store the Source Mode Register
+ pAic->AIC_SMR[irq_id] = src_type | priority ;
+ //* Clear the interrupt on the interrupt controller
+ pAic->AIC_ICCR = mask ;
- return oldHandler;
+ return oldHandler;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_EnableIt */
-/** \brief Enable corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
{
- /** Enable the interrupt on the interrupt controller */
- pAic->AIC_IECR = 0x1 << irq_id;
+ //* Enable the interrupt on the interrupt controller
+ pAic->AIC_IECR = 0x1 << irq_id ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_DisableIt */
-/** \brief Disable corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
{
unsigned int mask = 0x1 << irq_id;
-
- /** Disable the interrupt on the interrupt controller */
- pAic->AIC_IDCR = mask;
- /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
- pAic->AIC_ICCR = mask;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = mask ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_ClearIt */
-/** \brief Clear corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number to initialize
{
- /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
- pAic->AIC_ICCR = ( 0x1 << irq_id );
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = (0x1 << irq_id);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_AcknowledgeIt */
-/** \brief Acknowledge corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+ AT91PS_AIC pAic) // \arg pointer to the AIC registers
{
pAic->AIC_EOICR = pAic->AIC_EOICR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_SetExceptionVector */
-/** \brief Configure vector handler */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */
- void ( * Handler )() ) /* \arg Interrupt Handler */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_SetExceptionVector (
+ unsigned int *pVector, // \arg pointer to the AIC registers
+ void (*Handler) () ) // \arg Interrupt Handler
{
- unsigned int oldVector = *pVector;
+ unsigned int oldVector = *pVector;
- if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE )
- {
- *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE;
- }
- else
- {
- *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000;
- }
+ if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+ *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+ else
+ *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
- return oldVector;
+ return oldVector;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_Trig */
-/** \brief Trig an IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Trig (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number
{
- pAic->AIC_ISCR = ( 0x1 << irq_id );
+ pAic->AIC_ISCR = (0x1 << irq_id) ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_IsActive */
-/** \brief Test if an IT is active */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg Interrupt Number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsActive (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
{
- return( pAic->AIC_ISR & ( 0x1 << irq_id ) );
+ return (pAic->AIC_ISR & (0x1 << irq_id));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_IsPending */
-/** \brief Test if an IT is pending */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg Interrupt Number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsPending (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
{
- return( pAic->AIC_IPR & ( 0x1 << irq_id ) );
+ return (pAic->AIC_IPR & (0x1 << irq_id));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_Open */
-/** \brief Set exception vectors and AIC registers to default values */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- void ( * IrqHandler )(), /* \arg Default IRQ vector exception */
- void ( * FiqHandler )(), /* \arg Default FIQ vector exception */
- void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */
- void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */
- unsigned int protectMode ) /* \arg Debug Control Register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ void (*IrqHandler) (), // \arg Default IRQ vector exception
+ void (*FiqHandler) (), // \arg Default FIQ vector exception
+ void (*DefaultHandler) (), // \arg Default Handler set in ISR
+ void (*SpuriousHandler) (), // \arg Default Spurious Handler
+ unsigned int protectMode) // \arg Debug Control Register
{
- int i;
+ int i;
- /* Disable all interrupts and set IVR to the default handler */
- for( i = 0; i < 32; ++i )
- {
- AT91F_AIC_DisableIt( pAic, i );
- AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler );
- }
+ // Disable all interrupts and set IVR to the default handler
+ for (i = 0; i < 32; ++i) {
+ AT91F_AIC_DisableIt(pAic, i);
+ AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
+ }
- /* Set the IRQ exception vector */
- AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler );
- /* Set the Fast Interrupt exception vector */
- AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler );
+ // Set the IRQ exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+ // Set the Fast Interrupt exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
- pAic->AIC_SPU = ( unsigned int ) SpuriousHandler;
- pAic->AIC_DCR = protectMode;
+ pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+ pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+ SOFTWARE API FOR PDC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RNPR = (unsigned int) address;
+ pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TNPR = (unsigned int) address;
+ pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RPR = (unsigned int) address;
+ pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TPR = (unsigned int) address;
+ pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+ //* Enable the RX and TX PDC transfer requests
+ AT91F_PDC_EnableRx(pPDC);
+ AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ if (AT91F_PDC_IsTxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ if (AT91F_PDC_IsRxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+/* *****************************************************************************
+ SOFTWARE API FOR DBGU
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be enabled
+{
+ pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be disabled
+{
+ pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+ AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller
+{
+ return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR PDC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetNextRx */
-/** \brief Set the next receive transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be received */
- unsigned int bytes ) /* \arg number of bytes to be received */
+ SOFTWARE API FOR PIO
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int periphAEnable, // \arg PERIPH A to enable
+ unsigned int periphBEnable) // \arg PERIPH B to enable
+
{
- pPDC->PDC_RNPR = ( unsigned int ) address;
- pPDC->PDC_RNCR = bytes;
+ pPio->PIO_ASR = periphAEnable;
+ pPio->PIO_BSR = periphBEnable;
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetNextTx */
-/** \brief Set the next transmit transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be transmitted */
- unsigned int bytes ) /* \arg number of bytes to be transmitted */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pioEnable) // \arg PIO to be enabled
{
- pPDC->PDC_TNPR = ( unsigned int ) address;
- pPDC->PDC_TNCR = bytes;
+ pPio->PIO_PER = pioEnable; // Set in PIO mode
+ pPio->PIO_OER = pioEnable; // Configure in Output
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetRx */
-/** \brief Set the receive transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be received */
- unsigned int bytes ) /* \arg number of bytes to be received */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputEnable) // \arg PIO to be enabled
{
- pPDC->PDC_RPR = ( unsigned int ) address;
- pPDC->PDC_RCR = bytes;
+ // Disable output
+ pPio->PIO_ODR = inputEnable;
+ pPio->PIO_PER = inputEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetTx */
-/** \brief Set the transmit transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be transmitted */
- unsigned int bytes ) /* \arg number of bytes to be transmitted */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int multiDrvEnable) // \arg pio to be configured in open drain
{
- pPDC->PDC_TPR = ( unsigned int ) address;
- pPDC->PDC_TCR = bytes;
+ // Configure the multi-drive option
+ pPio->PIO_MDDR = ~multiDrvEnable;
+ pPio->PIO_MDER = multiDrvEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_EnableTx */
-/** \brief Enable transmit */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pullupEnable) // \arg enable pullup on PIO
{
- pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+ // Connect or not Pullup
+ pPio->PIO_PPUDR = ~pullupEnable;
+ pPio->PIO_PPUER = pullupEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_EnableRx */
-/** \brief Enable receive */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int directDrive) // \arg PIO to be configured with direct drive
+
{
- pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+ // Configure the Direct Drive
+ pPio->PIO_OWDR = ~directDrive;
+ pPio->PIO_OWER = directDrive;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_DisableTx */
-/** \brief Disable transmit */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputFilter) // \arg PIO to be configured with input filter
+
{
- pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+ // Configure the Direct Drive
+ pPio->PIO_IFDR = ~inputFilter;
+ pPio->PIO_IFER = inputFilter;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_DisableRx */
-/** \brief Disable receive */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+ return pPio->PIO_PDSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsTxEmpty */
-/** \brief Test if the current transfer descriptor has been sent */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return !( pPDC->PDC_TCR );
+ return (AT91F_PIO_GetInput(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsNextTxEmpty */
-/** \brief Test if the next transfer descriptor has been moved to the current td */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be set
{
- return !( pPDC->PDC_TNCR );
+ pPio->PIO_SODR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsRxEmpty */
-/** \brief Test if the current transfer descriptor has been filled */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be cleared
{
- return !( pPDC->PDC_RCR );
+ pPio->PIO_CODR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsNextRxEmpty */
-/** \brief Test if the next transfer descriptor has been moved to the current td */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be forced
{
- return !( pPDC->PDC_RNCR );
+ pPio->PIO_ODSR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_Open */
-/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
{
- /** Disable the RX and TX PDC transfer requests */
- AT91F_PDC_DisableRx( pPDC );
- AT91F_PDC_DisableTx( pPDC );
-
- /** Reset all Counter register Next buffer first */
- AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
-
- /** Enable the RX and TX PDC transfer requests */
- AT91F_PDC_EnableRx( pPDC );
- AT91F_PDC_EnableTx( pPDC );
+ pPio->PIO_PER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_Close */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
{
- /** Disable the RX and TX PDC transfer requests */
- AT91F_PDC_DisableRx( pPDC );
- AT91F_PDC_DisableTx( pPDC );
-
- /** Reset all Counter register Next buffer first */
- AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+ pPio->PIO_PDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SendFrame */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- if( AT91F_PDC_IsTxEmpty( pPDC ) )
- {
- /** Buffer and next buffer can be initialized */
- AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer );
- AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer );
- return 2;
- }
- else if( AT91F_PDC_IsNextTxEmpty( pPDC ) )
- {
- /** Only one buffer can be initialized */
- AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer );
- return 1;
- }
- else
- {
- /** All buffer are in use... */
- return 0;
- }
+ return pPio->PIO_PSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_ReceiveFrame */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- if( AT91F_PDC_IsRxEmpty( pPDC ) )
- {
- /** Buffer and next buffer can be initialized */
- AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer );
- AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer );
- return 2;
- }
- else if( AT91F_PDC_IsNextRxEmpty( pPDC ) )
- {
- /** Only one buffer can be initialized */
- AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer );
- return 1;
- }
- else
- {
- /** All buffer are in use... */
- return 0;
- }
+ return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be enabled
+{
+ pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be disabled
+{
+ pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be enabled
+{
+ pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be disabled
+{
+ pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be enabled
+{
+ pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be disabled
+{
+ pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
+{
+ pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
+{
+ pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio A register selection
+{
+ pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio B register selection
+{
+ pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be enabled
+{
+ pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be disabled
+{
+ pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR DBGU
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_InterruptEnable */
-/** \brief Enable DBGU Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg dbgu interrupt to be enabled */
+ SOFTWARE API FOR PMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
{
- pDbgu->DBGU_IER = flag;
+ //* Write to the SCER register
+ pPMC->PMC_SCER = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_InterruptDisable */
-/** \brief Disable DBGU Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg dbgu interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
{
- pDbgu->DBGU_IDR = flag;
+ //* Write to the SCDR register
+ pPMC->PMC_SCDR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_GetInterruptMaskStatus */
-/** \brief Return DBGU Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */
- AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+ AT91PS_PMC pPMC // pointer to a CAN controller
+ )
{
- return pDbgu->DBGU_IMR;
+ return pPMC->PMC_SCSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_IsInterruptMasked */
-/** \brief Test if DBGU Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
{
- return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag );
+ pPMC->PMC_PCER = periphIds;
}
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
+{
+ pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+ return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int mode)
+{
+ pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int startup_time, // \arg main osc startup time in microsecond (us)
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+ pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
+{
+ pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+ return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ unsigned int reg = pPMC->PMC_MCKR;
+ unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+ unsigned int pllDivider, pllMultiplier;
+
+ switch (reg & AT91C_PMC_CSS) {
+ case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+ return slowClock / prescaler;
+ case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+ case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+ reg = pCKGR->CKGR_PLLR;
+ pllDivider = (reg & AT91C_CKGR_DIV);
+ pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+ }
+ return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck, // \arg Peripheral clock identifier 0 .. 7
+ unsigned int mode)
+{
+ pPMC->PMC_PCKR[pck] = mode;
+ pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck) // \arg Peripheral clock identifier 0 .. 7
+{
+ pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be enabled
+{
+ //* Write to the IER register
+ pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be disabled
+{
+ //* Write to the IDR register
+ pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+ return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+ return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+ SOFTWARE API FOR RSTC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+ AT91PS_RSTC pRSTC,
+ unsigned int reset)
+{
+ pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+ AT91PS_RSTC pRSTC,
+ unsigned int mode)
+{
+ pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+ AT91PS_RSTC pRSTC)
+{
+ return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+ AT91PS_RSTC pRSTC)
+{
+ return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+ AT91PS_RSTC pRSTC)
+{
+ return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
/* *****************************************************************************
-* SOFTWARE API FOR PIO
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgPeriph */
-/** \brief Enable pins to be drived by peripheral */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int periphAEnable, /* \arg PERIPH A to enable */
- unsigned int periphBEnable ) /* \arg PERIPH B to enable */
-
+ SOFTWARE API FOR RTTC
+ ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_SetRTT_TimeBase()
+//* \brief Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+ AT91PS_RTTC pRTTC,
+ unsigned int ms)
{
- pPio->PIO_ASR = periphAEnable;
- pPio->PIO_BSR = periphBEnable;
- pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */
+ if (ms > 2000)
+ return 1; // AT91C_TIME_OUT_OF_RANGE
+ pRTTC->RTTC_RTMR &= ~0xFFFF;
+ pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
+ return 0;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgOutput */
-/** \brief Enable PIO in output mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int pioEnable ) /* \arg PIO to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTSetPrescaler()
+//* \brief Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+ AT91PS_RTTC pRTTC,
+ unsigned int rtpres)
{
- pPio->PIO_PER = pioEnable; /* Set in PIO mode */
- pPio->PIO_OER = pioEnable; /* Configure in Output */
+ pRTTC->RTTC_RTMR &= ~0xFFFF;
+ pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
+ return (pRTTC->RTTC_RTMR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgInput */
-/** \brief Enable PIO in input mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int inputEnable ) /* \arg PIO to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTRestart()
+//* \brief Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+ AT91PS_RTTC pRTTC)
{
- /* Disable output */
- pPio->PIO_ODR = inputEnable;
- pPio->PIO_PER = inputEnable;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgOpendrain */
-/** \brief Configure PIO in open drain */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */
-{
- /* Configure the multi-drive option */
- pPio->PIO_MDDR = ~multiDrvEnable;
- pPio->PIO_MDER = multiDrvEnable;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgPullup */
-/** \brief Enable pullup on PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int pullupEnable ) /* \arg enable pullup on PIO */
-{
- /* Connect or not Pullup */
- pPio->PIO_PPUDR = ~pullupEnable;
- pPio->PIO_PPUER = pullupEnable;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgDirectDrive */
-/** \brief Enable direct drive on PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int directDrive ) /* \arg PIO to be configured with direct drive */
-
-{
- /* Configure the Direct Drive */
- pPio->PIO_OWDR = ~directDrive;
- pPio->PIO_OWER = directDrive;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgInputFilter */
-/** \brief Enable input filter on input PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int inputFilter ) /* \arg PIO to be configured with input filter */
-
-{
- /* Configure the Direct Drive */
- pPio->PIO_IFDR = ~inputFilter;
- pPio->PIO_IFER = inputFilter;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInput */
-/** \brief Return PIO input value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_PDSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInputSet */
-/** \brief Test if PIO is input flag is active */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInput( pPio ) & flag );
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_SetOutput */
-/** \brief Set to 1 output PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be set */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetAlarmINT()
+//* \brief Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_SODR = flag;
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_ClearOutput */
-/** \brief Set to 0 output PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be cleared */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ClearAlarmINT()
+//* \brief Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_CODR = flag;
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_ForceOutput */
-/** \brief Force output when Direct drive option is enabled */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be forced */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetRttIncINT()
+//* \brief Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_ODSR = flag;
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Enable */
-/** \brief Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ClearRttIncINT()
+//* \brief Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_PER = flag;
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Disable */
-/** \brief Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be disabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetAlarmValue()
+//* \brief Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+ AT91PS_RTTC pRTTC, unsigned int alarm)
{
- pPio->PIO_PDR = flag;
+ pRTTC->RTTC_RTAR = alarm;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetStatus */
-/** \brief Return PIO Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_GetAlarmValue()
+//* \brief Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+ AT91PS_RTTC pRTTC)
{
- return pPio->PIO_PSR;
+ return(pRTTC->RTTC_RTAR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsSet */
-/** \brief Test if PIO is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTGetStatus()
+//* \brief Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+ AT91PS_RTTC pRTTC)
{
- return( AT91F_PIO_GetStatus( pPio ) & flag );
+ return(pRTTC->RTTC_RTSR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputEnable */
-/** \brief Output Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ReadValue()
+//* \brief Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_OER = flag;
+ register volatile unsigned int val1,val2;
+ do
+ {
+ val1 = pRTTC->RTTC_RTVR;
+ val2 = pRTTC->RTTC_RTVR;
+ }
+ while(val1 != val2);
+ return(val1);
}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputDisable */
-/** \brief Output Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output to be disabled */
-{
- pPio->PIO_ODR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputStatus */
-/** \brief Return PIO Output Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_OSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOuputSet */
-/** \brief Test if PIO Output is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetOutputStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InputFilterEnable */
-/** \brief Input Filter Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio input filter to be enabled */
-{
- pPio->PIO_IFER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InputFilterDisable */
-/** \brief Input Filter Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio input filter to be disabled */
-{
- pPio->PIO_IFDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInputFilterStatus */
-/** \brief Return PIO Input Filter Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_IFSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInputFilterSet */
-/** \brief Test if PIO Input filter is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputDataStatus */
-/** \brief Return PIO Output Data Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_ODSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InterruptEnable */
-/** \brief Enable PIO Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio interrupt to be enabled */
-{
- pPio->PIO_IER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InterruptDisable */
-/** \brief Disable PIO Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio interrupt to be disabled */
-{
- pPio->PIO_IDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInterruptMaskStatus */
-/** \brief Return PIO Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_IMR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInterruptStatus */
-/** \brief Return PIO Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_ISR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInterruptMasked */
-/** \brief Test if PIO Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInterruptSet */
-/** \brief Test if PIO Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInterruptStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_MultiDriverEnable */
-/** \brief Multi Driver Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be enabled */
-{
- pPio->PIO_MDER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_MultiDriverDisable */
-/** \brief Multi Driver Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be disabled */
-{
- pPio->PIO_MDDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetMultiDriverStatus */
-/** \brief Return PIO Multi Driver Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_MDSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsMultiDriverSet */
-/** \brief Test if PIO MultiDriver is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_A_RegisterSelection */
-/** \brief PIO A Register Selection */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio A register selection */
-{
- pPio->PIO_ASR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_B_RegisterSelection */
-/** \brief PIO B Register Selection */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio B register selection */
-{
- pPio->PIO_BSR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Get_AB_RegisterStatus */
-/** \brief Return PIO Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_ABSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsAB_RegisterSet */
-/** \brief Test if PIO AB Register is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputWriteEnable */
-/** \brief Output Write Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output write to be enabled */
-{
- pPio->PIO_OWER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputWriteDisable */
-/** \brief Output Write Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output write to be disabled */
-{
- pPio->PIO_OWDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputWriteStatus */
-/** \brief Return PIO Output Write Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_OWSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOutputWriteSet */
-/** \brief Test if PIO OutputWrite is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetCfgPullup */
-/** \brief Return PIO Configuration Pullup */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_PPUSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOutputDataStatusSet */
-/** \brief Test if PIO Output Data Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsCfgPullupStatusSet */
-/** \brief Test if PIO Configuration Pullup Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag );
-}
-
/* *****************************************************************************
-* SOFTWARE API FOR PMC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgSysClkEnableReg */
-/** \brief Configure the System Clock Enable Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
+ SOFTWARE API FOR PITC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITInit
+//* \brief System timer init : period in µsecond, system clock freq in MHz
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITInit(
+ AT91PS_PITC pPITC,
+ unsigned int period,
+ unsigned int pit_frequency)
{
- /** Write to the SCER register */
- pPMC->PMC_SCER = mode;
+ pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+ pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgSysClkDisableReg */
-/** \brief Configure the System Clock Disable Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITSetPIV
+//* \brief Set the PIT Periodic Interval Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITSetPIV(
+ AT91PS_PITC pPITC,
+ unsigned int piv)
{
- /** Write to the SCDR register */
- pPMC->PMC_SCDR = mode;
+ pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetSysClkStatusReg */
-/** \brief Return the System Clock Status Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITEnableInt
+//* \brief Enable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITEnableInt(
+ AT91PS_PITC pPITC)
{
- return pPMC->PMC_SCSR;
+ pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnablePeriphClock */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITDisableInt
+//* \brief Disable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITDisableInt(
+ AT91PS_PITC pPITC)
{
- pPMC->PMC_PCER = periphIds;
+ pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisablePeriphClock */
-/** \brief Disable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetMode
+//* \brief Read PIT mode register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetMode(
+ AT91PS_PITC pPITC)
{
- pPMC->PMC_PCDR = periphIds;
+ return(pPITC->PITC_PIMR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetPeriphClock */
-/** \brief Get peripheral clock status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetStatus
+//* \brief Read PIT status register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetStatus(
+ AT91PS_PITC pPITC)
{
- return pPMC->PMC_PCSR;
+ return(pPITC->PITC_PISR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_CfgMainOscillatorReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetPIIR
+//* \brief Read PIT CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIIR(
+ AT91PS_PITC pPITC)
{
- pCKGR->CKGR_MOR = mode;
+ return(pPITC->PITC_PIIR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainOscillatorReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetPIVR
+//* \brief Read System timer CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIVR(
+ AT91PS_PITC pPITC)
{
- return pCKGR->CKGR_MOR;
+ return(pPITC->PITC_PIVR);
}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_EnableMainOscillator */
-/** \brief Enable the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
-{
- pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_DisableMainOscillator */
-/** \brief Disable the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
-{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_CfgMainOscStartUpTime */
-/** \brief Cfg MOR Register according to the main osc startup time */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
- unsigned int slowClock ) /* \arg slowClock in Hz */
-{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
- pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainClockFreqReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
-{
- return pCKGR->CKGR_MCFR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainClock */
-/** \brief Return Main clock in Hz */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int slowClock ) /* \arg slowClock in Hz */
-{
- return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgMCKReg */
-/** \brief Cfg Master Clock Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
-{
- pPMC->PMC_MCKR = mode;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetMCKReg */
-/** \brief Return Master Clock Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
-{
- return pPMC->PMC_MCKR;
-}
-
-/**------------------------------------------------------------------------------ */
-/** \fn AT91F_PMC_GetMasterClock */
-/** \brief Return master clock in Hz which correponds to processor clock for ARM7 */
-/**------------------------------------------------------------------------------ */
-__inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int slowClock ) /* \arg slowClock in Hz */
-{
- unsigned int reg = pPMC->PMC_MCKR;
- unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) );
- unsigned int pllDivider, pllMultiplier;
-
- switch( reg & AT91C_PMC_CSS )
- {
- case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */
- return slowClock / prescaler;
-
- case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */
- return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
-
- case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */
- reg = pCKGR->CKGR_PLLR;
- pllDivider = ( reg & AT91C_CKGR_DIV );
- pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
- return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
- }
-
- return 0;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnablePCK */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */
- unsigned int mode )
-{
- pPMC->PMC_PCKR[ pck ] = mode;
- pPMC->PMC_SCER = ( 1 << pck ) << 8;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisablePCK */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */
-{
- pPMC->PMC_SCDR = ( 1 << pck ) << 8;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnableIt */
-/** \brief Enable PMC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */
- unsigned int flag ) /* IT to be enabled */
-{
- /** Write to the IER register */
- pPMC->PMC_IER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisableIt */
-/** \brief Disable PMC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */
- unsigned int flag ) /* IT to be disabled */
-{
- /** Write to the IDR register */
- pPMC->PMC_IDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetStatus */
-/** \brief Return PMC Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */
- AT91PS_PMC pPMC ) /* pointer to a PMC controller */
-{
- return pPMC->PMC_SR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetInterruptMaskStatus */
-/** \brief Return PMC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */
- AT91PS_PMC pPMC ) /* pointer to a PMC controller */
-{
- return pPMC->PMC_IMR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_IsInterruptMasked */
-/** \brief Test if PMC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_IsStatusSet */
-/** \brief Test if PMC Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PMC_GetStatus( pPMC ) & flag );
-} /* *****************************************************************************
- * SOFTWARE API FOR RSTC
- ***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTSoftReset */
-/** \brief Start Software Reset */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC,
- unsigned int reset )
-{
- pRSTC->RSTC_RCR = ( 0xA5000000 | reset );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTSetMode */
-/** \brief Set Reset Mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC,
- unsigned int mode )
-{
- pRSTC->RSTC_RMR = ( 0xA5000000 | mode );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTGetMode */
-/** \brief Get Reset Mode */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC )
-{
- return( pRSTC->RSTC_RMR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTGetStatus */
-/** \brief Get Reset Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC )
-{
- return( pRSTC->RSTC_RSR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTIsSoftRstActive */
-/** \brief Return !=0 if software reset is still not completed */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC )
-{
- return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP );
-}
-
/* *****************************************************************************
-* SOFTWARE API FOR RTTC
-***************************************************************************** */
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_SetRTT_TimeBase() */
-/** \brief Set the RTT prescaler according to the TimeBase in ms */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC,
- unsigned int ms )
+ SOFTWARE API FOR WDTC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTSetMode
+//* \brief Set Watchdog Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTSetMode(
+ AT91PS_WDTC pWDTC,
+ unsigned int Mode)
{
- if( ms > 2000 )
- {
- return 1; /* AT91C_TIME_OUT_OF_RANGE */
- }
-
- pRTTC->RTTC_RTMR &= ~0xFFFF;
- pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF );
- return 0;
+ pWDTC->WDTC_WDMR = Mode;
}
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTTSetPrescaler() */
-/** \brief Set the new prescaler value */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC,
- unsigned int rtpres )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTRestart
+//* \brief Restart Watchdog
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTRestart(
+ AT91PS_WDTC pWDTC)
{
- pRTTC->RTTC_RTMR &= ~0xFFFF;
- pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF );
- return( pRTTC->RTTC_RTMR );
+ pWDTC->WDTC_WDCR = 0xA5000001;
}
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTTRestart() */
-/** \brief Restart the RTT prescaler */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTSGettatus
+//* \brief Get Watchdog Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTSGettatus(
+ AT91PS_WDTC pWDTC)
{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
+ return(pWDTC->WDTC_WDSR & 0x3);
}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_SetAlarmINT() */
-/** \brief Enable RTT Alarm Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTGetPeriod
+//* \brief Translate ms into Watchdog Compatible value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+ if ((ms < 4) || (ms > 16000))
+ return 0;
+ return((ms << 8) / 1000);
}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_ClearAlarmINT() */
-/** \brief Disable RTT Alarm Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_SetRttIncINT() */
-/** \brief Enable RTT INC Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_ClearRttIncINT() */
-/** \brief Disable RTT INC Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_SetAlarmValue() */
-/** \brief Set RTT Alarm Value */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC,
- unsigned int alarm )
-{
- pRTTC->RTTC_RTAR = alarm;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_GetAlarmValue() */
-/** \brief Get RTT Alarm Value */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC )
-{
- return( pRTTC->RTTC_RTAR );
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTTGetStatus() */
-/** \brief Read the RTT status */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC )
-{
- return( pRTTC->RTTC_RTSR );
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_ReadValue() */
-/** \brief Read the RTT value */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC )
-{
- register volatile unsigned int val1, val2;
-
- do
- {
- val1 = pRTTC->RTTC_RTVR;
- val2 = pRTTC->RTTC_RTVR;
- }
- while( val1 != val2 );
-
- return( val1 );
-}
-
/* *****************************************************************************
-* SOFTWARE API FOR PITC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITInit */
-/** \brief System timer init : period in µsecond, system clock freq in MHz */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITInit( AT91PS_PITC pPITC,
- unsigned int period,
- unsigned int pit_frequency )
+ SOFTWARE API FOR VREG
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_Enable_LowPowerMode
+//* \brief Enable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Enable_LowPowerMode(
+ AT91PS_VREG pVREG)
{
- pPITC->PITC_PIMR = period ? ( period * pit_frequency + 8 ) >> 4 : 0; /* +8 to avoid %10 and /10 */
- pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
+ pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITSetPIV */
-/** \brief Set the PIT Periodic Interval Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITSetPIV( AT91PS_PITC pPITC,
- unsigned int piv )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_Disable_LowPowerMode
+//* \brief Disable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Disable_LowPowerMode(
+ AT91PS_VREG pVREG)
{
- pPITC->PITC_PIMR = piv | ( pPITC->PITC_PIMR & ( AT91C_PITC_PITEN | AT91C_PITC_PITIEN ) );
-}
+ pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
+}/* *****************************************************************************
+ SOFTWARE API FOR MC
+ ***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITEnableInt */
-/** \brief Enable PIT periodic interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITEnableInt( AT91PS_PITC pPITC )
+#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void) //
{
- pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITDisableInt */
-/** \brief Disable PIT periodic interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITDisableInt( AT91PS_PITC pPITC )
-{
- pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetMode */
-/** \brief Read PIT mode register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetMode( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PIMR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetStatus */
-/** \brief Read PIT status register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetStatus( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PISR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetPIIR */
-/** \brief Read PIT CPIV and PICNT without ressetting the counters */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetPIIR( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PIIR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetPIVR */
-/** \brief Read System timer CPIV and PICNT without ressetting the counters */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetPIVR( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PIVR );
-}
-
-/* *****************************************************************************
-* SOFTWARE API FOR WDTC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTSetMode */
-/** \brief Set Watchdog Mode Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_WDTSetMode( AT91PS_WDTC pWDTC,
- unsigned int Mode )
-{
- pWDTC->WDTC_WDMR = Mode;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTRestart */
-/** \brief Restart Watchdog */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_WDTRestart( AT91PS_WDTC pWDTC )
-{
- pWDTC->WDTC_WDCR = 0xA5000001;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTSGettatus */
-/** \brief Get Watchdog Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_WDTSGettatus( AT91PS_WDTC pWDTC )
-{
- return( pWDTC->WDTC_WDSR & 0x3 );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTGetPeriod */
-/** \brief Translate ms into Watchdog Compatible value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_WDTGetPeriod( unsigned int ms )
-{
- if( ( ms < 4 ) || ( ms > 16000 ) )
- {
- return 0;
- }
-
- return( ( ms << 8 ) / 1000 );
-}
-
-/* *****************************************************************************
-* SOFTWARE API FOR VREG
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_VREG_Enable_LowPowerMode */
-/** \brief Enable VREG Low Power Mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_VREG_Enable_LowPowerMode( AT91PS_VREG pVREG )
-{
- pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_VREG_Disable_LowPowerMode */
-/** \brief Disable VREG Low Power Mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_VREG_Disable_LowPowerMode( AT91PS_VREG pVREG )
-{
- pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
-} /* *****************************************************************************
- * SOFTWARE API FOR MC
- ***************************************************************************** */
-
-#define AT91C_MC_CORRECT_KEY ( ( unsigned int ) 0x5A << 24 ) /* (MC) Correct Protect Key */
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_Remap */
-/** \brief Make Remap */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_Remap( void ) /* */
-{
- AT91PS_MC pMC = ( AT91PS_MC ) AT91C_BASE_MC;
-
+ AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+
pMC->MC_RCR = AT91C_MC_RCB;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_CfgModeReg */
-/** \brief Configure the EFC Mode Register of the MC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, /* pointer to a MC controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+ AT91PS_MC pMC, // pointer to a MC controller
+ unsigned int mode) // mode register
{
- /* Write to the FMR register */
- pMC->MC_FMR = mode;
+ // Write to the FMR register
+ pMC->MC_FMR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_GetModeReg */
-/** \brief Return MC EFC Mode Regsiter */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+ AT91PS_MC pMC) // pointer to a MC controller
{
- return pMC->MC_FMR;
+ return pMC->MC_FMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_ComputeFMCN */
-/** \brief Return MC EFC Mode Regsiter */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+ int master_clock) // master clock in Hz
{
- return( master_clock / 1000000 + 2 );
+ return (master_clock/1000000 +2);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_PerformCmd */
-/** \brief Perform EFC Command */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_EFC_PerformCmd( AT91PS_MC pMC, /* pointer to a MC controller */
- unsigned int transfer_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+ AT91PS_MC pMC, // pointer to a MC controller
+ unsigned int transfer_cmd)
{
- pMC->MC_FCR = transfer_cmd;
+ pMC->MC_FCR = transfer_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_GetStatus */
-/** \brief Return MC EFC Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_GetStatus( AT91PS_MC pMC ) /* pointer to a MC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+ AT91PS_MC pMC) // pointer to a MC controller
{
- return pMC->MC_FSR;
+ return pMC->MC_FSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_IsInterruptMasked */
-/** \brief Test if EFC MC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( AT91PS_MC pMC, /* \arg pointer to a MC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+ AT91PS_MC pMC, // \arg pointer to a MC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_MC_EFC_GetModeReg( pMC ) & flag );
+ return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_IsInterruptSet */
-/** \brief Test if EFC MC Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, /* \arg pointer to a MC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+ AT91PS_MC pMC, // \arg pointer to a MC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_MC_EFC_GetStatus( pMC ) & flag );
+ return (AT91F_MC_EFC_GetStatus(pMC) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR SPI
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Open */
-/** \brief Open a SPI Port */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_Open( const unsigned int null ) /* \arg */
+ SOFTWARE API FOR SPI
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+ const unsigned int null) // \arg
{
- /* NOT DEFINED AT THIS MOMENT */
- return( 0 );
+ /* NOT DEFINED AT THIS MOMENT */
+ return ( 0 );
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgCs */
-/** \brief Configure SPI chip select register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgCs( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- int cs, /* SPI cs number (0 to 3) */
- int val ) /* chip select register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ int cs, // SPI cs number (0 to 3)
+ int val) // chip select register
{
- /** Write to the CSR register */
- *( pSPI->SPI_CSR + cs ) = val;
+ //* Write to the CSR register
+ *(pSPI->SPI_CSR + cs) = val;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_EnableIt */
-/** \brief Enable SPI interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_EnableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pSPI->SPI_IER = flag;
+ //* Write to the IER register
+ pSPI->SPI_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_DisableIt */
-/** \brief Disable SPI interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_DisableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pSPI->SPI_IDR = flag;
+ //* Write to the IDR register
+ pSPI->SPI_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Reset */
-/** \brief Reset the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Reset( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
- pSPI->SPI_CR = AT91C_SPI_SWRST;
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Enable */
-/** \brief Enable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Enable( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
- pSPI->SPI_CR = AT91C_SPI_SPIEN;
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Disable */
-/** \brief Disable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Disable( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ int mode) // mode register
+{
+ //* Write to the MR register
+ pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ char PCS_Device) // PCS of the Device
+{
+ //* Write to the MR register
+ pSPI->SPI_MR &= 0xFFF0FFFF;
+ pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+ AT91PS_SPI pSPI,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pSPI->SPI_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+ AT91PS_SPI pSPI,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pSPI->SPI_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+ AT91PS_SPI pSPI) // \arg pointer to a SPI controller
+{
+ //* Reset all the Chip Select register
+ pSPI->SPI_CSR[0] = 0 ;
+ pSPI->SPI_CSR[1] = 0 ;
+ pSPI->SPI_CSR[2] = 0 ;
+ pSPI->SPI_CSR[3] = 0 ;
+
+ //* Reset the SPI mode
+ pSPI->SPI_MR = 0 ;
+
+ //* Disable all interrupts
+ pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+ //* Abort the Peripheral Data Transfers
+ AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+ //* Disable receiver and transmitter and stop any activity immediately
pSPI->SPI_CR = AT91C_SPI_SPIDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgMode */
-/** \brief Enable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgMode( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- int mode ) /* mode register */
-{
- /** Write to the MR register */
- pSPI->SPI_MR = mode;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgPCS */
-/** \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgPCS( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- char PCS_Device ) /* PCS of the Device */
-{
- /** Write to the MR register */
- pSPI->SPI_MR &= 0xFFF0FFFF;
- pSPI->SPI_MR |= ( ( PCS_Device << 16 ) & AT91C_SPI_PCS );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_ReceiveFrame( AT91PS_SPI pSPI,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Close */
-/** \brief Close SPI: disable IT disable transfert, close PDC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */
-{
- /** Reset all the Chip Select register */
- pSPI->SPI_CSR[ 0 ] = 0;
- pSPI->SPI_CSR[ 1 ] = 0;
- pSPI->SPI_CSR[ 2 ] = 0;
- pSPI->SPI_CSR[ 3 ] = 0;
-
- /** Reset the SPI mode */
- pSPI->SPI_MR = 0;
-
- /** Disable all interrupts */
- pSPI->SPI_IDR = 0xFFFFFFFF;
-
- /** Abort the Peripheral Data Transfers */
- AT91F_PDC_Close( ( AT91PS_PDC ) &( pSPI->SPI_RPR ) );
-
- /** Disable receiver and transmitter and stop any activity immediately */
- pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_PutChar */
-/** \brief Send a character,does not check if ready to send */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_PutChar( AT91PS_SPI pSPI,
- unsigned int character,
- unsigned int cs_number )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+ AT91PS_SPI pSPI,
+ unsigned int character,
+ unsigned int cs_number )
{
unsigned int value_for_cs;
-
- value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; /*Place a zero among a 4 ONEs number */
- pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 );
+ value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number
+ pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_GetChar */
-/** \brief Receive a character,does not check if a character is available */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SPI_GetChar( const AT91PS_SPI pSPI )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+ const AT91PS_SPI pSPI)
{
- return( ( pSPI->SPI_RDR ) & 0xFFFF );
+ return((pSPI->SPI_RDR) & 0xFFFF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_GetInterruptMaskStatus */
-/** \brief Return SPI Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( /* \return SPI Interrupt Mask Status */
- AT91PS_SPI pSpi ) /* \arg pointer to a SPI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+ AT91PS_SPI pSpi) // \arg pointer to a SPI controller
{
- return pSpi->SPI_IMR;
+ return pSpi->SPI_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_IsInterruptMasked */
-/** \brief Test if SPI Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi, /* \arg pointer to a SPI controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+ AT91PS_SPI pSpi, // \arg pointer to a SPI controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_SPI_GetInterruptMaskStatus( pSpi ) & flag );
+ return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR USART
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Baudrate */
-/** \brief Calculate the baudrate */
-/** Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_ASYNC_MODE \
- ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+ SOFTWARE API FOR USART
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/** Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_ASYNC_SCK_MODE \
- ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_EXT )
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_EXT )
-/** Standard Synchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_SYNC_MODE \
- ( AT91C_US_SYNC + \
- AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+ AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/** SCK used Label */
-#define AT91C_US_SCK_USED ( AT91C_US_CKLO | AT91C_US_CLKS_EXT )
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-/** Standard ISO T=0 Mode : 8 bits , 1 stop , parity */
-#define AT91C_US_ISO_READER_MODE \
- ( AT91C_US_USMODE_ISO7816_0 + \
- AT91C_US_CLKS_CLOCK + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_EVEN + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CKLO + \
- AT91C_US_OVER )
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+ AT91C_US_CLKS_CLOCK +\
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_EVEN + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CKLO +\
+ AT91C_US_OVER)
-/** Standard IRDA mode */
-#define AT91C_US_ASYNC_IRDA_MODE \
- ( AT91C_US_USMODE_IRDA + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Baudrate */
-/** \brief Caluculate baud_value according to the main clock and the baud rate */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_Baudrate( const unsigned int main_clock, /* \arg peripheral clock */
- const unsigned int baud_rate ) /* \arg UART baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+ const unsigned int main_clock, // \arg peripheral clock
+ const unsigned int baud_rate) // \arg UART baudrate
{
- unsigned int baud_value = ( ( main_clock * 10 ) / ( baud_rate * 16 ) );
-
- if( ( baud_value % 10 ) >= 5 )
- {
- baud_value = ( baud_value / 10 ) + 1;
- }
- else
- {
- baud_value /= 10;
- }
-
- return baud_value;
+ unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+ if ((baud_value % 10) >= 5)
+ baud_value = (baud_value / 10) + 1;
+ else
+ baud_value /= 10;
+ return baud_value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetBaudrate */
-/** \brief Set the baudrate according to the CPU clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetBaudrate( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int speed ) /* \arg UART baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int speed) // \arg UART baudrate
{
- /** Define the baud rate divisor register */
- pUSART->US_BRGR = AT91F_US_Baudrate( mainClock, speed );
+ //* Define the baud rate divisor register
+ pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetTimeguard */
-/** \brief Set USART timeguard */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetTimeguard( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int timeguard ) /* \arg timeguard value */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int timeguard) // \arg timeguard value
{
- /** Write the Timeguard Register */
- pUSART->US_TTGR = timeguard;
+ //* Write the Timeguard Register
+ pUSART->US_TTGR = timeguard ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableIt */
-/** \brief Enable USART IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int flag ) /* \arg IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pUSART->US_IER = flag;
+ //* Write to the IER register
+ pUSART->US_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableIt */
-/** \brief Disable USART IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IER register */
- pUSART->US_IDR = flag;
+ //* Write to the IER register
+ pUSART->US_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Configure */
-/** \brief Configure USART */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_Configure( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int mode, /* \arg mode Register to be programmed */
- unsigned int baudRate, /* \arg baudrate to be programmed */
- unsigned int timeguard ) /* \arg timeguard to be programmed */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int mode , // \arg mode Register to be programmed
+ unsigned int baudRate , // \arg baudrate to be programmed
+ unsigned int timeguard ) // \arg timeguard to be programmed
{
- /** Disable interrupts */
- pUSART->US_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pUSART->US_IDR = (unsigned int) -1;
- /** Reset receiver and transmitter */
- pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
+ //* Reset receiver and transmitter
+ pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
- /** Define the baud rate divisor register */
- AT91F_US_SetBaudrate( pUSART, mainClock, baudRate );
+ //* Define the baud rate divisor register
+ AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
- /** Write the Timeguard Register */
- AT91F_US_SetTimeguard( pUSART, timeguard );
+ //* Write the Timeguard Register
+ AT91F_US_SetTimeguard(pUSART, timeguard);
- /** Clear Transmit and Receive Counters */
- AT91F_PDC_Open( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
+ //* Clear Transmit and Receive Counters
+ AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
- /** Define the USART mode */
- pUSART->US_MR = mode;
+ //* Define the USART mode
+ pUSART->US_MR = mode ;
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableRx */
-/** \brief Enable receiving characters */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Enable receiver */
+ //* Enable receiver
pUSART->US_CR = AT91C_US_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableTx */
-/** \brief Enable sending characters */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Enable transmitter */
+ //* Enable transmitter
pUSART->US_CR = AT91C_US_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ResetRx */
-/** \brief Reset Receiver and re-enable it */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_ResetRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset receiver */
- pUSART->US_CR = AT91C_US_RSTRX;
- /** Re-Enable receiver */
+ //* Reset receiver
+ pUSART->US_CR = AT91C_US_RSTRX;
+ //* Re-Enable receiver
pUSART->US_CR = AT91C_US_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ResetTx */
-/** \brief Reset Transmitter and re-enable it */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_ResetTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset transmitter */
- pUSART->US_CR = AT91C_US_RSTTX;
- /** Enable transmitter */
+ //* Reset transmitter
+ pUSART->US_CR = AT91C_US_RSTTX;
+ //* Enable transmitter
pUSART->US_CR = AT91C_US_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableRx */
-/** \brief Disable Receiver */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Disable receiver */
+ //* Disable receiver
pUSART->US_CR = AT91C_US_RXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableTx */
-/** \brief Disable Transmitter */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Disable transmitter */
+ //* Disable transmitter
pUSART->US_CR = AT91C_US_TXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Close */
-/** \brief Close USART: disable IT disable receiver and transmitter, close PDC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_Close( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset the baud rate divisor register */
- pUSART->US_BRGR = 0;
+ //* Reset the baud rate divisor register
+ pUSART->US_BRGR = 0 ;
- /** Reset the USART mode */
- pUSART->US_MR = 0;
+ //* Reset the USART mode
+ pUSART->US_MR = 0 ;
- /** Reset the Timeguard Register */
+ //* Reset the Timeguard Register
pUSART->US_TTGR = 0;
- /** Disable all interrupts */
- pUSART->US_IDR = 0xFFFFFFFF;
+ //* Disable all interrupts
+ pUSART->US_IDR = 0xFFFFFFFF ;
- /** Abort the Peripheral Data Transfers */
- AT91F_PDC_Close( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
+ //* Abort the Peripheral Data Transfers
+ AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
- /** Disable receiver and transmitter and stop any activity immediately */
- pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
+ //* Disable receiver and transmitter and stop any activity immediately
+ pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_TxReady */
-/** \brief Return 1 if a character can be written in US_THR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_TxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR & AT91C_US_TXRDY );
+ return (pUSART->US_CSR & AT91C_US_TXRDY);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_RxReady */
-/** \brief Return 1 if a character can be read in US_RHR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_RxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR & AT91C_US_RXRDY );
+ return (pUSART->US_CSR & AT91C_US_RXRDY);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Error */
-/** \brief Return the error flag */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_Error( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR &
- ( AT91C_US_OVRE | /* Overrun error */
- AT91C_US_FRAME | /* Framing error */
- AT91C_US_PARE ) ); /* Parity error */
+ return (pUSART->US_CSR &
+ (AT91C_US_OVRE | // Overrun error
+ AT91C_US_FRAME | // Framing error
+ AT91C_US_PARE)); // Parity error
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_PutChar */
-/** \brief Send a character,does not check if ready to send */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_PutChar( AT91PS_USART pUSART,
- int character )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+ AT91PS_USART pUSART,
+ int character )
{
- pUSART->US_THR = ( character & 0x1FF );
+ pUSART->US_THR = (character & 0x1FF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_GetChar */
-/** \brief Receive a character,does not check if a character is available */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_US_GetChar( const AT91PS_USART pUSART )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+ const AT91PS_USART pUSART)
{
- return( ( pUSART->US_RHR ) & 0x1FF );
+ return((pUSART->US_RHR) & 0x1FF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_SendFrame( AT91PS_USART pUSART,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+ AT91PS_USART pUSART,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pUSART->US_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pUSART->US_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_ReceiveFrame( AT91PS_USART pUSART,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+ AT91PS_USART pUSART,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pUSART->US_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pUSART->US_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetIrdaFilter */
-/** \brief Set the value of IrDa filter tregister */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetIrdaFilter( AT91PS_USART pUSART,
- unsigned char value )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+ AT91PS_USART pUSART,
+ unsigned char value
+)
{
- pUSART->US_IF = value;
+ pUSART->US_IF = value;
}
/* *****************************************************************************
-* SOFTWARE API FOR SSC
-***************************************************************************** */
-/** Define the standard I2S mode configuration */
+ SOFTWARE API FOR SSC
+ ***************************************************************************** */
+//* Define the standard I2S mode configuration
-/** Configuration to set in the SSC Transmit Clock Mode Register */
-/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
-/** nb_slot_by_frame : number of channels */
-#define AT91C_I2S_ASY_MASTER_TX_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
- ( + \
- AT91C_SSC_CKS_DIV + \
- AT91C_SSC_CKO_CONTINOUS + \
- AT91C_SSC_CKG_NONE + \
- AT91C_SSC_START_FALL_RF + \
- AT91C_SSC_STTOUT + \
- ( ( 1 << 16 ) & AT91C_SSC_STTDLY ) + \
- ( ( ( ( nb_bit_by_slot * nb_slot_by_frame ) / 2 ) - 1 ) << 24 ) )
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ AT91C_SSC_CKS_DIV +\
+ AT91C_SSC_CKO_CONTINOUS +\
+ AT91C_SSC_CKG_NONE +\
+ AT91C_SSC_START_FALL_RF +\
+ AT91C_SSC_STTOUT +\
+ ((1<<16) & AT91C_SSC_STTDLY) +\
+ ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
-/** Configuration to set in the SSC Transmit Frame Mode Register */
-/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
-/** nb_slot_by_frame : number of channels */
-#define AT91C_I2S_ASY_TX_FRAME_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
- ( + \
- ( nb_bit_by_slot - 1 ) + \
- AT91C_SSC_MSBF + \
- ( ( ( nb_slot_by_frame - 1 ) << 8 ) & AT91C_SSC_DATNB ) + \
- ( ( ( nb_bit_by_slot - 1 ) << 16 ) & AT91C_SSC_FSLEN ) + \
- AT91C_SSC_FSOS_NEGATIVE )
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ (nb_bit_by_slot-1) +\
+ AT91C_SSC_MSBF +\
+ (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
+ (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+ AT91C_SSC_FSOS_NEGATIVE)
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_SetBaudrate */
-/** \brief Set the baudrate according to the CPU clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_SetBaudrate( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int speed ) /* \arg SSC baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int speed) // \arg SSC baudrate
{
- unsigned int baud_value;
-
- /** Define the baud rate divisor register */
- if( speed == 0 )
- {
- baud_value = 0;
- }
- else
- {
- baud_value = ( unsigned int ) ( mainClock * 10 ) / ( 2 * speed );
-
- if( ( baud_value % 10 ) >= 5 )
- {
- baud_value = ( baud_value / 10 ) + 1;
- }
+ unsigned int baud_value;
+ //* Define the baud rate divisor register
+ if (speed == 0)
+ baud_value = 0;
else
{
- baud_value /= 10;
+ baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+ if ((baud_value % 10) >= 5)
+ baud_value = (baud_value / 10) + 1;
+ else
+ baud_value /= 10;
}
- }
- pSSC->SSC_CMR = baud_value;
+ pSSC->SSC_CMR = baud_value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_Configure */
-/** \brief Configure SSC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_Configure( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int syst_clock, /* \arg System Clock Frequency */
- unsigned int baud_rate, /* \arg Expected Baud Rate Frequency */
- unsigned int clock_rx, /* \arg Receiver Clock Parameters */
- unsigned int mode_rx, /* \arg mode Register to be programmed */
- unsigned int clock_tx, /* \arg Transmitter Clock Parameters */
- unsigned int mode_tx ) /* \arg mode Register to be programmed */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int syst_clock, // \arg System Clock Frequency
+ unsigned int baud_rate, // \arg Expected Baud Rate Frequency
+ unsigned int clock_rx, // \arg Receiver Clock Parameters
+ unsigned int mode_rx, // \arg mode Register to be programmed
+ unsigned int clock_tx, // \arg Transmitter Clock Parameters
+ unsigned int mode_tx) // \arg mode Register to be programmed
{
- /** Disable interrupts */
- pSSC->SSC_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pSSC->SSC_IDR = (unsigned int) -1;
- /** Reset receiver and transmitter */
- pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS;
+ //* Reset receiver and transmitter
+ pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
- /** Define the Clock Mode Register */
- AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate );
+ //* Define the Clock Mode Register
+ AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
- /** Write the Receive Clock Mode Register */
- pSSC->SSC_RCMR = clock_rx;
+ //* Write the Receive Clock Mode Register
+ pSSC->SSC_RCMR = clock_rx;
- /** Write the Transmit Clock Mode Register */
- pSSC->SSC_TCMR = clock_tx;
+ //* Write the Transmit Clock Mode Register
+ pSSC->SSC_TCMR = clock_tx;
- /** Write the Receive Frame Mode Register */
- pSSC->SSC_RFMR = mode_rx;
+ //* Write the Receive Frame Mode Register
+ pSSC->SSC_RFMR = mode_rx;
- /** Write the Transmit Frame Mode Register */
- pSSC->SSC_TFMR = mode_tx;
+ //* Write the Transmit Frame Mode Register
+ pSSC->SSC_TFMR = mode_tx;
- /** Clear Transmit and Receive Counters */
- AT91F_PDC_Open( ( AT91PS_PDC ) &( pSSC->SSC_RPR ) );
+ //* Clear Transmit and Receive Counters
+ AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableRx */
-/** \brief Enable receiving datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Enable receiver */
+ //* Enable receiver
pSSC->SSC_CR = AT91C_SSC_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableRx */
-/** \brief Disable receiving datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Disable receiver */
+ //* Disable receiver
pSSC->SSC_CR = AT91C_SSC_RXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableTx */
-/** \brief Enable sending datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Enable transmitter */
+ //* Enable transmitter
pSSC->SSC_CR = AT91C_SSC_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableTx */
-/** \brief Disable sending datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Disable transmitter */
+ //* Disable transmitter
pSSC->SSC_CR = AT91C_SSC_TXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableIt */
-/** \brief Enable SSC IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pSSC->SSC_IER = flag;
+ //* Write to the IER register
+ pSSC->SSC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableIt */
-/** \brief Disable SSC IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pSSC->SSC_IDR = flag;
+ //* Write to the IDR register
+ pSSC->SSC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_ReceiveFrame( AT91PS_SSC pSSC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+ AT91PS_SSC pSSC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pSSC->SSC_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_SendFrame( AT91PS_SSC pSSC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+ AT91PS_SSC pSSC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pSSC->SSC_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_GetInterruptMaskStatus */
-/** \brief Return SSC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( /* \return SSC Interrupt Mask Status */
- AT91PS_SSC pSsc ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+ AT91PS_SSC pSsc) // \arg pointer to a SSC controller
{
- return pSsc->SSC_IMR;
+ return pSsc->SSC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_IsInterruptMasked */
-/** \brief Test if SSC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+ AT91PS_SSC pSsc, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_SSC_GetInterruptMaskStatus( pSsc ) & flag );
+ return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR TWI
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_EnableIt */
-/** \brief Enable TWI IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_EnableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg IT to be enabled */
+ SOFTWARE API FOR TWI
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pTWI->TWI_IER = flag;
+ //* Write to the IER register
+ pTWI->TWI_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_DisableIt */
-/** \brief Disable TWI IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_DisableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pTWI->TWI_IDR = flag;
+ //* Write to the IDR register
+ pTWI->TWI_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_Configure */
-/** \brief Configure TWI in master mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_Configure( AT91PS_TWI pTWI ) /* \arg pointer to a TWI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller
{
- /** Disable interrupts */
- pTWI->TWI_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pTWI->TWI_IDR = (unsigned int) -1;
- /** Reset peripheral */
- pTWI->TWI_CR = AT91C_TWI_SWRST;
+ //* Reset peripheral
+ pTWI->TWI_CR = AT91C_TWI_SWRST;
- /** Set Master mode */
- pTWI->TWI_CR = AT91C_TWI_MSEN;
+ //* Set Master mode
+ pTWI->TWI_CR = AT91C_TWI_MSEN;
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_GetInterruptMaskStatus */
-/** \brief Return TWI Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( /* \return TWI Interrupt Mask Status */
- AT91PS_TWI pTwi ) /* \arg pointer to a TWI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+ AT91PS_TWI pTwi) // \arg pointer to a TWI controller
{
- return pTwi->TWI_IMR;
+ return pTwi->TWI_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_IsInterruptMasked */
-/** \brief Test if TWI Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+ AT91PS_TWI pTwi, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_TWI_GetInterruptMaskStatus( pTwi ) & flag );
+ return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR PWMC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_GetStatus */
-/** \brief Return PWM Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_GetStatus( /* \return PWM Interrupt Status */
- AT91PS_PWMC pPWM ) /* pointer to a PWM controller */
+ SOFTWARE API FOR PWMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+ AT91PS_PWMC pPWM) // pointer to a PWM controller
{
- return pPWM->PWMC_SR;
+ return pPWM->PWMC_SR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_InterruptEnable */
-/** \brief Enable PWM Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_InterruptEnable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg PWM interrupt to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg PWM interrupt to be enabled
{
- pPwm->PWMC_IER = flag;
+ pPwm->PWMC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_InterruptDisable */
-/** \brief Disable PWM Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_InterruptDisable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg PWM interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg PWM interrupt to be disabled
{
- pPwm->PWMC_IDR = flag;
+ pPwm->PWMC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_GetInterruptMaskStatus */
-/** \brief Return PWM Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( /* \return PWM Interrupt Mask Status */
- AT91PS_PWMC pPwm ) /* \arg pointer to a PWM controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+ AT91PS_PWMC pPwm) // \arg pointer to a PWM controller
{
- return pPwm->PWMC_IMR;
+ return pPwm->PWMC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_IsInterruptMasked */
-/** \brief Test if PWM Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_IsInterruptMasked( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PWMC_GetInterruptMaskStatus( pPWM ) & flag );
+ return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_IsStatusSet */
-/** \brief Test if PWM Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_IsStatusSet( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PWMC_GetStatus( pPWM ) & flag );
+ return (AT91F_PWMC_GetStatus(pPWM) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_CfgChannel */
-/** \brief Test if PWM Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int channelId, /* \arg PWM channel ID */
- unsigned int mode, /* \arg PWM mode */
- unsigned int period, /* \arg PWM period */
- unsigned int duty ) /* \arg PWM duty cycle */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int channelId, // \arg PWM channel ID
+ unsigned int mode, // \arg PWM mode
+ unsigned int period, // \arg PWM period
+ unsigned int duty) // \arg PWM duty cycle
{
- pPWM->PWMC_CH[ channelId ].PWMC_CMR = mode;
- pPWM->PWMC_CH[ channelId ].PWMC_CDTYR = duty;
- pPWM->PWMC_CH[ channelId ].PWMC_CPRDR = period;
+ pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+ pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+ pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_StartChannel */
-/** \brief Enable channel */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_ENA = flag;
+ pPWM->PWMC_ENA = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_StopChannel */
-/** \brief Disable channel */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_DIS = flag;
+ pPWM->PWMC_DIS = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_UpdateChannel */
-/** \brief Update Period or Duty Cycle */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int channelId, /* \arg PWM channel ID */
- unsigned int update ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int channelId, // \arg PWM channel ID
+ unsigned int update) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_CH[ channelId ].PWMC_CUPDR = update;
+ pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
}
/* *****************************************************************************
-* SOFTWARE API FOR UDP
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EnableIt */
-/** \brief Enable UDP IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EnableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg IT to be enabled */
+ SOFTWARE API FOR UDP
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pUDP->UDP_IER = flag;
+ //* Write to the IER register
+ pUDP->UDP_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_DisableIt */
-/** \brief Disable UDP IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_DisableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pUDP->UDP_IDR = flag;
+ //* Write to the IDR register
+ pUDP->UDP_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_SetAddress */
-/** \brief Set UDP functional address */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_SetAddress( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char address ) /* \arg new UDP address */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char address) // \arg new UDP address
{
- pUDP->UDP_FADDR = ( AT91C_UDP_FEN | address );
+ pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EnableEp */
-/** \brief Enable Endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EnableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_EPEDS;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_DisableEp */
-/** \brief Enable Endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_DisableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] &= ~AT91C_UDP_EPEDS;
+ pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_SetState */
-/** \brief Set UDP Device state */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_SetState( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg new UDP address */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg new UDP address
{
- pUDP->UDP_GLBSTATE &= ~( AT91C_UDP_FADDEN | AT91C_UDP_CONFG );
- pUDP->UDP_GLBSTATE |= flag;
+ pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+ pUDP->UDP_GLBSTATE |= flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_GetState */
-/** \brief return UDP Device state */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_GetState( /* \return the UDP device state */
- AT91PS_UDP pUDP ) /* \arg pointer to a UDP controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+ AT91PS_UDP pUDP) // \arg pointer to a UDP controller
{
- return( pUDP->UDP_GLBSTATE & ( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ) );
+ return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_ResetEp */
-/** \brief Reset UDP endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_ResetEp( /* \return the UDP device state */
- AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg Endpoints to be reset */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg Endpoints to be reset
{
- pUDP->UDP_RSTEP = flag;
- pUDP->UDP_RSTEP = 0;
+ pUDP->UDP_RSTEP = flag;
+ pUDP->UDP_RSTEP = 0;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpStall */
-/** \brief Endpoint will STALL requests */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpStall( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_FORCESTALL;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpWrite */
-/** \brief Write value in the DPR */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpWrite( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned char value ) /* \arg value to be written in the DPR */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned char value) // \arg value to be written in the DPR
{
- pUDP->UDP_FDR[ endpoint ] = value;
+ pUDP->UDP_FDR[endpoint] = value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpRead */
-/** \brief Return value from the DPR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_EpRead( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- return pUDP->UDP_FDR[ endpoint ];
+ return pUDP->UDP_FDR[endpoint];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpEndOfWr */
-/** \brief Notify the UDP that values in DPR are ready to be sent */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpEndOfWr( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_TXPKTRDY;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpClear */
-/** \brief Clear flag in the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpClear( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned int flag ) /* \arg flag to be cleared */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned int flag) // \arg flag to be cleared
{
- pUDP->UDP_CSR[ endpoint ] &= ~( flag );
+ pUDP->UDP_CSR[endpoint] &= ~(flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpSet */
-/** \brief Set flag in the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpSet( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned int flag ) /* \arg flag to be cleared */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned int flag) // \arg flag to be cleared
{
- pUDP->UDP_CSR[ endpoint ] |= flag;
+ pUDP->UDP_CSR[endpoint] |= flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpStatus */
-/** \brief Return the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_EpStatus( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- return pUDP->UDP_CSR[ endpoint ];
+ return pUDP->UDP_CSR[endpoint];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_GetInterruptMaskStatus */
-/** \brief Return UDP Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( /* \return UDP Interrupt Mask Status */
- AT91PS_UDP pUdp ) /* \arg pointer to a UDP controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+ AT91PS_UDP pUdp) // \arg pointer to a UDP controller
{
- return pUdp->UDP_IMR;
+ return pUdp->UDP_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_IsInterruptMasked */
-/** \brief Test if UDP Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+ AT91PS_UDP pUdp, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_UDP_GetInterruptMaskStatus( pUdp ) & flag );
+ return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR TC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_InterruptEnable */
-/** \brief Enable TC Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC_InterruptEnable( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg TC interrupt to be enabled */
+ SOFTWARE API FOR TC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg TC interrupt to be enabled
{
- pTc->TC_IER = flag;
+ pTc->TC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_InterruptDisable */
-/** \brief Disable TC Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC_InterruptDisable( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg TC interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg TC interrupt to be disabled
{
- pTc->TC_IDR = flag;
+ pTc->TC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_GetInterruptMaskStatus */
-/** \brief Return TC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TC_GetInterruptMaskStatus( /* \return TC Interrupt Mask Status */
- AT91PS_TC pTc ) /* \arg pointer to a TC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+ AT91PS_TC pTc) // \arg pointer to a TC controller
{
- return pTc->TC_IMR;
+ return pTc->TC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_IsInterruptMasked */
-/** \brief Test if TC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_TC_IsInterruptMasked( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_TC_GetInterruptMaskStatus( pTc ) & flag );
+ return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR CAN
-***************************************************************************** */
-#define STANDARD_FORMAT 0
-#define EXTENDED_FORMAT 1
+ SOFTWARE API FOR CAN
+ ***************************************************************************** */
+#define STANDARD_FORMAT 0
+#define EXTENDED_FORMAT 1
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_InitMailboxRegisters() */
-/** \brief Configure the corresponding mailbox */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_InitMailboxRegisters( AT91PS_CAN_MB CAN_Mailbox,
- int mode_reg,
- int acceptance_mask_reg,
- int id_reg,
- int data_low_reg,
- int data_high_reg,
- int control_reg )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_InitMailboxRegisters()
+//* \brief Configure the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox,
+ int mode_reg,
+ int acceptance_mask_reg,
+ int id_reg,
+ int data_low_reg,
+ int data_high_reg,
+ int control_reg)
{
- CAN_Mailbox->CAN_MB_MCR = 0x0;
- CAN_Mailbox->CAN_MB_MMR = mode_reg;
- CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;
- CAN_Mailbox->CAN_MB_MID = id_reg;
- CAN_Mailbox->CAN_MB_MDL = data_low_reg;
- CAN_Mailbox->CAN_MB_MDH = data_high_reg;
- CAN_Mailbox->CAN_MB_MCR = control_reg;
+ CAN_Mailbox->CAN_MB_MCR = 0x0;
+ CAN_Mailbox->CAN_MB_MMR = mode_reg;
+ CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;
+ CAN_Mailbox->CAN_MB_MID = id_reg;
+ CAN_Mailbox->CAN_MB_MDL = data_low_reg;
+ CAN_Mailbox->CAN_MB_MDH = data_high_reg;
+ CAN_Mailbox->CAN_MB_MCR = control_reg;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_EnableCAN() */
-/** \brief */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_EnableCAN( AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_EnableCAN()
+//* \brief
+//*----------------------------------------------------------------------------
+__inline void AT91F_EnableCAN(
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- pCAN->CAN_MR |= AT91C_CAN_CANEN;
+ pCAN->CAN_MR |= AT91C_CAN_CANEN;
- /* Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver */
- while( ( pCAN->CAN_SR & AT91C_CAN_WAKEUP ) != AT91C_CAN_WAKEUP )
- {
- }
+ // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
+ while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DisableCAN() */
-/** \brief */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DisableCAN( AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DisableCAN()
+//* \brief
+//*----------------------------------------------------------------------------
+__inline void AT91F_DisableCAN(
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
+ pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_EnableIt */
-/** \brief Enable CAN interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_EnableIt( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_EnableIt
+//* \brief Enable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_EnableIt (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pCAN->CAN_IER = flag;
+ //* Write to the IER register
+ pCAN->CAN_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_DisableIt */
-/** \brief Disable CAN interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_DisableIt( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_DisableIt
+//* \brief Disable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_DisableIt (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pCAN->CAN_IDR = flag;
+ //* Write to the IDR register
+ pCAN->CAN_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetStatus */
-/** \brief Return CAN Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetStatus( /* \return CAN Interrupt Status */
- AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetStatus
+//* \brief Return CAN Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- return pCAN->CAN_SR;
+ return pCAN->CAN_SR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetInterruptMaskStatus */
-/** \brief Return CAN Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( /* \return CAN Interrupt Mask Status */
- AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetInterruptMaskStatus
+//* \brief Return CAN Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- return pCAN->CAN_IMR;
+ return pCAN->CAN_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_IsInterruptMasked */
-/** \brief Test if CAN Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_IsInterruptMasked( AT91PS_CAN pCAN, /* \arg pointer to a CAN controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_IsInterruptMasked
+//* \brief Test if CAN Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsInterruptMasked(
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_CAN_GetInterruptMaskStatus( pCAN ) & flag );
+ return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_IsStatusSet */
-/** \brief Test if CAN Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_IsStatusSet( AT91PS_CAN pCAN, /* \arg pointer to a CAN controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_IsStatusSet
+//* \brief Test if CAN Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsStatusSet(
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_CAN_GetStatus( pCAN ) & flag );
+ return (AT91F_CAN_GetStatus(pCAN) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgModeReg */
-/** \brief Configure the Mode Register of the CAN controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgModeReg( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgModeReg
+//* \brief Configure the Mode Register of the CAN controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgModeReg (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int mode) // mode register
{
- /** Write to the MR register */
- pCAN->CAN_MR = mode;
+ //* Write to the MR register
+ pCAN->CAN_MR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetModeReg */
-/** \brief Return the Mode Register of the CAN controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetModeReg( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetModeReg
+//* \brief Return the Mode Register of the CAN controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetModeReg (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_MR;
+ return pCAN->CAN_MR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgBaudrateReg */
-/** \brief Configure the Baudrate of the CAN controller for the network */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgBaudrateReg( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int baudrate_cfg )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgBaudrateReg
+//* \brief Configure the Baudrate of the CAN controller for the network
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgBaudrateReg (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int baudrate_cfg)
{
- /** Write to the BR register */
- pCAN->CAN_BR = baudrate_cfg;
+ //* Write to the BR register
+ pCAN->CAN_BR = baudrate_cfg;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetBaudrate */
-/** \brief Return the Baudrate of the CAN controller for the network value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetBaudrate( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetBaudrate
+//* \brief Return the Baudrate of the CAN controller for the network value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetBaudrate (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_BR;
+ return pCAN->CAN_BR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetInternalCounter */
-/** \brief Return CAN Timer Regsiter Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetInternalCounter( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetInternalCounter
+//* \brief Return CAN Timer Regsiter Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInternalCounter (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_TIM;
+ return pCAN->CAN_TIM;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetTimestamp */
-/** \brief Return CAN Timestamp Register Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetTimestamp( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetTimestamp
+//* \brief Return CAN Timestamp Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetTimestamp (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_TIMESTP;
+ return pCAN->CAN_TIMESTP;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetErrorCounter */
-/** \brief Return CAN Error Counter Register Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetErrorCounter( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetErrorCounter
+//* \brief Return CAN Error Counter Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetErrorCounter (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_ECR;
+ return pCAN->CAN_ECR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_InitTransferRequest */
-/** \brief Request for a transfer on the corresponding mailboxes */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_InitTransferRequest( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int transfer_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_InitTransferRequest
+//* \brief Request for a transfer on the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitTransferRequest (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int transfer_cmd)
{
- pCAN->CAN_TCR = transfer_cmd;
+ pCAN->CAN_TCR = transfer_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_InitAbortRequest */
-/** \brief Abort the corresponding mailboxes */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_InitAbortRequest( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int abort_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_InitAbortRequest
+//* \brief Abort the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitAbortRequest (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int abort_cmd)
{
- pCAN->CAN_ACR = abort_cmd;
+ pCAN->CAN_ACR = abort_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageModeReg */
-/** \brief Program the Message Mode Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageModeReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageModeReg
+//* \brief Program the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageModeReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int mode)
{
- CAN_Mailbox->CAN_MB_MMR = mode;
+ CAN_Mailbox->CAN_MB_MMR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageModeReg */
-/** \brief Return the Message Mode Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageModeReg( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageModeReg
+//* \brief Return the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageModeReg (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MMR;
+ return CAN_Mailbox->CAN_MB_MMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageIDReg */
-/** \brief Program the Message ID Register */
-/** \brief Version == 0 for Standard messsage, Version == 1 for Extended */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageIDReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int id,
- unsigned char version )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageIDReg
+//* \brief Program the Message ID Register
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageIDReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int id,
+ unsigned char version)
{
- if( version == 0 ) /* IDvA Standard Format */
- {
- CAN_Mailbox->CAN_MB_MID = id << 18;
- }
- else /* IDvB Extended Format */
- {
- CAN_Mailbox->CAN_MB_MID = id | ( 1 << 29 ); /* set MIDE bit */
- }
+ if(version==0) // IDvA Standard Format
+ CAN_Mailbox->CAN_MB_MID = id<<18;
+ else // IDvB Extended Format
+ CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageIDReg */
-/** \brief Return the Message ID Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageIDReg( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageIDReg
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageIDReg (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MID;
+ return CAN_Mailbox->CAN_MB_MID;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageAcceptanceMaskReg */
-/** \brief Program the Message Acceptance Mask Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int mask )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg
+//* \brief Program the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int mask)
{
- CAN_Mailbox->CAN_MB_MAM = mask;
+ CAN_Mailbox->CAN_MB_MAM = mask;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageAcceptanceMaskReg */
-/** \brief Return the Message Acceptance Mask Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg
+//* \brief Return the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MAM;
+ return CAN_Mailbox->CAN_MB_MAM;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetFamilyID */
-/** \brief Return the Message ID Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetFamilyID( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetFamilyID
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetFamilyID (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MFID;
+ return CAN_Mailbox->CAN_MB_MFID;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageCtrl */
-/** \brief Request and config for a transfer on the corresponding mailbox */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageCtrlReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int message_ctrl_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageCtrl
+//* \brief Request and config for a transfer on the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageCtrlReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int message_ctrl_cmd)
{
- CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;
+ CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageStatus */
-/** \brief Return CAN Mailbox Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageStatus( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageStatus
+//* \brief Return CAN Mailbox Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageStatus (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MSR;
+ return CAN_Mailbox->CAN_MB_MSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageDataLow */
-/** \brief Program data low value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageDataLow( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int data )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageDataLow
+//* \brief Program data low value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataLow (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int data)
{
- CAN_Mailbox->CAN_MB_MDL = data;
+ CAN_Mailbox->CAN_MB_MDL = data;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageDataLow */
-/** \brief Return data low value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageDataLow( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageDataLow
+//* \brief Return data low value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataLow (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MDL;
+ return CAN_Mailbox->CAN_MB_MDL;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageDataHigh */
-/** \brief Program data high value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageDataHigh( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int data )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageDataHigh
+//* \brief Program data high value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataHigh (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int data)
{
- CAN_Mailbox->CAN_MB_MDH = data;
+ CAN_Mailbox->CAN_MB_MDH = data;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageDataHigh */
-/** \brief Return data high value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageDataHigh( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageDataHigh
+//* \brief Return data high value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MDH;
+ return CAN_Mailbox->CAN_MB_MDH;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_Open */
-/** \brief Open a CAN Port */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_Open( const unsigned int null ) /* \arg */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_Open
+//* \brief Open a CAN Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_Open (
+ const unsigned int null) // \arg
{
- /* NOT DEFINED AT THIS MOMENT */
- return( 0 );
+ /* NOT DEFINED AT THIS MOMENT */
+ return ( 0 );
+}
+/* *****************************************************************************
+ SOFTWARE API FOR ADC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int flag) // IT to be enabled
+{
+ //* Write to the IER register
+ pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int flag) // IT to be disabled
+{
+ //* Write to the IDR register
+ pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+ AT91PS_ADC pADC) // pointer to a ADC controller
+{
+ return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+ AT91PS_ADC pADC) // pointer to a ADC controller
+{
+ return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int mode) // mode register
+{
+ //* Write to the MR register
+ pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_MR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int mck_clock, // in MHz
+ unsigned int adc_clock, // in MHz
+ unsigned int startup_time, // in us
+ unsigned int sample_and_hold_time) // in ns
+{
+ unsigned int prescal,startup,shtim;
+
+ prescal = mck_clock/(2*adc_clock) - 1;
+ startup = adc_clock*startup_time/8 - 1;
+ shtim = adc_clock*sample_and_hold_time/1000 - 1;
+
+ //* Write to the MR register
+ pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int channel) // mode register
+{
+ //* Write to the CHER register
+ pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int channel) // mode register
+{
+ //* Write to the CHDR register
+ pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CHSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ pADC->ADC_CR = AT91C_ADC_START;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ pADC->ADC_CR = AT91C_ADC_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_LCDR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR1;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR2;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR3;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR5;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR6;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR7;
}
/* *****************************************************************************
-* SOFTWARE API FOR ADC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_EnableIt */
-/** \brief Enable ADC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_EnableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int flag ) /* IT to be enabled */
+ SOFTWARE API FOR AES
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_EnableIt
+//* \brief Enable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_EnableIt (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pADC->ADC_IER = flag;
+ //* Write to the IER register
+ pAES->AES_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_DisableIt */
-/** \brief Disable ADC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_DisableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_DisableIt
+//* \brief Disable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_DisableIt (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pADC->ADC_IDR = flag;
+ //* Write to the IDR register
+ pAES->AES_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetStatus */
-/** \brief Return ADC Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetStatus( /* \return ADC Interrupt Status */
- AT91PS_ADC pADC ) /* pointer to a ADC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetStatus
+//* \brief Return AES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
+ AT91PS_AES pAES) // pointer to a AES controller
{
- return pADC->ADC_SR;
+ return pAES->AES_ISR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetInterruptMaskStatus */
-/** \brief Return ADC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( /* \return ADC Interrupt Mask Status */
- AT91PS_ADC pADC ) /* pointer to a ADC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetInterruptMaskStatus
+//* \brief Return AES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
+ AT91PS_AES pAES) // pointer to a AES controller
{
- return pADC->ADC_IMR;
+ return pAES->AES_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_IsInterruptMasked */
-/** \brief Test if ADC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_IsInterruptMasked( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_IsInterruptMasked
+//* \brief Test if AES Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsInterruptMasked(
+ AT91PS_AES pAES, // \arg pointer to a AES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_ADC_GetInterruptMaskStatus( pADC ) & flag );
+ return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_IsStatusSet */
-/** \brief Test if ADC Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_IsStatusSet( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_IsStatusSet
+//* \brief Test if AES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsStatusSet(
+ AT91PS_AES pAES, // \arg pointer to a AES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_ADC_GetStatus( pADC ) & flag );
+ return (AT91F_AES_GetStatus(pAES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgModeReg */
-/** \brief Configure the Mode Register of the ADC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgModeReg( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_CfgModeReg
+//* \brief Configure the Mode Register of the AES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgModeReg (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned int mode) // mode register
{
- /** Write to the MR register */
- pADC->ADC_MR = mode;
+ //* Write to the MR register
+ pAES->AES_MR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetModeReg */
-/** \brief Return the Mode Register of the ADC controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetModeReg( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetModeReg
+//* \brief Return the Mode Register of the AES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetModeReg (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- return pADC->ADC_MR;
+ return pAES->AES_MR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgTimings */
-/** \brief Configure the different necessary timings of the ADC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgTimings( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int mck_clock, /* in MHz */
- unsigned int adc_clock, /* in MHz */
- unsigned int startup_time, /* in us */
- unsigned int sample_and_hold_time ) /* in ns */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_StartProcessing (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- unsigned int prescal, startup, shtim;
-
- prescal = mck_clock / ( 2 * adc_clock ) - 1;
- startup = adc_clock * startup_time / 8 - 1;
- shtim = adc_clock * sample_and_hold_time / 1000 - 1;
-
- /** Write to the MR register */
- pADC->ADC_MR = ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) & AT91C_ADC_SHTIM );
+ pAES->AES_CR = AT91C_AES_START;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_EnableChannel */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_EnableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int channel ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_SoftReset
+//* \brief Reset AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SoftReset (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- /** Write to the CHER register */
- pADC->ADC_CHER = channel;
+ pAES->AES_CR = AT91C_AES_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_DisableChannel */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_DisableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int channel ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_LoadNewSeed
+//* \brief Load New Seed in the random number generator
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_LoadNewSeed (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- /** Write to the CHDR register */
- pADC->ADC_CHDR = channel;
+ pAES->AES_CR = AT91C_AES_LOADSEED;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetChannelStatus */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetChannelStatus( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_SetCryptoKey
+//* \brief Set Cryptographic Key x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetCryptoKey (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- return pADC->ADC_CHSR;
+ pAES->AES_KEYWxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_StartConversion */
-/** \brief Software request for a analog to digital conversion */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_StartConversion( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_InputData (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index,
+ unsigned int indata
+ )
{
- pADC->ADC_CR = AT91C_ADC_START;
+ pAES->AES_IDATAxR[index] = indata;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_SoftReset */
-/** \brief Software reset */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_SoftReset( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetOutputData (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index
+ )
{
- pADC->ADC_CR = AT91C_ADC_SWRST;
+ return pAES->AES_ODATAxR[index];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetLastConvertedData */
-/** \brief Return the Last Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetLastConvertedData( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_SetInitializationVector
+//* \brief Set Initialization Vector (or Counter) x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetInitializationVector (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index,
+ unsigned int initvector
+ )
{
- return pADC->ADC_LCDR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH0 */
-/** \brief Return the Channel 0 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH0( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR0;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH1 */
-/** \brief Return the Channel 1 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH1( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR1;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH2 */
-/** \brief Return the Channel 2 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH2( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR2;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH3 */
-/** \brief Return the Channel 3 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH3( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR3;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH4 */
-/** \brief Return the Channel 4 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH4( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR4;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH5 */
-/** \brief Return the Channel 5 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH5( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR5;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH6 */
-/** \brief Return the Channel 6 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH6( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR6;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH7 */
-/** \brief Return the Channel 7 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH7( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR7;
+ pAES->AES_IVxR[index] = initvector;
}
/* *****************************************************************************
-* SOFTWARE API FOR AES
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_EnableIt */
-/** \brief Enable AES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_EnableIt( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned int flag ) /* IT to be enabled */
+ SOFTWARE API FOR TDES
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_EnableIt
+//* \brief Enable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_EnableIt (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pAES->AES_IER = flag;
+ //* Write to the IER register
+ pTDES->TDES_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_DisableIt */
-/** \brief Disable AES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_DisableIt( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_DisableIt
+//* \brief Disable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_DisableIt (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pAES->AES_IDR = flag;
+ //* Write to the IDR register
+ pTDES->TDES_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetStatus */
-/** \brief Return AES Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetStatus( /* \return AES Interrupt Status */
- AT91PS_AES pAES ) /* pointer to a AES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetStatus
+//* \brief Return TDES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
+ AT91PS_TDES pTDES) // pointer to a TDES controller
{
- return pAES->AES_ISR;
+ return pTDES->TDES_ISR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetInterruptMaskStatus */
-/** \brief Return AES Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetInterruptMaskStatus( /* \return AES Interrupt Mask Status */
- AT91PS_AES pAES ) /* pointer to a AES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetInterruptMaskStatus
+//* \brief Return TDES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
+ AT91PS_TDES pTDES) // pointer to a TDES controller
{
- return pAES->AES_IMR;
+ return pTDES->TDES_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_IsInterruptMasked */
-/** \brief Test if AES Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_IsInterruptMasked( AT91PS_AES pAES, /* \arg pointer to a AES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_IsInterruptMasked
+//* \brief Test if TDES Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsInterruptMasked(
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_AES_GetInterruptMaskStatus( pAES ) & flag );
+ return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_IsStatusSet */
-/** \brief Test if AES Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_IsStatusSet( AT91PS_AES pAES, /* \arg pointer to a AES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_IsStatusSet
+//* \brief Test if TDES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsStatusSet(
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_AES_GetStatus( pAES ) & flag );
+ return (AT91F_TDES_GetStatus(pTDES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_CfgModeReg */
-/** \brief Configure the Mode Register of the AES controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_CfgModeReg( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_CfgModeReg
+//* \brief Configure the Mode Register of the TDES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgModeReg (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned int mode) // mode register
{
- /** Write to the MR register */
- pAES->AES_MR = mode;
+ //* Write to the MR register
+ pTDES->TDES_MR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetModeReg */
-/** \brief Return the Mode Register of the AES controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetModeReg( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetModeReg
+//* \brief Return the Mode Register of the TDES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetModeReg (
+ AT91PS_TDES pTDES // pointer to a TDES controller
+ )
{
- return pAES->AES_MR;
+ return pTDES->TDES_MR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_StartProcessing */
-/** \brief Start Encryption or Decryption */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_StartProcessing( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_StartProcessing (
+ AT91PS_TDES pTDES // pointer to a TDES controller
+ )
{
- pAES->AES_CR = AT91C_AES_START;
+ pTDES->TDES_CR = AT91C_TDES_START;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_SoftReset */
-/** \brief Reset AES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_SoftReset( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SoftReset
+//* \brief Reset TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SoftReset (
+ AT91PS_TDES pTDES // pointer to a TDES controller
+ )
{
- pAES->AES_CR = AT91C_AES_SWRST;
+ pTDES->TDES_CR = AT91C_TDES_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_LoadNewSeed */
-/** \brief Load New Seed in the random number generator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_LoadNewSeed( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetCryptoKey1
+//* \brief Set Cryptographic Key 1 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey1 (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- pAES->AES_CR = AT91C_AES_LOADSEED;
+ pTDES->TDES_KEY1WxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_SetCryptoKey */
-/** \brief Set Cryptographic Key x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_SetCryptoKey( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetCryptoKey2
+//* \brief Set Cryptographic Key 2 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey2 (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- pAES->AES_KEYWxR[ index ] = keyword;
+ pTDES->TDES_KEY2WxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_InputData */
-/** \brief Set Input Data x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_InputData( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index,
- unsigned int indata )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetCryptoKey3
+//* \brief Set Cryptographic Key 3 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey3 (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- pAES->AES_IDATAxR[ index ] = indata;
+ pTDES->TDES_KEY3WxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetOutputData */
-/** \brief Get Output Data x */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetOutputData( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_InputData (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int indata
+ )
{
- return pAES->AES_ODATAxR[ index ];
+ pTDES->TDES_IDATAxR[index] = indata;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_SetInitializationVector */
-/** \brief Set Initialization Vector (or Counter) x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_SetInitializationVector( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index,
- unsigned int initvector )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetOutputData (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index
+ )
{
- pAES->AES_IVxR[ index ] = initvector;
+ return pTDES->TDES_ODATAxR[index];
}
-/* *****************************************************************************
-* SOFTWARE API FOR TDES
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_EnableIt */
-/** \brief Enable TDES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_EnableIt( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetInitializationVector
+//* \brief Set Initialization Vector x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetInitializationVector (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int initvector
+ )
{
- /** Write to the IER register */
- pTDES->TDES_IER = flag;
+ pTDES->TDES_IVxR[index] = initvector;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_DisableIt */
-/** \brief Disable TDES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_DisableIt( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
{
- /** Write to the IDR register */
- pTDES->TDES_IDR = flag;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetStatus */
-/** \brief Return TDES Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetStatus( /* \return TDES Interrupt Status */
- AT91PS_TDES pTDES ) /* pointer to a TDES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
{
- return pTDES->TDES_ISR;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA27_DRXD ) |
+ ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetInterruptMaskStatus */
-/** \brief Return TDES Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( /* \return TDES Interrupt Mask Status */
- AT91PS_TDES pTDES ) /* pointer to a TDES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
{
- return pTDES->TDES_IMR;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_IsInterruptMasked */
-/** \brief Test if TDES Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_IsInterruptMasked( AT91PS_TDES pTDES, /* \arg pointer to a TDES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
{
- return( AT91F_TDES_GetInterruptMaskStatus( pTDES ) & flag );
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB30_PCK2 ) |
+ ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A
+ ((unsigned int) AT91C_PB20_PCK0 ) |
+ ((unsigned int) AT91C_PB0_PCK0 ) |
+ ((unsigned int) AT91C_PB22_PCK2 ) |
+ ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA30_PCK2 ) |
+ ((unsigned int) AT91C_PA13_PCK1 ) |
+ ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_IsStatusSet */
-/** \brief Test if TDES Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_IsStatusSet( AT91PS_TDES pTDES, /* \arg pointer to a TDES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_CfgPMC
+//* \brief Enable Peripheral clock in PMC for VREG
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_CfgPMC (void)
{
- return( AT91F_TDES_GetStatus( pTDES ) & flag );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_CfgModeReg */
-/** \brief Configure the Mode Register of the TDES controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_CfgModeReg( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for RSTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTC_CfgPMC (void)
{
- /** Write to the MR register */
- pTDES->TDES_MR = mode;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetModeReg */
-/** \brief Return the Mode Register of the TDES controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetModeReg( AT91PS_TDES pTDES /* pointer to a TDES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
{
- return pTDES->TDES_MR;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SSC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_StartProcessing */
-/** \brief Start Encryption or Decryption */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_StartProcessing( AT91PS_TDES pTDES /* pointer to a TDES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
{
- pTDES->TDES_CR = AT91C_TDES_START;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA25_RK ) |
+ ((unsigned int) AT91C_PA22_TK ) |
+ ((unsigned int) AT91C_PA21_TF ) |
+ ((unsigned int) AT91C_PA24_RD ) |
+ ((unsigned int) AT91C_PA26_RF ) |
+ ((unsigned int) AT91C_PA23_TD ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SoftReset */
-/** \brief Reset TDES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SoftReset( AT91PS_TDES pTDES /* pointer to a TDES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for WDTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTC_CfgPMC (void)
{
- pTDES->TDES_CR = AT91C_TDES_SWRST;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetCryptoKey1 */
-/** \brief Set Cryptographic Key 1 Word x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetCryptoKey1( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
{
- pTDES->TDES_KEY1WxR[ index ] = keyword;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_US1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetCryptoKey2 */
-/** \brief Set Cryptographic Key 2 Word x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetCryptoKey2( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
{
- pTDES->TDES_KEY2WxR[ index ] = keyword;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB26_RI1 ) |
+ ((unsigned int) AT91C_PB24_DSR1 ) |
+ ((unsigned int) AT91C_PB23_DCD1 ) |
+ ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA7_SCK1 ) |
+ ((unsigned int) AT91C_PA8_RTS1 ) |
+ ((unsigned int) AT91C_PA6_TXD1 ) |
+ ((unsigned int) AT91C_PA5_RXD1 ) |
+ ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetCryptoKey3 */
-/** \brief Set Cryptographic Key 3 Word x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetCryptoKey3( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
{
- pTDES->TDES_KEY3WxR[ index ] = keyword;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_US0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_InputData */
-/** \brief Set Input Data x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_InputData( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int indata )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
{
- pTDES->TDES_IDATAxR[ index ] = indata;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA0_RXD0 ) |
+ ((unsigned int) AT91C_PA4_CTS0 ) |
+ ((unsigned int) AT91C_PA3_RTS0 ) |
+ ((unsigned int) AT91C_PA2_SCK0 ) |
+ ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetOutputData */
-/** \brief Get Output Data x */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetOutputData( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SPI1
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPMC (void)
{
- return pTDES->TDES_ODATAxR[ index ];
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SPI1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetInitializationVector */
-/** \brief Set Initialization Vector x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetInitializationVector( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int initvector )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI1_CfgPIO
+//* \brief Configure PIO controllers to drive SPI1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPIO (void)
{
- pTDES->TDES_IVxR[ index ] = initvector;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB16_NPCS13 ) |
+ ((unsigned int) AT91C_PB10_NPCS11 ) |
+ ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA4_NPCS13 ) |
+ ((unsigned int) AT91C_PA29_NPCS13 ) |
+ ((unsigned int) AT91C_PA21_NPCS10 ) |
+ ((unsigned int) AT91C_PA22_SPCK1 ) |
+ ((unsigned int) AT91C_PA25_NPCS11 ) |
+ ((unsigned int) AT91C_PA2_NPCS11 ) |
+ ((unsigned int) AT91C_PA24_MISO1 ) |
+ ((unsigned int) AT91C_PA3_NPCS12 ) |
+ ((unsigned int) AT91C_PA26_NPCS12 ) |
+ ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for DBGU */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SPI0
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SPI0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_CfgPIO */
-/** \brief Configure PIO controllers to drive DBGU signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI0_CfgPIO
+//* \brief Configure PIO controllers to drive SPI0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA27_DRXD ) |
- ( ( unsigned int ) AT91C_PA28_DTXD ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB13_NPCS01 ) |
+ ((unsigned int) AT91C_PB17_NPCS03 ) |
+ ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA16_MISO0 ) |
+ ((unsigned int) AT91C_PA13_NPCS01 ) |
+ ((unsigned int) AT91C_PA15_NPCS03 ) |
+ ((unsigned int) AT91C_PA17_MOSI0 ) |
+ ((unsigned int) AT91C_PA18_SPCK0 ) |
+ ((unsigned int) AT91C_PA14_NPCS02 ) |
+ ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A
+ ((unsigned int) AT91C_PA7_NPCS01 ) |
+ ((unsigned int) AT91C_PA9_NPCS03 ) |
+ ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PMC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PITC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgPIO */
-/** \brief Configure PIO controllers to drive PMC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB30_PCK2 ) |
- ( ( unsigned int ) AT91C_PB29_PCK1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB20_PCK0 ) |
- ( ( unsigned int ) AT91C_PB0_PCK0 ) |
- ( ( unsigned int ) AT91C_PB22_PCK2 ) |
- ( ( unsigned int ) AT91C_PB21_PCK1 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA30_PCK2 ) |
- ( ( unsigned int ) AT91C_PA13_PCK1 ) |
- ( ( unsigned int ) AT91C_PA27_PCK3 ) ); /* Peripheral B */
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_FIQ) |
+ ((unsigned int) 1 << AT91C_ID_IRQ0) |
+ ((unsigned int) 1 << AT91C_ID_IRQ1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_VREG_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for VREG */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_VREG_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA30_IRQ0 ) |
+ ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A
+ ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for RSTC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RSTC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_AES));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SSC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SSC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TWI));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_CfgPIO */
-/** \brief Configure PIO controllers to drive SSC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA25_RK ) |
- ( ( unsigned int ) AT91C_PA22_TK ) |
- ( ( unsigned int ) AT91C_PA21_TF ) |
- ( ( unsigned int ) AT91C_PA24_RD ) |
- ( ( unsigned int ) AT91C_PA26_RF ) |
- ( ( unsigned int ) AT91C_PA23_TD ), /* Peripheral A */
- 0 ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for WDTC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_WDTC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for US1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US1_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_US1 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US1_CfgPIO */
-/** \brief Configure PIO controllers to drive US1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US1_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB26_RI1 ) |
- ( ( unsigned int ) AT91C_PB24_DSR1 ) |
- ( ( unsigned int ) AT91C_PB23_DCD1 ) |
- ( ( unsigned int ) AT91C_PB25_DTR1 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA7_SCK1 ) |
- ( ( unsigned int ) AT91C_PA8_RTS1 ) |
- ( ( unsigned int ) AT91C_PA6_TXD1 ) |
- ( ( unsigned int ) AT91C_PA5_RXD1 ) |
- ( ( unsigned int ) AT91C_PA9_CTS1 ), /* Peripheral A */
- 0 ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for US0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US0_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_US0 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US0_CfgPIO */
-/** \brief Configure PIO controllers to drive US0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US0_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA0_RXD0 ) |
- ( ( unsigned int ) AT91C_PA4_CTS0 ) |
- ( ( unsigned int ) AT91C_PA3_RTS0 ) |
- ( ( unsigned int ) AT91C_PA2_SCK0 ) |
- ( ( unsigned int ) AT91C_PA1_TXD0 ), /* Peripheral A */
- 0 ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SPI1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI1_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SPI1 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI1_CfgPIO */
-/** \brief Configure PIO controllers to drive SPI1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI1_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB16_NPCS13 ) |
- ( ( unsigned int ) AT91C_PB10_NPCS11 ) |
- ( ( unsigned int ) AT91C_PB11_NPCS12 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA4_NPCS13 ) |
- ( ( unsigned int ) AT91C_PA29_NPCS13 ) |
- ( ( unsigned int ) AT91C_PA21_NPCS10 ) |
- ( ( unsigned int ) AT91C_PA22_SPCK1 ) |
- ( ( unsigned int ) AT91C_PA25_NPCS11 ) |
- ( ( unsigned int ) AT91C_PA2_NPCS11 ) |
- ( ( unsigned int ) AT91C_PA24_MISO1 ) |
- ( ( unsigned int ) AT91C_PA3_NPCS12 ) |
- ( ( unsigned int ) AT91C_PA26_NPCS12 ) |
- ( ( unsigned int ) AT91C_PA23_MOSI1 ) ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SPI0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI0_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SPI0 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI0_CfgPIO */
-/** \brief Configure PIO controllers to drive SPI0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI0_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB13_NPCS01 ) |
- ( ( unsigned int ) AT91C_PB17_NPCS03 ) |
- ( ( unsigned int ) AT91C_PB14_NPCS02 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA16_MISO0 ) |
- ( ( unsigned int ) AT91C_PA13_NPCS01 ) |
- ( ( unsigned int ) AT91C_PA15_NPCS03 ) |
- ( ( unsigned int ) AT91C_PA17_MOSI0 ) |
- ( ( unsigned int ) AT91C_PA18_SPCK0 ) |
- ( ( unsigned int ) AT91C_PA14_NPCS02 ) |
- ( ( unsigned int ) AT91C_PA12_NPCS00 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA7_NPCS01 ) |
- ( ( unsigned int ) AT91C_PA9_NPCS03 ) |
- ( ( unsigned int ) AT91C_PA8_NPCS02 ) ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PITC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for AIC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_FIQ ) |
- ( ( unsigned int ) 1 << AT91C_ID_IRQ0 ) |
- ( ( unsigned int ) 1 << AT91C_ID_IRQ1 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_CfgPIO */
-/** \brief Configure PIO controllers to drive AIC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA30_IRQ0 ) |
- ( ( unsigned int ) AT91C_PA29_FIQ ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA14_IRQ1 ) ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for AES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_AES ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TWI */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TWI ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_CfgPIO */
-/** \brief Configure PIO controllers to drive TWI signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA11_TWCK ) |
- ( ( unsigned int ) AT91C_PA10_TWD ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA11_TWCK ) |
+ ((unsigned int) AT91C_PA10_TWD ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for ADC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_ADC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_ADC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgPIO */
-/** \brief Configure PIO controllers to drive ADC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB18_ADTRG ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH3_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH3 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH3_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB22_PWM3 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB30_PWM3 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A
+ ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH2_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH2 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH2_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB21_PWM2 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB29_PWM2 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A
+ ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH1_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH1_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB20_PWM1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB28_PWM1 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A
+ ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH0_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH0_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB19_PWM0 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB27_PWM0 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A
+ ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RTTC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for RTTC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RTTC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RTTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for RTTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RTTC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for UDP */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_UDP ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_UDP));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TDES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TDES ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TDES));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_EMAC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for EMAC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_EMAC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_EMAC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for EMAC
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_EMAC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_EMAC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_EMAC_CfgPIO */
-/** \brief Configure PIO controllers to drive EMAC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_EMAC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_EMAC_CfgPIO
+//* \brief Configure PIO controllers to drive EMAC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB2_ETX0 ) |
- ( ( unsigned int ) AT91C_PB12_ETXER ) |
- ( ( unsigned int ) AT91C_PB16_ECOL ) |
- ( ( unsigned int ) AT91C_PB11_ETX3 ) |
- ( ( unsigned int ) AT91C_PB6_ERX1 ) |
- ( ( unsigned int ) AT91C_PB15_ERXDV ) |
- ( ( unsigned int ) AT91C_PB13_ERX2 ) |
- ( ( unsigned int ) AT91C_PB3_ETX1 ) |
- ( ( unsigned int ) AT91C_PB8_EMDC ) |
- ( ( unsigned int ) AT91C_PB5_ERX0 ) |
- /*((unsigned int) AT91C_PB18_EF100 ) | */
- ( ( unsigned int ) AT91C_PB14_ERX3 ) |
- ( ( unsigned int ) AT91C_PB4_ECRS_ECRSDV ) |
- ( ( unsigned int ) AT91C_PB1_ETXEN ) |
- ( ( unsigned int ) AT91C_PB10_ETX2 ) |
- ( ( unsigned int ) AT91C_PB0_ETXCK_EREFCK ) |
- ( ( unsigned int ) AT91C_PB9_EMDIO ) |
- ( ( unsigned int ) AT91C_PB7_ERXER ) |
- ( ( unsigned int ) AT91C_PB17_ERXCK ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB2_ETX0 ) |
+ ((unsigned int) AT91C_PB12_ETXER ) |
+ ((unsigned int) AT91C_PB16_ECOL ) |
+ ((unsigned int) AT91C_PB11_ETX3 ) |
+ ((unsigned int) AT91C_PB6_ERX1 ) |
+ ((unsigned int) AT91C_PB15_ERXDV ) |
+ ((unsigned int) AT91C_PB13_ERX2 ) |
+ ((unsigned int) AT91C_PB3_ETX1 ) |
+ ((unsigned int) AT91C_PB8_EMDC ) |
+ ((unsigned int) AT91C_PB5_ERX0 ) |
+ //((unsigned int) AT91C_PB18_EF100 ) |
+ ((unsigned int) AT91C_PB14_ERX3 ) |
+ ((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
+ ((unsigned int) AT91C_PB1_ETXEN ) |
+ ((unsigned int) AT91C_PB10_ETX2 ) |
+ ((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
+ ((unsigned int) AT91C_PB9_EMDIO ) |
+ ((unsigned int) AT91C_PB7_ERXER ) |
+ ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC0_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC0 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC0_CfgPIO */
-/** \brief Configure PIO controllers to drive TC0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC0_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB23_TIOA0 ) |
- ( ( unsigned int ) AT91C_PB24_TIOB0 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB12_TCLK0 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB23_TIOA0 ) |
+ ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A
+ ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC1_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC1 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC1_CfgPIO */
-/** \brief Configure PIO controllers to drive TC1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC1_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB25_TIOA1 ) |
- ( ( unsigned int ) AT91C_PB26_TIOB1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB19_TCLK1 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB25_TIOA1 ) |
+ ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A
+ ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC2_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC2 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC2_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC2 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC2));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC2_CfgPIO */
-/** \brief Configure PIO controllers to drive TC2 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC2_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB28_TIOB2 ) |
- ( ( unsigned int ) AT91C_PB27_TIOA2 ), /* Peripheral A */
- 0 ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA15_TCLK2 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB28_TIOB2 ) |
+ ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A
+ 0); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for MC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIOA_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PIOA */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIOA_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PIOA ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PIOA));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIOB_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PIOB */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIOB_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIOB_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PIOB
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOB_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PIOB ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PIOB));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for CAN */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgPMC
+//* \brief Enable Peripheral clock in PMC for CAN
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_CAN ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_CAN));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgPIO */
-/** \brief Configure PIO controllers to drive CAN signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgPIO
+//* \brief Configure PIO controllers to drive CAN signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA20_CANTX ) |
- ( ( unsigned int ) AT91C_PA19_CANRX ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA20_CANTX ) |
+ ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PWMC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PWMC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PWMC));
}
#endif // lib_AT91SAM7X256_H
diff --git a/portable/GCC/ARM7_AT91SAM7S/port.c b/portable/GCC/ARM7_AT91SAM7S/port.c
index ca39e9b..f4d17b9 100644
--- a/portable/GCC/ARM7_AT91SAM7S/port.c
+++ b/portable/GCC/ARM7_AT91SAM7S/port.c
@@ -27,12 +27,12 @@
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM7 port.
-*
-* Components that can be compiled to either ARM or THUMB mode are
-* contained in this file. The ISR routines, which can only be compiled
-* to ARM mode are contained in portISR.c.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file. The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
/* Standard includes. */
#include <stdlib.h>
@@ -45,139 +45,137 @@
#include "AT91SAM7X256.h"
/* Constants required to setup the task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE 0x00
-#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
+#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE 0x00
+#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
/* Constants required to setup the PIT. */
-#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )
-#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
-#define portINT_LEVEL_SENSITIVE 0
-#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
+#define portINT_LEVEL_SENSITIVE 0
+#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
/*-----------------------------------------------------------*/
/* Setup the timer to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
-/*
- * The scheduler can only be started from ARM mode, so
- * vPortISRStartFirstSTask() is defined in portISR.c.
+/*
+ * The scheduler can only be started from ARM mode, so
+ * vPortISRStartFirstSTask() is defined in portISR.c.
*/
extern void vPortISRStartFirstTask( void );
/*-----------------------------------------------------------*/
-/*
- * Initialise the stack of a task to look exactly as if a call to
+/*
+ * Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
- * See header file for description.
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The last thing onto the stack is the status register, which is set for
- * system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* The last thing onto the stack is the status register, which is set for
+ system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- #ifdef THUMB_INTERWORK
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
- #endif
+ #ifdef THUMB_INTERWORK
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+ #endif
- pxTopOfStack--;
+ pxTopOfStack--;
- /* Some optimisation levels use the stack differently to others. This
- * means the interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+ /* Some optimisation levels use the stack differently to others. This
+ means the interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortISRStartFirstTask();
+ /* Start the first task. */
+ vPortISRStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
@@ -186,23 +184,30 @@
*/
static void prvSetupTimerInterrupt( void )
{
- AT91PS_PITC pxPIT = AT91C_BASE_PITC;
+AT91PS_PITC pxPIT = AT91C_BASE_PITC;
- /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
- * on whether the preemptive or cooperative scheduler is being used. */
- #if configUSE_PREEMPTION == 0
- extern void( vNonPreemptiveTick ) ( void );
- AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vNonPreemptiveTick );
- #else
- extern void( vPreemptiveTick )( void );
- AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPreemptiveTick );
- #endif
+ /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
+ on whether the preemptive or cooperative scheduler is being used. */
+ #if configUSE_PREEMPTION == 0
- /* Configure the PIT period. */
- pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
+ extern void ( vNonPreemptiveTick ) ( void );
+ AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
- /* Enable the interrupt. Global interrupts are disables at this point so
- * this is safe. */
+ #else
+
+ extern void ( vPreemptiveTick )( void );
+ AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
+
+ #endif
+
+ /* Configure the PIT period. */
+ pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
+
+ /* Enable the interrupt. Global interrupts are disables at this point so
+ this is safe. */
AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/GCC/ARM7_AT91SAM7S/portISR.c b/portable/GCC/ARM7_AT91SAM7S/portISR.c
index a8d9e00..1445b4b 100644
--- a/portable/GCC/ARM7_AT91SAM7S/portISR.c
+++ b/portable/GCC/ARM7_AT91SAM7S/portISR.c
@@ -27,17 +27,17 @@
/*-----------------------------------------------------------
-* Components that can be compiled to either ARM or THUMB mode are
-* contained in port.c The ISR routines, which can only be compiled
-* to ARM mode, are contained in this file.
-*----------------------------------------------------------*/
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
/*
- * Changes from V3.2.4
- *
- + The assembler statements are now included in a single asm block rather
- + than each line having its own asm block.
- */
+ Changes from V3.2.4
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -46,17 +46,17 @@
#include "AT91SAM7X256.h"
/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
volatile uint32_t ulCriticalNesting = 9999UL;
/*-----------------------------------------------------------*/
/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
/*
* The scheduler can only be started from ARM mode, hence the inclusion of this
@@ -67,9 +67,9 @@
void vPortISRStartFirstTask( void )
{
- /* Simply start the scheduler. This is included here as it can only be
- * called from ARM mode. */
- portRESTORE_CONTEXT();
+ /* Simply start the scheduler. This is included here as it can only be
+ called from ARM mode. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@@ -83,19 +83,19 @@
*/
void vPortYieldProcessor( void )
{
- /* Within an IRQ ISR the link register has an offset from the true return
- * address, but an SWI ISR does not. Add the offset manually so the same
- * ISR return code can be used in both cases. */
- __asm volatile ( "ADD LR, LR, #4");
+ /* Within an IRQ ISR the link register has an offset from the true return
+ address, but an SWI ISR does not. Add the offset manually so the same
+ ISR return code can be used in both cases. */
+ __asm volatile ( "ADD LR, LR, #4" );
- /* Perform the context switch. First save the context of the current task. */
- portSAVE_CONTEXT();
+ /* Perform the context switch. First save the context of the current task. */
+ portSAVE_CONTEXT();
- /* Find the highest priority task that is ready to run. */
- vTaskSwitchContext();
+ /* Find the highest priority task that is ready to run. */
+ vTaskSwitchContext();
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@@ -106,49 +106,49 @@
#if configUSE_PREEMPTION == 0
-/* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick. */
- void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
- void vNonPreemptiveTick( void )
- {
- uint32_t ulDummy;
+ /* The cooperative scheduler requires a normal IRQ service routine to
+ simply increment the system tick. */
+ void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+ void vNonPreemptiveTick( void )
+ {
+ uint32_t ulDummy;
- /* Increment the tick count - which may wake some tasks but as the
- * preemptive scheduler is not being used any woken task is not given
- * processor time no matter what its priority. */
- xTaskIncrementTick();
+ /* Increment the tick count - which may wake some tasks but as the
+ preemptive scheduler is not being used any woken task is not given
+ processor time no matter what its priority. */
+ xTaskIncrementTick();
- /* Clear the PIT interrupt. */
- ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+ /* Clear the PIT interrupt. */
+ ulDummy = AT91C_BASE_PITC->PITC_PIVR;
- /* End the interrupt in the AIC. */
- AT91C_BASE_AIC->AIC_EOICR = ulDummy;
- }
+ /* End the interrupt in the AIC. */
+ AT91C_BASE_AIC->AIC_EOICR = ulDummy;
+ }
-#else /* if configUSE_PREEMPTION == 0 */
+#else
-/* The preemptive scheduler is defined as "naked" as the full context is
- * saved on entry as part of the context switch. */
- void vPreemptiveTick( void ) __attribute__( ( naked ) );
- void vPreemptiveTick( void )
- {
- /* Save the context of the current task. */
- portSAVE_CONTEXT();
+ /* The preemptive scheduler is defined as "naked" as the full context is
+ saved on entry as part of the context switch. */
+ void vPreemptiveTick( void ) __attribute__((naked));
+ void vPreemptiveTick( void )
+ {
+ /* Save the context of the current task. */
+ portSAVE_CONTEXT();
- /* Increment the tick count - this may wake a task. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Find the highest priority task that is ready to run. */
- vTaskSwitchContext();
- }
+ /* Increment the tick count - this may wake a task. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Find the highest priority task that is ready to run. */
+ vTaskSwitchContext();
+ }
- /* End the interrupt in the AIC. */
- AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;
+ /* End the interrupt in the AIC. */
+ AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;
- portRESTORE_CONTEXT();
- }
+ portRESTORE_CONTEXT();
+ }
-#endif /* if configUSE_PREEMPTION == 0 */
+#endif
/*-----------------------------------------------------------*/
/*
@@ -157,70 +157,71 @@
* ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
* the utilities are defined as macros in portmacro.h - as per other ports.
*/
-void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
-void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
void vPortDisableInterruptsFromThumb( void )
{
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0} \n\t"/* Pop R0. */
- "BX R14"); /* Return back to thumb. */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
}
void vPortEnableInterruptsFromThumb( void )
{
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0} \n\t"/* Pop R0. */
- "BX R14"); /* Return back to thumb. */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
}
/* The code generated by the GCC compiler uses the stack in different ways at
- * different optimisation levels. The interrupt flags can therefore not always
- * be saved to the stack. Instead the critical section nesting level is stored
- * in a variable, which is then saved as part of the stack context. */
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0}"); /* Pop R0. */
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0}"); /* Pop R0. */
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+ }
+ }
}
+
diff --git a/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/portable/GCC/ARM7_AT91SAM7S/portmacro.h
index 31aa431..72df670 100644
--- a/portable/GCC/ARM7_AT91SAM7S/portmacro.h
+++ b/portable/GCC/ARM7_AT91SAM7S/portmacro.h
@@ -26,34 +26,34 @@
*/
/*
- * Changes from V3.2.3
- *
- + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
- +
- + Changes from V3.2.4
- +
- + Removed the use of the %0 parameter within the assembler macros and
- + replaced them with hard coded registers. This will ensure the
- + assembler does not select the link register as the temp register as
- + was occasionally happening previously.
- +
- + The assembler statements are now included in a single asm block rather
- + than each line having its own asm block.
- +
- + Changes from V4.5.0
- +
- + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
- + and replaced them with portYIELD_FROM_ISR() macro. Application code
- + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
- + macros as per the V4.5.1 demo code.
- */
+ Changes from V3.2.3
+
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+ Changes from V3.2.4
+
+ + Removed the use of the %0 parameter within the assembler macros and
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
+ + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
+*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -66,32 +66,32 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE portLONG
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE portLONG
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP() __asm volatile ( "NOP" );
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP() __asm volatile ( "NOP" );
/*-----------------------------------------------------------*/
@@ -104,92 +104,92 @@
* THUMB mode code will result in a compile time error.
*/
- #define portRESTORE_CONTEXT() \
- { \
- extern volatile void * volatile pxCurrentTCB; \
- extern volatile uint32_t ulCriticalNesting; \
- \
- /* Set the LR to the task stack. */ \
- __asm volatile ( \
- "LDR R0, =pxCurrentTCB \n\t"\
- "LDR R0, [R0] \n\t"\
- "LDR LR, [R0] \n\t"\
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting \n\t"\
- "LDMFD LR!, {R1} \n\t"\
- "STR R1, [R0] \n\t"\
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0} \n\t"\
- "MSR SPSR, R0 \n\t"\
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^ \n\t"\
- "NOP \n\t"\
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60] \n\t"\
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4 \n\t"\
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
- }
+#define portRESTORE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Set the LR to the task stack. */ \
+ __asm volatile ( \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "LDR LR, [R0] \n\t" \
+ \
+ /* The critical nesting depth is the first item on the stack. */ \
+ /* Load it into the ulCriticalNesting variable. */ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDMFD LR!, {R1} \n\t" \
+ "STR R1, [R0] \n\t" \
+ \
+ /* Get the SPSR from the stack. */ \
+ "LDMFD LR!, {R0} \n\t" \
+ "MSR SPSR, R0 \n\t" \
+ \
+ /* Restore all system mode registers for the task. */ \
+ "LDMFD LR, {R0-R14}^ \n\t" \
+ "NOP \n\t" \
+ \
+ /* Restore the return address. */ \
+ "LDR LR, [LR, #+60] \n\t" \
+ \
+ /* And return - correcting the offset in the LR to obtain the */ \
+ /* correct address. */ \
+ "SUBS PC, LR, #4 \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
/*-----------------------------------------------------------*/
- #define portSAVE_CONTEXT() \
- { \
- extern volatile void * volatile pxCurrentTCB; \
- extern volatile uint32_t ulCriticalNesting; \
- \
- /* Push R0 as we are going to use the register. */ \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t"\
- \
- /* Set R0 to point to the task stack pointer. */ \
- "STMDB SP,{SP}^ \n\t"\
- "NOP \n\t"\
- "SUB SP, SP, #4 \n\t"\
- "LDMIA SP!,{R0} \n\t"\
- \
- /* Push the return address onto the stack. */ \
- "STMDB R0!, {LR} \n\t"\
- \
- /* Now we have saved LR we can use it instead of R0. */ \
- "MOV LR, R0 \n\t"\
- \
- /* Pop R0 so we can save it onto the system mode stack. */ \
- "LDMIA SP!, {R0} \n\t"\
- \
- /* Push all the system mode registers onto the task stack. */ \
- "STMDB LR,{R0-LR}^ \n\t"\
- "NOP \n\t"\
- "SUB LR, LR, #60 \n\t"\
- \
- /* Push the SPSR onto the task stack. */ \
- "MRS R0, SPSR \n\t"\
- "STMDB LR!, {R0} \n\t"\
- \
- "LDR R0, =ulCriticalNesting \n\t"\
- "LDR R0, [R0] \n\t"\
- "STMDB LR!, {R0} \n\t"\
- \
- /* Store the new top of stack for the task. */ \
- "LDR R0, =pxCurrentTCB \n\t"\
- "LDR R0, [R0] \n\t"\
- "STR LR, [R0] \n\t"\
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
- }
+#define portSAVE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Push R0 as we are going to use the register. */ \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" \
+ \
+ /* Set R0 to point to the task stack pointer. */ \
+ "STMDB SP,{SP}^ \n\t" \
+ "NOP \n\t" \
+ "SUB SP, SP, #4 \n\t" \
+ "LDMIA SP!,{R0} \n\t" \
+ \
+ /* Push the return address onto the stack. */ \
+ "STMDB R0!, {LR} \n\t" \
+ \
+ /* Now we have saved LR we can use it instead of R0. */ \
+ "MOV LR, R0 \n\t" \
+ \
+ /* Pop R0 so we can save it onto the system mode stack. */ \
+ "LDMIA SP!, {R0} \n\t" \
+ \
+ /* Push all the system mode registers onto the task stack. */ \
+ "STMDB LR,{R0-LR}^ \n\t" \
+ "NOP \n\t" \
+ "SUB LR, LR, #60 \n\t" \
+ \
+ /* Push the SPSR onto the task stack. */ \
+ "MRS R0, SPSR \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ /* Store the new top of stack for the task. */ \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STR LR, [R0] \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
- #define portYIELD_FROM_ISR() vTaskSwitchContext()
- #define portYIELD() __asm volatile ( "SWI 0" )
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD() __asm volatile ( "SWI 0" )
/*-----------------------------------------------------------*/
@@ -202,47 +202,48 @@
* defined then the utilities are defined as macros here - as per other ports.
*/
- #ifdef THUMB_INTERWORK
+#ifdef THUMB_INTERWORK
- extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
- extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
- #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
- #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
- #else
+#else
- #define portDISABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t"/* Push R0. */\
- "MRS R0, CPSR \n\t"/* Get CPSR. */\
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
- "MSR CPSR, R0 \n\t"/* Write back modified value. */\
- "LDMIA SP!, {R0} ") /* Pop R0. */
+ #define portDISABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
- #define portENABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t"/* Push R0. */\
- "MRS R0, CPSR \n\t"/* Get CPSR. */\
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
- "MSR CPSR, R0 \n\t"/* Write back modified value. */\
- "LDMIA SP!, {R0} ") /* Pop R0. */
+ #define portENABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
- #endif /* THUMB_INTERWORK */
+#endif /* THUMB_INTERWORK */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/ARM7_LPC2000/port.c b/portable/GCC/ARM7_LPC2000/port.c
index c30fec9..266333f 100644
--- a/portable/GCC/ARM7_LPC2000/port.c
+++ b/portable/GCC/ARM7_LPC2000/port.c
@@ -27,12 +27,12 @@
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM7 port.
-*
-* Components that can be compiled to either ARM or THUMB mode are
-* contained in this file. The ISR routines, which can only be compiled
-* to ARM mode are contained in portISR.c.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file. The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
/* Standard includes. */
@@ -43,136 +43,134 @@
#include "task.h"
/* Constants required to setup the task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE 0x00
-#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
+#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE 0x00
+#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
/* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
+#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
/*-----------------------------------------------------------*/
/* Setup the timer to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
-/*
- * The scheduler can only be started from ARM mode, so
- * vPortISRStartFirstSTask() is defined in portISR.c.
+/*
+ * The scheduler can only be started from ARM mode, so
+ * vPortISRStartFirstSTask() is defined in portISR.c.
*/
extern void vPortISRStartFirstTask( void );
/*-----------------------------------------------------------*/
-/*
- * Initialise the stack of a task to look exactly as if a call to
+/*
+ * Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
- * See header file for description.
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The last thing onto the stack is the status register, which is set for
- * system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* The last thing onto the stack is the status register, which is set for
+ system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
- pxTopOfStack--;
+ pxTopOfStack--;
- /* Some optimisation levels use the stack differently to others. This
- * means the interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+ /* Some optimisation levels use the stack differently to others. This
+ means the interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortISRStartFirstTask();
+ /* Start the first task. */
+ vPortISRStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
@@ -181,41 +179,43 @@
*/
static void prvSetupTimerInterrupt( void )
{
- uint32_t ulCompareMatch;
+uint32_t ulCompareMatch;
+extern void ( vTickISR )( void );
- extern void( vTickISR )( void );
+ /* A 1ms tick does not require the use of the timer prescale. This is
+ defaulted to zero but can be used if necessary. */
+ T0_PR = portPRESCALE_VALUE;
- /* A 1ms tick does not require the use of the timer prescale. This is
- * defaulted to zero but can be used if necessary. */
- T0_PR = portPRESCALE_VALUE;
+ /* Calculate the match value required for our wanted tick rate. */
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
- /* Calculate the match value required for our wanted tick rate. */
- ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+ /* Protect against divide by zero. Using an if() statement still results
+ in a warning - hence the #if. */
+ #if portPRESCALE_VALUE != 0
+ {
+ ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+ }
+ #endif
+ T0_MR0 = ulCompareMatch;
- /* Protect against divide by zero. Using an if() statement still results
- * in a warning - hence the #if. */
- #if portPRESCALE_VALUE != 0
- {
- ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
- }
- #endif
- T0_MR0 = ulCompareMatch;
+ /* Generate tick with timer 0 compare match. */
+ T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
- /* Generate tick with timer 0 compare match. */
- T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+ /* Setup the VIC for the timer. */
+ VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+ VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+
+ /* The ISR installed depends on whether the preemptive or cooperative
+ scheduler is being used. */
- /* Setup the VIC for the timer. */
- VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
- VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+ VICVectAddr0 = ( int32_t ) vTickISR;
+ VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
- /* The ISR installed depends on whether the preemptive or cooperative
- * scheduler is being used. */
-
- VICVectAddr0 = ( int32_t ) vTickISR;
- VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
-
- /* Start the timer - interrupts are disabled when this function is called
- * so it is okay to do this here. */
- T0_TCR = portENABLE_TIMER;
+ /* Start the timer - interrupts are disabled when this function is called
+ so it is okay to do this here. */
+ T0_TCR = portENABLE_TIMER;
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/GCC/ARM7_LPC2000/portISR.c b/portable/GCC/ARM7_LPC2000/portISR.c
index 8c57213..080dc13 100644
--- a/portable/GCC/ARM7_LPC2000/portISR.c
+++ b/portable/GCC/ARM7_LPC2000/portISR.c
@@ -27,45 +27,45 @@
/*-----------------------------------------------------------
-* Components that can be compiled to either ARM or THUMB mode are
-* contained in port.c The ISR routines, which can only be compiled
-* to ARM mode, are contained in this file.
-*----------------------------------------------------------*/
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
/*
- * Changes from V2.5.2
- *
- + The critical section management functions have been changed. These no
- + longer modify the stack and are safe to use at all optimisation levels.
- + The functions are now also the same for both ARM and THUMB modes.
- +
- + Changes from V2.6.0
- +
- + Removed the 'static' from the definition of vNonPreemptiveTick() to
- + allow the demo to link when using the cooperative scheduler.
- +
- + Changes from V3.2.4
- +
- + The assembler statements are now included in a single asm block rather
- + than each line having its own asm block.
- */
+ Changes from V2.5.2
+
+ + The critical section management functions have been changed. These no
+ longer modify the stack and are safe to use at all optimisation levels.
+ The functions are now also the same for both ARM and THUMB modes.
+
+ Changes from V2.6.0
+
+ + Removed the 'static' from the definition of vNonPreemptiveTick() to
+ allow the demo to link when using the cooperative scheduler.
+
+ Changes from V3.2.4
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+*/
/* Scheduler includes. */
#include "FreeRTOS.h"
/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
volatile uint32_t ulCriticalNesting = 9999UL;
/*-----------------------------------------------------------*/
/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
/*
* The scheduler can only be started from ARM mode, hence the inclusion of this
@@ -76,9 +76,9 @@
void vPortISRStartFirstTask( void )
{
- /* Simply start the scheduler. This is included here as it can only be
- * called from ARM mode. */
- portRESTORE_CONTEXT();
+ /* Simply start the scheduler. This is included here as it can only be
+ called from ARM mode. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@@ -92,48 +92,48 @@
*/
void vPortYieldProcessor( void )
{
- /* Within an IRQ ISR the link register has an offset from the true return
- * address, but an SWI ISR does not. Add the offset manually so the same
- * ISR return code can be used in both cases. */
- __asm volatile ( "ADD LR, LR, #4");
+ /* Within an IRQ ISR the link register has an offset from the true return
+ address, but an SWI ISR does not. Add the offset manually so the same
+ ISR return code can be used in both cases. */
+ __asm volatile ( "ADD LR, LR, #4" );
- /* Perform the context switch. First save the context of the current task. */
- portSAVE_CONTEXT();
+ /* Perform the context switch. First save the context of the current task. */
+ portSAVE_CONTEXT();
- /* Find the highest priority task that is ready to run. */
- __asm volatile ( "bl vTaskSwitchContext" );
+ /* Find the highest priority task that is ready to run. */
+ __asm volatile ( "bl vTaskSwitchContext" );
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
/*
* The ISR used for the scheduler tick.
*/
-void vTickISR( void ) __attribute__( ( naked ) );
+void vTickISR( void ) __attribute__((naked));
void vTickISR( void )
{
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
- /* Increment the RTOS tick count, then look for the highest priority
- * task that is ready to run. */
- __asm volatile
- (
- " bl xTaskIncrementTick \t\n"\
- " cmp r0, #0 \t\n"\
- " beq SkipContextSwitch \t\n"\
- " bl vTaskSwitchContext \t\n"\
- "SkipContextSwitch: \t\n"
- );
+ /* Increment the RTOS tick count, then look for the highest priority
+ task that is ready to run. */
+ __asm volatile
+ (
+ " bl xTaskIncrementTick \t\n" \
+ " cmp r0, #0 \t\n" \
+ " beq SkipContextSwitch \t\n" \
+ " bl vTaskSwitchContext \t\n" \
+ "SkipContextSwitch: \t\n"
+ );
- /* Ready for the next interrupt. */
- T0_IR = portTIMER_MATCH_ISR_BIT;
- VICVectAddr = portCLEAR_VIC_INTERRUPT;
+ /* Ready for the next interrupt. */
+ T0_IR = portTIMER_MATCH_ISR_BIT;
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@@ -145,71 +145,71 @@
*/
#ifdef THUMB_INTERWORK
- void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
- void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
- void vPortDisableInterruptsFromThumb( void )
- {
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0} \n\t"/* Pop R0. */
- "BX R14"); /* Return back to thumb. */
- }
+ void vPortDisableInterruptsFromThumb( void )
+ {
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
- void vPortEnableInterruptsFromThumb( void )
- {
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0} \n\t"/* Pop R0. */
- "BX R14"); /* Return back to thumb. */
- }
+ void vPortEnableInterruptsFromThumb( void )
+ {
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
#endif /* THUMB_INTERWORK */
/* The code generated by the GCC compiler uses the stack in different ways at
- * different optimisation levels. The interrupt flags can therefore not always
- * be saved to the stack. Instead the critical section nesting level is stored
- * in a variable, which is then saved as part of the stack context. */
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0}"); /* Pop R0. */
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0}"); /* Pop R0. */
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+ }
+ }
}
diff --git a/portable/GCC/ARM7_LPC2000/portmacro.h b/portable/GCC/ARM7_LPC2000/portmacro.h
index 8b02021..4859393 100644
--- a/portable/GCC/ARM7_LPC2000/portmacro.h
+++ b/portable/GCC/ARM7_LPC2000/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,32 +43,32 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE portLONG
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE portLONG
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP() __asm volatile ( "NOP" );
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP() __asm volatile ( "NOP" );
/*-----------------------------------------------------------*/
@@ -81,92 +81,92 @@
* THUMB mode code will result in a compile time error.
*/
- #define portRESTORE_CONTEXT() \
- { \
- extern volatile void * volatile pxCurrentTCB; \
- extern volatile uint32_t ulCriticalNesting; \
- \
- /* Set the LR to the task stack. */ \
- __asm volatile ( \
- "LDR R0, =pxCurrentTCB \n\t"\
- "LDR R0, [R0] \n\t"\
- "LDR LR, [R0] \n\t"\
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting \n\t"\
- "LDMFD LR!, {R1} \n\t"\
- "STR R1, [R0] \n\t"\
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0} \n\t"\
- "MSR SPSR, R0 \n\t"\
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^ \n\t"\
- "NOP \n\t"\
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60] \n\t"\
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4 \n\t"\
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
- }
+#define portRESTORE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Set the LR to the task stack. */ \
+ __asm volatile ( \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "LDR LR, [R0] \n\t" \
+ \
+ /* The critical nesting depth is the first item on the stack. */ \
+ /* Load it into the ulCriticalNesting variable. */ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDMFD LR!, {R1} \n\t" \
+ "STR R1, [R0] \n\t" \
+ \
+ /* Get the SPSR from the stack. */ \
+ "LDMFD LR!, {R0} \n\t" \
+ "MSR SPSR, R0 \n\t" \
+ \
+ /* Restore all system mode registers for the task. */ \
+ "LDMFD LR, {R0-R14}^ \n\t" \
+ "NOP \n\t" \
+ \
+ /* Restore the return address. */ \
+ "LDR LR, [LR, #+60] \n\t" \
+ \
+ /* And return - correcting the offset in the LR to obtain the */ \
+ /* correct address. */ \
+ "SUBS PC, LR, #4 \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
/*-----------------------------------------------------------*/
- #define portSAVE_CONTEXT() \
- { \
- extern volatile void * volatile pxCurrentTCB; \
- extern volatile uint32_t ulCriticalNesting; \
- \
- /* Push R0 as we are going to use the register. */ \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t"\
- \
- /* Set R0 to point to the task stack pointer. */ \
- "STMDB SP,{SP}^ \n\t"\
- "NOP \n\t"\
- "SUB SP, SP, #4 \n\t"\
- "LDMIA SP!,{R0} \n\t"\
- \
- /* Push the return address onto the stack. */ \
- "STMDB R0!, {LR} \n\t"\
- \
- /* Now we have saved LR we can use it instead of R0. */ \
- "MOV LR, R0 \n\t"\
- \
- /* Pop R0 so we can save it onto the system mode stack. */ \
- "LDMIA SP!, {R0} \n\t"\
- \
- /* Push all the system mode registers onto the task stack. */ \
- "STMDB LR,{R0-LR}^ \n\t"\
- "NOP \n\t"\
- "SUB LR, LR, #60 \n\t"\
- \
- /* Push the SPSR onto the task stack. */ \
- "MRS R0, SPSR \n\t"\
- "STMDB LR!, {R0} \n\t"\
- \
- "LDR R0, =ulCriticalNesting \n\t"\
- "LDR R0, [R0] \n\t"\
- "STMDB LR!, {R0} \n\t"\
- \
- /* Store the new top of stack for the task. */ \
- "LDR R0, =pxCurrentTCB \n\t"\
- "LDR R0, [R0] \n\t"\
- "STR LR, [R0] \n\t"\
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
- }
+#define portSAVE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Push R0 as we are going to use the register. */ \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" \
+ \
+ /* Set R0 to point to the task stack pointer. */ \
+ "STMDB SP,{SP}^ \n\t" \
+ "NOP \n\t" \
+ "SUB SP, SP, #4 \n\t" \
+ "LDMIA SP!,{R0} \n\t" \
+ \
+ /* Push the return address onto the stack. */ \
+ "STMDB R0!, {LR} \n\t" \
+ \
+ /* Now we have saved LR we can use it instead of R0. */ \
+ "MOV LR, R0 \n\t" \
+ \
+ /* Pop R0 so we can save it onto the system mode stack. */ \
+ "LDMIA SP!, {R0} \n\t" \
+ \
+ /* Push all the system mode registers onto the task stack. */ \
+ "STMDB LR,{R0-LR}^ \n\t" \
+ "NOP \n\t" \
+ "SUB LR, LR, #60 \n\t" \
+ \
+ /* Push the SPSR onto the task stack. */ \
+ "MRS R0, SPSR \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ /* Store the new top of stack for the task. */ \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STR LR, [R0] \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
- extern void vTaskSwitchContext( void );
- #define portYIELD_FROM_ISR() vTaskSwitchContext()
- #define portYIELD() __asm volatile ( "SWI 0" )
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD() __asm volatile ( "SWI 0" )
/*-----------------------------------------------------------*/
@@ -179,47 +179,48 @@
* defined then the utilities are defined as macros here - as per other ports.
*/
- #ifdef THUMB_INTERWORK
+#ifdef THUMB_INTERWORK
- extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
- extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
- #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
- #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
- #else
+#else
- #define portDISABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t"/* Push R0. */\
- "MRS R0, CPSR \n\t"/* Get CPSR. */\
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
- "MSR CPSR, R0 \n\t"/* Write back modified value. */\
- "LDMIA SP!, {R0} ") /* Pop R0. */
+ #define portDISABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
- #define portENABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t"/* Push R0. */\
- "MRS R0, CPSR \n\t"/* Get CPSR. */\
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
- "MSR CPSR, R0 \n\t"/* Write back modified value. */\
- "LDMIA SP!, {R0} ") /* Pop R0. */
+ #define portENABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
- #endif /* THUMB_INTERWORK */
+#endif /* THUMB_INTERWORK */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/ARM7_LPC23xx/port.c b/portable/GCC/ARM7_LPC23xx/port.c
index 56d8ed2..d2bf4f4 100644
--- a/portable/GCC/ARM7_LPC23xx/port.c
+++ b/portable/GCC/ARM7_LPC23xx/port.c
@@ -27,12 +27,12 @@
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM7 port.
-*
-* Components that can be compiled to either ARM or THUMB mode are
-* contained in this file. The ISR routines, which can only be compiled
-* to ARM mode are contained in portISR.c.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file. The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
/* Standard includes. */
@@ -43,136 +43,134 @@
#include "task.h"
/* Constants required to setup the task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE 0x00
-#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
+#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE 0x00
+#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
/* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
+#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
/*-----------------------------------------------------------*/
/* Setup the timer to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
-/*
- * The scheduler can only be started from ARM mode, so
- * vPortISRStartFirstSTask() is defined in portISR.c.
+/*
+ * The scheduler can only be started from ARM mode, so
+ * vPortISRStartFirstSTask() is defined in portISR.c.
*/
extern void vPortISRStartFirstTask( void );
/*-----------------------------------------------------------*/
-/*
- * Initialise the stack of a task to look exactly as if a call to
+/*
+ * Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
- * See header file for description.
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
+
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* The last thing onto the stack is the status register, which is set for
+ system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- /* The last thing onto the stack is the status register, which is set for
- * system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
- if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ pxTopOfStack--;
- pxTopOfStack--;
+ /* Some optimisation levels use the stack differently to others. This
+ means the interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
- /* Some optimisation levels use the stack differently to others. This
- * means the interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortISRStartFirstTask();
+ /* Start the first task. */
+ vPortISRStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
@@ -181,52 +179,55 @@
*/
static void prvSetupTimerInterrupt( void )
{
- uint32_t ulCompareMatch;
+uint32_t ulCompareMatch;
- PCLKSEL0 = ( PCLKSEL0 & ( ~( 0x3 << 2 ) ) ) | ( 0x01 << 2 );
- T0TCR = 2; /* Stop and reset the timer */
- T0CTCR = 0; /* Timer mode */
+ PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);
+ T0TCR = 2; /* Stop and reset the timer */
+ T0CTCR = 0; /* Timer mode */
+
+ /* A 1ms tick does not require the use of the timer prescale. This is
+ defaulted to zero but can be used if necessary. */
+ T0PR = portPRESCALE_VALUE;
- /* A 1ms tick does not require the use of the timer prescale. This is
- * defaulted to zero but can be used if necessary. */
- T0PR = portPRESCALE_VALUE;
+ /* Calculate the match value required for our wanted tick rate. */
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
- /* Calculate the match value required for our wanted tick rate. */
- ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+ /* Protect against divide by zero. Using an if() statement still results
+ in a warning - hence the #if. */
+ #if portPRESCALE_VALUE != 0
+ {
+ ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+ }
+ #endif
+ T0MR1 = ulCompareMatch;
- /* Protect against divide by zero. Using an if() statement still results
- * in a warning - hence the #if. */
- #if portPRESCALE_VALUE != 0
- {
- ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
- }
- #endif
- T0MR1 = ulCompareMatch;
+ /* Generate tick with timer 0 compare match. */
+ T0MCR = (3 << 3); /* Reset timer on match and generate interrupt */
- /* Generate tick with timer 0 compare match. */
- T0MCR = ( 3 << 3 ); /* Reset timer on match and generate interrupt */
+ /* Setup the VIC for the timer. */
+ VICIntEnable = 0x00000010;
+
+ /* The ISR installed depends on whether the preemptive or cooperative
+ scheduler is being used. */
+ #if configUSE_PREEMPTION == 1
+ {
+ extern void ( vPreemptiveTick )( void );
+ VICVectAddr4 = ( int32_t ) vPreemptiveTick;
+ }
+ #else
+ {
+ extern void ( vNonPreemptiveTick )( void );
+ VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
+ }
+ #endif
- /* Setup the VIC for the timer. */
- VICIntEnable = 0x00000010;
+ VICVectCntl4 = 1;
- /* The ISR installed depends on whether the preemptive or cooperative
- * scheduler is being used. */
- #if configUSE_PREEMPTION == 1
- {
- extern void( vPreemptiveTick )( void );
- VICVectAddr4 = ( int32_t ) vPreemptiveTick;
- }
- #else
- {
- extern void( vNonPreemptiveTick )( void );
- VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
- }
- #endif
-
- VICVectCntl4 = 1;
-
- /* Start the timer - interrupts are disabled when this function is called
- * so it is okay to do this here. */
- T0TCR = portENABLE_TIMER;
+ /* Start the timer - interrupts are disabled when this function is called
+ so it is okay to do this here. */
+ T0TCR = portENABLE_TIMER;
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/GCC/ARM7_LPC23xx/portISR.c b/portable/GCC/ARM7_LPC23xx/portISR.c
index b9f38e4..49f5e0b 100644
--- a/portable/GCC/ARM7_LPC23xx/portISR.c
+++ b/portable/GCC/ARM7_LPC23xx/portISR.c
@@ -27,29 +27,29 @@
/*-----------------------------------------------------------
-* Components that can be compiled to either ARM or THUMB mode are
-* contained in port.c The ISR routines, which can only be compiled
-* to ARM mode, are contained in this file.
-*----------------------------------------------------------*/
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
volatile uint32_t ulCriticalNesting = 9999UL;
/*-----------------------------------------------------------*/
/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
-/*
+/*
* The scheduler can only be started from ARM mode, hence the inclusion of this
* function here.
*/
@@ -58,39 +58,39 @@
void vPortISRStartFirstTask( void )
{
- /* Simply start the scheduler. This is included here as it can only be
- * called from ARM mode. */
- portRESTORE_CONTEXT();
+ /* Simply start the scheduler. This is included here as it can only be
+ called from ARM mode. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
/*
* Called by portYIELD() or taskYIELD() to manually force a context switch.
*
- * When a context switch is performed from the task level the saved task
+ * When a context switch is performed from the task level the saved task
* context is made to look as if it occurred from within the tick ISR. This
* way the same restore context function can be used when restoring the context
* saved from the ISR or that saved from a call to vPortYieldProcessor.
*/
void vPortYieldProcessor( void )
{
- /* Within an IRQ ISR the link register has an offset from the true return
- * address, but an SWI ISR does not. Add the offset manually so the same
- * ISR return code can be used in both cases. */
- __asm volatile ( "ADD LR, LR, #4");
+ /* Within an IRQ ISR the link register has an offset from the true return
+ address, but an SWI ISR does not. Add the offset manually so the same
+ ISR return code can be used in both cases. */
+ __asm volatile ( "ADD LR, LR, #4" );
- /* Perform the context switch. First save the context of the current task. */
- portSAVE_CONTEXT();
+ /* Perform the context switch. First save the context of the current task. */
+ portSAVE_CONTEXT();
- /* Find the highest priority task that is ready to run. */
- __asm volatile ( "bl vTaskSwitchContext");
+ /* Find the highest priority task that is ready to run. */
+ __asm volatile( "bl vTaskSwitchContext" );
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
-/*
+/*
* The ISR used for the scheduler tick depends on whether the cooperative or
* the preemptive scheduler is being used.
*/
@@ -98,46 +98,46 @@
#if configUSE_PREEMPTION == 0
-/* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick. */
- void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
- void vNonPreemptiveTick( void )
- {
- xTaskIncrementTick();
- T0IR = 2;
- VICVectAddr = portCLEAR_VIC_INTERRUPT;
- }
+ /* The cooperative scheduler requires a normal IRQ service routine to
+ simply increment the system tick. */
+ void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+ void vNonPreemptiveTick( void )
+ {
+ xTaskIncrementTick();
+ T0IR = 2;
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;
+ }
-#else /* if configUSE_PREEMPTION == 0 */
+#else
-/* The preemptive scheduler is defined as "naked" as the full context is
- * saved on entry as part of the context switch. */
- void vPreemptiveTick( void ) __attribute__( ( naked ) );
- void vPreemptiveTick( void )
- {
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
+ /* The preemptive scheduler is defined as "naked" as the full context is
+ saved on entry as part of the context switch. */
+ void vPreemptiveTick( void ) __attribute__((naked));
+ void vPreemptiveTick( void )
+ {
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
- /* Increment the RTOS tick count, then look for the highest priority
- * task that is ready to run. */
- __asm volatile
- (
- " bl xTaskIncrementTick \t\n"\
- " cmp r0, #0 \t\n"\
- " beq SkipContextSwitch \t\n"\
- " bl vTaskSwitchContext \t\n"\
- "SkipContextSwitch: \t\n"
- );
+ /* Increment the RTOS tick count, then look for the highest priority
+ task that is ready to run. */
+ __asm volatile
+ (
+ " bl xTaskIncrementTick \t\n" \
+ " cmp r0, #0 \t\n" \
+ " beq SkipContextSwitch \t\n" \
+ " bl vTaskSwitchContext \t\n" \
+ "SkipContextSwitch: \t\n"
+ );
- /* Ready for the next interrupt. */
- T0IR = 2;
- VICVectAddr = portCLEAR_VIC_INTERRUPT;
+ /* Ready for the next interrupt. */
+ T0IR = 2;
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+ }
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
- }
-
-#endif /* if configUSE_PREEMPTION == 0 */
+#endif
/*-----------------------------------------------------------*/
/*
@@ -148,71 +148,71 @@
*/
#ifdef THUMB_INTERWORK
- void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
- void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
- void vPortDisableInterruptsFromThumb( void )
- {
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0} \n\t"/* Pop R0. */
- "BX R14"); /* Return back to thumb. */
- }
-
- void vPortEnableInterruptsFromThumb( void )
- {
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0} \n\t"/* Pop R0. */
- "BX R14"); /* Return back to thumb. */
- }
+ void vPortDisableInterruptsFromThumb( void )
+ {
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+ void vPortEnableInterruptsFromThumb( void )
+ {
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
#endif /* THUMB_INTERWORK */
/* The code generated by the GCC compiler uses the stack in different ways at
- * different optimisation levels. The interrupt flags can therefore not always
- * be saved to the stack. Instead the critical section nesting level is stored
- * in a variable, which is then saved as part of the stack context. */
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0}"); /* Pop R0. */
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- __asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0}"); /* Pop R0. */
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+ }
+ }
}
diff --git a/portable/GCC/ARM7_LPC23xx/portmacro.h b/portable/GCC/ARM7_LPC23xx/portmacro.h
index 31aa431..b15157f 100644
--- a/portable/GCC/ARM7_LPC23xx/portmacro.h
+++ b/portable/GCC/ARM7_LPC23xx/portmacro.h
@@ -26,34 +26,34 @@
*/
/*
- * Changes from V3.2.3
- *
- + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
- +
- + Changes from V3.2.4
- +
- + Removed the use of the %0 parameter within the assembler macros and
- + replaced them with hard coded registers. This will ensure the
- + assembler does not select the link register as the temp register as
- + was occasionally happening previously.
- +
- + The assembler statements are now included in a single asm block rather
- + than each line having its own asm block.
- +
- + Changes from V4.5.0
- +
- + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
- + and replaced them with portYIELD_FROM_ISR() macro. Application code
- + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
- + macros as per the V4.5.1 demo code.
- */
+ Changes from V3.2.3
+
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+ Changes from V3.2.4
+
+ + Removed the use of the %0 parameter within the assembler macros and
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
+ + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
+*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -66,32 +66,32 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE portLONG
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE portLONG
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP() __asm volatile ( "NOP" );
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP() __asm volatile ( "NOP" );
/*-----------------------------------------------------------*/
@@ -104,92 +104,92 @@
* THUMB mode code will result in a compile time error.
*/
- #define portRESTORE_CONTEXT() \
- { \
- extern volatile void * volatile pxCurrentTCB; \
- extern volatile uint32_t ulCriticalNesting; \
- \
- /* Set the LR to the task stack. */ \
- __asm volatile ( \
- "LDR R0, =pxCurrentTCB \n\t"\
- "LDR R0, [R0] \n\t"\
- "LDR LR, [R0] \n\t"\
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting \n\t"\
- "LDMFD LR!, {R1} \n\t"\
- "STR R1, [R0] \n\t"\
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0} \n\t"\
- "MSR SPSR, R0 \n\t"\
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^ \n\t"\
- "NOP \n\t"\
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60] \n\t"\
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4 \n\t"\
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
- }
+#define portRESTORE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Set the LR to the task stack. */ \
+ __asm volatile ( \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "LDR LR, [R0] \n\t" \
+ \
+ /* The critical nesting depth is the first item on the stack. */ \
+ /* Load it into the ulCriticalNesting variable. */ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDMFD LR!, {R1} \n\t" \
+ "STR R1, [R0] \n\t" \
+ \
+ /* Get the SPSR from the stack. */ \
+ "LDMFD LR!, {R0} \n\t" \
+ "MSR SPSR, R0 \n\t" \
+ \
+ /* Restore all system mode registers for the task. */ \
+ "LDMFD LR, {R0-R14}^ \n\t" \
+ "NOP \n\t" \
+ \
+ /* Restore the return address. */ \
+ "LDR LR, [LR, #+60] \n\t" \
+ \
+ /* And return - correcting the offset in the LR to obtain the */ \
+ /* correct address. */ \
+ "SUBS PC, LR, #4 \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
/*-----------------------------------------------------------*/
- #define portSAVE_CONTEXT() \
- { \
- extern volatile void * volatile pxCurrentTCB; \
- extern volatile uint32_t ulCriticalNesting; \
- \
- /* Push R0 as we are going to use the register. */ \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t"\
- \
- /* Set R0 to point to the task stack pointer. */ \
- "STMDB SP,{SP}^ \n\t"\
- "NOP \n\t"\
- "SUB SP, SP, #4 \n\t"\
- "LDMIA SP!,{R0} \n\t"\
- \
- /* Push the return address onto the stack. */ \
- "STMDB R0!, {LR} \n\t"\
- \
- /* Now we have saved LR we can use it instead of R0. */ \
- "MOV LR, R0 \n\t"\
- \
- /* Pop R0 so we can save it onto the system mode stack. */ \
- "LDMIA SP!, {R0} \n\t"\
- \
- /* Push all the system mode registers onto the task stack. */ \
- "STMDB LR,{R0-LR}^ \n\t"\
- "NOP \n\t"\
- "SUB LR, LR, #60 \n\t"\
- \
- /* Push the SPSR onto the task stack. */ \
- "MRS R0, SPSR \n\t"\
- "STMDB LR!, {R0} \n\t"\
- \
- "LDR R0, =ulCriticalNesting \n\t"\
- "LDR R0, [R0] \n\t"\
- "STMDB LR!, {R0} \n\t"\
- \
- /* Store the new top of stack for the task. */ \
- "LDR R0, =pxCurrentTCB \n\t"\
- "LDR R0, [R0] \n\t"\
- "STR LR, [R0] \n\t"\
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
- }
+#define portSAVE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Push R0 as we are going to use the register. */ \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" \
+ \
+ /* Set R0 to point to the task stack pointer. */ \
+ "STMDB SP,{SP}^ \n\t" \
+ "NOP \n\t" \
+ "SUB SP, SP, #4 \n\t" \
+ "LDMIA SP!,{R0} \n\t" \
+ \
+ /* Push the return address onto the stack. */ \
+ "STMDB R0!, {LR} \n\t" \
+ \
+ /* Now we have saved LR we can use it instead of R0. */ \
+ "MOV LR, R0 \n\t" \
+ \
+ /* Pop R0 so we can save it onto the system mode stack. */ \
+ "LDMIA SP!, {R0} \n\t" \
+ \
+ /* Push all the system mode registers onto the task stack. */ \
+ "STMDB LR,{R0-LR}^ \n\t" \
+ "NOP \n\t" \
+ "SUB LR, LR, #60 \n\t" \
+ \
+ /* Push the SPSR onto the task stack. */ \
+ "MRS R0, SPSR \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ /* Store the new top of stack for the task. */ \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STR LR, [R0] \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
- #define portYIELD_FROM_ISR() vTaskSwitchContext()
- #define portYIELD() __asm volatile ( "SWI 0" )
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD() __asm volatile ( "SWI 0" )
/*-----------------------------------------------------------*/
@@ -202,47 +202,48 @@
* defined then the utilities are defined as macros here - as per other ports.
*/
- #ifdef THUMB_INTERWORK
+#ifdef THUMB_INTERWORK
- extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
- extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
- #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
- #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
- #else
+#else
- #define portDISABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t"/* Push R0. */\
- "MRS R0, CPSR \n\t"/* Get CPSR. */\
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
- "MSR CPSR, R0 \n\t"/* Write back modified value. */\
- "LDMIA SP!, {R0} ") /* Pop R0. */
+ #define portDISABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
- #define portENABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t"/* Push R0. */\
- "MRS R0, CPSR \n\t"/* Get CPSR. */\
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
- "MSR CPSR, R0 \n\t"/* Write back modified value. */\
- "LDMIA SP!, {R0} ") /* Pop R0. */
+ #define portENABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
- #endif /* THUMB_INTERWORK */
+#endif /* THUMB_INTERWORK */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/ARM_CA53_64_BIT/port.c b/portable/GCC/ARM_CA53_64_BIT/port.c
index d53ccc7..1d26e86 100644
--- a/portable/GCC/ARM_CA53_64_BIT/port.c
+++ b/portable/GCC/ARM_CA53_64_BIT/port.c
@@ -33,104 +33,104 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
- #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
- #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#endif
/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
- * portmacro.h. */
+portmacro.h. */
#ifndef configCLEAR_TICK_INTERRUPT
- #define configCLEAR_TICK_INTERRUPT()
+ #define configCLEAR_TICK_INTERRUPT()
#endif
/* A critical section is exited when the critical section nesting count reaches
- * this value. */
-#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
+this value. */
+#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
- * (but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
- * floating point context after they have been created. A variable is stored as
- * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
- * does not have an FPU context, or any other value if the task does have an FPU
- * context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
-#define portSP_ELx ( ( StackType_t ) 0x01 )
-#define portSP_EL0 ( ( StackType_t ) 0x00 )
+#define portSP_ELx ( ( StackType_t ) 0x01 )
+#define portSP_EL0 ( ( StackType_t ) 0x00 )
#if defined( GUEST )
- #define portEL1 ( ( StackType_t ) 0x04 )
- #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
+ #define portEL1 ( ( StackType_t ) 0x04 )
+ #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
#else
- #define portEL3 ( ( StackType_t ) 0x0c )
- /* At the time of writing, the BSP only supports EL3. */
- #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
+ #define portEL3 ( ( StackType_t ) 0x0c )
+ /* At the time of writing, the BSP only supports EL3. */
+ #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
#endif
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
- * point is zero. */
-#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x0C )
+#define portAPSR_MODE_BITS_MASK ( 0x0C )
/* The I bit in the DAIF bits. */
-#define portDAIF_I ( 0x80 )
+#define portDAIF_I ( 0x80 )
/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK() \
- { \
- portDISABLE_INTERRUPTS(); \
- portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
- __asm volatile ( "DSB SY \n" \
- "ISB SY \n"); \
- portENABLE_INTERRUPTS(); \
- }
+#define portCLEAR_INTERRUPT_MASK() \
+{ \
+ portDISABLE_INTERRUPTS(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm volatile ( "DSB SY \n" \
+ "ISB SY \n" ); \
+ portENABLE_INTERRUPTS(); \
+}
/* Hardware specifics used when sanity checking the configuration. */
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portBIT_0_SET ( ( uint8_t ) 0x01 )
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portBIT_0_SET ( ( uint8_t ) 0x01 )
/*-----------------------------------------------------------*/
@@ -143,381 +143,376 @@
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
- * variable has to be stored as part of the task context and must be initialised to
- * a non zero value to ensure interrupts don't inadvertently become unmasked before
- * the scheduler starts. As it is stored as part of the task context it will
- * automatically be set to 0 when the first task is started. */
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
volatile uint64_t ullCriticalNesting = 9999ULL;
/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
- * then floating point context must be saved and restored for the task. */
+then floating point context must be saved and restored for the task. */
uint64_t ullPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint64_t ullPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
- * if the nesting depth is 0. */
+if the nesting depth is 0. */
uint64_t ullPortInterruptNesting = 0;
/* Used in the ASM code. */
-__attribute__( ( used ) ) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First all the general purpose registers. */
- pxTopOfStack--;
- *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
- pxTopOfStack--;
+ /* First all the general purpose registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
+ pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSTATE;
- pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSTATE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
+ pxTopOfStack--;
- /* The task will start with a critical nesting count of 0 as interrupts are
- * enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
- /* The task will start without a floating point context. A task that uses
- * the floating point hardware must call vPortTaskUsesFPU() before executing
- * any floating point instructions. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- uint32_t ulAPSR;
+uint32_t ulAPSR;
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
- volatile uint8_t ucMaxPriorityValue;
+ #if( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+ volatile uint8_t ucMaxPriorityValue;
- /* Determine how many priority bits are implemented in the GIC.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
+ /* Determine how many priority bits are implemented in the GIC.
- /* Determine the number of priority bits available. First write to
- * all possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+ Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+ /* Determine the number of priority bits available. First write to
+ all possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
- /* Shift to the least significant bits. */
- while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
- {
- ucMaxPriorityValue >>= ( uint8_t ) 0x01;
- }
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
- /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
- * value. */
+ /* Shift to the least significant bits. */
+ while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+ {
+ ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+ }
- configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
+ /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+ value. */
+
+ configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* conifgASSERT_DEFINED */
+ /* Restore the clobbered interrupt priority register to its original
+ value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* conifgASSERT_DEFINED */
- /* At the time of writing, the BSP only supports EL3. */
- __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
+ /* At the time of writing, the BSP only supports EL3. */
+ __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
- #if defined( GUEST )
- #warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
- configASSERT( ulAPSR == portEL1 );
+#if defined( GUEST )
+ #warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
+ configASSERT( ulAPSR == portEL1 );
+ if( ulAPSR == portEL1 )
+#else
+ configASSERT( ulAPSR == portEL3 );
+ if( ulAPSR == portEL3 )
+#endif
+ {
+ /* Only continue if the binary point value is set to its lowest possible
+ setting. See the comments in vPortValidateInterruptPriority() below for
+ more information. */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
- if( ulAPSR == portEL1 )
- #else
- configASSERT( ulAPSR == portEL3 );
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+ {
+ /* Interrupts are turned off in the CPU itself to ensure a tick does
+ not execute while the scheduler is being started. Interrupts are
+ automatically turned back on in the CPU when the first task starts
+ executing. */
+ portDISABLE_INTERRUPTS();
- if( ulAPSR == portEL3 )
- #endif
- {
- /* Only continue if the binary point value is set to its lowest possible
- * setting. See the comments in vPortValidateInterruptPriority() below for
- * more information. */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ /* Start the timer that generates the tick ISR. */
+ configSETUP_TICK_INTERRUPT();
- if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
- {
- /* Interrupts are turned off in the CPU itself to ensure a tick does
- * not execute while the scheduler is being started. Interrupts are
- * automatically turned back on in the CPU when the first task starts
- * executing. */
- portDISABLE_INTERRUPTS();
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
+ }
- /* Start the timer that generates the tick ISR. */
- configSETUP_TICK_INTERRUPT();
-
- /* Start the first task executing. */
- vPortRestoreTaskContext();
- }
- }
-
- return 0;
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( ullCriticalNesting == 1000ULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ullCriticalNesting == 1000ULL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- /* Mask interrupts up to the max syscall interrupt priority. */
- uxPortSetInterruptMask();
+ /* Mask interrupts up to the max syscall interrupt priority. */
+ uxPortSetInterruptMask();
- /* Now interrupts are disabled ullCriticalNesting can be accessed
- * directly. Increment ullCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ullCriticalNesting++;
+ /* Now interrupts are disabled ullCriticalNesting can be accessed
+ directly. Increment ullCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ullCriticalNesting++;
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( ullCriticalNesting == 1ULL )
- {
- configASSERT( ullPortInterruptNesting == 0 );
- }
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ullCriticalNesting == 1ULL )
+ {
+ configASSERT( ullPortInterruptNesting == 0 );
+ }
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ullCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- * exited. */
- ullCriticalNesting--;
+ if( ullCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ullCriticalNesting--;
- /* If the nesting level has reached zero then all interrupt
- * priorities must be re-enabled. */
- if( ullCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- * should be unmasked. */
- portCLEAR_INTERRUPT_MASK();
- }
- }
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ullCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portCLEAR_INTERRUPT_MASK();
+ }
+ }
}
/*-----------------------------------------------------------*/
void FreeRTOS_Tick_Handler( void )
{
- /* Must be the lowest possible priority. */
- #if !defined( QEMU )
- {
- configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
- }
- #endif
+ /* Must be the lowest possible priority. */
+ #if !defined( QEMU )
+ {
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+ }
+ #endif
- /* Interrupts should not be enabled before this point. */
- #if ( configASSERT_DEFINED == 1 )
- {
- uint32_t ulMaskBits;
+ /* Interrupts should not be enabled before this point. */
+ #if( configASSERT_DEFINED == 1 )
+ {
+ uint32_t ulMaskBits;
- __asm volatile ( "mrs %0, daif" : "=r" ( ulMaskBits )::"memory" );
- configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
- }
- #endif /* configASSERT_DEFINED */
+ __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );
+ configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
+ }
+ #endif /* configASSERT_DEFINED */
- /* Set interrupt mask before altering scheduler structures. The tick
- * handler runs at the lowest priority, so interrupts cannot already be masked,
- * so there is no need to save and restore the current mask value. It is
- * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
- * updated. */
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb sy \n"
- "isb sy \n"::: "memory" );
+ /* Set interrupt mask before altering scheduler structures. The tick
+ handler runs at the lowest priority, so interrupts cannot already be masked,
+ so there is no need to save and restore the current mask value. It is
+ necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+ updated. */
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb sy \n"
+ "isb sy \n" ::: "memory" );
- /* Ok to enable interrupts after the interrupt source has been cleared. */
- configCLEAR_TICK_INTERRUPT();
- portENABLE_INTERRUPTS();
+ /* Ok to enable interrupts after the interrupt source has been cleared. */
+ configCLEAR_TICK_INTERRUPT();
+ portENABLE_INTERRUPTS();
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ullPortYieldRequired = pdTRUE;
- }
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ullPortYieldRequired = pdTRUE;
+ }
- /* Ensure all interrupt priorities are active again. */
- portCLEAR_INTERRUPT_MASK();
+ /* Ensure all interrupt priorities are active again. */
+ portCLEAR_INTERRUPT_MASK();
}
/*-----------------------------------------------------------*/
void vPortTaskUsesFPU( void )
{
- /* A task is registering the fact that it needs an FPU context. Set the
- * FPU flag (which is saved as part of the task context). */
- ullPortTaskHasFPUContext = pdTRUE;
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ullPortTaskHasFPUContext = pdTRUE;
- /* Consider initialising the FPSR here - but probably not necessary in
- * AArch64. */
+ /* Consider initialising the FPSR here - but probably not necessary in
+ AArch64. */
}
/*-----------------------------------------------------------*/
void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
{
- if( uxNewMaskValue == pdFALSE )
- {
- portCLEAR_INTERRUPT_MASK();
- }
+ if( uxNewMaskValue == pdFALSE )
+ {
+ portCLEAR_INTERRUPT_MASK();
+ }
}
/*-----------------------------------------------------------*/
UBaseType_t uxPortSetInterruptMask( void )
{
- uint32_t ulReturn;
+uint32_t ulReturn;
- /* Interrupt in the CPU must be turned off while the ICCPMR is being
- * updated. */
- portDISABLE_INTERRUPTS();
+ /* Interrupt in the CPU must be turned off while the ICCPMR is being
+ updated. */
+ portDISABLE_INTERRUPTS();
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+ {
+ /* Interrupts were already masked. */
+ ulReturn = pdTRUE;
+ }
+ else
+ {
+ ulReturn = pdFALSE;
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb sy \n"
+ "isb sy \n" ::: "memory" );
+ }
+ portENABLE_INTERRUPTS();
- if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
- {
- /* Interrupts were already masked. */
- ulReturn = pdTRUE;
- }
- else
- {
- ulReturn = pdFALSE;
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb sy \n"
- "isb sy \n"::: "memory" );
- }
-
- portENABLE_INTERRUPTS();
-
- return ulReturn;
+ return ulReturn;
}
/*-----------------------------------------------------------*/
-#if ( configASSERT_DEFINED == 1 )
+#if( configASSERT_DEFINED == 1 )
- void vPortValidateInterruptPriority( void )
- {
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible. */
- configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+ void vPortValidateInterruptPriority( void )
+ {
+ /* The following assertion will fail if a service routine (ISR) for
+ an interrupt that has been assigned a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ function. ISR safe FreeRTOS API functions must *only* be called
+ from interrupts that have been assigned a priority at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
- /* Priority grouping: The interrupt controller (GIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * The priority grouping is configured by the GIC's binary point register
- * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
- * possible value (which may be above 0). */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
- }
+ Numerically low interrupt priority numbers represent logically high
+ interrupt priorities, therefore the priority of the interrupt must
+ be set to a value equal to or numerically *higher* than
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ FreeRTOS maintains separate thread and ISR API functions to ensure
+ interrupt entry is as fast and simple as possible. */
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+ /* Priority grouping: The interrupt controller (GIC) allows the bits
+ that define each interrupt's priority to be split between bits that
+ define the interrupt's pre-emption priority bits and bits that define
+ the interrupt's sub-priority. For simplicity all bits must be defined
+ to be pre-emption priority bits. The following assertion will fail if
+ this is not the case (if some bits represent a sub-priority).
+
+ The priority grouping is configured by the GIC's binary point register
+ (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
+ possible value (which may be above 0). */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ }
#endif /* configASSERT_DEFINED */
/*-----------------------------------------------------------*/
+
diff --git a/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/portable/GCC/ARM_CA53_64_BIT/portmacro.h
index 5da5f22..47c9248 100644
--- a/portable/GCC/ARM_CA53_64_BIT/portmacro.h
+++ b/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,169 +43,169 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE size_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE size_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef portBASE_TYPE BaseType_t;
- typedef uint64_t UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef uint64_t UBaseType_t;
- typedef uint64_t TickType_t;
- #define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
+typedef uint64_t TickType_t;
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 16
- #define portPOINTER_SIZE_TYPE uint64_t
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 16
+#define portPOINTER_SIZE_TYPE uint64_t
/*-----------------------------------------------------------*/
/* Task utilities. */
/* Called at the end of an ISR that can cause a context switch. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern uint64_t ullPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ullPortYieldRequired = pdTRUE; \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{ \
+extern uint64_t ullPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ullPortYieldRequired = pdTRUE; \
+ } \
+}
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
- #if defined( GUEST )
- #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
- #else
- #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
- #endif
-
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#if defined( GUEST )
+ #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
+#else
+ #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
+#endif
/*-----------------------------------------------------------
-* Critical section control
-*----------------------------------------------------------*/
+ * Critical section control
+ *----------------------------------------------------------*/
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern UBaseType_t uxPortSetInterruptMask( void );
- extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
- extern void vPortInstallFreeRTOSVectorTable( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern UBaseType_t uxPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
- #define portDISABLE_INTERRUPTS() \
- __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
- __asm volatile ( "DSB SY" ); \
- __asm volatile ( "ISB SY" );
+#define portDISABLE_INTERRUPTS() \
+ __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
+ __asm volatile ( "DSB SY" ); \
+ __asm volatile ( "ISB SY" );
- #define portENABLE_INTERRUPTS() \
- __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
- __asm volatile ( "DSB SY" ); \
- __asm volatile ( "ISB SY" );
+#define portENABLE_INTERRUPTS() \
+ __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
+ __asm volatile ( "DSB SY" ); \
+ __asm volatile ( "ISB SY" );
/* These macros do not globally disable/enable interrupts. They do mask off
- * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
- #define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not required for this port but included in case common demo code that uses these
- * macros is used. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
- * handler for whichever peripheral is used to generate the RTOS tick. */
- void FreeRTOS_Tick_Handler( void );
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- * before any floating point instructions are executed. */
- void vPortTaskUsesFPU( void );
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
- #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
- #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif /* configASSERT */
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif /* configASSERT */
- #define portNOP() __asm volatile ( "NOP" )
- #define portINLINE __inline
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
- #ifdef __cplusplus
- } /* extern C */
- #endif
+#ifdef __cplusplus
+ } /* extern C */
+#endif
/* The number of bits to shift for an interrupt priority is dependent on the
- * number of bits implemented by the interrupt controller. */
- #if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
- #else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
- #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
- #endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+#else
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
/* Interrupt controller access addresses. */
- #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
- #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
- #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
- #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
- #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
- #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
- #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
- #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
- #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
- #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
- #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
- #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/ARM_CA9/port.c b/portable/GCC/ARM_CA9/port.c
index e826b9f..a968c1e 100644
--- a/portable/GCC/ARM_CA9/port.c
+++ b/portable/GCC/ARM_CA9/port.c
@@ -33,123 +33,123 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
- #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
- #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#endif
/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
- * portmacro.h. */
+portmacro.h. */
#ifndef configCLEAR_TICK_INTERRUPT
- #define configCLEAR_TICK_INTERRUPT()
+ #define configCLEAR_TICK_INTERRUPT()
#endif
/* A critical section is exited when the critical section nesting count reaches
- * this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
- * (but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
- * floating point context after they have been created. A variable is stored as
- * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
- * does not have an FPU context, or any other value if the task does have an FPU
- * context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINTERRUPT_ENABLE_BIT ( 0x80UL )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINTERRUPT_ENABLE_BIT ( 0x80UL )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
- * point is zero. */
-#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
- * mode. */
-#define portAPSR_USER_MODE ( 0x10 )
+mode. */
+#define portAPSR_USER_MODE ( 0x10 )
/* The critical section macros only mask interrupts up to an application
- * determined priority level. Sometimes it is necessary to turn interrupt off in
- * the CPU itself before modifying certain hardware registers. */
-#define portCPU_IRQ_DISABLE() \
- __asm volatile ( "CPSID i" ::: "memory" ); \
- __asm volatile ( "DSB" ); \
- __asm volatile ( "ISB" );
+determined priority level. Sometimes it is necessary to turn interrupt off in
+the CPU itself before modifying certain hardware registers. */
+#define portCPU_IRQ_DISABLE() \
+ __asm volatile ( "CPSID i" ::: "memory" ); \
+ __asm volatile ( "DSB" ); \
+ __asm volatile ( "ISB" );
-#define portCPU_IRQ_ENABLE() \
- __asm volatile ( "CPSIE i" ::: "memory" ); \
- __asm volatile ( "DSB" ); \
- __asm volatile ( "ISB" );
+#define portCPU_IRQ_ENABLE() \
+ __asm volatile ( "CPSIE i" ::: "memory" ); \
+ __asm volatile ( "DSB" ); \
+ __asm volatile ( "ISB" );
/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK() \
- { \
- portCPU_IRQ_DISABLE(); \
- portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
- __asm volatile ( "DSB \n" \
- "ISB \n"); \
- portCPU_IRQ_ENABLE(); \
- }
+#define portCLEAR_INTERRUPT_MASK() \
+{ \
+ portCPU_IRQ_DISABLE(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm volatile ( "DSB \n" \
+ "ISB \n" ); \
+ portCPU_IRQ_ENABLE(); \
+}
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portBIT_0_SET ( ( uint8_t ) 0x01 )
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portBIT_0_SET ( ( uint8_t ) 0x01 )
/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/* The space on the stack required to hold the FPU registers. This is 32 64-bit
- * registers, plus a 32-bit status register. */
-#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
+registers, plus a 32-bit status register. */
+#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
/*-----------------------------------------------------------*/
@@ -183,393 +183,386 @@
* FPU registers to be saved on interrupt entry their IRQ handler must be
* called vApplicationIRQHandler().
*/
-void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak ) );
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
- * variable has to be stored as part of the task context and must be initialised to
- * a non zero value to ensure interrupts don't inadvertently become unmasked before
- * the scheduler starts. As it is stored as part of the task context it will
- * automatically be set to 0 when the first task is started. */
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
- * a floating point context must be saved and restored for the task. */
+a floating point context must be saved and restored for the task. */
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
volatile uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
- * if the nesting depth is 0. */
+if the nesting depth is 0. */
volatile uint32_t ulPortInterruptNesting = 0UL;
/* Used in the asm file. */
-__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro.
- *
- * The fist real value on the stack is the status register, which is set for
- * system mode, with interrupts enabled. A few NULLs are added first to ensure
- * GDB does not try decoding a non-existent return address. */
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro.
- if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
- {
- /* The task will start in THUMB mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ The fist real value on the stack is the status register, which is set for
+ system mode, with interrupts enabled. A few NULLs are added first to ensure
+ GDB does not try decoding a non-existent return address. */
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- pxTopOfStack--;
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+ {
+ /* The task will start in THUMB mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
- /* Next the return address, which in this case is the start of the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
+ pxTopOfStack--;
- /* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* Next the return address, which in this case is the start of the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
- /* The task will start with a critical nesting count of 0 as interrupts are
- * enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
+ /* Next all the registers other than the stack pointer. */
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- #if ( configUSE_TASK_FPU_SUPPORT == 1 )
- {
- /* The task will start without a floating point context. A task that
- * uses the floating point hardware must call vPortTaskUsesFPU() before
- * executing any floating point instructions. */
- pxTopOfStack--;
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
- }
- #elif ( configUSE_TASK_FPU_SUPPORT == 2 )
- {
- /* The task will start with a floating point context. Leave enough
- * space for the registers - and ensure they are initialised to 0. */
- pxTopOfStack -= portFPU_REGISTER_WORDS;
- memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
- *pxTopOfStack = pdTRUE;
- ulPortTaskHasFPUContext = pdTRUE;
- }
- #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
- {
- #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
- }
- #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+ #if( configUSE_TASK_FPU_SUPPORT == 1 )
+ {
+ /* The task will start without a floating point context. A task that
+ uses the floating point hardware must call vPortTaskUsesFPU() before
+ executing any floating point instructions. */
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ }
+ #elif( configUSE_TASK_FPU_SUPPORT == 2 )
+ {
+ /* The task will start with a floating point context. Leave enough
+ space for the registers - and ensure they are initialised to 0. */
+ pxTopOfStack -= portFPU_REGISTER_WORDS;
+ memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
- return pxTopOfStack;
+ pxTopOfStack--;
+ *pxTopOfStack = pdTRUE;
+ ulPortTaskHasFPUContext = pdTRUE;
+ }
+ #else
+ {
+ #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
+ }
+ #endif
+
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( ulPortInterruptNesting == ~0UL );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulPortInterruptNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- uint32_t ulAPSR;
+uint32_t ulAPSR;
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
- volatile uint8_t ucMaxPriorityValue;
+ #if( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+ volatile uint8_t ucMaxPriorityValue;
- /* Determine how many priority bits are implemented in the GIC.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
+ /* Determine how many priority bits are implemented in the GIC.
- /* Determine the number of priority bits available. First write to
- * all possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+ Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+ /* Determine the number of priority bits available. First write to
+ all possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
- /* Shift to the least significant bits. */
- while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
- {
- ucMaxPriorityValue >>= ( uint8_t ) 0x01;
- }
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
- /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
- * value. */
- configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+ /* Shift to the least significant bits. */
+ while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+ {
+ ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+ }
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* conifgASSERT_DEFINED */
+ /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+ value. */
+ configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+
+ /* Restore the clobbered interrupt priority register to its original
+ value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* conifgASSERT_DEFINED */
- /* Only continue if the CPU is not in User mode. The CPU must be in a
- * Privileged mode for the scheduler to start. */
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
- configASSERT( ulAPSR != portAPSR_USER_MODE );
+ /* Only continue if the CPU is not in User mode. The CPU must be in a
+ Privileged mode for the scheduler to start. */
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+ configASSERT( ulAPSR != portAPSR_USER_MODE );
- if( ulAPSR != portAPSR_USER_MODE )
- {
- /* Only continue if the binary point value is set to its lowest possible
- * setting. See the comments in vPortValidateInterruptPriority() below for
- * more information. */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ if( ulAPSR != portAPSR_USER_MODE )
+ {
+ /* Only continue if the binary point value is set to its lowest possible
+ setting. See the comments in vPortValidateInterruptPriority() below for
+ more information. */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
- if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
- {
- /* Interrupts are turned off in the CPU itself to ensure tick does
- * not execute while the scheduler is being started. Interrupts are
- * automatically turned back on in the CPU when the first task starts
- * executing. */
- portCPU_IRQ_DISABLE();
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+ {
+ /* Interrupts are turned off in the CPU itself to ensure tick does
+ not execute while the scheduler is being started. Interrupts are
+ automatically turned back on in the CPU when the first task starts
+ executing. */
+ portCPU_IRQ_DISABLE();
- /* Start the timer that generates the tick ISR. */
- configSETUP_TICK_INTERRUPT();
+ /* Start the timer that generates the tick ISR. */
+ configSETUP_TICK_INTERRUPT();
- /* Start the first task executing. */
- vPortRestoreTaskContext();
- }
- }
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
+ }
- /* Will only get here if vTaskStartScheduler() was called with the CPU in
- * a non-privileged mode or the binary point register was not set to its lowest
- * possible value. prvTaskExitError() is referenced to prevent a compiler
- * warning about it being defined but not referenced in the case that the user
- * defines their own exit address. */
- ( void ) prvTaskExitError;
- return 0;
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in
+ a non-privileged mode or the binary point register was not set to its lowest
+ possible value. prvTaskExitError() is referenced to prevent a compiler
+ warning about it being defined but not referenced in the case that the user
+ defines their own exit address. */
+ ( void ) prvTaskExitError;
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- /* Mask interrupts up to the max syscall interrupt priority. */
- ulPortSetInterruptMask();
+ /* Mask interrupts up to the max syscall interrupt priority. */
+ ulPortSetInterruptMask();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( ulCriticalNesting == 1 )
- {
- configASSERT( ulPortInterruptNesting == 0 );
- }
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ulCriticalNesting == 1 )
+ {
+ configASSERT( ulPortInterruptNesting == 0 );
+ }
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- * exited. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then all interrupt
- * priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- * should be unmasked. */
- portCLEAR_INTERRUPT_MASK();
- }
- }
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portCLEAR_INTERRUPT_MASK();
+ }
+ }
}
/*-----------------------------------------------------------*/
void FreeRTOS_Tick_Handler( void )
{
- /* Set interrupt mask before altering scheduler structures. The tick
- * handler runs at the lowest priority, so interrupts cannot already be masked,
- * so there is no need to save and restore the current mask value. It is
- * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
- * updated. */
- portCPU_IRQ_DISABLE();
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb \n"
- "isb \n"::: "memory" );
- portCPU_IRQ_ENABLE();
+ /* Set interrupt mask before altering scheduler structures. The tick
+ handler runs at the lowest priority, so interrupts cannot already be masked,
+ so there is no need to save and restore the current mask value. It is
+ necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+ updated. */
+ portCPU_IRQ_DISABLE();
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb \n"
+ "isb \n" ::: "memory" );
+ portCPU_IRQ_ENABLE();
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ulPortYieldRequired = pdTRUE;
- }
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ulPortYieldRequired = pdTRUE;
+ }
- /* Ensure all interrupt priorities are active again. */
- portCLEAR_INTERRUPT_MASK();
- configCLEAR_TICK_INTERRUPT();
+ /* Ensure all interrupt priorities are active again. */
+ portCLEAR_INTERRUPT_MASK();
+ configCLEAR_TICK_INTERRUPT();
}
/*-----------------------------------------------------------*/
-#if ( configUSE_TASK_FPU_SUPPORT != 2 )
+#if( configUSE_TASK_FPU_SUPPORT != 2 )
- void vPortTaskUsesFPU( void )
- {
- uint32_t ulInitialFPSCR = 0;
+ void vPortTaskUsesFPU( void )
+ {
+ uint32_t ulInitialFPSCR = 0;
- /* A task is registering the fact that it needs an FPU context. Set the
- * FPU flag (which is saved as part of the task context). */
- ulPortTaskHasFPUContext = pdTRUE;
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ulPortTaskHasFPUContext = pdTRUE;
- /* Initialise the floating point status register. */
- __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
- }
+ /* Initialise the floating point status register. */
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+ }
#endif /* configUSE_TASK_FPU_SUPPORT */
/*-----------------------------------------------------------*/
void vPortClearInterruptMask( uint32_t ulNewMaskValue )
{
- if( ulNewMaskValue == pdFALSE )
- {
- portCLEAR_INTERRUPT_MASK();
- }
+ if( ulNewMaskValue == pdFALSE )
+ {
+ portCLEAR_INTERRUPT_MASK();
+ }
}
/*-----------------------------------------------------------*/
uint32_t ulPortSetInterruptMask( void )
{
- uint32_t ulReturn;
+uint32_t ulReturn;
- /* Interrupt in the CPU must be turned off while the ICCPMR is being
- * updated. */
- portCPU_IRQ_DISABLE();
+ /* Interrupt in the CPU must be turned off while the ICCPMR is being
+ updated. */
+ portCPU_IRQ_DISABLE();
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+ {
+ /* Interrupts were already masked. */
+ ulReturn = pdTRUE;
+ }
+ else
+ {
+ ulReturn = pdFALSE;
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb \n"
+ "isb \n" ::: "memory" );
+ }
+ portCPU_IRQ_ENABLE();
- if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
- {
- /* Interrupts were already masked. */
- ulReturn = pdTRUE;
- }
- else
- {
- ulReturn = pdFALSE;
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb \n"
- "isb \n"::: "memory" );
- }
-
- portCPU_IRQ_ENABLE();
-
- return ulReturn;
+ return ulReturn;
}
/*-----------------------------------------------------------*/
-#if ( configASSERT_DEFINED == 1 )
+#if( configASSERT_DEFINED == 1 )
- void vPortValidateInterruptPriority( void )
- {
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible. */
- configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+ void vPortValidateInterruptPriority( void )
+ {
+ /* The following assertion will fail if a service routine (ISR) for
+ an interrupt that has been assigned a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ function. ISR safe FreeRTOS API functions must *only* be called
+ from interrupts that have been assigned a priority at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
- /* Priority grouping: The interrupt controller (GIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * The priority grouping is configured by the GIC's binary point register
- * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
- * possible value (which may be above 0). */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
- }
+ Numerically low interrupt priority numbers represent logically high
+ interrupt priorities, therefore the priority of the interrupt must
+ be set to a value equal to or numerically *higher* than
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ FreeRTOS maintains separate thread and ISR API functions to ensure
+ interrupt entry is as fast and simple as possible. */
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+ /* Priority grouping: The interrupt controller (GIC) allows the bits
+ that define each interrupt's priority to be split between bits that
+ define the interrupt's pre-emption priority bits and bits that define
+ the interrupt's sub-priority. For simplicity all bits must be defined
+ to be pre-emption priority bits. The following assertion will fail if
+ this is not the case (if some bits represent a sub-priority).
+
+ The priority grouping is configured by the GIC's binary point register
+ (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
+ possible value (which may be above 0). */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ }
#endif /* configASSERT_DEFINED */
/*-----------------------------------------------------------*/
void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
{
- ( void ) ulICCIAR;
- configASSERT( ( volatile void * ) NULL );
+ ( void ) ulICCIAR;
+ configASSERT( ( volatile void * ) NULL );
}
diff --git a/portable/GCC/ARM_CA9/portmacro.h b/portable/GCC/ARM_CA9/portmacro.h
index 9c6498a..c6d35d8 100644
--- a/portable/GCC/ARM_CA9/portmacro.h
+++ b/portable/GCC/ARM_CA9/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,166 +43,166 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Task utilities. */
/* Called at the end of an ISR that can cause a context switch. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{ \
+extern uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+}
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
- #define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
/*-----------------------------------------------------------
-* Critical section control
-*----------------------------------------------------------*/
+ * Critical section control
+ *----------------------------------------------------------*/
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern uint32_t ulPortSetInterruptMask( void );
- extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
- extern void vPortInstallFreeRTOSVectorTable( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
/* These macros do not globally disable/enable interrupts. They do mask off
- * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
- #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
- #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not required for this port but included in case common demo code that uses these
- * macros is used. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
- * handler for whichever peripheral is used to generate the RTOS tick. */
- void FreeRTOS_Tick_Handler( void );
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
- * created without an FPU context and must call vPortTaskUsesFPU() to give
- * themselves an FPU context before using any FPU instructions. If
- * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
- * by default. */
- #if ( configUSE_TASK_FPU_SUPPORT != 2 )
- void vPortTaskUsesFPU( void );
- #else
+created without an FPU context and must call vPortTaskUsesFPU() to give
+themselves an FPU context before using any FPU instructions. If
+configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
+by default. */
+#if( configUSE_TASK_FPU_SUPPORT != 2 )
+ void vPortTaskUsesFPU( void );
+#else
+ /* Each task has an FPU context already, so define this function away to
+ nothing to prevent it being called accidentally. */
+ #define vPortTaskUsesFPU()
+#endif
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-/* Each task has an FPU context already, so define this function away to
- * nothing to prevent it being called accidentally. */
- #define vPortTaskUsesFPU()
- #endif
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
- #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
- #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif /* configASSERT */
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif /* configASSERT */
- #define portNOP() __asm volatile ( "NOP" )
- #define portINLINE __inline
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
- #ifdef __cplusplus
- } /* extern C */
- #endif
+#ifdef __cplusplus
+ } /* extern C */
+#endif
/* The number of bits to shift for an interrupt priority is dependent on the
- * number of bits implemented by the interrupt controller. */
- #if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
- #else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
- #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
- #endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+#else
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
/* Interrupt controller access addresses. */
- #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
- #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
- #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
- #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
- #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
- #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
- #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
- #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
- #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
- #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
- #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
- #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 3f39bc3..9ee28cd 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -612,7 +612,7 @@
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
- #else /* if defined( __ARMCC_VERSION ) */
+ #else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
@@ -802,22 +802,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
- }
- #else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0 );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@@ -835,21 +835,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -882,12 +882,12 @@
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
- BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+ BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
- void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
{
/* Simulate the stack frame as it would be created by a context switch
@@ -1051,7 +1051,9 @@
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
+
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1079,8 +1081,8 @@
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
- if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
- ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
@@ -1089,7 +1091,7 @@
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 3f39bc3..4d483d4 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -55,13 +55,13 @@
* on the secure side. The following are the valid configuration seetings:
*
* 1. Run FreeRTOS on the Secure Side:
- * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
*
* 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
*
* 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
*/
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
@@ -612,7 +612,7 @@
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
- #else /* if defined( __ARMCC_VERSION ) */
+ #else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
@@ -802,22 +802,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
- }
- #else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0 );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@@ -835,21 +835,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -877,18 +877,20 @@
}
/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
- BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+ BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
- void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@@ -1051,7 +1053,9 @@
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
+
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1079,8 +1083,8 @@
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
- if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
- ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
@@ -1089,7 +1093,7 @@
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 3f39bc3..e0a0c7e 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -612,7 +612,7 @@
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
- #else /* if defined( __ARMCC_VERSION ) */
+ #else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
@@ -802,22 +802,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
- }
- #else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0 );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@@ -835,21 +835,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -877,18 +877,20 @@
}
/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
- BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+ BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
- void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@@ -1051,7 +1053,9 @@
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
+
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1079,8 +1083,8 @@
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
- if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
- ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
@@ -1089,7 +1093,7 @@
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 3f39bc3..151ea8b 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -612,7 +612,7 @@
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
- #else /* if defined( __ARMCC_VERSION ) */
+ #else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
@@ -802,22 +802,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
- }
- #else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0 );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@@ -835,21 +835,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -877,18 +877,20 @@
}
/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
- BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+ BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
- void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@@ -1051,7 +1053,9 @@
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
+
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1079,8 +1083,8 @@
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
- if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
- ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
@@ -1089,7 +1093,7 @@
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index af9b53e..34ce94e 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -360,14 +360,14 @@
" str r3, [r2] \n"/* Disable MPU. */
" \n"
" ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
- " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
" \n"
#if ( portTOTAL_NUM_REGIONS == 16 )
- " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
#endif /* portTOTAL_NUM_REGIONS == 16. */
" \n"
" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
@@ -584,14 +584,14 @@
" str r3, [r2] \n"/* Disable MPU. */
" \n"
" ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
- " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
" \n"
#if ( portTOTAL_NUM_REGIONS == 16 )
- " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
#endif /* portTOTAL_NUM_REGIONS == 16. */
" \n"
" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
@@ -941,10 +941,10 @@
* be set to a value equal to or numerically *higher* than
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
*
- * Interrupts that use the FreeRTOS API must not be left at their
- * default priority of zero as that is the highest possible priority,
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
* which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
- * and therefore also guaranteed to be invalid.
+ * and therefore also guaranteed to be invalid.
*
* FreeRTOS maintains separate thread and ISR API functions to ensure
* interrupt entry is as fast and simple as possible.
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index 4588dd2..7f247a2 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -27,11 +27,14 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,169 +47,170 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* MPU specific constants. */
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
+#define portUSING_MPU_WRAPPERS 1
+#define portPRIVILEGE_BIT ( 0x80000000UL )
- #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
- #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
- #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
- /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
- * Register (RASR). */
- #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
- #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
+#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
- /* MPU settings that can be overriden in FreeRTOSConfig.h. */
- #ifndef configTOTAL_MPU_REGIONS
- /* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
- #endif
+/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
+ * Register (RASR). */
+#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
+#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
- /*
- * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
- * memory type, and where necessary the cacheable and shareable properties
- * of the memory region.
- *
- * The TEX, C, and B bits together indicate the memory type of the region,
- * and:
- * - For Normal memory, the cacheable properties of the region.
- * - For Device memory, whether the region is shareable.
- *
- * For Normal memory regions, the S bit indicates whether the region is
- * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
- *
- * See the following two tables for setting TEX, S, C and B bits for
- * unprivileged flash, privileged flash and privileged RAM regions.
- *
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 1 | Device | Shared device | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 1 | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 011 | X | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
- | | | | | outer cacheability rules that must be exported on the | |
- | | | | | bus. See the table below for the cacheability policy | |
- | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
- +-----------------------------------------+----------------------------------------+
- | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
- +-----------------------------------------+----------------------------------------+
- | 00 | Non-cacheable |
- +-----------------------------------------+----------------------------------------+
- | 01 | Write-back, write and read allocate |
- +-----------------------------------------+----------------------------------------+
- | 10 | Write-through, no write allocate |
- +-----------------------------------------+----------------------------------------+
- | 11 | Write-back, no write allocate |
- +-----------------------------------------+----------------------------------------+
- */
+/*
+ * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
+ * memory type, and where necessary the cacheable and shareable properties
+ * of the memory region.
+ *
+ * The TEX, C, and B bits together indicate the memory type of the region,
+ * and:
+ * - For Normal memory, the cacheable properties of the region.
+ * - For Device memory, whether the region is shareable.
+ *
+ * For Normal memory regions, the S bit indicates whether the region is
+ * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
+ *
+ * See the following two tables for setting TEX, S, C and B bits for
+ * unprivileged flash, privileged flash and privileged RAM regions.
+ *
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 1 | Device | Shared device | Shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 1 | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 1 | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 1 | X | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 011 | X | X | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
+ | | | | | outer cacheability rules that must be exported on the | |
+ | | | | | bus. See the table below for the cacheability policy | |
+ | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ |
+ +-----------------------------------------+----------------------------------------+
+ | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
+ +-----------------------------------------+----------------------------------------+
+ | 00 | Non-cacheable |
+ +-----------------------------------------+----------------------------------------+
+ | 01 | Write-back, write and read allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 10 | Write-through, no write allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 11 | Write-back, no write allocate |
+ +-----------------------------------------+----------------------------------------+
+ */
- /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
- * region. */
- #ifndef configTEX_S_C_B_FLASH
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_FLASH ( 0x07UL )
- #endif
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
+ * region. */
+#ifndef configTEX_S_C_B_FLASH
+ /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+ #define configTEX_S_C_B_FLASH ( 0x07UL )
+#endif
- /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
- * region. */
- #ifndef configTEX_S_C_B_SRAM
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_SRAM ( 0x07UL )
- #endif
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
+ * region. */
+#ifndef configTEX_S_C_B_SRAM
+ /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+ #define configTEX_S_C_B_SRAM ( 0x07UL )
+#endif
- #define portUNPRIVILEGED_FLASH_REGION ( 0UL )
- #define portPRIVILEGED_FLASH_REGION ( 1UL )
- #define portPRIVILEGED_RAM_REGION ( 2UL )
- #define portGENERAL_PERIPHERALS_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
- #define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
- #define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
+#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
+#define portPRIVILEGED_FLASH_REGION ( 1UL )
+#define portPRIVILEGED_RAM_REGION ( 2UL )
+#define portGENERAL_PERIPHERALS_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
+#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
+#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
- #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
- typedef struct MPU_REGION_REGISTERS
- {
- uint32_t ulRegionBaseAddress;
- uint32_t ulRegionAttribute;
- } xMPU_REGION_REGISTERS;
+typedef struct MPU_REGION_REGISTERS
+{
+ uint32_t ulRegionBaseAddress;
+ uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
/* Plus 1 to create space for the stack region. */
- typedef struct MPU_SETTINGS
- {
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portDONT_DISCARD __attribute__( ( used ) )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* SVC numbers for various services. */
- #define portSVC_START_SCHEDULER 0
- #define portSVC_YIELD 1
- #define portSVC_RAISE_PRIVILEGE 2
+#define portSVC_START_SCHEDULER 0
+#define portSVC_YIELD 1
+#define portSVC_RAISE_PRIVILEGE 2
/* Scheduler utilities. */
- #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
- #define portYIELD_WITHIN_API() \
+#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD_WITHIN_API() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -217,178 +221,181 @@
__asm volatile ( "isb" ); \
}
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
- return ucReturn;
- }
+ return ucReturn;
+ }
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
/*-----------------------------------------------------------*/
- extern BaseType_t xIsPrivileged( void );
- extern void vResetPrivilege( void );
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+#define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
+#define portRESET_PRIVILEGE() vResetPrivilege()
/*-----------------------------------------------------------*/
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
}
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI;
-
- __asm volatile
- (
- " mov %0, %1 \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
- }
+ return xReturn;
+}
/*-----------------------------------------------------------*/
- portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+ uint32_t ulNewBASEPRI;
- __asm volatile
- (
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
+ __asm volatile
+ (
+ " mov %0, %1 \n"\
+ " msr basepri, %0 \n"\
+ " isb \n"\
+ " dsb \n"\
+ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
- }
/*-----------------------------------------------------------*/
- portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
- {
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
- }
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mrs %0, basepri \n"\
+ " mov %1, %2 \n"\
+ " msr basepri, %1 \n"\
+ " isb \n"\
+ " dsb \n"\
+ : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+
+ /* This return will not be reached but is necessary to prevent compiler
+ * warnings. */
+ return ulOriginalBASEPRI;
+}
/*-----------------------------------------------------------*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-
- #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */
- #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
- #endif
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+ __asm volatile
+ (
+ " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
+ );
+}
/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+
+#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+ #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */
+ #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
+#endif
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
+/* *INDENT-ON* */
#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CR5/port.c b/portable/GCC/ARM_CR5/port.c
index 0658218..0e62131 100644
--- a/portable/GCC/ARM_CR5/port.c
+++ b/portable/GCC/ARM_CR5/port.c
@@ -149,17 +149,18 @@
/* Adding the necessary stuff in order to be able to determine from C code wheter or not the IRQs are enabled at the processor level (not interrupt controller level) */
-#define GET_CPSR() ({u32 rval = 0U; \
- __asm__ __volatile__(\
- "mrs %0, cpsr\n"\
- : "=r" (rval)\
- );\
- rval;\
- })
+#define GET_CPSR() \
+ ( { u32 rval = 0U; \
+ __asm__ __volatile__ ( \
+ "mrs %0, cpsr\n"\
+ : "=r" ( rval ) \
+ ); \
+ rval; \
+ } )
-#define CPSR_IRQ_ENABLE_MASK 0x80U
+#define CPSR_IRQ_ENABLE_MASK 0x80U
-#define IS_IRQ_DISABLED() ({unsigned int val = 0; val = (GET_CPSR() & CPSR_IRQ_ENABLE_MASK) ? 1 : 0; val;})
+#define IS_IRQ_DISABLED() ( { unsigned int val = 0; val = ( GET_CPSR() & CPSR_IRQ_ENABLE_MASK ) ? 1 : 0; val; } )
/*-----------------------------------------------------------*/
/*
@@ -482,12 +483,12 @@
{
uint32_t ulReturn;
uint32_t wasIRQDisabled;
-
+
/* We keep track of if the IRQ are enabled in the CPU (as opposed to interrupts masked in the interrupt controller, like the intend of this function).
* This is very important because when the CPU is interrupted, among other things, the hardware clears the IRQ Enable bit in the CPSR of the IRQ CPU Mode in which
* we enter. */
wasIRQDisabled = IS_IRQ_DISABLED();
-
+
/* Interrupt in the CPU must be turned off while the ICCPMR is being
* updated. */
portCPU_IRQ_DISABLE();
@@ -505,18 +506,20 @@
"isb \n"::: "memory" );
}
- /* Just like this function returns a value of wether or not the interrupts where masked in the interrupt controller in order to avoid race condition when
+ /* Just like this function returns a value of wether or not the interrupts where masked in the interrupt controller in order to avoid race condition when
* calling its matching vPortClearInterruptMask function, we needed a 'wasIRQDisabled' variable holding the state of the IRQ Enable bit in the CPSR in order
- * to leave that bit in it's original state. Like mentioned above, hardware automatically clear the IRQEnable bit upon trapping into IRQ Mode, so the programmer
+ * to leave that bit in it's original state. Like mentioned above, hardware automatically clear the IRQEnable bit upon trapping into IRQ Mode, so the programmer
* cannot make assumption about it's state. Very rare, but very important race condition is avoided with this when this function is called in an ISR. The race
* condition in question was discovered when integrating tracealyzer code. Inside the function 'void vTaskSwitchContext( void )' in tasks.c, there is a macro 'traceTASK_SWITCHED_IN();'
- * which gets replaced by something when using the tracing capabilities. That macro protects some critical section with matching calls to 'ulPortSetInterruptMask'
+ * which gets replaced by something when using the tracing capabilities. That macro protects some critical section with matching calls to 'ulPortSetInterruptMask'
* and 'vPortClearInterruptMask'. At the time of calling those functions, the interrupt mask is not set in the interrupt controller, thus the only protecting barrier
- * against the CPU traping into recursive interrupt was the IRQ Enable bit in the CPSR. By not taking it into acount, the very code that protects the CPU against
- * critical section violation just enabled it to happen : A SysTick was waiting to happen, and calling 'portCPU_IRQ_ENABLE' would enable it to occur... Thus triggering a
+ * against the CPU traping into recursive interrupt was the IRQ Enable bit in the CPSR. By not taking it into acount, the very code that protects the CPU against
+ * critical section violation just enabled it to happen : A SysTick was waiting to happen, and calling 'portCPU_IRQ_ENABLE' would enable it to occur... Thus triggering a
* switch of context while already performing a switch context. */
- if(!wasIRQDisabled)
- portCPU_IRQ_ENABLE();
+ if( !wasIRQDisabled )
+ {
+ portCPU_IRQ_ENABLE();
+ }
return ulReturn;
}
diff --git a/portable/GCC/ARM_CRx_No_GIC/port.c b/portable/GCC/ARM_CRx_No_GIC/port.c
index a06fc75..3e791c5 100644
--- a/portable/GCC/ARM_CRx_No_GIC/port.c
+++ b/portable/GCC/ARM_CRx_No_GIC/port.c
@@ -33,50 +33,50 @@
#include "task.h"
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
+ #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
#endif
#ifndef configCLEAR_TICK_INTERRUPT
- #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
+ #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
#endif
/* A critical section is exited when the critical section nesting count reaches
- * this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* Tasks are not created with a floating point context, but can be given a
- * floating point context after they have been created. A variable is stored as
- * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
- * does not have an FPU context, or any other value if the task does have an FPU
- * context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
- * mode. */
-#define portAPSR_USER_MODE ( 0x10 )
+mode. */
+#define portAPSR_USER_MODE ( 0x10 )
/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/*-----------------------------------------------------------*/
@@ -95,229 +95,225 @@
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
- * variable has to be stored as part of the task context and must be initialised to
- * a non zero value to ensure interrupts don't inadvertently become unmasked before
- * the scheduler starts. As it is stored as part of the task context it will
- * automatically be set to 0 when the first task is started. */
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
- * a floating point context must be saved and restored for the task. */
+a floating point context must be saved and restored for the task. */
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
volatile uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
- * if the nesting depth is 0. */
+if the nesting depth is 0. */
volatile uint32_t ulPortInterruptNesting = 0UL;
/* Used in the asm file to clear an interrupt. */
-__attribute__( ( used ) ) const uint32_t ulICCEOIR = configEOI_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro.
- *
- * The fist real value on the stack is the status register, which is set for
- * system mode, with interrupts enabled. A few NULLs are added first to ensure
- * GDB does not try decoding a non-existent return address. */
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro.
- if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
- {
- /* The task will start in THUMB mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ The fist real value on the stack is the status register, which is set for
+ system mode, with interrupts enabled. A few NULLs are added first to ensure
+ GDB does not try decoding a non-existent return address. */
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- pxTopOfStack--;
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+ {
+ /* The task will start in THUMB mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
- /* Next the return address, which in this case is the start of the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
+ pxTopOfStack--;
- /* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* Next the return address, which in this case is the start of the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
- /* The task will start with a critical nesting count of 0 as interrupts are
- * enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
+ /* Next all the registers other than the stack pointer. */
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The task will start without a floating point context. A task that uses
- * the floating point hardware must call vPortTaskUsesFPU() before executing
- * any floating point instructions. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
- return pxTopOfStack;
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( ulPortInterruptNesting == ~0UL );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulPortInterruptNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- uint32_t ulAPSR;
+uint32_t ulAPSR;
- /* Only continue if the CPU is not in User mode. The CPU must be in a
- * Privileged mode for the scheduler to start. */
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
+ /* Only continue if the CPU is not in User mode. The CPU must be in a
+ Privileged mode for the scheduler to start. */
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+ configASSERT( ulAPSR != portAPSR_USER_MODE );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
- configASSERT( ulAPSR != portAPSR_USER_MODE );
+ if( ulAPSR != portAPSR_USER_MODE )
+ {
+ /* Start the timer that generates the tick ISR. */
+ portDISABLE_INTERRUPTS();
+ configSETUP_TICK_INTERRUPT();
- if( ulAPSR != portAPSR_USER_MODE )
- {
- /* Start the timer that generates the tick ISR. */
- portDISABLE_INTERRUPTS();
- configSETUP_TICK_INTERRUPT();
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
- /* Start the first task executing. */
- vPortRestoreTaskContext();
- }
-
- /* Will only get here if vTaskStartScheduler() was called with the CPU in
- * a non-privileged mode or the binary point register was not set to its lowest
- * possible value. prvTaskExitError() is referenced to prevent a compiler
- * warning about it being defined but not referenced in the case that the user
- * defines their own exit address. */
- ( void ) prvTaskExitError;
- return 0;
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in
+ a non-privileged mode or the binary point register was not set to its lowest
+ possible value. prvTaskExitError() is referenced to prevent a compiler
+ warning about it being defined but not referenced in the case that the user
+ defines their own exit address. */
+ ( void ) prvTaskExitError;
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- portDISABLE_INTERRUPTS();
+ portDISABLE_INTERRUPTS();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( ulCriticalNesting == 1 )
- {
- configASSERT( ulPortInterruptNesting == 0 );
- }
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ulCriticalNesting == 1 )
+ {
+ configASSERT( ulPortInterruptNesting == 0 );
+ }
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- * exited. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then all interrupt
- * priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- * should be unmasked. */
- portENABLE_INTERRUPTS();
- }
- }
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portENABLE_INTERRUPTS();
+ }
+ }
}
/*-----------------------------------------------------------*/
void FreeRTOS_Tick_Handler( void )
{
- uint32_t ulInterruptStatus;
+uint32_t ulInterruptStatus;
- ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ulPortYieldRequired = pdTRUE;
- }
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ulPortYieldRequired = pdTRUE;
+ }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
- configCLEAR_TICK_INTERRUPT();
+ configCLEAR_TICK_INTERRUPT();
}
/*-----------------------------------------------------------*/
void vPortTaskUsesFPU( void )
{
- uint32_t ulInitialFPSCR = 0;
+uint32_t ulInitialFPSCR = 0;
- /* A task is registering the fact that it needs an FPU context. Set the
- * FPU flag (which is saved as part of the task context). */
- ulPortTaskHasFPUContext = pdTRUE;
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ulPortTaskHasFPUContext = pdTRUE;
- /* Initialise the floating point status register. */
- __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
+ /* Initialise the floating point status register. */
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
}
/*-----------------------------------------------------------*/
+
+
diff --git a/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/portable/GCC/ARM_CRx_No_GIC/portmacro.h
index f8b41dc..e02c74f 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portmacro.h
+++ b/portable/GCC/ARM_CRx_No_GIC/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,141 +43,139 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Task utilities. */
/* Called at the end of an ISR that can cause a context switch. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern volatile uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{ \
+extern volatile uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+}
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
- #define portYIELD() \
- __asm volatile ( "SWI 0 \n"\
- "ISB "::: "memory" );
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0 \n" \
+ "ISB " ::: "memory" );
/*-----------------------------------------------------------
-* Critical section control
-*----------------------------------------------------------*/
+ * Critical section control
+ *----------------------------------------------------------*/
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern uint32_t ulPortSetInterruptMask( void );
- extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
- extern void vPortInstallFreeRTOSVectorTable( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
/* The I bit within the CPSR. */
- #define portINTERRUPT_ENABLE_BIT ( 1 << 7 )
+#define portINTERRUPT_ENABLE_BIT ( 1 << 7 )
/* In the absence of a priority mask register, these functions and macros
- * globally enable and disable interrupts. */
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
- #define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n"::: "memory" );
- #define portDISABLE_INTERRUPTS() \
- __asm volatile ( "CPSID i \n" \
- "DSB \n" \
- "ISB "::: "memory" );
+globally enable and disable interrupts. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ::: "memory" );
+#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \
+ "DSB \n" \
+ "ISB " ::: "memory" );
- __attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
- {
- volatile uint32_t ulCPSR;
+__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
+{
+volatile uint32_t ulCPSR;
- __asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR )::"memory" );
+ __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );
+ ulCPSR &= portINTERRUPT_ENABLE_BIT;
+ portDISABLE_INTERRUPTS();
+ return ulCPSR;
+}
- ulCPSR &= portINTERRUPT_ENABLE_BIT;
- portDISABLE_INTERRUPTS();
- return ulCPSR;
- }
-
- #define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) if( x == 0 ) portENABLE_INTERRUPTS()
+#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) if( x == 0 ) portENABLE_INTERRUPTS()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not required for this port but included in case common demo code that uses these
- * macros is used. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/* Prototype of the FreeRTOS tick handler. This must be installed as the
- * handler for whichever peripheral is used to generate the RTOS tick. */
- void FreeRTOS_Tick_Handler( void );
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- * before any floating point instructions are executed. */
- void vPortTaskUsesFPU( void );
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
- #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
- #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
- #define portNOP() __asm volatile ( "NOP" )
- #define portINLINE __inline
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
- #ifdef __cplusplus
- } /* extern C */
- #endif
+#ifdef __cplusplus
+ } /* extern C */
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/ATMega323/port.c b/portable/GCC/ATMega323/port.c
index 5bbf012..31e28b6 100644
--- a/portable/GCC/ATMega323/port.c
+++ b/portable/GCC/ATMega323/port.c
@@ -25,14 +25,14 @@
* 1 tab == 4 spaces!
*/
-/*
- *
- * Changes from V2.6.0
- *
- + AVR port - Replaced the inb() and outb() functions with direct memory
- + access. This allows the port to be built with the 20050414 build of
- + WinAVR.
- */
+/*
+
+Changes from V2.6.0
+
+ + AVR port - Replaced the inb() and outb() functions with direct memory
+ access. This allows the port to be built with the 20050414 build of
+ WinAVR.
+*/
#include <stdlib.h>
#include <avr/interrupt.h>
@@ -41,135 +41,135 @@
#include "task.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the AVR port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the AVR port.
+ *----------------------------------------------------------*/
/* Start tasks with interrupts enables. */
-#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
/* Hardware constants for timer 1. */
-#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 )
-#define portPRESCALE_64 ( ( uint8_t ) 0x03 )
-#define portCLOCK_PRESCALER ( ( uint32_t ) 64 )
-#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 )
+#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 )
+#define portPRESCALE_64 ( ( uint8_t ) 0x03 )
+#define portCLOCK_PRESCALER ( ( uint32_t ) 64 )
+#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 )
/*-----------------------------------------------------------*/
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/*-----------------------------------------------------------*/
-/*
+/*
* Macro to save all the general purpose registers, the save the stack pointer
- * into the TCB.
- *
- * The first thing we do is save the flags then disable interrupts. This is to
- * guard our stack against having a context switch interrupt after we have already
- * pushed the registers onto the stack - causing the 32 registers to be on the
- * stack twice.
- *
+ * into the TCB.
+ *
+ * The first thing we do is save the flags then disable interrupts. This is to
+ * guard our stack against having a context switch interrupt after we have already
+ * pushed the registers onto the stack - causing the 32 registers to be on the
+ * stack twice.
+ *
* r1 is set to zero as the compiler expects it to be thus, however some
- * of the math routines make use of R1.
- *
+ * of the math routines make use of R1.
+ *
* The interrupts will have been disabled during the call to portSAVE_CONTEXT()
- * so we need not worry about reading/writing to the stack pointer.
+ * so we need not worry about reading/writing to the stack pointer.
*/
-#define portSAVE_CONTEXT() \
- asm volatile ( "push r0 \n\t"\
- "in r0, __SREG__ \n\t"\
- "cli \n\t"\
- "push r0 \n\t"\
- "push r1 \n\t"\
- "clr r1 \n\t"\
- "push r2 \n\t"\
- "push r3 \n\t"\
- "push r4 \n\t"\
- "push r5 \n\t"\
- "push r6 \n\t"\
- "push r7 \n\t"\
- "push r8 \n\t"\
- "push r9 \n\t"\
- "push r10 \n\t"\
- "push r11 \n\t"\
- "push r12 \n\t"\
- "push r13 \n\t"\
- "push r14 \n\t"\
- "push r15 \n\t"\
- "push r16 \n\t"\
- "push r17 \n\t"\
- "push r18 \n\t"\
- "push r19 \n\t"\
- "push r20 \n\t"\
- "push r21 \n\t"\
- "push r22 \n\t"\
- "push r23 \n\t"\
- "push r24 \n\t"\
- "push r25 \n\t"\
- "push r26 \n\t"\
- "push r27 \n\t"\
- "push r28 \n\t"\
- "push r29 \n\t"\
- "push r30 \n\t"\
- "push r31 \n\t"\
- "lds r26, pxCurrentTCB \n\t"\
- "lds r27, pxCurrentTCB + 1 \n\t"\
- "in r0, 0x3d \n\t"\
- "st x+, r0 \n\t"\
- "in r0, 0x3e \n\t"\
- "st x+, r0 \n\t"\
- );
+#define portSAVE_CONTEXT() \
+ asm volatile ( "push r0 \n\t" \
+ "in r0, __SREG__ \n\t" \
+ "cli \n\t" \
+ "push r0 \n\t" \
+ "push r1 \n\t" \
+ "clr r1 \n\t" \
+ "push r2 \n\t" \
+ "push r3 \n\t" \
+ "push r4 \n\t" \
+ "push r5 \n\t" \
+ "push r6 \n\t" \
+ "push r7 \n\t" \
+ "push r8 \n\t" \
+ "push r9 \n\t" \
+ "push r10 \n\t" \
+ "push r11 \n\t" \
+ "push r12 \n\t" \
+ "push r13 \n\t" \
+ "push r14 \n\t" \
+ "push r15 \n\t" \
+ "push r16 \n\t" \
+ "push r17 \n\t" \
+ "push r18 \n\t" \
+ "push r19 \n\t" \
+ "push r20 \n\t" \
+ "push r21 \n\t" \
+ "push r22 \n\t" \
+ "push r23 \n\t" \
+ "push r24 \n\t" \
+ "push r25 \n\t" \
+ "push r26 \n\t" \
+ "push r27 \n\t" \
+ "push r28 \n\t" \
+ "push r29 \n\t" \
+ "push r30 \n\t" \
+ "push r31 \n\t" \
+ "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "in r0, 0x3d \n\t" \
+ "st x+, r0 \n\t" \
+ "in r0, 0x3e \n\t" \
+ "st x+, r0 \n\t" \
+ );
-/*
+/*
* Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during
- * the context save so we can write to the stack pointer.
+ * the context save so we can write to the stack pointer.
*/
-#define portRESTORE_CONTEXT() \
- asm volatile ( "lds r26, pxCurrentTCB \n\t"\
- "lds r27, pxCurrentTCB + 1 \n\t"\
- "ld r28, x+ \n\t"\
- "out __SP_L__, r28 \n\t"\
- "ld r29, x+ \n\t"\
- "out __SP_H__, r29 \n\t"\
- "pop r31 \n\t"\
- "pop r30 \n\t"\
- "pop r29 \n\t"\
- "pop r28 \n\t"\
- "pop r27 \n\t"\
- "pop r26 \n\t"\
- "pop r25 \n\t"\
- "pop r24 \n\t"\
- "pop r23 \n\t"\
- "pop r22 \n\t"\
- "pop r21 \n\t"\
- "pop r20 \n\t"\
- "pop r19 \n\t"\
- "pop r18 \n\t"\
- "pop r17 \n\t"\
- "pop r16 \n\t"\
- "pop r15 \n\t"\
- "pop r14 \n\t"\
- "pop r13 \n\t"\
- "pop r12 \n\t"\
- "pop r11 \n\t"\
- "pop r10 \n\t"\
- "pop r9 \n\t"\
- "pop r8 \n\t"\
- "pop r7 \n\t"\
- "pop r6 \n\t"\
- "pop r5 \n\t"\
- "pop r4 \n\t"\
- "pop r3 \n\t"\
- "pop r2 \n\t"\
- "pop r1 \n\t"\
- "pop r0 \n\t"\
- "out __SREG__, r0 \n\t"\
- "pop r0 \n\t"\
- );
+#define portRESTORE_CONTEXT() \
+ asm volatile ( "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "ld r28, x+ \n\t" \
+ "out __SP_L__, r28 \n\t" \
+ "ld r29, x+ \n\t" \
+ "out __SP_H__, r29 \n\t" \
+ "pop r31 \n\t" \
+ "pop r30 \n\t" \
+ "pop r29 \n\t" \
+ "pop r28 \n\t" \
+ "pop r27 \n\t" \
+ "pop r26 \n\t" \
+ "pop r25 \n\t" \
+ "pop r24 \n\t" \
+ "pop r23 \n\t" \
+ "pop r22 \n\t" \
+ "pop r21 \n\t" \
+ "pop r20 \n\t" \
+ "pop r19 \n\t" \
+ "pop r18 \n\t" \
+ "pop r17 \n\t" \
+ "pop r16 \n\t" \
+ "pop r15 \n\t" \
+ "pop r14 \n\t" \
+ "pop r13 \n\t" \
+ "pop r12 \n\t" \
+ "pop r11 \n\t" \
+ "pop r10 \n\t" \
+ "pop r9 \n\t" \
+ "pop r8 \n\t" \
+ "pop r7 \n\t" \
+ "pop r6 \n\t" \
+ "pop r5 \n\t" \
+ "pop r4 \n\t" \
+ "pop r3 \n\t" \
+ "pop r2 \n\t" \
+ "pop r1 \n\t" \
+ "pop r0 \n\t" \
+ "out __SREG__, r0 \n\t" \
+ "pop r0 \n\t" \
+ );
/*-----------------------------------------------------------*/
@@ -179,147 +179,145 @@
static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
-/*
- * See header file for description.
+/*
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint16_t usAddress;
+uint16_t usAddress;
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging. */
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
- *pxTopOfStack = 0x11;
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
- pxTopOfStack--;
+ *pxTopOfStack = 0x11;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack--;
- /* Simulate how the stack would look after a call to vPortYield() generated by
- * the compiler. */
+ /* Simulate how the stack would look after a call to vPortYield() generated by
+ the compiler. */
- /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
- /* The start of the task code will be popped off the stack last, so place
- * it on first. */
- usAddress = ( uint16_t ) pxCode;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
+ /* The start of the task code will be popped off the stack last, so place
+ it on first. */
+ usAddress = ( uint16_t ) pxCode;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
- usAddress >>= 8;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
+ usAddress >>= 8;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
- /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
- * portSAVE_CONTEXT places the flags on the stack immediately after r0
- * to ensure the interrupts get disabled as soon as possible, and so ensuring
- * the stack use is minimal should a context switch interrupt occur. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = portFLAGS_INT_ENABLED;
- pxTopOfStack--;
+ /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+ portSAVE_CONTEXT places the flags on the stack immediately after r0
+ to ensure the interrupts get disabled as soon as possible, and so ensuring
+ the stack use is minimal should a context switch interrupt occur. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = portFLAGS_INT_ENABLED;
+ pxTopOfStack--;
- /* Now the remaining registers. The compiler expects R1 to be 0. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x16; /* R16 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x17; /* R17 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
- pxTopOfStack--;
+ /* Now the remaining registers. The compiler expects R1 to be 0. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R16 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R17 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
+ pxTopOfStack--;
- /* Place the parameter on the stack in the expected location. */
- usAddress = ( uint16_t ) pvParameters;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
+ /* Place the parameter on the stack in the expected location. */
+ usAddress = ( uint16_t ) pvParameters;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
- usAddress >>= 8;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
+ usAddress >>= 8;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x28; /* R28 Y */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x29; /* R29 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x28; /* R28 Y */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x29; /* R29 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
+ pxTopOfStack--;
- /*lint +e950 +e611 +e923 */
+ /*lint +e950 +e611 +e923 */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup the hardware to generate the tick. */
- prvSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. */
+ prvSetupTimerInterrupt();
- /* Restore the context of the first task that is going to run. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the first task that is going to run. */
+ portRESTORE_CONTEXT();
- /* Simulate a function call end as generated by the compiler. We will now
- * jump to the start of the task the context of which we have just restored. */
- asm volatile ( "ret" );
+ /* Simulate a function call end as generated by the compiler. We will now
+ jump to the start of the task the context of which we have just restored. */
+ asm volatile ( "ret" );
- /* Should not get here. */
- return pdTRUE;
+ /* Should not get here. */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the AVR port will get stopped. If required simply
- * disable the tick interrupt here. */
+ /* It is unlikely that the AVR port will get stopped. If required simply
+ disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@@ -327,36 +325,34 @@
* Manual context switch. The first thing we do is save the registers so we
* can use a naked attribute.
*/
-void vPortYield( void ) __attribute__( ( naked ) );
+void vPortYield( void ) __attribute__ ( ( naked ) );
void vPortYield( void )
{
- portSAVE_CONTEXT();
- vTaskSwitchContext();
- portRESTORE_CONTEXT();
+ portSAVE_CONTEXT();
+ vTaskSwitchContext();
+ portRESTORE_CONTEXT();
- asm volatile ( "ret" );
+ asm volatile ( "ret" );
}
/*-----------------------------------------------------------*/
/*
- * Context switch function used by the tick. This must be identical to
+ * Context switch function used by the tick. This must be identical to
* vPortYield() from the call to vTaskSwitchContext() onwards. The only
* difference from vPortYield() is the tick count is incremented as the
* call comes from the tick ISR.
*/
-void vPortYieldFromTick( void ) __attribute__( ( naked ) );
+void vPortYieldFromTick( void ) __attribute__ ( ( naked ) );
void vPortYieldFromTick( void )
{
- portSAVE_CONTEXT();
+ portSAVE_CONTEXT();
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+ portRESTORE_CONTEXT();
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- portRESTORE_CONTEXT();
-
- asm volatile ( "ret" );
+ asm volatile ( "ret" );
}
/*-----------------------------------------------------------*/
@@ -365,63 +361,66 @@
*/
static void prvSetupTimerInterrupt( void )
{
- uint32_t ulCompareMatch;
- uint8_t ucHighByte, ucLowByte;
+uint32_t ulCompareMatch;
+uint8_t ucHighByte, ucLowByte;
- /* Using 16bit timer 1 to generate the tick. Correct fuses must be
- * selected for the configCPU_CLOCK_HZ clock. */
+ /* Using 16bit timer 1 to generate the tick. Correct fuses must be
+ selected for the configCPU_CLOCK_HZ clock. */
- ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
- /* We only have 16 bits so have to scale to get our required tick rate. */
- ulCompareMatch /= portCLOCK_PRESCALER;
+ /* We only have 16 bits so have to scale to get our required tick rate. */
+ ulCompareMatch /= portCLOCK_PRESCALER;
- /* Adjust for correct value. */
- ulCompareMatch -= ( uint32_t ) 1;
+ /* Adjust for correct value. */
+ ulCompareMatch -= ( uint32_t ) 1;
- /* Setup compare match value for compare match A. Interrupts are disabled
- * before this is called so we need not worry here. */
- ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
- ulCompareMatch >>= 8;
- ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
- OCR1AH = ucHighByte;
- OCR1AL = ucLowByte;
+ /* Setup compare match value for compare match A. Interrupts are disabled
+ before this is called so we need not worry here. */
+ ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+ ulCompareMatch >>= 8;
+ ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+ OCR1AH = ucHighByte;
+ OCR1AL = ucLowByte;
- /* Setup clock source and compare match behaviour. */
- ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
- TCCR1B = ucLowByte;
+ /* Setup clock source and compare match behaviour. */
+ ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
+ TCCR1B = ucLowByte;
- /* Enable the interrupt - this is okay as interrupt are currently globally
- * disabled. */
- ucLowByte = TIMSK;
- ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
- TIMSK = ucLowByte;
+ /* Enable the interrupt - this is okay as interrupt are currently globally
+ disabled. */
+ ucLowByte = TIMSK;
+ ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+ TIMSK = ucLowByte;
}
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 1
-/*
- * Tick ISR for preemptive scheduler. We can use a naked attribute as
- * the context is saved at the start of vPortYieldFromTick(). The tick
- * count is incremented after the context is saved.
- */
- void SIG_OUTPUT_COMPARE1A( void ) __attribute__( ( signal, naked ) );
- void SIG_OUTPUT_COMPARE1A( void )
- {
- vPortYieldFromTick();
- asm volatile ( "reti" );
- }
+ /*
+ * Tick ISR for preemptive scheduler. We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick(). The tick
+ * count is incremented after the context is saved.
+ */
+ void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal, naked ) );
+ void SIG_OUTPUT_COMPARE1A( void )
+ {
+ vPortYieldFromTick();
+ asm volatile ( "reti" );
+ }
#else
-/*
- * Tick ISR for the cooperative scheduler. All this does is increment the
- * tick count. We don't need to switch context, this can only be done by
- * manual calls to taskYIELD();
- */
- void SIG_OUTPUT_COMPARE1A( void ) __attribute__( ( signal ) );
- void SIG_OUTPUT_COMPARE1A( void )
- {
- xTaskIncrementTick();
- }
-#endif /* if configUSE_PREEMPTION == 1 */
+ /*
+ * Tick ISR for the cooperative scheduler. All this does is increment the
+ * tick count. We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+ void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal ) );
+ void SIG_OUTPUT_COMPARE1A( void )
+ {
+ xTaskIncrementTick();
+ }
+#endif
+
+
+
diff --git a/portable/GCC/ATMega323/portmacro.h b/portable/GCC/ATMega323/portmacro.h
index 90b34c7..f43e78e 100644
--- a/portable/GCC/ATMega323/portmacro.h
+++ b/portable/GCC/ATMega323/portmacro.h
@@ -26,18 +26,18 @@
*/
/*
- * Changes from V1.2.3
- *
- + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
- + base 16.
- */
+Changes from V1.2.3
+
+ + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
+ base 16.
+*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -50,59 +50,58 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT int
- #define portSTACK_TYPE uint8_t
- #define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
- typedef portSTACK_TYPE StackType_t;
- typedef signed char BaseType_t;
- typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Critical section management. */
- #define portENTER_CRITICAL() \
- asm volatile ( "in __tmp_reg__, __SREG__"::); \
- asm volatile ( "cli" ::); \
- asm volatile ( "push __tmp_reg__"::)
+#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \
+ asm volatile ( "cli" :: ); \
+ asm volatile ( "push __tmp_reg__" :: )
- #define portEXIT_CRITICAL() \
- asm volatile ( "pop __tmp_reg__"::); \
- asm volatile ( "out __SREG__, __tmp_reg__"::)
+#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \
+ asm volatile ( "out __SREG__, __tmp_reg__" :: )
- #define portDISABLE_INTERRUPTS() asm volatile ( "cli" ::);
- #define portENABLE_INTERRUPTS() asm volatile ( "sei" ::);
+#define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: );
+#define portENABLE_INTERRUPTS() asm volatile ( "sei" :: );
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 1
- #define portNOP() asm volatile ( "nop" );
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 1
+#define portNOP() asm volatile ( "nop" );
/*-----------------------------------------------------------*/
/* Kernel utilities. */
- extern void vPortYield( void ) __attribute__( ( naked ) );
- #define portYIELD() vPortYield()
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD() vPortYield()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/AVR32_UC3/port.c b/portable/GCC/AVR32_UC3/port.c
index fbb33f3..2f5592a 100644
--- a/portable/GCC/AVR32_UC3/port.c
+++ b/portable/GCC/AVR32_UC3/port.c
@@ -1,5 +1,4 @@
/*This file has been prepared for Doxygen automatic documentation generation.*/
-
/*! \file *********************************************************************
*
* \brief FreeRTOS port source for AVR32 UC3.
@@ -53,23 +52,23 @@
/* AVR32 UC3 includes. */
#include <avr32/io.h>
#include "gpio.h"
-#if ( configTICK_USE_TC == 1 )
- #include "tc.h"
+#if( configTICK_USE_TC==1 )
+ #include "tc.h"
#endif
/* Constants required to setup the task context. */
-#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 )
+#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 )
/* Each task maintains its own critical nesting variable. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
volatile uint32_t ulCriticalNesting = 9999UL;
-#if ( configTICK_USE_TC == 0 )
- static void prvScheduleNextTick( void );
+#if( configTICK_USE_TC==0 )
+ static void prvScheduleNextTick( void );
#else
- static void prvClearTcInt( void );
+ static void prvClearTcInt( void );
#endif
/* Setup the timer to generate the tick interrupts. */
@@ -85,53 +84,55 @@
* vectors are not compatible with the SCALL management in the current FreeRTOS
* port. More low-level initializations are besides added here.
*/
-void _init_startup( void )
+void _init_startup(void)
{
- /* Import the Exception Vector Base Address. */
- extern void _evba;
+ /* Import the Exception Vector Base Address. */
+ extern void _evba;
- #if configHEAP_INIT
- extern void __heap_start__;
- extern void __heap_end__;
- BaseType_t * pxMem;
- #endif
+ #if configHEAP_INIT
+ extern void __heap_start__;
+ extern void __heap_end__;
+ BaseType_t *pxMem;
+ #endif
- /* Load the Exception Vector Base Address in the corresponding system register. */
- Set_system_register( AVR32_EVBA, ( int ) &_evba );
+ /* Load the Exception Vector Base Address in the corresponding system register. */
+ Set_system_register( AVR32_EVBA, ( int ) &_evba );
- /* Enable exceptions. */
- ENABLE_ALL_EXCEPTIONS();
+ /* Enable exceptions. */
+ ENABLE_ALL_EXCEPTIONS();
- /* Initialize interrupt handling. */
- INTC_init_interrupts();
+ /* Initialize interrupt handling. */
+ INTC_init_interrupts();
- #if configHEAP_INIT
- /* Initialize the heap used by malloc. */
- for( pxMem = &__heap_start__; pxMem < ( BaseType_t * ) &__heap_end__; )
- {
- *pxMem++ = 0xA5A5A5A5;
- }
- #endif
+ #if configHEAP_INIT
- /* Give the used CPU clock frequency to Newlib, so it can work properly. */
- set_cpu_hz( configCPU_CLOCK_HZ );
+ /* Initialize the heap used by malloc. */
+ for( pxMem = &__heap_start__; pxMem < ( BaseType_t * )&__heap_end__; )
+ {
+ *pxMem++ = 0xA5A5A5A5;
+ }
- /* Code section present if and only if the debug trace is activated. */
- #if configDBG
- {
- static const gpio_map_t DBG_USART_GPIO_MAP =
- {
- { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
- { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
- };
+ #endif
- /* Initialize the USART used for the debug trace with the configured parameters. */
- set_usart_base( ( void * ) configDBG_USART );
- gpio_enable_module( DBG_USART_GPIO_MAP,
- sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) );
- usart_init( configDBG_USART_BAUDRATE );
- }
- #endif /* if configDBG */
+ /* Give the used CPU clock frequency to Newlib, so it can work properly. */
+ set_cpu_hz( configCPU_CLOCK_HZ );
+
+ /* Code section present if and only if the debug trace is activated. */
+ #if configDBG
+ {
+ static const gpio_map_t DBG_USART_GPIO_MAP =
+ {
+ { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
+ { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
+ };
+
+ /* Initialize the USART used for the debug trace with the configured parameters. */
+ set_usart_base( ( void * ) configDBG_USART );
+ gpio_enable_module( DBG_USART_GPIO_MAP,
+ sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
+ usart_init( configDBG_USART_BAUDRATE );
+ }
+ #endif
}
/*-----------------------------------------------------------*/
@@ -154,9 +155,9 @@
* safe section as memory allocation management uses global data.
* See the aforementioned details.
*/
-void __malloc_lock( struct _reent * ptr )
+void __malloc_lock(struct _reent *ptr)
{
- vTaskSuspendAll();
+ vTaskSuspendAll();
}
/*
@@ -164,96 +165,92 @@
* a safe section as memory allocation management uses global data.
* See the aforementioned details.
*/
-void __malloc_unlock( struct _reent * ptr )
+void __malloc_unlock(struct _reent *ptr)
{
- xTaskResumeAll();
+ xTaskResumeAll();
}
/*-----------------------------------------------------------*/
/* Added as there is no such function in FreeRTOS. */
-void * pvPortRealloc( void * pv,
- size_t xWantedSize )
+void *pvPortRealloc( void *pv, size_t xWantedSize )
{
- void * pvReturn;
+void *pvReturn;
- vTaskSuspendAll();
- {
- pvReturn = realloc( pv, xWantedSize );
- }
- xTaskResumeAll();
+ vTaskSuspendAll();
+ {
+ pvReturn = realloc( pv, xWantedSize );
+ }
+ xTaskResumeAll();
- return pvReturn;
+ return pvReturn;
}
/*-----------------------------------------------------------*/
/* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick. */
-
+simply increment the system tick. */
/* The preemptive scheduler is defined as "naked" as the full context is saved
- * on entry as part of the context switch. */
-__attribute__( ( __naked__ ) ) static void vTick( void )
+on entry as part of the context switch. */
+__attribute__((__naked__)) static void vTick( void )
{
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT_OS_INT();
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT_OS_INT();
- #if ( configTICK_USE_TC == 1 )
- /* Clear the interrupt flag. */
- prvClearTcInt();
- #else
+ #if( configTICK_USE_TC==1 )
+ /* Clear the interrupt flag. */
+ prvClearTcInt();
+ #else
+ /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+ clock cycles from now. */
+ prvScheduleNextTick();
+ #endif
- /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
- * clock cycles from now. */
- prvScheduleNextTick();
- #endif
+ /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+ calls in a critical section . */
+ portENTER_CRITICAL();
+ xTaskIncrementTick();
+ portEXIT_CRITICAL();
- /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
- * calls in a critical section . */
- portENTER_CRITICAL();
- xTaskIncrementTick();
- portEXIT_CRITICAL();
-
- /* Restore the context of the "elected task". */
- portRESTORE_CONTEXT_OS_INT();
+ /* Restore the context of the "elected task". */
+ portRESTORE_CONTEXT_OS_INT();
}
/*-----------------------------------------------------------*/
-__attribute__( ( __naked__ ) ) void SCALLYield( void )
+__attribute__((__naked__)) void SCALLYield( void )
{
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT_SCALL();
- vTaskSwitchContext();
- portRESTORE_CONTEXT_SCALL();
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT_SCALL();
+ vTaskSwitchContext();
+ portRESTORE_CONTEXT_SCALL();
}
/*-----------------------------------------------------------*/
/* The code generated by the GCC compiler uses the stack in different ways at
- * different optimisation levels. The interrupt flags can therefore not always
- * be saved to the stack. Instead the critical section nesting level is stored
- * in a variable, which is then saved as part of the stack context. */
-__attribute__( ( __noinline__ ) ) void vPortEnterCritical( void )
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+__attribute__((__noinline__)) void vPortEnterCritical( void )
{
- /* Disable interrupts */
- portDISABLE_INTERRUPTS();
+ /* Disable interrupts */
+ portDISABLE_INTERRUPTS();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
-__attribute__( ( __noinline__ ) ) void vPortExitCritical( void )
+__attribute__((__noinline__)) void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- ulCriticalNesting--;
-
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable all interrupt/exception. */
- portENABLE_INTERRUPTS();
- }
- }
+ if(ulCriticalNesting > portNO_CRITICAL_NESTING)
+ {
+ ulCriticalNesting--;
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable all interrupt/exception. */
+ portENABLE_INTERRUPTS();
+ }
+ }
}
/*-----------------------------------------------------------*/
@@ -263,182 +260,176 @@
*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* When the task starts, it will expect to find the function parameter in R12. */
- pxTopOfStack--;
- *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */
- *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */
- *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */
- *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */
- *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */
- *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */
- *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
- *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */
- *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */
- *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */
- *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */
- *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */
- *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */
- *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
- *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
- *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
+ /* When the task starts, it will expect to find the function parameter in R12. */
+ pxTopOfStack--;
+ *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */
+ *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */
+ *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */
+ *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */
+ *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */
+ *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */
+ *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
+ *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */
+ *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */
+ *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */
+ *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */
+ *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */
+ *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */
+ *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
+ *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
+ *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- portRESTORE_CONTEXT();
+ /* Start the first task. */
+ portRESTORE_CONTEXT();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the AVR32 port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the AVR32 port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
- * clock cycles from now. */
-#if ( configTICK_USE_TC == 0 )
- static void prvScheduleFirstTick( void )
- {
- uint32_t lCycles;
+clock cycles from now. */
+#if( configTICK_USE_TC==0 )
+ static void prvScheduleFirstTick(void)
+ {
+ uint32_t lCycles;
- lCycles = Get_system_register( AVR32_COUNT );
- lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+ lCycles = Get_system_register(AVR32_COUNT);
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+ // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+ // generation feature does not get disabled.
+ if(0 == lCycles)
+ {
+ lCycles++;
+ }
+ Set_system_register(AVR32_COMPARE, lCycles);
+ }
+
+ __attribute__((__noinline__)) static void prvScheduleNextTick(void)
+ {
+ uint32_t lCycles, lCount;
- /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
- /* generation feature does not get disabled. */
- if( 0 == lCycles )
- {
- lCycles++;
- }
-
- Set_system_register( AVR32_COMPARE, lCycles );
- }
-
- __attribute__( ( __noinline__ ) ) static void prvScheduleNextTick( void )
- {
- uint32_t lCycles, lCount;
-
- lCycles = Get_system_register( AVR32_COMPARE );
- lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
-
- /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
- /* generation feature does not get disabled. */
- if( 0 == lCycles )
- {
- lCycles++;
- }
-
- lCount = Get_system_register( AVR32_COUNT );
-
- if( lCycles < lCount )
- { /* We missed a tick, recover for the next. */
- lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
- }
-
- Set_system_register( AVR32_COMPARE, lCycles );
- }
-#else /* if ( configTICK_USE_TC == 0 ) */
- __attribute__( ( __noinline__ ) ) static void prvClearTcInt( void )
- {
- AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr;
- }
-#endif /* if ( configTICK_USE_TC == 0 ) */
+ lCycles = Get_system_register(AVR32_COMPARE);
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+ // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+ // generation feature does not get disabled.
+ if(0 == lCycles)
+ {
+ lCycles++;
+ }
+ lCount = Get_system_register(AVR32_COUNT);
+ if( lCycles < lCount )
+ { // We missed a tick, recover for the next.
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+ }
+ Set_system_register(AVR32_COMPARE, lCycles);
+ }
+#else
+ __attribute__((__noinline__)) static void prvClearTcInt(void)
+ {
+ AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
+ }
+#endif
/*-----------------------------------------------------------*/
/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void )
+static void prvSetupTimerInterrupt(void)
{
- #if ( configTICK_USE_TC == 1 )
- volatile avr32_tc_t * tc = &AVR32_TC;
+#if( configTICK_USE_TC==1 )
- /* Options for waveform genration. */
- tc_waveform_opt_t waveform_opt =
- {
- .channel = configTICK_TC_CHANNEL, /* Channel selection. */
+ volatile avr32_tc_t *tc = &AVR32_TC;
- .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
- .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
- .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
- .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
+ // Options for waveform genration.
+ tc_waveform_opt_t waveform_opt =
+ {
+ .channel = configTICK_TC_CHANNEL, /* Channel selection. */
- .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
- .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
- .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
- .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
+ .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
+ .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
+ .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
+ .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
- .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode without automatic trigger on RC compare. */
- .enetrg = FALSE, /* External event trigger enable. */
- .eevt = 0, /* External event selection. */
- .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
- .cpcdis = FALSE, /* Counter disable when RC compare. */
- .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
+ .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
+ .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
+ .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
+ .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
- .burst = FALSE, /* Burst signal selection. */
- .clki = FALSE, /* Clock inversion. */
- .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
- };
+ .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
+ .enetrg = FALSE, /* External event trigger enable. */
+ .eevt = 0, /* External event selection. */
+ .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
+ .cpcdis = FALSE, /* Counter disable when RC compare. */
+ .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
- tc_interrupt_t tc_interrupt =
- {
- .etrgs = 0,
- .ldrbs = 0,
- .ldras = 0,
- .cpcs = 1,
- .cpbs = 0,
- .cpas = 0,
- .lovrs = 0,
- .covfs = 0,
- };
- #endif /* if ( configTICK_USE_TC == 1 ) */
+ .burst = FALSE, /* Burst signal selection. */
+ .clki = FALSE, /* Clock inversion. */
+ .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
+ };
- /* Disable all interrupt/exception. */
- portDISABLE_INTERRUPTS();
+ tc_interrupt_t tc_interrupt =
+ {
+ .etrgs=0,
+ .ldrbs=0,
+ .ldras=0,
+ .cpcs =1,
+ .cpbs =0,
+ .cpas =0,
+ .lovrs=0,
+ .covfs=0,
+ };
- /* Register the compare interrupt handler to the interrupt controller and
- * enable the compare interrupt. */
+#endif
- #if ( configTICK_USE_TC == 1 )
- {
- INTC_register_interrupt( &vTick, configTICK_TC_IRQ, INT0 );
+ /* Disable all interrupt/exception. */
+ portDISABLE_INTERRUPTS();
- /* Initialize the timer/counter. */
- tc_init_waveform( tc, &waveform_opt );
+ /* Register the compare interrupt handler to the interrupt controller and
+ enable the compare interrupt. */
- /* Set the compare triggers.
- * Remember TC counter is 16-bits, so counting second is not possible!
- * That's why we configure it to count ms. */
- tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ );
+ #if( configTICK_USE_TC==1 )
+ {
+ INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
- tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
+ /* Initialize the timer/counter. */
+ tc_init_waveform(tc, &waveform_opt);
- /* Start the timer/counter. */
- tc_start( tc, configTICK_TC_CHANNEL );
- }
- #else /* if ( configTICK_USE_TC == 1 ) */
- {
- INTC_register_interrupt( &vTick, AVR32_CORE_COMPARE_IRQ, INT0 );
- prvScheduleFirstTick();
- }
- #endif /* if ( configTICK_USE_TC == 1 ) */
+ /* Set the compare triggers.
+ Remember TC counter is 16-bits, so counting second is not possible!
+ That's why we configure it to count ms. */
+ tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
+
+ tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
+
+ /* Start the timer/counter. */
+ tc_start(tc, configTICK_TC_CHANNEL);
+ }
+ #else
+ {
+ INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
+ prvScheduleFirstTick();
+ }
+ #endif
}
diff --git a/portable/GCC/AVR32_UC3/portmacro.h b/portable/GCC/AVR32_UC3/portmacro.h
index f672004..c4de32b 100644
--- a/portable/GCC/AVR32_UC3/portmacro.h
+++ b/portable/GCC/AVR32_UC3/portmacro.h
@@ -1,5 +1,4 @@
/*This file has been prepared for Doxygen automatic documentation generation.*/
-
/*! \file *********************************************************************
*
* \brief FreeRTOS port source for AVR32 UC3.
@@ -42,7 +41,7 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
@@ -53,62 +52,62 @@
* These settings should not be altered.
*-----------------------------------------------------------
*/
- #include <avr32/io.h>
- #include "intc.h"
- #include "compiler.h"
+#include <avr32/io.h>
+#include "intc.h"
+#include "compiler.h"
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #define TASK_DELAY_MS( x ) ( ( x ) / portTICK_PERIOD_MS )
- #define TASK_DELAY_S( x ) ( ( x ) * 1000 / portTICK_PERIOD_MS )
- #define TASK_DELAY_MIN( x ) ( ( x ) * 60 * 1000 / portTICK_PERIOD_MS )
+#define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS )
+#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS )
+#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS )
- #define configTICK_TC_IRQ ATPASTE2( AVR32_TC_IRQ, configTICK_TC_CHANNEL )
+#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 4
- #define portNOP() { __asm__ __volatile__ ( "nop" ); }
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() {__asm__ __volatile__ ("nop");}
/*-----------------------------------------------------------*/
/*-----------------------------------------------------------*/
/* INTC-specific. */
- #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
- #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
+#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
+#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
- #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
- #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
+#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
+#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
- #define DISABLE_INT_LEVEL( int_lev ) Disable_interrupt_level( int_lev )
- #define ENABLE_INT_LEVEL( int_lev ) Enable_interrupt_level( int_lev )
+#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
+#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
/*
@@ -124,33 +123,32 @@
* SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
* which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
*/
- #if configDBG
- #define portDBG_TRACE( ... ) \
- { \
- fputs( __FILE__ ":" ASTRINGZ( __LINE__ ) ": ", stdout ); \
- printf( __VA_ARGS__ ); \
- fputs( "\r\n", stdout ); \
- }
- #else
- #define portDBG_TRACE( ... )
- #endif
+#if configDBG
+#define portDBG_TRACE(...) \
+{\
+ fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
+ printf(__VA_ARGS__);\
+ fputs("\r\n", stdout);\
+}
+#else
+#define portDBG_TRACE(...)
+#endif
/* Critical section management. */
- #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
- #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
+#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
+#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
/* Added as there is no such function in FreeRTOS. */
- extern void * pvPortRealloc( void * pv,
- size_t xSize );
+extern void *pvPortRealloc( void *pv, size_t xSize );
/*-----------------------------------------------------------*/
@@ -159,44 +157,44 @@
/*
* Restore Context for cases other than INTi.
*/
- #define portRESTORE_CONTEXT() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- __asm__ __volatile__ ( \
- /* Set SP to point to new stack */ \
- "mov r8, LO(%[pxCurrentTCB]) \n\t"\
- "orh r8, HI(%[pxCurrentTCB]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "ld.w sp, r0[0] \n\t"\
- \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t"\
- "mov r8, LO(%[ulCriticalNesting]) \n\t"\
- "orh r8, HI(%[ulCriticalNesting]) \n\t"\
- "st.w r8[0], r0 \n\t"\
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- /* R0-R7 should not be used below this line */ \
- /* Skip PC and SR (will do it at the end) */ \
- "sub sp, -2*4 \n\t"\
- /* Restore R8..R12 and LR */ \
- "ldm sp++, r8-r12, lr \n\t"\
- /* Restore SR */ \
- "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
- "mtsr %[SR], r0 \n\t"\
- /* Restore r0 */ \
- "ld.w r0, sp[-9*4] \n\t"\
- /* Restore PC */ \
- "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
- : \
- :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
- [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
- [ SR ] "i" ( AVR32_SR ) \
- ); \
- }
+#define portRESTORE_CONTEXT() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ __asm__ __volatile__ ( \
+ /* Set SP to point to new stack */ \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0] \n\t"\
+ \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t"\
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ /* R0-R7 should not be used below this line */ \
+ /* Skip PC and SR (will do it at the end) */ \
+ "sub sp, -2*4 \n\t"\
+ /* Restore R8..R12 and LR */ \
+ "ldm sp++, r8-r12, lr \n\t"\
+ /* Restore SR */ \
+ "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
+ "mtsr %[SR], r0 \n\t"\
+ /* Restore r0 */ \
+ "ld.w r0, sp[-9*4] \n\t"\
+ /* Restore PC */ \
+ "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting), \
+ [pxCurrentTCB] "i" (&pxCurrentTCB), \
+ [SR] "i" (AVR32_SR) \
+ ); \
+}
/*
@@ -207,174 +205,174 @@
* are not the same between INT0..3 exceptions and the scall exception.
*/
-/* Task context stack layout: */
-/* R8 (*) */
-/* R9 (*) */
-/* R10 (*) */
-/* R11 (*) */
-/* R12 (*) */
-/* R14/LR (*) */
-/* R15/PC (*) */
-/* SR (*) */
-/* R0 */
-/* R1 */
-/* R2 */
-/* R3 */
-/* R4 */
-/* R5 */
-/* R6 */
-/* R7 */
-/* ulCriticalNesting */
-/* (*) automatically done for INT0..INT3, but not for SCALL */
+// Task context stack layout:
+ // R8 (*)
+ // R9 (*)
+ // R10 (*)
+ // R11 (*)
+ // R12 (*)
+ // R14/LR (*)
+ // R15/PC (*)
+ // SR (*)
+ // R0
+ // R1
+ // R2
+ // R3
+ // R4
+ // R5
+ // R6
+ // R7
+ // ulCriticalNesting
+// (*) automatically done for INT0..INT3, but not for SCALL
/*
* The ISR used for the scheduler tick depends on whether the cooperative or
* the preemptive scheduler is being used.
*/
- #if configUSE_PREEMPTION == 0
+#if configUSE_PREEMPTION == 0
/*
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
*/
- #define portSAVE_CONTEXT_OS_INT() \
- { \
- /* Save R0..R7 */ \
- __asm__ __volatile__ ( "stm --sp, r0-r7" ); \
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context save. */ \
- }
+#define portSAVE_CONTEXT_OS_INT() \
+{ \
+ /* Save R0..R7 */ \
+ __asm__ __volatile__ ("stm --sp, r0-r7"); \
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context save. */ \
+}
/*
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
*/
- #define portRESTORE_CONTEXT_OS_INT() \
- { \
- __asm__ __volatile__ ( \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7\n\t" \
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context restore. */ \
- "rete" \
- ); \
- }
+#define portRESTORE_CONTEXT_OS_INT() \
+{ \
+ __asm__ __volatile__ ( \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7\n\t" \
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context restore. */ \
+ "rete" \
+ ); \
+}
- #else /* if configUSE_PREEMPTION == 0 */
+#else
/*
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
*/
- #define portSAVE_CONTEXT_OS_INT() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- /* When we come here */ \
- /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
- \
- __asm__ __volatile__ ( \
- /* Save R0..R7 */ \
- "stm --sp, r0-r7 \n\t"\
- \
- /* Save ulCriticalNesting variable - R0 is overwritten */ \
- "mov r8, LO(%[ulCriticalNesting])\n\t" \
- "orh r8, HI(%[ulCriticalNesting])\n\t" \
- "ld.w r0, r8[0] \n\t"\
- "st.w --sp, r0 \n\t"\
- \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case we don't want to do a task switch because we don't know what the stack */ \
- /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
- /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
- /* will just be restoring the interrupt handler, no way!!! */ \
- /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
- "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
- "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
- "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
- "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
- \
- /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
- /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
- /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
- /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
- /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
- "mov r8, LO(%[pxCurrentTCB])\n\t" \
- "orh r8, HI(%[pxCurrentTCB])\n\t" \
- "ld.w r0, r8[0]\n\t" \
- "st.w r0[0], sp\n" \
- \
- "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
- : \
- :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
- [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
- [ LINE ] "i" ( __LINE__ ) \
- ); \
- }
+#define portSAVE_CONTEXT_OS_INT() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* When we come here */ \
+ /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
+ \
+ __asm__ __volatile__ ( \
+ /* Save R0..R7 */ \
+ "stm --sp, r0-r7 \n\t"\
+ \
+ /* Save ulCriticalNesting variable - R0 is overwritten */ \
+ "mov r8, LO(%[ulCriticalNesting])\n\t" \
+ "orh r8, HI(%[ulCriticalNesting])\n\t" \
+ "ld.w r0, r8[0] \n\t"\
+ "st.w --sp, r0 \n\t"\
+ \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case we don't want to do a task switch because we don't know what the stack */ \
+ /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
+ /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
+ /* will just be restoring the interrupt handler, no way!!! */ \
+ /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
+ "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
+ "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
+ "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
+ "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
+ \
+ /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
+ /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
+ /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
+ /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
+ /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
+ "mov r8, LO(%[pxCurrentTCB])\n\t" \
+ "orh r8, HI(%[pxCurrentTCB])\n\t" \
+ "ld.w r0, r8[0]\n\t" \
+ "st.w r0[0], sp\n" \
+ \
+ "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting), \
+ [pxCurrentTCB] "i" (&pxCurrentTCB), \
+ [LINE] "i" (__LINE__) \
+ ); \
+}
/*
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
*/
- #define portRESTORE_CONTEXT_OS_INT() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case we don't want to do a task switch because we don't know what the stack */ \
- /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
- /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
- /* will just be restoring the interrupt handler, no way!!! */ \
- __asm__ __volatile__ ( \
- "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
- "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
- "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
- "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
- : \
- :[ LINE ] "i" ( __LINE__ ) \
- ); \
- \
- /* Else */ \
- /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
- /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
- portENTER_CRITICAL(); \
- vTaskSwitchContext(); \
- portEXIT_CRITICAL(); \
- \
- /* Restore all registers */ \
- \
- __asm__ __volatile__ ( \
- /* Set SP to point to new stack */ \
- "mov r8, LO(%[pxCurrentTCB]) \n\t"\
- "orh r8, HI(%[pxCurrentTCB]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "ld.w sp, r0[0] \n"\
- \
- "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
- \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t"\
- "mov r8, LO(%[ulCriticalNesting]) \n\t"\
- "orh r8, HI(%[ulCriticalNesting]) \n\t"\
- "st.w r8[0], r0 \n\t"\
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- /* Now, the stack should be R8..R12, LR, PC and SR */ \
- "rete" \
- : \
- :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
- [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
- [ LINE ] "i" ( __LINE__ ) \
- ); \
- }
+#define portRESTORE_CONTEXT_OS_INT() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case we don't want to do a task switch because we don't know what the stack */ \
+ /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
+ /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
+ /* will just be restoring the interrupt handler, no way!!! */ \
+ __asm__ __volatile__ ( \
+ "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
+ "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
+ "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
+ "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
+ : \
+ : [LINE] "i" (__LINE__) \
+ ); \
+ \
+ /* Else */ \
+ /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
+ /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+ portENTER_CRITICAL(); \
+ vTaskSwitchContext(); \
+ portEXIT_CRITICAL(); \
+ \
+ /* Restore all registers */ \
+ \
+ __asm__ __volatile__ ( \
+ /* Set SP to point to new stack */ \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0] \n"\
+ \
+ "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
+ \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t" \
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ /* Now, the stack should be R8..R12, LR, PC and SR */ \
+ "rete" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting), \
+ [pxCurrentTCB] "i" (&pxCurrentTCB), \
+ [LINE] "i" (__LINE__) \
+ ); \
+}
- #endif /* if configUSE_PREEMPTION == 0 */
+#endif
/*
@@ -383,287 +381,287 @@
* NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
*
*/
- #define portSAVE_CONTEXT_SCALL() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
- /* If SR[M2:M0] == 001 */ \
- /* PC and SR are on the stack. */ \
- /* Else (other modes) */ \
- /* Nothing on the stack. */ \
- \
- /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
- /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
- /* in an interrupt|exception handler. */ \
- \
- __asm__ __volatile__ ( \
- /* in order to save R0-R7 */ \
- "sub sp, 6*4 \n\t"\
- /* Save R0..R7 */ \
- "stm --sp, r0-r7 \n\t"\
- \
- /* in order to save R8-R12 and LR */ \
- /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
- "sub r7, sp,-16*4 \n\t"\
- /* Copy PC and SR in other places in the stack. */ \
- "ld.w r0, r7[-2*4] \n\t"/* Read SR */\
- "st.w r7[-8*4], r0 \n\t"/* Copy SR */\
- "ld.w r0, r7[-1*4] \n\t"/* Read PC */\
- "st.w r7[-7*4], r0 \n\t"/* Copy PC */\
- \
- /* Save R8..R12 and LR on the stack. */ \
- "stm --r7, r8-r12, lr \n\t"\
- \
- /* Arriving here we have the following stack organizations: */ \
- /* R8..R12, LR, PC, SR, R0..R7. */ \
- \
- /* Now we can finalize the save. */ \
- \
- /* Save ulCriticalNesting variable - R0 is overwritten */ \
- "mov r8, LO(%[ulCriticalNesting]) \n\t"\
- "orh r8, HI(%[ulCriticalNesting]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "st.w --sp, r0" \
- : \
- :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
- ); \
- \
- /* Disable the its which may cause a context switch (i.e. cause a change of */ \
- /* pxCurrentTCB). */ \
- /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
- /* critical section because it is a global structure. */ \
- portENTER_CRITICAL(); \
- \
- /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
- __asm__ __volatile__ ( \
- "mov r8, LO(%[pxCurrentTCB]) \n\t"\
- "orh r8, HI(%[pxCurrentTCB]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "st.w r0[0], sp" \
- : \
- :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
- ); \
- }
+#define portSAVE_CONTEXT_SCALL() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
+ /* If SR[M2:M0] == 001 */ \
+ /* PC and SR are on the stack. */ \
+ /* Else (other modes) */ \
+ /* Nothing on the stack. */ \
+ \
+ /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
+ /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
+ /* in an interrupt|exception handler. */ \
+ \
+ __asm__ __volatile__ ( \
+ /* in order to save R0-R7 */ \
+ "sub sp, 6*4 \n\t"\
+ /* Save R0..R7 */ \
+ "stm --sp, r0-r7 \n\t"\
+ \
+ /* in order to save R8-R12 and LR */ \
+ /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
+ "sub r7, sp,-16*4 \n\t"\
+ /* Copy PC and SR in other places in the stack. */ \
+ "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
+ "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
+ "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
+ "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
+ \
+ /* Save R8..R12 and LR on the stack. */ \
+ "stm --r7, r8-r12, lr \n\t"\
+ \
+ /* Arriving here we have the following stack organizations: */ \
+ /* R8..R12, LR, PC, SR, R0..R7. */ \
+ \
+ /* Now we can finalize the save. */ \
+ \
+ /* Save ulCriticalNesting variable - R0 is overwritten */ \
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w --sp, r0" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting) \
+ ); \
+ \
+ /* Disable the its which may cause a context switch (i.e. cause a change of */ \
+ /* pxCurrentTCB). */ \
+ /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
+ /* critical section because it is a global structure. */ \
+ portENTER_CRITICAL(); \
+ \
+ /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
+ __asm__ __volatile__ ( \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w r0[0], sp" \
+ : \
+ : [pxCurrentTCB] "i" (&pxCurrentTCB) \
+ ); \
+}
/*
* portRESTORE_CONTEXT() for SupervisorCALL exception.
*/
- #define portRESTORE_CONTEXT_SCALL() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- /* Restore all registers */ \
- \
- /* Set SP to point to new stack */ \
- __asm__ __volatile__ ( \
- "mov r8, LO(%[pxCurrentTCB]) \n\t"\
- "orh r8, HI(%[pxCurrentTCB]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "ld.w sp, r0[0]" \
- : \
- :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
- ); \
- \
- /* Leave pxCurrentTCB variable access critical section */ \
- portEXIT_CRITICAL(); \
- \
- __asm__ __volatile__ ( \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t"\
- "mov r8, LO(%[ulCriticalNesting]) \n\t"\
- "orh r8, HI(%[ulCriticalNesting]) \n\t"\
- "st.w r8[0], r0 \n\t"\
- \
- /* skip PC and SR */ \
- /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
- "sub r7, sp, -10*4 \n\t"\
- /* Restore r8-r12 and LR */ \
- "ldm r7++, r8-r12, lr \n\t"\
- \
- /* RETS will take care of the extra PC and SR restore. */ \
- /* So, we have to prepare the stack for this. */ \
- "ld.w r0, r7[-8*4] \n\t"/* Read SR */\
- "st.w r7[-2*4], r0 \n\t"/* Copy SR */\
- "ld.w r0, r7[-7*4] \n\t"/* Read PC */\
- "st.w r7[-1*4], r0 \n\t"/* Copy PC */\
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- "sub sp, -6*4 \n\t"\
- \
- "rets" \
- : \
- :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
- ); \
- }
+#define portRESTORE_CONTEXT_SCALL() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* Restore all registers */ \
+ \
+ /* Set SP to point to new stack */ \
+ __asm__ __volatile__ ( \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0]" \
+ : \
+ : [pxCurrentTCB] "i" (&pxCurrentTCB) \
+ ); \
+ \
+ /* Leave pxCurrentTCB variable access critical section */ \
+ portEXIT_CRITICAL(); \
+ \
+ __asm__ __volatile__ ( \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t"\
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* skip PC and SR */ \
+ /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
+ "sub r7, sp, -10*4 \n\t"\
+ /* Restore r8-r12 and LR */ \
+ "ldm r7++, r8-r12, lr \n\t"\
+ \
+ /* RETS will take care of the extra PC and SR restore. */ \
+ /* So, we have to prepare the stack for this. */ \
+ "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
+ "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
+ "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
+ "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ "sub sp, -6*4 \n\t"\
+ \
+ "rets" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting) \
+ ); \
+}
/*
* The ISR used depends on whether the cooperative or
* the preemptive scheduler is being used.
*/
- #if configUSE_PREEMPTION == 0
+#if configUSE_PREEMPTION == 0
/*
* ISR entry and exit macros. These are only required if a task switch
* is required from the ISR.
*/
- #define portENTER_SWITCHING_ISR() \
- { \
- /* Save R0..R7 */ \
- __asm__ __volatile__ ( "stm --sp, r0-r7" ); \
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context save. */ \
- }
+#define portENTER_SWITCHING_ISR() \
+{ \
+ /* Save R0..R7 */ \
+ __asm__ __volatile__ ("stm --sp, r0-r7"); \
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context save. */ \
+}
/*
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
*/
- #define portEXIT_SWITCHING_ISR() \
- { \
- __asm__ __volatile__ ( \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context restore. */ \
- "rete" \
- ); \
- }
+#define portEXIT_SWITCHING_ISR() \
+{ \
+ __asm__ __volatile__ ( \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context restore. */ \
+ "rete" \
+ ); \
+}
- #else /* if configUSE_PREEMPTION == 0 */
+#else
/*
* ISR entry and exit macros. These are only required if a task switch
* is required from the ISR.
*/
- #define portENTER_SWITCHING_ISR() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- /* When we come here */ \
- /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
- \
- __asm__ __volatile__ ( \
- /* Save R0..R7 */ \
- "stm --sp, r0-r7 \n\t" \
- \
- /* Save ulCriticalNesting variable - R0 is overwritten */ \
- "mov r8, LO(%[ulCriticalNesting]) \n\t" \
- "orh r8, HI(%[ulCriticalNesting]) \n\t" \
- "ld.w r0, r8[0] \n\t" \
- "st.w --sp, r0 \n\t" \
- \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case we don't want to do a task switch because we don't know what the stack */ \
- /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
- /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
- /* will just be restoring the interrupt handler, no way!!! */ \
- /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
- "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */\
- "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */\
- "cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\
- "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \
- \
- /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
- "mov r8, LO(%[pxCurrentTCB]) \n\t" \
- "orh r8, HI(%[pxCurrentTCB]) \n\t" \
- "ld.w r0, r8[0] \n\t" \
- "st.w r0[0], sp \n" \
- \
- "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
- : \
- :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
- [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
- [ LINE ] "i" ( __LINE__ ) \
- ); \
- }
+#define portENTER_SWITCHING_ISR() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* When we come here */ \
+ /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
+ \
+ __asm__ __volatile__ ( \
+ /* Save R0..R7 */ \
+ "stm --sp, r0-r7 \n\t"\
+ \
+ /* Save ulCriticalNesting variable - R0 is overwritten */ \
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w --sp, r0 \n\t"\
+ \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case we don't want to do a task switch because we don't know what the stack */ \
+ /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
+ /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
+ /* will just be restoring the interrupt handler, no way!!! */ \
+ /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
+ "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
+ "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
+ "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+ "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
+ \
+ /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w r0[0], sp \n"\
+ \
+ "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting), \
+ [pxCurrentTCB] "i" (&pxCurrentTCB), \
+ [LINE] "i" (__LINE__) \
+ ); \
+}
/*
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
*/
- #define portEXIT_SWITCHING_ISR() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- __asm__ __volatile__ ( \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
- /* did not previously save SP in its TCB. */ \
- "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */\
- "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */\
- "cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\
- "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \
- \
- /* If a switch is required then we just need to call */ \
- /* vTaskSwitchContext() as the context has already been */ \
- /* saved. */ \
- "cp.w r12, 1 \n\t"/* Check if Switch context is required. */\
- "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
- : \
- :[ LINE ] "i" ( __LINE__ ) \
- ); \
- \
- /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
- portENTER_CRITICAL(); \
- vTaskSwitchContext(); \
- portEXIT_CRITICAL(); \
- \
- __asm__ __volatile__ ( \
- "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t" \
- /* Restore the context of which ever task is now the highest */ \
- /* priority that is ready to run. */ \
- \
- /* Restore all registers */ \
- \
- /* Set SP to point to new stack */ \
- "mov r8, LO(%[pxCurrentTCB]) \n\t" \
- "orh r8, HI(%[pxCurrentTCB]) \n\t" \
- "ld.w r0, r8[0] \n\t" \
- "ld.w sp, r0[0] \n" \
- \
- "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \
- \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t" \
- "mov r8, LO(%[ulCriticalNesting]) \n\t" \
- "orh r8, HI(%[ulCriticalNesting]) \n\t" \
- "st.w r8[0], r0 \n\t" \
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t" \
- \
- /* Now, the stack should be R8..R12, LR, PC and SR */ \
- "rete" \
- : \
- :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
- [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
- [ LINE ] "i" ( __LINE__ ) \
- ); \
- }
+#define portEXIT_SWITCHING_ISR() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ __asm__ __volatile__ ( \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
+ /* did not previously save SP in its TCB. */ \
+ "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
+ "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
+ "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+ "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\
+ \
+ /* If a switch is required then we just need to call */ \
+ /* vTaskSwitchContext() as the context has already been */ \
+ /* saved. */ \
+ "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
+ "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
+ : \
+ : [LINE] "i" (__LINE__) \
+ ); \
+ \
+ /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
+ portENTER_CRITICAL(); \
+ vTaskSwitchContext(); \
+ portEXIT_CRITICAL(); \
+ \
+ __asm__ __volatile__ ( \
+ "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\
+ /* Restore the context of which ever task is now the highest */ \
+ /* priority that is ready to run. */ \
+ \
+ /* Restore all registers */ \
+ \
+ /* Set SP to point to new stack */ \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0] \n"\
+ \
+ "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
+ \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t"\
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ /* Now, the stack should be R8..R12, LR, PC and SR */ \
+ "rete" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting), \
+ [pxCurrentTCB] "i" (&pxCurrentTCB), \
+ [LINE] "i" (__LINE__) \
+ ); \
+}
- #endif /* if configUSE_PREEMPTION == 0 */
+#endif
- #define portYIELD() { __asm__ __volatile__ ( "scall" ); }
+#define portYIELD() {__asm__ __volatile__ ("scall");}
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
diff --git a/portable/GCC/AVR_AVRDx/port.c b/portable/GCC/AVR_AVRDx/port.c
index 9d5cb96..0a995d8 100644
--- a/portable/GCC/AVR_AVRDx/port.c
+++ b/portable/GCC/AVR_AVRDx/port.c
@@ -34,18 +34,18 @@
#include "task.h"
/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the AVR port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
/* Start tasks with interrupts enables. */
-#define portFLAGS_INT_ENABLED ((StackType_t) 0x80)
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
/*-----------------------------------------------------------*/
/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
typedef void RTOS_TCB_t;
-extern volatile RTOS_TCB_t *volatile pxCurrentTCB;
+extern volatile RTOS_TCB_t * volatile pxCurrentTCB;
/*-----------------------------------------------------------*/
@@ -65,161 +65,163 @@
* so we need not worry about reading/writing to the stack pointer.
*/
-#define portSAVE_CONTEXT() \
- asm volatile("push r0 \n\t" \
- "in r0, __SREG__ \n\t" \
- "cli \n\t" \
- "push r0 \n\t" \
- "in r0, __RAMPZ__ \n\t" \
- "push r0 \n\t" \
- "push r1 \n\t" \
- "clr r1 \n\t" \
- "push r2 \n\t" \
- "push r3 \n\t" \
- "push r4 \n\t" \
- "push r5 \n\t" \
- "push r6 \n\t" \
- "push r7 \n\t" \
- "push r8 \n\t" \
- "push r9 \n\t" \
- "push r10 \n\t" \
- "push r11 \n\t" \
- "push r12 \n\t" \
- "push r13 \n\t" \
- "push r14 \n\t" \
- "push r15 \n\t" \
- "push r16 \n\t" \
- "push r17 \n\t" \
- "push r18 \n\t" \
- "push r19 \n\t" \
- "push r20 \n\t" \
- "push r21 \n\t" \
- "push r22 \n\t" \
- "push r23 \n\t" \
- "push r24 \n\t" \
- "push r25 \n\t" \
- "push r26 \n\t" \
- "push r27 \n\t" \
- "push r28 \n\t" \
- "push r29 \n\t" \
- "push r30 \n\t" \
- "push r31 \n\t" \
- "lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "in r0, __SP_L__ \n\t" \
- "st x+, r0 \n\t" \
- "in r0, __SP_H__ \n\t" \
- "st x+, r0 \n\t");
+#define portSAVE_CONTEXT() \
+ asm volatile ( "push r0 \n\t" \
+ "in r0, __SREG__ \n\t" \
+ "cli \n\t" \
+ "push r0 \n\t" \
+ "in r0, __RAMPZ__ \n\t" \
+ "push r0 \n\t" \
+ "push r1 \n\t" \
+ "clr r1 \n\t" \
+ "push r2 \n\t" \
+ "push r3 \n\t" \
+ "push r4 \n\t" \
+ "push r5 \n\t" \
+ "push r6 \n\t" \
+ "push r7 \n\t" \
+ "push r8 \n\t" \
+ "push r9 \n\t" \
+ "push r10 \n\t" \
+ "push r11 \n\t" \
+ "push r12 \n\t" \
+ "push r13 \n\t" \
+ "push r14 \n\t" \
+ "push r15 \n\t" \
+ "push r16 \n\t" \
+ "push r17 \n\t" \
+ "push r18 \n\t" \
+ "push r19 \n\t" \
+ "push r20 \n\t" \
+ "push r21 \n\t" \
+ "push r22 \n\t" \
+ "push r23 \n\t" \
+ "push r24 \n\t" \
+ "push r25 \n\t" \
+ "push r26 \n\t" \
+ "push r27 \n\t" \
+ "push r28 \n\t" \
+ "push r29 \n\t" \
+ "push r30 \n\t" \
+ "push r31 \n\t" \
+ "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "in r0, __SP_L__ \n\t" \
+ "st x+, r0 \n\t" \
+ "in r0, __SP_H__ \n\t" \
+ "st x+, r0 \n\t" );
/*
* Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during
* the context save so we can write to the stack pointer.
*/
-#define portRESTORE_CONTEXT() \
- asm volatile("lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "ld r28, x+ \n\t" \
- "out __SP_L__, r28 \n\t" \
- "ld r29, x+ \n\t" \
- "out __SP_H__, r29 \n\t" \
- "pop r31 \n\t" \
- "pop r30 \n\t" \
- "pop r29 \n\t" \
- "pop r28 \n\t" \
- "pop r27 \n\t" \
- "pop r26 \n\t" \
- "pop r25 \n\t" \
- "pop r24 \n\t" \
- "pop r23 \n\t" \
- "pop r22 \n\t" \
- "pop r21 \n\t" \
- "pop r20 \n\t" \
- "pop r19 \n\t" \
- "pop r18 \n\t" \
- "pop r17 \n\t" \
- "pop r16 \n\t" \
- "pop r15 \n\t" \
- "pop r14 \n\t" \
- "pop r13 \n\t" \
- "pop r12 \n\t" \
- "pop r11 \n\t" \
- "pop r10 \n\t" \
- "pop r9 \n\t" \
- "pop r8 \n\t" \
- "pop r7 \n\t" \
- "pop r6 \n\t" \
- "pop r5 \n\t" \
- "pop r4 \n\t" \
- "pop r3 \n\t" \
- "pop r2 \n\t" \
- "pop r1 \n\t" \
- "pop r0 \n\t" \
- "out __RAMPZ__, r0 \n\t" \
- "pop r0 \n\t" \
- "out __SREG__, r0 \n\t" \
- "pop r0 \n\t");
+#define portRESTORE_CONTEXT() \
+ asm volatile ( "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "ld r28, x+ \n\t" \
+ "out __SP_L__, r28 \n\t" \
+ "ld r29, x+ \n\t" \
+ "out __SP_H__, r29 \n\t" \
+ "pop r31 \n\t" \
+ "pop r30 \n\t" \
+ "pop r29 \n\t" \
+ "pop r28 \n\t" \
+ "pop r27 \n\t" \
+ "pop r26 \n\t" \
+ "pop r25 \n\t" \
+ "pop r24 \n\t" \
+ "pop r23 \n\t" \
+ "pop r22 \n\t" \
+ "pop r21 \n\t" \
+ "pop r20 \n\t" \
+ "pop r19 \n\t" \
+ "pop r18 \n\t" \
+ "pop r17 \n\t" \
+ "pop r16 \n\t" \
+ "pop r15 \n\t" \
+ "pop r14 \n\t" \
+ "pop r13 \n\t" \
+ "pop r12 \n\t" \
+ "pop r11 \n\t" \
+ "pop r10 \n\t" \
+ "pop r9 \n\t" \
+ "pop r8 \n\t" \
+ "pop r7 \n\t" \
+ "pop r6 \n\t" \
+ "pop r5 \n\t" \
+ "pop r4 \n\t" \
+ "pop r3 \n\t" \
+ "pop r2 \n\t" \
+ "pop r1 \n\t" \
+ "pop r0 \n\t" \
+ "out __RAMPZ__, r0 \n\t" \
+ "pop r0 \n\t" \
+ "out __SREG__, r0 \n\t" \
+ "pop r0 \n\t" );
/*-----------------------------------------------------------*/
/*
* Perform hardware setup to enable ticks from timer.
*/
-static void prvSetupTimerInterrupt(void);
+static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters)
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
{
uint16_t usAddress;
/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
/* Place a few bytes of known values on the bottom of the stack.
- This is just useful for debugging. Uncomment if needed. */
- // *pxTopOfStack = 0x11;
- // pxTopOfStack--;
- // *pxTopOfStack = 0x22;
- // pxTopOfStack--;
- // *pxTopOfStack = 0x33;
- // pxTopOfStack--;
+ * This is just useful for debugging. Uncomment if needed. */
+ /* *pxTopOfStack = 0x11; */
+ /* pxTopOfStack--; */
+ /* *pxTopOfStack = 0x22; */
+ /* pxTopOfStack--; */
+ /* *pxTopOfStack = 0x33; */
+ /* pxTopOfStack--; */
/* The start of the task code will be popped off the stack last, so place
- it on first. */
- usAddress = (uint16_t)pxCode;
- *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff);
+ * it on first. */
+ usAddress = ( uint16_t ) pxCode;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
usAddress >>= 8;
- *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff);
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
- portSAVE_CONTEXT places the flags on the stack immediately after r0
- to ensure the interrupts get disabled as soon as possible, and so ensuring
- the stack use is minimal should a context switch interrupt occur. */
- *pxTopOfStack = (StackType_t)0x00; /* R0 */
+ * portSAVE_CONTEXT places the flags on the stack immediately after r0
+ * to ensure the interrupts get disabled as soon as possible, and so ensuring
+ * the stack use is minimal should a context switch interrupt occur. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
pxTopOfStack--;
-
+
/* Now the remaining registers. The compiler expects R1 to be 0. */
- *pxTopOfStack = (StackType_t)0x00; /* R1 */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
/* Leave R2 - R23 untouched */
pxTopOfStack -= 23;
/* Place the parameter on the stack in the expected location. */
- usAddress = (uint16_t)pvParameters;
- *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff);
+ usAddress = ( uint16_t ) pvParameters;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
usAddress >>= 8;
- *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff);
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
/* Leave register R26 - R31 untouched */
pxTopOfStack -= 7;
@@ -230,7 +232,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t xPortStartScheduler(void)
+BaseType_t xPortStartScheduler( void )
{
/* Setup the hardware to generate the tick. */
prvSetupTimerInterrupt();
@@ -239,15 +241,15 @@
portRESTORE_CONTEXT();
/* Simulate a function call end as generated by the compiler. We will now
- jump to the start of the task the context of which we have just restored. */
- asm volatile("ret");
+ * jump to the start of the task the context of which we have just restored. */
+ asm volatile ( "ret" );
/* Should not get here. */
return pdTRUE;
}
/*-----------------------------------------------------------*/
-void vPortEndScheduler(void)
+void vPortEndScheduler( void )
{
/* vPortEndScheduler is not implemented in this port. */
}
@@ -257,13 +259,13 @@
* Manual context switch. The first thing we do is save the registers so we
* can use a naked attribute.
*/
-void vPortYield(void) __attribute__((naked));
-void vPortYield(void)
+void vPortYield( void ) __attribute__( ( naked ) );
+void vPortYield( void )
{
portSAVE_CONTEXT();
vTaskSwitchContext();
portRESTORE_CONTEXT();
- asm volatile("ret");
+ asm volatile ( "ret" );
}
/*-----------------------------------------------------------*/
@@ -271,13 +273,13 @@
* Manual context switch callable from ISRs. The first thing
* we do is save the registers so we can use a naked attribute.
*/
-void vPortYieldFromISR(void) __attribute__((naked));
-void vPortYieldFromISR(void)
+void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+void vPortYieldFromISR( void )
{
portSAVE_CONTEXT();
vTaskSwitchContext();
portRESTORE_CONTEXT();
- asm volatile("reti");
+ asm volatile ( "reti" );
}
/*-----------------------------------------------------------*/
@@ -287,24 +289,26 @@
* difference from vPortYield() is the tick count is incremented as the
* call comes from the tick ISR.
*/
-void vPortYieldFromTick(void) __attribute__((naked));
-void vPortYieldFromTick(void)
+void vPortYieldFromTick( void ) __attribute__( ( naked ) );
+void vPortYieldFromTick( void )
{
portSAVE_CONTEXT();
- if (xTaskIncrementTick() != pdFALSE) {
+
+ if( xTaskIncrementTick() != pdFALSE )
+ {
vTaskSwitchContext();
}
portRESTORE_CONTEXT();
- asm volatile("reti");
+ asm volatile ( "reti" );
}
/*-----------------------------------------------------------*/
/*
* Setup timer to generate a tick interrupt.
*/
-static void prvSetupTimerInterrupt(void)
+static void prvSetupTimerInterrupt( void )
{
TICK_init();
}
@@ -317,26 +321,26 @@
* the context is saved at the start of vPortYieldFromTick(). The tick
* count is incremented after the context is saved.
*/
-ISR(TICK_INT_vect, ISR_NAKED)
-{
- /* Clear tick interrupt flag. */
- CLR_INT(INT_FLAGS, INT_MASK);
+ ISR( TICK_INT_vect, ISR_NAKED )
+ {
+ /* Clear tick interrupt flag. */
+ CLR_INT( INT_FLAGS, INT_MASK );
- vPortYieldFromTick();
+ vPortYieldFromTick();
- asm volatile("reti");
-}
-#else
+ asm volatile ( "reti" );
+ }
+#else /* if configUSE_PREEMPTION == 1 */
/*
* Tick ISR for the cooperative scheduler. All this does is increment the
* tick count. We don't need to switch context, this can only be done by
* manual calls to taskYIELD();
*/
-ISR(TICK_INT_vect)
-{
- /* Clear tick interrupt flag. */
- INT_FLAGS = INT_MASK;
- xTaskIncrementTick();
-}
-#endif
+ ISR( TICK_INT_vect )
+ {
+ /* Clear tick interrupt flag. */
+ INT_FLAGS = INT_MASK;
+ xTaskIncrementTick();
+ }
+#endif /* if configUSE_PREEMPTION == 1 */
diff --git a/portable/GCC/AVR_AVRDx/porthardware.h b/portable/GCC/AVR_AVRDx/porthardware.h
index cf23778..7e670d9 100644
--- a/portable/GCC/AVR_AVRDx/porthardware.h
+++ b/portable/GCC/AVR_AVRDx/porthardware.h
@@ -5,98 +5,104 @@
/*-----------------------------------------------------------*/
-#define CLR_INT(FLAG_REG, FLAG_MASK) \
- asm volatile( \
- "push r16\n\t" \
- "ldi r16, %1\n\t" \
- "sts %0, r16\n\t" \
- "pop r16\n\t" \
- : \
- : "i"(_SFR_MEM_ADDR(FLAG_REG)),"i"((uint8_t)(FLAG_MASK)) \
+#define CLR_INT( FLAG_REG, FLAG_MASK ) \
+ asm volatile ( \
+ "push r16\n\t" \
+ "ldi r16, %1\n\t" \
+ "sts %0, r16\n\t" \
+ "pop r16\n\t" \
+ : \
+ : "i" ( _SFR_MEM_ADDR( FLAG_REG ) ), "i" ( ( uint8_t ) ( FLAG_MASK ) ) \
);
#if ( configUSE_TIMER_INSTANCE == 0 )
- #define TICK_INT_vect TCB0_INT_vect
- #define INT_FLAGS TCB0_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB0_INT_vect
+ #define INT_FLAGS TCB0_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB0.INTCTRL = TCB_CAPT_bm; \
- TCB0.CTRLA = TCB_ENABLE_bm; \
- }
+ #define TICK_init() \
+ { \
+ TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB0.INTCTRL = TCB_CAPT_bm; \
+ TCB0.CTRLA = TCB_ENABLE_bm; \
+ }
#elif ( configUSE_TIMER_INSTANCE == 1 )
- #define TICK_INT_vect TCB1_INT_vect
- #define INT_FLAGS TCB1_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB1_INT_vect
+ #define INT_FLAGS TCB1_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB1.INTCTRL = TCB_CAPT_bm; \
- TCB1.CTRLA = TCB_ENABLE_bm; \
- }
-
+ #define TICK_init() \
+ { \
+ TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB1.INTCTRL = TCB_CAPT_bm; \
+ TCB1.CTRLA = TCB_ENABLE_bm; \
+ }
+
#elif ( configUSE_TIMER_INSTANCE == 2 )
- #define TICK_INT_vect TCB2_INT_vect
- #define INT_FLAGS TCB2_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB2_INT_vect
+ #define INT_FLAGS TCB2_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB2.INTCTRL = TCB_CAPT_bm; \
- TCB2.CTRLA = TCB_ENABLE_bm; \
- }
-
+ #define TICK_init() \
+ { \
+ TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB2.INTCTRL = TCB_CAPT_bm; \
+ TCB2.CTRLA = TCB_ENABLE_bm; \
+ }
+
#elif ( configUSE_TIMER_INSTANCE == 3 )
- #define TICK_INT_vect TCB3_INT_vect
- #define INT_FLAGS TCB3_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB3_INT_vect
+ #define INT_FLAGS TCB3_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB3.INTCTRL = TCB_CAPT_bm; \
- TCB3.CTRLA = TCB_ENABLE_bm; \
- }
-
+ #define TICK_init() \
+ { \
+ TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB3.INTCTRL = TCB_CAPT_bm; \
+ TCB3.CTRLA = TCB_ENABLE_bm; \
+ }
+
#elif ( configUSE_TIMER_INSTANCE == 4 )
- #define TICK_INT_vect TCB4_INT_vect
- #define INT_FLAGS TCB4_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB4_INT_vect
+ #define INT_FLAGS TCB4_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB4.INTCTRL = TCB_CAPT_bm; \
- TCB4.CTRLA = TCB_ENABLE_bm; \
- }
+ #define TICK_init() \
+ { \
+ TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB4.INTCTRL = TCB_CAPT_bm; \
+ TCB4.CTRLA = TCB_ENABLE_bm; \
+ }
#elif ( configUSE_TIMER_INSTANCE == 5 )
- #define TICK_INT_vect RTC_CNT_vect
- #define INT_FLAGS RTC_INTFLAGS
- #define INT_MASK RTC_OVF_bm
+ #define TICK_INT_vect RTC_CNT_vect
+ #define INT_FLAGS RTC_INTFLAGS
+ #define INT_MASK RTC_OVF_bm
- /* Hertz to period for RTC setup */
- #define RTC_PERIOD_HZ(x) ( 32768 * ( ( 1.0 / x ) ) )
- #define TICK_init() { \
- while (RTC.STATUS > 0); \
- RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
- RTC.PER = RTC_PERIOD_HZ(configTICK_RATE_HZ); \
- RTC.INTCTRL |= 1 << RTC_OVF_bp; \
- }
+/* Hertz to period for RTC setup */
+ #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) )
+ #define TICK_init() \
+ { \
+ while( RTC.STATUS > 0 ) {; } \
+ RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
+ RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \
+ RTC.INTCTRL |= 1 << RTC_OVF_bp; \
+ }
-#else
+#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
#undef TICK_INT_vect
#undef INT_FLAGS
#undef INT_MASK
#undef TICK_init()
#error Invalid timer setting.
-#endif
+#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
/*-----------------------------------------------------------*/
diff --git a/portable/GCC/AVR_AVRDx/portmacro.h b/portable/GCC/AVR_AVRDx/portmacro.h
index 085a27f..99fd4b3 100644
--- a/portable/GCC/AVR_AVRDx/portmacro.h
+++ b/portable/GCC/AVR_AVRDx/portmacro.h
@@ -23,14 +23,16 @@
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
-*/
+ */
#ifndef PORTMACRO_H
#define PORTMACRO_H
-#ifdef __cplusplus
-extern "C" {
-#endif
+/* *INDENT-OFF* */
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+/* *INDENT-ON* */
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,64 +45,66 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint8_t
-#define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
-#define portPOINTER_SIZE_TYPE uint16_t
+#define portPOINTER_SIZE_TYPE uint16_t
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
-#if (configUSE_16_BIT_TICKS == 1)
-typedef uint16_t TickType_t;
-#define portMAX_DELAY (TickType_t)0xffff
+#if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
-typedef uint32_t TickType_t;
-#define portMAX_DELAY (TickType_t)0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Critical section management. */
-#define portENTER_CRITICAL() \
- asm volatile("in __tmp_reg__, __SREG__"); \
- asm volatile("cli"); \
- asm volatile("push __tmp_reg__")
+#define portENTER_CRITICAL() \
+ asm volatile ( "in __tmp_reg__, __SREG__" ); \
+ asm volatile ( "cli" ); \
+ asm volatile ( "push __tmp_reg__" )
-#define portEXIT_CRITICAL() \
- asm volatile("pop __tmp_reg__"); \
- asm volatile("out __SREG__, __tmp_reg__")
+#define portEXIT_CRITICAL() \
+ asm volatile ( "pop __tmp_reg__" ); \
+ asm volatile ( "out __SREG__, __tmp_reg__" )
-#define portDISABLE_INTERRUPTS() asm volatile("cli" ::);
-#define portENABLE_INTERRUPTS() asm volatile("sei" ::);
+#define portDISABLE_INTERRUPTS() asm volatile ( "cli" ::);
+#define portENABLE_INTERRUPTS() asm volatile ( "sei" ::);
/*-----------------------------------------------------------*/
/* Architecture specifics. */
-#define portSTACK_GROWTH (-1)
-#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
-#define portBYTE_ALIGNMENT 1
-#define portNOP() asm volatile("nop");
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 1
+#define portNOP() asm volatile ( "nop" );
/*-----------------------------------------------------------*/
/* Kernel utilities. */
-extern void vPortYield(void) __attribute__((naked));
-#define portYIELD() vPortYield()
+extern void vPortYield( void ) __attribute__( ( naked ) );
+#define portYIELD() vPortYield()
-extern void vPortYieldFromISR(void) __attribute__((naked));
-#define portYIELD_FROM_ISR() vPortYieldFromISR()
+extern void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+#define portYIELD_FROM_ISR() vPortYieldFromISR()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
-#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#ifdef __cplusplus
-}
-#endif
+/* *INDENT-OFF* */
+ #ifdef __cplusplus
+ }
+ #endif
+/* *INDENT-ON* */
#endif /* PORTMACRO_H */
diff --git a/portable/GCC/AVR_Mega0/port.c b/portable/GCC/AVR_Mega0/port.c
index 8c46842..c27b7cc 100644
--- a/portable/GCC/AVR_Mega0/port.c
+++ b/portable/GCC/AVR_Mega0/port.c
@@ -34,18 +34,18 @@
#include "task.h"
/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the AVR port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
/* Start tasks with interrupts enables. */
-#define portFLAGS_INT_ENABLED ((StackType_t) 0x80)
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
/*-----------------------------------------------------------*/
/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
typedef void RTOS_TCB_t;
-extern volatile RTOS_TCB_t *volatile pxCurrentTCB;
+extern volatile RTOS_TCB_t * volatile pxCurrentTCB;
/*-----------------------------------------------------------*/
@@ -65,155 +65,157 @@
* so we need not worry about reading/writing to the stack pointer.
*/
-#define portSAVE_CONTEXT() \
- asm volatile("push r0 \n\t" \
- "in r0, __SREG__ \n\t" \
- "cli \n\t" \
- "push r0 \n\t" \
- "push r1 \n\t" \
- "clr r1 \n\t" \
- "push r2 \n\t" \
- "push r3 \n\t" \
- "push r4 \n\t" \
- "push r5 \n\t" \
- "push r6 \n\t" \
- "push r7 \n\t" \
- "push r8 \n\t" \
- "push r9 \n\t" \
- "push r10 \n\t" \
- "push r11 \n\t" \
- "push r12 \n\t" \
- "push r13 \n\t" \
- "push r14 \n\t" \
- "push r15 \n\t" \
- "push r16 \n\t" \
- "push r17 \n\t" \
- "push r18 \n\t" \
- "push r19 \n\t" \
- "push r20 \n\t" \
- "push r21 \n\t" \
- "push r22 \n\t" \
- "push r23 \n\t" \
- "push r24 \n\t" \
- "push r25 \n\t" \
- "push r26 \n\t" \
- "push r27 \n\t" \
- "push r28 \n\t" \
- "push r29 \n\t" \
- "push r30 \n\t" \
- "push r31 \n\t" \
- "lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "in r0, __SP_L__ \n\t" \
- "st x+, r0 \n\t" \
- "in r0, __SP_H__ \n\t" \
- "st x+, r0 \n\t");
+#define portSAVE_CONTEXT() \
+ asm volatile ( "push r0 \n\t" \
+ "in r0, __SREG__ \n\t" \
+ "cli \n\t" \
+ "push r0 \n\t" \
+ "push r1 \n\t" \
+ "clr r1 \n\t" \
+ "push r2 \n\t" \
+ "push r3 \n\t" \
+ "push r4 \n\t" \
+ "push r5 \n\t" \
+ "push r6 \n\t" \
+ "push r7 \n\t" \
+ "push r8 \n\t" \
+ "push r9 \n\t" \
+ "push r10 \n\t" \
+ "push r11 \n\t" \
+ "push r12 \n\t" \
+ "push r13 \n\t" \
+ "push r14 \n\t" \
+ "push r15 \n\t" \
+ "push r16 \n\t" \
+ "push r17 \n\t" \
+ "push r18 \n\t" \
+ "push r19 \n\t" \
+ "push r20 \n\t" \
+ "push r21 \n\t" \
+ "push r22 \n\t" \
+ "push r23 \n\t" \
+ "push r24 \n\t" \
+ "push r25 \n\t" \
+ "push r26 \n\t" \
+ "push r27 \n\t" \
+ "push r28 \n\t" \
+ "push r29 \n\t" \
+ "push r30 \n\t" \
+ "push r31 \n\t" \
+ "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "in r0, __SP_L__ \n\t" \
+ "st x+, r0 \n\t" \
+ "in r0, __SP_H__ \n\t" \
+ "st x+, r0 \n\t" );
/*
* Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during
* the context save so we can write to the stack pointer.
*/
-#define portRESTORE_CONTEXT() \
- asm volatile("lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "ld r28, x+ \n\t" \
- "out __SP_L__, r28 \n\t" \
- "ld r29, x+ \n\t" \
- "out __SP_H__, r29 \n\t" \
- "pop r31 \n\t" \
- "pop r30 \n\t" \
- "pop r29 \n\t" \
- "pop r28 \n\t" \
- "pop r27 \n\t" \
- "pop r26 \n\t" \
- "pop r25 \n\t" \
- "pop r24 \n\t" \
- "pop r23 \n\t" \
- "pop r22 \n\t" \
- "pop r21 \n\t" \
- "pop r20 \n\t" \
- "pop r19 \n\t" \
- "pop r18 \n\t" \
- "pop r17 \n\t" \
- "pop r16 \n\t" \
- "pop r15 \n\t" \
- "pop r14 \n\t" \
- "pop r13 \n\t" \
- "pop r12 \n\t" \
- "pop r11 \n\t" \
- "pop r10 \n\t" \
- "pop r9 \n\t" \
- "pop r8 \n\t" \
- "pop r7 \n\t" \
- "pop r6 \n\t" \
- "pop r5 \n\t" \
- "pop r4 \n\t" \
- "pop r3 \n\t" \
- "pop r2 \n\t" \
- "pop r1 \n\t" \
- "pop r0 \n\t" \
- "out __SREG__, r0 \n\t" \
- "pop r0 \n\t");
+#define portRESTORE_CONTEXT() \
+ asm volatile ( "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "ld r28, x+ \n\t" \
+ "out __SP_L__, r28 \n\t" \
+ "ld r29, x+ \n\t" \
+ "out __SP_H__, r29 \n\t" \
+ "pop r31 \n\t" \
+ "pop r30 \n\t" \
+ "pop r29 \n\t" \
+ "pop r28 \n\t" \
+ "pop r27 \n\t" \
+ "pop r26 \n\t" \
+ "pop r25 \n\t" \
+ "pop r24 \n\t" \
+ "pop r23 \n\t" \
+ "pop r22 \n\t" \
+ "pop r21 \n\t" \
+ "pop r20 \n\t" \
+ "pop r19 \n\t" \
+ "pop r18 \n\t" \
+ "pop r17 \n\t" \
+ "pop r16 \n\t" \
+ "pop r15 \n\t" \
+ "pop r14 \n\t" \
+ "pop r13 \n\t" \
+ "pop r12 \n\t" \
+ "pop r11 \n\t" \
+ "pop r10 \n\t" \
+ "pop r9 \n\t" \
+ "pop r8 \n\t" \
+ "pop r7 \n\t" \
+ "pop r6 \n\t" \
+ "pop r5 \n\t" \
+ "pop r4 \n\t" \
+ "pop r3 \n\t" \
+ "pop r2 \n\t" \
+ "pop r1 \n\t" \
+ "pop r0 \n\t" \
+ "out __SREG__, r0 \n\t" \
+ "pop r0 \n\t" );
/*-----------------------------------------------------------*/
/*
* Perform hardware setup to enable ticks from timer.
*/
-static void prvSetupTimerInterrupt(void);
+static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters)
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
{
uint16_t usAddress;
/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
-
+
/* Place a few bytes of known values on the bottom of the stack.
- This is just useful for debugging. Uncomment if needed. */
- // *pxTopOfStack = 0x11;
- // pxTopOfStack--;
- // *pxTopOfStack = 0x22;
- // pxTopOfStack--;
- // *pxTopOfStack = 0x33;
- // pxTopOfStack--;
+ * This is just useful for debugging. Uncomment if needed. */
+ /* *pxTopOfStack = 0x11; */
+ /* pxTopOfStack--; */
+ /* *pxTopOfStack = 0x22; */
+ /* pxTopOfStack--; */
+ /* *pxTopOfStack = 0x33; */
+ /* pxTopOfStack--; */
/* The start of the task code will be popped off the stack last, so place
- it on first. */
- usAddress = (uint16_t)pxCode;
- *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff);
+ * it on first. */
+ usAddress = ( uint16_t ) pxCode;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
usAddress >>= 8;
- *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff);
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
- portSAVE_CONTEXT places the flags on the stack immediately after r0
- to ensure the interrupts get disabled as soon as possible, and so ensuring
- the stack use is minimal should a context switch interrupt occur. */
- *pxTopOfStack = (StackType_t)0x00; /* R0 */
+ * portSAVE_CONTEXT places the flags on the stack immediately after r0
+ * to ensure the interrupts get disabled as soon as possible, and so ensuring
+ * the stack use is minimal should a context switch interrupt occur. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
pxTopOfStack--;
/* Now the remaining registers. The compiler expects R1 to be 0. */
- *pxTopOfStack = (StackType_t)0x00; /* R1 */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
/* Leave R2 - R23 untouched */
pxTopOfStack -= 23;
/* Place the parameter on the stack in the expected location. */
- usAddress = (uint16_t)pvParameters;
- *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff);
+ usAddress = ( uint16_t ) pvParameters;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
usAddress >>= 8;
- *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff);
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
/* Leave register R26 - R31 untouched */
pxTopOfStack -= 7;
@@ -224,7 +226,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t xPortStartScheduler(void)
+BaseType_t xPortStartScheduler( void )
{
/* Setup the hardware to generate the tick. */
prvSetupTimerInterrupt();
@@ -233,15 +235,15 @@
portRESTORE_CONTEXT();
/* Simulate a function call end as generated by the compiler. We will now
- jump to the start of the task the context of which we have just restored. */
- asm volatile("ret");
+ * jump to the start of the task the context of which we have just restored. */
+ asm volatile ( "ret" );
/* Should not get here. */
return pdTRUE;
}
/*-----------------------------------------------------------*/
-void vPortEndScheduler(void)
+void vPortEndScheduler( void )
{
/* vPortEndScheduler is not implemented in this port. */
}
@@ -251,13 +253,13 @@
* Manual context switch. The first thing we do is save the registers so we
* can use a naked attribute.
*/
-void vPortYield(void) __attribute__((naked));
-void vPortYield(void)
+void vPortYield( void ) __attribute__( ( naked ) );
+void vPortYield( void )
{
portSAVE_CONTEXT();
vTaskSwitchContext();
portRESTORE_CONTEXT();
- asm volatile("ret");
+ asm volatile ( "ret" );
}
/*-----------------------------------------------------------*/
@@ -265,13 +267,13 @@
* Manual context switch callable from ISRs. The first thing
* we do is save the registers so we can use a naked attribute.
*/
-void vPortYieldFromISR(void) __attribute__((naked));
-void vPortYieldFromISR(void)
+void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+void vPortYieldFromISR( void )
{
portSAVE_CONTEXT();
vTaskSwitchContext();
portRESTORE_CONTEXT();
- asm volatile("reti");
+ asm volatile ( "reti" );
}
/*-----------------------------------------------------------*/
@@ -281,24 +283,26 @@
* difference from vPortYield() is the tick count is incremented as the
* call comes from the tick ISR.
*/
-void vPortYieldFromTick(void) __attribute__((naked));
-void vPortYieldFromTick(void)
+void vPortYieldFromTick( void ) __attribute__( ( naked ) );
+void vPortYieldFromTick( void )
{
portSAVE_CONTEXT();
- if (xTaskIncrementTick() != pdFALSE) {
+
+ if( xTaskIncrementTick() != pdFALSE )
+ {
vTaskSwitchContext();
}
portRESTORE_CONTEXT();
- asm volatile("reti");
+ asm volatile ( "reti" );
}
/*-----------------------------------------------------------*/
/*
* Setup timer to generate a tick interrupt.
*/
-static void prvSetupTimerInterrupt(void)
+static void prvSetupTimerInterrupt( void )
{
TICK_init();
}
@@ -311,26 +315,26 @@
* the context is saved at the start of vPortYieldFromTick(). The tick
* count is incremented after the context is saved.
*/
-ISR(TICK_INT_vect, ISR_NAKED)
-{
- /* Clear tick interrupt flag. */
- CLR_INT(INT_FLAGS, INT_MASK);
+ ISR( TICK_INT_vect, ISR_NAKED )
+ {
+ /* Clear tick interrupt flag. */
+ CLR_INT( INT_FLAGS, INT_MASK );
- vPortYieldFromTick();
+ vPortYieldFromTick();
- asm volatile("reti");
-}
-#else
+ asm volatile ( "reti" );
+ }
+#else /* if configUSE_PREEMPTION == 1 */
/*
* Tick ISR for the cooperative scheduler. All this does is increment the
* tick count. We don't need to switch context, this can only be done by
* manual calls to taskYIELD();
*/
-ISR(TICK_INT_vect)
-{
- /* Clear tick interrupt flag. */
- INT_FLAGS = INT_MASK;
- xTaskIncrementTick();
-}
-#endif
+ ISR( TICK_INT_vect )
+ {
+ /* Clear tick interrupt flag. */
+ INT_FLAGS = INT_MASK;
+ xTaskIncrementTick();
+ }
+#endif /* if configUSE_PREEMPTION == 1 */
diff --git a/portable/GCC/AVR_Mega0/porthardware.h b/portable/GCC/AVR_Mega0/porthardware.h
index aeeccf5..8d4f1bc 100644
--- a/portable/GCC/AVR_Mega0/porthardware.h
+++ b/portable/GCC/AVR_Mega0/porthardware.h
@@ -5,86 +5,91 @@
/*-----------------------------------------------------------*/
-#define CLR_INT(FLAG_REG, FLAG_MASK) \
- asm volatile( \
- "push r16\n\t" \
- "ldi r16, %1\n\t" \
- "sts %0, r16\n\t" \
- "pop r16\n\t" \
- : \
- : "i"(_SFR_MEM_ADDR(FLAG_REG)),"i"((uint8_t)(FLAG_MASK)) \
+#define CLR_INT( FLAG_REG, FLAG_MASK ) \
+ asm volatile ( \
+ "push r16\n\t" \
+ "ldi r16, %1\n\t" \
+ "sts %0, r16\n\t" \
+ "pop r16\n\t" \
+ : \
+ : "i" ( _SFR_MEM_ADDR( FLAG_REG ) ), "i" ( ( uint8_t ) ( FLAG_MASK ) ) \
);
#if ( configUSE_TIMER_INSTANCE == 0 )
- #define TICK_INT_vect TCB0_INT_vect
- #define INT_FLAGS TCB0_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB0_INT_vect
+ #define INT_FLAGS TCB0_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB0.INTCTRL = TCB_CAPT_bm; \
- TCB0.CTRLA = TCB_ENABLE_bm; \
- }
+ #define TICK_init() \
+ { \
+ TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB0.INTCTRL = TCB_CAPT_bm; \
+ TCB0.CTRLA = TCB_ENABLE_bm; \
+ }
#elif ( configUSE_TIMER_INSTANCE == 1 )
- #define TICK_INT_vect TCB1_INT_vect
- #define INT_FLAGS TCB1_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB1_INT_vect
+ #define INT_FLAGS TCB1_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB1.INTCTRL = TCB_CAPT_bm; \
- TCB1.CTRLA = TCB_ENABLE_bm; \
- }
+ #define TICK_init() \
+ { \
+ TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB1.INTCTRL = TCB_CAPT_bm; \
+ TCB1.CTRLA = TCB_ENABLE_bm; \
+ }
#elif ( configUSE_TIMER_INSTANCE == 2 )
- #define TICK_INT_vect TCB2_INT_vect
- #define INT_FLAGS TCB2_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB2_INT_vect
+ #define INT_FLAGS TCB2_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB2.INTCTRL = TCB_CAPT_bm; \
- TCB2.CTRLA = TCB_ENABLE_bm; \
- }
+ #define TICK_init() \
+ { \
+ TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB2.INTCTRL = TCB_CAPT_bm; \
+ TCB2.CTRLA = TCB_ENABLE_bm; \
+ }
#elif ( configUSE_TIMER_INSTANCE == 3 )
- #define TICK_INT_vect TCB3_INT_vect
- #define INT_FLAGS TCB3_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB3_INT_vect
+ #define INT_FLAGS TCB3_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB3.INTCTRL = TCB_CAPT_bm; \
- TCB3.CTRLA = TCB_ENABLE_bm; \
- }
+ #define TICK_init() \
+ { \
+ TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB3.INTCTRL = TCB_CAPT_bm; \
+ TCB3.CTRLA = TCB_ENABLE_bm; \
+ }
#elif ( configUSE_TIMER_INSTANCE == 4 )
- #define TICK_INT_vect RTC_CNT_vect
- #define INT_FLAGS RTC_INTFLAGS
- #define INT_MASK RTC_OVF_bm
+ #define TICK_INT_vect RTC_CNT_vect
+ #define INT_FLAGS RTC_INTFLAGS
+ #define INT_MASK RTC_OVF_bm
- /* Hertz to period for RTC setup */
- #define RTC_PERIOD_HZ(x) ( 32768 * ( ( 1.0 / x ) ) )
- #define TICK_init() { \
- while (RTC.STATUS > 0); \
- RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
- RTC.PER = RTC_PERIOD_HZ(configTICK_RATE_HZ); \
- RTC.INTCTRL |= 1 << RTC_OVF_bp; \
- }
+/* Hertz to period for RTC setup */
+ #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) )
+ #define TICK_init() \
+ { \
+ while( RTC.STATUS > 0 ) {; } \
+ RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
+ RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \
+ RTC.INTCTRL |= 1 << RTC_OVF_bp; \
+ }
-#else
+#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
#undef TICK_INT_vect
#undef INT_FLAGS
#undef INT_MASK
#undef TICK_init()
#error Invalid timer setting.
-#endif
+#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
/*-----------------------------------------------------------*/
diff --git a/portable/GCC/AVR_Mega0/portmacro.h b/portable/GCC/AVR_Mega0/portmacro.h
index 085a27f..a464215 100644
--- a/portable/GCC/AVR_Mega0/portmacro.h
+++ b/portable/GCC/AVR_Mega0/portmacro.h
@@ -23,14 +23,16 @@
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
-*/
+ */
#ifndef PORTMACRO_H
#define PORTMACRO_H
+/* *INDENT-OFF* */
#ifdef __cplusplus
-extern "C" {
+ extern "C" {
#endif
+/* *INDENT-ON* */
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,64 +45,66 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint8_t
-#define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
-#define portPOINTER_SIZE_TYPE uint16_t
+#define portPOINTER_SIZE_TYPE uint16_t
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
-#if (configUSE_16_BIT_TICKS == 1)
-typedef uint16_t TickType_t;
-#define portMAX_DELAY (TickType_t)0xffff
+#if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
-typedef uint32_t TickType_t;
-#define portMAX_DELAY (TickType_t)0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Critical section management. */
-#define portENTER_CRITICAL() \
- asm volatile("in __tmp_reg__, __SREG__"); \
- asm volatile("cli"); \
- asm volatile("push __tmp_reg__")
+#define portENTER_CRITICAL() \
+ asm volatile ( "in __tmp_reg__, __SREG__" ); \
+ asm volatile ( "cli" ); \
+ asm volatile ( "push __tmp_reg__" )
-#define portEXIT_CRITICAL() \
- asm volatile("pop __tmp_reg__"); \
- asm volatile("out __SREG__, __tmp_reg__")
+#define portEXIT_CRITICAL() \
+ asm volatile ( "pop __tmp_reg__" ); \
+ asm volatile ( "out __SREG__, __tmp_reg__" )
-#define portDISABLE_INTERRUPTS() asm volatile("cli" ::);
-#define portENABLE_INTERRUPTS() asm volatile("sei" ::);
+#define portDISABLE_INTERRUPTS() asm volatile ( "cli" ::);
+#define portENABLE_INTERRUPTS() asm volatile ( "sei" ::);
/*-----------------------------------------------------------*/
/* Architecture specifics. */
-#define portSTACK_GROWTH (-1)
-#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
-#define portBYTE_ALIGNMENT 1
-#define portNOP() asm volatile("nop");
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 1
+#define portNOP() asm volatile ( "nop" );
/*-----------------------------------------------------------*/
/* Kernel utilities. */
-extern void vPortYield(void) __attribute__((naked));
-#define portYIELD() vPortYield()
+extern void vPortYield( void ) __attribute__( ( naked ) );
+#define portYIELD() vPortYield()
-extern void vPortYieldFromISR(void) __attribute__((naked));
-#define portYIELD_FROM_ISR() vPortYieldFromISR()
+extern void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+#define portYIELD_FROM_ISR() vPortYieldFromISR()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
-#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/* *INDENT-OFF* */
#ifdef __cplusplus
-}
+ }
#endif
+/* *INDENT-ON* */
#endif /* PORTMACRO_H */
diff --git a/portable/GCC/CORTUS_APS3/port.c b/portable/GCC/CORTUS_APS3/port.c
index e14f7f0..b6c55a3 100644
--- a/portable/GCC/CORTUS_APS3/port.c
+++ b/portable/GCC/CORTUS_APS3/port.c
@@ -38,7 +38,7 @@
/*-----------------------------------------------------------*/
/* The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. */
-#define portINITIAL_PSR ( 0x00020000 )
+#define portINITIAL_PSR ( 0x00020000 )
/*-----------------------------------------------------------*/
@@ -48,100 +48,98 @@
static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Make space on the stack for the context - this leaves a couple of spaces
- * empty. */
- pxTopOfStack -= 20;
+ /* Make space on the stack for the context - this leaves a couple of spaces
+ empty. */
+ pxTopOfStack -= 20;
- /* Fill the registers with known values to assist debugging. */
- pxTopOfStack[ 16 ] = 0;
- pxTopOfStack[ 15 ] = portINITIAL_PSR;
- pxTopOfStack[ 14 ] = ( uint32_t ) pxCode;
- pxTopOfStack[ 13 ] = 0x00000000UL; /* R15. */
- pxTopOfStack[ 12 ] = 0x00000000UL; /* R14. */
- pxTopOfStack[ 11 ] = 0x0d0d0d0dUL;
- pxTopOfStack[ 10 ] = 0x0c0c0c0cUL;
- pxTopOfStack[ 9 ] = 0x0b0b0b0bUL;
- pxTopOfStack[ 8 ] = 0x0a0a0a0aUL;
- pxTopOfStack[ 7 ] = 0x09090909UL;
- pxTopOfStack[ 6 ] = 0x08080808UL;
- pxTopOfStack[ 5 ] = 0x07070707UL;
- pxTopOfStack[ 4 ] = 0x06060606UL;
- pxTopOfStack[ 3 ] = 0x05050505UL;
- pxTopOfStack[ 2 ] = 0x04040404UL;
- pxTopOfStack[ 1 ] = 0x03030303UL;
- pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters;
+ /* Fill the registers with known values to assist debugging. */
+ pxTopOfStack[ 16 ] = 0;
+ pxTopOfStack[ 15 ] = portINITIAL_PSR;
+ pxTopOfStack[ 14 ] = ( uint32_t ) pxCode;
+ pxTopOfStack[ 13 ] = 0x00000000UL; /* R15. */
+ pxTopOfStack[ 12 ] = 0x00000000UL; /* R14. */
+ pxTopOfStack[ 11 ] = 0x0d0d0d0dUL;
+ pxTopOfStack[ 10 ] = 0x0c0c0c0cUL;
+ pxTopOfStack[ 9 ] = 0x0b0b0b0bUL;
+ pxTopOfStack[ 8 ] = 0x0a0a0a0aUL;
+ pxTopOfStack[ 7 ] = 0x09090909UL;
+ pxTopOfStack[ 6 ] = 0x08080808UL;
+ pxTopOfStack[ 5 ] = 0x07070707UL;
+ pxTopOfStack[ 4 ] = 0x06060606UL;
+ pxTopOfStack[ 3 ] = 0x05050505UL;
+ pxTopOfStack[ 2 ] = 0x04040404UL;
+ pxTopOfStack[ 1 ] = 0x03030303UL;
+ pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Set-up the timer interrupt. */
- prvSetupTimerInterrupt();
+ /* Set-up the timer interrupt. */
+ prvSetupTimerInterrupt();
- /* Integrated Interrupt Controller: Enable all interrupts. */
- ic->ien = 1;
+ /* Integrated Interrupt Controller: Enable all interrupts. */
+ ic->ien = 1;
- /* Restore callee saved registers. */
- portRESTORE_CONTEXT();
+ /* Restore callee saved registers. */
+ portRESTORE_CONTEXT();
- /* Should not get here. */
- return 0;
+ /* Should not get here. */
+ return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- /* Enable timer interrupts */
- counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1;
- counter1->value = counter1->reload;
- counter1->mask = 1;
+ /* Enable timer interrupts */
+ counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1;
+ counter1->value = counter1->reload;
+ counter1->mask = 1;
- /* Set the IRQ Handler priority and enable it. */
- irq[ IRQ_COUNTER1 ].ien = 1;
+ /* Set the IRQ Handler priority and enable it. */
+ irq[ IRQ_COUNTER1 ].ien = 1;
}
/*-----------------------------------------------------------*/
/* Trap 31 handler. */
-void interrupt31_handler( void ) __attribute__( ( naked ) );
+void interrupt31_handler( void ) __attribute__((naked));
void interrupt31_handler( void )
{
- portSAVE_CONTEXT();
- __asm volatile ( "call vTaskSwitchContext" );
- portRESTORE_CONTEXT();
+ portSAVE_CONTEXT();
+ __asm volatile ( "call vTaskSwitchContext" );
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
-static void prvProcessTick( void ) __attribute__( ( noinline ) );
+static void prvProcessTick( void ) __attribute__((noinline));
static void prvProcessTick( void )
{
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Clear the Tick Interrupt. */
- counter1->expired = 0;
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ /* Clear the Tick Interrupt. */
+ counter1->expired = 0;
}
/*-----------------------------------------------------------*/
/* Timer 1 interrupt handler, used for tick interrupt. */
-void interrupt7_handler( void ) __attribute__( ( naked ) );
+void interrupt7_handler( void ) __attribute__((naked));
void interrupt7_handler( void )
{
- portSAVE_CONTEXT();
- prvProcessTick();
- portRESTORE_CONTEXT();
+ portSAVE_CONTEXT();
+ prvProcessTick();
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Nothing to do. Unlikely to want to end. */
+ /* Nothing to do. Unlikely to want to end. */
}
/*-----------------------------------------------------------*/
diff --git a/portable/GCC/CORTUS_APS3/portmacro.h b/portable/GCC/CORTUS_APS3/portmacro.h
index 1788ebb..dbbe3a6 100644
--- a/portable/GCC/CORTUS_APS3/portmacro.h
+++ b/portable/GCC/CORTUS_APS3/portmacro.h
@@ -26,13 +26,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
- #include <machine/cpu.h>
+#include <machine/cpu.h>
/*-----------------------------------------------------------
* Port specific definitions.
@@ -45,108 +45,108 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 4
- #define portNOP() __asm__ volatile ( "mov r0, r0" )
- #define portCRITICAL_NESTING_IN_TCB 1
- #define portIRQ_TRAP_YIELD 31
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() __asm__ volatile ( "mov r0, r0" )
+#define portCRITICAL_NESTING_IN_TCB 1
+#define portIRQ_TRAP_YIELD 31
/*-----------------------------------------------------------*/
/* Task utilities. */
- extern void vPortYield( void );
+extern void vPortYield( void );
/*---------------------------------------------------------------------------*/
- #define portYIELD() asm __volatile__ ( " trap #%0 " : : "i" ( portIRQ_TRAP_YIELD ) : "memory" )
+#define portYIELD() asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory")
/*---------------------------------------------------------------------------*/
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/*---------------------------------------------------------------------------*/
/* Critical section management. */
- #define portDISABLE_INTERRUPTS() cpu_int_disable()
- #define portENABLE_INTERRUPTS() cpu_int_enable()
+#define portDISABLE_INTERRUPTS() cpu_int_disable()
+#define portENABLE_INTERRUPTS() cpu_int_enable()
/*---------------------------------------------------------------------------*/
- #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext()
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext()
/*---------------------------------------------------------------------------*/
- #define portSAVE_CONTEXT() \
- asm __volatile__ \
- ( \
- "sub r1, #68 \n"/* Make space on the stack for the context. */ \
- "std r2, [r1] + 0 \n" \
- "stq r4, [r1] + 8 \n" \
- "stq r8, [r1] + 24 \n" \
- "stq r12, [r1] + 40 \n" \
- "mov r6, rtt \n" \
- "mov r7, psr \n" \
- "std r6, [r1] + 56 \n" \
- "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \
- "ldub r3, [r2] + 2 \n" /* Load the current interrupt mask. */ \
- "st r3, [r1]+ 64 \n" /* Store the interrupt mask on the stack. */ \
- "ld r2, [r0]+short(pxCurrentTCB) \n"/* Load the pointer to the TCB. */ \
- "st r1, [r2] \n" /* Save the stack pointer into the TCB. */ \
- "mov r14, r1 \n" /* Compiler expects r14 to be set to the function stack. */ \
- );
+#define portSAVE_CONTEXT() \
+ asm __volatile__ \
+ ( \
+ "sub r1, #68 \n" /* Make space on the stack for the context. */ \
+ "std r2, [r1] + 0 \n" \
+ "stq r4, [r1] + 8 \n" \
+ "stq r8, [r1] + 24 \n" \
+ "stq r12, [r1] + 40 \n" \
+ "mov r6, rtt \n" \
+ "mov r7, psr \n" \
+ "std r6, [r1] + 56 \n" \
+ "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \
+ "ldub r3, [r2] + 2 \n" /* Load the current interrupt mask. */ \
+ "st r3, [r1]+ 64 \n" /* Store the interrupt mask on the stack. */ \
+ "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the pointer to the TCB. */ \
+ "st r1, [r2] \n" /* Save the stack pointer into the TCB. */ \
+ "mov r14, r1 \n" /* Compiler expects r14 to be set to the function stack. */ \
+ );
/*---------------------------------------------------------------------------*/
- #define portRESTORE_CONTEXT() \
- asm __volatile__ ( \
- "ld r2, [r0]+short(pxCurrentTCB) \n"/* Load the TCB to find the stack pointer and context. */\
- "ld r1, [r2] \n" \
- "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \
- "ld r3, [r1] + 64 \n" /* Load the previous interrupt mask. */ \
- "stb r3, [r2] + 2 \n" /* Set the current interrupt mask to be the previous. */ \
- "ldd r6, [r1] + 56 \n" /* Restore context. */ \
- "mov rtt, r6 \n" \
- "mov psr, r7 \n" \
- "ldd r2, [r1] + 0 \n" \
- "ldq r4, [r1] + 8 \n" \
- "ldq r8, [r1] + 24 \n" \
- "ldq r12, [r1] + 40 \n" \
- "add r1, #68 \n" \
- "rti \n" \
- );
+#define portRESTORE_CONTEXT() \
+ asm __volatile__( \
+ "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the TCB to find the stack pointer and context. */ \
+ "ld r1, [r2] \n" \
+ "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \
+ "ld r3, [r1] + 64 \n" /* Load the previous interrupt mask. */ \
+ "stb r3, [r2] + 2 \n" /* Set the current interrupt mask to be the previous. */ \
+ "ldd r6, [r1] + 56 \n" /* Restore context. */ \
+ "mov rtt, r6 \n" \
+ "mov psr, r7 \n" \
+ "ldd r2, [r1] + 0 \n" \
+ "ldq r4, [r1] + 8 \n" \
+ "ldq r8, [r1] + 24 \n" \
+ "ldq r12, [r1] + 40 \n" \
+ "add r1, #68 \n" \
+ "rti \n" \
+ );
/*---------------------------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*---------------------------------------------------------------------------*/
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ColdFire_V2/port.c b/portable/GCC/ColdFire_V2/port.c
index 4e1f51b..3d7e529 100644
--- a/portable/GCC/ColdFire_V2/port.c
+++ b/portable/GCC/ColdFire_V2/port.c
@@ -29,36 +29,34 @@
#include "FreeRTOS.h"
#include "task.h"
-#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 )
+#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 )
/* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000 )
+#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000)
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
- * will be set to 0 prior to the first task being started. */
+will be set to 0 prior to the first task being started. */
static uint32_t ulCriticalNesting = 0x9999UL;
/*-----------------------------------------------------------*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+ pxTopOfStack--;
- /* Exception stack frame starts with the return address. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
+ /* Exception stack frame starts with the return address. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
- *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
- pxTopOfStack--;
+ *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
- pxTopOfStack -= 14; /* A5 to D0. */
+ *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
+ pxTopOfStack -= 14; /* A5 to D0. */
return pxTopOfStack;
}
@@ -66,67 +64,71 @@
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
- ulCriticalNesting = 0UL;
+ ulCriticalNesting = 0UL;
- /* Configure the interrupts used by this port. */
- vApplicationSetupInterrupts();
+ /* Configure the interrupts used by this port. */
+ vApplicationSetupInterrupts();
- /* Start the first task executing. */
- vPortStartFirstTask();
+ /* Start the first task executing. */
+ vPortStartFirstTask();
- return pdFALSE;
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented as there is nothing to return to. */
+ /* Not implemented as there is nothing to return to. */
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- if( ulCriticalNesting == 0UL )
- {
- /* Guard against context switches being pended simultaneously with a
- * critical section being entered. */
- do
- {
- portDISABLE_INTERRUPTS();
+ if( ulCriticalNesting == 0UL )
+ {
+ /* Guard against context switches being pended simultaneously with a
+ critical section being entered. */
+ do
+ {
+ portDISABLE_INTERRUPTS();
+ if( MCF_INTC0_INTFRCL == 0UL )
+ {
+ break;
+ }
- if( MCF_INTC0_INTFRCL == 0UL )
- {
- break;
- }
+ portENABLE_INTERRUPTS();
- portENABLE_INTERRUPTS();
- } while( 1 );
- }
-
- ulCriticalNesting++;
+ } while( 1 );
+ }
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- ulCriticalNesting--;
-
- if( ulCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
+ ulCriticalNesting--;
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
}
/*-----------------------------------------------------------*/
void vPortYieldHandler( void )
{
- uint32_t ulSavedInterruptMask;
+uint32_t ulSavedInterruptMask;
- ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
- /* Note this will clear all forced interrupts - this is done for speed. */
- MCF_INTC0_INTFRCL = 0;
- vTaskSwitchContext();
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* Note this will clear all forced interrupts - this is done for speed. */
+ MCF_INTC0_INTFRCL = 0;
+ vTaskSwitchContext();
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}
+
+
+
+
+
+
diff --git a/portable/GCC/ColdFire_V2/portmacro.h b/portable/GCC/ColdFire_V2/portmacro.h
index 99b4d40..ad46a61 100644
--- a/portable/GCC/ColdFire_V2/portmacro.h
+++ b/portable/GCC/ColdFire_V2/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,72 +43,72 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 4
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
- uint32_t ulPortSetIPL( uint32_t );
- #define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
+uint32_t ulPortSetIPL( uint32_t );
+#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
- extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
- extern void vPortClearInterruptMaskFromISR( UBaseType_t );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portNOP() asm volatile ( "nop" )
+#define portNOP() asm volatile ( "nop" )
/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
- #define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()
+#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- if( xSwitchRequired != pdFALSE ) \
- { \
- portYIELD(); \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) \
+ { \
+ portYIELD(); \
+ }
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/H8S2329/port.c b/portable/GCC/H8S2329/port.c
index 4cf4570..6f49b14 100644
--- a/portable/GCC/H8S2329/port.c
+++ b/portable/GCC/H8S2329/port.c
@@ -31,22 +31,22 @@
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the H8S port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the H8S port.
+ *----------------------------------------------------------*/
/*-----------------------------------------------------------*/
/* When the task starts interrupts should be enabled. */
-#define portINITIAL_CCR ( ( StackType_t ) 0x00 )
+#define portINITIAL_CCR ( ( StackType_t ) 0x00 )
/* Hardware specific constants used to generate the RTOS tick from the TPU. */
-#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 )
-#define portCLOCK_DIV_64 ( ( uint8_t ) 0x03 )
-#define portCLOCK_DIV ( ( uint32_t ) 64 )
-#define portTGRA_INTERRUPT_ENABLE ( ( uint8_t ) 0x01 )
-#define portTIMER_CHANNEL ( ( uint8_t ) 0x02 )
-#define portMSTP13 ( ( uint16_t ) 0x2000 )
+#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 )
+#define portCLOCK_DIV_64 ( ( uint8_t ) 0x03 )
+#define portCLOCK_DIV ( ( uint32_t ) 64 )
+#define portTGRA_INTERRUPT_ENABLE ( ( uint8_t ) 0x01 )
+#define portTIMER_CHANNEL ( ( uint8_t ) 0x02 )
+#define portMSTP13 ( ( uint16_t ) 0x2000 )
/*
* Setup TPU channel one for the RTOS tick at the requested frequency.
@@ -56,167 +56,164 @@
/*
* The ISR used by portYIELD(). This is installed as a trap handler.
*/
-void vPortYield( void ) __attribute__( ( saveall, interrupt_handler ) );
+void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) );
/*-----------------------------------------------------------*/
-/*
- * See header file for description.
+/*
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint32_t ulValue;
+uint32_t ulValue;
- /* This requires an even address. */
- ulValue = ( uint32_t ) pxTopOfStack;
+ /* This requires an even address. */
+ ulValue = ( uint32_t ) pxTopOfStack;
+ if( ulValue & 1UL )
+ {
+ pxTopOfStack = pxTopOfStack - 1;
+ }
- if( ulValue & 1UL )
- {
- pxTopOfStack = pxTopOfStack - 1;
- }
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdd;
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging. */
- pxTopOfStack--;
- *pxTopOfStack = 0xaa;
- pxTopOfStack--;
- *pxTopOfStack = 0xbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xcc;
- pxTopOfStack--;
- *pxTopOfStack = 0xdd;
+ /* The initial stack mimics an interrupt stack. First there is the program
+ counter (24 bits). */
+ ulValue = ( uint32_t ) pxCode;
- /* The initial stack mimics an interrupt stack. First there is the program
- * counter (24 bits). */
- ulValue = ( uint32_t ) pxCode;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ pxTopOfStack--;
+ ulValue >>= 8UL;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ pxTopOfStack--;
+ ulValue >>= 8UL;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- ulValue >>= 8UL;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- ulValue >>= 8UL;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ /* Followed by the CCR. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_CCR;
- /* Followed by the CCR. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_CCR;
+ /* Next all the general purpose registers - with the parameters being passed
+ in ER0. The parameter order must match that used by the compiler when the
+ "saveall" function attribute is used. */
- /* Next all the general purpose registers - with the parameters being passed
- * in ER0. The parameter order must match that used by the compiler when the
- * "saveall" function attribute is used. */
+ /* ER6 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66;
+
+ /* ER0 */
+ ulValue = ( uint32_t ) pvParameters;
- /* ER6 */
- pxTopOfStack--;
- *pxTopOfStack = 0x66;
- pxTopOfStack--;
- *pxTopOfStack = 0x66;
- pxTopOfStack--;
- *pxTopOfStack = 0x66;
- pxTopOfStack--;
- *pxTopOfStack = 0x66;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ pxTopOfStack--;
+ ulValue >>= 8UL;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ pxTopOfStack--;
+ ulValue >>= 8UL;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ pxTopOfStack--;
+ ulValue >>= 8UL;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+
+ /* ER1 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11;
- /* ER0 */
- ulValue = ( uint32_t ) pvParameters;
+ /* ER2 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- ulValue >>= 8UL;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- ulValue >>= 8UL;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- ulValue >>= 8UL;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ /* ER3 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
- /* ER1 */
- pxTopOfStack--;
- *pxTopOfStack = 0x11;
- pxTopOfStack--;
- *pxTopOfStack = 0x11;
- pxTopOfStack--;
- *pxTopOfStack = 0x11;
- pxTopOfStack--;
- *pxTopOfStack = 0x11;
+ /* ER4 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44;
- /* ER2 */
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
+ /* ER5 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55;
- /* ER3 */
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
-
- /* ER4 */
- pxTopOfStack--;
- *pxTopOfStack = 0x44;
- pxTopOfStack--;
- *pxTopOfStack = 0x44;
- pxTopOfStack--;
- *pxTopOfStack = 0x44;
- pxTopOfStack--;
- *pxTopOfStack = 0x44;
-
- /* ER5 */
- pxTopOfStack--;
- *pxTopOfStack = 0x55;
- pxTopOfStack--;
- *pxTopOfStack = 0x55;
- pxTopOfStack--;
- *pxTopOfStack = 0x55;
- pxTopOfStack--;
- *pxTopOfStack = 0x55;
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void * pxCurrentTCB;
+extern void * pxCurrentTCB;
- /* Setup the hardware to generate the tick. */
- prvSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. */
+ prvSetupTimerInterrupt();
- /* Restore the context of the first task that is going to run. This
- * mirrors the function epilogue code generated by the compiler when the
- * "saveall" function attribute is used. */
- asm volatile (
- "MOV.L @_pxCurrentTCB, ER6 \n\t"
- "MOV.L @ER6, ER7 \n\t"
- "LDM.L @SP+, (ER4-ER5) \n\t"
- "LDM.L @SP+, (ER0-ER3) \n\t"
- "MOV.L @ER7+, ER6 \n\t"
- "RTE \n\t"
- );
+ /* Restore the context of the first task that is going to run. This
+ mirrors the function epilogue code generated by the compiler when the
+ "saveall" function attribute is used. */
+ asm volatile (
+ "MOV.L @_pxCurrentTCB, ER6 \n\t"
+ "MOV.L @ER6, ER7 \n\t"
+ "LDM.L @SP+, (ER4-ER5) \n\t"
+ "LDM.L @SP+, (ER0-ER3) \n\t"
+ "MOV.L @ER7+, ER6 \n\t"
+ "RTE \n\t"
+ );
- ( void ) pxCurrentTCB;
+ ( void ) pxCurrentTCB;
- /* Should not get here. */
- return pdTRUE;
+ /* Should not get here. */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the h8 port will get stopped. */
+ /* It is unlikely that the h8 port will get stopped. */
}
/*-----------------------------------------------------------*/
@@ -227,56 +224,56 @@
*/
void vPortYield( void )
{
- portSAVE_STACK_POINTER();
- vTaskSwitchContext();
- portRESTORE_STACK_POINTER();
+ portSAVE_STACK_POINTER();
+ vTaskSwitchContext();
+ portRESTORE_STACK_POINTER();
}
/*-----------------------------------------------------------*/
-/*
- * The interrupt handler installed for the RTOS tick depends on whether the
- * preemptive or cooperative scheduler is being used.
+/*
+ * The interrupt handler installed for the RTOS tick depends on whether the
+ * preemptive or cooperative scheduler is being used.
*/
-#if ( configUSE_PREEMPTION == 1 )
+#if( configUSE_PREEMPTION == 1 )
-/*
- * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().
- * The function prologue saves the context so all we have to do is save
- * the stack pointer.
- */
- void vTickISR( void ) __attribute__( ( saveall, interrupt_handler ) );
- void vTickISR( void )
- {
- portSAVE_STACK_POINTER();
+ /*
+ * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().
+ * The function prologue saves the context so all we have to do is save
+ * the stack pointer.
+ */
+ void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+ void vTickISR( void )
+ {
+ portSAVE_STACK_POINTER();
+
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
+ /* Clear the interrupt. */
+ TSR1 &= ~0x01;
- /* Clear the interrupt. */
- TSR1 &= ~0x01;
+ portRESTORE_STACK_POINTER();
+ }
- portRESTORE_STACK_POINTER();
- }
+#else
-#else /* if ( configUSE_PREEMPTION == 1 ) */
+ /*
+ * The cooperative scheduler is being used so all we have to do is
+ * periodically increment the tick. This can just be a normal ISR and
+ * the "saveall" attribute is not required.
+ */
+ void vTickISR( void ) __attribute__ ( ( interrupt_handler ) );
+ void vTickISR( void )
+ {
+ xTaskIncrementTick();
-/*
- * The cooperative scheduler is being used so all we have to do is
- * periodically increment the tick. This can just be a normal ISR and
- * the "saveall" attribute is not required.
- */
- void vTickISR( void ) __attribute__( ( interrupt_handler ) );
- void vTickISR( void )
- {
- xTaskIncrementTick();
+ /* Clear the interrupt. */
+ TSR1 &= ~0x01;
+ }
- /* Clear the interrupt. */
- TSR1 &= ~0x01;
- }
-
-#endif /* if ( configUSE_PREEMPTION == 1 ) */
+#endif
/*-----------------------------------------------------------*/
/*
@@ -284,20 +281,23 @@
*/
static void prvSetupTimerInterrupt( void )
{
- const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;
+const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;
- /* Turn the module on. */
- MSTPCR &= ~portMSTP13;
+ /* Turn the module on. */
+ MSTPCR &= ~portMSTP13;
- /* Configure timer 1. */
- TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;
+ /* Configure timer 1. */
+ TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;
- /* Configure the compare match value for a tick of configTICK_RATE_HZ. */
- TGR1A = ulCompareMatch;
+ /* Configure the compare match value for a tick of configTICK_RATE_HZ. */
+ TGR1A = ulCompareMatch;
- /* Start the timer and enable the interrupt - we can do this here as
- * interrupts are globally disabled when this function is called. */
- TIER1 |= portTGRA_INTERRUPT_ENABLE;
- TSTR |= portTIMER_CHANNEL;
+ /* Start the timer and enable the interrupt - we can do this here as
+ interrupts are globally disabled when this function is called. */
+ TIER1 |= portTGRA_INTERRUPT_ENABLE;
+ TSTR |= portTIMER_CHANNEL;
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/GCC/H8S2329/portmacro.h b/portable/GCC/H8S2329/portmacro.h
index 6d7fbc7..48fdc2c 100644
--- a/portable/GCC/H8S2329/portmacro.h
+++ b/portable/GCC/H8S2329/portmacro.h
@@ -27,11 +27,11 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,95 +44,95 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint8_t
- #define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
- typedef portSTACK_TYPE StackType_t;
- typedef signed char BaseType_t;
- typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 2
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portYIELD() asm volatile ( "TRAPA #0" )
- #define portNOP() asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD() asm volatile( "TRAPA #0" )
+#define portNOP() asm volatile( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
- #define portENABLE_INTERRUPTS() asm volatile ( "ANDC #0x7F, CCR");
- #define portDISABLE_INTERRUPTS() asm volatile ( "ORC #0x80, CCR" );
+#define portENABLE_INTERRUPTS() asm volatile( "ANDC #0x7F, CCR" );
+#define portDISABLE_INTERRUPTS() asm volatile( "ORC #0x80, CCR" );
/* Push the CCR then disable interrupts. */
- #define portENTER_CRITICAL() \
- asm volatile ( "STC CCR, @-ER7" ); \
- portDISABLE_INTERRUPTS();
+#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \
+ portDISABLE_INTERRUPTS();
/* Pop the CCR to set the interrupt masking back to its previous state. */
- #define portEXIT_CRITICAL() asm volatile ( "LDC @ER7+, CCR" );
+#define portEXIT_CRITICAL() asm volatile( "LDC @ER7+, CCR" );
/*-----------------------------------------------------------*/
/* Task utilities. */
/* Context switch macros. These macros are very simple as the context
- * is saved simply by selecting the saveall attribute of the context switch
- * interrupt service routines. These macros save and restore the stack
- * pointer to the TCB. */
+is saved simply by selecting the saveall attribute of the context switch
+interrupt service routines. These macros save and restore the stack
+pointer to the TCB. */
- #define portSAVE_STACK_POINTER() \
- extern void * pxCurrentTCB; \
- \
- asm volatile ( \
- "MOV.L @_pxCurrentTCB, ER5 \n\t"\
- "MOV.L ER7, @ER5 \n\t"\
- ); \
- ( void ) pxCurrentTCB;
+#define portSAVE_STACK_POINTER() \
+extern void* pxCurrentTCB; \
+ \
+ asm volatile( \
+ "MOV.L @_pxCurrentTCB, ER5 \n\t" \
+ "MOV.L ER7, @ER5 \n\t" \
+ ); \
+ ( void ) pxCurrentTCB;
- #define portRESTORE_STACK_POINTER() \
- extern void * pxCurrentTCB; \
- \
- asm volatile ( \
- "MOV.L @_pxCurrentTCB, ER5 \n\t"\
- "MOV.L @ER5, ER7 \n\t"\
- ); \
- ( void ) pxCurrentTCB;
+#define portRESTORE_STACK_POINTER() \
+extern void* pxCurrentTCB; \
+ \
+ asm volatile( \
+ "MOV.L @_pxCurrentTCB, ER5 \n\t" \
+ "MOV.L @ER5, ER7 \n\t" \
+ ); \
+ ( void ) pxCurrentTCB;
/*-----------------------------------------------------------*/
/* Macros to allow a context switch from within an application ISR. */
- #define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
- #define portEXIT_SWITCHING_ISR( x ) \
- if( x ) \
- { \
- extern void vTaskSwitchContext( void ); \
- vTaskSwitchContext(); \
- } \
- } \
- portRESTORE_STACK_POINTER();
+#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
+
+#define portEXIT_SWITCHING_ISR( x ) \
+ if( x ) \
+ { \
+ extern void vTaskSwitchContext( void ); \
+ vTaskSwitchContext(); \
+ } \
+ } portRESTORE_STACK_POINTER();
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/HCS12/port.c b/portable/GCC/HCS12/port.c
index 086074f..55d9402 100644
--- a/portable/GCC/HCS12/port.c
+++ b/portable/GCC/HCS12/port.c
@@ -35,144 +35,143 @@
#include <sys/ports_def.h>
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the HCS12 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the HCS12 port.
+ *----------------------------------------------------------*/
/*
- * Configure a timer to generate the RTOS tick at the frequency specified
+ * Configure a timer to generate the RTOS tick at the frequency specified
* within FreeRTOSConfig.h.
*/
static void prvSetupTimerInterrupt( void );
/* NOTE: Interrupt service routines must be in non-banked memory - as does the
- * scheduler startup function. */
-#define ATTR_NEAR __attribute__( ( near ) )
+scheduler startup function. */
+#define ATTR_NEAR __attribute__((near))
/* Manual context switch function. This is the SWI ISR. */
-/* __attribute__((interrupt)) */
+// __attribute__((interrupt))
void ATTR_NEAR vPortYield( void );
/* Tick context switch function. This is the timer ISR. */
-/* __attribute__((interrupt)) */
+// __attribute__((interrupt))
void ATTR_NEAR vPortTickInterrupt( void );
/* Function in non-banked memory which actually switches to first task. */
BaseType_t ATTR_NEAR xStartSchedulerNear( void );
-/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
- * critical section should not be left (i.e. interrupts should not be re-enabled)
- * until the nesting depth reaches 0. This variable simply tracks the nesting
- * depth. Each task maintains it's own critical nesting depth variable so
- * uxCriticalNesting is saved and restored from the task stack during a context
- * switch. */
-volatile UBaseType_t uxCriticalNesting = 0x80; /* un-initialized */
+/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
+critical section should not be left (i.e. interrupts should not be re-enabled)
+until the nesting depth reaches 0. This variable simply tracks the nesting
+depth. Each task maintains it's own critical nesting depth variable so
+uxCriticalNesting is saved and restored from the task stack during a context
+switch. */
+volatile UBaseType_t uxCriticalNesting = 0x80; // un-initialized
/*-----------------------------------------------------------*/
-/*
- * See header file for description.
+/*
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. In this case the stack as
- * expected by the HCS12 RTI instruction. */
- /* The address of the task function is placed in the stack byte at a time. */
- *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 1 );
- *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 0 );
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. In this case the stack as
+ expected by the HCS12 RTI instruction. */
- /* Next are all the registers that form part of the task context. */
- /* Y register */
- *--pxTopOfStack = ( StackType_t ) 0xff;
- *--pxTopOfStack = ( StackType_t ) 0xee;
+ /* The address of the task function is placed in the stack byte at a time. */
+ *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
+ *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
- /* X register */
- *--pxTopOfStack = ( StackType_t ) 0xdd;
- *--pxTopOfStack = ( StackType_t ) 0xcc;
+ /* Next are all the registers that form part of the task context. */
- /* A register contains parameter high byte. */
- *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 0 );
+ /* Y register */
+ *--pxTopOfStack = ( StackType_t ) 0xff;
+ *--pxTopOfStack = ( StackType_t ) 0xee;
- /* B register contains parameter low byte. */
- *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 );
+ /* X register */
+ *--pxTopOfStack = ( StackType_t ) 0xdd;
+ *--pxTopOfStack = ( StackType_t ) 0xcc;
+
+ /* A register contains parameter high byte. */
+ *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
- /* CCR: Note that when the task starts interrupts will be enabled since
- * "I" bit of CCR is cleared */
- *--pxTopOfStack = ( StackType_t ) 0x80; /* keeps Stop disabled (MCU default) */
+ /* B register contains parameter low byte. */
+ *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
- /* tmp softregs used by GCC. Values right now don't matter. */
- __asm( "\n\
+ /* CCR: Note that when the task starts interrupts will be enabled since
+ "I" bit of CCR is cleared */
+ *--pxTopOfStack = ( StackType_t ) 0x80; // keeps Stop disabled (MCU default)
+
+ /* tmp softregs used by GCC. Values right now don't matter. */
+ __asm("\n\
movw _.frame, 2,-%0 \n\
movw _.tmp, 2,-%0 \n\
movw _.z, 2,-%0 \n\
movw _.xy, 2,-%0 \n\
;movw _.d2, 2,-%0 \n\
;movw _.d1, 2,-%0 \n\
- " : "=A" ( pxTopOfStack ) : "0" ( pxTopOfStack ) );
+ ": "=A"(pxTopOfStack) : "0"(pxTopOfStack) );
- #ifdef BANKED_MODEL
- /* The page of the task. */
- *--pxTopOfStack = 0x30; /* can only directly start in PPAGE 0x30 */
- #endif
-
- /* The critical nesting depth is initialised with 0 (meaning not in
- * a critical section). */
- *--pxTopOfStack = ( StackType_t ) 0x00;
+ #ifdef BANKED_MODEL
+ /* The page of the task. */
+ *--pxTopOfStack = 0x30; // can only directly start in PPAGE 0x30
+ #endif
+
+ /* The critical nesting depth is initialised with 0 (meaning not in
+ a critical section). */
+ *--pxTopOfStack = ( StackType_t ) 0x00;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the HCS12 port will get stopped. */
+ /* It is unlikely that the HCS12 port will get stopped. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- /* Enable hardware RTI timer */
- /* Ignores configTICK_RATE_HZ */
- RTICTL = 0x50; /* 16 MHz xtal: 976.56 Hz, 1024mS */
- CRGINT |= 0x80; /* RTIE */
+ /* Enable hardware RTI timer */
+ /* Ignores configTICK_RATE_HZ */
+ RTICTL = 0x50; // 16 MHz xtal: 976.56 Hz, 1024mS
+ CRGINT |= 0x80; // RTIE
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* xPortStartScheduler() does not start the scheduler directly because
- * the header file containing the xPortStartScheduler() prototype is part
- * of the common kernel code, and therefore cannot use the CODE_SEG pragma.
- * Instead it simply calls the locally defined xNearStartScheduler() -
- * which does use the CODE_SEG pragma. */
+ /* xPortStartScheduler() does not start the scheduler directly because
+ the header file containing the xPortStartScheduler() prototype is part
+ of the common kernel code, and therefore cannot use the CODE_SEG pragma.
+ Instead it simply calls the locally defined xNearStartScheduler() -
+ which does use the CODE_SEG pragma. */
- int16_t register d;
-
- __asm( "jmp xStartSchedulerNear ; will never return": "=d" ( d ) );
- return d;
+ int16_t register d;
+ __asm ("jmp xStartSchedulerNear ; will never return": "=d"(d));
+ return d;
}
/*-----------------------------------------------------------*/
BaseType_t xStartSchedulerNear( void )
{
- /* Configure the timer that will generate the RTOS tick. Interrupts are
- * disabled when this function is called. */
- prvSetupTimerInterrupt();
+ /* Configure the timer that will generate the RTOS tick. Interrupts are
+ disabled when this function is called. */
+ prvSetupTimerInterrupt();
- /* Restore the context of the first task. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the first task. */
+ portRESTORE_CONTEXT();
- portISR_TAIL();
+ portISR_TAIL();
- /* Should not get here! */
- return pdFALSE;
+ /* Should not get here! */
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
@@ -186,53 +185,53 @@
*/
void vPortYield( void )
{
- portISR_HEAD();
+ portISR_HEAD();
+ /* NOTE: This is the trap routine (swi) although not defined as a trap.
+ It will fill the stack the same way as an ISR in order to mix preemtion
+ and cooperative yield. */
- /* NOTE: This is the trap routine (swi) although not defined as a trap.
- * It will fill the stack the same way as an ISR in order to mix preemtion
- * and cooperative yield. */
+ portSAVE_CONTEXT();
+ vTaskSwitchContext();
+ portRESTORE_CONTEXT();
- portSAVE_CONTEXT();
- vTaskSwitchContext();
- portRESTORE_CONTEXT();
-
- portISR_TAIL();
+ portISR_TAIL();
}
/*-----------------------------------------------------------*/
/*
- * RTOS tick interrupt service routine. If the cooperative scheduler is
- * being used then this simply increments the tick count. If the
+ * RTOS tick interrupt service routine. If the cooperative scheduler is
+ * being used then this simply increments the tick count. If the
* preemptive scheduler is being used a context switch can occur.
*/
void vPortTickInterrupt( void )
{
- portISR_HEAD();
+ portISR_HEAD();
- /* Clear tick timer flag */
- CRGFLG = 0x80;
+ /* Clear tick timer flag */
+ CRGFLG = 0x80;
- #if configUSE_PREEMPTION == 1
- {
- /* A context switch might happen so save the context. */
- portSAVE_CONTEXT();
+ #if configUSE_PREEMPTION == 1
+ {
+ /* A context switch might happen so save the context. */
+ portSAVE_CONTEXT();
- /* Increment the tick ... */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* A context switch is necessary. */
- vTaskSwitchContext();
- }
+ /* Increment the tick ... */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* A context switch is necessary. */
+ vTaskSwitchContext();
+ }
- /* Restore the context of a task - which may be a different task
- * to that interrupted. */
- portRESTORE_CONTEXT();
- }
- #else /* if configUSE_PREEMPTION == 1 */
- {
- xTaskIncrementTick();
- }
- #endif /* if configUSE_PREEMPTION == 1 */
+ /* Restore the context of a task - which may be a different task
+ to that interrupted. */
+ portRESTORE_CONTEXT();
+ }
+ #else
+ {
+ xTaskIncrementTick();
+ }
+ #endif
- portISR_TAIL();
+ portISR_TAIL();
}
+
diff --git a/portable/GCC/HCS12/portmacro.h b/portable/GCC/HCS12/portmacro.h
index 6689b3e..d7ccb89 100644
--- a/portable/GCC/HCS12/portmacro.h
+++ b/portable/GCC/HCS12/portmacro.h
@@ -27,11 +27,11 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,38 +44,38 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint8_t
- #define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
- typedef portSTACK_TYPE StackType_t;
- typedef signed char BaseType_t;
- typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 1
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portYIELD() __asm( "swi" );
+#define portBYTE_ALIGNMENT 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD() __asm( "swi" );
/*-----------------------------------------------------------*/
/* Critical section handling. */
- #define portENABLE_INTERRUPTS() __asm( "cli" )
- #define portDISABLE_INTERRUPTS() __asm( "sei" )
+#define portENABLE_INTERRUPTS() __asm( "cli" )
+#define portDISABLE_INTERRUPTS() __asm( "sei" )
/*
* Disable interrupts before incrementing the count of critical section nesting.
@@ -83,29 +83,29 @@
* re-enabled. Once interrupts are disabled the nesting count can be accessed
* directly. Each task maintains its own nesting count.
*/
- #define portENTER_CRITICAL() \
- { \
- extern volatile UBaseType_t uxCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- uxCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ uxCriticalNesting++; \
+}
/*
* Interrupts are disabled so we can access the nesting count directly. If the
* nesting is found to be 0 (no nesting) then we are leaving the critical
* section and interrupts can be re-enabled.
*/
- #define portEXIT_CRITICAL() \
- { \
- extern volatile UBaseType_t uxCriticalNesting; \
- \
- uxCriticalNesting--; \
- if( uxCriticalNesting == 0 ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ \
+ uxCriticalNesting--; \
+ if( uxCriticalNesting == 0 ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
@@ -120,16 +120,15 @@
* register is also stored as part of the tasks context.
*/
- #ifdef BANKED_MODEL
-
-/*
- * Load the stack pointer for the task, then pull the critical nesting
- * count and PPAGE register from the stack. The remains of the
- * context are restored by the RTI instruction.
- */
- #define portRESTORE_CONTEXT() \
- { \
- __asm( " \n\
+#ifdef BANKED_MODEL
+ /*
+ * Load the stack pointer for the task, then pull the critical nesting
+ * count and PPAGE register from the stack. The remains of the
+ * context are restored by the RTI instruction.
+ */
+ #define portRESTORE_CONTEXT() \
+ { \
+ __asm( " \n\
.globl pxCurrentTCB ; void * \n\
.globl uxCriticalNesting ; char \n\
\n\
@@ -138,17 +137,17 @@
\n\
movb 1,sp+,uxCriticalNesting \n\
movb 1,sp+,0x30 ; PPAGE \n\
- " ); \
- }
+ " ); \
+ }
-/*
- * By the time this macro is called the processor has already stacked the
- * registers. Simply stack the nesting count and PPAGE value, then save
- * the task stack pointer.
- */
- #define portSAVE_CONTEXT() \
- { \
- __asm( " \n\
+ /*
+ * By the time this macro is called the processor has already stacked the
+ * registers. Simply stack the nesting count and PPAGE value, then save
+ * the task stack pointer.
+ */
+ #define portSAVE_CONTEXT() \
+ { \
+ __asm( " \n\
.globl pxCurrentTCB ; void * \n\
.globl uxCriticalNesting ; char \n\
\n\
@@ -157,18 +156,18 @@
\n\
ldx pxCurrentTCB \n\
sts 0,x ; Stack \n\
- " ); \
- }
- #else /* ifdef BANKED_MODEL */
+ " ); \
+ }
+#else
-/*
- * These macros are as per the BANKED versions above, but without saving
- * and restoring the PPAGE register.
- */
+ /*
+ * These macros are as per the BANKED versions above, but without saving
+ * and restoring the PPAGE register.
+ */
- #define portRESTORE_CONTEXT() \
- { \
- __asm( " \n\
+ #define portRESTORE_CONTEXT() \
+ { \
+ __asm( " \n\
.globl pxCurrentTCB ; void * \n\
.globl uxCriticalNesting ; char \n\
\n\
@@ -176,12 +175,12 @@
lds 0,x ; Stack \n\
\n\
movb 1,sp+,uxCriticalNesting \n\
- " ); \
- }
+ " ); \
+ }
- #define portSAVE_CONTEXT() \
- { \
- __asm( " \n\
+ #define portSAVE_CONTEXT() \
+ { \
+ __asm( " \n\
.globl pxCurrentTCB ; void * \n\
.globl uxCriticalNesting ; char \n\
\n\
@@ -189,29 +188,29 @@
\n\
ldx pxCurrentTCB \n\
sts 0,x ; Stack \n\
- " ); \
- }
- #endif /* ifdef BANKED_MODEL */
+ " ); \
+ }
+#endif
/*
* Utility macros to save/restore correct software registers for GCC. This is
* useful when GCC does not generate appropriate ISR head/tail code.
*/
- #define portISR_HEAD() \
- { \
- __asm( " \n\
+#define portISR_HEAD() \
+{ \
+ __asm(" \n\
movw _.frame, 2,-sp \n\
movw _.tmp, 2,-sp \n\
movw _.z, 2,-sp \n\
movw _.xy, 2,-sp \n\
;movw _.d2, 2,-sp \n\
;movw _.d1, 2,-sp \n\
- " ); \
- }
+ "); \
+}
- #define portISR_TAIL() \
- { \
- __asm( " \n\
+#define portISR_TAIL() \
+{ \
+ __asm(" \n\
movw 2,sp+, _.xy \n\
movw 2,sp+, _.z \n\
movw 2,sp+, _.tmp \n\
@@ -219,8 +218,8 @@
;movw 2,sp+, _.d1 \n\
;movw 2,sp+, _.d2 \n\
rti \n\
- " ); \
- }
+ "); \
+}
/*
* Utility macro to call macros above in correct order in order to perform a
@@ -229,18 +228,19 @@
* variables portYIELD() should be used in it's place.
*/
- #define portTASK_SWITCH_FROM_ISR() \
- portSAVE_CONTEXT(); \
- vTaskSwitchContext(); \
- portRESTORE_CONTEXT();
+#define portTASK_SWITCH_FROM_ISR() \
+ portSAVE_CONTEXT(); \
+ vTaskSwitchContext(); \
+ portRESTORE_CONTEXT();
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/IA32_flat/ISR_Support.h b/portable/GCC/IA32_flat/ISR_Support.h
index 82765dd..0222f49 100644
--- a/portable/GCC/IA32_flat/ISR_Support.h
+++ b/portable/GCC/IA32_flat/ISR_Support.h
@@ -25,102 +25,103 @@
* 1 tab == 4 spaces!
*/
-.extern ulTopOfSystemStack
- .extern ulInterruptNesting
+ .extern ulTopOfSystemStack
+ .extern ulInterruptNesting
/*-----------------------------------------------------------*/
- .macro portFREERTOS_INTERRUPT_ENTRY
+.macro portFREERTOS_INTERRUPT_ENTRY
-/* Save general purpose registers. */
-pusha
+ /* Save general purpose registers. */
+ pusha
-/* If ulInterruptNesting is zero the rest of the task context will need
- * saving and a stack switch might be required. */
-movl ulInterruptNesting, % eax
-test % eax, % eax
-jne 2f
+ /* If ulInterruptNesting is zero the rest of the task context will need
+ saving and a stack switch might be required. */
+ movl ulInterruptNesting, %eax
+ test %eax, %eax
+ jne 2f
-/* Interrupts are not nested, so save the rest of the task context. */
- .if configSUPPORT_FPU == 1
+ /* Interrupts are not nested, so save the rest of the task context. */
+ .if configSUPPORT_FPU == 1
-/* If the task has a buffer allocated to save the FPU context then
- * save the FPU context now. */
-movl pucPortTaskFPUContextBuffer, % eax
-test % eax, % eax
-je 1f
-fnsave( % eax ) /* Save FLOP context into ucTempFPUBuffer array. */
-fwait
+ /* If the task has a buffer allocated to save the FPU context then
+ save the FPU context now. */
+ movl pucPortTaskFPUContextBuffer, %eax
+ test %eax, %eax
+ je 1f
+ fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
+ fwait
-1 :
-/* Save the address of the FPU context, if any. */
-push pucPortTaskFPUContextBuffer
+ 1:
+ /* Save the address of the FPU context, if any. */
+ push pucPortTaskFPUContextBuffer
- .endif /* configSUPPORT_FPU */
+ .endif /* configSUPPORT_FPU */
-/* Find the TCB. */
-movl pxCurrentTCB, % eax
+ /* Find the TCB. */
+ movl pxCurrentTCB, %eax
-/* Stack location is first item in the TCB. */
- movl % esp, ( % eax )
+ /* Stack location is first item in the TCB. */
+ movl %esp, (%eax)
-/* Switch stacks. */
-movl ulTopOfSystemStack, % esp
-movl % esp, % ebp
+ /* Switch stacks. */
+ movl ulTopOfSystemStack, %esp
+ movl %esp, %ebp
-2 :
-/* Increment nesting count. */
-add $1, ulInterruptNesting
+ 2:
+ /* Increment nesting count. */
+ add $1, ulInterruptNesting
- .endm
+.endm
/*-----------------------------------------------------------*/
- .macro portINTERRUPT_EPILOGUE
+.macro portINTERRUPT_EPILOGUE
-cli
-sub $1, ulInterruptNesting
+ cli
+ sub $1, ulInterruptNesting
-/* If the nesting has unwound to zero. */
-movl ulInterruptNesting, % eax
- test % eax, % eax
- jne 2f
+ /* If the nesting has unwound to zero. */
+ movl ulInterruptNesting, %eax
+ test %eax, %eax
+ jne 2f
-/* If a yield was requested then select a new TCB now. */
-movl ulPortYieldPending, % eax
- test % eax, % eax
- je 1f
-movl $0, ulPortYieldPending
-call vTaskSwitchContext
+ /* If a yield was requested then select a new TCB now. */
+ movl ulPortYieldPending, %eax
+ test %eax, %eax
+ je 1f
+ movl $0, ulPortYieldPending
+ call vTaskSwitchContext
-1 :
-/* Stack location is first item in the TCB. */
-movl pxCurrentTCB, % eax movl( % eax ), % esp
+ 1:
+ /* Stack location is first item in the TCB. */
+ movl pxCurrentTCB, %eax
+ movl (%eax), %esp
- .if configSUPPORT_FPU == 1
+ .if configSUPPORT_FPU == 1
-/* Restore address of task's FPU context buffer. */
-pop pucPortTaskFPUContextBuffer
+ /* Restore address of task's FPU context buffer. */
+ pop pucPortTaskFPUContextBuffer
-/* If the task has a buffer allocated in which its FPU context is saved,
- * then restore it now. */
-movl pucPortTaskFPUContextBuffer, % eax
-test % eax, % eax
-je 1f
-frstor( % eax )
-1 :
-.endif
+ /* If the task has a buffer allocated in which its FPU context is saved,
+ then restore it now. */
+ movl pucPortTaskFPUContextBuffer, %eax
+ test %eax, %eax
+ je 1f
+ frstor ( %eax )
+ 1:
+ .endif
-2 :
-popa
+ 2:
+ popa
- .endm
+.endm
/*-----------------------------------------------------------*/
- .macro portFREERTOS_INTERRUPT_EXIT
+.macro portFREERTOS_INTERRUPT_EXIT
-portINTERRUPT_EPILOGUE
-/* EOI. */
-movl $0x00, ( 0xFEE000B0 )
-iret
+ portINTERRUPT_EPILOGUE
+ /* EOI. */
+ movl $0x00, (0xFEE000B0)
+ iret
- .endm
+.endm
diff --git a/portable/GCC/IA32_flat/port.c b/portable/GCC/IA32_flat/port.c
index 41b5220..1a20c8e 100644
--- a/portable/GCC/IA32_flat/port.c
+++ b/portable/GCC/IA32_flat/port.c
@@ -33,61 +33,61 @@
#include "task.h"
#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
- /* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-#if ( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )
- #warning configISR_STACK_SIZE is probably too small!
+#if( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )
+ #warning configISR_STACK_SIZE is probably too small!
#endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */
-#if ( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15
+#if( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15
#endif
-#if ( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
- #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU
+#if( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+ #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU
#endif
/* A critical section is exited when the critical section nesting count reaches
- * this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* Tasks are not created with a floating point context, but can be given a
- * floating point context after they have been created. A variable is stored as
- * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
- * does not have an FPU context, or any other value if the task does have an FPU
- * context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Only the IF bit is set so tasks start with interrupts enabled. */
-#define portINITIAL_EFLAGS ( 0x200UL )
+#define portINITIAL_EFLAGS ( 0x200UL )
/* Error interrupts are at the highest priority vectors. */
-#define portAPIC_LVT_ERROR_VECTOR ( 0xfe )
-#define portAPIC_SPURIOUS_INT_VECTOR ( 0xff )
+#define portAPIC_LVT_ERROR_VECTOR ( 0xfe )
+#define portAPIC_SPURIOUS_INT_VECTOR ( 0xff )
/* EFLAGS bits. */
-#define portEFLAGS_IF ( 0x200UL )
+#define portEFLAGS_IF ( 0x200UL )
/* FPU context size if FSAVE is used. */
-#define portFPU_CONTEXT_SIZE_BYTES 108
+#define portFPU_CONTEXT_SIZE_BYTES 108
/* The expected size of each entry in the IDT. Used to check structure packing
- * is set correctly. */
-#define portEXPECTED_IDT_ENTRY_SIZE 8
+ is set correctly. */
+#define portEXPECTED_IDT_ENTRY_SIZE 8
/* Default flags setting for entries in the IDT. */
-#define portIDT_FLAGS ( 0x8E )
+#define portIDT_FLAGS ( 0x8E )
/* This is the lowest possible ISR vector available to application code. */
-#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 )
+#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 )
/* If configASSERT() is defined then the system stack is filled with this value
- * to allow for a crude stack overflow check. */
-#define portSTACK_WORD ( 0xecececec )
+to allow for a crude stack overflow check. */
+#define portSTACK_WORD ( 0xecececec )
/*-----------------------------------------------------------*/
/*
@@ -103,9 +103,7 @@
/*
* Complete one descriptor in the IDT.
*/
-static void prvSetInterruptGate( uint8_t ucNumber,
- ISR_Handler_t pxHandlerFunction,
- uint8_t ucFlags );
+static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags );
/*
* The default handler installed in each IDT position.
@@ -136,417 +134,408 @@
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
- * variable must be initialised to a non zero value to ensure interrupts don't
- * inadvertently become unmasked before the scheduler starts. It is set to zero
- * before the first task starts executing. */
+variable must be initialised to a non zero value to ensure interrupts don't
+inadvertently become unmasked before the scheduler starts. It is set to zero
+before the first task starts executing. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* A structure used to map the various fields of an IDT entry into separate
- * structure members. */
+structure members. */
struct IDTEntry
{
- uint16_t usISRLow; /* Low 16 bits of handler address. */
- uint16_t usSegmentSelector; /* Flat model means this is not changed. */
- uint8_t ucZero; /* Must be set to zero. */
- uint8_t ucFlags; /* Flags for this entry. */
- uint16_t usISRHigh; /* High 16 bits of handler address. */
-}
-__attribute__( ( packed ) );
+ uint16_t usISRLow; /* Low 16 bits of handler address. */
+ uint16_t usSegmentSelector; /* Flat model means this is not changed. */
+ uint8_t ucZero; /* Must be set to zero. */
+ uint8_t ucFlags; /* Flags for this entry. */
+ uint16_t usISRHigh; /* High 16 bits of handler address. */
+} __attribute__( ( packed ) );
typedef struct IDTEntry IDTEntry_t;
/* Use to pass the location of the IDT to the CPU. */
struct IDTPointer
{
- uint16_t usTableLimit;
- uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */
-}
-__attribute__( ( __packed__ ) );
+ uint16_t usTableLimit;
+ uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */
+} __attribute__( ( __packed__ ) );
typedef struct IDTPointer IDTPointer_t;
/* The IDT itself. */
-static __attribute__( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];
+static __attribute__ ( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];
#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
-/* A table in which application defined interrupt handlers are stored. These
- * are called by the central interrupt handler if a common interrupt entry
- * point it used. */
- static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
+ /* A table in which application defined interrupt handlers are stored. These
+ are called by the central interrupt handler if a common interrupt entry
+ point it used. */
+ static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
#if ( configSUPPORT_FPU == 1 )
-/* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL
- * then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is
- * not NULL then it points to a buffer into which the FPU context can be saved. */
- uint8_t * pucPortTaskFPUContextBuffer __attribute__( ( used ) ) = pdFALSE;
+ /* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL
+ then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is
+ not NULL then it points to a buffer into which the FPU context can be saved. */
+ uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE;
#endif /* configSUPPORT_FPU */
/* The stack used by interrupt handlers. */
-static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__( ( used ) ) = { 0 };
+static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used)) = { 0 };
/* Don't use the very top of the system stack so the return address
- * appears as 0 if the debugger tries to unwind the stack. */
-volatile uint32_t ulTopOfSystemStack __attribute__( ( used ) ) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
+appears as 0 if the debugger tries to unwind the stack. */
+volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
/* If a yield is requested from an interrupt or from a critical section then
- * the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
- * instead to indicate the yield should be performed at the end of the interrupt
- * when the critical section is exited. */
-volatile uint32_t ulPortYieldPending __attribute__( ( used ) ) = pdFALSE;
+the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
+instead to indicate the yield should be performed at the end of the interrupt
+when the critical section is exited. */
+volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE;
/* Counts the interrupt nesting depth. Used to know when to switch to the
- * interrupt/system stack and when to save/restore a complete context. */
-volatile uint32_t ulInterruptNesting __attribute__( ( used ) ) = 0;
+interrupt/system stack and when to save/restore a complete context. */
+volatile uint32_t ulInterruptNesting __attribute__((used)) = 0;
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint32_t ulCodeSegment;
+uint32_t ulCodeSegment;
- /* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */
+ /* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
- /* Parameters first. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
+ /* Parameters first. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
- /* There is nothing to return to so assert if attempting to use the return
- * address. */
- *pxTopOfStack = ( StackType_t ) prvTaskExitError;
- pxTopOfStack--;
+ /* There is nothing to return to so assert if attempting to use the return
+ address. */
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError;
+ pxTopOfStack--;
- /* iret used to start the task pops up to here. */
- *pxTopOfStack = portINITIAL_EFLAGS;
- pxTopOfStack--;
+ /* iret used to start the task pops up to here. */
+ *pxTopOfStack = portINITIAL_EFLAGS;
+ pxTopOfStack--;
- /* CS */
- __asm volatile ( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );
- *pxTopOfStack = ulCodeSegment;
- pxTopOfStack--;
+ /* CS */
+ __asm volatile( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );
+ *pxTopOfStack = ulCodeSegment;
+ pxTopOfStack--;
- /* First instruction in the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
+ /* First instruction in the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
- /* General purpose registers as expected by a POPA instruction. */
- *pxTopOfStack = 0xEA;
- pxTopOfStack--;
+ /* General purpose registers as expected by a POPA instruction. */
+ *pxTopOfStack = 0xEA;
+ pxTopOfStack--;
- *pxTopOfStack = 0xEC;
- pxTopOfStack--;
+ *pxTopOfStack = 0xEC;
+ pxTopOfStack--;
- *pxTopOfStack = 0xED1; /* EDX */
- pxTopOfStack--;
+ *pxTopOfStack = 0xED1; /* EDX */
+ pxTopOfStack--;
- *pxTopOfStack = 0xEB1; /* EBX */
- pxTopOfStack--;
+ *pxTopOfStack = 0xEB1; /* EBX */
+ pxTopOfStack--;
- /* Hole for ESP. */
- pxTopOfStack--;
+ /* Hole for ESP. */
+ pxTopOfStack--;
- *pxTopOfStack = 0x00; /* EBP */
- pxTopOfStack--;
+ *pxTopOfStack = 0x00; /* EBP */
+ pxTopOfStack--;
- *pxTopOfStack = 0xE5; /* ESI */
- pxTopOfStack--;
+ *pxTopOfStack = 0xE5; /* ESI */
+ pxTopOfStack--;
- *pxTopOfStack = 0xeeeeeeee; /* EDI */
+ *pxTopOfStack = 0xeeeeeeee; /* EDI */
- #if ( configSUPPORT_FPU == 1 )
- {
- pxTopOfStack--;
+ #if ( configSUPPORT_FPU == 1 )
+ {
+ pxTopOfStack--;
- /* Buffer for FPU context, which is initialised to NULL as tasks are not
- * created with an FPU context. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
- }
- #endif /* configSUPPORT_FPU */
+ /* Buffer for FPU context, which is initialised to NULL as tasks are not
+ created with an FPU context. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ }
+ #endif /* configSUPPORT_FPU */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
-static void prvSetInterruptGate( uint8_t ucNumber,
- ISR_Handler_t pxHandlerFunction,
- uint8_t ucFlags )
+static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags )
{
- uint16_t usCodeSegment;
- uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
+uint16_t usCodeSegment;
+uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
- xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
- xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
+ xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
+ xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
- /* When the flat model is used the CS will never change. */
- __asm volatile ( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
- xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;
- xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
- xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
+ /* When the flat model is used the CS will never change. */
+ __asm volatile( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
+ xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;
+ xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
+ xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
}
/*-----------------------------------------------------------*/
void vPortSetupIDT( void )
{
- uint32_t ulNum;
- IDTPointer_t xIDT;
+uint32_t ulNum;
+IDTPointer_t xIDT;
- #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
- {
- for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ )
- {
- /* If a handler has not already been installed on this vector. */
- if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) )
- {
- prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS );
- }
- }
- }
- #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+ #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+ {
+ for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ )
+ {
+ /* If a handler has not already been installed on this vector. */
+ if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) )
+ {
+ prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS );
+ }
+ }
+ }
+ #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
- /* Set IDT address. */
- xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;
- xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;
+ /* Set IDT address. */
+ xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;
+ xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;
- /* Set IDT in CPU. */
- __asm volatile ( "lidt %0" ::"m" ( xIDT ) );
+ /* Set IDT in CPU. */
+ __asm volatile( "lidt %0" :: "m" (xIDT) );
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( ulCriticalNesting == ~0UL );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- extern void vPortAPICErrorHandlerWrapper( void );
- extern void vPortAPICSpuriousHandler( void );
+extern void vPortAPICErrorHandlerWrapper( void );
+extern void vPortAPICSpuriousHandler( void );
- /* Initialise LAPIC to a well known state. */
- portAPIC_LDR = 0xFFFFFFFF;
- portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );
- portAPIC_LVT_TIMER = portAPIC_DISABLE;
- portAPIC_LVT_PERF = portAPIC_NMI;
- portAPIC_LVT_LINT0 = portAPIC_DISABLE;
- portAPIC_LVT_LINT1 = portAPIC_DISABLE;
- portAPIC_TASK_PRIORITY = 0;
+ /* Initialise LAPIC to a well known state. */
+ portAPIC_LDR = 0xFFFFFFFF;
+ portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );
+ portAPIC_LVT_TIMER = portAPIC_DISABLE;
+ portAPIC_LVT_PERF = portAPIC_NMI;
+ portAPIC_LVT_LINT0 = portAPIC_DISABLE;
+ portAPIC_LVT_LINT1 = portAPIC_DISABLE;
+ portAPIC_TASK_PRIORITY = 0;
- /* Install APIC timer ISR vector. */
- prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS );
+ /* Install APIC timer ISR vector. */
+ prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS );
- /* Install API error handler. */
- prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS );
+ /* Install API error handler. */
+ prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS );
- /* Install Yield handler. */
- prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS );
+ /* Install Yield handler. */
+ prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS );
- /* Install spurious interrupt vector. */
- prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS );
+ /* Install spurious interrupt vector. */
+ prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS );
- /* Enable the APIC, mapping the spurious interrupt at the same time. */
- portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;
+ /* Enable the APIC, mapping the spurious interrupt at the same time. */
+ portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;
- /* Set timer error vector. */
- portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;
+ /* Set timer error vector. */
+ portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;
- /* Set the interrupt frequency. */
- portAPIC_TMRDIV = portAPIC_DIV_16;
- portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL;
+ /* Set the interrupt frequency. */
+ portAPIC_TMRDIV = portAPIC_DIV_16;
+ portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- BaseType_t xWord;
+BaseType_t xWord;
- /* Some versions of GCC require the -mno-ms-bitfields command line option
- * for packing to work. */
- configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );
+ /* Some versions of GCC require the -mno-ms-bitfields command line option
+ for packing to work. */
+ configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );
- /* Fill part of the system stack with a known value to help detect stack
- * overflow. A few zeros are left so GDB doesn't get confused unwinding
- * the stack. */
- for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )
- {
- ulSystemStack[ xWord ] = portSTACK_WORD;
- }
+ /* Fill part of the system stack with a known value to help detect stack
+ overflow. A few zeros are left so GDB doesn't get confused unwinding
+ the stack. */
+ for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )
+ {
+ ulSystemStack[ xWord ] = portSTACK_WORD;
+ }
- /* Initialise Interrupt Descriptor Table (IDT). */
- vPortSetupIDT();
+ /* Initialise Interrupt Descriptor Table (IDT). */
+ vPortSetupIDT();
- /* Initialise LAPIC and install system handlers. */
- prvSetupTimerInterrupt();
+ /* Initialise LAPIC and install system handlers. */
+ prvSetupTimerInterrupt();
- /* Make sure the stack used by interrupts is aligned. */
- ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK;
+ /* Make sure the stack used by interrupts is aligned. */
+ ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK;
- ulCriticalNesting = 0;
+ ulCriticalNesting = 0;
- /* Enable LAPIC Counter.*/
- portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;
+ /* Enable LAPIC Counter.*/
+ portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;
- /* Sometimes needed. */
- portAPIC_TMRDIV = portAPIC_DIV_16;
+ /* Sometimes needed. */
+ portAPIC_TMRDIV = portAPIC_DIV_16;
- /* Should not return from the following function as the scheduler will then
- * be executing the tasks. */
- vPortStartFirstTask();
+ /* Should not return from the following function as the scheduler will then
+ be executing the tasks. */
+ vPortStartFirstTask();
- return 0;
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- if( ulCriticalNesting == 0 )
- {
- #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
- {
- __asm volatile ( "cli" );
- }
- #else
- {
- portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
- configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
- }
- #endif
- }
+ if( ulCriticalNesting == 0 )
+ {
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+ {
+ __asm volatile( "cli" );
+ }
+ #else
+ {
+ portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
+ configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
+ }
+ #endif
+ }
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- * exited. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then all interrupt
- * priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- * should be unmasked. */
- #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
- {
- __asm volatile ( "sti" );
- }
- #else
- {
- portAPIC_TASK_PRIORITY = 0;
- }
- #endif
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+ {
+ __asm volatile( "sti" );
+ }
+ #else
+ {
+ portAPIC_TASK_PRIORITY = 0;
+ }
+ #endif
- /* If a yield was pended from within the critical section then
- * perform the yield now. */
- if( ulPortYieldPending != pdFALSE )
- {
- ulPortYieldPending = pdFALSE;
- __asm volatile ( portYIELD_INTERRUPT );
- }
- }
- }
+ /* If a yield was pended from within the critical section then
+ perform the yield now. */
+ if( ulPortYieldPending != pdFALSE )
+ {
+ ulPortYieldPending = pdFALSE;
+ __asm volatile( portYIELD_INTERRUPT );
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
uint32_t ulPortSetInterruptMask( void )
{
- volatile uint32_t ulOriginalMask;
+volatile uint32_t ulOriginalMask;
- /* Set mask to max syscall priority. */
- #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
- {
- /* Return whether interrupts were already enabled or not. Pop adjusts
- * the stack first. */
- __asm volatile ( "pushf \t\n"
- "pop %0 \t\n"
- "cli "
- : "=rm" ( ulOriginalMask )::"memory" );
+ /* Set mask to max syscall priority. */
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+ {
+ /* Return whether interrupts were already enabled or not. Pop adjusts
+ the stack first. */
+ __asm volatile( "pushf \t\n"
+ "pop %0 \t\n"
+ "cli "
+ : "=rm" (ulOriginalMask) :: "memory" );
- ulOriginalMask &= portEFLAGS_IF;
- }
- #else
- {
- /* Return original mask. */
- ulOriginalMask = portAPIC_TASK_PRIORITY;
- portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
- configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
- }
- #endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */
+ ulOriginalMask &= portEFLAGS_IF;
+ }
+ #else
+ {
+ /* Return original mask. */
+ ulOriginalMask = portAPIC_TASK_PRIORITY;
+ portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
+ configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
+ }
+ #endif
- return ulOriginalMask;
+ return ulOriginalMask;
}
/*-----------------------------------------------------------*/
void vPortClearInterruptMask( uint32_t ulNewMaskValue )
{
- #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
- {
- if( ulNewMaskValue != pdFALSE )
- {
- __asm volatile ( "sti" );
- }
- }
- #else
- {
- portAPIC_TASK_PRIORITY = ulNewMaskValue;
- configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );
- }
- #endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+ {
+ if( ulNewMaskValue != pdFALSE )
+ {
+ __asm volatile( "sti" );
+ }
+ }
+ #else
+ {
+ portAPIC_TASK_PRIORITY = ulNewMaskValue;
+ configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );
+ }
+ #endif
}
/*-----------------------------------------------------------*/
#if ( configSUPPORT_FPU == 1 )
- void vPortTaskUsesFPU( void )
- {
- /* A task is registering the fact that it needs an FPU context. Allocate a
- * buffer into which the context can be saved. */
- pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );
- configASSERT( pucPortTaskFPUContextBuffer );
+ void vPortTaskUsesFPU( void )
+ {
+ /* A task is registering the fact that it needs an FPU context. Allocate a
+ buffer into which the context can be saved. */
+ pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );
+ configASSERT( pucPortTaskFPUContextBuffer );
- /* Initialise the floating point registers. */
- __asm volatile ( "fninit" );
- }
+ /* Initialise the floating point registers. */
+ __asm volatile( "fninit" );
+ }
#endif /* configSUPPORT_FPU */
/*-----------------------------------------------------------*/
@@ -554,132 +543,144 @@
void vPortAPICErrorHandler( void )
{
/* Variable to hold the APIC error status for viewing in the debugger. */
- volatile uint32_t ulErrorStatus = 0;
+volatile uint32_t ulErrorStatus = 0;
- portAPIC_ERROR_STATUS = 0;
- ulErrorStatus = portAPIC_ERROR_STATUS;
- ( void ) ulErrorStatus;
+ portAPIC_ERROR_STATUS = 0;
+ ulErrorStatus = portAPIC_ERROR_STATUS;
+ ( void ) ulErrorStatus;
- /* Force an assert. */
- configASSERT( ulCriticalNesting == ~0UL );
+ /* Force an assert. */
+ configASSERT( ulCriticalNesting == ~0UL );
}
/*-----------------------------------------------------------*/
-#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+#if( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
- void vPortCentralInterruptHandler( uint32_t ulVector )
- {
- if( ulVector < portNUM_VECTORS )
- {
- if( xInterruptHandlerTable[ ulVector ] != NULL )
- {
- ( xInterruptHandlerTable[ ulVector ] )();
- }
- }
+ void vPortCentralInterruptHandler( uint32_t ulVector )
+ {
+ if( ulVector < portNUM_VECTORS )
+ {
+ if( xInterruptHandlerTable[ ulVector ] != NULL )
+ {
+ ( xInterruptHandlerTable[ ulVector ] )();
+ }
+ }
- /* Check for a system stack overflow. */
- configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD );
- configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD );
- configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD );
- }
+ /* Check for a system stack overflow. */
+ configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD );
+ configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD );
+ configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD );
+ }
#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
/*-----------------------------------------------------------*/
#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
- BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler,
- uint32_t ulVectorNumber )
- {
- BaseType_t xReturn;
+ BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
+ {
+ BaseType_t xReturn;
- xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
+ xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
- if( xReturn != pdFAIL )
- {
- /* Save the handler passed in by the application in the vector number
- * passed in. The addresses are then called from the central interrupt
- * handler. */
- xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;
- }
+ if( xReturn != pdFAIL )
+ {
+ /* Save the handler passed in by the application in the vector number
+ passed in. The addresses are then called from the central interrupt
+ handler. */
+ xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;
+ }
- return xReturn;
- }
+ return xReturn;
+ }
#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
/*-----------------------------------------------------------*/
-BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler,
- uint32_t ulVectorNumber )
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
{
- BaseType_t xReturn;
+BaseType_t xReturn;
- xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
+ xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
- if( xReturn != pdFAIL )
- {
- taskENTER_CRITICAL();
- {
- /* Update the IDT to include the application defined handler. */
- prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS );
- }
- taskEXIT_CRITICAL();
- }
+ if( xReturn != pdFAIL )
+ {
+ taskENTER_CRITICAL();
+ {
+ /* Update the IDT to include the application defined handler. */
+ prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS );
+ }
+ taskEXIT_CRITICAL();
+ }
- return xReturn;
+ return xReturn;
}
/*-----------------------------------------------------------*/
static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber )
{
- BaseType_t xReturn;
+BaseType_t xReturn;
- /* Check validity of vector number. */
- if( ulVectorNumber >= portNUM_VECTORS )
- {
- /* Too high. */
- xReturn = pdFAIL;
- }
- else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR )
- {
- /* Too low. */
- xReturn = pdFAIL;
- }
- else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR )
- {
- /* In use by FreeRTOS. */
- xReturn = pdFAIL;
- }
- else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR )
- {
- /* In use by FreeRTOS. */
- xReturn = pdFAIL;
- }
- else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR )
- {
- /* In use by FreeRTOS. */
- xReturn = pdFAIL;
- }
- else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR )
- {
- /* In use by FreeRTOS. */
- xReturn = pdFAIL;
- }
- else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL )
- {
- /* Already in use by the application. */
- xReturn = pdFAIL;
- }
- else
- {
- xReturn = pdPASS;
- }
+ /* Check validity of vector number. */
+ if( ulVectorNumber >= portNUM_VECTORS )
+ {
+ /* Too high. */
+ xReturn = pdFAIL;
+ }
+ else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR )
+ {
+ /* Too low. */
+ xReturn = pdFAIL;
+ }
+ else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR )
+ {
+ /* In use by FreeRTOS. */
+ xReturn = pdFAIL;
+ }
+ else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR )
+ {
+ /* In use by FreeRTOS. */
+ xReturn = pdFAIL;
+ }
+ else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR )
+ {
+ /* In use by FreeRTOS. */
+ xReturn = pdFAIL;
+ }
+ else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR )
+ {
+ /* In use by FreeRTOS. */
+ xReturn = pdFAIL;
+ }
+ else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL )
+ {
+ /* Already in use by the application. */
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ xReturn = pdPASS;
+ }
- return xReturn;
+ return xReturn;
}
/*-----------------------------------------------------------*/
void vGenerateYieldInterrupt( void )
{
- __asm volatile ( portYIELD_INTERRUPT );
+ __asm volatile( portYIELD_INTERRUPT );
}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/portable/GCC/IA32_flat/portmacro.h b/portable/GCC/IA32_flat/portmacro.h
index 4041858..012207f 100644
--- a/portable/GCC/IA32_flat/portmacro.h
+++ b/portable/GCC/IA32_flat/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,255 +43,249 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL )
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL )
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 32
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 32
/*-----------------------------------------------------------*/
/* Task utilities. */
/* The interrupt priority (for vectors 16 to 255) is determined using vector/16.
- * The quotient is rounded to the nearest integer with 1 being the lowest priority
- * and 15 is the highest. Therefore the following two interrupts are at the lowest
- * priority. *NOTE 1* If the yield vector is changed then it must also be changed
- * in the portYIELD_INTERRUPT definition immediately below. */
- #define portAPIC_TIMER_INT_VECTOR ( 0x21 )
- #define portAPIC_YIELD_INT_VECTOR ( 0x20 )
+The quotient is rounded to the nearest integer with 1 being the lowest priority
+and 15 is the highest. Therefore the following two interrupts are at the lowest
+priority. *NOTE 1* If the yield vector is changed then it must also be changed
+in the portYIELD_INTERRUPT definition immediately below. */
+#define portAPIC_TIMER_INT_VECTOR ( 0x21 )
+#define portAPIC_YIELD_INT_VECTOR ( 0x20 )
/* Build yield interrupt instruction. */
- #define portYIELD_INTERRUPT "int $0x20"
+#define portYIELD_INTERRUPT "int $0x20"
/* APIC register addresses. */
- #define portAPIC_EOI ( *( ( volatile uint32_t * ) 0xFEE000B0UL ) )
+#define portAPIC_EOI ( *( ( volatile uint32_t * ) 0xFEE000B0UL ) )
/* APIC bit definitions. */
- #define portAPIC_ENABLE_BIT ( 1UL << 8UL )
- #define portAPIC_TIMER_PERIODIC ( 1UL << 17UL )
- #define portAPIC_DISABLE ( 1UL << 16UL )
- #define portAPIC_NMI ( 4 << 8 )
- #define portAPIC_DIV_16 ( 0x03 )
+#define portAPIC_ENABLE_BIT ( 1UL << 8UL )
+#define portAPIC_TIMER_PERIODIC ( 1UL << 17UL )
+#define portAPIC_DISABLE ( 1UL << 16UL )
+#define portAPIC_NMI ( 4 << 8)
+#define portAPIC_DIV_16 ( 0x03 )
/* Define local API register addresses. */
- #define portAPIC_ID_REGISTER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL ) ) )
- #define portAPIC_SPURIOUS_INT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL ) ) )
- #define portAPIC_LVT_TIMER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) )
- #define portAPIC_TIMER_INITIAL_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) )
- #define portAPIC_TIMER_CURRENT_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) )
- #define portAPIC_TASK_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL ) ) )
- #define portAPIC_LVT_ERROR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) )
- #define portAPIC_ERROR_STATUS ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) )
- #define portAPIC_LDR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL ) ) )
- #define portAPIC_TMRDIV ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) )
- #define portAPIC_LVT_PERF ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) )
- #define portAPIC_LVT_LINT0 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) )
- #define portAPIC_LVT_LINT1 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) )
+#define portAPIC_ID_REGISTER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL ) ) )
+#define portAPIC_SPURIOUS_INT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL ) ) )
+#define portAPIC_LVT_TIMER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) )
+#define portAPIC_TIMER_INITIAL_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) )
+#define portAPIC_TIMER_CURRENT_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) )
+#define portAPIC_TASK_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL ) ) )
+#define portAPIC_LVT_ERROR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) )
+#define portAPIC_ERROR_STATUS ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) )
+#define portAPIC_LDR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL ) ) )
+#define portAPIC_TMRDIV ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) )
+#define portAPIC_LVT_PERF ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) )
+#define portAPIC_LVT_LINT0 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) )
+#define portAPIC_LVT_LINT1 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) )
/* Don't yield if inside a critical section - instead hold the yield pending
- * so it is performed when the critical section is exited. */
- #define portYIELD() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile uint32_t ulPortYieldPending; \
- if( ulCriticalNesting != 0 ) \
- { \
- ulPortYieldPending = pdTRUE; \
- } \
- else \
- { \
- __asm volatile ( portYIELD_INTERRUPT ); \
- } \
- }
+so it is performed when the critical section is exited. */
+#define portYIELD() \
+{ \
+extern volatile uint32_t ulCriticalNesting; \
+extern volatile uint32_t ulPortYieldPending; \
+ if( ulCriticalNesting != 0 ) \
+ { \
+ ulPortYieldPending = pdTRUE; \
+ } \
+ else \
+ { \
+ __asm volatile( portYIELD_INTERRUPT ); \
+ } \
+}
/* Called at the end of an ISR that can cause a context switch - pend a yield if
- * xSwithcRequired is not false. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern volatile uint32_t ulPortYieldPending; \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldPending = 1; \
- } \
- }
+xSwithcRequired is not false. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+{ \
+extern volatile uint32_t ulPortYieldPending; \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldPending = 1; \
+ } \
+}
/* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------
-* Critical section control
-*----------------------------------------------------------*/
+ * Critical section control
+ *----------------------------------------------------------*/
/* Critical sections for use in interrupts. */
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask( x )
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern uint32_t ulPortSetInterruptMask( void );
- extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
/* These macros do not globally disable/enable interrupts. They do mask off
- * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
- #define portDISABLE_INTERRUPTS() __asm volatile ( "cli" )
- #define portENABLE_INTERRUPTS() __asm volatile ( "sti" )
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() __asm volatile( "cli" )
+#define portENABLE_INTERRUPTS() __asm volatile( "sti" )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not required for this port but included in case common demo code that uses these
- * macros is used. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Architecture specific optimisations. */
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Store/clear the ready priorities in a bit map. */
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
- __asm volatile ( "bsr %1, %0\n\t" \
- : "=r" ( uxTopPriority ) : "rm" ( uxReadyPriorities ) : "cc" )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
+ __asm volatile( "bsr %1, %0\n\t" \
+ :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
- #define portNOP() __asm volatile ( "NOP" )
+#define portNOP() __asm volatile( "NOP" )
/*-----------------------------------------------------------
-* Misc
-*----------------------------------------------------------*/
+ * Misc
+ *----------------------------------------------------------*/
- #define portNUM_VECTORS 256
- #define portMAX_PRIORITY 15
- typedef void ( * ISR_Handler_t ) ( void );
+#define portNUM_VECTORS 256
+#define portMAX_PRIORITY 15
+typedef void ( *ISR_Handler_t ) ( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- * before any floating point instructions are executed. */
- #ifndef configSUPPORT_FPU
- #define configSUPPORT_FPU 0
- #endif
+before any floating point instructions are executed. */
+#ifndef configSUPPORT_FPU
+ #define configSUPPORT_FPU 0
+#endif
- #if configSUPPORT_FPU == 1
- void vPortTaskUsesFPU( void );
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
- #endif
+#if configSUPPORT_FPU == 1
+ void vPortTaskUsesFPU( void );
+ #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#endif
/* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition
- * below. */
- BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler,
- uint32_t ulVectorNumber );
- BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler,
- uint32_t ulVectorNumber );
+below. */
+BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
- #ifndef configAPIC_BASE
+#ifndef configAPIC_BASE
+ /* configAPIC_BASE_ADDRESS sets the base address of the local APIC. It can
+ be overridden in FreeRTOSConfig.h should it not be constant. */
+ #define configAPIC_BASE 0xFEE00000UL
+#endif
-/* configAPIC_BASE_ADDRESS sets the base address of the local APIC. It can
- * be overridden in FreeRTOSConfig.h should it not be constant. */
- #define configAPIC_BASE 0xFEE00000UL
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ /* The FreeRTOS scheduling algorithm selects the task that will enter the
+ Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
+ that is done.
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
+ enter the Running state is selected using a portable algorithm written in
+ C. This is the slowest method, but the algorithm does not restrict the
+ maximum number of unique RTOS task priorities that are available.
-/* The FreeRTOS scheduling algorithm selects the task that will enter the
- * Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
- * that is done.
- *
- * If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
- * enter the Running state is selected using a portable algorithm written in
- * C. This is the slowest method, but the algorithm does not restrict the
- * maximum number of unique RTOS task priorities that are available.
- *
- * If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
- * enter the Running state is selected using a single assembly instruction.
- * This is the fastest method, but restricts the maximum number of unique RTOS
- * task priorities to 32 (the same task priority can be assigned to any number
- * of RTOS tasks). */
- #warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+ If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
+ enter the Running state is selected using a single assembly instruction.
+ This is the fastest method, but restricts the maximum number of unique RTOS
+ task priorities to 32 (the same task priority can be assigned to any number
+ of RTOS tasks). */
+ #warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT
+#ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT
+ /* There are two ways of implementing interrupt handlers:
-/* There are two ways of implementing interrupt handlers:
- *
- * 1) As standard C functions -
- *
- * This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
- * is set to 1. The C function is installed using
- * xPortRegisterCInterruptHandler().
- *
- * This is the simplest of the two methods but incurs a slightly longer
- * interrupt entry time.
- *
- * 2) By using an assembly stub that wraps the handler in the FreeRTOS
- * portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
- *
- * This method can always be used. It is slightly more complex than
- * method 1 but benefits from a faster interrupt entry time. */
- #warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1.
- #define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1
- #endif
+ 1) As standard C functions -
- #ifndef configISR_STACK_SIZE
+ This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
+ is set to 1. The C function is installed using
+ xPortRegisterCInterruptHandler().
-/* Interrupt entry code will switch the stack in use to a dedicated system
- * stack.
- *
- * configISR_STACK_SIZE defines the number of 32-bit values that can be stored
- * on the system stack, and must be large enough to hold a potentially nested
- * interrupt stack frame. */
+ This is the simplest of the two methods but incurs a slightly longer
+ interrupt entry time.
- #error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h.
- #endif
+ 2) By using an assembly stub that wraps the handler in the FreeRTOS
+ portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
- #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+ This method can always be used. It is slightly more complex than
+ method 1 but benefits from a faster interrupt entry time. */
+ #warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1.
+ #define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1
+#endif
-/* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not
- * be called from an interrupt that has a priority above that set by
- * configMAX_API_CALL_INTERRUPT_PRIORITY. */
- #warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10
- #define configMAX_API_CALL_INTERRUPT_PRIORITY 10
- #endif
+#ifndef configISR_STACK_SIZE
+ /* Interrupt entry code will switch the stack in use to a dedicated system
+ stack.
- #ifndef configSUPPORT_FPU
- #warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0
- #define configSUPPORT_FPU 0
- #endif
+ configISR_STACK_SIZE defines the number of 32-bit values that can be stored
+ on the system stack, and must be large enough to hold a potentially nested
+ interrupt stack frame. */
+
+ #error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h.
+#endif
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+ /* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not
+ be called from an interrupt that has a priority above that set by
+ configMAX_API_CALL_INTERRUPT_PRIORITY. */
+ #warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10
+ #define configMAX_API_CALL_INTERRUPT_PRIORITY 10
+#endif
+
+#ifndef configSUPPORT_FPU
+ #warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0
+ #define configSUPPORT_FPU 0
+#endif
/* The value written to the task priority register to raise the interrupt mask
- * to the maximum from which FreeRTOS API calls can be made. */
- #define portAPIC_PRIORITY_SHIFT ( 4UL )
- #define portAPIC_MAX_SUB_PRIORITY ( 0x0fUL )
- #define portMAX_API_CALL_PRIORITY ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )
+to the maximum from which FreeRTOS API calls can be made. */
+#define portAPIC_PRIORITY_SHIFT ( 4UL )
+#define portAPIC_MAX_SUB_PRIORITY ( 0x0fUL )
+#define portMAX_API_CALL_PRIORITY ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )
/* Asserts if interrupt safe FreeRTOS functions are called from a priority
- * above the max system call interrupt priority. */
- #define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) )
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )
+above the max system call interrupt priority. */
+#define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) )
+#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )
- #ifdef __cplusplus
- } /* extern C */
- #endif
+#ifdef __cplusplus
+ } /* extern C */
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/MCF5235/port.c b/portable/GCC/MCF5235/port.c
index 58b2569..092ea51 100644
--- a/portable/GCC/MCF5235/port.c
+++ b/portable/GCC/MCF5235/port.c
@@ -1,55 +1,55 @@
/*
- * FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
- * MCF5235 Port - Copyright (C) 2006 Christian Walter.
- *
- * This file is part of the FreeRTOS distribution.
- *
- * FreeRTOS is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License** as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * FreeRTOS is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with FreeRTOS; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * A special exception to the GPL can be applied should you wish to distribute
- * a combined work that includes FreeRTOS, without being obliged to provide
- * the source code for any proprietary components. See the licensing section
- * of http://www.FreeRTOS.org for full details of how and when the exception
- * can be applied.
- *
- ***************************************************************************
- ***************************************************************************
- * *
- * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
- * *
- * This is a concise, step by step, 'hands on' guide that describes both *
- * general multitasking concepts and FreeRTOS specifics. It presents and *
- * explains numerous examples that are written using the FreeRTOS API. *
- * Full source code for all the examples is provided in an accompanying *
- * .zip file. *
- * *
- ***************************************************************************
- ***************************************************************************
- *
- * Please ensure to read the configuration and relevant port sections of the
- * online documentation.
- *
- * http://www.FreeRTOS.org - Documentation, latest information, license and
- * contact details.
- *
- * http://www.SafeRTOS.com - A version that is certified for use in safety
- * critical systems.
- *
- * http://www.OpenRTOS.com - Commercial support, development, porting,
- * licensing and training services.
- */
+ FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
+ MCF5235 Port - Copyright (C) 2006 Christian Walter.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License** as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ FreeRTOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with FreeRTOS; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+ A special exception to the GPL can be applied should you wish to distribute
+ a combined work that includes FreeRTOS, without being obliged to provide
+ the source code for any proprietary components. See the licensing section
+ of http://www.FreeRTOS.org for full details of how and when the exception
+ can be applied.
+
+ ***************************************************************************
+ ***************************************************************************
+ * *
+ * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
+ * *
+ * This is a concise, step by step, 'hands on' guide that describes both *
+ * general multitasking concepts and FreeRTOS specifics. It presents and *
+ * explains numerous examples that are written using the FreeRTOS API. *
+ * Full source code for all the examples is provided in an accompanying *
+ * .zip file. *
+ * *
+ ***************************************************************************
+ ***************************************************************************
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
#include <stdlib.h>
@@ -58,52 +58,52 @@
#include "task.h"
/* ------------------------ Types ----------------------------------------- */
-typedef volatile uint32_t vuint32;
-typedef volatile uint16_t vuint16;
-typedef volatile uint8_t vuint8;
+typedef volatile uint32_t vuint32;
+typedef volatile uint16_t vuint16;
+typedef volatile uint8_t vuint8;
/* ------------------------ Defines --------------------------------------- */
-#define portVECTOR_TABLE __RAMVEC
-#define portVECTOR_SYSCALL ( 32 + portTRAP_YIELD )
-#define portVECTOR_TIMER ( 64 + 36 )
+#define portVECTOR_TABLE __RAMVEC
+#define portVECTOR_SYSCALL ( 32 + portTRAP_YIELD )
+#define portVECTOR_TIMER ( 64 + 36 )
-#define MCF_PIT_PRESCALER 512UL
-#define MCF_PIT_TIMER_TICKS ( FSYS_2 / MCF_PIT_PRESCALER )
-#define MCF_PIT_MODULUS_REGISTER( freq ) ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL )
+#define MCF_PIT_PRESCALER 512UL
+#define MCF_PIT_TIMER_TICKS ( FSYS_2 / MCF_PIT_PRESCALER )
+#define MCF_PIT_MODULUS_REGISTER(freq) ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL)
-#define MCF_PIT_PMR0 ( *( vuint16 * ) ( void * ) ( &__IPSBAR[ 0x150002 ] ) )
-#define MCF_PIT_PCSR0 ( *( vuint16 * ) ( void * ) ( &__IPSBAR[ 0x150000 ] ) )
-#define MCF_PIT_PCSR_PRE( x ) ( ( ( x ) & 0x000F ) << 8 )
-#define MCF_PIT_PCSR_EN ( 0x0001 )
-#define MCF_PIT_PCSR_RLD ( 0x0002 )
-#define MCF_PIT_PCSR_PIF ( 0x0004 )
-#define MCF_PIT_PCSR_PIE ( 0x0008 )
-#define MCF_PIT_PCSR_OVW ( 0x0010 )
-#define MCF_INTC0_ICR36 ( *( vuint8 * ) ( void * ) ( &__IPSBAR[ 0x000C64 ] ) )
-#define MCF_INTC0_IMRH ( *( vuint32 * ) ( void * ) ( &__IPSBAR[ 0x000C08 ] ) )
-#define MCF_INTC0_IMRH_INT_MASK36 ( 0x00000010 )
-#define MCF_INTC0_IMRH_MASKALL ( 0x00000001 )
-#define MCF_INTC0_ICRn_IP( x ) ( ( ( x ) & 0x07 ) << 0 )
-#define MCF_INTC0_ICRn_IL( x ) ( ( ( x ) & 0x07 ) << 3 )
+#define MCF_PIT_PMR0 ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150002 ] ) )
+#define MCF_PIT_PCSR0 ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150000 ] ) )
+#define MCF_PIT_PCSR_PRE(x) ( ( ( x ) & 0x000F ) << 8 )
+#define MCF_PIT_PCSR_EN ( 0x0001 )
+#define MCF_PIT_PCSR_RLD ( 0x0002 )
+#define MCF_PIT_PCSR_PIF ( 0x0004 )
+#define MCF_PIT_PCSR_PIE ( 0x0008 )
+#define MCF_PIT_PCSR_OVW ( 0x0010 )
+#define MCF_INTC0_ICR36 ( *( vuint8 * )( void * )( &__IPSBAR[ 0x000C64 ] ) )
+#define MCF_INTC0_IMRH ( *( vuint32 * )( void * )( &__IPSBAR[ 0x000C08 ] ) )
+#define MCF_INTC0_IMRH_INT_MASK36 ( 0x00000010 )
+#define MCF_INTC0_IMRH_MASKALL ( 0x00000001 )
+#define MCF_INTC0_ICRn_IP(x) ( ( ( x ) & 0x07 ) << 0 )
+#define MCF_INTC0_ICRn_IL(x) ( ( ( x ) & 0x07 ) << 3 )
#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
#define portINITIAL_CRITICAL_NESTING ( ( uint32_t ) 10 )
/* ------------------------ Static variables ------------------------------ */
-volatile uint32_t ulCriticalNesting = portINITIAL_CRITICAL_NESTING;
+volatile uint32_t ulCriticalNesting = portINITIAL_CRITICAL_NESTING;
/* ------------------------ Static functions ------------------------------ */
#if configUSE_PREEMPTION == 0
- static void prvPortPreemptiveTick( void ) __attribute__( ( interrupt_handler ) );
+static void prvPortPreemptiveTick ( void ) __attribute__ ((interrupt_handler));
#else
- static void prvPortPreemptiveTick( void );
+static void prvPortPreemptiveTick ( void );
#endif
/* ------------------------ Start implementation -------------------------- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *
+pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode,
+ void *pvParameters )
{
/* Place the parameter on the stack in the expected location. */
*pxTopOfStack = ( StackType_t ) pvParameters;
@@ -129,35 +129,35 @@
*pxTopOfStack = 0;
*pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xA6; /* A6 / FP */
+ *pxTopOfStack = ( StackType_t ) 0xA6; /* A6 / FP */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xA5; /* A5 */
+ *pxTopOfStack = ( StackType_t ) 0xA5; /* A5 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xA4; /* A4 */
+ *pxTopOfStack = ( StackType_t ) 0xA4; /* A4 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xA3; /* A3 */
+ *pxTopOfStack = ( StackType_t ) 0xA3; /* A3 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xA2; /* A2 */
+ *pxTopOfStack = ( StackType_t ) 0xA2; /* A2 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xA1; /* A1 */
+ *pxTopOfStack = ( StackType_t ) 0xA1; /* A1 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xA0; /* A0 */
+ *pxTopOfStack = ( StackType_t ) 0xA0; /* A0 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xD7; /* D7 */
+ *pxTopOfStack = ( StackType_t ) 0xD7; /* D7 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xD6; /* D6 */
+ *pxTopOfStack = ( StackType_t ) 0xD6; /* D6 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xD5; /* D5 */
+ *pxTopOfStack = ( StackType_t ) 0xD5; /* D5 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xD4; /* D4 */
+ *pxTopOfStack = ( StackType_t ) 0xD4; /* D4 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xD3; /* D3 */
+ *pxTopOfStack = ( StackType_t ) 0xD3; /* D3 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xD2; /* D2 */
+ *pxTopOfStack = ( StackType_t ) 0xD2; /* D2 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xD1; /* D1 */
+ *pxTopOfStack = ( StackType_t ) 0xD1; /* D1 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xD0; /* D0 */
+ *pxTopOfStack = ( StackType_t ) 0xD0; /* D0 */
return pxTopOfStack;
}
@@ -165,64 +165,65 @@
/*
* Called by portYIELD() or taskYIELD() to manually force a context switch.
*/
-static void prvPortYield( void )
+static void
+prvPortYield( void )
{
asm volatile ( "move.w #0x2700, %sr\n\t" );
- #if _GCC_USES_FP == 1
- asm volatile ( "unlk %fp\n\t" );
- #endif
- /* Perform the context switch. First save the context of the current task. */
- portSAVE_CONTEXT();
+#if _GCC_USES_FP == 1
+ asm volatile ( "unlk %fp\n\t" );
+#endif
+ /* Perform the context switch. First save the context of the current task. */
+ portSAVE_CONTEXT( );
/* Find the highest priority task that is ready to run. */
- vTaskSwitchContext();
+ vTaskSwitchContext( );
/* Restore the context of the new task. */
- portRESTORE_CONTEXT();
+ portRESTORE_CONTEXT( );
}
#if configUSE_PREEMPTION == 0
-
/*
* The ISR used for the scheduler tick depends on whether the cooperative or
* the preemptive scheduler is being used.
*/
- static void prvPortPreemptiveTick( void )
- {
- /* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick.
- */
+static void
+prvPortPreemptiveTick ( void )
+{
+ /* The cooperative scheduler requires a normal IRQ service routine to
+ * simply increment the system tick.
+ */
- xTaskIncrementTick();
- MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
- }
+ xTaskIncrementTick();
+ MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
+}
-#else /* if configUSE_PREEMPTION == 0 */
+#else
- static void prvPortPreemptiveTick( void )
- {
- asm volatile ( "move.w #0x2700, %sr\n\t" );
- #if _GCC_USES_FP == 1
- asm volatile ( "unlk %fp\n\t" );
- #endif
- portSAVE_CONTEXT();
- MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
+static void
+prvPortPreemptiveTick( void )
+{
+ asm volatile ( "move.w #0x2700, %sr\n\t" );
+#if _GCC_USES_FP == 1
+ asm volatile ( "unlk %fp\n\t" );
+#endif
+ portSAVE_CONTEXT( );
+ MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext( );
+ }
+ portRESTORE_CONTEXT( );
+}
+#endif
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- portRESTORE_CONTEXT();
- }
-#endif /* if configUSE_PREEMPTION == 0 */
-
-void vPortEnterCritical()
+void
+vPortEnterCritical()
{
/* FIXME: We should store the old IPL here - How are we supposed to do
* this.
*/
- ( void ) portSET_IPL( portIPL_MAX );
+ ( void )portSET_IPL( portIPL_MAX );
/* Now interrupts are disabled ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
@@ -230,7 +231,8 @@
ulCriticalNesting++;
}
-void vPortExitCritical()
+void
+vPortExitCritical()
{
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
@@ -238,17 +240,18 @@
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
+ re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
- ( void ) portSET_IPL( 0 );
+ ( void )portSET_IPL( 0 );
}
}
}
-BaseType_t xPortStartScheduler( void )
+BaseType_t
+xPortStartScheduler( void )
{
- extern void ( * portVECTOR_TABLE[] ) ();
+ extern void ( *portVECTOR_TABLE[ ] ) ( );
/* Add entry in vector table for yield system call. */
portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield;
@@ -256,7 +259,7 @@
portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick;
/* Configure the timer for the system clock. */
- if( configTICK_RATE_HZ > 0 )
+ if ( configTICK_RATE_HZ > 0)
{
/* Configure prescaler */
MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW;
@@ -270,12 +273,13 @@
}
/* Restore the context of the first task that is going to run. */
- portRESTORE_CONTEXT();
+ portRESTORE_CONTEXT( );
/* Should not get here. */
return pdTRUE;
}
-void vPortEndScheduler( void )
+void
+vPortEndScheduler( void )
{
}
diff --git a/portable/GCC/MCF5235/portmacro.h b/portable/GCC/MCF5235/portmacro.h
index 3dae7d7..ea2598b 100644
--- a/portable/GCC/MCF5235/portmacro.h
+++ b/portable/GCC/MCF5235/portmacro.h
@@ -1,91 +1,91 @@
/*
- * FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
- * MCF5235 Port - Copyright (C) 2006 Christian Walter.
- *
- * This file is part of the FreeRTOS distribution.
- *
- * FreeRTOS is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License** as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * FreeRTOS is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with FreeRTOS; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * A special exception to the GPL can be applied should you wish to distribute
- * a combined work that includes FreeRTOS, without being obliged to provide
- * the source code for any proprietary components. See the licensing section
- * of http://www.FreeRTOS.org for full details of how and when the exception
- * can be applied.
- *
- ***************************************************************************
- ***************************************************************************
- * *
- * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
- * *
- * This is a concise, step by step, 'hands on' guide that describes both *
- * general multitasking concepts and FreeRTOS specifics. It presents and *
- * explains numerous examples that are written using the FreeRTOS API. *
- * Full source code for all the examples is provided in an accompanying *
- * .zip file. *
- * *
- ***************************************************************************
- ***************************************************************************
- *
- * Please ensure to read the configuration and relevant port sections of the
- * online documentation.
- *
- * http://www.FreeRTOS.org - Documentation, latest information, license and
- * contact details.
- *
- * http://www.SafeRTOS.com - A version that is certified for use in safety
- * critical systems.
- *
- * http://www.OpenRTOS.com - Commercial support, development, porting,
- * licensing and training services.
- */
+ FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
+ MCF5235 Port - Copyright (C) 2006 Christian Walter.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License** as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ FreeRTOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with FreeRTOS; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+ A special exception to the GPL can be applied should you wish to distribute
+ a combined work that includes FreeRTOS, without being obliged to provide
+ the source code for any proprietary components. See the licensing section
+ of http://www.FreeRTOS.org for full details of how and when the exception
+ can be applied.
+
+ ***************************************************************************
+ ***************************************************************************
+ * *
+ * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
+ * *
+ * This is a concise, step by step, 'hands on' guide that describes both *
+ * general multitasking concepts and FreeRTOS specifics. It presents and *
+ * explains numerous examples that are written using the FreeRTOS API. *
+ * Full source code for all the examples is provided in an accompanying *
+ * .zip file. *
+ * *
+ ***************************************************************************
+ ***************************************************************************
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* ------------------------ Data types for Coldfire ----------------------- */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE unsigned int
- #define portBASE_TYPE int
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE unsigned int
+#define portBASE_TYPE int
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/* ------------------------ Architecture specifics ------------------------ */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
- #define portTRAP_YIELD 0 /* Trap 0 */
- #define portIPL_MAX 7 /* Only NMI interrupt 7 allowed. */
+#define portTRAP_YIELD 0 /* Trap 0 */
+#define portIPL_MAX 7 /* Only NMI interrupt 7 allowed. */
/* ------------------------ FreeRTOS macros for port ---------------------- */
@@ -97,17 +97,17 @@
* the stack for the CPU registers and other task dependent values (e.g
* ulCriticalNesting) and updates the top of the stack in the TCB.
*/
- #define portSAVE_CONTEXT() \
- asm volatile ( /* reserve space for task state. */ \
- "lea.l (-64, %sp), %sp\n\t" \
- /* push data register %d0-%d7/%a0-%a6 on stack. */ \
- "movem.l %d0-%d7/%a0-%a6, (%sp)\n\t" \
- /* push ulCriticalNesting counter on stack. */ \
- "lea.l (60, %sp), %a0\n\t" \
- "move.l ulCriticalNesting, (%a0)\n\t" \
- /* set the new top of the stack in the TCB. */ \
- "move.l pxCurrentTCB, %a0\n\t" \
- "move.l %sp, (%a0)" );
+#define portSAVE_CONTEXT() \
+ asm volatile ( /* reserve space for task state. */ \
+ "lea.l (-64, %sp), %sp\n\t" \
+ /* push data register %d0-%d7/%a0-%a6 on stack. */ \
+ "movem.l %d0-%d7/%a0-%a6, (%sp)\n\t" \
+ /* push ulCriticalNesting counter on stack. */ \
+ "lea.l (60, %sp), %a0\n\t" \
+ "move.l ulCriticalNesting, (%a0)\n\t" \
+ /* set the new top of the stack in the TCB. */ \
+ "move.l pxCurrentTCB, %a0\n\t" \
+ "move.l %sp, (%a0)");
/*.
* This function restores the current active and continues its execution.
@@ -115,66 +115,68 @@
* task dependent values (e.g ulCriticalNesting). Finally execution
* is continued by executing an rte instruction.
*/
- #define portRESTORE_CONTEXT() \
- asm volatile ( "move.l pxCurrentTCB, %sp\n\t" \
- "move.l (%sp), %sp\n\t" \
- /* stack pointer now points to the saved registers. */ \
- "movem.l (%sp), %d0-%d7/%a0-%a6\n\t" \
- /* restore ulCriticalNesting counter from stack. */ \
- "lea.l (%sp, 60), %sp\n\t" \
- "move.l (%sp)+, ulCriticalNesting\n\t" \
- /* stack pointer now points to exception frame. */ \
+#define portRESTORE_CONTEXT() \
+ asm volatile ( "move.l pxCurrentTCB, %sp\n\t" \
+ "move.l (%sp), %sp\n\t" \
+ /* stack pointer now points to the saved registers. */ \
+ "movem.l (%sp), %d0-%d7/%a0-%a6\n\t" \
+ /* restore ulCriticalNesting counter from stack. */ \
+ "lea.l (%sp, 60), %sp\n\t" \
+ "move.l (%sp)+, ulCriticalNesting\n\t" \
+ /* stack pointer now points to exception frame. */ \
"rte\n\t" );
- #define portENTER_CRITICAL() \
+#define portENTER_CRITICAL() \
vPortEnterCritical();
- #define portEXIT_CRITICAL() \
+#define portEXIT_CRITICAL() \
vPortExitCritical();
- #define portSET_IPL( xIPL ) \
+#define portSET_IPL( xIPL ) \
asm_set_ipl( xIPL )
- #define portDISABLE_INTERRUPTS() \
- do { ( void ) portSET_IPL( portIPL_MAX ); } while( 0 )
- #define portENABLE_INTERRUPTS() \
- do { ( void ) portSET_IPL( 0 ); } while( 0 )
+#define portDISABLE_INTERRUPTS() \
+ do { ( void )portSET_IPL( portIPL_MAX ); } while( 0 )
+#define portENABLE_INTERRUPTS() \
+ do { ( void )portSET_IPL( 0 ); } while( 0 )
- #define portYIELD() \
- asm volatile ( " trap %0\n\t" : : "i" ( portTRAP_YIELD ) )
+#define portYIELD() \
+ asm volatile ( " trap %0\n\t" : : "i"(portTRAP_YIELD) )
- #define portNOP() \
+#define portNOP() \
asm volatile ( "nop\n\t" )
- #define portENTER_SWITCHING_ISR() \
- asm volatile ( "move.w #0x2700, %sr" ); \
- /* Save the context of the interrupted task. */ \
- portSAVE_CONTEXT(); \
+#define portENTER_SWITCHING_ISR() \
+ asm volatile ( "move.w #0x2700, %sr" ); \
+ /* Save the context of the interrupted task. */ \
+ portSAVE_CONTEXT( ); \
{
- #define portEXIT_SWITCHING_ISR( SwitchRequired ) \
- /* If a switch is required we call vTaskSwitchContext(). */ \
- if( SwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
- } \
- portRESTORE_CONTEXT();
+
+#define portEXIT_SWITCHING_ISR( SwitchRequired ) \
+ /* If a switch is required we call vTaskSwitchContext(). */ \
+ if( SwitchRequired ) \
+ { \
+ vTaskSwitchContext( ); \
+ } \
+ } \
+ portRESTORE_CONTEXT( );
/* ------------------------ Function prototypes --------------------------- */
- void vPortEnterCritical( void );
- void vPortExitCritical( void );
- int asm_set_ipl( uint32_t int uiNewIPL );
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+int asm_set_ipl( uint32_t int uiNewIPL );
/* ------------------------ Compiler specifics ---------------------------- */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) \
- void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) \
+ void vFunction( void *pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) \
- void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) \
+ void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/MSP430F449/port.c b/portable/GCC/MSP430F449/port.c
index 04927e7..59b8fb6 100644
--- a/portable/GCC/MSP430F449/port.c
+++ b/portable/GCC/MSP430F449/port.c
@@ -26,10 +26,10 @@
*/
/*
- * Changes from V2.5.2
- *
- + usCriticalNesting now has a volatile qualifier.
- */
+ Changes from V2.5.2
+
+ + usCriticalNesting now has a volatile qualifier.
+*/
/* Standard includes. */
#include <stdlib.h>
@@ -40,62 +40,62 @@
#include "task.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the MSP430 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
-/* Constants required for hardware setup. The tick ISR runs off the ACLK,
- * not the MCLK. */
-#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
+/* Constants required for hardware setup. The tick ISR runs off the ACLK,
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/* Most ports implement critical sections by placing the interrupt flags on
- * the stack before disabling interrupts. Exiting the critical section is then
- * simply a case of popping the flags from the stack. As mspgcc does not use
- * a frame pointer this cannot be done as modifying the stack will clobber all
- * the stack variables. Instead each task maintains a count of the critical
- * section nesting depth. Each time a critical section is entered the count is
- * incremented. Each time a critical section is left the count is decremented -
- * with interrupts only being re-enabled if the count is zero.
- *
- * usCriticalNesting will get set to zero when the scheduler starts, but must
- * not be initialised to zero as this will cause problems during the startup
- * sequence. */
+the stack before disabling interrupts. Exiting the critical section is then
+simply a case of popping the flags from the stack. As mspgcc does not use
+a frame pointer this cannot be done as modifying the stack will clobber all
+the stack variables. Instead each task maintains a count of the critical
+section nesting depth. Each time a critical section is entered the count is
+incremented. Each time a critical section is left the count is decremented -
+with interrupts only being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
-/*
- * Macro to save a task context to the task stack. This simply pushes all the
- * general purpose msp430 registers onto the stack, followed by the
- * usCriticalNesting value used by the task. Finally the resultant stack
- * pointer value is saved into the task control block so it can be retrieved
+/*
+ * Macro to save a task context to the task stack. This simply pushes all the
+ * general purpose msp430 registers onto the stack, followed by the
+ * usCriticalNesting value used by the task. Finally the resultant stack
+ * pointer value is saved into the task control block so it can be retrieved
* the next time the task executes.
*/
-#define portSAVE_CONTEXT() \
- asm volatile ( "push r4 \n\t"\
- "push r5 \n\t"\
- "push r6 \n\t"\
- "push r7 \n\t"\
- "push r8 \n\t"\
- "push r9 \n\t"\
- "push r10 \n\t"\
- "push r11 \n\t"\
- "push r12 \n\t"\
- "push r13 \n\t"\
- "push r14 \n\t"\
- "push r15 \n\t"\
- "mov.w usCriticalNesting, r14 \n\t"\
- "push r14 \n\t"\
- "mov.w pxCurrentTCB, r12 \n\t"\
- "mov.w r1, @r12 \n\t"\
- );
+#define portSAVE_CONTEXT() \
+ asm volatile ( "push r4 \n\t" \
+ "push r5 \n\t" \
+ "push r6 \n\t" \
+ "push r7 \n\t" \
+ "push r8 \n\t" \
+ "push r9 \n\t" \
+ "push r10 \n\t" \
+ "push r11 \n\t" \
+ "push r12 \n\t" \
+ "push r13 \n\t" \
+ "push r14 \n\t" \
+ "push r15 \n\t" \
+ "mov.w usCriticalNesting, r14 \n\t" \
+ "push r14 \n\t" \
+ "mov.w pxCurrentTCB, r12 \n\t" \
+ "mov.w r1, @r12 \n\t" \
+ );
-/*
+/*
* Macro to restore a task context from the task stack. This is effectively
* the reverse of portSAVE_CONTEXT(). First the stack pointer value is
* loaded from the task control block. Next the value for usCriticalNesting
@@ -105,26 +105,26 @@
* The bic instruction ensures there are no low power bits set in the status
* register that is about to be popped from the stack.
*/
-#define portRESTORE_CONTEXT() \
- asm volatile ( "mov.w pxCurrentTCB, r12 \n\t"\
- "mov.w @r12, r1 \n\t"\
- "pop r15 \n\t" \
- "mov.w r15, usCriticalNesting \n\t"\
- "pop r15 \n\t" \
- "pop r14 \n\t" \
- "pop r13 \n\t" \
- "pop r12 \n\t" \
- "pop r11 \n\t" \
- "pop r10 \n\t" \
- "pop r9 \n\t" \
- "pop r8 \n\t" \
- "pop r7 \n\t" \
- "pop r6 \n\t" \
- "pop r5 \n\t" \
- "pop r4 \n\t" \
- "bic #(0xf0),0(r1) \n\t" \
- "reti \n\t"\
- );
+#define portRESTORE_CONTEXT() \
+ asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \
+ "mov.w @r12, r1 \n\t" \
+ "pop r15 \n\t" \
+ "mov.w r15, usCriticalNesting \n\t" \
+ "pop r15 \n\t" \
+ "pop r14 \n\t" \
+ "pop r13 \n\t" \
+ "pop r12 \n\t" \
+ "pop r11 \n\t" \
+ "pop r10 \n\t" \
+ "pop r9 \n\t" \
+ "pop r8 \n\t" \
+ "pop r7 \n\t" \
+ "pop r6 \n\t" \
+ "pop r5 \n\t" \
+ "pop r4 \n\t" \
+ "bic #(0xf0),0(r1) \n\t" \
+ "reti \n\t" \
+ );
/*-----------------------------------------------------------*/
/*
@@ -134,194 +134,195 @@
static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
-/*
- * Initialise the stack of a task to look exactly as if a call to
+/*
+ * Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
- *
+ *
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /*
- * Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging and can be included if required.
- *
- * pxTopOfStack = ( StackType_t ) 0x1111;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x2222;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x3333;
- * pxTopOfStack--;
- */
+ /*
+ Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging and can be included if required.
- /* The msp430 automatically pushes the PC then SR onto the stack before
- * executing an ISR. We want the stack to look just as if this has happened
- * so place a pointer to the start of the task on the stack first - followed
- * by the flags we want the task to use when it starts up. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
- *pxTopOfStack = portFLAGS_INT_ENABLED;
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x3333;
+ pxTopOfStack--;
+ */
- /* Next the general purpose registers. */
- *pxTopOfStack = ( StackType_t ) 0x4444;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x5555;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x6666;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x7777;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x8888;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x9999;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaa;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xbbbb;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xcccc;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xdddd;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xeeee;
- pxTopOfStack--;
+ /* The msp430 automatically pushes the PC then SR onto the stack before
+ executing an ISR. We want the stack to look just as if this has happened
+ so place a pointer to the start of the task on the stack first - followed
+ by the flags we want the task to use when it starts up. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+ *pxTopOfStack = portFLAGS_INT_ENABLED;
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R15. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
+ /* Next the general purpose registers. */
+ *pxTopOfStack = ( StackType_t ) 0x4444;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x5555;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x6666;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x7777;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x8888;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x9999;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xcccc;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xdddd;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xeeee;
+ pxTopOfStack--;
- /* The code generated by the mspgcc compiler does not maintain separate
- * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
- * use the stack as per other ports. Instead a variable is used to keep
- * track of the critical section nesting. This variable has to be stored
- * as part of the task context and is initially set to zero. */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+ /* When the task starts is will expect to find the function parameter in
+ R15. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
- /* Return a pointer to the top of the stack we have generated so this can
- * be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* The code generated by the mspgcc compiler does not maintain separate
+ stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+ use the stack as per other ports. Instead a variable is used to keep
+ track of the critical section nesting. This variable has to be stored
+ as part of the task context and is initially set to zero. */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+ /* Return a pointer to the top of the stack we have generated so this can
+ be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- * this function is called. */
- prvSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called. */
+ prvSetupTimerInterrupt();
- /* Restore the context of the first task that is going to run. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the first task that is going to run. */
+ portRESTORE_CONTEXT();
- /* Should not get here as the tasks are now running! */
- return pdTRUE;
+ /* Should not get here as the tasks are now running! */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the MSP430 port will get stopped. If required simply
- * disable the tick interrupt here. */
+ /* It is unlikely that the MSP430 port will get stopped. If required simply
+ disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
/*
- * Manual context switch called by portYIELD or taskYIELD.
+ * Manual context switch called by portYIELD or taskYIELD.
*
* The first thing we do is save the registers so we can use a naked attribute.
*/
-void vPortYield( void ) __attribute__( ( naked ) );
+void vPortYield( void ) __attribute__ ( ( naked ) );
void vPortYield( void )
{
- /* We want the stack of the task being saved to look exactly as if the task
- * was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the
- * msp430 places the status register onto the stack. As this is a function
- * call and not an ISR we have to do this manually. */
- asm volatile ( "push r2");
- _DINT();
+ /* We want the stack of the task being saved to look exactly as if the task
+ was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the
+ msp430 places the status register onto the stack. As this is a function
+ call and not an ISR we have to do this manually. */
+ asm volatile ( "push r2" );
+ _DINT();
- /* Save the context of the current task. */
- portSAVE_CONTEXT();
+ /* Save the context of the current task. */
+ portSAVE_CONTEXT();
- /* Switch to the highest priority task that is ready to run. */
- vTaskSwitchContext();
+ /* Switch to the highest priority task that is ready to run. */
+ vTaskSwitchContext();
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
/*
* Hardware initialisation to generate the RTOS tick. This uses timer 0
- * but could alternatively use the watchdog timer or timer 1.
+ * but could alternatively use the watchdog timer or timer 1.
*/
static void prvSetupTimerInterrupt( void )
{
- /* Ensure the timer is stopped. */
- TACTL = 0;
+ /* Ensure the timer is stopped. */
+ TACTL = 0;
- /* Run the timer of the ACLK. */
- TACTL = TASSEL_1;
+ /* Run the timer of the ACLK. */
+ TACTL = TASSEL_1;
- /* Clear everything to start with. */
- TACTL |= TACLR;
+ /* Clear everything to start with. */
+ TACTL |= TACLR;
- /* Set the compare match value according to the tick rate we want. */
- TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+ /* Set the compare match value according to the tick rate we want. */
+ TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
- /* Enable the interrupts. */
- TACCTL0 = CCIE;
+ /* Enable the interrupts. */
+ TACCTL0 = CCIE;
- /* Start up clean. */
- TACTL |= TACLR;
+ /* Start up clean. */
+ TACTL |= TACLR;
- /* Up mode. */
- TACTL |= MC_1;
+ /* Up mode. */
+ TACTL |= MC_1;
}
/*-----------------------------------------------------------*/
-/*
+/*
* The interrupt service routine used depends on whether the pre-emptive
* scheduler is being used or not.
*/
#if configUSE_PREEMPTION == 1
-/*
- * Tick ISR for preemptive scheduler. We can use a naked attribute as
- * the context is saved at the start of vPortYieldFromTick(). The tick
- * count is incremented after the context is saved.
- */
- interrupt( TIMERA0_VECTOR ) prvTickISR( void ) __attribute__( ( naked ) );
- interrupt( TIMERA0_VECTOR ) prvTickISR( void )
- {
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
+ /*
+ * Tick ISR for preemptive scheduler. We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick(). The tick
+ * count is incremented after the context is saved.
+ */
+ interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) );
+ interrupt (TIMERA0_VECTOR) prvTickISR( void )
+ {
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
- /* Increment the tick count then switch to the highest priority task
- * that is ready to run. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
+ /* Increment the tick count then switch to the highest priority task
+ that is ready to run. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
- }
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+ }
-#else /* if configUSE_PREEMPTION == 1 */
+#else
-/*
- * Tick ISR for the cooperative scheduler. All this does is increment the
- * tick count. We don't need to switch context, this can only be done by
- * manual calls to taskYIELD();
- */
- interrupt( TIMERA0_VECTOR ) prvTickISR( void );
- interrupt( TIMERA0_VECTOR ) prvTickISR( void )
- {
- xTaskIncrementTick();
- }
-#endif /* if configUSE_PREEMPTION == 1 */
+ /*
+ * Tick ISR for the cooperative scheduler. All this does is increment the
+ * tick count. We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+ interrupt (TIMERA0_VECTOR) prvTickISR( void );
+ interrupt (TIMERA0_VECTOR) prvTickISR( void )
+ {
+ xTaskIncrementTick();
+ }
+#endif
+
+
+
diff --git a/portable/GCC/MSP430F449/portmacro.h b/portable/GCC/MSP430F449/portmacro.h
index 66d4f1c..8dda844 100644
--- a/portable/GCC/MSP430F449/portmacro.h
+++ b/portable/GCC/MSP430F449/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,84 +43,85 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT int
- #define portSTACK_TYPE uint16_t
- #define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
- typedef portSTACK_TYPE StackType_t;
- typedef short BaseType_t;
- typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
- #define portDISABLE_INTERRUPTS() asm volatile ( "DINT" ); asm volatile ( "NOP" )
- #define portENABLE_INTERRUPTS() asm volatile ( "EINT" ); asm volatile ( "NOP" )
+#define portDISABLE_INTERRUPTS() asm volatile ( "DINT" ); asm volatile ( "NOP" )
+#define portENABLE_INTERRUPTS() asm volatile ( "EINT" ); asm volatile ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section control macros. */
- #define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
- #define portENTER_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
- #define portEXIT_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
- extern void vPortYield( void ) __attribute__( ( naked ) );
- #define portYIELD() vPortYield()
- #define portNOP() asm volatile ( "NOP" )
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD() vPortYield()
+#define portNOP() asm volatile ( "NOP" )
/*-----------------------------------------------------------*/
/* Hardwware specifics. */
- #define portBYTE_ALIGNMENT 2
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/MicroBlaze/port.c b/portable/GCC/MicroBlaze/port.c
index 3c70257..a0192b3 100644
--- a/portable/GCC/MicroBlaze/port.c
+++ b/portable/GCC/MicroBlaze/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the MicroBlaze port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
@@ -42,33 +42,33 @@
#include <xintc_i.h>
#include <xtmrctr.h>
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
- #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+ #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
#endif
/* Tasks are started with interrupts enabled. */
-#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 )
+#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 )
/* Tasks are started with a critical section nesting of 0 - however prior
- * to the scheduler being commenced we don't want the critical nesting level
- * to reach zero, so it is initialised to a high value. */
-#define portINITIAL_NESTING_VALUE ( 0xff )
+to the scheduler being commenced we don't want the critical nesting level
+to reach zero, so it is initialised to a high value. */
+#define portINITIAL_NESTING_VALUE ( 0xff )
/* Our hardware setup only uses one counter. */
-#define portCOUNTER_0 0
+#define portCOUNTER_0 0
/* The stack used by the ISR is filled with a known value to assist in
- * debugging. */
-#define portISR_STACK_FILL_VALUE 0x55555555
+debugging. */
+#define portISR_STACK_FILL_VALUE 0x55555555
/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
- * maintains it's own count, so this variable is saved as part of the task
- * context. */
+maintains it's own count, so this variable is saved as part of the task
+context. */
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
/* To limit the amount of stack required by each task, this port uses a
- * separate stack for interrupts. */
-uint32_t * pulISRStack;
+separate stack for interrupts. */
+uint32_t *pulISRStack;
/*-----------------------------------------------------------*/
@@ -85,142 +85,140 @@
*
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- extern void * _SDA2_BASE_, * _SDA_BASE_;
- const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
- const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+extern void *_SDA2_BASE_, *_SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
- /* Place a few bytes of known values on the bottom of the stack.
- * This is essential for the Microblaze port and these lines must
- * not be omitted. The parameter value will overwrite the
- * 0x22222222 value during the function prologue. */
- *pxTopOfStack = ( StackType_t ) 0x11111111;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x22222222;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x33333333;
- pxTopOfStack--;
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is essential for the Microblaze port and these lines must
+ not be omitted. The parameter value will overwrite the
+ 0x22222222 value during the function prologue. */
+ *pxTopOfStack = ( StackType_t ) 0x11111111;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x22222222;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x33333333;
+ pxTopOfStack--;
- /* First stack an initial value for the critical section nesting. This
- * is initialised to zero as tasks are started with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */
+ /* First stack an initial value for the critical section nesting. This
+ is initialised to zero as tasks are started with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */
- /* Place an initial value for all the general purpose registers. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */
- pxTopOfStack--;
+ /* Place an initial value for all the general purpose registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */
+ pxTopOfStack--;
- /* The MSR is stacked between R30 and R31. */
- *pxTopOfStack = portINITIAL_MSR_STATE;
- pxTopOfStack--;
+ /* The MSR is stacked between R30 and R31. */
+ *pxTopOfStack = portINITIAL_MSR_STATE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */
+ pxTopOfStack--;
- /* Return a pointer to the top of the stack we have generated so this can
- * be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* Return a pointer to the top of the stack we have generated so this can
+ be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void( __FreeRTOS_interrupt_Handler )( void );
- extern void( vStartFirstTask )( void );
+extern void ( __FreeRTOS_interrupt_Handler )( void );
+extern void ( vStartFirstTask )( void );
- /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */
- asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t"\
- "sw r6, r1, r0 \n\t"\
- "lhu r7, r1, r0 \n\t"\
- "shi r7, r0, 0x12 \n\t"\
- "shi r6, r0, 0x16 " );
+ /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */
+ asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \
+ "sw r6, r1, r0 \n\t" \
+ "lhu r7, r1, r0 \n\t" \
+ "shi r7, r0, 0x12 \n\t" \
+ "shi r6, r0, 0x16 " );
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- * this function is called. */
- prvSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called. */
+ prvSetupTimerInterrupt();
- /* Allocate the stack to be used by the interrupt handler. */
- pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
+ /* Allocate the stack to be used by the interrupt handler. */
+ pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
- /* Restore the context of the first task that is going to run. */
- if( pulISRStack != NULL )
- {
- /* Fill the ISR stack with a known value to facilitate debugging. */
- memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
- pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
+ /* Restore the context of the first task that is going to run. */
+ if( pulISRStack != NULL )
+ {
+ /* Fill the ISR stack with a known value to facilitate debugging. */
+ memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
+ pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
- /* Kick off the first task. */
- vStartFirstTask();
- }
+ /* Kick off the first task. */
+ vStartFirstTask();
+ }
- /* Should not get here as the tasks are now running! */
- return pdFALSE;
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented. */
+ /* Not implemented. */
}
/*-----------------------------------------------------------*/
@@ -229,18 +227,17 @@
*/
void vPortYield( void )
{
- extern void VPortYieldASM( void );
+extern void VPortYieldASM( void );
- /* Perform the context switch in a critical section to assure it is
- * not interrupted by the tick ISR. It is not a problem to do this as
- * each task maintains it's own interrupt status. */
- portENTER_CRITICAL();
-
- /* Jump directly to the yield function to ensure there is no
- * compiler generated prologue code. */
- asm volatile ( "bralid r14, VPortYieldASM \n\t"\
- "or r0, r0, r0 \n\t");
- portEXIT_CRITICAL();
+ /* Perform the context switch in a critical section to assure it is
+ not interrupted by the tick ISR. It is not a problem to do this as
+ each task maintains it's own interrupt status. */
+ portENTER_CRITICAL();
+ /* Jump directly to the yield function to ensure there is no
+ compiler generated prologue code. */
+ asm volatile ( "bralid r14, VPortYieldASM \n\t" \
+ "or r0, r0, r0 \n\t" );
+ portEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
@@ -249,26 +246,26 @@
*/
static void prvSetupTimerInterrupt( void )
{
- XTmrCtr xTimer;
- const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
- UBaseType_t uxMask;
+XTmrCtr xTimer;
+const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+UBaseType_t uxMask;
- /* The OPB timer1 is used to generate the tick. Use the provided library
- * functions to enable the timer and set the tick frequency. */
- XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
- XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
- XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
- XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
+ /* The OPB timer1 is used to generate the tick. Use the provided library
+ functions to enable the timer and set the tick frequency. */
+ XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
+ XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
+ XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
+ XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
- /* Set the timer interrupt enable bit while maintaining the other bit
- * states. */
- uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
- uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
- XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
+ /* Set the timer interrupt enable bit while maintaining the other bit
+ states. */
+ uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
+ uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
+ XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
- XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
- XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
- XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
+ XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
+ XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
+ XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
}
/*-----------------------------------------------------------*/
@@ -280,53 +277,57 @@
*/
void vTaskISRHandler( void )
{
- static uint32_t ulPending;
+static uint32_t ulPending;
- /* Which interrupts are pending? */
- ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
+ /* Which interrupts are pending? */
+ ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
- if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
- {
- static XIntc_VectorTableEntry * pxTablePtr;
- static XIntc_Config * pxConfig;
- static uint32_t ulInterruptMask;
+ if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
+ {
+ static XIntc_VectorTableEntry *pxTablePtr;
+ static XIntc_Config *pxConfig;
+ static uint32_t ulInterruptMask;
- ulInterruptMask = ( uint32_t ) 1 << ulPending;
+ ulInterruptMask = ( uint32_t ) 1 << ulPending;
- /* Get the configuration data using the device ID */
- pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
+ /* Get the configuration data using the device ID */
+ pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
- pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
-
- if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
- {
- XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
- pxTablePtr->Handler( pxTablePtr->CallBackRef );
- }
- else
- {
- pxTablePtr->Handler( pxTablePtr->CallBackRef );
- XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
- }
- }
+ pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
+ if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
+ {
+ XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+ pxTablePtr->Handler( pxTablePtr->CallBackRef );
+ }
+ else
+ {
+ pxTablePtr->Handler( pxTablePtr->CallBackRef );
+ XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+ }
+ }
}
/*-----------------------------------------------------------*/
/*
* Handler for the timer interrupt.
*/
-void vTickISR( void * pvBaseAddress )
+void vTickISR( void *pvBaseAddress )
{
- uint32_t ulCSR;
+uint32_t ulCSR;
- /* Increment the RTOS tick - this might cause a task to unblock. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
+ /* Increment the RTOS tick - this might cause a task to unblock. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
- /* Clear the timer interrupt */
- ulCSR = XTmrCtr_mGetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, 0 );
- XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
+ /* Clear the timer interrupt */
+ ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
+ XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
}
/*-----------------------------------------------------------*/
+
+
+
+
+
diff --git a/portable/GCC/MicroBlaze/portmacro.h b/portable/GCC/MicroBlaze/portmacro.h
index 486d61f..9489020 100644
--- a/portable/GCC/MicroBlaze/portmacro.h
+++ b/portable/GCC/MicroBlaze/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,85 +43,84 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
- void microblaze_disable_interrupts( void );
- void microblaze_enable_interrupts( void );
- #define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
- #define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
/*-----------------------------------------------------------*/
/* Critical section macros. */
- void vPortEnterCritical( void );
- void vPortExitCritical( void );
- #define portENTER_CRITICAL() \
- { \
- extern UBaseType_t uxCriticalNesting; \
- microblaze_disable_interrupts(); \
- uxCriticalNesting++; \
- }
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL() { \
+ extern UBaseType_t uxCriticalNesting; \
+ microblaze_disable_interrupts(); \
+ uxCriticalNesting++; \
+ }
- #define portEXIT_CRITICAL() \
- { \
- extern UBaseType_t uxCriticalNesting; \
- /* Interrupts are disabled, so we can */ \
- /* access the variable directly. */ \
- uxCriticalNesting--; \
- if( uxCriticalNesting == 0 ) \
- { \
- /* The nesting has unwound and we \
- * can enable interrupts again. */ \
- portENABLE_INTERRUPTS(); \
- } \
- }
+#define portEXIT_CRITICAL() { \
+ extern UBaseType_t uxCriticalNesting; \
+ /* Interrupts are disabled, so we can */ \
+ /* access the variable directly. */ \
+ uxCriticalNesting--; \
+ if( uxCriticalNesting == 0 ) \
+ { \
+ /* The nesting has unwound and we \
+ can enable interrupts again. */ \
+ portENABLE_INTERRUPTS(); \
+ } \
+ }
/*-----------------------------------------------------------*/
/* Task utilities. */
- void vPortYield( void );
- #define portYIELD() vPortYield()
+void vPortYield( void );
+#define portYIELD() vPortYield()
- void vTaskSwitchContext();
- #define portYIELD_FROM_ISR() vTaskSwitchContext()
+void vTaskSwitchContext();
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 4
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "NOP" )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/MicroBlazeV8/port.c b/portable/GCC/MicroBlazeV8/port.c
index edd5186..bd70f2a 100644
--- a/portable/GCC/MicroBlazeV8/port.c
+++ b/portable/GCC/MicroBlazeV8/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the MicroBlaze port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
@@ -43,20 +43,20 @@
#include <microblaze_exceptions_g.h>
/* Tasks are started with a critical section nesting of 0 - however, prior to
- * the scheduler being commenced interrupts should not be enabled, so the critical
- * nesting variable is initialised to a non-zero value. */
-#define portINITIAL_NESTING_VALUE ( 0xff )
+the scheduler being commenced interrupts should not be enabled, so the critical
+nesting variable is initialised to a non-zero value. */
+#define portINITIAL_NESTING_VALUE ( 0xff )
-/* The bit within the MSR register that enabled/disables interrupts and
- * exceptions respectively. */
-#define portMSR_IE ( 0x02U )
-#define portMSR_EE ( 0x100U )
+/* The bit within the MSR register that enabled/disables interrupts and
+exceptions respectively. */
+#define portMSR_IE ( 0x02U )
+#define portMSR_EE ( 0x100U )
/* If the floating point unit is included in the MicroBlaze build, then the
- * FSR register is saved as part of the task context. portINITIAL_FSR is the value
- * given to the FSR register when the initial context is set up for a task being
- * created. */
-#define portINITIAL_FSR ( 0U )
+FSR register is saved as part of the task context. portINITIAL_FSR is the value
+given to the FSR register when the initial context is set up for a task being
+created. */
+#define portINITIAL_FSR ( 0U )
/*-----------------------------------------------------------*/
/*
@@ -72,27 +72,27 @@
/*-----------------------------------------------------------*/
/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
- * maintains its own count, so this variable is saved as part of the task
- * context. */
+maintains its own count, so this variable is saved as part of the task
+context. */
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
/* This port uses a separate stack for interrupts. This prevents the stack of
- * every task needing to be large enough to hold an entire interrupt stack on top
- * of the task stack. */
-uint32_t * pulISRStack;
+every task needing to be large enough to hold an entire interrupt stack on top
+of the task stack. */
+uint32_t *pulISRStack;
/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
- * get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
- * handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
- * will call vTaskSwitchContext() to ensure the task that runs immediately after
- * the interrupt exists is the highest priority task that is able to run. This is
- * an unusual mechanism, but is used for this port because a single interrupt can
- * cause the servicing of multiple peripherals - and it is inefficient to call
- * vTaskSwitchContext() multiple times as each peripheral is serviced. */
+get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
+handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
+will call vTaskSwitchContext() to ensure the task that runs immediately after
+the interrupt exists is the highest priority task that is able to run. This is
+an unusual mechanism, but is used for this port because a single interrupt can
+cause the servicing of multiple peripherals - and it is inefficient to call
+vTaskSwitchContext() multiple times as each peripheral is serviced. */
volatile uint32_t ulTaskSwitchRequested = 0UL;
/* The instance of the interrupt controller used by this port. This is required
- * by the Xilinx library API functions. */
+by the Xilinx library API functions. */
static XIntc xInterruptControllerInstance;
/*-----------------------------------------------------------*/
@@ -103,174 +103,172 @@
*
* See the portable.h header file.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- extern void * _SDA2_BASE_, * _SDA_BASE_;
- const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
- const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+extern void *_SDA2_BASE_, *_SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
- /* Place a few bytes of known values on the bottom of the stack.
- * This is essential for the Microblaze port and these lines must
- * not be omitted. */
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is essential for the Microblaze port and these lines must
+ not be omitted. */
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
- #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
- /* The FSR value placed in the initial task context is just 0. */
- *pxTopOfStack = portINITIAL_FSR;
- pxTopOfStack--;
- #endif
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ /* The FSR value placed in the initial task context is just 0. */
+ *pxTopOfStack = portINITIAL_FSR;
+ pxTopOfStack--;
+ #endif
- /* The MSR value placed in the initial task context should have interrupts
- * disabled. Each task will enable interrupts automatically when it enters
- * the running state for the first time. */
- *pxTopOfStack = mfmsr() & ~portMSR_IE;
+ /* The MSR value placed in the initial task context should have interrupts
+ disabled. Each task will enable interrupts automatically when it enters
+ the running state for the first time. */
+ *pxTopOfStack = mfmsr() & ~portMSR_IE;
+
+ #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
+ {
+ /* Ensure exceptions are enabled for the task. */
+ *pxTopOfStack |= portMSR_EE;
+ }
+ #endif
- #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
- {
- /* Ensure exceptions are enabled for the task. */
- *pxTopOfStack |= portMSR_EE;
- }
- #endif
+ pxTopOfStack--;
- pxTopOfStack--;
+ /* First stack an initial value for the critical section nesting. This
+ is initialised to zero. */
+ *pxTopOfStack = ( StackType_t ) 0x00;
- /* First stack an initial value for the critical section nesting. This
- * is initialised to zero. */
- *pxTopOfStack = ( StackType_t ) 0x00;
+ /* R0 is always zero. */
+ /* R1 is the SP. */
- /* R0 is always zero. */
- /* R1 is the SP. */
+ /* Place an initial value for all the general purpose registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
- /* Place an initial value for all the general purpose registers. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack-= 8;
+ #endif
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
- pxTopOfStack--;
- #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
- pxTopOfStack -= 8;
- #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
+ *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */
- *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack -= 4;
+ #endif
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
- pxTopOfStack--;
- #else
- pxTopOfStack -= 4;
- #endif
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack -= 13;
+ #endif
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
- pxTopOfStack -= 13;
- #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
-
- /* Return a pointer to the top of the stack that has been generated so this
- * can be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* Return a pointer to the top of the stack that has been generated so this
+ can be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void( vPortStartFirstTask )( void );
- extern uint32_t _stack[];
+extern void ( vPortStartFirstTask )( void );
+extern uint32_t _stack[];
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- * this function is called.
- *
- * This port uses an application defined callback function to install the tick
- * interrupt handler because the kernel will run on lots of different
- * MicroBlaze and FPGA configurations - not all of which will have the same
- * timer peripherals defined or available. An example definition of
- * vApplicationSetupTimerInterrupt() is provided in the official demo
- * application that accompanies this port. */
- vApplicationSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called.
- /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
- pulISRStack = ( uint32_t * ) _stack;
+ This port uses an application defined callback function to install the tick
+ interrupt handler because the kernel will run on lots of different
+ MicroBlaze and FPGA configurations - not all of which will have the same
+ timer peripherals defined or available. An example definition of
+ vApplicationSetupTimerInterrupt() is provided in the official demo
+ application that accompanies this port. */
+ vApplicationSetupTimerInterrupt();
- /* Ensure there is enough space for the functions called from the interrupt
- * service routines to write back into the stack frame of the caller. */
- pulISRStack -= 2;
+ /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
+ pulISRStack = ( uint32_t * ) _stack;
- /* Restore the context of the first task that is going to run. From here
- * on, the created tasks will be executing. */
- vPortStartFirstTask();
+ /* Ensure there is enough space for the functions called from the interrupt
+ service routines to write back into the stack frame of the caller. */
+ pulISRStack -= 2;
- /* Should not get here as the tasks are now running! */
- return pdFALSE;
+ /* Restore the context of the first task that is going to run. From here
+ on, the created tasks will be executing. */
+ vPortStartFirstTask();
+
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@@ -279,107 +277,104 @@
*/
void vPortYield( void )
{
- extern void VPortYieldASM( void );
+extern void VPortYieldASM( void );
- /* Perform the context switch in a critical section to assure it is
- * not interrupted by the tick ISR. It is not a problem to do this as
- * each task maintains its own interrupt status. */
- portENTER_CRITICAL();
- {
- /* Jump directly to the yield function to ensure there is no
- * compiler generated prologue code. */
- asm volatile ( "bralid r14, VPortYieldASM \n\t"\
- "or r0, r0, r0 \n\t");
- }
- portEXIT_CRITICAL();
+ /* Perform the context switch in a critical section to assure it is
+ not interrupted by the tick ISR. It is not a problem to do this as
+ each task maintains its own interrupt status. */
+ portENTER_CRITICAL();
+ {
+ /* Jump directly to the yield function to ensure there is no
+ compiler generated prologue code. */
+ asm volatile ( "bralid r14, VPortYieldASM \n\t" \
+ "or r0, r0, r0 \n\t" );
+ }
+ portEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vPortEnableInterrupt( uint8_t ucInterruptID )
{
- int32_t lReturn;
+int32_t lReturn;
- /* An API function is provided to enable an interrupt in the interrupt
- * controller because the interrupt controller instance variable is private
- * to this file. */
- lReturn = prvEnsureInterruptControllerIsInitialised();
+ /* An API function is provided to enable an interrupt in the interrupt
+ controller because the interrupt controller instance variable is private
+ to this file. */
+ lReturn = prvEnsureInterruptControllerIsInitialised();
+ if( lReturn == pdPASS )
+ {
+ XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
+ }
- if( lReturn == pdPASS )
- {
- XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
- }
-
- configASSERT( lReturn );
+ configASSERT( lReturn );
}
/*-----------------------------------------------------------*/
void vPortDisableInterrupt( uint8_t ucInterruptID )
{
- int32_t lReturn;
+int32_t lReturn;
- /* An API function is provided to disable an interrupt in the interrupt
- * controller because the interrupt controller instance variable is private
- * to this file. */
- lReturn = prvEnsureInterruptControllerIsInitialised();
+ /* An API function is provided to disable an interrupt in the interrupt
+ controller because the interrupt controller instance variable is private
+ to this file. */
+ lReturn = prvEnsureInterruptControllerIsInitialised();
- if( lReturn == pdPASS )
- {
- XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
- }
+ if( lReturn == pdPASS )
+ {
+ XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
+ }
- configASSERT( lReturn );
+ configASSERT( lReturn );
}
/*-----------------------------------------------------------*/
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
- XInterruptHandler pxHandler,
- void * pvCallBackRef )
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
{
- int32_t lReturn;
+int32_t lReturn;
- /* An API function is provided to install an interrupt handler because the
- * interrupt controller instance variable is private to this file. */
+ /* An API function is provided to install an interrupt handler because the
+ interrupt controller instance variable is private to this file. */
- lReturn = prvEnsureInterruptControllerIsInitialised();
+ lReturn = prvEnsureInterruptControllerIsInitialised();
- if( lReturn == pdPASS )
- {
- lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
- }
+ if( lReturn == pdPASS )
+ {
+ lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
+ }
- if( lReturn == XST_SUCCESS )
- {
- lReturn = pdPASS;
- }
+ if( lReturn == XST_SUCCESS )
+ {
+ lReturn = pdPASS;
+ }
- configASSERT( lReturn == pdPASS );
+ configASSERT( lReturn == pdPASS );
- return lReturn;
+ return lReturn;
}
/*-----------------------------------------------------------*/
static int32_t prvEnsureInterruptControllerIsInitialised( void )
{
- static int32_t lInterruptControllerInitialised = pdFALSE;
- int32_t lReturn;
+static int32_t lInterruptControllerInitialised = pdFALSE;
+int32_t lReturn;
- /* Ensure the interrupt controller instance variable is initialised before
- * it is used, and that the initialisation only happens once. */
- if( lInterruptControllerInitialised != pdTRUE )
- {
- lReturn = prvInitialiseInterruptController();
+ /* Ensure the interrupt controller instance variable is initialised before
+ it is used, and that the initialisation only happens once. */
+ if( lInterruptControllerInitialised != pdTRUE )
+ {
+ lReturn = prvInitialiseInterruptController();
- if( lReturn == pdPASS )
- {
- lInterruptControllerInitialised = pdTRUE;
- }
- }
- else
- {
- lReturn = pdPASS;
- }
+ if( lReturn == pdPASS )
+ {
+ lInterruptControllerInitialised = pdTRUE;
+ }
+ }
+ else
+ {
+ lReturn = pdPASS;
+ }
- return lReturn;
+ return lReturn;
}
/*-----------------------------------------------------------*/
@@ -387,69 +382,71 @@
* Handler for the timer interrupt. This is the handler that the application
* defined callback function vApplicationSetupTimerInterrupt() should install.
*/
-void vPortTickISR( void * pvUnused )
+void vPortTickISR( void *pvUnused )
{
- extern void vApplicationClearTimerInterrupt( void );
+extern void vApplicationClearTimerInterrupt( void );
- /* Ensure the unused parameter does not generate a compiler warning. */
- ( void ) pvUnused;
+ /* Ensure the unused parameter does not generate a compiler warning. */
+ ( void ) pvUnused;
- /* This port uses an application defined callback function to clear the tick
- * interrupt because the kernel will run on lots of different MicroBlaze and
- * FPGA configurations - not all of which will have the same timer peripherals
- * defined or available. An example definition of
- * vApplicationClearTimerInterrupt() is provided in the official demo
- * application that accompanies this port. */
- vApplicationClearTimerInterrupt();
+ /* This port uses an application defined callback function to clear the tick
+ interrupt because the kernel will run on lots of different MicroBlaze and
+ FPGA configurations - not all of which will have the same timer peripherals
+ defined or available. An example definition of
+ vApplicationClearTimerInterrupt() is provided in the official demo
+ application that accompanies this port. */
+ vApplicationClearTimerInterrupt();
- /* Increment the RTOS tick - this might cause a task to unblock. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Force vTaskSwitchContext() to be called as the interrupt exits. */
- ulTaskSwitchRequested = 1;
- }
+ /* Increment the RTOS tick - this might cause a task to unblock. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Force vTaskSwitchContext() to be called as the interrupt exits. */
+ ulTaskSwitchRequested = 1;
+ }
}
/*-----------------------------------------------------------*/
static int32_t prvInitialiseInterruptController( void )
{
- int32_t lStatus;
+int32_t lStatus;
- lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
+ lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
- if( lStatus == XST_SUCCESS )
- {
- /* Initialise the exception table. */
- Xil_ExceptionInit();
+ if( lStatus == XST_SUCCESS )
+ {
+ /* Initialise the exception table. */
+ Xil_ExceptionInit();
- /* Service all pending interrupts each time the handler is entered. */
- XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
+ /* Service all pending interrupts each time the handler is entered. */
+ XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
- /* Install exception handlers if the MicroBlaze is configured to handle
- * exceptions, and the application defined constant
- * configINSTALL_EXCEPTION_HANDLERS is set to 1. */
- #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
- {
- vPortExceptionsInstallHandlers();
- }
- #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
+ /* Install exception handlers if the MicroBlaze is configured to handle
+ exceptions, and the application defined constant
+ configINSTALL_EXCEPTION_HANDLERS is set to 1. */
+ #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+ {
+ vPortExceptionsInstallHandlers();
+ }
+ #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
- /* Start the interrupt controller. Interrupts are enabled when the
- * scheduler starts. */
- lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
+ /* Start the interrupt controller. Interrupts are enabled when the
+ scheduler starts. */
+ lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
- if( lStatus == XST_SUCCESS )
- {
- lStatus = pdPASS;
- }
- else
- {
- lStatus = pdFAIL;
- }
- }
+ if( lStatus == XST_SUCCESS )
+ {
+ lStatus = pdPASS;
+ }
+ else
+ {
+ lStatus = pdFAIL;
+ }
+ }
- configASSERT( lStatus == pdPASS );
+ configASSERT( lStatus == pdPASS );
- return lStatus;
+ return lStatus;
}
/*-----------------------------------------------------------*/
+
+
diff --git a/portable/GCC/MicroBlazeV8/port_exceptions.c b/portable/GCC/MicroBlazeV8/port_exceptions.c
index 6d798cc..ca2a1ac 100644
--- a/portable/GCC/MicroBlazeV8/port_exceptions.c
+++ b/portable/GCC/MicroBlazeV8/port_exceptions.c
@@ -34,244 +34,249 @@
#include <microblaze_exceptions_g.h>
/* The Xilinx library defined exception entry point stacks a number of
- * registers. These definitions are offsets from the stack pointer to the various
- * stacked register values. */
-#define portexR3_STACK_OFFSET 4
-#define portexR4_STACK_OFFSET 5
-#define portexR5_STACK_OFFSET 6
-#define portexR6_STACK_OFFSET 7
-#define portexR7_STACK_OFFSET 8
-#define portexR8_STACK_OFFSET 9
-#define portexR9_STACK_OFFSET 10
-#define portexR10_STACK_OFFSET 11
-#define portexR11_STACK_OFFSET 12
-#define portexR12_STACK_OFFSET 13
-#define portexR15_STACK_OFFSET 16
-#define portexR18_STACK_OFFSET 19
-#define portexMSR_STACK_OFFSET 20
-#define portexR19_STACK_OFFSET -1
+registers. These definitions are offsets from the stack pointer to the various
+stacked register values. */
+#define portexR3_STACK_OFFSET 4
+#define portexR4_STACK_OFFSET 5
+#define portexR5_STACK_OFFSET 6
+#define portexR6_STACK_OFFSET 7
+#define portexR7_STACK_OFFSET 8
+#define portexR8_STACK_OFFSET 9
+#define portexR9_STACK_OFFSET 10
+#define portexR10_STACK_OFFSET 11
+#define portexR11_STACK_OFFSET 12
+#define portexR12_STACK_OFFSET 13
+#define portexR15_STACK_OFFSET 16
+#define portexR18_STACK_OFFSET 19
+#define portexMSR_STACK_OFFSET 20
+#define portexR19_STACK_OFFSET -1
/* This is defined to equal the size, in bytes, of the stack frame generated by
- * the Xilinx standard library exception entry point. It is required to determine
- * the stack pointer value prior to the exception being entered. */
-#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
+the Xilinx standard library exception entry point. It is required to determine
+the stack pointer value prior to the exception being entered. */
+#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
/* The number of bytes a MicroBlaze instruction consumes. */
-#define portexINSTRUCTION_SIZE 4
+#define portexINSTRUCTION_SIZE 4
/* Exclude this entire file if the MicroBlaze is not configured to handle
- * exceptions, or the application defined configuration constant
- * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+exceptions, or the application defined configuration constant
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
/* This variable is set in the exception entry code, before
- * vPortExceptionHandler is called. */
- uint32_t * pulStackPointerOnFunctionEntry = NULL;
+vPortExceptionHandler is called. */
+uint32_t *pulStackPointerOnFunctionEntry = NULL;
/* This is the structure that is filled with the MicroBlaze context as it
- * existed immediately prior to the exception occurrence. A pointer to this
- * structure is passed into the vApplicationExceptionRegisterDump() callback
- * function, if one is defined. */
- static xPortRegisterDump xRegisterDump;
+existed immediately prior to the exception occurrence. A pointer to this
+structure is passed into the vApplicationExceptionRegisterDump() callback
+function, if one is defined. */
+static xPortRegisterDump xRegisterDump;
/* This is the FreeRTOS exception handler that is installed for all exception
- * types. It is called from vPortExceptionHanlderEntry() - which is itself defined
- * in portasm.S. */
- void vPortExceptionHandler( void * pvExceptionID );
- extern void vPortExceptionHandlerEntry( void * pvExceptionID );
+types. It is called from vPortExceptionHanlderEntry() - which is itself defined
+in portasm.S. */
+void vPortExceptionHandler( void *pvExceptionID );
+extern void vPortExceptionHandlerEntry( void *pvExceptionID );
/*-----------------------------------------------------------*/
/* vApplicationExceptionRegisterDump() is a callback function that the
- * application can optionally define to receive a populated xPortRegisterDump
- * structure. If the application chooses not to define a version of
- * vApplicationExceptionRegisterDump() then this weekly defined default
- * implementation will be called instead. */
- extern void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) __attribute__( ( weak ) );
- void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump )
- {
- ( void ) xRegisterDump;
+application can optionally define to receive a populated xPortRegisterDump
+structure. If the application chooses not to define a version of
+vApplicationExceptionRegisterDump() then this weekly defined default
+implementation will be called instead. */
+extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
+{
+ ( void ) xRegisterDump;
- for( ; ; )
- {
- portNOP();
- }
- }
+ for( ;; )
+ {
+ portNOP();
+ }
+}
/*-----------------------------------------------------------*/
- void vPortExceptionHandler( void * pvExceptionID )
- {
- extern void * pxCurrentTCB;
+void vPortExceptionHandler( void *pvExceptionID )
+{
+extern void *pxCurrentTCB;
- /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
- * was immediately before the exception occurrence. */
+ /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
+ was immediately before the exception occurrence. */
- /* First fill in the name and handle of the task that was in the Running
- * state when the exception occurred. */
- xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
- xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
+ /* First fill in the name and handle of the task that was in the Running
+ state when the exception occurred. */
+ xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
+ xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
- configASSERT( pulStackPointerOnFunctionEntry );
+ configASSERT( pulStackPointerOnFunctionEntry );
- /* Obtain the values of registers that were stacked prior to this function
- * being called, and may have changed since they were stacked. */
- xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
- xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
- xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
- xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
- xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
- xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
- xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
- xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
- xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
- xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
- xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
- xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
- xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
- xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
+ /* Obtain the values of registers that were stacked prior to this function
+ being called, and may have changed since they were stacked. */
+ xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
+ xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
+ xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
+ xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
+ xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
+ xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
+ xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
+ xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
+ xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
+ xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
+ xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
+ xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
+ xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
+ xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
- /* Obtain the value of all other registers. */
- xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
- xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
- xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
- xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
- xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
- xRegisterDump.ulR20 = mfgpr( R20 );
- xRegisterDump.ulR21 = mfgpr( R21 );
- xRegisterDump.ulR22 = mfgpr( R22 );
- xRegisterDump.ulR23 = mfgpr( R23 );
- xRegisterDump.ulR24 = mfgpr( R24 );
- xRegisterDump.ulR25 = mfgpr( R25 );
- xRegisterDump.ulR26 = mfgpr( R26 );
- xRegisterDump.ulR27 = mfgpr( R27 );
- xRegisterDump.ulR28 = mfgpr( R28 );
- xRegisterDump.ulR29 = mfgpr( R29 );
- xRegisterDump.ulR30 = mfgpr( R30 );
- xRegisterDump.ulR31 = mfgpr( R31 );
- xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
- xRegisterDump.ulEAR = mfear();
- xRegisterDump.ulESR = mfesr();
- xRegisterDump.ulEDR = mfedr();
+ /* Obtain the value of all other registers. */
+ xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
+ xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
+ xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
+ xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
+ xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
+ xRegisterDump.ulR20 = mfgpr( R20 );
+ xRegisterDump.ulR21 = mfgpr( R21 );
+ xRegisterDump.ulR22 = mfgpr( R22 );
+ xRegisterDump.ulR23 = mfgpr( R23 );
+ xRegisterDump.ulR24 = mfgpr( R24 );
+ xRegisterDump.ulR25 = mfgpr( R25 );
+ xRegisterDump.ulR26 = mfgpr( R26 );
+ xRegisterDump.ulR27 = mfgpr( R27 );
+ xRegisterDump.ulR28 = mfgpr( R28 );
+ xRegisterDump.ulR29 = mfgpr( R29 );
+ xRegisterDump.ulR30 = mfgpr( R30 );
+ xRegisterDump.ulR31 = mfgpr( R31 );
+ xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+ xRegisterDump.ulEAR = mfear();
+ xRegisterDump.ulESR = mfesr();
+ xRegisterDump.ulEDR = mfedr();
- /* Move the saved program counter back to the instruction that was executed
- * when the exception occurred. This is only valid for certain types of
- * exception. */
- xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
+ /* Move the saved program counter back to the instruction that was executed
+ when the exception occurred. This is only valid for certain types of
+ exception. */
+ xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
- #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
- {
- xRegisterDump.ulFSR = mffsr();
- }
- #else
- {
- xRegisterDump.ulFSR = 0UL;
- }
- #endif
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ {
+ xRegisterDump.ulFSR = mffsr();
+ }
+ #else
+ {
+ xRegisterDump.ulFSR = 0UL;
+ }
+ #endif
- /* Also fill in a string that describes what type of exception this is.
- * The string uses the same ID names as defined in the MicroBlaze standard
- * library exception header files. */
- switch( ( uint32_t ) pvExceptionID )
- {
- case XEXC_ID_FSL:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
- break;
+ /* Also fill in a string that describes what type of exception this is.
+ The string uses the same ID names as defined in the MicroBlaze standard
+ library exception header files. */
+ switch( ( uint32_t ) pvExceptionID )
+ {
+ case XEXC_ID_FSL :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
+ break;
- case XEXC_ID_UNALIGNED_ACCESS:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
- break;
+ case XEXC_ID_UNALIGNED_ACCESS :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
+ break;
- case XEXC_ID_ILLEGAL_OPCODE:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
- break;
+ case XEXC_ID_ILLEGAL_OPCODE :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
+ break;
- case XEXC_ID_M_AXI_I_EXCEPTION:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
- break;
+ case XEXC_ID_M_AXI_I_EXCEPTION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
+ break;
- case XEXC_ID_M_AXI_D_EXCEPTION:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
- break;
+ case XEXC_ID_M_AXI_D_EXCEPTION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
+ break;
- case XEXC_ID_DIV_BY_ZERO:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
- break;
+ case XEXC_ID_DIV_BY_ZERO :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
+ break;
- case XEXC_ID_STACK_VIOLATION:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
- break;
+ case XEXC_ID_STACK_VIOLATION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
+ break;
- #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
- case XEXC_ID_FPU:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
- break;
- #endif /* XPAR_MICROBLAZE_USE_FPU */
- }
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
- /* vApplicationExceptionRegisterDump() is a callback function that the
- * application can optionally define to receive the populated xPortRegisterDump
- * structure. If the application chooses not to define a version of
- * vApplicationExceptionRegisterDump() then the weekly defined default
- * implementation within this file will be called instead. */
- vApplicationExceptionRegisterDump( &xRegisterDump );
+ case XEXC_ID_FPU :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
+ break;
- /* Must not attempt to leave this function! */
- for( ; ; )
- {
- portNOP();
- }
- }
+ #endif /* XPAR_MICROBLAZE_USE_FPU */
+ }
+
+ /* vApplicationExceptionRegisterDump() is a callback function that the
+ application can optionally define to receive the populated xPortRegisterDump
+ structure. If the application chooses not to define a version of
+ vApplicationExceptionRegisterDump() then the weekly defined default
+ implementation within this file will be called instead. */
+ vApplicationExceptionRegisterDump( &xRegisterDump );
+
+ /* Must not attempt to leave this function! */
+ for( ;; )
+ {
+ portNOP();
+ }
+}
/*-----------------------------------------------------------*/
- void vPortExceptionsInstallHandlers( void )
- {
- static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
+void vPortExceptionsInstallHandlers( void )
+{
+static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
- if( ulHandlersAlreadyInstalled == pdFALSE )
- {
- ulHandlersAlreadyInstalled = pdTRUE;
+ if( ulHandlersAlreadyInstalled == pdFALSE )
+ {
+ ulHandlersAlreadyInstalled = pdTRUE;
- #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
- microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
- #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
+ #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
+ microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
+ #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
- #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
- #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
+ #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
+ #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
- #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
+ #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
- #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
+ #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
- #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
+ #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
- #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
+ #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
- #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
- #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
+ #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
+ #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
- #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
- #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
+ #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
+ #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
- #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
- #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+ #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
+ #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
- microblaze_enable_exceptions();
- }
- }
+ microblaze_enable_exceptions();
+ }
+}
/* Exclude the entire file if the MicroBlaze is not configured to handle
- * exceptions, or the application defined configuration item
- * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+exceptions, or the application defined configuration item
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
+
+
+
diff --git a/portable/GCC/MicroBlazeV8/portmacro.h b/portable/GCC/MicroBlazeV8/portmacro.h
index 5b5840e..19b5288 100644
--- a/portable/GCC/MicroBlazeV8/portmacro.h
+++ b/portable/GCC/MicroBlazeV8/portmacro.h
@@ -26,15 +26,15 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* BSP includes. */
- #include <mb_interface.h>
- #include <xparameters.h>
+#include <mb_interface.h>
+#include <xparameters.h>
/*-----------------------------------------------------------
* Port specific definitions.
@@ -47,177 +47,175 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros and functions. */
- void microblaze_disable_interrupts( void );
- void microblaze_enable_interrupts( void );
- #define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
- #define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
/*-----------------------------------------------------------*/
/* Critical section macros. */
- void vPortEnterCritical( void );
- void vPortExitCritical( void );
- #define portENTER_CRITICAL() \
- { \
- extern volatile UBaseType_t uxCriticalNesting; \
- microblaze_disable_interrupts(); \
- uxCriticalNesting++; \
- }
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL() { \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ microblaze_disable_interrupts(); \
+ uxCriticalNesting++; \
+ }
- #define portEXIT_CRITICAL() \
- { \
- extern volatile UBaseType_t uxCriticalNesting; \
- /* Interrupts are disabled, so we can */ \
- /* access the variable directly. */ \
- uxCriticalNesting--; \
- if( uxCriticalNesting == 0 ) \
- { \
- /* The nesting has unwound and we \
- * can enable interrupts again. */ \
- portENABLE_INTERRUPTS(); \
- } \
- }
+#define portEXIT_CRITICAL() { \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ /* Interrupts are disabled, so we can */ \
+ /* access the variable directly. */ \
+ uxCriticalNesting--; \
+ if( uxCriticalNesting == 0 ) \
+ { \
+ /* The nesting has unwound and we \
+ can enable interrupts again. */ \
+ portENABLE_INTERRUPTS(); \
+ } \
+ }
/*-----------------------------------------------------------*/
/* The yield macro maps directly to the vPortYield() function. */
- void vPortYield( void );
- #define portYIELD() vPortYield()
+void vPortYield( void );
+#define portYIELD() vPortYield()
/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
- * sets a flag to say that a yield has been requested. The interrupt exit code
- * then checks this flag, and calls vTaskSwitchContext() before restoring a task
- * context, if the flag is not false. This is done to prevent multiple calls to
- * vTaskSwitchContext() being made from a single interrupt, as a single interrupt
- * can result in multiple peripherals being serviced. */
- extern volatile uint32_t ulTaskSwitchRequested;
- #define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
+sets a flag to say that a yield has been requested. The interrupt exit code
+then checks this flag, and calls vTaskSwitchContext() before restoring a task
+context, if the flag is not false. This is done to prevent multiple calls to
+vTaskSwitchContext() being made from a single interrupt, as a single interrupt
+can result in multiple peripherals being serviced. */
+extern volatile uint32_t ulTaskSwitchRequested;
+#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
- #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
+ /* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+ return ucReturn;
+ }
- return ucReturn;
- }
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /*-----------------------------------------------------------*/
-/*-----------------------------------------------------------*/
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 4
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "NOP" )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
/* The following structure is used by the FreeRTOS exception handler. It is
- * filled with the MicroBlaze context as it was at the time the exception occurred.
- * This is done as an aid to debugging exception occurrences. */
- typedef struct PORT_REGISTER_DUMP
- {
- /* The following structure members hold the values of the MicroBlaze
- * registers at the time the exception was raised. */
- uint32_t ulR1_SP;
- uint32_t ulR2_small_data_area;
- uint32_t ulR3;
- uint32_t ulR4;
- uint32_t ulR5;
- uint32_t ulR6;
- uint32_t ulR7;
- uint32_t ulR8;
- uint32_t ulR9;
- uint32_t ulR10;
- uint32_t ulR11;
- uint32_t ulR12;
- uint32_t ulR13_read_write_small_data_area;
- uint32_t ulR14_return_address_from_interrupt;
- uint32_t ulR15_return_address_from_subroutine;
- uint32_t ulR16_return_address_from_trap;
- uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
- uint32_t ulR18;
- uint32_t ulR19;
- uint32_t ulR20;
- uint32_t ulR21;
- uint32_t ulR22;
- uint32_t ulR23;
- uint32_t ulR24;
- uint32_t ulR25;
- uint32_t ulR26;
- uint32_t ulR27;
- uint32_t ulR28;
- uint32_t ulR29;
- uint32_t ulR30;
- uint32_t ulR31;
- uint32_t ulPC;
- uint32_t ulESR;
- uint32_t ulMSR;
- uint32_t ulEAR;
- uint32_t ulFSR;
- uint32_t ulEDR;
+filled with the MicroBlaze context as it was at the time the exception occurred.
+This is done as an aid to debugging exception occurrences. */
+typedef struct PORT_REGISTER_DUMP
+{
+ /* The following structure members hold the values of the MicroBlaze
+ registers at the time the exception was raised. */
+ uint32_t ulR1_SP;
+ uint32_t ulR2_small_data_area;
+ uint32_t ulR3;
+ uint32_t ulR4;
+ uint32_t ulR5;
+ uint32_t ulR6;
+ uint32_t ulR7;
+ uint32_t ulR8;
+ uint32_t ulR9;
+ uint32_t ulR10;
+ uint32_t ulR11;
+ uint32_t ulR12;
+ uint32_t ulR13_read_write_small_data_area;
+ uint32_t ulR14_return_address_from_interrupt;
+ uint32_t ulR15_return_address_from_subroutine;
+ uint32_t ulR16_return_address_from_trap;
+ uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
+ uint32_t ulR18;
+ uint32_t ulR19;
+ uint32_t ulR20;
+ uint32_t ulR21;
+ uint32_t ulR22;
+ uint32_t ulR23;
+ uint32_t ulR24;
+ uint32_t ulR25;
+ uint32_t ulR26;
+ uint32_t ulR27;
+ uint32_t ulR28;
+ uint32_t ulR29;
+ uint32_t ulR30;
+ uint32_t ulR31;
+ uint32_t ulPC;
+ uint32_t ulESR;
+ uint32_t ulMSR;
+ uint32_t ulEAR;
+ uint32_t ulFSR;
+ uint32_t ulEDR;
- /* A human readable description of the exception cause. The strings used
- * are the same as the #define constant names found in the
- * microblaze_exceptions_i.h header file */
- int8_t * pcExceptionCause;
+ /* A human readable description of the exception cause. The strings used
+ are the same as the #define constant names found in the
+ microblaze_exceptions_i.h header file */
+ int8_t *pcExceptionCause;
- /* The human readable name of the task that was running at the time the
- * exception occurred. This is the name that was given to the task when the
- * task was created using the FreeRTOS xTaskCreate() API function. */
- char * pcCurrentTaskName;
+ /* The human readable name of the task that was running at the time the
+ exception occurred. This is the name that was given to the task when the
+ task was created using the FreeRTOS xTaskCreate() API function. */
+ char *pcCurrentTaskName;
- /* The handle of the task that was running a the time the exception
- * occurred. */
- void * xCurrentTaskHandle;
- } xPortRegisterDump;
+ /* The handle of the task that was running a the time the exception
+ occurred. */
+ void * xCurrentTaskHandle;
+
+} xPortRegisterDump;
/*
@@ -255,9 +253,7 @@
* pdPASS is returned if the function executes successfully. Any other value
* being returned indicates that the function did not execute correctly.
*/
- BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
- XInterruptHandler pxHandler,
- void * pvCallBackRef );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
/*
@@ -278,7 +274,7 @@
* XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
*
*/
- void vPortEnableInterrupt( uint8_t ucInterruptID );
+void vPortEnableInterrupt( uint8_t ucInterruptID );
/*
* Disables the interrupt, within the interrupt controller, for the peripheral
@@ -298,7 +294,7 @@
* XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
*
*/
- void vPortDisableInterrupt( uint8_t ucInterruptID );
+void vPortDisableInterrupt( uint8_t ucInterruptID );
/*
* This is an application defined callback function used to install the tick
@@ -310,7 +306,7 @@
* The name of the interrupt handler that should be installed is vPortTickISR(),
* which the function below declares as an extern.
*/
- void vApplicationSetupTimerInterrupt( void );
+void vApplicationSetupTimerInterrupt( void );
/*
* This is an application defined callback function used to clear whichever
@@ -323,7 +319,7 @@
* implementation should not require modification provided the example definition
* of vApplicationSetupTimerInterrupt() is also not modified.
*/
- void vApplicationClearTimerInterrupt( void );
+void vApplicationClearTimerInterrupt( void );
/*
* vPortExceptionsInstallHandlers() is only available when the MicroBlaze
@@ -346,7 +342,7 @@
* See the description of vApplicationExceptionRegisterDump() for information
* on the processing performed by the FreeRTOS exception handler.
*/
- void vPortExceptionsInstallHandlers( void );
+void vPortExceptionsInstallHandlers( void );
/*
* The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
@@ -362,11 +358,12 @@
* register dump information. For example, an implementation could be provided
* that wrote the register dump data to a display, or a UART port.
*/
- void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump );
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/MicroBlazeV9/port.c b/portable/GCC/MicroBlazeV9/port.c
index 9967287..943615d 100644
--- a/portable/GCC/MicroBlazeV9/port.c
+++ b/portable/GCC/MicroBlazeV9/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the MicroBlaze port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
@@ -43,20 +43,20 @@
#include <microblaze_exceptions_g.h>
/* Tasks are started with a critical section nesting of 0 - however, prior to
- * the scheduler being commenced interrupts should not be enabled, so the critical
- * nesting variable is initialised to a non-zero value. */
-#define portINITIAL_NESTING_VALUE ( 0xff )
+the scheduler being commenced interrupts should not be enabled, so the critical
+nesting variable is initialised to a non-zero value. */
+#define portINITIAL_NESTING_VALUE ( 0xff )
/* The bit within the MSR register that enabled/disables interrupts and
- * exceptions respectively. */
-#define portMSR_IE ( 0x02U )
-#define portMSR_EE ( 0x100U )
+exceptions respectively. */
+#define portMSR_IE ( 0x02U )
+#define portMSR_EE ( 0x100U )
/* If the floating point unit is included in the MicroBlaze build, then the
- * FSR register is saved as part of the task context. portINITIAL_FSR is the value
- * given to the FSR register when the initial context is set up for a task being
- * created. */
-#define portINITIAL_FSR ( 0U )
+FSR register is saved as part of the task context. portINITIAL_FSR is the value
+given to the FSR register when the initial context is set up for a task being
+created. */
+#define portINITIAL_FSR ( 0U )
/*-----------------------------------------------------------*/
@@ -73,27 +73,27 @@
/*-----------------------------------------------------------*/
/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
- * maintains its own count, so this variable is saved as part of the task
- * context. */
+maintains its own count, so this variable is saved as part of the task
+context. */
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
/* This port uses a separate stack for interrupts. This prevents the stack of
- * every task needing to be large enough to hold an entire interrupt stack on top
- * of the task stack. */
-uint32_t * pulISRStack;
+every task needing to be large enough to hold an entire interrupt stack on top
+of the task stack. */
+uint32_t *pulISRStack;
/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
- * get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
- * handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
- * will call vTaskSwitchContext() to ensure the task that runs immediately after
- * the interrupt exists is the highest priority task that is able to run. This is
- * an unusual mechanism, but is used for this port because a single interrupt can
- * cause the servicing of multiple peripherals - and it is inefficient to call
- * vTaskSwitchContext() multiple times as each peripheral is serviced. */
+get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
+handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
+will call vTaskSwitchContext() to ensure the task that runs immediately after
+the interrupt exists is the highest priority task that is able to run. This is
+an unusual mechanism, but is used for this port because a single interrupt can
+cause the servicing of multiple peripherals - and it is inefficient to call
+vTaskSwitchContext() multiple times as each peripheral is serviced. */
volatile uint32_t ulTaskSwitchRequested = 0UL;
/* The instance of the interrupt controller used by this port. This is required
- * by the Xilinx library API functions. */
+by the Xilinx library API functions. */
static XIntc xInterruptControllerInstance;
/*-----------------------------------------------------------*/
@@ -104,175 +104,173 @@
*
* See the portable.h header file.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- extern void * _SDA2_BASE_, * _SDA_BASE_;
- const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
- const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
- extern void _start1( void );
+extern void *_SDA2_BASE_, *_SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+extern void _start1( void );
- /* Place a few bytes of known values on the bottom of the stack.
- * This is essential for the Microblaze port and these lines must
- * not be omitted. */
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is essential for the Microblaze port and these lines must
+ not be omitted. */
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
- #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
- /* The FSR value placed in the initial task context is just 0. */
- *pxTopOfStack = portINITIAL_FSR;
- pxTopOfStack--;
- #endif
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ /* The FSR value placed in the initial task context is just 0. */
+ *pxTopOfStack = portINITIAL_FSR;
+ pxTopOfStack--;
+ #endif
- /* The MSR value placed in the initial task context should have interrupts
- * disabled. Each task will enable interrupts automatically when it enters
- * the running state for the first time. */
- *pxTopOfStack = mfmsr() & ~portMSR_IE;
+ /* The MSR value placed in the initial task context should have interrupts
+ disabled. Each task will enable interrupts automatically when it enters
+ the running state for the first time. */
+ *pxTopOfStack = mfmsr() & ~portMSR_IE;
- #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
- {
- /* Ensure exceptions are enabled for the task. */
- *pxTopOfStack |= portMSR_EE;
- }
- #endif
+ #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
+ {
+ /* Ensure exceptions are enabled for the task. */
+ *pxTopOfStack |= portMSR_EE;
+ }
+ #endif
- pxTopOfStack--;
+ pxTopOfStack--;
- /* First stack an initial value for the critical section nesting. This
- * is initialised to zero. */
- *pxTopOfStack = ( StackType_t ) 0x00;
+ /* First stack an initial value for the critical section nesting. This
+ is initialised to zero. */
+ *pxTopOfStack = ( StackType_t ) 0x00;
- /* R0 is always zero. */
- /* R1 is the SP. */
+ /* R0 is always zero. */
+ /* R1 is the SP. */
- /* Place an initial value for all the general purpose registers. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
+ /* Place an initial value for all the general purpose registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL; /* R8 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
- pxTopOfStack--;
- #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
- pxTopOfStack -= 8;
- #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL; /* R8 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack-= 8;
+ #endif
- *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */
+ *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
- pxTopOfStack--;
- #else
- pxTopOfStack -= 4;
- #endif
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack -= 4;
+ #endif
- *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
- pxTopOfStack -= 13;
- #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack -= 13;
+ #endif
- /* Return a pointer to the top of the stack that has been generated so this
- * can be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* Return a pointer to the top of the stack that has been generated so this
+ can be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void( vPortStartFirstTask )( void );
- extern uint32_t _stack[];
+extern void ( vPortStartFirstTask )( void );
+extern uint32_t _stack[];
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- * this function is called.
- *
- * This port uses an application defined callback function to install the tick
- * interrupt handler because the kernel will run on lots of different
- * MicroBlaze and FPGA configurations - not all of which will have the same
- * timer peripherals defined or available. An example definition of
- * vApplicationSetupTimerInterrupt() is provided in the official demo
- * application that accompanies this port. */
- vApplicationSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called.
- /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
- pulISRStack = ( uint32_t * ) _stack;
+ This port uses an application defined callback function to install the tick
+ interrupt handler because the kernel will run on lots of different
+ MicroBlaze and FPGA configurations - not all of which will have the same
+ timer peripherals defined or available. An example definition of
+ vApplicationSetupTimerInterrupt() is provided in the official demo
+ application that accompanies this port. */
+ vApplicationSetupTimerInterrupt();
- /* Ensure there is enough space for the functions called from the interrupt
- * service routines to write back into the stack frame of the caller. */
- pulISRStack -= 2;
+ /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
+ pulISRStack = ( uint32_t * ) _stack;
- /* Restore the context of the first task that is going to run. From here
- * on, the created tasks will be executing. */
- vPortStartFirstTask();
+ /* Ensure there is enough space for the functions called from the interrupt
+ service routines to write back into the stack frame of the caller. */
+ pulISRStack -= 2;
- /* Should not get here as the tasks are now running! */
- return pdFALSE;
+ /* Restore the context of the first task that is going to run. From here
+ on, the created tasks will be executing. */
+ vPortStartFirstTask();
+
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@@ -281,113 +279,110 @@
*/
void vPortYield( void )
{
- extern void VPortYieldASM( void );
+extern void VPortYieldASM( void );
- /* Perform the context switch in a critical section to assure it is
- * not interrupted by the tick ISR. It is not a problem to do this as
- * each task maintains its own interrupt status. */
- portENTER_CRITICAL();
- {
- /* Jump directly to the yield function to ensure there is no
- * compiler generated prologue code. */
- asm volatile ( "bralid r14, VPortYieldASM \n\t"\
- "or r0, r0, r0 \n\t");
- }
- portEXIT_CRITICAL();
+ /* Perform the context switch in a critical section to assure it is
+ not interrupted by the tick ISR. It is not a problem to do this as
+ each task maintains its own interrupt status. */
+ portENTER_CRITICAL();
+ {
+ /* Jump directly to the yield function to ensure there is no
+ compiler generated prologue code. */
+ asm volatile ( "bralid r14, VPortYieldASM \n\t" \
+ "or r0, r0, r0 \n\t" );
+ }
+ portEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vPortEnableInterrupt( uint8_t ucInterruptID )
{
- int32_t lReturn;
+int32_t lReturn;
- /* An API function is provided to enable an interrupt in the interrupt
- * controller because the interrupt controller instance variable is private
- * to this file. */
- lReturn = prvEnsureInterruptControllerIsInitialised();
+ /* An API function is provided to enable an interrupt in the interrupt
+ controller because the interrupt controller instance variable is private
+ to this file. */
+ lReturn = prvEnsureInterruptControllerIsInitialised();
+ if( lReturn == pdPASS )
+ {
+ /* Critical section protects read/modify/writer operation inside
+ XIntc_Enable(). */
+ portENTER_CRITICAL();
+ {
+ XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
+ }
+ portEXIT_CRITICAL();
+ }
- if( lReturn == pdPASS )
- {
- /* Critical section protects read/modify/writer operation inside
- * XIntc_Enable(). */
- portENTER_CRITICAL();
- {
- XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
- }
- portEXIT_CRITICAL();
- }
-
- configASSERT( lReturn );
+ configASSERT( lReturn );
}
/*-----------------------------------------------------------*/
void vPortDisableInterrupt( uint8_t ucInterruptID )
{
- int32_t lReturn;
+int32_t lReturn;
- /* An API function is provided to disable an interrupt in the interrupt
- * controller because the interrupt controller instance variable is private
- * to this file. */
- lReturn = prvEnsureInterruptControllerIsInitialised();
+ /* An API function is provided to disable an interrupt in the interrupt
+ controller because the interrupt controller instance variable is private
+ to this file. */
+ lReturn = prvEnsureInterruptControllerIsInitialised();
- if( lReturn == pdPASS )
- {
- XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
- }
+ if( lReturn == pdPASS )
+ {
+ XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
+ }
- configASSERT( lReturn );
+ configASSERT( lReturn );
}
/*-----------------------------------------------------------*/
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
- XInterruptHandler pxHandler,
- void * pvCallBackRef )
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
{
- int32_t lReturn;
+int32_t lReturn;
- /* An API function is provided to install an interrupt handler because the
- * interrupt controller instance variable is private to this file. */
+ /* An API function is provided to install an interrupt handler because the
+ interrupt controller instance variable is private to this file. */
- lReturn = prvEnsureInterruptControllerIsInitialised();
+ lReturn = prvEnsureInterruptControllerIsInitialised();
- if( lReturn == pdPASS )
- {
- lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
- }
+ if( lReturn == pdPASS )
+ {
+ lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
+ }
- if( lReturn == XST_SUCCESS )
- {
- lReturn = pdPASS;
- }
+ if( lReturn == XST_SUCCESS )
+ {
+ lReturn = pdPASS;
+ }
- configASSERT( lReturn == pdPASS );
+ configASSERT( lReturn == pdPASS );
- return lReturn;
+ return lReturn;
}
/*-----------------------------------------------------------*/
static int32_t prvEnsureInterruptControllerIsInitialised( void )
{
- static int32_t lInterruptControllerInitialised = pdFALSE;
- int32_t lReturn;
+static int32_t lInterruptControllerInitialised = pdFALSE;
+int32_t lReturn;
- /* Ensure the interrupt controller instance variable is initialised before
- * it is used, and that the initialisation only happens once. */
- if( lInterruptControllerInitialised != pdTRUE )
- {
- lReturn = prvInitialiseInterruptController();
+ /* Ensure the interrupt controller instance variable is initialised before
+ it is used, and that the initialisation only happens once. */
+ if( lInterruptControllerInitialised != pdTRUE )
+ {
+ lReturn = prvInitialiseInterruptController();
- if( lReturn == pdPASS )
- {
- lInterruptControllerInitialised = pdTRUE;
- }
- }
- else
- {
- lReturn = pdPASS;
- }
+ if( lReturn == pdPASS )
+ {
+ lInterruptControllerInitialised = pdTRUE;
+ }
+ }
+ else
+ {
+ lReturn = pdPASS;
+ }
- return lReturn;
+ return lReturn;
}
/*-----------------------------------------------------------*/
@@ -395,69 +390,71 @@
* Handler for the timer interrupt. This is the handler that the application
* defined callback function vApplicationSetupTimerInterrupt() should install.
*/
-void vPortTickISR( void * pvUnused )
+void vPortTickISR( void *pvUnused )
{
- extern void vApplicationClearTimerInterrupt( void );
+extern void vApplicationClearTimerInterrupt( void );
- /* Ensure the unused parameter does not generate a compiler warning. */
- ( void ) pvUnused;
+ /* Ensure the unused parameter does not generate a compiler warning. */
+ ( void ) pvUnused;
- /* This port uses an application defined callback function to clear the tick
- * interrupt because the kernel will run on lots of different MicroBlaze and
- * FPGA configurations - not all of which will have the same timer peripherals
- * defined or available. An example definition of
- * vApplicationClearTimerInterrupt() is provided in the official demo
- * application that accompanies this port. */
- vApplicationClearTimerInterrupt();
+ /* This port uses an application defined callback function to clear the tick
+ interrupt because the kernel will run on lots of different MicroBlaze and
+ FPGA configurations - not all of which will have the same timer peripherals
+ defined or available. An example definition of
+ vApplicationClearTimerInterrupt() is provided in the official demo
+ application that accompanies this port. */
+ vApplicationClearTimerInterrupt();
- /* Increment the RTOS tick - this might cause a task to unblock. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Force vTaskSwitchContext() to be called as the interrupt exits. */
- ulTaskSwitchRequested = 1;
- }
+ /* Increment the RTOS tick - this might cause a task to unblock. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Force vTaskSwitchContext() to be called as the interrupt exits. */
+ ulTaskSwitchRequested = 1;
+ }
}
/*-----------------------------------------------------------*/
static int32_t prvInitialiseInterruptController( void )
{
- int32_t lStatus;
+int32_t lStatus;
- lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
+ lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
- if( lStatus == XST_SUCCESS )
- {
- /* Initialise the exception table. */
- Xil_ExceptionInit();
+ if( lStatus == XST_SUCCESS )
+ {
+ /* Initialise the exception table. */
+ Xil_ExceptionInit();
- /* Service all pending interrupts each time the handler is entered. */
- XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
+ /* Service all pending interrupts each time the handler is entered. */
+ XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
- /* Install exception handlers if the MicroBlaze is configured to handle
- * exceptions, and the application defined constant
- * configINSTALL_EXCEPTION_HANDLERS is set to 1. */
- #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
- {
- vPortExceptionsInstallHandlers();
- }
- #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
+ /* Install exception handlers if the MicroBlaze is configured to handle
+ exceptions, and the application defined constant
+ configINSTALL_EXCEPTION_HANDLERS is set to 1. */
+ #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+ {
+ vPortExceptionsInstallHandlers();
+ }
+ #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
- /* Start the interrupt controller. Interrupts are enabled when the
- * scheduler starts. */
- lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
+ /* Start the interrupt controller. Interrupts are enabled when the
+ scheduler starts. */
+ lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
- if( lStatus == XST_SUCCESS )
- {
- lStatus = pdPASS;
- }
- else
- {
- lStatus = pdFAIL;
- }
- }
+ if( lStatus == XST_SUCCESS )
+ {
+ lStatus = pdPASS;
+ }
+ else
+ {
+ lStatus = pdFAIL;
+ }
+ }
- configASSERT( lStatus == pdPASS );
+ configASSERT( lStatus == pdPASS );
- return lStatus;
+ return lStatus;
}
/*-----------------------------------------------------------*/
+
+
diff --git a/portable/GCC/MicroBlazeV9/port_exceptions.c b/portable/GCC/MicroBlazeV9/port_exceptions.c
index 6d798cc..ca2a1ac 100644
--- a/portable/GCC/MicroBlazeV9/port_exceptions.c
+++ b/portable/GCC/MicroBlazeV9/port_exceptions.c
@@ -34,244 +34,249 @@
#include <microblaze_exceptions_g.h>
/* The Xilinx library defined exception entry point stacks a number of
- * registers. These definitions are offsets from the stack pointer to the various
- * stacked register values. */
-#define portexR3_STACK_OFFSET 4
-#define portexR4_STACK_OFFSET 5
-#define portexR5_STACK_OFFSET 6
-#define portexR6_STACK_OFFSET 7
-#define portexR7_STACK_OFFSET 8
-#define portexR8_STACK_OFFSET 9
-#define portexR9_STACK_OFFSET 10
-#define portexR10_STACK_OFFSET 11
-#define portexR11_STACK_OFFSET 12
-#define portexR12_STACK_OFFSET 13
-#define portexR15_STACK_OFFSET 16
-#define portexR18_STACK_OFFSET 19
-#define portexMSR_STACK_OFFSET 20
-#define portexR19_STACK_OFFSET -1
+registers. These definitions are offsets from the stack pointer to the various
+stacked register values. */
+#define portexR3_STACK_OFFSET 4
+#define portexR4_STACK_OFFSET 5
+#define portexR5_STACK_OFFSET 6
+#define portexR6_STACK_OFFSET 7
+#define portexR7_STACK_OFFSET 8
+#define portexR8_STACK_OFFSET 9
+#define portexR9_STACK_OFFSET 10
+#define portexR10_STACK_OFFSET 11
+#define portexR11_STACK_OFFSET 12
+#define portexR12_STACK_OFFSET 13
+#define portexR15_STACK_OFFSET 16
+#define portexR18_STACK_OFFSET 19
+#define portexMSR_STACK_OFFSET 20
+#define portexR19_STACK_OFFSET -1
/* This is defined to equal the size, in bytes, of the stack frame generated by
- * the Xilinx standard library exception entry point. It is required to determine
- * the stack pointer value prior to the exception being entered. */
-#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
+the Xilinx standard library exception entry point. It is required to determine
+the stack pointer value prior to the exception being entered. */
+#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
/* The number of bytes a MicroBlaze instruction consumes. */
-#define portexINSTRUCTION_SIZE 4
+#define portexINSTRUCTION_SIZE 4
/* Exclude this entire file if the MicroBlaze is not configured to handle
- * exceptions, or the application defined configuration constant
- * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+exceptions, or the application defined configuration constant
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
/* This variable is set in the exception entry code, before
- * vPortExceptionHandler is called. */
- uint32_t * pulStackPointerOnFunctionEntry = NULL;
+vPortExceptionHandler is called. */
+uint32_t *pulStackPointerOnFunctionEntry = NULL;
/* This is the structure that is filled with the MicroBlaze context as it
- * existed immediately prior to the exception occurrence. A pointer to this
- * structure is passed into the vApplicationExceptionRegisterDump() callback
- * function, if one is defined. */
- static xPortRegisterDump xRegisterDump;
+existed immediately prior to the exception occurrence. A pointer to this
+structure is passed into the vApplicationExceptionRegisterDump() callback
+function, if one is defined. */
+static xPortRegisterDump xRegisterDump;
/* This is the FreeRTOS exception handler that is installed for all exception
- * types. It is called from vPortExceptionHanlderEntry() - which is itself defined
- * in portasm.S. */
- void vPortExceptionHandler( void * pvExceptionID );
- extern void vPortExceptionHandlerEntry( void * pvExceptionID );
+types. It is called from vPortExceptionHanlderEntry() - which is itself defined
+in portasm.S. */
+void vPortExceptionHandler( void *pvExceptionID );
+extern void vPortExceptionHandlerEntry( void *pvExceptionID );
/*-----------------------------------------------------------*/
/* vApplicationExceptionRegisterDump() is a callback function that the
- * application can optionally define to receive a populated xPortRegisterDump
- * structure. If the application chooses not to define a version of
- * vApplicationExceptionRegisterDump() then this weekly defined default
- * implementation will be called instead. */
- extern void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) __attribute__( ( weak ) );
- void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump )
- {
- ( void ) xRegisterDump;
+application can optionally define to receive a populated xPortRegisterDump
+structure. If the application chooses not to define a version of
+vApplicationExceptionRegisterDump() then this weekly defined default
+implementation will be called instead. */
+extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
+{
+ ( void ) xRegisterDump;
- for( ; ; )
- {
- portNOP();
- }
- }
+ for( ;; )
+ {
+ portNOP();
+ }
+}
/*-----------------------------------------------------------*/
- void vPortExceptionHandler( void * pvExceptionID )
- {
- extern void * pxCurrentTCB;
+void vPortExceptionHandler( void *pvExceptionID )
+{
+extern void *pxCurrentTCB;
- /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
- * was immediately before the exception occurrence. */
+ /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
+ was immediately before the exception occurrence. */
- /* First fill in the name and handle of the task that was in the Running
- * state when the exception occurred. */
- xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
- xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
+ /* First fill in the name and handle of the task that was in the Running
+ state when the exception occurred. */
+ xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
+ xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
- configASSERT( pulStackPointerOnFunctionEntry );
+ configASSERT( pulStackPointerOnFunctionEntry );
- /* Obtain the values of registers that were stacked prior to this function
- * being called, and may have changed since they were stacked. */
- xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
- xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
- xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
- xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
- xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
- xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
- xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
- xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
- xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
- xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
- xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
- xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
- xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
- xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
+ /* Obtain the values of registers that were stacked prior to this function
+ being called, and may have changed since they were stacked. */
+ xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
+ xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
+ xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
+ xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
+ xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
+ xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
+ xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
+ xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
+ xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
+ xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
+ xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
+ xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
+ xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
+ xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
- /* Obtain the value of all other registers. */
- xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
- xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
- xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
- xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
- xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
- xRegisterDump.ulR20 = mfgpr( R20 );
- xRegisterDump.ulR21 = mfgpr( R21 );
- xRegisterDump.ulR22 = mfgpr( R22 );
- xRegisterDump.ulR23 = mfgpr( R23 );
- xRegisterDump.ulR24 = mfgpr( R24 );
- xRegisterDump.ulR25 = mfgpr( R25 );
- xRegisterDump.ulR26 = mfgpr( R26 );
- xRegisterDump.ulR27 = mfgpr( R27 );
- xRegisterDump.ulR28 = mfgpr( R28 );
- xRegisterDump.ulR29 = mfgpr( R29 );
- xRegisterDump.ulR30 = mfgpr( R30 );
- xRegisterDump.ulR31 = mfgpr( R31 );
- xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
- xRegisterDump.ulEAR = mfear();
- xRegisterDump.ulESR = mfesr();
- xRegisterDump.ulEDR = mfedr();
+ /* Obtain the value of all other registers. */
+ xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
+ xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
+ xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
+ xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
+ xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
+ xRegisterDump.ulR20 = mfgpr( R20 );
+ xRegisterDump.ulR21 = mfgpr( R21 );
+ xRegisterDump.ulR22 = mfgpr( R22 );
+ xRegisterDump.ulR23 = mfgpr( R23 );
+ xRegisterDump.ulR24 = mfgpr( R24 );
+ xRegisterDump.ulR25 = mfgpr( R25 );
+ xRegisterDump.ulR26 = mfgpr( R26 );
+ xRegisterDump.ulR27 = mfgpr( R27 );
+ xRegisterDump.ulR28 = mfgpr( R28 );
+ xRegisterDump.ulR29 = mfgpr( R29 );
+ xRegisterDump.ulR30 = mfgpr( R30 );
+ xRegisterDump.ulR31 = mfgpr( R31 );
+ xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+ xRegisterDump.ulEAR = mfear();
+ xRegisterDump.ulESR = mfesr();
+ xRegisterDump.ulEDR = mfedr();
- /* Move the saved program counter back to the instruction that was executed
- * when the exception occurred. This is only valid for certain types of
- * exception. */
- xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
+ /* Move the saved program counter back to the instruction that was executed
+ when the exception occurred. This is only valid for certain types of
+ exception. */
+ xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
- #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
- {
- xRegisterDump.ulFSR = mffsr();
- }
- #else
- {
- xRegisterDump.ulFSR = 0UL;
- }
- #endif
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ {
+ xRegisterDump.ulFSR = mffsr();
+ }
+ #else
+ {
+ xRegisterDump.ulFSR = 0UL;
+ }
+ #endif
- /* Also fill in a string that describes what type of exception this is.
- * The string uses the same ID names as defined in the MicroBlaze standard
- * library exception header files. */
- switch( ( uint32_t ) pvExceptionID )
- {
- case XEXC_ID_FSL:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
- break;
+ /* Also fill in a string that describes what type of exception this is.
+ The string uses the same ID names as defined in the MicroBlaze standard
+ library exception header files. */
+ switch( ( uint32_t ) pvExceptionID )
+ {
+ case XEXC_ID_FSL :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
+ break;
- case XEXC_ID_UNALIGNED_ACCESS:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
- break;
+ case XEXC_ID_UNALIGNED_ACCESS :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
+ break;
- case XEXC_ID_ILLEGAL_OPCODE:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
- break;
+ case XEXC_ID_ILLEGAL_OPCODE :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
+ break;
- case XEXC_ID_M_AXI_I_EXCEPTION:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
- break;
+ case XEXC_ID_M_AXI_I_EXCEPTION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
+ break;
- case XEXC_ID_M_AXI_D_EXCEPTION:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
- break;
+ case XEXC_ID_M_AXI_D_EXCEPTION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
+ break;
- case XEXC_ID_DIV_BY_ZERO:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
- break;
+ case XEXC_ID_DIV_BY_ZERO :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
+ break;
- case XEXC_ID_STACK_VIOLATION:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
- break;
+ case XEXC_ID_STACK_VIOLATION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
+ break;
- #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
- case XEXC_ID_FPU:
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
- break;
- #endif /* XPAR_MICROBLAZE_USE_FPU */
- }
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
- /* vApplicationExceptionRegisterDump() is a callback function that the
- * application can optionally define to receive the populated xPortRegisterDump
- * structure. If the application chooses not to define a version of
- * vApplicationExceptionRegisterDump() then the weekly defined default
- * implementation within this file will be called instead. */
- vApplicationExceptionRegisterDump( &xRegisterDump );
+ case XEXC_ID_FPU :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
+ break;
- /* Must not attempt to leave this function! */
- for( ; ; )
- {
- portNOP();
- }
- }
+ #endif /* XPAR_MICROBLAZE_USE_FPU */
+ }
+
+ /* vApplicationExceptionRegisterDump() is a callback function that the
+ application can optionally define to receive the populated xPortRegisterDump
+ structure. If the application chooses not to define a version of
+ vApplicationExceptionRegisterDump() then the weekly defined default
+ implementation within this file will be called instead. */
+ vApplicationExceptionRegisterDump( &xRegisterDump );
+
+ /* Must not attempt to leave this function! */
+ for( ;; )
+ {
+ portNOP();
+ }
+}
/*-----------------------------------------------------------*/
- void vPortExceptionsInstallHandlers( void )
- {
- static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
+void vPortExceptionsInstallHandlers( void )
+{
+static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
- if( ulHandlersAlreadyInstalled == pdFALSE )
- {
- ulHandlersAlreadyInstalled = pdTRUE;
+ if( ulHandlersAlreadyInstalled == pdFALSE )
+ {
+ ulHandlersAlreadyInstalled = pdTRUE;
- #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
- microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
- #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
+ #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
+ microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
+ #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
- #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
- #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
+ #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
+ #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
- #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
+ #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
- #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
+ #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
- #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
+ #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
- #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
+ #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
- #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
- #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
+ #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
+ #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
- #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
- #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
+ #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
+ #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
- #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
- #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+ #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
+ #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
- microblaze_enable_exceptions();
- }
- }
+ microblaze_enable_exceptions();
+ }
+}
/* Exclude the entire file if the MicroBlaze is not configured to handle
- * exceptions, or the application defined configuration item
- * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+exceptions, or the application defined configuration item
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
+
+
+
diff --git a/portable/GCC/MicroBlazeV9/portmacro.h b/portable/GCC/MicroBlazeV9/portmacro.h
index 5b5840e..19b5288 100644
--- a/portable/GCC/MicroBlazeV9/portmacro.h
+++ b/portable/GCC/MicroBlazeV9/portmacro.h
@@ -26,15 +26,15 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* BSP includes. */
- #include <mb_interface.h>
- #include <xparameters.h>
+#include <mb_interface.h>
+#include <xparameters.h>
/*-----------------------------------------------------------
* Port specific definitions.
@@ -47,177 +47,175 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros and functions. */
- void microblaze_disable_interrupts( void );
- void microblaze_enable_interrupts( void );
- #define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
- #define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
/*-----------------------------------------------------------*/
/* Critical section macros. */
- void vPortEnterCritical( void );
- void vPortExitCritical( void );
- #define portENTER_CRITICAL() \
- { \
- extern volatile UBaseType_t uxCriticalNesting; \
- microblaze_disable_interrupts(); \
- uxCriticalNesting++; \
- }
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL() { \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ microblaze_disable_interrupts(); \
+ uxCriticalNesting++; \
+ }
- #define portEXIT_CRITICAL() \
- { \
- extern volatile UBaseType_t uxCriticalNesting; \
- /* Interrupts are disabled, so we can */ \
- /* access the variable directly. */ \
- uxCriticalNesting--; \
- if( uxCriticalNesting == 0 ) \
- { \
- /* The nesting has unwound and we \
- * can enable interrupts again. */ \
- portENABLE_INTERRUPTS(); \
- } \
- }
+#define portEXIT_CRITICAL() { \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ /* Interrupts are disabled, so we can */ \
+ /* access the variable directly. */ \
+ uxCriticalNesting--; \
+ if( uxCriticalNesting == 0 ) \
+ { \
+ /* The nesting has unwound and we \
+ can enable interrupts again. */ \
+ portENABLE_INTERRUPTS(); \
+ } \
+ }
/*-----------------------------------------------------------*/
/* The yield macro maps directly to the vPortYield() function. */
- void vPortYield( void );
- #define portYIELD() vPortYield()
+void vPortYield( void );
+#define portYIELD() vPortYield()
/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
- * sets a flag to say that a yield has been requested. The interrupt exit code
- * then checks this flag, and calls vTaskSwitchContext() before restoring a task
- * context, if the flag is not false. This is done to prevent multiple calls to
- * vTaskSwitchContext() being made from a single interrupt, as a single interrupt
- * can result in multiple peripherals being serviced. */
- extern volatile uint32_t ulTaskSwitchRequested;
- #define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
+sets a flag to say that a yield has been requested. The interrupt exit code
+then checks this flag, and calls vTaskSwitchContext() before restoring a task
+context, if the flag is not false. This is done to prevent multiple calls to
+vTaskSwitchContext() being made from a single interrupt, as a single interrupt
+can result in multiple peripherals being serviced. */
+extern volatile uint32_t ulTaskSwitchRequested;
+#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
- #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
+ /* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+ return ucReturn;
+ }
- return ucReturn;
- }
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /*-----------------------------------------------------------*/
-/*-----------------------------------------------------------*/
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 4
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "NOP" )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
/* The following structure is used by the FreeRTOS exception handler. It is
- * filled with the MicroBlaze context as it was at the time the exception occurred.
- * This is done as an aid to debugging exception occurrences. */
- typedef struct PORT_REGISTER_DUMP
- {
- /* The following structure members hold the values of the MicroBlaze
- * registers at the time the exception was raised. */
- uint32_t ulR1_SP;
- uint32_t ulR2_small_data_area;
- uint32_t ulR3;
- uint32_t ulR4;
- uint32_t ulR5;
- uint32_t ulR6;
- uint32_t ulR7;
- uint32_t ulR8;
- uint32_t ulR9;
- uint32_t ulR10;
- uint32_t ulR11;
- uint32_t ulR12;
- uint32_t ulR13_read_write_small_data_area;
- uint32_t ulR14_return_address_from_interrupt;
- uint32_t ulR15_return_address_from_subroutine;
- uint32_t ulR16_return_address_from_trap;
- uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
- uint32_t ulR18;
- uint32_t ulR19;
- uint32_t ulR20;
- uint32_t ulR21;
- uint32_t ulR22;
- uint32_t ulR23;
- uint32_t ulR24;
- uint32_t ulR25;
- uint32_t ulR26;
- uint32_t ulR27;
- uint32_t ulR28;
- uint32_t ulR29;
- uint32_t ulR30;
- uint32_t ulR31;
- uint32_t ulPC;
- uint32_t ulESR;
- uint32_t ulMSR;
- uint32_t ulEAR;
- uint32_t ulFSR;
- uint32_t ulEDR;
+filled with the MicroBlaze context as it was at the time the exception occurred.
+This is done as an aid to debugging exception occurrences. */
+typedef struct PORT_REGISTER_DUMP
+{
+ /* The following structure members hold the values of the MicroBlaze
+ registers at the time the exception was raised. */
+ uint32_t ulR1_SP;
+ uint32_t ulR2_small_data_area;
+ uint32_t ulR3;
+ uint32_t ulR4;
+ uint32_t ulR5;
+ uint32_t ulR6;
+ uint32_t ulR7;
+ uint32_t ulR8;
+ uint32_t ulR9;
+ uint32_t ulR10;
+ uint32_t ulR11;
+ uint32_t ulR12;
+ uint32_t ulR13_read_write_small_data_area;
+ uint32_t ulR14_return_address_from_interrupt;
+ uint32_t ulR15_return_address_from_subroutine;
+ uint32_t ulR16_return_address_from_trap;
+ uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
+ uint32_t ulR18;
+ uint32_t ulR19;
+ uint32_t ulR20;
+ uint32_t ulR21;
+ uint32_t ulR22;
+ uint32_t ulR23;
+ uint32_t ulR24;
+ uint32_t ulR25;
+ uint32_t ulR26;
+ uint32_t ulR27;
+ uint32_t ulR28;
+ uint32_t ulR29;
+ uint32_t ulR30;
+ uint32_t ulR31;
+ uint32_t ulPC;
+ uint32_t ulESR;
+ uint32_t ulMSR;
+ uint32_t ulEAR;
+ uint32_t ulFSR;
+ uint32_t ulEDR;
- /* A human readable description of the exception cause. The strings used
- * are the same as the #define constant names found in the
- * microblaze_exceptions_i.h header file */
- int8_t * pcExceptionCause;
+ /* A human readable description of the exception cause. The strings used
+ are the same as the #define constant names found in the
+ microblaze_exceptions_i.h header file */
+ int8_t *pcExceptionCause;
- /* The human readable name of the task that was running at the time the
- * exception occurred. This is the name that was given to the task when the
- * task was created using the FreeRTOS xTaskCreate() API function. */
- char * pcCurrentTaskName;
+ /* The human readable name of the task that was running at the time the
+ exception occurred. This is the name that was given to the task when the
+ task was created using the FreeRTOS xTaskCreate() API function. */
+ char *pcCurrentTaskName;
- /* The handle of the task that was running a the time the exception
- * occurred. */
- void * xCurrentTaskHandle;
- } xPortRegisterDump;
+ /* The handle of the task that was running a the time the exception
+ occurred. */
+ void * xCurrentTaskHandle;
+
+} xPortRegisterDump;
/*
@@ -255,9 +253,7 @@
* pdPASS is returned if the function executes successfully. Any other value
* being returned indicates that the function did not execute correctly.
*/
- BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
- XInterruptHandler pxHandler,
- void * pvCallBackRef );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
/*
@@ -278,7 +274,7 @@
* XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
*
*/
- void vPortEnableInterrupt( uint8_t ucInterruptID );
+void vPortEnableInterrupt( uint8_t ucInterruptID );
/*
* Disables the interrupt, within the interrupt controller, for the peripheral
@@ -298,7 +294,7 @@
* XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
*
*/
- void vPortDisableInterrupt( uint8_t ucInterruptID );
+void vPortDisableInterrupt( uint8_t ucInterruptID );
/*
* This is an application defined callback function used to install the tick
@@ -310,7 +306,7 @@
* The name of the interrupt handler that should be installed is vPortTickISR(),
* which the function below declares as an extern.
*/
- void vApplicationSetupTimerInterrupt( void );
+void vApplicationSetupTimerInterrupt( void );
/*
* This is an application defined callback function used to clear whichever
@@ -323,7 +319,7 @@
* implementation should not require modification provided the example definition
* of vApplicationSetupTimerInterrupt() is also not modified.
*/
- void vApplicationClearTimerInterrupt( void );
+void vApplicationClearTimerInterrupt( void );
/*
* vPortExceptionsInstallHandlers() is only available when the MicroBlaze
@@ -346,7 +342,7 @@
* See the description of vApplicationExceptionRegisterDump() for information
* on the processing performed by the FreeRTOS exception handler.
*/
- void vPortExceptionsInstallHandlers( void );
+void vPortExceptionsInstallHandlers( void );
/*
* The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
@@ -362,11 +358,12 @@
* register dump information. For example, an implementation could be provided
* that wrote the register dump data to a display, or a UART port.
*/
- void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump );
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/NiosII/port.c b/portable/GCC/NiosII/port.c
index 845d50c..57b5337 100644
--- a/portable/GCC/NiosII/port.c
+++ b/portable/GCC/NiosII/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the NIOS2 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the NIOS2 port.
+ *----------------------------------------------------------*/
/* Standard Includes. */
#include <string.h>
@@ -43,11 +43,11 @@
#include "task.h"
/* Interrupts are enabled. */
-#define portINITIAL_ESTATUS ( StackType_t ) 0x01
+#define portINITIAL_ESTATUS ( StackType_t ) 0x01
/*-----------------------------------------------------------*/
-/*
+/*
* Setup the timer to generate the tick interrupts.
*/
static void prvSetupTimerInterrupt( void );
@@ -55,80 +55,77 @@
/*
* Call back for the alarm function.
*/
-void vPortSysTickHandler( void * context,
- alt_u32 id );
+void vPortSysTickHandler( void * context, alt_u32 id );
/*-----------------------------------------------------------*/
-static void prvReadGp( uint32_t * ulValue )
+static void prvReadGp( uint32_t *ulValue )
{
- asm ( "stw gp, (%0)" ::"r" ( ulValue ) );
+ asm( "stw gp, (%0)" :: "r"(ulValue) );
}
/*-----------------------------------------------------------*/
-/*
- * See header file for description.
+/*
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
-{
- StackType_t * pxFramePointer = pxTopOfStack - 1;
- StackType_t xGlobalPointer;
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxFramePointer = pxTopOfStack - 1;
+StackType_t xGlobalPointer;
- prvReadGp( &xGlobalPointer );
+ prvReadGp( &xGlobalPointer );
/* End of stack marker. */
*pxTopOfStack = 0xdeadbeef;
pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) pxFramePointer;
+
+ *pxTopOfStack = ( StackType_t ) pxFramePointer;
pxTopOfStack--;
-
- *pxTopOfStack = xGlobalPointer;
-
+
+ *pxTopOfStack = xGlobalPointer;
+
/* Space for R23 to R16. */
pxTopOfStack -= 9;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ *pxTopOfStack = ( StackType_t ) pxCode;
pxTopOfStack--;
- *pxTopOfStack = portINITIAL_ESTATUS;
+ *pxTopOfStack = portINITIAL_ESTATUS;
- /* Space for R15 to R5. */
+ /* Space for R15 to R5. */
pxTopOfStack -= 12;
-
- *pxTopOfStack = ( StackType_t ) pvParameters;
+
+ *pxTopOfStack = ( StackType_t ) pvParameters;
/* Space for R3 to R1, muldiv and RA. */
pxTopOfStack -= 5;
-
+
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
-/*
- * See header file for description.
+/*
+ * See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
+
+ /* Start the first task. */
+ asm volatile ( " movia r2, restore_sp_from_pxCurrentTCB \n"
+ " jmp r2 " );
- /* Start the first task. */
- asm volatile ( " movia r2, restore_sp_from_pxCurrentTCB \n"
- " jmp r2 " );
-
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the NIOS2 port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the NIOS2 port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
@@ -138,71 +135,69 @@
*/
void prvSetupTimerInterrupt( void )
{
- /* Try to register the interrupt handler. */
- if( -EINVAL == alt_irq_register( SYS_CLK_IRQ, 0x0, vPortSysTickHandler ) )
- {
- /* Failed to install the Interrupt Handler. */
- asm ( "break" );
- }
- else
- {
- /* Configure SysTick to interrupt at the requested rate. */
- IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK );
- IOWR_ALTERA_AVALON_TIMER_PERIODL( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) & 0xFFFF );
- IOWR_ALTERA_AVALON_TIMER_PERIODH( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) >> 16 );
- IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK );
- }
+ /* Try to register the interrupt handler. */
+ if ( -EINVAL == alt_irq_register( SYS_CLK_IRQ, 0x0, vPortSysTickHandler ) )
+ {
+ /* Failed to install the Interrupt Handler. */
+ asm( "break" );
+ }
+ else
+ {
+ /* Configure SysTick to interrupt at the requested rate. */
+ IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK );
+ IOWR_ALTERA_AVALON_TIMER_PERIODL( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) & 0xFFFF );
+ IOWR_ALTERA_AVALON_TIMER_PERIODH( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) >> 16 );
+ IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK );
+ }
- /* Clear any already pending interrupts generated by the Timer. */
- IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
+ /* Clear any already pending interrupts generated by the Timer. */
+ IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
}
/*-----------------------------------------------------------*/
-void vPortSysTickHandler( void * context,
- alt_u32 id )
+void vPortSysTickHandler( void * context, alt_u32 id )
{
- /* Increment the kernel tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
+ /* Increment the kernel tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
vTaskSwitchContext();
- }
-
- /* Clear the interrupt. */
- IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
+ }
+
+ /* Clear the interrupt. */
+ IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
}
/*-----------------------------------------------------------*/
/** This function is a re-implementation of the Altera provided function.
* The function is re-implemented to prevent it from enabling an interrupt
* when it is registered. Interrupts should only be enabled after the FreeRTOS.org
- * kernel has its scheduler started so that contexts are saved and switched
+ * kernel has its scheduler started so that contexts are saved and switched
* correctly.
*/
-int alt_irq_register( alt_u32 id,
- void * context,
- void ( * handler )( void *, alt_u32 ) )
+int alt_irq_register( alt_u32 id, void* context, void (*handler)(void*, alt_u32) )
{
- int rc = -EINVAL;
- alt_irq_context status;
+ int rc = -EINVAL;
+ alt_irq_context status;
- if( id < ALT_NIRQ )
- {
- /*
- * interrupts are disabled while the handler tables are updated to ensure
- * that an interrupt doesn't occur while the tables are in an inconsistent
- * state.
- */
-
- status = alt_irq_disable_all();
-
- alt_irq[ id ].handler = handler;
- alt_irq[ id ].context = context;
-
- rc = ( handler ) ? alt_irq_enable( id ) : alt_irq_disable( id );
-
- /* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */
- }
-
- return rc;
+ if (id < ALT_NIRQ)
+ {
+ /*
+ * interrupts are disabled while the handler tables are updated to ensure
+ * that an interrupt doesn't occur while the tables are in an inconsistent
+ * state.
+ */
+
+ status = alt_irq_disable_all ();
+
+ alt_irq[id].handler = handler;
+ alt_irq[id].context = context;
+
+ rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id);
+
+ /* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */
+ }
+
+ return rc;
}
/*-----------------------------------------------------------*/
+
diff --git a/portable/GCC/NiosII/portmacro.h b/portable/GCC/NiosII/portmacro.h
index 7263e19..3695fef 100644
--- a/portable/GCC/NiosII/portmacro.h
+++ b/portable/GCC/NiosII/portmacro.h
@@ -26,13 +26,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
- #include "sys/alt_irq.h"
+#include "sys/alt_irq.h"
/*-----------------------------------------------------------
* Port specific definitions.
@@ -45,64 +45,65 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 4
- #define portNOP() asm volatile ( "NOP" )
- #define portCRITICAL_NESTING_IN_TCB 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() asm volatile ( "NOP" )
+#define portCRITICAL_NESTING_IN_TCB 1
/*-----------------------------------------------------------*/
- extern void vTaskSwitchContext( void );
- #define portYIELD() asm volatile ( "trap" );
- #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
+extern void vTaskSwitchContext( void );
+#define portYIELD() asm volatile ( "trap" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
/* Include the port_asm.S file where the Context saving/restoring is defined. */
- __asm__ ( "\n\t.globl save_context");
+__asm__( "\n\t.globl save_context" );
/*-----------------------------------------------------------*/
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
- #define portDISABLE_INTERRUPTS() alt_irq_disable_all()
- #define portENABLE_INTERRUPTS() alt_irq_enable_all( 0x01 );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+#define portDISABLE_INTERRUPTS() alt_irq_disable_all()
+#define portENABLE_INTERRUPTS() alt_irq_enable_all( 0x01 );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/portable/GCC/PPC405_Xilinx/FPU_Macros.h
index 891cd7b..dd8ddee 100644
--- a/portable/GCC/PPC405_Xilinx/FPU_Macros.h
+++ b/portable/GCC/PPC405_Xilinx/FPU_Macros.h
@@ -26,19 +26,20 @@
*/
/* When switching out a task, if the task tag contains a buffer address then
- * save the flop context into the buffer. */
-#define traceTASK_SWITCHED_OUT() \
- if( pxCurrentTCB->pxTaskTag != NULL ) \
- { \
- extern void vPortSaveFPURegisters( void * ); \
- vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
- }
+save the flop context into the buffer. */
+#define traceTASK_SWITCHED_OUT() \
+ if( pxCurrentTCB->pxTaskTag != NULL ) \
+ { \
+ extern void vPortSaveFPURegisters( void * ); \
+ vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
+ }
/* When switching in a task, if the task tag contains a buffer address then
- * load the flop context from the buffer. */
-#define traceTASK_SWITCHED_IN() \
- if( pxCurrentTCB->pxTaskTag != NULL ) \
- { \
- extern void vPortRestoreFPURegisters( void * ); \
- vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
- }
+load the flop context from the buffer. */
+#define traceTASK_SWITCHED_IN() \
+ if( pxCurrentTCB->pxTaskTag != NULL ) \
+ { \
+ extern void vPortRestoreFPURegisters( void * ); \
+ vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
+ }
+
diff --git a/portable/GCC/PPC405_Xilinx/port.c b/portable/GCC/PPC405_Xilinx/port.c
index 5891ecf..286e937 100644
--- a/portable/GCC/PPC405_Xilinx/port.c
+++ b/portable/GCC/PPC405_Xilinx/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PPC405 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PPC405 port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
@@ -42,19 +42,19 @@
/*-----------------------------------------------------------*/
/* Definitions to set the initial MSR of each task. */
-#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
-#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
-#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
+#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
+#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
+#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
#if configUSE_FPU == 1
- #define portAPU_PRESENT ( 1UL << 25UL )
- #define portFCM_FPU_PRESENT ( 1UL << 13UL )
+ #define portAPU_PRESENT ( 1UL << 25UL )
+ #define portFCM_FPU_PRESENT ( 1UL << 13UL )
#else
- #define portAPU_PRESENT ( 0UL )
- #define portFCM_FPU_PRESENT ( 0UL )
+ #define portAPU_PRESENT ( 0UL )
+ #define portFCM_FPU_PRESENT ( 0UL )
#endif
-#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
+#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
extern const unsigned _SDA_BASE_;
@@ -90,177 +90,171 @@
/*-----------------------------------------------------------*/
-/*
+/*
* Initialise the stack of a task to look exactly as if the task had been
* interrupted.
- *
+ *
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Place a known value at the bottom of the stack for debugging. */
- *pxTopOfStack = 0xDEADBEEF;
- pxTopOfStack--;
+ /* Place a known value at the bottom of the stack for debugging. */
+ *pxTopOfStack = 0xDEADBEEF;
+ pxTopOfStack--;
- /* EABI stack frame. */
- pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
+ /* EABI stack frame. */
+ pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
- /* Parameters in R13. */
- *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
- pxTopOfStack -= 10;
+ /* Parameters in R13. */
+ *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
+ pxTopOfStack -= 10;
- /* Parameters in R3. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
+ /* Parameters in R3. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
- /* Parameters in R2. */
- *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
- pxTopOfStack--;
+ /* Parameters in R2. */
+ *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
+ pxTopOfStack--;
- /* R1 is the stack pointer so is omitted. */
+ /* R1 is the stack pointer so is omitted. */
- *pxTopOfStack = 0x10000001UL; /* R0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* USPRG0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* CR. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* XER. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* CTR. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_MSR; /* SRR1. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* Next LR. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* Backchain. */
+ *pxTopOfStack = 0x10000001UL;; /* R0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* USPRG0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* CR. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* XER. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* CTR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_MSR;/* SRR1. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL;/* Backchain. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- prvSetupTimerInterrupt();
- XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
- vPortStartFirstTask();
+ prvSetupTimerInterrupt();
+ XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
+ vPortStartFirstTask();
- /* Should not get here as the tasks are now running! */
- return pdFALSE;
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented. */
- for( ; ; )
- {
- }
+ /* Not implemented. */
+ for( ;; );
}
/*-----------------------------------------------------------*/
/*
- * Hardware initialisation to generate the RTOS tick.
+ * Hardware initialisation to generate the RTOS tick.
*/
static void prvSetupTimerInterrupt( void )
{
- const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
+const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
- XTime_PITClearInterrupt();
- XTime_FITClearInterrupt();
- XTime_WDTClearInterrupt();
- XTime_WDTDisableInterrupt();
- XTime_FITDisableInterrupt();
+ XTime_PITClearInterrupt();
+ XTime_FITClearInterrupt();
+ XTime_WDTClearInterrupt();
+ XTime_WDTDisableInterrupt();
+ XTime_FITDisableInterrupt();
- XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
+ XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
- XTime_PITEnableAutoReload();
- XTime_PITSetInterval( ulInterval );
- XTime_PITEnableInterrupt();
+ XTime_PITEnableAutoReload();
+ XTime_PITSetInterval( ulInterval );
+ XTime_PITEnableInterrupt();
}
/*-----------------------------------------------------------*/
-void vPortISRHandler( void * pvNullDoNotUse )
+void vPortISRHandler( void *pvNullDoNotUse )
{
- uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
- BaseType_t xInterruptNumber;
- XIntc_Config * pxInterruptController;
- XIntc_VectorTableEntry * pxTable;
+uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
+BaseType_t xInterruptNumber;
+XIntc_Config *pxInterruptController;
+XIntc_VectorTableEntry *pxTable;
- /* Just to remove compiler warning. */
- ( void ) pvNullDoNotUse;
+ /* Just to remove compiler warning. */
+ ( void ) pvNullDoNotUse;
- /* Get the configuration by using the device ID - in this case it is
- * assumed that only one interrupt controller is being used. */
- pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
+ /* Get the configuration by using the device ID - in this case it is
+ assumed that only one interrupt controller is being used. */
+ pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
+
+ /* Which interrupts are pending? */
+ ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
+
+ for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
+ {
+ if( ulInterruptStatus & 0x01UL )
+ {
+ /* Clear the pending interrupt. */
+ XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
- /* Which interrupts are pending? */
- ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
+ /* Call the registered handler. */
+ pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
+ pxTable->Handler( pxTable->CallBackRef );
+ }
+
+ /* Check the next interrupt. */
+ ulInterruptMask <<= 0x01UL;
+ ulInterruptStatus >>= 0x01UL;
- for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
- {
- if( ulInterruptStatus & 0x01UL )
- {
- /* Clear the pending interrupt. */
- XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
-
- /* Call the registered handler. */
- pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
- pxTable->Handler( pxTable->CallBackRef );
- }
-
- /* Check the next interrupt. */
- ulInterruptMask <<= 0x01UL;
- ulInterruptStatus >>= 0x01UL;
-
- /* Have we serviced all interrupts? */
- if( ulInterruptStatus == 0UL )
- {
- break;
- }
- }
+ /* Have we serviced all interrupts? */
+ if( ulInterruptStatus == 0UL )
+ {
+ break;
+ }
+ }
}
/*-----------------------------------------------------------*/
void vPortSetupInterruptController( void )
{
- extern void vPortISRWrapper( void );
+extern void vPortISRWrapper( void );
- /* Perform all library calls necessary to initialise the exception table
- * and interrupt controller. This assumes only one interrupt controller is in
- * use. */
- XExc_mDisableExceptions( XEXC_NON_CRITICAL );
- XExc_Init();
+ /* Perform all library calls necessary to initialise the exception table
+ and interrupt controller. This assumes only one interrupt controller is in
+ use. */
+ XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+ XExc_Init();
- /* The library functions save the context - we then jump to a wrapper to
- * save the stack into the TCB. The wrapper then calls the handler defined
- * above. */
- XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
- XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
- XIntc_Start( &xInterruptController, XIN_REAL_MODE );
+ /* The library functions save the context - we then jump to a wrapper to
+ save the stack into the TCB. The wrapper then calls the handler defined
+ above. */
+ XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
+ XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
+ XIntc_Start( &xInterruptController, XIN_REAL_MODE );
}
/*-----------------------------------------------------------*/
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
- XInterruptHandler pxHandler,
- void * pvCallBackRef )
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
{
- BaseType_t xReturn = pdFAIL;
+BaseType_t xReturn = pdFAIL;
- /* This function is defined here so the scope of xInterruptController can
- * remain within this file. */
+ /* This function is defined here so the scope of xInterruptController can
+ remain within this file. */
- if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
- {
- XIntc_Enable( &xInterruptController, ucInterruptID );
- xReturn = pdPASS;
- }
+ if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
+ {
+ XIntc_Enable( &xInterruptController, ucInterruptID );
+ xReturn = pdPASS;
+ }
- return xReturn;
+ return xReturn;
}
diff --git a/portable/GCC/PPC405_Xilinx/portmacro.h b/portable/GCC/PPC405_Xilinx/portmacro.h
index 298500e..0a53e71 100644
--- a/portable/GCC/PPC405_Xilinx/portmacro.h
+++ b/portable/GCC/PPC405_Xilinx/portmacro.h
@@ -26,13 +26,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include "xexception_l.h"
+#include "xexception_l.h"
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -45,75 +45,74 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* This port uses the critical nesting count from the TCB rather than
- * maintaining a separate value and then saving this value in the task stack. */
- #define portCRITICAL_NESTING_IN_TCB 1
+maintaining a separate value and then saving this value in the task stack. */
+#define portCRITICAL_NESTING_IN_TCB 1
/* Interrupt control macros. */
- #define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL );
- #define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL );
+#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL );
/*-----------------------------------------------------------*/
/* Critical section macros. */
- void vTaskEnterCritical( void );
- void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+void vTaskEnterCritical( void );
+void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
- void vPortYield( void );
- #define portYIELD() asm volatile ( "SC \n\t NOP" )
- #define portYIELD_FROM_ISR() vTaskSwitchContext()
+void vPortYield( void );
+#define portYIELD() asm volatile ( "SC \n\t NOP" )
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "NOP" )
/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
- #define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 )
+#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Port specific interrupt handling functions. */
- void vPortSetupInterruptController( void );
- BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
- XInterruptHandler pxHandler,
- void * pvCallBackRef );
+void vPortSetupInterruptController( void );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/portable/GCC/PPC440_Xilinx/FPU_Macros.h
index 891cd7b..dd8ddee 100644
--- a/portable/GCC/PPC440_Xilinx/FPU_Macros.h
+++ b/portable/GCC/PPC440_Xilinx/FPU_Macros.h
@@ -26,19 +26,20 @@
*/
/* When switching out a task, if the task tag contains a buffer address then
- * save the flop context into the buffer. */
-#define traceTASK_SWITCHED_OUT() \
- if( pxCurrentTCB->pxTaskTag != NULL ) \
- { \
- extern void vPortSaveFPURegisters( void * ); \
- vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
- }
+save the flop context into the buffer. */
+#define traceTASK_SWITCHED_OUT() \
+ if( pxCurrentTCB->pxTaskTag != NULL ) \
+ { \
+ extern void vPortSaveFPURegisters( void * ); \
+ vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
+ }
/* When switching in a task, if the task tag contains a buffer address then
- * load the flop context from the buffer. */
-#define traceTASK_SWITCHED_IN() \
- if( pxCurrentTCB->pxTaskTag != NULL ) \
- { \
- extern void vPortRestoreFPURegisters( void * ); \
- vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
- }
+load the flop context from the buffer. */
+#define traceTASK_SWITCHED_IN() \
+ if( pxCurrentTCB->pxTaskTag != NULL ) \
+ { \
+ extern void vPortRestoreFPURegisters( void * ); \
+ vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
+ }
+
diff --git a/portable/GCC/PPC440_Xilinx/port.c b/portable/GCC/PPC440_Xilinx/port.c
index 46660e0..2b104a5 100644
--- a/portable/GCC/PPC440_Xilinx/port.c
+++ b/portable/GCC/PPC440_Xilinx/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PPC440 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PPC440 port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
@@ -42,19 +42,19 @@
/*-----------------------------------------------------------*/
/* Definitions to set the initial MSR of each task. */
-#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
-#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
-#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
+#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
+#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
+#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
#if configUSE_FPU == 1
- #define portAPU_PRESENT ( 1UL << 25UL )
- #define portFCM_FPU_PRESENT ( 1UL << 13UL )
+ #define portAPU_PRESENT ( 1UL << 25UL )
+ #define portFCM_FPU_PRESENT ( 1UL << 13UL )
#else
- #define portAPU_PRESENT ( 0UL )
- #define portFCM_FPU_PRESENT ( 0UL )
+ #define portAPU_PRESENT ( 0UL )
+ #define portFCM_FPU_PRESENT ( 0UL )
#endif
-#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
+#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
extern const unsigned _SDA_BASE_;
@@ -96,72 +96,68 @@
*
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Place a known value at the bottom of the stack for debugging. */
- *pxTopOfStack = 0xDEADBEEF;
- pxTopOfStack--;
+ /* Place a known value at the bottom of the stack for debugging. */
+ *pxTopOfStack = 0xDEADBEEF;
+ pxTopOfStack--;
- /* EABI stack frame. */
- pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
+ /* EABI stack frame. */
+ pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
- /* Parameters in R13. */
- *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
- pxTopOfStack -= 10;
+ /* Parameters in R13. */
+ *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
+ pxTopOfStack -= 10;
- /* Parameters in R3. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
+ /* Parameters in R3. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
- /* Parameters in R2. */
- *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
- pxTopOfStack--;
+ /* Parameters in R2. */
+ *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
+ pxTopOfStack--;
- /* R1 is the stack pointer so is omitted. */
+ /* R1 is the stack pointer so is omitted. */
- *pxTopOfStack = 0x10000001UL; /* R0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* USPRG0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* CR. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* XER. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* CTR. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_MSR; /* SRR1. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* Next LR. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* Backchain. */
+ *pxTopOfStack = 0x10000001UL;; /* R0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* USPRG0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* CR. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* XER. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* CTR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_MSR;/* SRR1. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL;/* Backchain. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- prvSetupTimerInterrupt();
- XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
- vPortStartFirstTask();
+ prvSetupTimerInterrupt();
+ XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
+ vPortStartFirstTask();
- /* Should not get here as the tasks are now running! */
- return pdFALSE;
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented. */
- for( ; ; )
- {
- }
+ /* Not implemented. */
+ for( ;; );
}
/*-----------------------------------------------------------*/
@@ -170,97 +166,95 @@
*/
static void prvSetupTimerInterrupt( void )
{
- const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
+const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
- XTime_DECClearInterrupt();
- XTime_FITClearInterrupt();
- XTime_WDTClearInterrupt();
- XTime_WDTDisableInterrupt();
- XTime_FITDisableInterrupt();
+ XTime_DECClearInterrupt();
+ XTime_FITClearInterrupt();
+ XTime_WDTClearInterrupt();
+ XTime_WDTDisableInterrupt();
+ XTime_FITDisableInterrupt();
- XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
+ XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
- XTime_DECEnableAutoReload();
- XTime_DECSetInterval( ulInterval );
- XTime_DECEnableInterrupt();
+ XTime_DECEnableAutoReload();
+ XTime_DECSetInterval( ulInterval );
+ XTime_DECEnableInterrupt();
}
/*-----------------------------------------------------------*/
-void vPortISRHandler( void * pvNullDoNotUse )
+void vPortISRHandler( void *pvNullDoNotUse )
{
- uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
- BaseType_t xInterruptNumber;
- XIntc_Config * pxInterruptController;
- XIntc_VectorTableEntry * pxTable;
+uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
+BaseType_t xInterruptNumber;
+XIntc_Config *pxInterruptController;
+XIntc_VectorTableEntry *pxTable;
- /* Just to remove compiler warning. */
- ( void ) pvNullDoNotUse;
+ /* Just to remove compiler warning. */
+ ( void ) pvNullDoNotUse;
- /* Get the configuration by using the device ID - in this case it is
- * assumed that only one interrupt controller is being used. */
- pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
+ /* Get the configuration by using the device ID - in this case it is
+ assumed that only one interrupt controller is being used. */
+ pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
- /* Which interrupts are pending? */
- ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
+ /* Which interrupts are pending? */
+ ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
- for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
- {
- if( ulInterruptStatus & 0x01UL )
- {
- /* Clear the pending interrupt. */
- XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
+ for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
+ {
+ if( ulInterruptStatus & 0x01UL )
+ {
+ /* Clear the pending interrupt. */
+ XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
- /* Call the registered handler. */
- pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
- pxTable->Handler( pxTable->CallBackRef );
- }
+ /* Call the registered handler. */
+ pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
+ pxTable->Handler( pxTable->CallBackRef );
+ }
- /* Check the next interrupt. */
- ulInterruptMask <<= 0x01UL;
- ulInterruptStatus >>= 0x01UL;
+ /* Check the next interrupt. */
+ ulInterruptMask <<= 0x01UL;
+ ulInterruptStatus >>= 0x01UL;
- /* Have we serviced all interrupts? */
- if( ulInterruptStatus == 0UL )
- {
- break;
- }
- }
+ /* Have we serviced all interrupts? */
+ if( ulInterruptStatus == 0UL )
+ {
+ break;
+ }
+ }
}
/*-----------------------------------------------------------*/
void vPortSetupInterruptController( void )
{
- extern void vPortISRWrapper( void );
+extern void vPortISRWrapper( void );
- /* Perform all library calls necessary to initialise the exception table
- * and interrupt controller. This assumes only one interrupt controller is in
- * use. */
- XExc_mDisableExceptions( XEXC_NON_CRITICAL );
- XExc_Init();
+ /* Perform all library calls necessary to initialise the exception table
+ and interrupt controller. This assumes only one interrupt controller is in
+ use. */
+ XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+ XExc_Init();
- /* The library functions save the context - we then jump to a wrapper to
- * save the stack into the TCB. The wrapper then calls the handler defined
- * above. */
- XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
- XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
- XIntc_Start( &xInterruptController, XIN_REAL_MODE );
+ /* The library functions save the context - we then jump to a wrapper to
+ save the stack into the TCB. The wrapper then calls the handler defined
+ above. */
+ XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
+ XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
+ XIntc_Start( &xInterruptController, XIN_REAL_MODE );
}
/*-----------------------------------------------------------*/
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
- XInterruptHandler pxHandler,
- void * pvCallBackRef )
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
{
- BaseType_t xReturn = pdFAIL;
+BaseType_t xReturn = pdFAIL;
- /* This function is defined here so the scope of xInterruptController can
- * remain within this file. */
+ /* This function is defined here so the scope of xInterruptController can
+ remain within this file. */
- if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
- {
- XIntc_Enable( &xInterruptController, ucInterruptID );
- xReturn = pdPASS;
- }
+ if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
+ {
+ XIntc_Enable( &xInterruptController, ucInterruptID );
+ xReturn = pdPASS;
+ }
- return xReturn;
+ return xReturn;
}
diff --git a/portable/GCC/PPC440_Xilinx/portmacro.h b/portable/GCC/PPC440_Xilinx/portmacro.h
index 298500e..0a53e71 100644
--- a/portable/GCC/PPC440_Xilinx/portmacro.h
+++ b/portable/GCC/PPC440_Xilinx/portmacro.h
@@ -26,13 +26,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include "xexception_l.h"
+#include "xexception_l.h"
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -45,75 +45,74 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* This port uses the critical nesting count from the TCB rather than
- * maintaining a separate value and then saving this value in the task stack. */
- #define portCRITICAL_NESTING_IN_TCB 1
+maintaining a separate value and then saving this value in the task stack. */
+#define portCRITICAL_NESTING_IN_TCB 1
/* Interrupt control macros. */
- #define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL );
- #define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL );
+#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL );
/*-----------------------------------------------------------*/
/* Critical section macros. */
- void vTaskEnterCritical( void );
- void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+void vTaskEnterCritical( void );
+void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
- void vPortYield( void );
- #define portYIELD() asm volatile ( "SC \n\t NOP" )
- #define portYIELD_FROM_ISR() vTaskSwitchContext()
+void vPortYield( void );
+#define portYIELD() asm volatile ( "SC \n\t NOP" )
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "NOP" )
/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
- #define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 )
+#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Port specific interrupt handling functions. */
- void vPortSetupInterruptController( void );
- BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
- XInterruptHandler pxHandler,
- void * pvCallBackRef );
+void vPortSetupInterruptController( void );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
index d882d60..8cd6cdb 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -7,8 +7,8 @@
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and t
- *
- * o permit persons to whom the Software is furnished to do so,
+
+ o permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -59,51 +59,51 @@
#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
#define __FREERTOS_RISC_V_EXTENSIONS_H__
-#define portasmHAS_MTIME 0
+#define portasmHAS_MTIME 0
/* Constants to define the additional registers found on the Pulpino RI5KY. */
-#define lpstart0 0x7b0
-#define lpend0 0x7b1
-#define lpcount0 0x7b2
-#define lpstart1 0x7b4
-#define lpend1 0x7b5
-#define lpcount1 0x7b6
+#define lpstart0 0x7b0
+#define lpend0 0x7b1
+#define lpcount0 0x7b2
+#define lpstart1 0x7b4
+#define lpend1 0x7b5
+#define lpcount1 0x7b6
/* Six additional registers to save and restore, as per the #defines above. */
-#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
+#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
/* Save additional registers found on the Pulpino. */
.macro portasmSAVE_ADDITIONAL_REGISTERS
-addi sp, sp, -( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Make room for the additional registers. */
-csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */
-csrr t1, lpend0
-csrr t2, lpcount0
-csrr t3, lpstart1
-csrr t4, lpend1
-csrr t5, lpcount1
-sw t0, 1 * portWORD_SIZE( sp )
-sw t1, 2 * portWORD_SIZE( sp )
-sw t2, 3 * portWORD_SIZE( sp )
-sw t3, 4 * portWORD_SIZE( sp )
-sw t4, 5 * portWORD_SIZE( sp )
-sw t5, 6 * portWORD_SIZE( sp )
- .endm
+ addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
+ csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */
+ csrr t1, lpend0
+ csrr t2, lpcount0
+ csrr t3, lpstart1
+ csrr t4, lpend1
+ csrr t5, lpcount1
+ sw t0, 1 * portWORD_SIZE( sp )
+ sw t1, 2 * portWORD_SIZE( sp )
+ sw t2, 3 * portWORD_SIZE( sp )
+ sw t3, 4 * portWORD_SIZE( sp )
+ sw t4, 5 * portWORD_SIZE( sp )
+ sw t5, 6 * portWORD_SIZE( sp )
+ .endm
/* Restore the additional registers found on the Pulpino. */
- .macro portasmRESTORE_ADDITIONAL_REGISTERS
-lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
-lw t1, 2 * portWORD_SIZE( sp )
-lw t2, 3 * portWORD_SIZE( sp )
-lw t3, 4 * portWORD_SIZE( sp )
-lw t4, 5 * portWORD_SIZE( sp )
-lw t5, 6 * portWORD_SIZE( sp )
-csrw lpstart0, t0
-csrw lpend0, t1
-csrw lpcount0, t2
-csrw lpstart1, t3
-csrw lpend1, t4
-csrw lpcount1, t5
-addi sp, sp, ( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Remove space added for additional registers. */
- .endm
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+ lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
+ lw t1, 2 * portWORD_SIZE( sp )
+ lw t2, 3 * portWORD_SIZE( sp )
+ lw t3, 4 * portWORD_SIZE( sp )
+ lw t4, 5 * portWORD_SIZE( sp )
+ lw t5, 6 * portWORD_SIZE( sp )
+ csrw lpstart0, t0
+ csrw lpend0, t1
+ csrw lpcount0, t2
+ csrw lpstart1, t3
+ csrw lpend1, t4
+ csrw lpcount1, t5
+ addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
+ .endm
#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
index babff6a..be1908a 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -53,16 +53,16 @@
#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
#define __FREERTOS_RISC_V_EXTENSIONS_H__
-#define portasmHAS_SIFIVE_CLINT 1
-#define portasmHAS_MTIME 1
-#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+#define portasmHAS_SIFIVE_CLINT 1
+#define portasmHAS_MTIME 1
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
.macro portasmSAVE_ADDITIONAL_REGISTERS
-/* No additional registers to save, so this macro does nothing. */
- .endm
+ /* No additional registers to save, so this macro does nothing. */
+ .endm
- .macro portasmRESTORE_ADDITIONAL_REGISTERS
-/* No additional registers to restore, so this macro does nothing. */
- .endm
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+ /* No additional registers to restore, so this macro does nothing. */
+ .endm
#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/portable/GCC/RISC-V/port.c b/portable/GCC/RISC-V/port.c
index 799ad1d..9525ff6 100644
--- a/portable/GCC/RISC-V/port.c
+++ b/portable/GCC/RISC-V/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RISC-V RV32 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RISC-V RV32 port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -38,44 +38,44 @@
#include "string.h"
#ifdef configCLINT_BASE_ADDRESS
- #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
+ #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef configMTIME_BASE_ADDRESS
- #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
+ #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef configMTIMECMP_BASE_ADDRESS
- #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
+ #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
- * to use a statically allocated array as the interrupt stack. Alternative leave
- * configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
- * linker variable names __freertos_irq_stack_top has the same value as the top
- * of the stack used by main. Using the linker script method will repurpose the
- * stack that was used by main before the scheduler was started for use as the
- * interrupt stack after the scheduler has started. */
+to use a statically allocated array as the interrupt stack. Alternative leave
+configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
+linker variable names __freertos_irq_stack_top has the same value as the top
+of the stack used by main. Using the linker script method will repurpose the
+stack that was used by main before the scheduler was started for use as the
+interrupt stack after the scheduler has started. */
#ifdef configISR_STACK_SIZE_WORDS
- static __attribute__( ( aligned( 16 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
- const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
+ static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
+ const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
-/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
- * the task stacks, and so will legitimately appear in many positions within
- * the ISR stack. */
- #define portISR_STACK_FILL_BYTE 0xee
+ /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+ the task stacks, and so will legitimately appear in many positions within
+ the ISR stack. */
+ #define portISR_STACK_FILL_BYTE 0xee
#else
- extern const uint32_t __freertos_irq_stack_top[];
- const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
+ extern const uint32_t __freertos_irq_stack_top[];
+ const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
#endif
/*
@@ -83,130 +83,130 @@
* file is weak to allow application writers to change the timer used to
* generate the tick interrupt.
*/
-void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
+void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
/*-----------------------------------------------------------*/
/* Used to program the machine timer compare register. */
uint64_t ullNextTime = 0ULL;
-const uint64_t * pullNextTime = &ullNextTime;
+const uint64_t *pullNextTime = &ullNextTime;
const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
volatile uint64_t * pullMachineTimerCompareRegister = NULL;
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
- * stack checking. A problem in the ISR stack will trigger an assert, not call the
- * stack overflow hook function (because the stack overflow hook is specific to a
- * task stack, not the ISR stack). */
+stack checking. A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
- #warning This path not tested, or even compiled yet.
+ #warning This path not tested, or even compiled yet.
- static const uint8_t ucExpectedStackBytes[] =
- {
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
- }; \
+ static const uint8_t ucExpectedStackBytes[] = {
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
- #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
- /* Define the function away. */
- #define portCHECK_ISR_STACK()
+ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+ /* Define the function away. */
+ #define portCHECK_ISR_STACK()
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
/*-----------------------------------------------------------*/
-#if ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
+#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
- void vPortSetupTimerInterrupt( void )
- {
- uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
- volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */
- volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
- volatile uint32_t ulHartId;
+ void vPortSetupTimerInterrupt( void )
+ {
+ uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+ volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */
+ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
+ volatile uint32_t ulHartId;
- __asm volatile ( "csrr %0, mhartid" : "=r" ( ulHartId ) );
+ __asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
+ pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
- pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
+ do
+ {
+ ulCurrentTimeHigh = *pulTimeHigh;
+ ulCurrentTimeLow = *pulTimeLow;
+ } while( ulCurrentTimeHigh != *pulTimeHigh );
- do
- {
- ulCurrentTimeHigh = *pulTimeHigh;
- ulCurrentTimeLow = *pulTimeLow;
- } while( ulCurrentTimeHigh != *pulTimeHigh );
+ ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
+ ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
+ ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+ *pullMachineTimerCompareRegister = ullNextTime;
- ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
- ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
- ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
- ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
- *pullMachineTimerCompareRegister = ullNextTime;
-
- /* Prepare the time to use after the next tick interrupt. */
- ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
- }
+ /* Prepare the time to use after the next tick interrupt. */
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+ }
#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void xPortStartFirstTask( void );
+extern void xPortStartFirstTask( void );
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t mtvec = 0;
+ #if( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t mtvec = 0;
- /* Check the least significant two bits of mtvec are 00 - indicating
- * single vector mode. */
- __asm volatile ( "csrr %0, mtvec" : "=r" ( mtvec ) );
- configASSERT( ( mtvec & 0x03UL ) == 0 );
+ /* Check the least significant two bits of mtvec are 00 - indicating
+ single vector mode. */
+ __asm volatile( "csrr %0, mtvec" : "=r"( mtvec ) );
+ configASSERT( ( mtvec & 0x03UL ) == 0 );
- /* Check alignment of the interrupt stack - which is the same as the
- * stack that was being used by main() prior to the scheduler being
- * started. */
- configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
+ /* Check alignment of the interrupt stack - which is the same as the
+ stack that was being used by main() prior to the scheduler being
+ started. */
+ configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
- #ifdef configISR_STACK_SIZE_WORDS
- {
- memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
- }
- #endif /* configISR_STACK_SIZE_WORDS */
- }
- #endif /* configASSERT_DEFINED */
+ #ifdef configISR_STACK_SIZE_WORDS
+ {
+ memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+ }
+ #endif /* configISR_STACK_SIZE_WORDS */
+ }
+ #endif /* configASSERT_DEFINED */
- /* If there is a CLINT then it is ok to use the default implementation
- * in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
- * configure whichever clock is to be used to generate the tick interrupt. */
- vPortSetupTimerInterrupt();
+ /* If there is a CLINT then it is ok to use the default implementation
+ in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
+ configure whichever clock is to be used to generate the tick interrupt. */
+ vPortSetupTimerInterrupt();
- #if ( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
- {
- /* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
- * for external interrupt. _RB_ What happens here when mtime is not present as
- * with pulpino? */
- __asm volatile ( "csrs mie, %0" ::"r" ( 0x880 ) );
- }
- #else
- {
- /* Enable external interrupts. */
- __asm volatile ( "csrs mie, %0" ::"r" ( 0x800 ) );
- }
- #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
+ #if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
+ {
+ /* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
+ for external interrupt. _RB_ What happens here when mtime is not present as
+ with pulpino? */
+ __asm volatile( "csrs mie, %0" :: "r"(0x880) );
+ }
+ #else
+ {
+ /* Enable external interrupts. */
+ __asm volatile( "csrs mie, %0" :: "r"(0x800) );
+ }
+ #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
- xPortStartFirstTask();
+ xPortStartFirstTask();
- /* Should not get here as after calling xPortStartFirstTask() only tasks
- * should be executing. */
- return pdFAIL;
+ /* Should not get here as after calling xPortStartFirstTask() only tasks
+ should be executing. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented. */
- for( ; ; )
- {
- }
+ /* Not implemented. */
+ for( ;; );
}
+
+
+
+
+
diff --git a/portable/GCC/RISC-V/portmacro.h b/portable/GCC/RISC-V/portmacro.h
index 968bc42..0ec8496 100644
--- a/portable/GCC/RISC-V/portmacro.h
+++ b/portable/GCC/RISC-V/portmacro.h
@@ -27,11 +27,11 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,144 +44,143 @@
*/
/* Type definitions. */
- #if __riscv_xlen == 64
- #define portSTACK_TYPE uint64_t
- #define portBASE_TYPE int64_t
- #define portUBASE_TYPE uint64_t
- #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
- #define portPOINTER_SIZE_TYPE uint64_t
- #elif __riscv_xlen == 32
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE int32_t
- #define portUBASE_TYPE uint32_t
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #else /* if __riscv_xlen == 64 */
- #error Assembler did not define __riscv_xlen
- #endif /* if __riscv_xlen == 64 */
+#if __riscv_xlen == 64
+ #define portSTACK_TYPE uint64_t
+ #define portBASE_TYPE int64_t
+ #define portUBASE_TYPE uint64_t
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
+ #define portPOINTER_SIZE_TYPE uint64_t
+#elif __riscv_xlen == 32
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE int32_t
+ #define portUBASE_TYPE uint32_t
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#else
+ #error Assembler did not define __riscv_xlen
+#endif
- typedef portSTACK_TYPE StackType_t;
- typedef portBASE_TYPE BaseType_t;
- typedef portUBASE_TYPE UBaseType_t;
- typedef portUBASE_TYPE TickType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef portUBASE_TYPE UBaseType_t;
+typedef portUBASE_TYPE TickType_t;
/* Legacy type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #ifdef __riscv64
- #error This is the RV32 port that has not yet been adapted for 64.
- #define portBYTE_ALIGNMENT 16
- #else
- #define portBYTE_ALIGNMENT 16
- #endif
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#ifdef __riscv64
+ #error This is the RV32 port that has not yet been adapted for 64.
+ #define portBYTE_ALIGNMENT 16
+#else
+ #define portBYTE_ALIGNMENT 16
+#endif
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- extern void vTaskSwitchContext( void );
- #define portYIELD() __asm volatile ( "ecall" );
- #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+extern void vTaskSwitchContext( void );
+#define portYIELD() __asm volatile( "ecall" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- #define portCRITICAL_NESTING_IN_TCB 1
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB 1
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() 0
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
- #define portDISABLE_INTERRUPTS() __asm volatile ( "csrc mstatus, 8" )
- #define portENABLE_INTERRUPTS() __asm volatile ( "csrs mstatus, 8" )
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" )
+#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" )
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo files
- * (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+not necessary for to use this port. They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
- #define portNOP() __asm volatile ( " nop " )
+#define portNOP() __asm volatile ( " nop " )
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
- * configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
- * backward compatibility derive the newer definitions from the old if the old
- * definition is found. */
- #if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
-
-/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
- * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
- * addresses to 0. */
- #define configMTIME_BASE_ADDRESS ( 0 )
- #define configMTIMECMP_BASE_ADDRESS ( 0 )
- #elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
-
-/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
- * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
- * from the CLINT address. */
- #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
- #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
- #elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
- #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
- #endif /* if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) */
+configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
+backward compatibility derive the newer definitions from the old if the old
+definition is found. */
+#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
+ /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
+ there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
+ addresses to 0. */
+ #define configMTIME_BASE_ADDRESS ( 0 )
+ #define configMTIMECMP_BASE_ADDRESS ( 0 )
+#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
+ /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
+ the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
+ from the CLINT address. */
+ #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
+ #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
+#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
+ #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
+#endif
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/RL78/isr_support.h b/portable/GCC/RL78/isr_support.h
index e804c3f..3687fdc 100644
--- a/portable/GCC/RL78/isr_support.h
+++ b/portable/GCC/RL78/isr_support.h
@@ -26,8 +26,8 @@
*/
/* Variables used by scheduler */
-.extern _pxCurrentTCB
- .extern _usCriticalNesting
+ .extern _pxCurrentTCB
+ .extern _usCriticalNesting
/*
* portSAVE_CONTEXT MACRO
@@ -35,47 +35,47 @@
* memory mode) registers the usCriticalNesting Value and the Stack Pointer
* of the active Task onto the task stack
*/
- .macro portSAVE_CONTEXT
+ .macro portSAVE_CONTEXT
-SEL RB0
+ SEL RB0
-/* Save AX Register to stack. */
-PUSH AX
-PUSH HL
-/* Save CS register. */
-MOV A, CS
-XCH A, X
-/* Save ES register. */
-MOV A, ES
-PUSH AX
-/* Save the remaining general purpose registers from bank 0. */
-PUSH DE
-PUSH BC
-/* Save the other register banks - only necessary in the GCC port. */
-SEL RB1
-PUSH AX
-PUSH BC
-PUSH DE
-PUSH HL
-SEL RB2
-PUSH AX
-PUSH BC
-PUSH DE
-PUSH HL
-/* Registers in bank 3 are for ISR use only so don't need saving. */
-SEL RB0
-/* Save the usCriticalNesting value. */
-MOVW AX, !_usCriticalNesting
-PUSH AX
-/* Save the Stack pointer. */
-MOVW AX, !_pxCurrentTCB
-MOVW HL, AX
-MOVW AX, SP
-MOVW[ HL ], AX
-/* Switch stack pointers. */
-movw sp, # _stack /* Set stack pointer */
+ /* Save AX Register to stack. */
+ PUSH AX
+ PUSH HL
+ /* Save CS register. */
+ MOV A, CS
+ XCH A, X
+ /* Save ES register. */
+ MOV A, ES
+ PUSH AX
+ /* Save the remaining general purpose registers from bank 0. */
+ PUSH DE
+ PUSH BC
+ /* Save the other register banks - only necessary in the GCC port. */
+ SEL RB1
+ PUSH AX
+ PUSH BC
+ PUSH DE
+ PUSH HL
+ SEL RB2
+ PUSH AX
+ PUSH BC
+ PUSH DE
+ PUSH HL
+ /* Registers in bank 3 are for ISR use only so don't need saving. */
+ SEL RB0
+ /* Save the usCriticalNesting value. */
+ MOVW AX, !_usCriticalNesting
+ PUSH AX
+ /* Save the Stack pointer. */
+ MOVW AX, !_pxCurrentTCB
+ MOVW HL, AX
+ MOVW AX, SP
+ MOVW [HL], AX
+ /* Switch stack pointers. */
+ movw sp,#_stack /* Set stack pointer */
- .endm
+ .endm
/*
@@ -84,43 +84,43 @@
* general purpose registers and the CS and ES (only in far memory mode)
* of the selected task from the task stack
*/
- .macro portRESTORE_CONTEXT MACRO
-SEL RB0
-/* Restore the Stack pointer. */
-MOVW AX, !_pxCurrentTCB
-MOVW HL, AX
-MOVW AX, [ HL ]
-MOVW SP, AX
-/* Restore usCriticalNesting value. */
-POP AX
-MOVW !_usCriticalNesting, AX
+.macro portRESTORE_CONTEXT MACRO
+ SEL RB0
+ /* Restore the Stack pointer. */
+ MOVW AX, !_pxCurrentTCB
+ MOVW HL, AX
+ MOVW AX, [HL]
+ MOVW SP, AX
+ /* Restore usCriticalNesting value. */
+ POP AX
+ MOVW !_usCriticalNesting, AX
+ /* Restore the alternative register banks - only necessary in the GCC
+ port. Register bank 3 is dedicated for interrupts use so is not saved or
+ restored. */
+ SEL RB2
+ POP HL
+ POP DE
+ POP BC
+ POP AX
+ SEL RB1
+ POP HL
+ POP DE
+ POP BC
+ POP AX
+ SEL RB0
+ /* Restore the necessary general purpose registers. */
+ POP BC
+ POP DE
+ /* Restore the ES register. */
+ POP AX
+ MOV ES, A
+ /* Restore the CS register. */
+ XCH A, X
+ MOV CS, A
+ /* Restore general purpose register HL. */
+ POP HL
+ /* Restore AX. */
+ POP AX
-/* Restore the alternative register banks - only necessary in the GCC
- * port. Register bank 3 is dedicated for interrupts use so is not saved or
- * restored. */
-SEL RB2
-POP HL
-POP DE
-POP BC
-POP AX
-SEL RB1
-POP HL
-POP DE
-POP BC
-POP AX
-SEL RB0
-/* Restore the necessary general purpose registers. */
-POP BC
-POP DE
-/* Restore the ES register. */
-POP AX
-MOV ES, A
-/* Restore the CS register. */
-XCH A, X
-MOV CS, A
-/* Restore general purpose register HL. */
-POP HL
-/* Restore AX. */
-POP AX
+ .endm
- .endm
diff --git a/portable/GCC/RL78/port.c b/portable/GCC/RL78/port.c
index 82b51be..dc1fc56 100644
--- a/portable/GCC/RL78/port.c
+++ b/portable/GCC/RL78/port.c
@@ -30,8 +30,8 @@
#include "task.h"
/* The critical nesting value is initialised to a non zero value to ensure
- * interrupts don't accidentally become enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
+interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
/* Initial PSW value allocated to a newly created task.
* 11000110
@@ -44,16 +44,16 @@
* |--------------------- Zero Flag set
* ---------------------- Global Interrupt Flag set (enabled)
*/
-#define portPSW ( 0xc6UL )
+#define portPSW ( 0xc6UL )
/* Each task maintains a count of the critical section nesting depth. Each time
- * a critical section is entered the count is incremented. Each time a critical
- * section is exited the count is decremented - with interrupts only being
- * re-enabled if the count is zero.
- *
- * usCriticalNesting will get set to zero when the scheduler starts, but must
- * not be initialised to zero as that could cause problems during the startup
- * sequence. */
+a critical section is entered the count is incremented. Each time a critical
+section is exited the count is decremented - with interrupts only being
+re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as that could cause problems during the startup
+sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@@ -61,7 +61,7 @@
/*
* Sets up the periodic ISR used for the RTOS tick.
*/
-__attribute__( ( weak ) ) void vApplicationSetupTimerInterrupt( void );
+__attribute__((weak)) void vApplicationSetupTimerInterrupt( void );
/*
* Starts the scheduler by loading the context of the first task to run.
@@ -77,136 +77,135 @@
*
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint32_t * pulLocal;
+uint32_t *pulLocal;
- /* Stack type and pointers to the stack type are both 2 bytes. */
+ /* Stack type and pointers to the stack type are both 2 bytes. */
- /* Parameters are passed in on the stack, and written using a 32bit value
- * hence a space is left for the second two bytes. */
- pxTopOfStack--;
+ /* Parameters are passed in on the stack, and written using a 32bit value
+ hence a space is left for the second two bytes. */
+ pxTopOfStack--;
- /* Write in the parameter value. */
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( StackType_t ) pvParameters;
- pxTopOfStack--;
+ /* Write in the parameter value. */
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
- /* The return address, leaving space for the first two bytes of the
- * 32-bit value. */
- pxTopOfStack--;
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( uint32_t ) 0;
- pxTopOfStack--;
+ /* The return address, leaving space for the first two bytes of the
+ 32-bit value. */
+ pxTopOfStack--;
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( uint32_t ) 0;
+ pxTopOfStack--;
- /* The start address / PSW value is also written in as a 32bit value,
- * so leave a space for the second two bytes. */
- pxTopOfStack--;
+ /* The start address / PSW value is also written in as a 32bit value,
+ so leave a space for the second two bytes. */
+ pxTopOfStack--;
- /* Task function start address combined with the PSW. */
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
- pxTopOfStack--;
+ /* Task function start address combined with the PSW. */
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+ pxTopOfStack--;
- /* An initial value for the AX register. */
- *pxTopOfStack = ( StackType_t ) 0x1111;
- pxTopOfStack--;
+ /* An initial value for the AX register. */
+ *pxTopOfStack = ( StackType_t ) 0x1111;
+ pxTopOfStack--;
- /* An initial value for the HL register. */
- *pxTopOfStack = ( StackType_t ) 0x2222;
- pxTopOfStack--;
+ /* An initial value for the HL register. */
+ *pxTopOfStack = ( StackType_t ) 0x2222;
+ pxTopOfStack--;
- /* CS and ES registers. */
- *pxTopOfStack = ( StackType_t ) 0x0F00;
- pxTopOfStack--;
+ /* CS and ES registers. */
+ *pxTopOfStack = ( StackType_t ) 0x0F00;
+ pxTopOfStack--;
- /* The remaining general purpose registers bank 0 (DE and BC) and the other
- * two register banks...register bank 3 is dedicated for use by interrupts so
- * is not saved as part of the task context. */
- pxTopOfStack -= 10;
+ /* The remaining general purpose registers bank 0 (DE and BC) and the other
+ two register banks...register bank 3 is dedicated for use by interrupts so
+ is not saved as part of the task context. */
+ pxTopOfStack -= 10;
- /* Finally the critical section nesting count is set to zero when the task
- * first starts. */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+ /* Finally the critical section nesting count is set to zero when the task
+ first starts. */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
- /* Return a pointer to the top of the stack that has beene generated so it
- * can be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* Return a pointer to the top of the stack that has beene generated so it
+ can be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- * this function is called. */
- vApplicationSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called. */
+ vApplicationSetupTimerInterrupt();
- /* Restore the context of the first task that is going to run. */
- vPortStartFirstTask();
+ /* Restore the context of the first task that is going to run. */
+ vPortStartFirstTask();
- /* Execution should not reach here as the tasks are now running! */
- return pdTRUE;
+ /* Execution should not reach here as the tasks are now running! */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the RL78 port will get stopped. */
+ /* It is unlikely that the RL78 port will get stopped. */
}
/*-----------------------------------------------------------*/
-__attribute__( ( weak ) ) void vApplicationSetupTimerInterrupt( void )
+__attribute__((weak)) void vApplicationSetupTimerInterrupt( void )
{
- const uint16_t usClockHz = 15000UL; /* Internal clock. */
- const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
+const uint16_t usClockHz = 15000UL; /* Internal clock. */
+const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
- /* Use the internal 15K clock. */
- OSMC = ( unsigned char ) 0x16;
+ /* Use the internal 15K clock. */
+ OSMC = ( unsigned char ) 0x16;
- #ifdef RTCEN
- {
- /* Supply the interval timer clock. */
- RTCEN = ( unsigned char ) 1U;
+ #ifdef RTCEN
+ {
+ /* Supply the interval timer clock. */
+ RTCEN = ( unsigned char ) 1U;
- /* Disable INTIT interrupt. */
- ITMK = ( unsigned char ) 1;
+ /* Disable INTIT interrupt. */
+ ITMK = ( unsigned char ) 1;
- /* Disable ITMC operation. */
- ITMC = ( unsigned char ) 0x0000;
+ /* Disable ITMC operation. */
+ ITMC = ( unsigned char ) 0x0000;
- /* Clear INIT interrupt. */
- ITIF = ( unsigned char ) 0;
+ /* Clear INIT interrupt. */
+ ITIF = ( unsigned char ) 0;
- /* Set interval and enable interrupt operation. */
- ITMC = usCompareMatch | 0x8000U;
+ /* Set interval and enable interrupt operation. */
+ ITMC = usCompareMatch | 0x8000U;
- /* Enable INTIT interrupt. */
- ITMK = ( unsigned char ) 0;
- }
- #endif /* ifdef RTCEN */
+ /* Enable INTIT interrupt. */
+ ITMK = ( unsigned char ) 0;
+ }
+ #endif
- #ifdef TMKAEN
- {
- /* Supply the interval timer clock. */
- TMKAEN = ( unsigned char ) 1U;
+ #ifdef TMKAEN
+ {
+ /* Supply the interval timer clock. */
+ TMKAEN = ( unsigned char ) 1U;
- /* Disable INTIT interrupt. */
- TMKAMK = ( unsigned char ) 1;
+ /* Disable INTIT interrupt. */
+ TMKAMK = ( unsigned char ) 1;
- /* Disable ITMC operation. */
- ITMC = ( unsigned char ) 0x0000;
+ /* Disable ITMC operation. */
+ ITMC = ( unsigned char ) 0x0000;
- /* Clear INIT interrupt. */
- TMKAIF = ( unsigned char ) 0;
+ /* Clear INIT interrupt. */
+ TMKAIF = ( unsigned char ) 0;
- /* Set interval and enable interrupt operation. */
- ITMC = usCompareMatch | 0x8000U;
+ /* Set interval and enable interrupt operation. */
+ ITMC = usCompareMatch | 0x8000U;
- /* Enable INTIT interrupt. */
- TMKAMK = ( unsigned char ) 0;
- }
- #endif /* ifdef TMKAEN */
+ /* Enable INTIT interrupt. */
+ TMKAMK = ( unsigned char ) 0;
+ }
+ #endif
}
/*-----------------------------------------------------------*/
+
diff --git a/portable/GCC/RL78/portmacro.h b/portable/GCC/RL78/portmacro.h
index 4c59588..da2ce53 100644
--- a/portable/GCC/RL78/portmacro.h
+++ b/portable/GCC/RL78/portmacro.h
@@ -40,81 +40,82 @@
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint16_t
-#define portBASE_TYPE short
-#define portPOINTER_SIZE_TYPE uint16_t
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
+#define portPOINTER_SIZE_TYPE uint16_t
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" )
-#define portENABLE_INTERRUPTS() __asm volatile ( "EI" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" )
+#define portENABLE_INTERRUPTS() __asm volatile ( "EI" )
/*-----------------------------------------------------------*/
/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned short ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned short ) 0 )
-#define portENTER_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
-#define portEXIT_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
-#define portYIELD() __asm volatile ( "BRK" )
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
-#define portNOP() __asm volatile ( "NOP" )
+#define portYIELD() __asm volatile ( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+#define portNOP() __asm volatile ( "NOP" )
/*-----------------------------------------------------------*/
/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT 2
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/RX100/port.c b/portable/GCC/RX100/port.c
index 1c6d16c..a77efbc 100644
--- a/portable/GCC/RX100/port.c
+++ b/portable/GCC/RX100/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the SH2A port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
/* Standard C includes. */
#include "limits.h"
@@ -45,36 +45,36 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
/* The peripheral clock is divided by this value before being supplying the
- * CMT. */
+CMT. */
#if ( configUSE_TICKLESS_IDLE == 0 )
- /* If tickless idle is not used then the divisor can be fixed. */
- #define portCLOCK_DIVISOR 8UL
+ /* If tickless idle is not used then the divisor can be fixed. */
+ #define portCLOCK_DIVISOR 8UL
#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
- #define portCLOCK_DIVISOR 512UL
+ #define portCLOCK_DIVISOR 512UL
#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
- #define portCLOCK_DIVISOR 128UL
+ #define portCLOCK_DIVISOR 128UL
#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
- #define portCLOCK_DIVISOR 32UL
+ #define portCLOCK_DIVISOR 32UL
#else
- #define portCLOCK_DIVISOR 8UL
+ #define portCLOCK_DIVISOR 8UL
#endif
/* These macros allow a critical section to be added around the call to
- * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
- * priority - ie a known priority. Therefore these local macros are a slight
- * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
- * which would require the old IPL to be read first and stored in a local variable. */
-#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0"::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority. Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
/* Keys required to lock and unlock access to certain system registers
- * respectively. */
-#define portUNLOCK_KEY 0xA50B
-#define portLOCK_KEY 0xA500
+respectively. */
+#define portUNLOCK_KEY 0xA50B
+#define portLOCK_KEY 0xA500
/*-----------------------------------------------------------*/
@@ -82,19 +82,19 @@
* Function to start the first task executing - written in asm code as direct
* access to registers is required.
*/
-static void prvStartFirstTask( void ) __attribute__( ( naked ) );
+static void prvStartFirstTask( void ) __attribute__((naked));
/*
* Software interrupt handler. Performs the actual context switch (saving and
* restoring of registers). Written in asm code as direct register access is
* required.
*/
-void vPortSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+void vPortSoftwareInterruptISR( void ) __attribute__((naked));
/*
* The tick interrupt handler.
*/
-void vPortTickISR( void ) __attribute__( ( interrupt ) );
+void vPortTickISR( void ) __attribute__((interrupt));
/*
* Sets up the periodic ISR used for the RTOS tick using the CMT.
@@ -104,10 +104,9 @@
*/
static void prvSetupTimerInterrupt( void );
#ifndef configSETUP_TICK_INTERRUPT
-
-/* The user has not provided their own tick interrupt configuration so use
- * the definition in this file (which uses the interval timer). */
- #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+ /* The user has not provided their own tick interrupt configuration so use
+ the definition in this file (which uses the interval timer). */
+ #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
#endif /* configSETUP_TICK_INTERRUPT */
/*
@@ -116,572 +115,560 @@
* instruction.
*/
#if configUSE_TICKLESS_IDLE == 1
- static void prvSleep( TickType_t xExpectedIdleTime );
+ static void prvSleep( TickType_t xExpectedIdleTime );
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
/* Used in the context save and restore code. */
-extern void * pxCurrentTCB;
+extern void *pxCurrentTCB;
/* Calculate how many clock increments make up a single tick period. */
static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
#if configUSE_TICKLESS_IDLE == 1
-/* Holds the maximum number of ticks that can be suppressed - which is
- * basically how far into the future an interrupt can be generated. Set
- * during initialisation. This is the maximum possible value that the
- * compare match register can hold divided by ulMatchValueForOneTick. */
- static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+ /* Holds the maximum number of ticks that can be suppressed - which is
+ basically how far into the future an interrupt can be generated. Set
+ during initialisation. This is the maximum possible value that the
+ compare match register can hold divided by ulMatchValueForOneTick. */
+ static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-/* Flag set from the tick interrupt to allow the sleep processing to know if
- * sleep mode was exited because of a tick interrupt, or an interrupt
- * generated by something else. */
- static volatile uint32_t ulTickFlag = pdFALSE;
+ /* Flag set from the tick interrupt to allow the sleep processing to know if
+ sleep mode was exited because of a tick interrupt, or an interrupt
+ generated by something else. */
+ static volatile uint32_t ulTickFlag = pdFALSE;
-/* The CMT counter is stopped temporarily each time it is re-programmed.
- * The following constant offsets the CMT counter match value by the number of
- * CMT counts that would typically be missed while the counter was stopped to
- * compensate for the lost time. The large difference between the divided CMT
- * clock and the CPU clock means it is likely ulStoppedTimerCompensation will
- * equal zero - and be optimised away. */
- static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
+ /* The CMT counter is stopped temporarily each time it is re-programmed.
+ The following constant offsets the CMT counter match value by the number of
+ CMT counts that would typically be missed while the counter was stopped to
+ compensate for the lost time. The large difference between the divided CMT
+ clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+ equal zero - and be optimised away. */
+ static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
-#endif /* if configUSE_TICKLESS_IDLE == 1 */
+#endif
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Offset to end up on 8 byte boundary. */
- pxTopOfStack--;
+ /* Offset to end up on 8 byte boundary. */
+ pxTopOfStack--;
- /* R0 is not included as it is the stack pointer. */
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ /* R0 is not included as it is the stack pointer. */
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
- /* When debugging it can be useful if every register is set to a known
- * value. Otherwise code space can be saved by just setting the registers
- * that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaabbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
- {
- /* Leave space for the registers that will get popped from the stack
- * when the task first starts executing. */
- pxTopOfStack -= 15;
- }
- #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaabbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ /* Leave space for the registers that will get popped from the stack
+ when the task first starts executing. */
+ pxTopOfStack -= 15;
+ }
+ #endif
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* Accumulator. */
- pxTopOfStack--;
- *pxTopOfStack = 0x87654321; /* Accumulator. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* Accumulator. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x87654321; /* Accumulator. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate
- * the tick interrupt. This way the application can decide which
- * peripheral to use. If tickless mode is used then the default
- * implementation defined in this file (which uses CMT0) should not be
- * overridden. */
- configSETUP_TICK_INTERRUPT();
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate
+ the tick interrupt. This way the application can decide which
+ peripheral to use. If tickless mode is used then the default
+ implementation defined in this file (which uses CMT0) should not be
+ overridden. */
+ configSETUP_TICK_INTERRUPT();
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the first task. */
- prvStartFirstTask();
- }
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
- /* Execution should not reach here as the tasks are now running!
- * prvSetupTimerInterrupt() is called here to prevent the compiler outputting
- * a warning about a statically declared function not being referenced in the
- * case that the application writer has provided their own tick interrupt
- * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
- * their own routine will be called in place of prvSetupTimerInterrupt()). */
- prvSetupTimerInterrupt();
+ /* Execution should not reach here as the tasks are now running!
+ prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+ a warning about a statically declared function not being referenced in the
+ case that the application writer has provided their own tick interrupt
+ configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+ their own routine will be called in place of prvSetupTimerInterrupt()). */
+ prvSetupTimerInterrupt();
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
}
/*-----------------------------------------------------------*/
static void prvStartFirstTask( void )
{
- __asm volatile
- (
+ __asm volatile
+ (
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ "SETPSW U \n" \
- /* When starting the scheduler there is nothing that needs moving to the
- * interrupt stack because the function is not called from an interrupt.
- * Just ensure the current stack is the user stack. */
- "SETPSW U \n"\
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [R15], R15 \n" \
+ "MOV.L [R15], R0 \n" \
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ "POP R15 \n" \
- /* Obtain the location of the stack associated with which ever task
- * pxCurrentTCB is currently pointing to. */
- "MOV.L #_pxCurrentTCB, R15 \n"\
- "MOV.L [R15], R15 \n"\
- "MOV.L [R15], R0 \n"\
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15 \n" \
+ "POP R15 \n" \
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15 \n" \
- /* Restore the registers from the stack of the task pointed to by
- * pxCurrentTCB. */
- "POP R15 \n"\
+ /* R1 to R15 - R0 is not included as it is the SP. */
+ "POPM R1-R15 \n" \
- /* Accumulator low 32 bits. */
- "MVTACLO R15 \n"\
- "POP R15 \n"\
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15 \n"\
-
- /* R1 to R15 - R0 is not included as it is the SP. */
- "POPM R1-R15 \n"\
-
- /* This pops the remaining registers. */
- "RTE \n"\
- "NOP \n"\
- "NOP \n"
- );
+ /* This pops the remaining registers. */
+ "RTE \n" \
+ "NOP \n" \
+ "NOP \n"
+ );
}
/*-----------------------------------------------------------*/
void vPortSoftwareInterruptISR( void )
{
- __asm volatile
- (
- /* Re-enable interrupts. */
- "SETPSW I \n"\
+ __asm volatile
+ (
+ /* Re-enable interrupts. */
+ "SETPSW I \n" \
+ /* Move the data that was automatically pushed onto the interrupt stack when
+ the interrupt occurred from the interrupt stack to the user stack.
- /* Move the data that was automatically pushed onto the interrupt stack when
- * the interrupt occurred from the interrupt stack to the user stack.
- *
- * R15 is saved before it is clobbered. */
- "PUSH.L R15 \n"\
+ R15 is saved before it is clobbered. */
+ "PUSH.L R15 \n" \
- /* Read the user stack pointer. */
- "MVFC USP, R15 \n"\
+ /* Read the user stack pointer. */
+ "MVFC USP, R15 \n" \
- /* Move the address down to the data being moved. */
- "SUB #12, R15 \n"\
- "MVTC R15, USP \n"\
+ /* Move the address down to the data being moved. */
+ "SUB #12, R15 \n" \
+ "MVTC R15, USP \n" \
- /* Copy the data across, R15, then PC, then PSW. */
- "MOV.L [ R0 ], [ R15 ] \n"\
- "MOV.L 4[ R0 ], 4[ R15 ] \n"\
- "MOV.L 8[ R0 ], 8[ R15 ] \n"\
+ /* Copy the data across, R15, then PC, then PSW. */
+ "MOV.L [ R0 ], [ R15 ] \n" \
+ "MOV.L 4[ R0 ], 4[ R15 ] \n" \
+ "MOV.L 8[ R0 ], 8[ R15 ] \n" \
- /* Move the interrupt stack pointer to its new correct position. */
- "ADD #12, R0 \n"\
+ /* Move the interrupt stack pointer to its new correct position. */
+ "ADD #12, R0 \n" \
- /* All the rest of the registers are saved directly to the user stack. */
- "SETPSW U \n"\
+ /* All the rest of the registers are saved directly to the user stack. */
+ "SETPSW U \n" \
- /* Save the rest of the general registers (R15 has been saved already). */
- "PUSHM R1-R14 \n"\
+ /* Save the rest of the general registers (R15 has been saved already). */
+ "PUSHM R1-R14 \n" \
- /* Save the accumulator. */
- "MVFACHI R15 \n"\
- "PUSH.L R15 \n"\
+ /* Save the accumulator. */
+ "MVFACHI R15 \n" \
+ "PUSH.L R15 \n" \
- /* Middle word. */
- "MVFACMI R15 \n"\
+ /* Middle word. */
+ "MVFACMI R15 \n" \
- /* Shifted left as it is restored to the low order word. */
- "SHLL #16, R15 \n"\
- "PUSH.L R15 \n"\
+ /* Shifted left as it is restored to the low order word. */
+ "SHLL #16, R15 \n" \
+ "PUSH.L R15 \n" \
- /* Save the stack pointer to the TCB. */
- "MOV.L #_pxCurrentTCB, R15 \n"\
- "MOV.L [ R15 ], R15 \n"\
- "MOV.L R0, [ R15 ] \n"\
+ /* Save the stack pointer to the TCB. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L R0, [ R15 ] \n" \
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel
+ structures are being accessed. */
+ "MVTIPL %0 \n" \
- /* Ensure the interrupt mask is set to the syscall priority while the kernel
- * structures are being accessed. */
- "MVTIPL %0 \n"\
+ /* Select the next task to run. */
+ "BSR.A _vTaskSwitchContext \n" \
- /* Select the next task to run. */
- "BSR.A _vTaskSwitchContext \n"\
+ /* Reset the interrupt mask as no more data structure access is required. */
+ "MVTIPL %1 \n" \
- /* Reset the interrupt mask as no more data structure access is required. */
- "MVTIPL %1 \n"\
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ "MOV.L #_pxCurrentTCB,R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L [ R15 ], R0 \n" \
-
- /* Load the stack pointer of the task that is now selected as the Running
- * state task from its TCB. */
- "MOV.L #_pxCurrentTCB,R15 \n"\
- "MOV.L [ R15 ], R15 \n"\
- "MOV.L [ R15 ], R0 \n"\
-
-
- /* Restore the context of the new task. The PSW (Program Status Word) and
- * PC will be popped by the RTE instruction. */
- "POP R15 \n"\
- "MVTACLO R15 \n"\
- "POP R15 \n"\
- "MVTACHI R15 \n"\
- "POPM R1-R15 \n"\
- "RTE \n"\
- "NOP \n"\
- "NOP "
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
- );
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ "POP R15 \n" \
+ "MVTACLO R15 \n" \
+ "POP R15 \n" \
+ "MVTACHI R15 \n" \
+ "POPM R1-R15 \n" \
+ "RTE \n" \
+ "NOP \n" \
+ "NOP "
+ :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+ );
}
/*-----------------------------------------------------------*/
void vPortTickISR( void )
{
- /* Re-enabled interrupts. */
- __asm volatile ( "SETPSW I");
+ /* Re-enabled interrupts. */
+ __asm volatile( "SETPSW I" );
- /* Increment the tick, and perform any processing the new tick value
- * necessitates. Ensure IPL is at the max syscall value first. */
- portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. Ensure IPL is at the max syscall value first. */
+ portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
- #if configUSE_TICKLESS_IDLE == 1
- {
- /* The CPU woke because of a tick. */
- ulTickFlag = pdTRUE;
+ #if configUSE_TICKLESS_IDLE == 1
+ {
+ /* The CPU woke because of a tick. */
+ ulTickFlag = pdTRUE;
- /* If this is the first tick since exiting tickless mode then the CMT
- * compare match value needs resetting. */
- CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
- }
- #endif
+ /* If this is the first tick since exiting tickless mode then the CMT
+ compare match value needs resetting. */
+ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+ }
+ #endif
}
/*-----------------------------------------------------------*/
uint32_t ulPortGetIPL( void )
{
- __asm volatile
- (
- "MVFC PSW, R1 \n"\
- "SHLR #24, R1 \n"\
- "RTS "
- );
+ __asm volatile
+ (
+ "MVFC PSW, R1 \n" \
+ "SHLR #24, R1 \n" \
+ "RTS "
+ );
- /* This will never get executed, but keeps the compiler from complaining. */
- return 0;
+ /* This will never get executed, but keeps the compiler from complaining. */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortSetIPL( uint32_t ulNewIPL )
{
- __asm volatile
- (
- "PUSH R5 \n"\
- "MVFC PSW, R5 \n"\
- "SHLL #24, R1 \n"\
- "AND #-0F000001H, R5 \n"\
- "OR R1, R5 \n"\
- "MVTC R5, PSW \n"\
- "POP R5 \n"\
- "RTS "
- );
+ __asm volatile
+ (
+ "PUSH R5 \n" \
+ "MVFC PSW, R5 \n" \
+ "SHLL #24, R1 \n" \
+ "AND #-0F000001H, R5 \n" \
+ "OR R1, R5 \n" \
+ "MVTC R5, PSW \n" \
+ "POP R5 \n" \
+ "RTS "
+ );
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- /* Unlock. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+ /* Unlock. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
- /* Enable CMT0. */
- MSTP( CMT0 ) = 0;
+ /* Enable CMT0. */
+ MSTP( CMT0 ) = 0;
- /* Lock again. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
+ /* Lock again. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
- /* Interrupt on compare match. */
- CMT0.CMCR.BIT.CMIE = 1;
+ /* Interrupt on compare match. */
+ CMT0.CMCR.BIT.CMIE = 1;
- /* Set the compare match value. */
- CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+ /* Set the compare match value. */
+ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
- /* Divide the PCLK. */
- #if portCLOCK_DIVISOR == 512
- {
- CMT0.CMCR.BIT.CKS = 3;
- }
- #elif portCLOCK_DIVISOR == 128
- {
- CMT0.CMCR.BIT.CKS = 2;
- }
- #elif portCLOCK_DIVISOR == 32
- {
- CMT0.CMCR.BIT.CKS = 1;
- }
- #elif portCLOCK_DIVISOR == 8
- {
- CMT0.CMCR.BIT.CKS = 0;
- }
- #else /* if portCLOCK_DIVISOR == 512 */
- {
- #error Invalid portCLOCK_DIVISOR setting
- }
- #endif /* if portCLOCK_DIVISOR == 512 */
+ /* Divide the PCLK. */
+ #if portCLOCK_DIVISOR == 512
+ {
+ CMT0.CMCR.BIT.CKS = 3;
+ }
+ #elif portCLOCK_DIVISOR == 128
+ {
+ CMT0.CMCR.BIT.CKS = 2;
+ }
+ #elif portCLOCK_DIVISOR == 32
+ {
+ CMT0.CMCR.BIT.CKS = 1;
+ }
+ #elif portCLOCK_DIVISOR == 8
+ {
+ CMT0.CMCR.BIT.CKS = 0;
+ }
+ #else
+ {
+ #error Invalid portCLOCK_DIVISOR setting
+ }
+ #endif
- /* Enable the interrupt... */
- _IEN( _CMT0_CMI0 ) = 1;
+ /* Enable the interrupt... */
+ _IEN( _CMT0_CMI0 ) = 1;
- /* ...and set its priority to the application defined kernel priority. */
- _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* ...and set its priority to the application defined kernel priority. */
+ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the timer. */
- CMT.CMSTR0.BIT.STR0 = 1;
+ /* Start the timer. */
+ CMT.CMSTR0.BIT.STR0 = 1;
}
/*-----------------------------------------------------------*/
#if configUSE_TICKLESS_IDLE == 1
- static void prvSleep( TickType_t xExpectedIdleTime )
- {
- /* Allow the application to define some pre-sleep processing. */
- configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
+ static void prvSleep( TickType_t xExpectedIdleTime )
+ {
+ /* Allow the application to define some pre-sleep processing. */
+ configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
- /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
- * means the application defined code has already executed the WAIT
- * instruction. */
- if( xExpectedIdleTime > 0 )
- {
- __asm volatile ( "WAIT" );
- }
+ /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
+ means the application defined code has already executed the WAIT
+ instruction. */
+ if( xExpectedIdleTime > 0 )
+ {
+ __asm volatile( "WAIT" );
+ }
- /* Allow the application to define some post sleep processing. */
- configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
- }
+ /* Allow the application to define some post sleep processing. */
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
#if configUSE_TICKLESS_IDLE == 1
- void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
- {
- uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
- eSleepModeStatus eSleepAction;
+ void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+ eSleepModeStatus eSleepAction;
- /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
+ /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
- /* Make sure the CMT reload value does not overflow the counter. */
- if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
- {
- xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
- }
+ /* Make sure the CMT reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
- /* Calculate the reload value required to wait xExpectedIdleTime tick
- * periods. */
- ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+ /* Calculate the reload value required to wait xExpectedIdleTime tick
+ periods. */
+ ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+ if( ulMatchValue > ulStoppedTimerCompensation )
+ {
+ /* Compensate for the fact that the CMT is going to be stopped
+ momentarily. */
+ ulMatchValue -= ulStoppedTimerCompensation;
+ }
- if( ulMatchValue > ulStoppedTimerCompensation )
- {
- /* Compensate for the fact that the CMT is going to be stopped
- * momentarily. */
- ulMatchValue -= ulStoppedTimerCompensation;
- }
+ /* Stop the CMT momentarily. The time the CMT is stopped for is
+ accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ CMT.CMSTR0.BIT.STR0 = 0;
+ while( CMT.CMSTR0.BIT.STR0 == 1 )
+ {
+ /* Nothing to do here. */
+ }
- /* Stop the CMT momentarily. The time the CMT is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- CMT.CMSTR0.BIT.STR0 = 0;
+ /* Critical section using the global interrupt bit as the i bit is
+ automatically reset by the WAIT instruction. */
+ __asm volatile( "CLRPSW i" );
- while( CMT.CMSTR0.BIT.STR0 == 1 )
- {
- /* Nothing to do here. */
- }
+ /* The tick flag is set to false before sleeping. If it is true when
+ sleep mode is exited then sleep mode was probably exited because the
+ tick was suppressed for the entire xExpectedIdleTime period. */
+ ulTickFlag = pdFALSE;
- /* Critical section using the global interrupt bit as the i bit is
- * automatically reset by the WAIT instruction. */
- __asm volatile ( "CLRPSW i" );
+ /* If a context switch is pending then abandon the low power entry as
+ the context switch might have been pended by an external interrupt that
+ requires processing. */
+ eSleepAction = eTaskConfirmSleepModeStatus();
+ if( eSleepAction == eAbortSleep )
+ {
+ /* Restart tick. */
+ CMT.CMSTR0.BIT.STR0 = 1;
+ __asm volatile( "SETPSW i" );
+ }
+ else if( eSleepAction == eNoTasksWaitingTimeout )
+ {
+ /* Protection off. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
- /* The tick flag is set to false before sleeping. If it is true when
- * sleep mode is exited then sleep mode was probably exited because the
- * tick was suppressed for the entire xExpectedIdleTime period. */
- ulTickFlag = pdFALSE;
+ /* Ready for software standby with all clocks stopped. */
+ SYSTEM.SBYCR.BIT.SSBY = 1;
- /* If a context switch is pending then abandon the low power entry as
- * the context switch might have been pended by an external interrupt that
- * requires processing. */
- eSleepAction = eTaskConfirmSleepModeStatus();
+ /* Protection on. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
- if( eSleepAction == eAbortSleep )
- {
- /* Restart tick. */
- CMT.CMSTR0.BIT.STR0 = 1;
- __asm volatile ( "SETPSW i" );
- }
- else if( eSleepAction == eNoTasksWaitingTimeout )
- {
- /* Protection off. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+ /* Sleep until something happens. Calling prvSleep() will
+ automatically reset the i bit in the PSW. */
+ prvSleep( xExpectedIdleTime );
- /* Ready for software standby with all clocks stopped. */
- SYSTEM.SBYCR.BIT.SSBY = 1;
+ /* Restart the CMT. */
+ CMT.CMSTR0.BIT.STR0 = 1;
+ }
+ else
+ {
+ /* Protection off. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
- /* Protection on. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
+ /* Ready for deep sleep mode. */
+ SYSTEM.MSTPCRC.BIT.DSLPE = 1;
+ SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
+ SYSTEM.SBYCR.BIT.SSBY = 0;
- /* Sleep until something happens. Calling prvSleep() will
- * automatically reset the i bit in the PSW. */
- prvSleep( xExpectedIdleTime );
+ /* Protection on. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
- /* Restart the CMT. */
- CMT.CMSTR0.BIT.STR0 = 1;
- }
- else
- {
- /* Protection off. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+ /* Adjust the match value to take into account that the current
+ time slice is already partially complete. */
+ ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
- /* Ready for deep sleep mode. */
- SYSTEM.MSTPCRC.BIT.DSLPE = 1;
- SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
- SYSTEM.SBYCR.BIT.SSBY = 0;
+ /* Restart the CMT to count up to the new match value. */
+ CMT0.CMCNT = 0;
+ CMT.CMSTR0.BIT.STR0 = 1;
- /* Protection on. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
+ /* Sleep until something happens. Calling prvSleep() will
+ automatically reset the i bit in the PSW. */
+ prvSleep( xExpectedIdleTime );
- /* Adjust the match value to take into account that the current
- * time slice is already partially complete. */
- ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+ /* Stop CMT. Again, the time the SysTick is stopped for is
+ accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ CMT.CMSTR0.BIT.STR0 = 0;
+ while( CMT.CMSTR0.BIT.STR0 == 1 )
+ {
+ /* Nothing to do here. */
+ }
- /* Restart the CMT to count up to the new match value. */
- CMT0.CMCNT = 0;
- CMT.CMSTR0.BIT.STR0 = 1;
+ ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
- /* Sleep until something happens. Calling prvSleep() will
- * automatically reset the i bit in the PSW. */
- prvSleep( xExpectedIdleTime );
+ if( ulTickFlag != pdFALSE )
+ {
+ /* The tick interrupt has already executed, although because
+ this function is called with the scheduler suspended the actual
+ tick processing will not occur until after this function has
+ exited. Reset the match value with whatever remains of this
+ tick period. */
+ ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
- /* Stop CMT. Again, the time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- CMT.CMSTR0.BIT.STR0 = 0;
+ /* The tick interrupt handler will already have pended the tick
+ processing in the kernel. As the pending tick will be
+ processed as soon as this function exits, the tick value
+ maintained by the tick is stepped forward by one less than the
+ time spent sleeping. The actual stepping of the tick appears
+ later in this function. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep.
+ How many complete tick periods passed while the processor was
+ sleeping? */
+ ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
- while( CMT.CMSTR0.BIT.STR0 == 1 )
- {
- /* Nothing to do here. */
- }
+ /* The match value is set to whatever fraction of a single tick
+ period remains. */
+ ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+ }
- ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
+ /* Restart the CMT so it runs up to the match value. The match value
+ will get set to the value required to generate exactly one tick period
+ the next time the CMT interrupt executes. */
+ CMT0.CMCNT = 0;
+ CMT.CMSTR0.BIT.STR0 = 1;
- if( ulTickFlag != pdFALSE )
- {
- /* The tick interrupt has already executed, although because
- * this function is called with the scheduler suspended the actual
- * tick processing will not occur until after this function has
- * exited. Reset the match value with whatever remains of this
- * tick period. */
- ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
- /* The tick interrupt handler will already have pended the tick
- * processing in the kernel. As the pending tick will be
- * processed as soon as this function exits, the tick value
- * maintained by the tick is stepped forward by one less than the
- * time spent sleeping. The actual stepping of the tick appears
- * later in this function. */
- ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
- }
- else
- {
- /* Something other than the tick interrupt ended the sleep.
- * How many complete tick periods passed while the processor was
- * sleeping? */
- ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
-
- /* The match value is set to whatever fraction of a single tick
- * period remains. */
- ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
- }
-
- /* Restart the CMT so it runs up to the match value. The match value
- * will get set to the value required to generate exactly one tick period
- * the next time the CMT interrupt executes. */
- CMT0.CMCNT = 0;
- CMT.CMSTR0.BIT.STR0 = 1;
-
- /* Wind the tick forward by the number of tick periods that the CPU
- * remained in a low power state. */
- vTaskStepTick( ulCompleteTickPeriods );
- }
- }
+ /* Wind the tick forward by the number of tick periods that the CPU
+ remained in a low power state. */
+ vTaskStepTick( ulCompleteTickPeriods );
+ }
+ }
#endif /* configUSE_TICKLESS_IDLE */
+
diff --git a/portable/GCC/RX100/portmacro.h b/portable/GCC/RX100/portmacro.h
index fb356e8..77e91a1 100644
--- a/portable/GCC/RX100/portmacro.h
+++ b/portable/GCC/RX100/portmacro.h
@@ -27,11 +27,11 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,100 +44,101 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() __asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __asm volatile( "NOP" )
/* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value
- * back to ensure it is set before continuing, then restore the clobbered
- * register. */
- #define portYIELD() \
- __asm volatile \
- ( \
- "MOV.L #0x872E0, r5 \n\t"\
- "MOV.B #1, [r5] \n\t"\
- "MOV.L [r5], r5 \n\t"\
- ::: "r5" \
- )
+back to ensure it is set before continuing, then restore the clobbered
+register. */
+#define portYIELD() \
+ __asm volatile \
+ ( \
+ "MOV.L #0x872E0, r5 \n\t" \
+ "MOV.B #1, [r5] \n\t" \
+ "MOV.L [r5], r5 \n\t" \
+ ::: "r5" \
+ )
- #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) { portYIELD(); }
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) { portYIELD(); }
/* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
- * functions are those that end in FromISR. FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
- #define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0")
- #ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #else
- #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #endif
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+ #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
- uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) );
- void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
/* Tickless idle/low power functionality. */
- #if configUSE_TICKLESS_IDLE == 1
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
- #endif
+#if configUSE_TICKLESS_IDLE == 1
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+#endif
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/RX600/port.c b/portable/GCC/RX600/port.c
index 15f2a6c..422b6c7 100644
--- a/portable/GCC/RX600/port.c
+++ b/portable/GCC/RX600/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the SH2A port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -42,17 +42,17 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
+PSW is set with U and I set, and PM and IPL clear. */
#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
/* These macros allow a critical section to be added around the call to
- * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
- * priority - ie a known priority. Therefore these local macros are a slight
- * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
- * which would require the old IPL to be read first and stored in a local variable. */
-#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0"::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority. Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
/*-----------------------------------------------------------*/
@@ -60,308 +60,299 @@
* Function to start the first task executing - written in asm code as direct
* access to registers is required.
*/
-static void prvStartFirstTask( void ) __attribute__( ( naked ) );
+static void prvStartFirstTask( void ) __attribute__((naked));
/*
* Software interrupt handler. Performs the actual context switch (saving and
* restoring of registers). Written in asm code as direct register access is
* required.
*/
-void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+void vSoftwareInterruptISR( void ) __attribute__((naked));
/*
* The tick interrupt handler.
*/
-void vTickISR( void ) __attribute__( ( interrupt ) );
+void vTickISR( void ) __attribute__((interrupt));
/*-----------------------------------------------------------*/
-extern void * pxCurrentTCB;
+extern void *pxCurrentTCB;
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* R0 is not included as it is the stack pointer. */
+ /* R0 is not included as it is the stack pointer. */
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
- /* When debugging it can be useful if every register is set to a known
- * value. Otherwise code space can be saved by just setting the registers
- * that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0xffffffff; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xeeeeeeee;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
- {
- pxTopOfStack -= 15;
- }
- #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0xffffffff; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xeeeeeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= 15;
+ }
+ #endif
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_FPSW;
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* Accumulator. */
- pxTopOfStack--;
- *pxTopOfStack = 0x87654321; /* Accumulator. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_FPSW;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* Accumulator. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x87654321; /* Accumulator. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate the
- * tick interrupt. This way the application can decide which peripheral to
- * use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the first task. */
- prvStartFirstTask();
- }
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
}
/*-----------------------------------------------------------*/
static void prvStartFirstTask( void )
{
- __asm volatile
- (
+ __asm volatile
+ (
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ "SETPSW U \n" \
- /* When starting the scheduler there is nothing that needs moving to the
- * interrupt stack because the function is not called from an interrupt.
- * Just ensure the current stack is the user stack. */
- "SETPSW U \n"\
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [R15], R15 \n" \
+ "MOV.L [R15], R0 \n" \
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ "POP R15 \n" \
- /* Obtain the location of the stack associated with which ever task
- * pxCurrentTCB is currently pointing to. */
- "MOV.L #_pxCurrentTCB, R15 \n"\
- "MOV.L [R15], R15 \n"\
- "MOV.L [R15], R0 \n"\
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15 \n" \
+ "POP R15 \n" \
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15 \n" \
+ "POP R15 \n" \
- /* Restore the registers from the stack of the task pointed to by
- * pxCurrentTCB. */
- "POP R15 \n"\
+ /* Floating point status word. */
+ "MVTC R15, FPSW \n" \
- /* Accumulator low 32 bits. */
- "MVTACLO R15 \n"\
- "POP R15 \n"\
+ /* R1 to R15 - R0 is not included as it is the SP. */
+ "POPM R1-R15 \n" \
- /* Accumulator high 32 bits. */
- "MVTACHI R15 \n"\
- "POP R15 \n"\
-
- /* Floating point status word. */
- "MVTC R15, FPSW \n"\
-
- /* R1 to R15 - R0 is not included as it is the SP. */
- "POPM R1-R15 \n"\
-
- /* This pops the remaining registers. */
- "RTE \n"\
- "NOP \n"\
- "NOP \n"
- );
+ /* This pops the remaining registers. */
+ "RTE \n" \
+ "NOP \n" \
+ "NOP \n"
+ );
}
/*-----------------------------------------------------------*/
void vSoftwareInterruptISR( void )
{
- __asm volatile
- (
- /* Re-enable interrupts. */
- "SETPSW I \n"\
+ __asm volatile
+ (
+ /* Re-enable interrupts. */
+ "SETPSW I \n" \
+ /* Move the data that was automatically pushed onto the interrupt stack when
+ the interrupt occurred from the interrupt stack to the user stack.
- /* Move the data that was automatically pushed onto the interrupt stack when
- * the interrupt occurred from the interrupt stack to the user stack.
- *
- * R15 is saved before it is clobbered. */
- "PUSH.L R15 \n"\
+ R15 is saved before it is clobbered. */
+ "PUSH.L R15 \n" \
- /* Read the user stack pointer. */
- "MVFC USP, R15 \n"\
+ /* Read the user stack pointer. */
+ "MVFC USP, R15 \n" \
- /* Move the address down to the data being moved. */
- "SUB #12, R15 \n"\
- "MVTC R15, USP \n"\
+ /* Move the address down to the data being moved. */
+ "SUB #12, R15 \n" \
+ "MVTC R15, USP \n" \
- /* Copy the data across, R15, then PC, then PSW. */
- "MOV.L [ R0 ], [ R15 ] \n"\
- "MOV.L 4[ R0 ], 4[ R15 ] \n"\
- "MOV.L 8[ R0 ], 8[ R15 ] \n"\
+ /* Copy the data across, R15, then PC, then PSW. */
+ "MOV.L [ R0 ], [ R15 ] \n" \
+ "MOV.L 4[ R0 ], 4[ R15 ] \n" \
+ "MOV.L 8[ R0 ], 8[ R15 ] \n" \
- /* Move the interrupt stack pointer to its new correct position. */
- "ADD #12, R0 \n"\
+ /* Move the interrupt stack pointer to its new correct position. */
+ "ADD #12, R0 \n" \
- /* All the rest of the registers are saved directly to the user stack. */
- "SETPSW U \n"\
+ /* All the rest of the registers are saved directly to the user stack. */
+ "SETPSW U \n" \
- /* Save the rest of the general registers (R15 has been saved already). */
- "PUSHM R1-R14 \n"\
+ /* Save the rest of the general registers (R15 has been saved already). */
+ "PUSHM R1-R14 \n" \
- /* Save the FPSW and accumulator. */
- "MVFC FPSW, R15 \n"\
- "PUSH.L R15 \n"\
- "MVFACHI R15 \n"\
- "PUSH.L R15 \n"\
+ /* Save the FPSW and accumulator. */
+ "MVFC FPSW, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACHI R15 \n" \
+ "PUSH.L R15 \n" \
- /* Middle word. */
- "MVFACMI R15 \n"\
+ /* Middle word. */
+ "MVFACMI R15 \n" \
- /* Shifted left as it is restored to the low order word. */
- "SHLL #16, R15 \n"\
- "PUSH.L R15 \n"\
+ /* Shifted left as it is restored to the low order word. */
+ "SHLL #16, R15 \n" \
+ "PUSH.L R15 \n" \
- /* Save the stack pointer to the TCB. */
- "MOV.L #_pxCurrentTCB, R15 \n"\
- "MOV.L [ R15 ], R15 \n"\
- "MOV.L R0, [ R15 ] \n"\
+ /* Save the stack pointer to the TCB. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L R0, [ R15 ] \n" \
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel
+ structures are being accessed. */
+ "MVTIPL %0 \n" \
- /* Ensure the interrupt mask is set to the syscall priority while the kernel
- * structures are being accessed. */
- "MVTIPL %0 \n"\
+ /* Select the next task to run. */
+ "BSR.A _vTaskSwitchContext \n" \
- /* Select the next task to run. */
- "BSR.A _vTaskSwitchContext \n"\
+ /* Reset the interrupt mask as no more data structure access is required. */
+ "MVTIPL %1 \n" \
- /* Reset the interrupt mask as no more data structure access is required. */
- "MVTIPL %1 \n"\
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ "MOV.L #_pxCurrentTCB,R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L [ R15 ], R0 \n" \
-
- /* Load the stack pointer of the task that is now selected as the Running
- * state task from its TCB. */
- "MOV.L #_pxCurrentTCB,R15 \n"\
- "MOV.L [ R15 ], R15 \n"\
- "MOV.L [ R15 ], R0 \n"\
-
-
- /* Restore the context of the new task. The PSW (Program Status Word) and
- * PC will be popped by the RTE instruction. */
- "POP R15 \n"\
- "MVTACLO R15 \n"\
- "POP R15 \n"\
- "MVTACHI R15 \n"\
- "POP R15 \n"\
- "MVTC R15, FPSW \n"\
- "POPM R1-R15 \n"\
- "RTE \n"\
- "NOP \n"\
- "NOP "
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
- );
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ "POP R15 \n" \
+ "MVTACLO R15 \n" \
+ "POP R15 \n" \
+ "MVTACHI R15 \n" \
+ "POP R15 \n" \
+ "MVTC R15, FPSW \n" \
+ "POPM R1-R15 \n" \
+ "RTE \n" \
+ "NOP \n" \
+ "NOP "
+ :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+ );
}
/*-----------------------------------------------------------*/
void vTickISR( void )
{
- /* Re-enabled interrupts. */
- __asm volatile ( "SETPSW I");
+ /* Re-enabled interrupts. */
+ __asm volatile( "SETPSW I" );
- /* Increment the tick, and perform any processing the new tick value
- * necessitates. Ensure IPL is at the max syscall value first. */
- portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. Ensure IPL is at the max syscall value first. */
+ portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
}
/*-----------------------------------------------------------*/
uint32_t ulPortGetIPL( void )
{
- __asm volatile
- (
- "MVFC PSW, R1 \n"\
- "SHLR #24, R1 \n"\
- "RTS "
- );
+ __asm volatile
+ (
+ "MVFC PSW, R1 \n" \
+ "SHLR #24, R1 \n" \
+ "RTS "
+ );
- /* This will never get executed, but keeps the compiler from complaining. */
- return 0;
+ /* This will never get executed, but keeps the compiler from complaining. */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortSetIPL( uint32_t ulNewIPL )
{
- __asm volatile
- (
- "PUSH R5 \n"\
- "MVFC PSW, R5 \n"\
- "SHLL #24, R1 \n"\
- "AND #-0F000001H, R5 \n"\
- "OR R1, R5 \n"\
- "MVTC R5, PSW \n"\
- "POP R5 \n"\
- "RTS "
- );
+ __asm volatile
+ (
+ "PUSH R5 \n" \
+ "MVFC PSW, R5 \n" \
+ "SHLL #24, R1 \n" \
+ "AND #-0F000001H, R5 \n" \
+ "OR R1, R5 \n" \
+ "MVTC R5, PSW \n" \
+ "POP R5 \n" \
+ "RTS "
+ );
}
diff --git a/portable/GCC/RX600/portmacro.h b/portable/GCC/RX600/portmacro.h
index 46b88af..c6cb841 100644
--- a/portable/GCC/RX600/portmacro.h
+++ b/portable/GCC/RX600/portmacro.h
@@ -27,11 +27,11 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,94 +44,95 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() __asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __asm volatile( "NOP" )
/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
- * where portITU_SWINTR is the location of the software interrupt register
- * (0x000872E0). Don't rely on the assembler to select a register, so instead
- * save and restore clobbered registers manually. */
- #define portYIELD() \
- __asm volatile \
- ( \
- "PUSH.L R10 \n"\
- "MOV.L #0x872E0, R10 \n"\
- "MOV.B #0x1, [R10] \n"\
- "MOV.L [R10], R10 \n"\
- "POP R10 \n"\
- )
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0). Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD() \
+ __asm volatile \
+ ( \
+ "PUSH.L R10 \n" \
+ "MOV.L #0x872E0, R10 \n" \
+ "MOV.B #0x1, [R10] \n" \
+ "MOV.L [R10], R10 \n" \
+ "POP R10 \n" \
+ )
- #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
- * functions are those that end in FromISR. FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
- #define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0")
- #ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #else
- #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #endif
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+ #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
- uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) );
- void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/RX600v2/port.c b/portable/GCC/RX600v2/port.c
index 520bc7a..3480c18 100644
--- a/portable/GCC/RX600v2/port.c
+++ b/portable/GCC/RX600v2/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the SH2A port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -42,17 +42,17 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
+PSW is set with U and I set, and PM and IPL clear. */
#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
/* These macros allow a critical section to be added around the call to
- * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
- * priority - ie a known priority. Therefore these local macros are a slight
- * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
- * which would require the old IPL to be read first and stored in a local variable. */
-#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority. Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
/*-----------------------------------------------------------*/
@@ -60,357 +60,348 @@
* Function to start the first task executing - written in asm code as direct
* access to registers is required.
*/
-static void prvStartFirstTask( void ) __attribute__( ( naked ) );
+static void prvStartFirstTask( void ) __attribute__((naked));
/*
* Software interrupt handler. Performs the actual context switch (saving and
* restoring of registers). Written in asm code as direct register access is
* required.
*/
-void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+void vSoftwareInterruptISR( void ) __attribute__((naked));
/*
* The tick interrupt handler.
*/
-void vTickISR( void ) __attribute__( ( interrupt ) );
+void vTickISR( void ) __attribute__((interrupt));
/*-----------------------------------------------------------*/
-extern void * pxCurrentTCB;
+extern void *pxCurrentTCB;
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* R0 is not included as it is the stack pointer. */
+ /* R0 is not included as it is the stack pointer. */
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
- /* When debugging it can be useful if every register is set to a known
- * value. Otherwise code space can be saved by just setting the registers
- * that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0xffffffff; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xeeeeeeee;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
- {
- pxTopOfStack -= 15;
- }
- #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0xffffffff; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xeeeeeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= 15;
+ }
+ #endif
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_FPSW;
- pxTopOfStack--;
- *pxTopOfStack = 0x11111111; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444; /* Accumulator 1. */
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555; /* Accumulator 1. */
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666; /* Accumulator 1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_FPSW;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11111111; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444; /* Accumulator 1. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555; /* Accumulator 1. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666; /* Accumulator 1. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate the
- * tick interrupt. This way the application can decide which peripheral to
- * use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the first task. */
- prvStartFirstTask();
- }
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
}
/*-----------------------------------------------------------*/
static void prvStartFirstTask( void )
{
- __asm volatile
- (
+ __asm volatile
+ (
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ "SETPSW U \n" \
- /* When starting the scheduler there is nothing that needs moving to the
- * interrupt stack because the function is not called from an interrupt.
- * Just ensure the current stack is the user stack. */
- "SETPSW U \n"\
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [R15], R15 \n" \
+ "MOV.L [R15], R0 \n" \
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ "POP R15 \n" \
- /* Obtain the location of the stack associated with which ever task
- * pxCurrentTCB is currently pointing to. */
- "MOV.L #_pxCurrentTCB, R15 \n"\
- "MOV.L [R15], R15 \n"\
- "MOV.L [R15], R0 \n"\
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A0 \n" \
+ "POP R15 \n" \
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A0 \n" \
+ "POP R15 \n" \
- /* Restore the registers from the stack of the task pointed to by
- * pxCurrentTCB. */
- "POP R15 \n"\
+ /* Accumulator guard. */
+ "MVTACGU R15, A0 \n" \
+ "POP R15 \n" \
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A0 \n"\
- "POP R15 \n"\
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A1 \n" \
+ "POP R15 \n" \
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A0 \n"\
- "POP R15 \n"\
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A1 \n" \
+ "POP R15 \n" \
- /* Accumulator guard. */
- "MVTACGU R15, A0 \n"\
- "POP R15 \n"\
+ /* Accumulator guard. */
+ "MVTACGU R15, A1 \n" \
+ "POP R15 \n" \
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A1 \n"\
- "POP R15 \n"\
+ /* Floating point status word. */
+ "MVTC R15, FPSW \n" \
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A1 \n"\
- "POP R15 \n"\
+ /* R1 to R15 - R0 is not included as it is the SP. */
+ "POPM R1-R15 \n" \
- /* Accumulator guard. */
- "MVTACGU R15, A1 \n"\
- "POP R15 \n"\
-
- /* Floating point status word. */
- "MVTC R15, FPSW \n"\
-
- /* R1 to R15 - R0 is not included as it is the SP. */
- "POPM R1-R15 \n"\
-
- /* This pops the remaining registers. */
- "RTE \n"\
- "NOP \n"\
- "NOP \n"
- );
+ /* This pops the remaining registers. */
+ "RTE \n" \
+ "NOP \n" \
+ "NOP \n"
+ );
}
/*-----------------------------------------------------------*/
void vSoftwareInterruptISR( void )
{
- __asm volatile
- (
- /* Re-enable interrupts. */
- "SETPSW I \n"\
+ __asm volatile
+ (
+ /* Re-enable interrupts. */
+ "SETPSW I \n" \
+ /* Move the data that was automatically pushed onto the interrupt stack when
+ the interrupt occurred from the interrupt stack to the user stack.
- /* Move the data that was automatically pushed onto the interrupt stack when
- * the interrupt occurred from the interrupt stack to the user stack.
- *
- * R15 is saved before it is clobbered. */
- "PUSH.L R15 \n"\
+ R15 is saved before it is clobbered. */
+ "PUSH.L R15 \n" \
- /* Read the user stack pointer. */
- "MVFC USP, R15 \n"\
+ /* Read the user stack pointer. */
+ "MVFC USP, R15 \n" \
- /* Move the address down to the data being moved. */
- "SUB #12, R15 \n"\
- "MVTC R15, USP \n"\
+ /* Move the address down to the data being moved. */
+ "SUB #12, R15 \n" \
+ "MVTC R15, USP \n" \
- /* Copy the data across, R15, then PC, then PSW. */
- "MOV.L [ R0 ], [ R15 ] \n"\
- "MOV.L 4[ R0 ], 4[ R15 ] \n"\
- "MOV.L 8[ R0 ], 8[ R15 ] \n"\
+ /* Copy the data across, R15, then PC, then PSW. */
+ "MOV.L [ R0 ], [ R15 ] \n" \
+ "MOV.L 4[ R0 ], 4[ R15 ] \n" \
+ "MOV.L 8[ R0 ], 8[ R15 ] \n" \
- /* Move the interrupt stack pointer to its new correct position. */
- "ADD #12, R0 \n"\
+ /* Move the interrupt stack pointer to its new correct position. */
+ "ADD #12, R0 \n" \
- /* All the rest of the registers are saved directly to the user stack. */
- "SETPSW U \n"\
+ /* All the rest of the registers are saved directly to the user stack. */
+ "SETPSW U \n" \
- /* Save the rest of the general registers (R15 has been saved already). */
- "PUSHM R1-R14 \n"\
+ /* Save the rest of the general registers (R15 has been saved already). */
+ "PUSHM R1-R14 \n" \
- /* Save the FPSW and accumulator. */
- "MVFC FPSW, R15 \n"\
- "PUSH.L R15 \n"\
- "MVFACGU #0, A1, R15 \n"\
- "PUSH.L R15 \n"\
- "MVFACHI #0, A1, R15 \n"\
- "PUSH.L R15 \n"\
- /* Low order word. */
- "MVFACLO #0, A1, R15 \n"\
- "PUSH.L R15 \n"\
- "MVFACGU #0, A0, R15 \n"\
- "PUSH.L R15 \n"\
- "MVFACHI #0, A0, R15 \n"\
- "PUSH.L R15 \n"\
- /* Low order word. */
- "MVFACLO #0, A0, R15 \n"\
- "PUSH.L R15 \n"\
+ /* Save the FPSW and accumulator. */
+ "MVFC FPSW, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACGU #0, A1, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACHI #0, A1, R15 \n" \
+ "PUSH.L R15 \n" \
+ /* Low order word. */
+ "MVFACLO #0, A1, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACGU #0, A0, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACHI #0, A0, R15 \n" \
+ "PUSH.L R15 \n" \
+ /* Low order word. */
+ "MVFACLO #0, A0, R15 \n" \
+ "PUSH.L R15 \n" \
- /* Save the stack pointer to the TCB. */
- "MOV.L #_pxCurrentTCB, R15 \n"\
- "MOV.L [ R15 ], R15 \n"\
- "MOV.L R0, [ R15 ] \n"\
+ /* Save the stack pointer to the TCB. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L R0, [ R15 ] \n" \
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel
+ structures are being accessed. */
+ "MVTIPL %0 \n" \
- /* Ensure the interrupt mask is set to the syscall priority while the kernel
- * structures are being accessed. */
- "MVTIPL %0 \n"\
+ /* Select the next task to run. */
+ "BSR.A _vTaskSwitchContext \n" \
- /* Select the next task to run. */
- "BSR.A _vTaskSwitchContext \n"\
+ /* Reset the interrupt mask as no more data structure access is required. */
+ "MVTIPL %1 \n" \
- /* Reset the interrupt mask as no more data structure access is required. */
- "MVTIPL %1 \n"\
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ "MOV.L #_pxCurrentTCB,R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L [ R15 ], R0 \n" \
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ "POP R15 \n" \
- /* Load the stack pointer of the task that is now selected as the Running
- * state task from its TCB. */
- "MOV.L #_pxCurrentTCB,R15 \n"\
- "MOV.L [ R15 ], R15 \n"\
- "MOV.L [ R15 ], R0 \n"\
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A0 \n" \
+ "POP R15 \n" \
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A0 \n" \
+ "POP R15 \n" \
- /* Restore the context of the new task. The PSW (Program Status Word) and
- * PC will be popped by the RTE instruction. */
- "POP R15 \n"\
+ /* Accumulator guard. */
+ "MVTACGU R15, A0 \n" \
+ "POP R15 \n" \
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A0 \n"\
- "POP R15 \n"\
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A1 \n" \
+ "POP R15 \n" \
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A0 \n"\
- "POP R15 \n"\
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A1 \n" \
+ "POP R15 \n" \
- /* Accumulator guard. */
- "MVTACGU R15, A0 \n"\
- "POP R15 \n"\
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A1 \n"\
- "POP R15 \n"\
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A1 \n"\
- "POP R15 \n"\
-
- /* Accumulator guard. */
- "MVTACGU R15, A1 \n"\
- "POP R15 \n"\
- "MVTC R15, FPSW \n"\
- "POPM R1-R15 \n"\
- "RTE \n"\
- "NOP \n"\
- "NOP "
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
- );
+ /* Accumulator guard. */
+ "MVTACGU R15, A1 \n" \
+ "POP R15 \n" \
+ "MVTC R15, FPSW \n" \
+ "POPM R1-R15 \n" \
+ "RTE \n" \
+ "NOP \n" \
+ "NOP "
+ :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+ );
}
/*-----------------------------------------------------------*/
void vTickISR( void )
{
- /* Re-enabled interrupts. */
- __asm volatile ( "SETPSW I");
+ /* Re-enabled interrupts. */
+ __asm volatile( "SETPSW I" );
- /* Increment the tick, and perform any processing the new tick value
- * necessitates. Ensure IPL is at the max syscall value first. */
- portMASK_INTERRUPTS_FROM_KERNEL_ISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. Ensure IPL is at the max syscall value first. */
+ portMASK_INTERRUPTS_FROM_KERNEL_ISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
}
/*-----------------------------------------------------------*/
uint32_t ulPortGetIPL( void )
{
- __asm volatile
- (
- "MVFC PSW, R1 \n"\
- "SHLR #24, R1 \n"\
- "RTS "
- );
+ __asm volatile
+ (
+ "MVFC PSW, R1 \n" \
+ "SHLR #24, R1 \n" \
+ "RTS "
+ );
- /* This will never get executed, but keeps the compiler from complaining. */
- return 0;
+ /* This will never get executed, but keeps the compiler from complaining. */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortSetIPL( uint32_t ulNewIPL )
{
- __asm volatile
- (
- "PUSH R5 \n"\
- "MVFC PSW, R5 \n"\
- "SHLL #24, R1 \n"\
- "AND #-0F000001H, R5 \n"\
- "OR R1, R5 \n"\
- "MVTC R5, PSW \n"\
- "POP R5 \n"\
- "RTS "
- );
+ __asm volatile
+ (
+ "PUSH R5 \n" \
+ "MVFC PSW, R5 \n" \
+ "SHLL #24, R1 \n" \
+ "AND #-0F000001H, R5 \n" \
+ "OR R1, R5 \n" \
+ "MVTC R5, PSW \n" \
+ "POP R5 \n" \
+ "RTS "
+ );
}
diff --git a/portable/GCC/RX600v2/portmacro.h b/portable/GCC/RX600v2/portmacro.h
index 46b88af..c6cb841 100644
--- a/portable/GCC/RX600v2/portmacro.h
+++ b/portable/GCC/RX600v2/portmacro.h
@@ -27,11 +27,11 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,94 +44,95 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() __asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __asm volatile( "NOP" )
/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
- * where portITU_SWINTR is the location of the software interrupt register
- * (0x000872E0). Don't rely on the assembler to select a register, so instead
- * save and restore clobbered registers manually. */
- #define portYIELD() \
- __asm volatile \
- ( \
- "PUSH.L R10 \n"\
- "MOV.L #0x872E0, R10 \n"\
- "MOV.B #0x1, [R10] \n"\
- "MOV.L [R10], R10 \n"\
- "POP R10 \n"\
- )
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0). Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD() \
+ __asm volatile \
+ ( \
+ "PUSH.L R10 \n" \
+ "MOV.L #0x872E0, R10 \n" \
+ "MOV.B #0x1, [R10] \n" \
+ "MOV.L [R10], R10 \n" \
+ "POP R10 \n" \
+ )
- #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
- * functions are those that end in FromISR. FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
- #define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0")
- #ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #else
- #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #endif
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+ #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
- uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) );
- void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/GCC/STR75x/port.c b/portable/GCC/STR75x/port.c
index e219669..dc27a14 100644
--- a/portable/GCC/STR75x/port.c
+++ b/portable/GCC/STR75x/port.c
@@ -26,9 +26,9 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ST STR75x ARM7
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the ST STR75x ARM7
+ * port.
+ *----------------------------------------------------------*/
/* Library includes. */
#include "75x_tb.h"
@@ -39,15 +39,15 @@
#include "task.h"
/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* Prescale used on the timer clock when calculating the tick period. */
-#define portPRESCALE 20
+#define portPRESCALE 20
/*-----------------------------------------------------------*/
@@ -63,130 +63,135 @@
*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The status register is set for system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* The status register is set for system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- #ifdef THUMB_INTERWORK
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
- #endif
+ #ifdef THUMB_INTERWORK
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+ #endif
- pxTopOfStack--;
+ pxTopOfStack--;
- /* Interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
+ /* Interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortISRStartFirstTask( void );
+extern void vPortISRStartFirstTask( void );
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortISRStartFirstTask();
+ /* Start the first task. */
+ vPortISRStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- EIC_IRQInitTypeDef EIC_IRQInitStructure;
- TB_InitTypeDef TB_InitStructure;
+EIC_IRQInitTypeDef EIC_IRQInitStructure;
+TB_InitTypeDef TB_InitStructure;
- /* Setup the EIC for the TB. */
- EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
- EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
- EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
- EIC_IRQInit( &EIC_IRQInitStructure );
+ /* Setup the EIC for the TB. */
+ EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
+ EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
+ EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
+ EIC_IRQInit(&EIC_IRQInitStructure);
+
+ /* Setup the TB for the generation of the tick interrupt. */
+ TB_InitStructure.TB_Mode = TB_Mode_Timing;
+ TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
+ TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
+ TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
+ TB_Init(&TB_InitStructure);
+
+ /* Enable TB Update interrupt */
+ TB_ITConfig(TB_IT_Update, ENABLE);
- /* Setup the TB for the generation of the tick interrupt. */
- TB_InitStructure.TB_Mode = TB_Mode_Timing;
- TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
- TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
- TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
- TB_Init( &TB_InitStructure );
+ /* Clear TB Update interrupt pending bit */
+ TB_ClearITPendingBit(TB_IT_Update);
- /* Enable TB Update interrupt */
- TB_ITConfig( TB_IT_Update, ENABLE );
-
- /* Clear TB Update interrupt pending bit */
- TB_ClearITPendingBit( TB_IT_Update );
-
- /* Enable TB */
- TB_Cmd( ENABLE );
+ /* Enable TB */
+ TB_Cmd(ENABLE);
}
/*-----------------------------------------------------------*/
+
+
+
+
+
+
+
diff --git a/portable/GCC/STR75x/portISR.c b/portable/GCC/STR75x/portISR.c
index 28e5738..5d29df8 100644
--- a/portable/GCC/STR75x/portISR.c
+++ b/portable/GCC/STR75x/portISR.c
@@ -27,26 +27,26 @@
/*-----------------------------------------------------------
-* Components that can be compiled to either ARM or THUMB mode are
-* contained in port.c The ISR routines, which can only be compiled
-* to ARM mode, are contained in this file.
-*----------------------------------------------------------*/
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
/*
- */
+*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
volatile uint32_t ulCriticalNesting = 9999UL;
/*-----------------------------------------------------------*/
-/*
+/*
* The scheduler can only be started from ARM mode, hence the inclusion of this
* function here.
*/
@@ -55,48 +55,48 @@
void vPortISRStartFirstTask( void )
{
- /* Simply start the scheduler. This is included here as it can only be
- * called from ARM mode. */
- asm volatile ( \
- "LDR R0, =pxCurrentTCB \n\t"\
- "LDR R0, [R0] \n\t"\
- "LDR LR, [R0] \n\t"\
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting \n\t"\
- "LDMFD LR!, {R1} \n\t"\
- "STR R1, [R0] \n\t"\
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0} \n\t"\
- "MSR SPSR, R0 \n\t"\
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^ \n\t"\
- "NOP \n\t"\
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60] \n\t"\
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4 \n\t"\
- );
+ /* Simply start the scheduler. This is included here as it can only be
+ called from ARM mode. */
+ asm volatile ( \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "LDR LR, [R0] \n\t" \
+ \
+ /* The critical nesting depth is the first item on the stack. */ \
+ /* Load it into the ulCriticalNesting variable. */ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDMFD LR!, {R1} \n\t" \
+ "STR R1, [R0] \n\t" \
+ \
+ /* Get the SPSR from the stack. */ \
+ "LDMFD LR!, {R0} \n\t" \
+ "MSR SPSR, R0 \n\t" \
+ \
+ /* Restore all system mode registers for the task. */ \
+ "LDMFD LR, {R0-R14}^ \n\t" \
+ "NOP \n\t" \
+ \
+ /* Restore the return address. */ \
+ "LDR LR, [LR, #+60] \n\t" \
+ \
+ /* And return - correcting the offset in the LR to obtain the */ \
+ /* correct address. */ \
+ "SUBS PC, LR, #4 \n\t" \
+ );
}
/*-----------------------------------------------------------*/
void vPortTickISR( void )
{
- /* Increment the RTOS tick count, then look for the highest priority
- * task that is ready to run. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Ready for the next interrupt. */
- TB_ClearITPendingBit( TB_IT_Update );
+ /* Increment the RTOS tick count, then look for the highest priority
+ task that is ready to run. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ /* Ready for the next interrupt. */
+ TB_ClearITPendingBit( TB_IT_Update );
}
/*-----------------------------------------------------------*/
@@ -109,69 +109,74 @@
*/
#ifdef THUMB_INTERWORK
- void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
- void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
- void vPortDisableInterruptsFromThumb( void )
- {
- asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0} \n\t"/* Pop R0. */
- "BX R14"); /* Return back to thumb. */
- }
-
- void vPortEnableInterruptsFromThumb( void )
- {
- asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0} \n\t"/* Pop R0. */
- "BX R14"); /* Return back to thumb. */
- }
+ void vPortDisableInterruptsFromThumb( void )
+ {
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+ void vPortEnableInterruptsFromThumb( void )
+ {
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
#endif /* THUMB_INTERWORK */
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0}"); /* Pop R0. */
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- asm volatile (
- "STMDB SP!, {R0} \n\t"/* Push R0. */
- "MRS R0, CPSR \n\t"/* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t"/* Write back modified value. */
- "LDMIA SP!, {R0}"); /* Pop R0. */
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+ }
+ }
}
+
+
+
+
+
diff --git a/portable/GCC/STR75x/portmacro.h b/portable/GCC/STR75x/portmacro.h
index adab88c..2bd6d43 100644
--- a/portable/GCC/STR75x/portmacro.h
+++ b/portable/GCC/STR75x/portmacro.h
@@ -27,11 +27,11 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,37 +44,36 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portYIELD() asm volatile ( "SWI 0" )
- #define portNOP() asm volatile ( "NOP" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portYIELD() asm volatile ( "SWI 0" )
+#define portNOP() asm volatile ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
-
/*
* The interrupt management utilities can only be called from ARM mode. When
* THUMB_INTERWORK is defined the utilities are defined as functions in
@@ -82,59 +81,61 @@
* defined then the utilities are defined as macros here - as per other ports.
*/
- #ifdef THUMB_INTERWORK
+#ifdef THUMB_INTERWORK
- extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
- extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
- #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
- #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
- #else
+#else
- #define portDISABLE_INTERRUPTS() \
- asm volatile ( \
- "STMDB SP!, {R0} \n\t"/* Push R0. */\
- "MRS R0, CPSR \n\t"/* Get CPSR. */\
- "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
- "MSR CPSR, R0 \n\t"/* Write back modified value. */\
- "LDMIA SP!, {R0} ") /* Pop R0. */
+ #define portDISABLE_INTERRUPTS() \
+ asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
- #define portENABLE_INTERRUPTS() \
- asm volatile ( \
- "STMDB SP!, {R0} \n\t"/* Push R0. */\
- "MRS R0, CPSR \n\t"/* Get CPSR. */\
- "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
- "MSR CPSR, R0 \n\t"/* Write back modified value. */\
- "LDMIA SP!, {R0} ") /* Pop R0. */
+ #define portENABLE_INTERRUPTS() \
+ asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
- #endif /* THUMB_INTERWORK */
+#endif /* THUMB_INTERWORK */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern void vTaskSwitchContext( void ); \
- \
- if( xSwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+{ \
+extern void vTaskSwitchContext( void ); \
+ \
+ if( xSwitchRequired ) \
+ { \
+ vTaskSwitchContext(); \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
+
diff --git a/portable/GCC/TriCore_1782/port.c b/portable/GCC/TriCore_1782/port.c
index fdc3ec9..c43cfa4 100644
--- a/portable/GCC/TriCore_1782/port.c
+++ b/portable/GCC/TriCore_1782/port.c
@@ -41,38 +41,38 @@
#include "list.h"
#if configCHECK_FOR_STACK_OVERFLOW > 0
- #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
- /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
+ #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
+ /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
#endif /* configCHECK_FOR_STACK_OVERFLOW */
/*-----------------------------------------------------------*/
/* System register Definitions. */
-#define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
-#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
-#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
-#define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
-#define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
+#define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
+#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
+#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
+#define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
+#define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
/* CSA manipulation macros. */
-#define portCSA_FCX_MASK ( 0x000FFFFFUL )
+#define portCSA_FCX_MASK ( 0x000FFFFFUL )
/* OS Interrupt and Trap mechanisms. */
-#define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
-#define portSYSCALL_TRAP ( 6 )
+#define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
+#define portSYSCALL_TRAP ( 6 )
/* Each CSA contains 16 words of data. */
-#define portNUM_WORDS_IN_CSA ( 16 )
+#define portNUM_WORDS_IN_CSA ( 16 )
/* The interrupt enable bit in the PCP_SRC register. */
-#define portENABLE_CPU_INTERRUPT ( 1U << 12U )
+#define portENABLE_CPU_INTERRUPT ( 1U << 12U )
/*-----------------------------------------------------------*/
/*
* Perform any hardware configuration necessary to generate the tick interrupt.
*/
-static void prvSystemTickHandler( int ) __attribute__( ( longcall ) );
+static void prvSystemTickHandler( int ) __attribute__((longcall));
static void prvSetupTimerInterrupt( void );
/*
@@ -88,278 +88,272 @@
/*-----------------------------------------------------------*/
/* This reference is required by the save/restore context macros. */
-extern volatile uint32_t * pxCurrentTCB;
+extern volatile uint32_t *pxCurrentTCB;
/* Precalculate the compare match value at compile time. */
static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
/*-----------------------------------------------------------*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint32_t * pulUpperCSA = NULL;
- uint32_t * pulLowerCSA = NULL;
+uint32_t *pulUpperCSA = NULL;
+uint32_t *pulLowerCSA = NULL;
- /* 16 Address Registers (4 Address registers are global), 16 Data
- * Registers, and 3 System Registers.
- *
- * There are 3 registers that track the CSAs.
- * FCX points to the head of globally free set of CSAs.
- * PCX for the task needs to point to Lower->Upper->NULL arrangement.
- * LCX points to the last free CSA so that corrective action can be taken.
- *
- * Need two CSAs to store the context of a task.
- * The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
- * The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
- * The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
- * The Lower Context points to the Upper Context ready for the return from the interrupt handler.
- *
- * The Real stack pointer for the task is stored in the A10 which is restored
- * with the upper context. */
+ /* 16 Address Registers (4 Address registers are global), 16 Data
+ Registers, and 3 System Registers.
- /* Have to disable interrupts here because the CSAs are going to be
- * manipulated. */
- portENTER_CRITICAL();
- {
- /* DSync to ensure that buffering is not a problem. */
- _dsync();
+ There are 3 registers that track the CSAs.
+ FCX points to the head of globally free set of CSAs.
+ PCX for the task needs to point to Lower->Upper->NULL arrangement.
+ LCX points to the last free CSA so that corrective action can be taken.
- /* Consume two free CSAs. */
- pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
+ Need two CSAs to store the context of a task.
+ The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
+ The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
+ The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
+ The Lower Context points to the Upper Context ready for the return from the interrupt handler.
- if( NULL != pulLowerCSA )
- {
- /* The Lower Links to the Upper. */
- pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
- }
+ The Real stack pointer for the task is stored in the A10 which is restored
+ with the upper context. */
- /* Check that we have successfully reserved two CSAs. */
- if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
- {
- /* Remove the two consumed CSAs from the free CSA list. */
- _disable();
- _dsync();
- _mtcr( $FCX, pulUpperCSA[ 0 ] );
- _isync();
- _enable();
- }
- else
- {
- /* Simply trigger a context list depletion trap. */
- _svlcx();
- }
- }
- portEXIT_CRITICAL();
+ /* Have to disable interrupts here because the CSAs are going to be
+ manipulated. */
+ portENTER_CRITICAL();
+ {
+ /* DSync to ensure that buffering is not a problem. */
+ _dsync();
- /* Clear the upper CSA. */
- memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
+ /* Consume two free CSAs. */
+ pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
+ if( NULL != pulLowerCSA )
+ {
+ /* The Lower Links to the Upper. */
+ pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
+ }
- /* Upper Context. */
- pulUpperCSA[ 2 ] = ( uint32_t ) pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
- pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
+ /* Check that we have successfully reserved two CSAs. */
+ if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
+ {
+ /* Remove the two consumed CSAs from the free CSA list. */
+ _disable();
+ _dsync();
+ _mtcr( $FCX, pulUpperCSA[ 0 ] );
+ _isync();
+ _enable();
+ }
+ else
+ {
+ /* Simply trigger a context list depletion trap. */
+ _svlcx();
+ }
+ }
+ portEXIT_CRITICAL();
- /* Clear the lower CSA. */
- memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
+ /* Clear the upper CSA. */
+ memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
- /* Lower Context. */
- pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */
- pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */
+ /* Upper Context. */
+ pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
+ pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
- /* PCXI pointing to the Upper context. */
- pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
+ /* Clear the lower CSA. */
+ memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
- /* Save the link to the CSA in the top of stack. */
- pxTopOfStack = ( uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
+ /* Lower Context. */
+ pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */
+ pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */
- /* DSync to ensure that buffering is not a problem. */
- _dsync();
+ /* PCXI pointing to the Upper context. */
+ pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
- return pxTopOfStack;
+ /* Save the link to the CSA in the top of stack. */
+ pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
+
+ /* DSync to ensure that buffering is not a problem. */
+ _dsync();
+
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
int32_t xPortStartScheduler( void )
{
- extern void vTrapInstallHandlers( void );
- uint32_t ulMFCR = 0UL;
- uint32_t * pulUpperCSA = NULL;
- uint32_t * pulLowerCSA = NULL;
+extern void vTrapInstallHandlers( void );
+uint32_t ulMFCR = 0UL;
+uint32_t *pulUpperCSA = NULL;
+uint32_t *pulLowerCSA = NULL;
- /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
- * when this function is called. */
+ /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
+ when this function is called. */
- /* Set-up the timer interrupt. */
- prvSetupTimerInterrupt();
+ /* Set-up the timer interrupt. */
+ prvSetupTimerInterrupt();
- /* Install the Trap Handlers. */
- vTrapInstallHandlers();
+ /* Install the Trap Handlers. */
+ vTrapInstallHandlers();
- /* Install the Syscall Handler for yield calls. */
- if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
- {
- /* Failed to install the yield handler, force an assert. */
- configASSERT( ( ( volatile void * ) NULL ) );
- }
+ /* Install the Syscall Handler for yield calls. */
+ if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
+ {
+ /* Failed to install the yield handler, force an assert. */
+ configASSERT( ( ( volatile void * ) NULL ) );
+ }
- /* Enable then install the priority 1 interrupt for pending context
- * switches from an ISR. See mod_SRC in the TriCore manual. */
- CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
+ /* Enable then install the priority 1 interrupt for pending context
+ switches from an ISR. See mod_SRC in the TriCore manual. */
+ CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
+ if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
+ {
+ /* Failed to install the yield handler, force an assert. */
+ configASSERT( ( ( volatile void * ) NULL ) );
+ }
- if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
- {
- /* Failed to install the yield handler, force an assert. */
- configASSERT( ( ( volatile void * ) NULL ) );
- }
+ _disable();
- _disable();
+ /* Load the initial SYSCON. */
+ _mtcr( $SYSCON, portINITIAL_SYSCON );
+ _isync();
- /* Load the initial SYSCON. */
- _mtcr( $SYSCON, portINITIAL_SYSCON );
- _isync();
+ /* ENDINIT has already been applied in the 'cstart.c' code. */
- /* ENDINIT has already been applied in the 'cstart.c' code. */
+ /* Clear the PSW.CDC to enable the use of an RFE without it generating an
+ exception because this code is not genuinely in an exception. */
+ ulMFCR = __MFCR( $PSW );
+ ulMFCR &= portRESTORE_PSW_MASK;
+ _dsync();
+ _mtcr( $PSW, ulMFCR );
+ _isync();
- /* Clear the PSW.CDC to enable the use of an RFE without it generating an
- * exception because this code is not genuinely in an exception. */
- ulMFCR = __MFCR( $PSW );
- ulMFCR &= portRESTORE_PSW_MASK;
- _dsync();
- _mtcr( $PSW, ulMFCR );
- _isync();
+ /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
+ pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
+ pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
+ _dsync();
+ _mtcr( $PCXI, *pxCurrentTCB );
+ _isync();
+ _nop();
+ _rslcx();
+ _nop();
- /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
- pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
- pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
- _dsync();
- _mtcr( $PCXI, *pxCurrentTCB );
- _isync();
- _nop();
- _rslcx();
- _nop();
+ /* Return to the first task selected to execute. */
+ __asm volatile( "rfe" );
- /* Return to the first task selected to execute. */
- __asm volatile ( "rfe" );
-
- /* Will not get here. */
- return 0;
+ /* Will not get here. */
+ return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- /* Set-up the clock divider. */
- unlock_wdtcon();
- {
- /* Wait until access to Endint protected register is enabled. */
- while( 0 != ( WDT_CON0.reg & 0x1UL ) )
- {
- }
+ /* Set-up the clock divider. */
+ unlock_wdtcon();
+ {
+ /* Wait until access to Endint protected register is enabled. */
+ while( 0 != ( WDT_CON0.reg & 0x1UL ) );
- /* RMC == 1 so STM Clock == FPI */
- STM_CLC.reg = ( 1UL << 8 );
- }
- lock_wdtcon();
+ /* RMC == 1 so STM Clock == FPI */
+ STM_CLC.reg = ( 1UL << 8 );
+ }
+ lock_wdtcon();
/* Determine how many bits are used without changing other bits in the CMCON register. */
- STM_CMCON.reg &= ~( 0x1fUL );
- STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
+ STM_CMCON.reg &= ~( 0x1fUL );
+ STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
- /* Take into account the current time so a tick doesn't happen immediately. */
- STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
+ /* Take into account the current time so a tick doesn't happen immediately. */
+ STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
- if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
- {
- /* Set-up the interrupt. */
- STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
+ if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
+ {
+ /* Set-up the interrupt. */
+ STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
- /* Enable the Interrupt. */
- STM_ISRR.reg &= ~( 0x03UL );
- STM_ISRR.reg |= 0x1UL;
- STM_ISRR.reg &= ~( 0x07UL );
- STM_ICR.reg |= 0x1UL;
- }
- else
- {
- /* Failed to install the Tick Interrupt. */
- configASSERT( ( ( volatile void * ) NULL ) );
- }
+ /* Enable the Interrupt. */
+ STM_ISRR.reg &= ~( 0x03UL );
+ STM_ISRR.reg |= 0x1UL;
+ STM_ISRR.reg &= ~( 0x07UL );
+ STM_ICR.reg |= 0x1UL;
+ }
+ else
+ {
+ /* Failed to install the Tick Interrupt. */
+ configASSERT( ( ( volatile void * ) NULL ) );
+ }
}
/*-----------------------------------------------------------*/
static void prvSystemTickHandler( int iArg )
{
- uint32_t ulSavedInterruptMask;
- uint32_t * pxUpperCSA = NULL;
- uint32_t xUpperCSA = 0UL;
- extern volatile uint32_t * pxCurrentTCB;
- int32_t lYieldRequired;
+uint32_t ulSavedInterruptMask;
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+int32_t lYieldRequired;
- /* Just to avoid compiler warnings about unused parameters. */
- ( void ) iArg;
+ /* Just to avoid compiler warnings about unused parameters. */
+ ( void ) iArg;
- /* Clear the interrupt source. */
- STM_ISRR.reg = 1UL;
+ /* Clear the interrupt source. */
+ STM_ISRR.reg = 1UL;
- /* Reload the Compare Match register for X ticks into the future.
- *
- * If critical section or interrupt nesting budgets are exceeded, then
- * it is possible that the calculated next compare match value is in the
- * past. If this occurs (unlikely), it is possible that the resulting
- * time slippage will exceed a single tick period. Any adverse effect of
- * this is time bounded by the fact that only the first n bits of the 56 bit
- * STM timer are being used for a compare match, so another compare match
- * will occur after an overflow in just those n bits (not the entire 56 bits).
- * As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
- * a missed tick could result in the next tick interrupt occurring within a
- * time that is 1.7 times the desired period. The fact that this is greater
- * than a single tick period is an effect of using a timer that cannot be
- * automatically reset, in hardware, by the occurrence of a tick interrupt.
- * Changing the tick source to a timer that has an automatic reset on compare
- * match (such as a GPTA timer) will reduce the maximum possible additional
- * period to exactly 1 times the desired period. */
- STM_CMP0.reg += ulCompareMatchValue;
+ /* Reload the Compare Match register for X ticks into the future.
- /* Kernel API calls require Critical Sections. */
- ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- /* Increment the Tick. */
- lYieldRequired = xTaskIncrementTick();
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+ If critical section or interrupt nesting budgets are exceeded, then
+ it is possible that the calculated next compare match value is in the
+ past. If this occurs (unlikely), it is possible that the resulting
+ time slippage will exceed a single tick period. Any adverse effect of
+ this is time bounded by the fact that only the first n bits of the 56 bit
+ STM timer are being used for a compare match, so another compare match
+ will occur after an overflow in just those n bits (not the entire 56 bits).
+ As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
+ a missed tick could result in the next tick interrupt occurring within a
+ time that is 1.7 times the desired period. The fact that this is greater
+ than a single tick period is an effect of using a timer that cannot be
+ automatically reset, in hardware, by the occurrence of a tick interrupt.
+ Changing the tick source to a timer that has an automatic reset on compare
+ match (such as a GPTA timer) will reduce the maximum possible additional
+ period to exactly 1 times the desired period. */
+ STM_CMP0.reg += ulCompareMatchValue;
- if( lYieldRequired != pdFALSE )
- {
- /* Save the context of a task.
- * The upper context is automatically saved when entering a trap or interrupt.
- * Need to save the lower context as well and copy the PCXI CSA ID into
- * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
- * TCB of a task.
- *
- * Call vTaskSwitchContext to select the next task, note that this changes the
- * value of pxCurrentTCB so that it needs to be reloaded.
- *
- * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
- * that has just been switched in.
- *
- * Load the context of the task.
- * Need to restore the lower context by loading the CSA from
- * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
- * In the Interrupt handler post-amble, RSLCX will restore the lower context
- * of the task. RFE will restore the upper context of the task, jump to the
- * return address and restore the previous state of interrupts being
- * enabled/disabled. */
- _disable();
- _dsync();
- xUpperCSA = __MFCR( $PCXI );
- pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
- *pxCurrentTCB = pxUpperCSA[ 0 ];
- vTaskSwitchContext();
- pxUpperCSA[ 0 ] = *pxCurrentTCB;
- CPU_SRC0.bits.SETR = 0;
- _isync();
- }
+ /* Kernel API calls require Critical Sections. */
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the Tick. */
+ lYieldRequired = xTaskIncrementTick();
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+
+ if( lYieldRequired != pdFALSE )
+ {
+ /* Save the context of a task.
+ The upper context is automatically saved when entering a trap or interrupt.
+ Need to save the lower context as well and copy the PCXI CSA ID into
+ pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+ TCB of a task.
+
+ Call vTaskSwitchContext to select the next task, note that this changes the
+ value of pxCurrentTCB so that it needs to be reloaded.
+
+ Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+ that has just been switched in.
+
+ Load the context of the task.
+ Need to restore the lower context by loading the CSA from
+ pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+ In the Interrupt handler post-amble, RSLCX will restore the lower context
+ of the task. RFE will restore the upper context of the task, jump to the
+ return address and restore the previous state of interrupts being
+ enabled/disabled. */
+ _disable();
+ _dsync();
+ xUpperCSA = __MFCR( $PCXI );
+ pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+ *pxCurrentTCB = pxUpperCSA[ 0 ];
+ vTaskSwitchContext();
+ pxUpperCSA[ 0 ] = *pxCurrentTCB;
+ CPU_SRC0.bits.SETR = 0;
+ _isync();
+ }
}
/*-----------------------------------------------------------*/
@@ -381,166 +375,167 @@
* than they can be freed assuming that tasks are being spawned and
* deleted frequently.
*/
-void vPortReclaimCSA( uint32_t * pxTCB )
+void vPortReclaimCSA( uint32_t *pxTCB )
{
- uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
- uint32_t * pulNextCSA;
+uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
+uint32_t *pulNextCSA;
- /* A pointer to the first CSA in the list of CSAs consumed by the task is
- * stored in the first element of the tasks TCB structure (where the stack
- * pointer would be on a traditional stack based architecture). */
- pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
+ /* A pointer to the first CSA in the list of CSAs consumed by the task is
+ stored in the first element of the tasks TCB structure (where the stack
+ pointer would be on a traditional stack based architecture). */
+ pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
- /* Mask off everything in the CSA link field other than the address. If
- * the address is NULL, then the CSA is not linking anywhere and there is
- * nothing to do. */
- pxTailCSA = pxHeadCSA;
+ /* Mask off everything in the CSA link field other than the address. If
+ the address is NULL, then the CSA is not linking anywhere and there is
+ nothing to do. */
+ pxTailCSA = pxHeadCSA;
- /* Convert the link value to contain just a raw address and store this
- * in a local variable. */
- pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
+ /* Convert the link value to contain just a raw address and store this
+ in a local variable. */
+ pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
- /* Iterate over the CSAs that were consumed as part of the task. The
- * first field in the CSA is the pointer to then next CSA. Mask off
- * everything in the pointer to the next CSA, other than the link address.
- * If this is NULL, then the CSA currently being pointed to is the last in
- * the chain. */
- while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
- {
- /* Clear all bits of the pointer to the next in the chain, other
- * than the address bits themselves. */
- pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
+ /* Iterate over the CSAs that were consumed as part of the task. The
+ first field in the CSA is the pointer to then next CSA. Mask off
+ everything in the pointer to the next CSA, other than the link address.
+ If this is NULL, then the CSA currently being pointed to is the last in
+ the chain. */
+ while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
+ {
+ /* Clear all bits of the pointer to the next in the chain, other
+ than the address bits themselves. */
+ pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
- /* Move the pointer to point to the next CSA in the list. */
- pxTailCSA = pulNextCSA[ 0 ];
+ /* Move the pointer to point to the next CSA in the list. */
+ pxTailCSA = pulNextCSA[ 0 ];
- /* Update the local pointer to the CSA. */
- pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
- }
+ /* Update the local pointer to the CSA. */
+ pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
+ }
- _disable();
- {
- /* Look up the current free CSA head. */
- _dsync();
- pxFreeCSA = __MFCR( $FCX );
+ _disable();
+ {
+ /* Look up the current free CSA head. */
+ _dsync();
+ pxFreeCSA = __MFCR( $FCX );
- /* Join the current Free onto the Tail of what is being reclaimed. */
- portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
+ /* Join the current Free onto the Tail of what is being reclaimed. */
+ portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
- /* Move the head of the reclaimed into the Free. */
- _dsync();
- _mtcr( $FCX, pxHeadCSA );
- _isync();
- }
- _enable();
+ /* Move the head of the reclaimed into the Free. */
+ _dsync();
+ _mtcr( $FCX, pxHeadCSA );
+ _isync();
+ }
+ _enable();
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Nothing to do. Unlikely to want to end. */
+ /* Nothing to do. Unlikely to want to end. */
}
/*-----------------------------------------------------------*/
static void prvTrapYield( int iTrapIdentification )
{
- uint32_t * pxUpperCSA = NULL;
- uint32_t xUpperCSA = 0UL;
- extern volatile uint32_t * pxCurrentTCB;
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
- switch( iTrapIdentification )
- {
- case portSYSCALL_TASK_YIELD:
+ switch( iTrapIdentification )
+ {
+ case portSYSCALL_TASK_YIELD:
+ /* Save the context of a task.
+ The upper context is automatically saved when entering a trap or interrupt.
+ Need to save the lower context as well and copy the PCXI CSA ID into
+ pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+ TCB of a task.
- /* Save the context of a task.
- * The upper context is automatically saved when entering a trap or interrupt.
- * Need to save the lower context as well and copy the PCXI CSA ID into
- * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
- * TCB of a task.
- *
- * Call vTaskSwitchContext to select the next task, note that this changes the
- * value of pxCurrentTCB so that it needs to be reloaded.
- *
- * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
- * that has just been switched in.
- *
- * Load the context of the task.
- * Need to restore the lower context by loading the CSA from
- * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
- * In the Interrupt handler post-amble, RSLCX will restore the lower context
- * of the task. RFE will restore the upper context of the task, jump to the
- * return address and restore the previous state of interrupts being
- * enabled/disabled. */
- _disable();
- _dsync();
- xUpperCSA = __MFCR( $PCXI );
- pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
- *pxCurrentTCB = pxUpperCSA[ 0 ];
- vTaskSwitchContext();
- pxUpperCSA[ 0 ] = *pxCurrentTCB;
- CPU_SRC0.bits.SETR = 0;
- _isync();
- break;
+ Call vTaskSwitchContext to select the next task, note that this changes the
+ value of pxCurrentTCB so that it needs to be reloaded.
- default:
- /* Unimplemented trap called. */
- configASSERT( ( ( volatile void * ) NULL ) );
- break;
- }
+ Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+ that has just been switched in.
+
+ Load the context of the task.
+ Need to restore the lower context by loading the CSA from
+ pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+ In the Interrupt handler post-amble, RSLCX will restore the lower context
+ of the task. RFE will restore the upper context of the task, jump to the
+ return address and restore the previous state of interrupts being
+ enabled/disabled. */
+ _disable();
+ _dsync();
+ xUpperCSA = __MFCR( $PCXI );
+ pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+ *pxCurrentTCB = pxUpperCSA[ 0 ];
+ vTaskSwitchContext();
+ pxUpperCSA[ 0 ] = *pxCurrentTCB;
+ CPU_SRC0.bits.SETR = 0;
+ _isync();
+ break;
+
+ default:
+ /* Unimplemented trap called. */
+ configASSERT( ( ( volatile void * ) NULL ) );
+ break;
+ }
}
/*-----------------------------------------------------------*/
static void prvInterruptYield( int iId )
{
- uint32_t * pxUpperCSA = NULL;
- uint32_t xUpperCSA = 0UL;
- extern volatile uint32_t * pxCurrentTCB;
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
- /* Just to remove compiler warnings. */
- ( void ) iId;
+ /* Just to remove compiler warnings. */
+ ( void ) iId;
- /* Save the context of a task.
- * The upper context is automatically saved when entering a trap or interrupt.
- * Need to save the lower context as well and copy the PCXI CSA ID into
- * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
- * TCB of a task.
- *
- * Call vTaskSwitchContext to select the next task, note that this changes the
- * value of pxCurrentTCB so that it needs to be reloaded.
- *
- * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
- * that has just been switched in.
- *
- * Load the context of the task.
- * Need to restore the lower context by loading the CSA from
- * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
- * In the Interrupt handler post-amble, RSLCX will restore the lower context
- * of the task. RFE will restore the upper context of the task, jump to the
- * return address and restore the previous state of interrupts being
- * enabled/disabled. */
- _disable();
- _dsync();
- xUpperCSA = __MFCR( $PCXI );
- pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
- *pxCurrentTCB = pxUpperCSA[ 0 ];
- vTaskSwitchContext();
- pxUpperCSA[ 0 ] = *pxCurrentTCB;
- CPU_SRC0.bits.SETR = 0;
- _isync();
+ /* Save the context of a task.
+ The upper context is automatically saved when entering a trap or interrupt.
+ Need to save the lower context as well and copy the PCXI CSA ID into
+ pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+ TCB of a task.
+
+ Call vTaskSwitchContext to select the next task, note that this changes the
+ value of pxCurrentTCB so that it needs to be reloaded.
+
+ Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+ that has just been switched in.
+
+ Load the context of the task.
+ Need to restore the lower context by loading the CSA from
+ pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+ In the Interrupt handler post-amble, RSLCX will restore the lower context
+ of the task. RFE will restore the upper context of the task, jump to the
+ return address and restore the previous state of interrupts being
+ enabled/disabled. */
+ _disable();
+ _dsync();
+ xUpperCSA = __MFCR( $PCXI );
+ pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+ *pxCurrentTCB = pxUpperCSA[ 0 ];
+ vTaskSwitchContext();
+ pxUpperCSA[ 0 ] = *pxCurrentTCB;
+ CPU_SRC0.bits.SETR = 0;
+ _isync();
}
/*-----------------------------------------------------------*/
uint32_t uxPortSetInterruptMaskFromISR( void )
{
- uint32_t uxReturn = 0UL;
+uint32_t uxReturn = 0UL;
- _disable();
- uxReturn = __MFCR( $ICR );
- _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
- _isync();
- _enable();
+ _disable();
+ uxReturn = __MFCR( $ICR );
+ _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+ _isync();
+ _enable();
- /* Return just the interrupt mask bits. */
- return( uxReturn & portCCPN_MASK );
+ /* Return just the interrupt mask bits. */
+ return ( uxReturn & portCCPN_MASK );
}
/*-----------------------------------------------------------*/
+
+
diff --git a/portable/GCC/TriCore_1782/portmacro.h b/portable/GCC/TriCore_1782/portmacro.h
index 4feea70..2e2a483 100644
--- a/portable/GCC/TriCore_1782/portmacro.h
+++ b/portable/GCC/TriCore_1782/portmacro.h
@@ -26,15 +26,15 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* System Includes. */
- #include <tc1782.h>
- #include <machine/intrinsics.h>
+#include <tc1782.h>
+#include <machine/intrinsics.h>
/*-----------------------------------------------------------
* Port specific definitions.
@@ -47,130 +47,127 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*---------------------------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 4
- #define portNOP() __asm volatile ( " nop " )
- #define portCRITICAL_NESTING_IN_TCB 1
- #define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() __asm volatile( " nop " )
+#define portCRITICAL_NESTING_IN_TCB 1
+#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1
/*---------------------------------------------------------------------------*/
- typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
/* Define away the instruction from the Restore Context Macro. */
- #define portPRIVILEGE_BIT 0x0UL
+#define portPRIVILEGE_BIT 0x0UL
- #define portCCPN_MASK ( 0x000000FFUL )
+#define portCCPN_MASK ( 0x000000FFUL )
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/*---------------------------------------------------------------------------*/
/* CSA Manipulation. */
- #define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * ) ( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
- #define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t ) ( ( ( ( ( uint32_t ) ( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t ) ( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
+#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
+#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
/*---------------------------------------------------------------------------*/
- #define portYIELD() _syscall( 0 )
+#define portYIELD() _syscall( 0 )
/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
- #define portSYSCALL_TASK_YIELD 0
- #define portSYSCALL_RAISE_PRIORITY 1
+#define portSYSCALL_TASK_YIELD 0
+#define portSYSCALL_RAISE_PRIORITY 1
/*---------------------------------------------------------------------------*/
/* Critical section management. */
/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- #define portDISABLE_INTERRUPTS() \
- { \
- uint32_t ulICR; \
- _disable(); \
- ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
- ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
- ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
- _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
- _isync(); \
- _enable(); \
- }
+#define portDISABLE_INTERRUPTS() { \
+ uint32_t ulICR; \
+ _disable(); \
+ ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
+ ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
+ ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
+ _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
+ _isync(); \
+ _enable(); \
+ }
/* Clear ICR.CCPN to allow all interrupt priorities. */
- #define portENABLE_INTERRUPTS() \
- { \
- uint32_t ulICR; \
- _disable(); \
- ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
- ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
- _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
- _isync(); \
- _enable(); \
- }
+#define portENABLE_INTERRUPTS() { \
+ uint32_t ulICR; \
+ _disable(); \
+ ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
+ ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
+ _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
+ _isync(); \
+ _enable(); \
+ }
/* Set ICR.CCPN to uxSavedMaskValue. */
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) \
- { \
- uint32_t ulICR; \
- _disable(); \
- ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
- ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
- ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
- _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
- _isync(); \
- _enable(); \
- }
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) { \
+ uint32_t ulICR; \
+ _disable(); \
+ ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
+ ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
+ ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
+ _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
+ _isync(); \
+ _enable(); \
+ }
/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
- extern uint32_t uxPortSetInterruptMaskFromISR( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+extern uint32_t uxPortSetInterruptMaskFromISR( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
/* Pend a priority 1 interrupt, which will take care of the context switch. */
- #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); }
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); }
/*---------------------------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*---------------------------------------------------------------------------*/
/*
* Port specific clean up macro required to free the CSAs that were consumed by
* a task that has since been deleted.
*/
- void vPortReclaimCSA( uint32_t * pxTCB );
- #define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
+void vPortReclaimCSA( uint32_t *pxTCB );
+#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
diff --git a/portable/GCC/TriCore_1782/porttrap.c b/portable/GCC/TriCore_1782/porttrap.c
index 94e5eae..039321b 100644
--- a/portable/GCC/TriCore_1782/porttrap.c
+++ b/portable/GCC/TriCore_1782/porttrap.c
@@ -37,7 +37,7 @@
/*
* This reference is required by the Save/Restore Context Macros.
*/
-extern volatile uint32_t * pxCurrentTCB;
+extern volatile uint32_t *pxCurrentTCB;
/*-----------------------------------------------------------*/
/*
@@ -50,57 +50,57 @@
*/
/* The Trap Classes. */
-#define portMMU_TRAP 0
-#define portIPT_TRAP 1
-#define portIE_TRAP 2
-#define portCM_TRAP 3
-#define portSBP_TRAP 4
-#define portASSERT_TRAP 5
-#define portNMI_TRAP 7
+#define portMMU_TRAP 0
+#define portIPT_TRAP 1
+#define portIE_TRAP 2
+#define portCM_TRAP 3
+#define portSBP_TRAP 4
+#define portASSERT_TRAP 5
+#define portNMI_TRAP 7
/* MMU Trap Identifications. */
-#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0
-#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1
+#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0
+#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1
/* Internal Protection Trap Identifications. */
-#define portTIN_IPT_PRIVILIGED_INSTRUCTION 1
-#define portTIN_IPT_MEMORY_PROTECTION_READ 2
-#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3
-#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4
-#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
-#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6
-#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7
+#define portTIN_IPT_PRIVILIGED_INSTRUCTION 1
+#define portTIN_IPT_MEMORY_PROTECTION_READ 2
+#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3
+#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4
+#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
+#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6
+#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7
/* Instruction Error Trap Identifications. */
-#define portTIN_IE_ILLEGAL_OPCODE 1
-#define portTIN_IE_UNIMPLEMENTED_OPCODE 2
-#define portTIN_IE_INVALID_OPERAND 3
-#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4
-#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
+#define portTIN_IE_ILLEGAL_OPCODE 1
+#define portTIN_IE_UNIMPLEMENTED_OPCODE 2
+#define portTIN_IE_INVALID_OPERAND 3
+#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4
+#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
/* Context Management Trap Identifications. */
-#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1
-#define portTIN_CM_CALL_DEPTH_OVERFLOW 2
-#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3
-#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4
-#define portTIN_CM_CALL_STACK_UNDERFLOW 5
-#define portTIN_CM_CONTEXT_TYPE 6
-#define portTIN_CM_NESTING_ERROR 7
+#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1
+#define portTIN_CM_CALL_DEPTH_OVERFLOW 2
+#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3
+#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4
+#define portTIN_CM_CALL_STACK_UNDERFLOW 5
+#define portTIN_CM_CONTEXT_TYPE 6
+#define portTIN_CM_NESTING_ERROR 7
/* System Bus and Peripherals Trap Identifications. */
-#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1
-#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2
-#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3
-#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4
-#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
-#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6
+#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1
+#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2
+#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3
+#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4
+#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
+#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6
/* Assertion Trap Identifications. */
-#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1
-#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2
+#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1
+#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2
/* Non-maskable Interrupt Trap Identifications. */
-#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0
+#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0
/*---------------------------------------------------------------------------*/
void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
@@ -114,168 +114,168 @@
void vTrapInstallHandlers( void )
{
- if( 0 == _install_trap_handler( portMMU_TRAP, vMMUTrap ) )
- {
- _debug();
- }
+ if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
+ {
+ _debug();
+ }
- if( 0 == _install_trap_handler( portIPT_TRAP, vInternalProtectionTrap ) )
- {
- _debug();
- }
+ if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
+ {
+ _debug();
+ }
- if( 0 == _install_trap_handler( portIE_TRAP, vInstructionErrorTrap ) )
- {
- _debug();
- }
+ if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
+ {
+ _debug();
+ }
- if( 0 == _install_trap_handler( portCM_TRAP, vContextManagementTrap ) )
- {
- _debug();
- }
+ if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
+ {
+ _debug();
+ }
- if( 0 == _install_trap_handler( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
- {
- _debug();
- }
+ if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
+ {
+ _debug();
+ }
- if( 0 == _install_trap_handler( portASSERT_TRAP, vAssertionTrap ) )
- {
- _debug();
- }
+ if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
+ {
+ _debug();
+ }
- if( 0 == _install_trap_handler( portNMI_TRAP, vNonMaskableInterruptTrap ) )
- {
- _debug();
- }
+ if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
+ {
+ _debug();
+ }
}
/*-----------------------------------------------------------*/
void vMMUTrap( int iTrapIdentification )
{
- switch( iTrapIdentification )
- {
- case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
- case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
- default:
- _debug();
- break;
- }
+ switch( iTrapIdentification )
+ {
+ case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
+ case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
+ default:
+ _debug();
+ break;
+ }
}
/*---------------------------------------------------------------------------*/
void vInternalProtectionTrap( int iTrapIdentification )
{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_IPT_PRIVILIGED_INSTRUCTION:
- /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_IPT_PRIVILIGED_INSTRUCTION:
+ /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
- case portTIN_IPT_MEMORY_PROTECTION_READ:
- /* Load word using invalid address. */
-
- case portTIN_IPT_MEMORY_PROTECTION_WRITE:
- /* Store Word using invalid address. */
-
- case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
- /* PC jumped to an address outside of the valid range. */
-
- case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
- /* Access to a peripheral denied at current execution level. */
-
- case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
- /* NULL Pointer. */
-
- case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
- /* Tried to modify a global address pointer register. */
-
- default:
-
- pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
- _debug();
- break;
- }
+ case portTIN_IPT_MEMORY_PROTECTION_READ:
+ /* Load word using invalid address. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_WRITE:
+ /* Store Word using invalid address. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
+ /* PC jumped to an address outside of the valid range. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
+ /* Access to a peripheral denied at current execution level. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
+ /* NULL Pointer. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
+ /* Tried to modify a global address pointer register. */
+
+ default:
+
+ pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
+ _debug();
+ break;
+ }
}
/*---------------------------------------------------------------------------*/
void vInstructionErrorTrap( int iTrapIdentification )
{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_IE_ILLEGAL_OPCODE:
- case portTIN_IE_UNIMPLEMENTED_OPCODE:
- case portTIN_IE_INVALID_OPERAND:
- case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
- case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
- default:
- _debug();
- break;
- }
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_IE_ILLEGAL_OPCODE:
+ case portTIN_IE_UNIMPLEMENTED_OPCODE:
+ case portTIN_IE_INVALID_OPERAND:
+ case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
+ case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
+ default:
+ _debug();
+ break;
+ }
}
/*---------------------------------------------------------------------------*/
void vContextManagementTrap( int iTrapIdentification )
{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
- case portTIN_CM_CALL_DEPTH_OVERFLOW:
- case portTIN_CM_CALL_DEPTH_UNDEFLOW:
- case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
- case portTIN_CM_CALL_STACK_UNDERFLOW:
- case portTIN_CM_CONTEXT_TYPE:
- case portTIN_CM_NESTING_ERROR:
- default:
- _debug();
- break;
- }
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
+ case portTIN_CM_CALL_DEPTH_OVERFLOW:
+ case portTIN_CM_CALL_DEPTH_UNDEFLOW:
+ case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
+ case portTIN_CM_CALL_STACK_UNDERFLOW:
+ case portTIN_CM_CONTEXT_TYPE:
+ case portTIN_CM_NESTING_ERROR:
+ default:
+ _debug();
+ break;
+ }
}
/*---------------------------------------------------------------------------*/
void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
- case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
- case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
- case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
- case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
- case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
- default:
- _debug();
- break;
- }
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
+ case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
+ case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
+ case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
+ case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
+ case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
+ default:
+ _debug();
+ break;
+ }
}
/*---------------------------------------------------------------------------*/
void vAssertionTrap( int iTrapIdentification )
{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
- case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
- default:
- _debug();
- break;
- }
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
+ case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
+ default:
+ _debug();
+ break;
+ }
}
/*---------------------------------------------------------------------------*/
void vNonMaskableInterruptTrap( int iTrapIdentification )
{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_NMI_NON_MASKABLE_INTERRUPT:
- default:
- _debug();
- break;
- }
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_NMI_NON_MASKABLE_INTERRUPT:
+ default:
+ _debug();
+ break;
+ }
}
/*---------------------------------------------------------------------------*/
diff --git a/portable/IAR/78K0R/ISR_Support.h b/portable/IAR/78K0R/ISR_Support.h
index 38f45d6..4e39841 100644
--- a/portable/IAR/78K0R/ISR_Support.h
+++ b/portable/IAR/78K0R/ISR_Support.h
@@ -1,111 +1,82 @@
-; /*
- * ; * FreeRTOS Kernel V10.3.1
- * ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * ; *
- * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * ; * this software and associated documentation files (the "Software"), to deal in
- * ; * the Software without restriction, including without limitation the rights to
- * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * ; * the Software, and to permit persons to whom the Software is furnished to do so,
- * ; * subject to the following conditions:
- * ; *
- * ; * The above copyright notice and this permission notice shall be included in all
- * ; * copies or substantial portions of the Software.
- * ; *
- * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * ; *
- * ; * http://www.FreeRTOS.org
- * ; * http://aws.amazon.com/freertos
- * ; *
- * ; * 1 tab == 4 spaces!
- * ; */
+;/*
+; * FreeRTOS Kernel V10.3.1
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
#include "FreeRTOSConfig.h"
-;
-Variables used by scheduler
-;
-------------------------------------------------------------------------------
-EXTERN pxCurrentTCB
-EXTERN usCriticalNesting
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+ EXTERN pxCurrentTCB
+ EXTERN usCriticalNesting
-;
-------------------------------------------------------------------------------
-;
-portSAVE_CONTEXT MACRO
-;
-Saves the context of the general purpose registers, CS and ES( only in far
- ;
- memory mode ) registers the usCriticalNesting Value and the Stack Pointer
-;
-of the active Task onto the task stack
-;
-------------------------------------------------------------------------------
+;------------------------------------------------------------------------------
+; portSAVE_CONTEXT MACRO
+; Saves the context of the general purpose registers, CS and ES (only in far
+; memory mode) registers the usCriticalNesting Value and the Stack Pointer
+; of the active Task onto the task stack
+;------------------------------------------------------------------------------
portSAVE_CONTEXT MACRO
-PUSH AX;
-Save AX Register to stack.
- PUSH HL
-MOV A, CS;
-Save CS register.
- XCH A, X
-MOV A, ES;
-Save ES register.
- PUSH AX
-PUSH DE;
-Save the remaining general purpose registers.
- PUSH BC
-MOVW AX, usCriticalNesting;
-Save the usCriticalNesting value.
- PUSH AX
-MOVW AX, pxCurrentTCB;
-Save the Stack pointer.
- MOVW HL, AX
-MOVW AX, SP
- MOVW[ HL ], AX
- ENDM
-;
-------------------------------------------------------------------------------
+ PUSH AX ; Save AX Register to stack.
+ PUSH HL
+ MOV A, CS ; Save CS register.
+ XCH A, X
+ MOV A, ES ; Save ES register.
+ PUSH AX
+ PUSH DE ; Save the remaining general purpose registers.
+ PUSH BC
+ MOVW AX, usCriticalNesting ; Save the usCriticalNesting value.
+ PUSH AX
+ MOVW AX, pxCurrentTCB ; Save the Stack pointer.
+ MOVW HL, AX
+ MOVW AX, SP
+ MOVW [HL], AX
+ ENDM
+;------------------------------------------------------------------------------
-;
-------------------------------------------------------------------------------
-;
+;------------------------------------------------------------------------------
+; portRESTORE_CONTEXT MACRO
+; Restores the task Stack Pointer then use this to restore usCriticalNesting,
+; general purpose registers and the CS and ES (only in far memory mode)
+; of the selected task from the task stack
+;------------------------------------------------------------------------------
portRESTORE_CONTEXT MACRO
-;
-Restores the task Stack Pointer then use this to restore usCriticalNesting,
-;
-general purpose registers and the CS and ES( only in far memory mode )
-;
-of the selected task from the task stack
-;
-------------------------------------------------------------------------------
-portRESTORE_CONTEXT MACRO
-MOVW AX, pxCurrentTCB;
-Restore the Stack pointer.
- MOVW HL, AX
-MOVW AX, [ HL ]
-MOVW SP, AX
-POP AX;
-Restore usCriticalNesting value.
- MOVW usCriticalNesting, AX
-POP BC;
-Restore the necessary general purpose registers.
- POP DE
-POP AX;
-Restore the ES register.
- MOV ES, A
-XCH A, X;
-Restore the CS register.
- MOV CS, A
-POP HL;
-Restore general purpose register HL.
- POP AX;
-Restore AX.
- ENDM
-;
-------------------------------------------------------------------------------
+ MOVW AX, pxCurrentTCB ; Restore the Stack pointer.
+ MOVW HL, AX
+ MOVW AX, [HL]
+ MOVW SP, AX
+ POP AX ; Restore usCriticalNesting value.
+ MOVW usCriticalNesting, AX
+ POP BC ; Restore the necessary general purpose registers.
+ POP DE
+ POP AX ; Restore the ES register.
+ MOV ES, A
+ XCH A, X ; Restore the CS register.
+ MOV CS, A
+ POP HL ; Restore general purpose register HL.
+ POP AX ; Restore AX.
+ ENDM
+;------------------------------------------------------------------------------
diff --git a/portable/IAR/78K0R/port.c b/portable/IAR/78K0R/port.c
index 50d454d..4fb2047 100644
--- a/portable/IAR/78K0R/port.c
+++ b/portable/IAR/78K0R/port.c
@@ -33,8 +33,8 @@
#include "task.h"
/* The critical nesting value is initialised to a non zero value to ensure
- * interrupts don't accidentally become enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
+interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING (( uint16_t ) 10)
/* Initial PSW value allocated to a newly created task.
* 1100011000000000
@@ -47,25 +47,25 @@
* |--------------------- Zero Flag set
* ---------------------- Global Interrupt Flag set (enabled)
*/
-#define portPSW ( 0xc6UL )
+#define portPSW (0xc6UL)
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/* Most ports implement critical sections by placing the interrupt flags on
- * the stack before disabling interrupts. Exiting the critical section is then
- * simply a case of popping the flags from the stack. As 78K0 IAR does not use
- * a frame pointer this cannot be done as modifying the stack will clobber all
- * the stack variables. Instead each task maintains a count of the critical
- * section nesting depth. Each time a critical section is entered the count is
- * incremented. Each time a critical section is left the count is decremented -
- * with interrupts only being re-enabled if the count is zero.
- *
- * usCriticalNesting will get set to zero when the scheduler starts, but must
- * not be initialised to zero as this will cause problems during the startup
- * sequence. */
+the stack before disabling interrupts. Exiting the critical section is then
+simply a case of popping the flags from the stack. As 78K0 IAR does not use
+a frame pointer this cannot be done as modifying the stack will clobber all
+the stack variables. Instead each task maintains a count of the critical
+section nesting depth. Each time a critical section is entered the count is
+incremented. Each time a critical section is left the count is decremented -
+with interrupts only being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@@ -81,146 +81,145 @@
*
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint32_t * pulLocal;
+uint32_t *pulLocal;
- #if configMEMORY_MODE == 1
- {
- /* Parameters are passed in on the stack, and written using a 32bit value
- * hence a space is left for the second two bytes. */
- pxTopOfStack--;
+ #if configMEMORY_MODE == 1
+ {
+ /* Parameters are passed in on the stack, and written using a 32bit value
+ hence a space is left for the second two bytes. */
+ pxTopOfStack--;
- /* Write in the parameter value. */
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( uint32_t ) pvParameters;
- pxTopOfStack--;
+ /* Write in the parameter value. */
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( uint32_t ) pvParameters;
+ pxTopOfStack--;
- /* These values are just spacers. The return address of the function
- * would normally be written here. */
- *pxTopOfStack = ( StackType_t ) 0xcdcd;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xcdcd;
- pxTopOfStack--;
+ /* These values are just spacers. The return address of the function
+ would normally be written here. */
+ *pxTopOfStack = ( StackType_t ) 0xcdcd;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xcdcd;
+ pxTopOfStack--;
- /* The start address / PSW value is also written in as a 32bit value,
- * so leave a space for the second two bytes. */
- pxTopOfStack--;
+ /* The start address / PSW value is also written in as a 32bit value,
+ so leave a space for the second two bytes. */
+ pxTopOfStack--;
+
+ /* Task function start address combined with the PSW. */
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+ pxTopOfStack--;
- /* Task function start address combined with the PSW. */
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
- pxTopOfStack--;
+ /* An initial value for the AX register. */
+ *pxTopOfStack = ( StackType_t ) 0x1111;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ /* Task function address is written to the stack first. As it is
+ written as a 32bit value a space is left on the stack for the second
+ two bytes. */
+ pxTopOfStack--;
- /* An initial value for the AX register. */
- *pxTopOfStack = ( StackType_t ) 0x1111;
- pxTopOfStack--;
- }
- #else /* if configMEMORY_MODE == 1 */
- {
- /* Task function address is written to the stack first. As it is
- * written as a 32bit value a space is left on the stack for the second
- * two bytes. */
- pxTopOfStack--;
+ /* Task function start address combined with the PSW. */
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+ pxTopOfStack--;
- /* Task function start address combined with the PSW. */
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
- pxTopOfStack--;
+ /* The parameter is passed in AX. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+ }
+ #endif
- /* The parameter is passed in AX. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
- }
- #endif /* if configMEMORY_MODE == 1 */
+ /* An initial value for the HL register. */
+ *pxTopOfStack = ( StackType_t ) 0x2222;
+ pxTopOfStack--;
- /* An initial value for the HL register. */
- *pxTopOfStack = ( StackType_t ) 0x2222;
- pxTopOfStack--;
+ /* CS and ES registers. */
+ *pxTopOfStack = ( StackType_t ) 0x0F00;
+ pxTopOfStack--;
- /* CS and ES registers. */
- *pxTopOfStack = ( StackType_t ) 0x0F00;
- pxTopOfStack--;
+ /* Finally the remaining general purpose registers DE and BC */
+ *pxTopOfStack = ( StackType_t ) 0xDEDE;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xBCBC;
+ pxTopOfStack--;
- /* Finally the remaining general purpose registers DE and BC */
- *pxTopOfStack = ( StackType_t ) 0xDEDE;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xBCBC;
- pxTopOfStack--;
+ /* Finally the critical section nesting count is set to zero when the task
+ first starts. */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
- /* Finally the critical section nesting count is set to zero when the task
- * first starts. */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
-
- /* Return a pointer to the top of the stack we have generated so this can
- * be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* Return a pointer to the top of the stack we have generated so this can
+ be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- * this function is called. */
- prvSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called. */
+ prvSetupTimerInterrupt();
- /* Restore the context of the first task that is going to run. */
- vPortStart();
+ /* Restore the context of the first task that is going to run. */
+ vPortStart();
- /* Should not get here as the tasks are now running! */
- return pdTRUE;
+ /* Should not get here as the tasks are now running! */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the 78K0R port will get stopped. If required simply
- * disable the tick interrupt here. */
+ /* It is unlikely that the 78K0R port will get stopped. If required simply
+ disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- /* Setup channel 5 of the TAU to generate the tick interrupt. */
+ /* Setup channel 5 of the TAU to generate the tick interrupt. */
- /* First the Timer Array Unit has to be enabled. */
- TAU0EN = 1;
+ /* First the Timer Array Unit has to be enabled. */
+ TAU0EN = 1;
- /* To configure the Timer Array Unit all Channels have to first be stopped. */
- TT0 = 0xff;
+ /* To configure the Timer Array Unit all Channels have to first be stopped. */
+ TT0 = 0xff;
- /* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt
- * priority. */
- TMMK05 = 1;
+ /* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt
+ priority. */
+ TMMK05 = 1;
- /* Clear Timer Array Unit Channel 5 interrupt flag. */
- TMIF05 = 0;
+ /* Clear Timer Array Unit Channel 5 interrupt flag. */
+ TMIF05 = 0;
- /* Set Timer Array Unit Channel 5 interrupt priority */
- TMPR005 = 0;
- TMPR105 = 0;
+ /* Set Timer Array Unit Channel 5 interrupt priority */
+ TMPR005 = 0;
+ TMPR105 = 0;
- /* Set Timer Array Unit Channel 5 Mode as interval timer. */
- TMR05 = 0x0000;
+ /* Set Timer Array Unit Channel 5 Mode as interval timer. */
+ TMR05 = 0x0000;
- /* Set the compare match value according to the tick rate we want. */
- TDR05 = ( TickType_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+ /* Set the compare match value according to the tick rate we want. */
+ TDR05 = ( TickType_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
- /* Set Timer Array Unit Channel 5 output mode */
- TOM0 &= ~0x0020;
+ /* Set Timer Array Unit Channel 5 output mode */
+ TOM0 &= ~0x0020;
- /* Set Timer Array Unit Channel 5 output level */
- TOL0 &= ~0x0020;
+ /* Set Timer Array Unit Channel 5 output level */
+ TOL0 &= ~0x0020;
- /* Set Timer Array Unit Channel 5 output enable */
- TOE0 &= ~0x0020;
+ /* Set Timer Array Unit Channel 5 output enable */
+ TOE0 &= ~0x0020;
- /* Interrupt of Timer Array Unit Channel 5 enabled */
- TMMK05 = 0;
+ /* Interrupt of Timer Array Unit Channel 5 enabled */
+ TMMK05 = 0;
- /* Start Timer Array Unit Channel 5.*/
- TS0 |= 0x0020;
+ /* Start Timer Array Unit Channel 5.*/
+ TS0 |= 0x0020;
}
/*-----------------------------------------------------------*/
+
diff --git a/portable/IAR/78K0R/portmacro.h b/portable/IAR/78K0R/portmacro.h
index a30323b..79efeed 100644
--- a/portable/IAR/78K0R/portmacro.h
+++ b/portable/IAR/78K0R/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,101 +44,102 @@
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint16_t
- #define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
- typedef portSTACK_TYPE StackType_t;
- typedef short BaseType_t;
- typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef unsigned int TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if (configUSE_16_BIT_TICKS==1)
+ typedef unsigned int TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
- #define portDISABLE_INTERRUPTS() __asm( "DI" )
- #define portENABLE_INTERRUPTS() __asm( "EI" )
+#define portDISABLE_INTERRUPTS() __asm ( "DI" )
+#define portENABLE_INTERRUPTS() __asm ( "EI" )
/*-----------------------------------------------------------*/
/* Critical section control macros. */
- #define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
- #define portENTER_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
- #define portEXIT_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
- extern void vPortStart( void );
- #define portYIELD() __asm( "BRK" )
- #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
- #define portNOP() __asm( "NOP" )
+extern void vPortStart( void );
+#define portYIELD() __asm( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+#define portNOP() __asm( "NOP" )
/*-----------------------------------------------------------*/
/* Hardwware specifics. */
- #define portBYTE_ALIGNMENT 2
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- static __interrupt void P0_isr( void );
+static __interrupt void P0_isr (void);
/* --------------------------------------------------------------------------*/
/* Option-bytes and security ID */
/* --------------------------------------------------------------------------*/
- #define OPT_BYTES_SIZE 4
- #define SECU_ID_SIZE 10
- #define WATCHDOG_DISABLED 0x00
- #define LVI_ENABLED 0xFE
- #define LVI_DISABLED 0xFF
- #define RESERVED_FF 0xFF
- #define OCD_DISABLED 0x04
- #define OCD_ENABLED 0x81
- #define OCD_ENABLED_ERASE 0x80
+#define OPT_BYTES_SIZE 4
+#define SECU_ID_SIZE 10
+#define WATCHDOG_DISABLED 0x00
+#define LVI_ENABLED 0xFE
+#define LVI_DISABLED 0xFF
+#define RESERVED_FF 0xFF
+#define OCD_DISABLED 0x04
+#define OCD_ENABLED 0x81
+#define OCD_ENABLED_ERASE 0x80
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/ARM_CA5_No_GIC/port.c b/portable/IAR/ARM_CA5_No_GIC/port.c
index 38f7bb3..25b5fb5 100644
--- a/portable/IAR/ARM_CA5_No_GIC/port.c
+++ b/portable/IAR/ARM_CA5_No_GIC/port.c
@@ -33,42 +33,42 @@
#include "task.h"
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt. A default that uses the PIT is provided in the official demo application.
+ #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt. A default that uses the PIT is provided in the official demo application.
#endif
#ifndef configCLEAR_TICK_INTERRUPT
- #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. A default that uses the PIT is provided in the official demo application.
+ #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. A default that uses the PIT is provided in the official demo application.
#endif
/* A critical section is exited when the critical section nesting count reaches
- * this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* Tasks are not created with a floating point context, but can be given a
- * floating point context after they have been created. A variable is stored as
- * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
- * does not have an FPU context, or any other value if the task does have an FPU
- * context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
- * mode. */
-#define portAPSR_USER_MODE ( 0x10 )
+mode. */
+#define portAPSR_USER_MODE ( 0x10 )
/*-----------------------------------------------------------*/
@@ -86,21 +86,21 @@
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
- * variable has to be stored as part of the task context and must be initialised to
- * a non zero value to ensure interrupts don't inadvertently become unmasked before
- * the scheduler starts. As it is stored as part of the task context it will
- * automatically be set to 0 when the first task is started. */
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero
- * then a floating point context must be saved and restored for the task. */
+then a floating point context must be saved and restored for the task. */
uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
- * if the nesting depth is 0. */
+if the nesting depth is 0. */
uint32_t ulPortInterruptNesting = 0UL;
@@ -109,195 +109,192 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro.
- *
- * The fist real value on the stack is the status register, which is set for
- * system mode, with interrupts enabled. A few NULLs are added first to ensure
- * GDB does not try decoding a non-existent return address. */
- *pxTopOfStack = NULL;
- pxTopOfStack--;
- *pxTopOfStack = NULL;
- pxTopOfStack--;
- *pxTopOfStack = NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro.
- if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
- {
- /* The task will start in THUMB mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ The fist real value on the stack is the status register, which is set for
+ system mode, with interrupts enabled. A few NULLs are added first to ensure
+ GDB does not try decoding a non-existent return address. */
+ *pxTopOfStack = NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- pxTopOfStack--;
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+ {
+ /* The task will start in THUMB mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
- /* Next the return address, which in this case is the start of the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
+ pxTopOfStack--;
- /* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* Next the return address, which in this case is the start of the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
- /* The task will start with a critical nesting count of 0 as interrupts are
- * enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
+ /* Next all the registers other than the stack pointer. */
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The task will start without a floating point context. A task that uses
- * the floating point hardware must call vPortTaskUsesFPU() before executing
- * any floating point instructions. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
- return pxTopOfStack;
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( ulPortInterruptNesting == ~0UL );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulPortInterruptNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- uint32_t ulAPSR;
+uint32_t ulAPSR;
- /* Only continue if the CPU is not in User mode. The CPU must be in a
- * Privileged mode for the scheduler to start. */
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+ /* Only continue if the CPU is not in User mode. The CPU must be in a
+ Privileged mode for the scheduler to start. */
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+ configASSERT( ulAPSR != portAPSR_USER_MODE );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
- configASSERT( ulAPSR != portAPSR_USER_MODE );
+ if( ulAPSR != portAPSR_USER_MODE )
+ {
+ /* Start the timer that generates the tick ISR. */
+ configSETUP_TICK_INTERRUPT();
+ vPortRestoreTaskContext();
+ }
- if( ulAPSR != portAPSR_USER_MODE )
- {
- /* Start the timer that generates the tick ISR. */
- configSETUP_TICK_INTERRUPT();
- vPortRestoreTaskContext();
- }
-
- /* Will only get here if vTaskStartScheduler() was called with the CPU in
- * a non-privileged mode or the binary point register was not set to its lowest
- * possible value. */
- return 0;
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in
+ a non-privileged mode or the binary point register was not set to its lowest
+ possible value. */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- portDISABLE_INTERRUPTS();
+ portDISABLE_INTERRUPTS();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( ulCriticalNesting == 1 )
- {
- configASSERT( ulPortInterruptNesting == 0 );
- }
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ulCriticalNesting == 1 )
+ {
+ configASSERT( ulPortInterruptNesting == 0 );
+ }
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- * exited. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then all interrupt
- * priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- * should be unmasked. */
- portENABLE_INTERRUPTS();
- }
- }
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portENABLE_INTERRUPTS();
+ }
+ }
}
/*-----------------------------------------------------------*/
void FreeRTOS_Tick_Handler( void )
{
- portDISABLE_INTERRUPTS();
+ portDISABLE_INTERRUPTS();
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ulPortYieldRequired = pdTRUE;
- }
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ulPortYieldRequired = pdTRUE;
+ }
- portENABLE_INTERRUPTS();
- configCLEAR_TICK_INTERRUPT();
+ portENABLE_INTERRUPTS();
+ configCLEAR_TICK_INTERRUPT();
}
/*-----------------------------------------------------------*/
void vPortTaskUsesFPU( void )
{
- uint32_t ulInitialFPSCR = 0;
+uint32_t ulInitialFPSCR = 0;
- /* A task is registering the fact that it needs an FPU context. Set the
- * FPU flag (which is saved as part of the task context). */
- ulPortTaskHasFPUContext = pdTRUE;
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ulPortTaskHasFPUContext = pdTRUE;
- /* Initialise the floating point status register. */
- __asm( "FMXR FPSCR, %0"::"r" ( ulInitialFPSCR ) );
+ /* Initialise the floating point status register. */
+ __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/IAR/ARM_CA5_No_GIC/portASM.h b/portable/IAR/ARM_CA5_No_GIC/portASM.h
index ebc9f01..c050268 100644
--- a/portable/IAR/ARM_CA5_No_GIC/portASM.h
+++ b/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -1,127 +1,113 @@
-; /*
- * ; * FreeRTOS Kernel V10.3.1
- * ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * ; *
- * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * ; * this software and associated documentation files (the "Software"), to deal in
- * ; * the Software without restriction, including without limitation the rights to
- * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * ; * the Software, and to permit persons to whom the Software is furnished to do so,
- * ; * subject to the following conditions:
- * ; *
- * ; * The above copyright notice and this permission notice shall be included in all
- * ; * copies or substantial portions of the Software.
- * ; *
- * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * ; *
- * ; * http://www.FreeRTOS.org
- * ; * http://aws.amazon.com/freertos
- * ; *
- * ; * 1 tab == 4 spaces!
- * ; */
+;/*
+; * FreeRTOS Kernel V10.3.1
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
-EXTERN vTaskSwitchContext
-EXTERN ulCriticalNesting
-EXTERN pxCurrentTCB
-EXTERN ulPortTaskHasFPUContext
-EXTERN ulAsmAPIPriorityMask
+ EXTERN vTaskSwitchContext
+ EXTERN ulCriticalNesting
+ EXTERN pxCurrentTCB
+ EXTERN ulPortTaskHasFPUContext
+ EXTERN ulAsmAPIPriorityMask
portSAVE_CONTEXT macro
-;
-Save the LR and SPSR onto the system mode stack before switching to
-;
-system mode to save the remaining system mode registers
-SRSDB sp !, # SYS_MODE
- CPS # SYS_MODE
- PUSH { R0 - R12, R14 }
+ ; Save the LR and SPSR onto the system mode stack before switching to
+ ; system mode to save the remaining system mode registers
+ SRSDB sp!, #SYS_MODE
+ CPS #SYS_MODE
+ PUSH {R0-R12, R14}
-;
-Push the critical nesting count
-LDR R2, = ulCriticalNesting
- LDR R1, [ R2 ]
-PUSH { R1 }
+ ; Push the critical nesting count
+ LDR R2, =ulCriticalNesting
+ LDR R1, [R2]
+ PUSH {R1}
-;
-Does the task have a floating point context that needs saving ? If
-;
-ulPortTaskHasFPUContext is 0 then no.
- LDR R2, = ulPortTaskHasFPUContext
- LDR R3, [ R2 ]
-CMP R3, # 0
+ ; Does the task have a floating point context that needs saving? If
+ ; ulPortTaskHasFPUContext is 0 then no.
+ LDR R2, =ulPortTaskHasFPUContext
+ LDR R3, [R2]
+ CMP R3, #0
-;
-Save the floating point context, if any
-FMRXNE R1, FPSCR
- VPUSHNE { D0 - D15 }
+ ; Save the floating point context, if any
+ FMRXNE R1, FPSCR
+ VPUSHNE {D0-D15}
#if configFPU_D32 == 1
- VPUSHNE { D16 - D31 }
-#endif; configFPU_D32
-PUSHNE { R1 }
+ VPUSHNE {D16-D31}
+#endif ; configFPU_D32
+ PUSHNE {R1}
-;
-Save ulPortTaskHasFPUContext itself
- PUSH { R3 }
+ ; Save ulPortTaskHasFPUContext itself
+ PUSH {R3}
-;
-Save the stack pointer in the TCB
-LDR R0, = pxCurrentTCB
- LDR R1, [ R0 ]
-STR SP, [ R1 ]
+ ; Save the stack pointer in the TCB
+ LDR R0, =pxCurrentTCB
+ LDR R1, [R0]
+ STR SP, [R1]
-endm
+ endm
; /**********************************************************************/
portRESTORE_CONTEXT macro
-;
-Set the SP to point to the stack of the task being restored.
- LDR R0, = pxCurrentTCB
- LDR R1, [ R0 ]
-LDR SP, [ R1 ]
+ ; Set the SP to point to the stack of the task being restored.
+ LDR R0, =pxCurrentTCB
+ LDR R1, [R0]
+ LDR SP, [R1]
-;
-Is there a floating point context to restore ? If the restored
-;
-ulPortTaskHasFPUContext is zero then no.
- LDR R0, = ulPortTaskHasFPUContext
- POP { R1 }
-STR R1, [ R0 ]
-CMP R1, # 0
+ ; Is there a floating point context to restore? If the restored
+ ; ulPortTaskHasFPUContext is zero then no.
+ LDR R0, =ulPortTaskHasFPUContext
+ POP {R1}
+ STR R1, [R0]
+ CMP R1, #0
-;
-Restore the floating point context, if any
- POPNE { R0 }
+ ; Restore the floating point context, if any
+ POPNE {R0}
#if configFPU_D32 == 1
- VPOPNE { D16 - D31 }
-#endif; configFPU_D32
-VPOPNE { D0 - D15 }
-VMSRNE FPSCR, R0
+ VPOPNE {D16-D31}
+#endif ; configFPU_D32
+ VPOPNE {D0-D15}
+ VMSRNE FPSCR, R0
-;
-Restore the critical section nesting depth
-LDR R0, = ulCriticalNesting
- POP { R1 }
-STR R1, [ R0 ]
+ ; Restore the critical section nesting depth
+ LDR R0, =ulCriticalNesting
+ POP {R1}
+ STR R1, [R0]
-;
-Restore all system mode registers other than the SP( which is already
- ;
- being used )
-POP
-{
- R0 - R12, R14
-}
+ ; Restore all system mode registers other than the SP (which is already
+ ; being used)
+ POP {R0-R12, R14}
-Return to the task code, loading CPSR on the way.CPSR has the interrupt
-;
-enable bit set appropriately for the task about to execute.
- RFEIA sp !
+ ; Return to the task code, loading CPSR on the way. CPSR has the interrupt
+ ; enable bit set appropriately for the task about to execute.
+ RFEIA sp!
-endm
+ endm
+
+
+
+
+
diff --git a/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/portable/IAR/ARM_CA5_No_GIC/portmacro.h
index 4c5584c..da2f30b 100644
--- a/portable/IAR/ARM_CA5_No_GIC/portmacro.h
+++ b/portable/IAR/ARM_CA5_No_GIC/portmacro.h
@@ -26,136 +26,137 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/* IAR includes. */
- #ifdef __ICCARM__
+#ifdef __ICCARM__
- #include <intrinsics.h>
+ #include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
+ /*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
-/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+ /* Type definitions. */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
-/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+ /* Hardware specifics. */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
-/* Task utilities. */
+ /* Task utilities. */
-/* Called at the end of an ISR that can cause a context switch. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
- }
+ /* Called at the end of an ISR that can cause a context switch. */
+ #define portEND_SWITCHING_ISR( xSwitchRequired )\
+ { \
+ extern uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+ }
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
- #define portYIELD() __asm volatile ( "SWI 0" ); __ISB()
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+ #define portYIELD() __asm volatile ( "SWI 0" ); __ISB()
-/*-----------------------------------------------------------
-* Critical section control
-*----------------------------------------------------------*/
+ /*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern uint32_t ulPortSetInterruptMask( void );
- extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+ extern void vPortEnterCritical( void );
+ extern void vPortExitCritical( void );
+ extern uint32_t ulPortSetInterruptMask( void );
+ extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
- #define portDISABLE_INTERRUPTS() __disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */
- #define portENABLE_INTERRUPTS() __enable_irq()
- #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_interrupt_state( x )
+ #define portENTER_CRITICAL() vPortEnterCritical();
+ #define portEXIT_CRITICAL() vPortExitCritical();
+ #define portDISABLE_INTERRUPTS() __disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */
+ #define portENABLE_INTERRUPTS() __enable_irq()
+ #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_interrupt_state(x)
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not required for this port but included in case common demo code that uses these
- * macros is used. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ /* Task function macros as described on the FreeRTOS.org WEB site. These are
+ not required for this port but included in case common demo code that uses these
+ macros is used. */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/* Prototype of the FreeRTOS tick handler. This must be installed as the
- * handler for whichever peripheral is used to generate the RTOS tick. */
- void FreeRTOS_Tick_Handler( void );
+ /* Prototype of the FreeRTOS tick handler. This must be installed as the
+ handler for whichever peripheral is used to generate the RTOS tick. */
+ void FreeRTOS_Tick_Handler( void );
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- * before any floating point instructions are executed. */
- void vPortTaskUsesFPU( void );
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+ /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+ before any floating point instructions are executed. */
+ void vPortTaskUsesFPU( void );
+ #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+ /* Architecture specific optimisations. */
+ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+ #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
- #define portNOP() __asm volatile ( "NOP" )
+ #define portNOP() __asm volatile( "NOP" )
- #ifdef __cplusplus
- } /* extern C */
- #endif
+ #ifdef __cplusplus
+ } /* extern C */
+ #endif
-/* Suppress warnings that are generated by the IAR tools, but cannot be
- * fixed in the source code because to do so would cause other compilers to
- * generate warnings. */
- #pragma diag_suppress=Pe191
- #pragma diag_suppress=Pa082
+ /* Suppress warnings that are generated by the IAR tools, but cannot be
+ fixed in the source code because to do so would cause other compilers to
+ generate warnings. */
+ #pragma diag_suppress=Pe191
+ #pragma diag_suppress=Pa082
- #endif /* __ICCARM__ */
+#endif /* __ICCARM__ */
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/ARM_CA9/port.c b/portable/IAR/ARM_CA9/port.c
index 416be8e..a1d9c29 100644
--- a/portable/IAR/ARM_CA9/port.c
+++ b/portable/IAR/ARM_CA9/port.c
@@ -36,89 +36,89 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
- #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
- #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#endif
#ifndef configCLEAR_TICK_INTERRUPT
- #define configCLEAR_TICK_INTERRUPT()
+ #define configCLEAR_TICK_INTERRUPT()
#endif
/* A critical section is exited when the critical section nesting count reaches
- * this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
- * (but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
- * floating point context after they have been created. A variable is stored as
- * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
- * does not have an FPU context, or any other value if the task does have an FPU
- * context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
- * point is zero. */
-#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
- * mode. */
-#define portAPSR_USER_MODE ( 0x10 )
+mode. */
+#define portAPSR_USER_MODE ( 0x10 )
/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK() \
- { \
- __disable_irq(); \
- portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
- __asm( "DSB \n" \
- "ISB \n"); \
- __enable_irq(); \
- }
+#define portCLEAR_INTERRUPT_MASK() \
+{ \
+ __disable_irq(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm( "DSB \n" \
+ "ISB \n" ); \
+ __enable_irq(); \
+}
/*-----------------------------------------------------------*/
@@ -136,21 +136,21 @@
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
- * variable has to be stored as part of the task context and must be initialised to
- * a non zero value to ensure interrupts don't inadvertently become unmasked before
- * the scheduler starts. As it is stored as part of the task context it will
- * automatically be set to 0 when the first task is started. */
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero
- * then a floating point context must be saved and restored for the task. */
+then a floating point context must be saved and restored for the task. */
uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
- * if the nesting depth is 0. */
+if the nesting depth is 0. */
uint32_t ulPortInterruptNesting = 0UL;
@@ -159,287 +159,281 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro.
- *
- * The fist real value on the stack is the status register, which is set for
- * system mode, with interrupts enabled. A few NULLs are added first to ensure
- * GDB does not try decoding a non-existent return address. */
- *pxTopOfStack = NULL;
- pxTopOfStack--;
- *pxTopOfStack = NULL;
- pxTopOfStack--;
- *pxTopOfStack = NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro.
- if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
- {
- /* The task will start in THUMB mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ The fist real value on the stack is the status register, which is set for
+ system mode, with interrupts enabled. A few NULLs are added first to ensure
+ GDB does not try decoding a non-existent return address. */
+ *pxTopOfStack = NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- pxTopOfStack--;
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+ {
+ /* The task will start in THUMB mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
- /* Next the return address, which in this case is the start of the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
+ pxTopOfStack--;
- /* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* Next the return address, which in this case is the start of the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
- /* The task will start with a critical nesting count of 0 as interrupts are
- * enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
+ /* Next all the registers other than the stack pointer. */
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The task will start without a floating point context. A task that uses
- * the floating point hardware must call vPortTaskUsesFPU() before executing
- * any floating point instructions. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
- return pxTopOfStack;
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( ulPortInterruptNesting == ~0UL );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulPortInterruptNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- uint32_t ulAPSR;
+uint32_t ulAPSR;
- /* Only continue if the CPU is not in User mode. The CPU must be in a
- * Privileged mode for the scheduler to start. */
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+ /* Only continue if the CPU is not in User mode. The CPU must be in a
+ Privileged mode for the scheduler to start. */
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+ configASSERT( ulAPSR != portAPSR_USER_MODE );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
- configASSERT( ulAPSR != portAPSR_USER_MODE );
+ if( ulAPSR != portAPSR_USER_MODE )
+ {
+ /* Only continue if the binary point value is set to its lowest possible
+ setting. See the comments in vPortValidateInterruptPriority() below for
+ more information. */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
- if( ulAPSR != portAPSR_USER_MODE )
- {
- /* Only continue if the binary point value is set to its lowest possible
- * setting. See the comments in vPortValidateInterruptPriority() below for
- * more information. */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+ {
+ /* Start the timer that generates the tick ISR. */
+ configSETUP_TICK_INTERRUPT();
- if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
- {
- /* Start the timer that generates the tick ISR. */
- configSETUP_TICK_INTERRUPT();
+ __enable_irq();
+ vPortRestoreTaskContext();
+ }
+ }
- __enable_irq();
- vPortRestoreTaskContext();
- }
- }
-
- /* Will only get here if vTaskStartScheduler() was called with the CPU in
- * a non-privileged mode or the binary point register was not set to its lowest
- * possible value. */
- return 0;
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in
+ a non-privileged mode or the binary point register was not set to its lowest
+ possible value. */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- ulPortSetInterruptMask();
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ ulPortSetInterruptMask();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( ulCriticalNesting == 1 )
- {
- configASSERT( ulPortInterruptNesting == 0 );
- }
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ulCriticalNesting == 1 )
+ {
+ configASSERT( ulPortInterruptNesting == 0 );
+ }
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- * exited. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then all interrupt
- * priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- * should be unmasked. */
- portCLEAR_INTERRUPT_MASK();
- }
- }
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portCLEAR_INTERRUPT_MASK();
+ }
+ }
}
/*-----------------------------------------------------------*/
void FreeRTOS_Tick_Handler( void )
{
- /* Set interrupt mask before altering scheduler structures. The tick
- * handler runs at the lowest priority, so interrupts cannot already be masked,
- * so there is no need to save and restore the current mask value. */
- __disable_irq();
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm( "DSB \n"
- "ISB \n");
- __enable_irq();
+ /* Set interrupt mask before altering scheduler structures. The tick
+ handler runs at the lowest priority, so interrupts cannot already be masked,
+ so there is no need to save and restore the current mask value. */
+ __disable_irq();
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm( "DSB \n"
+ "ISB \n" );
+ __enable_irq();
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ulPortYieldRequired = pdTRUE;
- }
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ulPortYieldRequired = pdTRUE;
+ }
- /* Ensure all interrupt priorities are active again. */
- portCLEAR_INTERRUPT_MASK();
- configCLEAR_TICK_INTERRUPT();
+ /* Ensure all interrupt priorities are active again. */
+ portCLEAR_INTERRUPT_MASK();
+ configCLEAR_TICK_INTERRUPT();
}
/*-----------------------------------------------------------*/
void vPortTaskUsesFPU( void )
{
- uint32_t ulInitialFPSCR = 0;
+uint32_t ulInitialFPSCR = 0;
- /* A task is registering the fact that it needs an FPU context. Set the
- * FPU flag (which is saved as part of the task context). */
- ulPortTaskHasFPUContext = pdTRUE;
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ulPortTaskHasFPUContext = pdTRUE;
- /* Initialise the floating point status register. */
- __asm( "FMXR FPSCR, %0"::"r" ( ulInitialFPSCR ) );
+ /* Initialise the floating point status register. */
+ __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
}
/*-----------------------------------------------------------*/
void vPortClearInterruptMask( uint32_t ulNewMaskValue )
{
- if( ulNewMaskValue == pdFALSE )
- {
- portCLEAR_INTERRUPT_MASK();
- }
+ if( ulNewMaskValue == pdFALSE )
+ {
+ portCLEAR_INTERRUPT_MASK();
+ }
}
/*-----------------------------------------------------------*/
uint32_t ulPortSetInterruptMask( void )
{
- uint32_t ulReturn;
+uint32_t ulReturn;
- __disable_irq();
+ __disable_irq();
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+ {
+ /* Interrupts were already masked. */
+ ulReturn = pdTRUE;
+ }
+ else
+ {
+ ulReturn = pdFALSE;
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm( "DSB \n"
+ "ISB \n" );
+ }
+ __enable_irq();
- if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
- {
- /* Interrupts were already masked. */
- ulReturn = pdTRUE;
- }
- else
- {
- ulReturn = pdFALSE;
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm( "DSB \n"
- "ISB \n");
- }
-
- __enable_irq();
-
- return ulReturn;
+ return ulReturn;
}
/*-----------------------------------------------------------*/
-#if ( configASSERT_DEFINED == 1 )
+#if( configASSERT_DEFINED == 1 )
- void vPortValidateInterruptPriority( void )
- {
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible.
- *
- * The following links provide detailed information:
- * http://www.freertos.org/RTOS-Cortex-M3-M4.html
- * http://www.freertos.org/FAQHelp.html */
- configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+ void vPortValidateInterruptPriority( void )
+ {
+ /* The following assertion will fail if a service routine (ISR) for
+ an interrupt that has been assigned a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ function. ISR safe FreeRTOS API functions must *only* be called
+ from interrupts that have been assigned a priority at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
- /* Priority grouping: The interrupt controller (GIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * The priority grouping is configured by the GIC's binary point register
- * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
- * possible value (which may be above 0). */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
- }
+ Numerically low interrupt priority numbers represent logically high
+ interrupt priorities, therefore the priority of the interrupt must
+ be set to a value equal to or numerically *higher* than
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ FreeRTOS maintains separate thread and ISR API functions to ensure
+ interrupt entry is as fast and simple as possible.
+
+ The following links provide detailed information:
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html
+ http://www.freertos.org/FAQHelp.html */
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+ /* Priority grouping: The interrupt controller (GIC) allows the bits
+ that define each interrupt's priority to be split between bits that
+ define the interrupt's pre-emption priority bits and bits that define
+ the interrupt's sub-priority. For simplicity all bits must be defined
+ to be pre-emption priority bits. The following assertion will fail if
+ this is not the case (if some bits represent a sub-priority).
+
+ The priority grouping is configured by the GIC's binary point register
+ (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
+ possible value (which may be above 0). */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ }
#endif /* configASSERT_DEFINED */
+
+
diff --git a/portable/IAR/ARM_CA9/portASM.h b/portable/IAR/ARM_CA9/portASM.h
index 827b01f..4ecbc9f 100644
--- a/portable/IAR/ARM_CA9/portASM.h
+++ b/portable/IAR/ARM_CA9/portASM.h
@@ -1,129 +1,115 @@
-; /*
- * ; * FreeRTOS Kernel V10.3.1
- * ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * ; *
- * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * ; * this software and associated documentation files (the "Software"), to deal in
- * ; * the Software without restriction, including without limitation the rights to
- * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * ; * the Software, and to permit persons to whom the Software is furnished to do so,
- * ; * subject to the following conditions:
- * ; *
- * ; * The above copyright notice and this permission notice shall be included in all
- * ; * copies or substantial portions of the Software.
- * ; *
- * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * ; *
- * ; * http://www.FreeRTOS.org
- * ; * http://aws.amazon.com/freertos
- * ; *
- * ; * 1 tab == 4 spaces!
- * ; */
+;/*
+; * FreeRTOS Kernel V10.3.1
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
-EXTERN vTaskSwitchContext
-EXTERN ulCriticalNesting
-EXTERN pxCurrentTCB
-EXTERN ulPortTaskHasFPUContext
-EXTERN ulAsmAPIPriorityMask
+ EXTERN vTaskSwitchContext
+ EXTERN ulCriticalNesting
+ EXTERN pxCurrentTCB
+ EXTERN ulPortTaskHasFPUContext
+ EXTERN ulAsmAPIPriorityMask
portSAVE_CONTEXT macro
-;
-Save the LR and SPSR onto the system mode stack before switching to
-;
-system mode to save the remaining system mode registers
-SRSDB sp !, # SYS_MODE
- CPS # SYS_MODE
- PUSH { R0 - R12, R14 }
+ ; Save the LR and SPSR onto the system mode stack before switching to
+ ; system mode to save the remaining system mode registers
+ SRSDB sp!, #SYS_MODE
+ CPS #SYS_MODE
+ PUSH {R0-R12, R14}
-;
-Push the critical nesting count
-LDR R2, = ulCriticalNesting
- LDR R1, [ R2 ]
-PUSH { R1 }
+ ; Push the critical nesting count
+ LDR R2, =ulCriticalNesting
+ LDR R1, [R2]
+ PUSH {R1}
-;
-Does the task have a floating point context that needs saving ? If
-;
-ulPortTaskHasFPUContext is 0 then no.
- LDR R2, = ulPortTaskHasFPUContext
- LDR R3, [ R2 ]
-CMP R3, # 0
+ ; Does the task have a floating point context that needs saving? If
+ ; ulPortTaskHasFPUContext is 0 then no.
+ LDR R2, =ulPortTaskHasFPUContext
+ LDR R3, [R2]
+ CMP R3, #0
-;
-Save the floating point context, if any
-FMRXNE R1, FPSCR
- VPUSHNE { D0 - D15 }
-VPUSHNE { D16 - D31 }
-PUSHNE { R1 }
+ ; Save the floating point context, if any
+ FMRXNE R1, FPSCR
+ VPUSHNE {D0-D15}
+ VPUSHNE {D16-D31}
+ PUSHNE {R1}
-;
-Save ulPortTaskHasFPUContext itself
- PUSH { R3 }
+ ; Save ulPortTaskHasFPUContext itself
+ PUSH {R3}
-;
-Save the stack pointer in the TCB
-LDR R0, = pxCurrentTCB
- LDR R1, [ R0 ]
-STR SP, [ R1 ]
+ ; Save the stack pointer in the TCB
+ LDR R0, =pxCurrentTCB
+ LDR R1, [R0]
+ STR SP, [R1]
-endm
+ endm
; /**********************************************************************/
portRESTORE_CONTEXT macro
-;
-Set the SP to point to the stack of the task being restored.
- LDR R0, = pxCurrentTCB
- LDR R1, [ R0 ]
-LDR SP, [ R1 ]
+ ; Set the SP to point to the stack of the task being restored.
+ LDR R0, =pxCurrentTCB
+ LDR R1, [R0]
+ LDR SP, [R1]
-;
-Is there a floating point context to restore ? If the restored
-;
-ulPortTaskHasFPUContext is zero then no.
- LDR R0, = ulPortTaskHasFPUContext
- POP { R1 }
-STR R1, [ R0 ]
-CMP R1, # 0
+ ; Is there a floating point context to restore? If the restored
+ ; ulPortTaskHasFPUContext is zero then no.
+ LDR R0, =ulPortTaskHasFPUContext
+ POP {R1}
+ STR R1, [R0]
+ CMP R1, #0
-;
-Restore the floating point context, if any
- POPNE { R0 }
-VPOPNE { D16 - D31 }
-VPOPNE { D0 - D15 }
-VMSRNE FPSCR, R0
+ ; Restore the floating point context, if any
+ POPNE {R0}
+ VPOPNE {D16-D31}
+ VPOPNE {D0-D15}
+ VMSRNE FPSCR, R0
-;
-Restore the critical section nesting depth
-LDR R0, = ulCriticalNesting
- POP { R1 }
-STR R1, [ R0 ]
+ ; Restore the critical section nesting depth
+ LDR R0, =ulCriticalNesting
+ POP {R1}
+ STR R1, [R0]
-;
-Ensure the priority mask is correct for the critical nesting depth
-LDR R2, = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
- CMP R1, # 0
-MOVEQ R4, # 255
-LDRNE R4, = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
- STR R4, [ r2 ]
+ ; Ensure the priority mask is correct for the critical nesting depth
+ LDR R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
+ CMP R1, #0
+ MOVEQ R4, #255
+ LDRNE R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
+ STR R4, [r2]
-;
-Restore all system mode registers other than the SP( which is already
- ;
- being used )
-POP
-{
- R0 - R12, R14
-}
+ ; Restore all system mode registers other than the SP (which is already
+ ; being used)
+ POP {R0-R12, R14}
-Return to the task code, loading CPSR on the way.
- RFEIA sp !
+ ; Return to the task code, loading CPSR on the way.
+ RFEIA sp!
-endm
+ endm
+
+
+
+
+
diff --git a/portable/IAR/ARM_CA9/portmacro.h b/portable/IAR/ARM_CA9/portmacro.h
index 343fffc..2b1baa5 100644
--- a/portable/IAR/ARM_CA9/portmacro.h
+++ b/portable/IAR/ARM_CA9/portmacro.h
@@ -26,183 +26,184 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/* IAR includes. */
- #ifdef __ICCARM__
+#ifdef __ICCARM__
- #include <intrinsics.h>
+ #include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
+ /*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
-/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+ /* Type definitions. */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
-/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+ /* Hardware specifics. */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
-/* Task utilities. */
+ /* Task utilities. */
-/* Called at the end of an ISR that can cause a context switch. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
- }
+ /* Called at the end of an ISR that can cause a context switch. */
+ #define portEND_SWITCHING_ISR( xSwitchRequired )\
+ { \
+ extern uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+ }
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
- #define portYIELD() __asm( "SWI 0" );
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+ #define portYIELD() __asm( "SWI 0" );
-/*-----------------------------------------------------------
-* Critical section control
-*----------------------------------------------------------*/
+ /*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern uint32_t ulPortSetInterruptMask( void );
- extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+ extern void vPortEnterCritical( void );
+ extern void vPortExitCritical( void );
+ extern uint32_t ulPortSetInterruptMask( void );
+ extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-/* These macros do not globally disable/enable interrupts. They do mask off
- * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
- #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
- #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
+ /* These macros do not globally disable/enable interrupts. They do mask off
+ interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+ #define portENTER_CRITICAL() vPortEnterCritical();
+ #define portEXIT_CRITICAL() vPortExitCritical();
+ #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
+ #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not required for this port but included in case common demo code that uses these
- * macros is used. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ /* Task function macros as described on the FreeRTOS.org WEB site. These are
+ not required for this port but included in case common demo code that uses these
+ macros is used. */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/* Prototype of the FreeRTOS tick handler. This must be installed as the
- * handler for whichever peripheral is used to generate the RTOS tick. */
- void FreeRTOS_Tick_Handler( void );
+ /* Prototype of the FreeRTOS tick handler. This must be installed as the
+ handler for whichever peripheral is used to generate the RTOS tick. */
+ void FreeRTOS_Tick_Handler( void );
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- * before any floating point instructions are executed. */
- void vPortTaskUsesFPU( void );
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+ /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+ before any floating point instructions are executed. */
+ void vPortTaskUsesFPU( void );
+ #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
- #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
- #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+ #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+ #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+ /* Architecture specific optimisations. */
+ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+ #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif /* configASSERT */
+ #ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif /* configASSERT */
- #define portNOP() __asm volatile ( "NOP" )
+ #define portNOP() __asm volatile( "NOP" )
- #ifdef __cplusplus
- } /* extern C */
- #endif
+ #ifdef __cplusplus
+ } /* extern C */
+ #endif
-/* Suppress warnings that are generated by the IAR tools, but cannot be
- * fixed in the source code because to do so would cause other compilers to
- * generate warnings. */
- #pragma diag_suppress=Pe191
- #pragma diag_suppress=Pa082
+ /* Suppress warnings that are generated by the IAR tools, but cannot be
+ fixed in the source code because to do so would cause other compilers to
+ generate warnings. */
+ #pragma diag_suppress=Pe191
+ #pragma diag_suppress=Pa082
- #endif /* __ICCARM__ */
+#endif /* __ICCARM__ */
/* The number of bits to shift for an interrupt priority is dependent on the
- * number of bits implemented by the interrupt controller. */
- #if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
- #else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
- #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
- #endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+#else
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
/* Interrupt controller access addresses. */
- #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
- #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
- #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
- #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
- #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
- #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
- #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
- #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
- #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
- #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
- #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
- #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 3f39bc3..e0a0c7e 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -612,7 +612,7 @@
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
- #else /* if defined( __ARMCC_VERSION ) */
+ #else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
@@ -802,22 +802,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
- }
- #else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0 );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@@ -835,21 +835,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -877,18 +877,20 @@
}
/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
- BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+ BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
- void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@@ -1051,7 +1053,9 @@
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
+
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1079,8 +1083,8 @@
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
- if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
- ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
@@ -1089,7 +1093,7 @@
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 3f39bc3..e0a0c7e 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -612,7 +612,7 @@
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
- #else /* if defined( __ARMCC_VERSION ) */
+ #else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
@@ -802,22 +802,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
- }
- #else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0 );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@@ -835,21 +835,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -877,18 +877,20 @@
}
/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
- BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+ BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
- void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@@ -1051,7 +1053,9 @@
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
+
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1079,8 +1083,8 @@
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
- if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
- ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
@@ -1089,7 +1093,7 @@
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 3f39bc3..e0a0c7e 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -612,7 +612,7 @@
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
- #else /* if defined( __ARMCC_VERSION ) */
+ #else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
@@ -802,22 +802,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
- }
- #else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0 );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@@ -835,21 +835,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -877,18 +877,20 @@
}
/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
- BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+ BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
- void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@@ -1051,7 +1053,9 @@
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
+
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1079,8 +1083,8 @@
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
- if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
- ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
@@ -1089,7 +1093,7 @@
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 3f39bc3..e0a0c7e 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -612,7 +612,7 @@
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
- #else /* if defined( __ARMCC_VERSION ) */
+ #else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
@@ -802,22 +802,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
- }
- #else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0 );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else /* if ( configENABLE_MPU == 1 ) */
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@@ -835,21 +835,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -877,18 +877,20 @@
}
/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
- BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+ BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
- void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
@@ -1051,7 +1053,9 @@
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
+
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1079,8 +1083,8 @@
* using a separate MPU region. This is needed because privileged
* SRAM is already protected using an MPU region and ARMv8-M does
* not allow overlapping MPU regions. */
- if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
- ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
+ if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+ ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
{
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
@@ -1089,7 +1093,7 @@
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index dc72bb9..df776db 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -27,11 +27,13 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,171 +46,172 @@
*/
/* IAR includes. */
- #include <intrinsics.h>
+#include <intrinsics.h>
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* MPU specific constants. */
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
+#define portUSING_MPU_WRAPPERS 1
+#define portPRIVILEGE_BIT ( 0x80000000UL )
- #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
- #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
- #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
- /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
- * Register (RASR). */
- #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
- #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
+#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
- /* MPU settings that can be overriden in FreeRTOSConfig.h. */
- #ifndef configTOTAL_MPU_REGIONS
- /* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
- #endif
+/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
+ * Register (RASR). */
+#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
+#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
- /*
- * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
- * memory type, and where necessary the cacheable and shareable properties
- * of the memory region.
- *
- * The TEX, C, and B bits together indicate the memory type of the region,
- * and:
- * - For Normal memory, the cacheable properties of the region.
- * - For Device memory, whether the region is shareable.
- *
- * For Normal memory regions, the S bit indicates whether the region is
- * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
- *
- * See the following two tables for setting TEX, S, C and B bits for
- * unprivileged flash, privileged flash and privileged RAM regions.
- *
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 1 | Device | Shared device | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 1 | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 011 | X | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
- | | | | | outer cacheability rules that must be exported on the | |
- | | | | | bus. See the table below for the cacheability policy | |
- | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
- +-----------------------------------------+----------------------------------------+
- | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
- +-----------------------------------------+----------------------------------------+
- | 00 | Non-cacheable |
- +-----------------------------------------+----------------------------------------+
- | 01 | Write-back, write and read allocate |
- +-----------------------------------------+----------------------------------------+
- | 10 | Write-through, no write allocate |
- +-----------------------------------------+----------------------------------------+
- | 11 | Write-back, no write allocate |
- +-----------------------------------------+----------------------------------------+
- */
+/*
+ * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
+ * memory type, and where necessary the cacheable and shareable properties
+ * of the memory region.
+ *
+ * The TEX, C, and B bits together indicate the memory type of the region,
+ * and:
+ * - For Normal memory, the cacheable properties of the region.
+ * - For Device memory, whether the region is shareable.
+ *
+ * For Normal memory regions, the S bit indicates whether the region is
+ * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
+ *
+ * See the following two tables for setting TEX, S, C and B bits for
+ * unprivileged flash, privileged flash and privileged RAM regions.
+ *
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 1 | Device | Shared device | Shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 1 | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 1 | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 1 | X | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 011 | X | X | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
+ | | | | | outer cacheability rules that must be exported on the | |
+ | | | | | bus. See the table below for the cacheability policy | |
+ | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ |
+ +-----------------------------------------+----------------------------------------+
+ | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
+ +-----------------------------------------+----------------------------------------+
+ | 00 | Non-cacheable |
+ +-----------------------------------------+----------------------------------------+
+ | 01 | Write-back, write and read allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 10 | Write-through, no write allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 11 | Write-back, no write allocate |
+ +-----------------------------------------+----------------------------------------+
+ */
- /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
- * region. */
- #ifndef configTEX_S_C_B_FLASH
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_FLASH ( 0x07UL )
- #endif
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
+ * region. */
+#ifndef configTEX_S_C_B_FLASH
+ /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+ #define configTEX_S_C_B_FLASH ( 0x07UL )
+#endif
- /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
- * region. */
- #ifndef configTEX_S_C_B_SRAM
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_SRAM ( 0x07UL )
- #endif
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
+ * region. */
+#ifndef configTEX_S_C_B_SRAM
+ /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+ #define configTEX_S_C_B_SRAM ( 0x07UL )
+#endif
- #define portUNPRIVILEGED_FLASH_REGION ( 0UL )
- #define portPRIVILEGED_FLASH_REGION ( 1UL )
- #define portPRIVILEGED_RAM_REGION ( 2UL )
- #define portGENERAL_PERIPHERALS_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
- #define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
- #define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
+#define portPRIVILEGED_FLASH_REGION ( 1UL )
+#define portPRIVILEGED_RAM_REGION ( 2UL )
+#define portGENERAL_PERIPHERALS_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
+#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
+#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1UL )
- #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
- typedef struct MPU_REGION_REGISTERS
- {
- uint32_t ulRegionBaseAddress;
- uint32_t ulRegionAttribute;
- } xMPU_REGION_REGISTERS;
+typedef struct MPU_REGION_REGISTERS
+{
+ uint32_t ulRegionBaseAddress;
+ uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
/* Plus 1 to create space for the stack region. */
- typedef struct MPU_SETTINGS
- {
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* SVC numbers for various services. */
- #define portSVC_START_SCHEDULER 0
- #define portSVC_YIELD 1
- #define portSVC_RAISE_PRIVILEGE 2
+#define portSVC_START_SCHEDULER 0
+#define portSVC_YIELD 1
+#define portSVC_RAISE_PRIVILEGE 2
/* Scheduler utilities. */
- #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
- #define portYIELD_WITHIN_API() \
+#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD_WITHIN_API() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -216,137 +219,139 @@
__ISB(); \
}
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API()
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() \
+#define portDISABLE_INTERRUPTS() \
{ \
__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
__DSB(); \
__ISB(); \
}
- #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
- #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
+#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
/*-----------------------------------------------------------*/
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
}
+ return xReturn;
+}
+
/*-----------------------------------------------------------*/
- extern BaseType_t xIsPrivileged( void );
- extern void vResetPrivilege( void );
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+#define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
+#define portRESET_PRIVILEGE() vResetPrivilege()
/*-----------------------------------------------------------*/
- #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */
- #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
- #endif
+#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+ #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */
+ #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
+#endif
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
* the source code because to do so would cause other compilers to generate
* warnings. */
- #pragma diag_suppress=Pe191
- #pragma diag_suppress=Pa082
- #pragma diag_suppress=Be006
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
+#pragma diag_suppress=Be006
/*-----------------------------------------------------------*/
- #ifdef __cplusplus
- }
- #endif
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
#endif /* PORTMACRO_H */
diff --git a/portable/IAR/ARM_CRx_No_GIC/port.c b/portable/IAR/ARM_CRx_No_GIC/port.c
index d436fc5..e84773b 100644
--- a/portable/IAR/ARM_CRx_No_GIC/port.c
+++ b/portable/IAR/ARM_CRx_No_GIC/port.c
@@ -33,50 +33,50 @@
#include "task.h"
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
+ #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
#endif
#ifndef configCLEAR_TICK_INTERRUPT
- #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
+ #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
#endif
/* A critical section is exited when the critical section nesting count reaches
- * this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* Tasks are not created with a floating point context, but can be given a
- * floating point context after they have been created. A variable is stored as
- * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
- * does not have an FPU context, or any other value if the task does have an FPU
- * context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
- * mode. */
-#define portAPSR_USER_MODE ( 0x10 )
+mode. */
+#define portAPSR_USER_MODE ( 0x10 )
/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/*-----------------------------------------------------------*/
@@ -95,21 +95,21 @@
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
- * variable has to be stored as part of the task context and must be initialised to
- * a non zero value to ensure interrupts don't inadvertently become unmasked before
- * the scheduler starts. As it is stored as part of the task context it will
- * automatically be set to 0 when the first task is started. */
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
- * a floating point context must be saved and restored for the task. */
+a floating point context must be saved and restored for the task. */
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
volatile uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
- * if the nesting depth is 0. */
+if the nesting depth is 0. */
volatile uint32_t ulPortInterruptNesting = 0UL;
/*-----------------------------------------------------------*/
@@ -117,204 +117,200 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro.
- *
- * The fist real value on the stack is the status register, which is set for
- * system mode, with interrupts enabled. A few NULLs are added first to ensure
- * GDB does not try decoding a non-existent return address. */
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro.
- if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
- {
- /* The task will start in THUMB mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ The fist real value on the stack is the status register, which is set for
+ system mode, with interrupts enabled. A few NULLs are added first to ensure
+ GDB does not try decoding a non-existent return address. */
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- pxTopOfStack--;
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+ {
+ /* The task will start in THUMB mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
- /* Next the return address, which in this case is the start of the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
+ pxTopOfStack--;
- /* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* Next the return address, which in this case is the start of the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
- /* The task will start with a critical nesting count of 0 as interrupts are
- * enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
+ /* Next all the registers other than the stack pointer. */
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The task will start without a floating point context. A task that uses
- * the floating point hardware must call vPortTaskUsesFPU() before executing
- * any floating point instructions. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
- return pxTopOfStack;
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( ulPortInterruptNesting == ~0UL );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulPortInterruptNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- uint32_t ulAPSR;
+uint32_t ulAPSR;
- /* Only continue if the CPU is not in User mode. The CPU must be in a
- * Privileged mode for the scheduler to start. */
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+ /* Only continue if the CPU is not in User mode. The CPU must be in a
+ Privileged mode for the scheduler to start. */
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+ configASSERT( ulAPSR != portAPSR_USER_MODE );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
- configASSERT( ulAPSR != portAPSR_USER_MODE );
+ if( ulAPSR != portAPSR_USER_MODE )
+ {
+ /* Start the timer that generates the tick ISR. */
+ portDISABLE_INTERRUPTS();
+ configSETUP_TICK_INTERRUPT();
- if( ulAPSR != portAPSR_USER_MODE )
- {
- /* Start the timer that generates the tick ISR. */
- portDISABLE_INTERRUPTS();
- configSETUP_TICK_INTERRUPT();
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
- /* Start the first task executing. */
- vPortRestoreTaskContext();
- }
-
- /* Will only get here if vTaskStartScheduler() was called with the CPU in
- * a non-privileged mode or the binary point register was not set to its lowest
- * possible value. prvTaskExitError() is referenced to prevent a compiler
- * warning about it being defined but not referenced in the case that the user
- * defines their own exit address. */
- ( void ) prvTaskExitError;
- return 0;
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in
+ a non-privileged mode or the binary point register was not set to its lowest
+ possible value. prvTaskExitError() is referenced to prevent a compiler
+ warning about it being defined but not referenced in the case that the user
+ defines their own exit address. */
+ ( void ) prvTaskExitError;
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- portDISABLE_INTERRUPTS();
+ portDISABLE_INTERRUPTS();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( ulCriticalNesting == 1 )
- {
- configASSERT( ulPortInterruptNesting == 0 );
- }
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ulCriticalNesting == 1 )
+ {
+ configASSERT( ulPortInterruptNesting == 0 );
+ }
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- * exited. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then all interrupt
- * priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- * should be unmasked. */
- portENABLE_INTERRUPTS();
- }
- }
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portENABLE_INTERRUPTS();
+ }
+ }
}
/*-----------------------------------------------------------*/
void FreeRTOS_Tick_Handler( void )
{
- uint32_t ulInterruptStatus;
+uint32_t ulInterruptStatus;
- ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ulPortYieldRequired = pdTRUE;
- }
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ulPortYieldRequired = pdTRUE;
+ }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
- configCLEAR_TICK_INTERRUPT();
+ configCLEAR_TICK_INTERRUPT();
}
/*-----------------------------------------------------------*/
void vPortTaskUsesFPU( void )
{
- uint32_t ulInitialFPSCR = 0;
+uint32_t ulInitialFPSCR = 0;
- /* A task is registering the fact that it needs an FPU context. Set the
- * FPU flag (which is saved as part of the task context). */
- ulPortTaskHasFPUContext = pdTRUE;
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ulPortTaskHasFPUContext = pdTRUE;
- /* Initialise the floating point status register. */
- __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) );
+ /* Initialise the floating point status register. */
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
}
/*-----------------------------------------------------------*/
+
+
diff --git a/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/portable/IAR/ARM_CRx_No_GIC/portmacro.h
index 7ffd835..99fc18d 100644
--- a/portable/IAR/ARM_CRx_No_GIC/portmacro.h
+++ b/portable/IAR/ARM_CRx_No_GIC/portmacro.h
@@ -26,13 +26,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include <intrinsics.h>
+#include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -45,139 +45,137 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Task utilities. */
/* Called at the end of an ISR that can cause a context switch. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern volatile uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{ \
+extern volatile uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+}
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
- #define portYIELD() \
- __asm volatile ( "SWI 0 \n"\
- "ISB ");
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0 \n" \
+ "ISB " );
/*-----------------------------------------------------------
-* Critical section control
-*----------------------------------------------------------*/
+ * Critical section control
+ *----------------------------------------------------------*/
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern uint32_t ulPortSetInterruptMask( void );
- extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
- extern void vPortInstallFreeRTOSVectorTable( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
/* The I bit within the CPSR. */
- #define portINTERRUPT_ENABLE_BIT ( 1 << 7 )
+#define portINTERRUPT_ENABLE_BIT ( 1 << 7 )
/* In the absence of a priority mask register, these functions and macros
- * globally enable and disable interrupts. */
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
- #define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n");
- #define portDISABLE_INTERRUPTS() \
- __asm volatile ( "CPSID i \n" \
- "DSB \n" \
- "ISB ");
- #pragma inline
- static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
- {
- volatile uint32_t ulCPSR;
+globally enable and disable interrupts. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" );
+#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \
+ "DSB \n" \
+ "ISB " );
+#pragma inline
+static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
+{
+volatile uint32_t ulCPSR;
- __asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR ) );
+ __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) );
+ ulCPSR &= portINTERRUPT_ENABLE_BIT;
+ portDISABLE_INTERRUPTS();
+ return ulCPSR;
+}
- ulCPSR &= portINTERRUPT_ENABLE_BIT;
- portDISABLE_INTERRUPTS();
- return ulCPSR;
- }
-
- #define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) if( x == 0 ) portENABLE_INTERRUPTS()
+#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) if( x == 0 ) portENABLE_INTERRUPTS()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not required for this port but included in case common demo code that uses these
- * macros is used. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
- * handler for whichever peripheral is used to generate the RTOS tick. */
- void FreeRTOS_Tick_Handler( void );
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- * before any floating point instructions are executed. */
- void vPortTaskUsesFPU( void );
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
- #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
- #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
- #define portNOP() __asm volatile ( "NOP" )
- #define portINLINE inline
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE inline
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
- * the source code because to do so would cause other compilers to generate
- * warnings. */
- #pragma diag_suppress=Pe191
- #pragma diag_suppress=Pa082
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
- #ifdef __cplusplus
- } /* extern C */
- #endif
+#ifdef __cplusplus
+ } /* extern C */
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/ATMega323/port.c b/portable/IAR/ATMega323/port.c
index 3f44886..bc9ce9f 100644
--- a/portable/IAR/ATMega323/port.c
+++ b/portable/IAR/ATMega323/port.c
@@ -31,25 +31,25 @@
#include "task.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the AVR/IAR port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the AVR/IAR port.
+ *----------------------------------------------------------*/
/* Start tasks with interrupts enables. */
-#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
/* Hardware constants for timer 1. */
-#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 )
-#define portPRESCALE_64 ( ( uint8_t ) 0x03 )
-#define portCLOCK_PRESCALER ( ( uint32_t ) 64 )
-#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 )
+#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 )
+#define portPRESCALE_64 ( ( uint8_t ) 0x03 )
+#define portCLOCK_PRESCALER ( ( uint32_t ) 64 )
+#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 )
/* The number of bytes used on the hardware stack by the task start address. */
-#define portBYTES_USED_BY_RETURN_ADDRESS ( 2 )
+#define portBYTES_USED_BY_RETURN_ADDRESS ( 2 )
/*-----------------------------------------------------------*/
/* Stores the critical section nesting. This must not be initialised to 0.
- * It will be initialised when a task starts. */
-#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 )
+It will be initialised when a task starts. */
+#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 )
UBaseType_t uxCriticalNesting = 0x50;
@@ -70,187 +70,186 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint16_t usAddress;
- StackType_t * pxTopOfHardwareStack;
+uint16_t usAddress;
+StackType_t *pxTopOfHardwareStack;
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging. */
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
- *pxTopOfStack = 0x11;
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
- pxTopOfStack--;
+ *pxTopOfStack = 0x11;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack--;
- /* Remember where the top of the hardware stack is - this is required
- * below. */
- pxTopOfHardwareStack = pxTopOfStack;
+ /* Remember where the top of the hardware stack is - this is required
+ below. */
+ pxTopOfHardwareStack = pxTopOfStack;
- /* Simulate how the stack would look after a call to vPortYield(). */
+ /* Simulate how the stack would look after a call to vPortYield(). */
- /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
- /* The IAR compiler requires two stacks per task. First there is the
- * hardware call stack which uses the AVR stack pointer. Second there is the
- * software stack (local variables, parameter passing, etc.) which uses the
- * AVR Y register.
- *
- * This function places both stacks within the memory block passed in as the
- * first parameter. The hardware stack is placed at the bottom of the memory
- * block. A gap is then left for the hardware stack to grow. Next the software
- * stack is placed. The amount of space between the software and hardware
- * stacks is defined by configCALL_STACK_SIZE.
- *
- *
- *
- * The first part of the stack is the hardware stack. Place the start
- * address of the task on the hardware stack. */
- usAddress = ( uint16_t ) pxCode;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
+ /* The IAR compiler requires two stacks per task. First there is the
+ hardware call stack which uses the AVR stack pointer. Second there is the
+ software stack (local variables, parameter passing, etc.) which uses the
+ AVR Y register.
- usAddress >>= 8;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
-
-
- /* Leave enough space for the hardware stack before starting the software
- * stack. The '- 2' is because we have already used two spaces for the
- * address of the start of the task. */
- pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );
+ This function places both stacks within the memory block passed in as the
+ first parameter. The hardware stack is placed at the bottom of the memory
+ block. A gap is then left for the hardware stack to grow. Next the software
+ stack is placed. The amount of space between the software and hardware
+ stacks is defined by configCALL_STACK_SIZE.
- /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
- * portSAVE_CONTEXT places the flags on the stack immediately after r0
- * to ensure the interrupts get disabled as soon as possible, and so ensuring
- * the stack use is minimal should a context switch interrupt occur. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = portFLAGS_INT_ENABLED;
- pxTopOfStack--;
+ The first part of the stack is the hardware stack. Place the start
+ address of the task on the hardware stack. */
+ usAddress = ( uint16_t ) pxCode;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
- /* Next place the address of the hardware stack. This is required so
- * the AVR stack pointer can be restored to point to the hardware stack. */
- pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;
- usAddress = ( uint16_t ) pxTopOfHardwareStack;
+ usAddress >>= 8;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
- /* SPL */
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
- /* SPH */
- usAddress >>= 8;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
+ /* Leave enough space for the hardware stack before starting the software
+ stack. The '- 2' is because we have already used two spaces for the
+ address of the start of the task. */
+ pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );
- /* Now the remaining registers. */
- *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
- pxTopOfStack--;
+ /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+ portSAVE_CONTEXT places the flags on the stack immediately after r0
+ to ensure the interrupts get disabled as soon as possible, and so ensuring
+ the stack use is minimal should a context switch interrupt occur. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = portFLAGS_INT_ENABLED;
+ pxTopOfStack--;
- /* Place the parameter on the stack in the expected location. */
- usAddress = ( uint16_t ) pvParameters;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
+ /* Next place the address of the hardware stack. This is required so
+ the AVR stack pointer can be restored to point to the hardware stack. */
+ pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;
+ usAddress = ( uint16_t ) pxTopOfHardwareStack;
- usAddress >>= 8;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
+ /* SPL */
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
- pxTopOfStack--;
+ /* SPH */
+ usAddress >>= 8;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
- /* The Y register is not stored as it is used as the software stack and
- * gets saved into the task control block. */
- *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
- pxTopOfStack--;
- *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */
- /*lint +e950 +e611 +e923 */
+ /* Now the remaining registers. */
+ *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
+ pxTopOfStack--;
- return pxTopOfStack;
+ /* Place the parameter on the stack in the expected location. */
+ usAddress = ( uint16_t ) pvParameters;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
+
+ usAddress >>= 8;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
+ pxTopOfStack--;
+
+ /* The Y register is not stored as it is used as the software stack and
+ gets saved into the task control block. */
+
+ *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
+
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */
+
+ /*lint +e950 +e611 +e923 */
+
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup the hardware to generate the tick. */
- prvSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. */
+ prvSetupTimerInterrupt();
- /* Restore the context of the first task that is going to run.
- * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
- * compiler does not fully support inline assembler we have to make a call.*/
- vPortStart();
+ /* Restore the context of the first task that is going to run.
+ Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
+ compiler does not fully support inline assembler we have to make a call.*/
+ vPortStart();
- /* Should not get here! */
- return pdTRUE;
+ /* Should not get here! */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the AVR port will get stopped. If required simply
- * disable the tick interrupt here. */
+ /* It is unlikely that the AVR port will get stopped. If required simply
+ disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@@ -259,81 +258,82 @@
*/
static void prvSetupTimerInterrupt( void )
{
- uint32_t ulCompareMatch;
- uint8_t ucHighByte, ucLowByte;
+uint32_t ulCompareMatch;
+uint8_t ucHighByte, ucLowByte;
- /* Using 16bit timer 1 to generate the tick. Correct fuses must be
- * selected for the configCPU_CLOCK_HZ clock. */
+ /* Using 16bit timer 1 to generate the tick. Correct fuses must be
+ selected for the configCPU_CLOCK_HZ clock. */
- ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
- /* We only have 16 bits so have to scale to get our required tick rate. */
- ulCompareMatch /= portCLOCK_PRESCALER;
+ /* We only have 16 bits so have to scale to get our required tick rate. */
+ ulCompareMatch /= portCLOCK_PRESCALER;
- /* Adjust for correct value. */
- ulCompareMatch -= ( uint32_t ) 1;
+ /* Adjust for correct value. */
+ ulCompareMatch -= ( uint32_t ) 1;
- /* Setup compare match value for compare match A. Interrupts are disabled
- * before this is called so we need not worry here. */
- ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
- ulCompareMatch >>= 8;
- ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
- OCR1AH = ucHighByte;
- OCR1AL = ucLowByte;
+ /* Setup compare match value for compare match A. Interrupts are disabled
+ before this is called so we need not worry here. */
+ ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+ ulCompareMatch >>= 8;
+ ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+ OCR1AH = ucHighByte;
+ OCR1AL = ucLowByte;
- /* Setup clock source and compare match behaviour. */
- ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
- TCCR1B = ucLowByte;
+ /* Setup clock source and compare match behaviour. */
+ ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
+ TCCR1B = ucLowByte;
- /* Enable the interrupt - this is okay as interrupt are currently globally
- * disabled. */
- TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+ /* Enable the interrupt - this is okay as interrupt are currently globally
+ disabled. */
+ TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
}
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 1
-/*
- * Tick ISR for preemptive scheduler. We can use a __task attribute as
- * the context is saved at the start of vPortYieldFromTick(). The tick
- * count is incremented after the context is saved.
- */
- __task void SIG_OUTPUT_COMPARE1A( void )
- {
- vPortYieldFromTick();
- asm ( "reti" );
- }
+ /*
+ * Tick ISR for preemptive scheduler. We can use a __task attribute as
+ * the context is saved at the start of vPortYieldFromTick(). The tick
+ * count is incremented after the context is saved.
+ */
+ __task void SIG_OUTPUT_COMPARE1A( void )
+ {
+ vPortYieldFromTick();
+ asm( "reti" );
+ }
#else
-/*
- * Tick ISR for the cooperative scheduler. All this does is increment the
- * tick count. We don't need to switch context, this can only be done by
- * manual calls to taskYIELD();
- *
- * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL
- * IT HERE USING THE USUAL PRAGMA.
- */
- __interrupt void SIG_OUTPUT_COMPARE1A( void )
- {
- xTaskIncrementTick();
- }
-#endif /* if configUSE_PREEMPTION == 1 */
+ /*
+ * Tick ISR for the cooperative scheduler. All this does is increment the
+ * tick count. We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ *
+ * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL
+ * IT HERE USING THE USUAL PRAGMA.
+ */
+ __interrupt void SIG_OUTPUT_COMPARE1A( void )
+ {
+ xTaskIncrementTick();
+ }
+#endif
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- uxCriticalNesting--;
-
- if( uxCriticalNesting == portNO_CRITICAL_NESTING )
- {
- portENABLE_INTERRUPTS();
- }
+ uxCriticalNesting--;
+ if( uxCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ portENABLE_INTERRUPTS();
+ }
}
+
+
diff --git a/portable/IAR/ATMega323/portmacro.h b/portable/IAR/ATMega323/portmacro.h
index df8358f..4b7f125 100644
--- a/portable/IAR/ATMega323/portmacro.h
+++ b/portable/IAR/ATMega323/portmacro.h
@@ -26,18 +26,18 @@
*/
/*
- * Changes from V1.2.3
- *
- + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
- + base 16.
- */
+Changes from V1.2.3
+
+ + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
+ base 16.
+*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -50,61 +50,63 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT int
- #define portSTACK_TYPE uint8_t
- #define portBASE_TYPE char
- #define portPOINTER_SIZE_TYPE uint16_t
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
+#define portPOINTER_SIZE_TYPE uint16_t
- typedef portSTACK_TYPE StackType_t;
- typedef signed char BaseType_t;
- typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
- #define portDISABLE_INTERRUPTS() asm ( "cli" )
- #define portENABLE_INTERRUPTS() asm ( "sei" )
+#define portDISABLE_INTERRUPTS() asm( "cli" )
+#define portENABLE_INTERRUPTS() asm( "sei" )
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 1
- #define portNOP() asm ( "nop" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 1
+#define portNOP() asm( "nop" )
/*-----------------------------------------------------------*/
/* Kernel utilities. */
- void vPortYield( void );
- #define portYIELD() vPortYield()
+void vPortYield( void );
+#define portYIELD() vPortYield()
- #ifdef IAR_MEGA_AVR
- #define outb( PORT, VALUE ) PORT = VALUE
- #endif
+#ifdef IAR_MEGA_AVR
+ #define outb( PORT, VALUE ) PORT = VALUE
+#endif
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
+
diff --git a/portable/IAR/AVR32_UC3/port.c b/portable/IAR/AVR32_UC3/port.c
index 5b4e0e9..4b71888 100644
--- a/portable/IAR/AVR32_UC3/port.c
+++ b/portable/IAR/AVR32_UC3/port.c
@@ -1,5 +1,4 @@
/*This file has been prepared for Doxygen automatic documentation generation.*/
-
/*! \file *********************************************************************
*
* \brief FreeRTOS port source for AVR32 UC3.
@@ -51,26 +50,26 @@
#include "gpio.h"
#if configDBG
- #include "usart.h"
+ #include "usart.h"
#endif
-#if ( configTICK_USE_TC == 1 )
- #include "tc.h"
+#if( configTICK_USE_TC==1 )
+ #include "tc.h"
#endif
/* Constants required to setup the task context. */
-#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 )
+#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 )
/* Each task maintains its own critical nesting variable. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
volatile uint32_t ulCriticalNesting = 9999UL;
-#if ( configTICK_USE_TC == 0 )
- static void prvScheduleNextTick( void );
+#if( configTICK_USE_TC==0 )
+ static void prvScheduleNextTick( void );
#else
- static void prvClearTcInt( void );
+ static void prvClearTcInt( void );
#endif
/* Setup the timer to generate the tick interrupts. */
@@ -82,149 +81,145 @@
* Low-level initialization routine called during startup, before the main
* function.
*/
-int __low_level_init( void )
+int __low_level_init(void)
{
- #if configHEAP_INIT
- #pragma segment = "HEAP"
- BaseType_t * pxMem;
- #endif
+ #if configHEAP_INIT
+ #pragma segment = "HEAP"
+ BaseType_t *pxMem;
+ #endif
- /* Enable exceptions. */
- ENABLE_ALL_EXCEPTIONS();
+ /* Enable exceptions. */
+ ENABLE_ALL_EXCEPTIONS();
- /* Initialize interrupt handling. */
- INTC_init_interrupts();
+ /* Initialize interrupt handling. */
+ INTC_init_interrupts();
- #if configHEAP_INIT
- {
- /* Initialize the heap used by malloc. */
- for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); )
- {
- *pxMem++ = 0xA5A5A5A5;
- }
- }
- #endif
+ #if configHEAP_INIT
+ {
+ /* Initialize the heap used by malloc. */
+ for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); )
+ {
+ *pxMem++ = 0xA5A5A5A5;
+ }
+ }
+ #endif
- /* Code section present if and only if the debug trace is activated. */
- #if configDBG
- {
- static const gpio_map_t DBG_USART_GPIO_MAP =
- {
- { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
- { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
- };
+ /* Code section present if and only if the debug trace is activated. */
+ #if configDBG
+ {
+ static const gpio_map_t DBG_USART_GPIO_MAP =
+ {
+ { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
+ { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
+ };
- static const usart_options_t DBG_USART_OPTIONS =
- {
- .baudrate = configDBG_USART_BAUDRATE,
- .charlength = 8,
- .paritytype = USART_NO_PARITY,
- .stopbits = USART_1_STOPBIT,
- .channelmode = USART_NORMAL_CHMODE
- };
+ static const usart_options_t DBG_USART_OPTIONS =
+ {
+ .baudrate = configDBG_USART_BAUDRATE,
+ .charlength = 8,
+ .paritytype = USART_NO_PARITY,
+ .stopbits = USART_1_STOPBIT,
+ .channelmode = USART_NORMAL_CHMODE
+ };
- /* Initialize the USART used for the debug trace with the configured parameters. */
- extern volatile avr32_usart_t * volatile stdio_usart_base;
- stdio_usart_base = configDBG_USART;
- gpio_enable_module( DBG_USART_GPIO_MAP,
- sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) );
- usart_init_rs232( configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ );
- }
- #endif /* if configDBG */
+ /* Initialize the USART used for the debug trace with the configured parameters. */
+ extern volatile avr32_usart_t *volatile stdio_usart_base;
+ stdio_usart_base = configDBG_USART;
+ gpio_enable_module( DBG_USART_GPIO_MAP,
+ sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
+ usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
+ }
+ #endif
- /* Request initialization of data segments. */
- return 1;
+ /* Request initialization of data segments. */
+ return 1;
}
/*-----------------------------------------------------------*/
/* Added as there is no such function in FreeRTOS. */
-void * pvPortRealloc( void * pv,
- size_t xWantedSize )
+void *pvPortRealloc( void *pv, size_t xWantedSize )
{
- void * pvReturn;
+void *pvReturn;
- vTaskSuspendAll();
- {
- pvReturn = realloc( pv, xWantedSize );
- }
- xTaskResumeAll();
+ vTaskSuspendAll();
+ {
+ pvReturn = realloc( pv, xWantedSize );
+ }
+ xTaskResumeAll();
- return pvReturn;
+ return pvReturn;
}
/*-----------------------------------------------------------*/
/* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick. */
-
+simply increment the system tick. */
/* The preemptive scheduler is defined as "naked" as the full context is saved
- * on entry as part of the context switch. */
-#pragma shadow_registers = full /* Naked. */
+on entry as part of the context switch. */
+#pragma shadow_registers = full // Naked.
static void vTick( void )
{
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT_OS_INT();
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT_OS_INT();
- #if ( configTICK_USE_TC == 1 )
- /* Clear the interrupt flag. */
- prvClearTcInt();
- #else
+ #if( configTICK_USE_TC==1 )
+ /* Clear the interrupt flag. */
+ prvClearTcInt();
+ #else
+ /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+ clock cycles from now. */
+ prvScheduleNextTick();
+ #endif
- /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
- * clock cycles from now. */
- prvScheduleNextTick();
- #endif
+ /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+ calls in a critical section . */
+ portENTER_CRITICAL();
+ xTaskIncrementTick();
+ portEXIT_CRITICAL();
- /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
- * calls in a critical section . */
- portENTER_CRITICAL();
- xTaskIncrementTick();
- portEXIT_CRITICAL();
-
- /* Restore the context of the "elected task". */
- portRESTORE_CONTEXT_OS_INT();
+ /* Restore the context of the "elected task". */
+ portRESTORE_CONTEXT_OS_INT();
}
/*-----------------------------------------------------------*/
-#pragma shadow_registers = full /* Naked. */
+#pragma shadow_registers = full // Naked.
void SCALLYield( void )
{
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT_SCALL();
- vTaskSwitchContext();
- portRESTORE_CONTEXT_SCALL();
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT_SCALL();
+ vTaskSwitchContext();
+ portRESTORE_CONTEXT_SCALL();
}
/*-----------------------------------------------------------*/
/* The code generated by the GCC compiler uses the stack in different ways at
- * different optimisation levels. The interrupt flags can therefore not always
- * be saved to the stack. Instead the critical section nesting level is stored
- * in a variable, which is then saved as part of the stack context. */
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
#pragma optimize = no_inline
void vPortEnterCritical( void )
{
- /* Disable interrupts */
- portDISABLE_INTERRUPTS();
+ /* Disable interrupts */
+ portDISABLE_INTERRUPTS();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
#pragma optimize = no_inline
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- ulCriticalNesting--;
-
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable all interrupt/exception. */
- portENABLE_INTERRUPTS();
- }
- }
+ if(ulCriticalNesting > portNO_CRITICAL_NESTING)
+ {
+ ulCriticalNesting--;
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable all interrupt/exception. */
+ portENABLE_INTERRUPTS();
+ }
+ }
}
/*-----------------------------------------------------------*/
@@ -234,184 +229,178 @@
*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* When the task starts, it will expect to find the function parameter in R12. */
- pxTopOfStack--;
- *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */
- *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */
- *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */
- *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */
- *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */
- *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */
- *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
- *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */
- *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */
- *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */
- *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */
- *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */
- *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */
- *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
- *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
- *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
+ /* When the task starts, it will expect to find the function parameter in R12. */
+ pxTopOfStack--;
+ *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */
+ *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */
+ *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */
+ *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */
+ *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */
+ *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */
+ *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
+ *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */
+ *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */
+ *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */
+ *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */
+ *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */
+ *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */
+ *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
+ *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
+ *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- portRESTORE_CONTEXT();
+ /* Start the first task. */
+ portRESTORE_CONTEXT();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the AVR32 port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the AVR32 port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
- * clock cycles from now. */
-#if ( configTICK_USE_TC == 0 )
- static void prvScheduleFirstTick( void )
- {
- uint32_t lCycles;
+clock cycles from now. */
+#if( configTICK_USE_TC==0 )
+ static void prvScheduleFirstTick(void)
+ {
+ uint32_t lCycles;
- lCycles = Get_system_register( AVR32_COUNT );
- lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+ lCycles = Get_system_register(AVR32_COUNT);
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+ // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+ // generation feature does not get disabled.
+ if(0 == lCycles)
+ {
+ lCycles++;
+ }
+ Set_system_register(AVR32_COMPARE, lCycles);
+ }
+
+ #pragma optimize = no_inline
+ static void prvScheduleNextTick(void)
+ {
+ uint32_t lCycles, lCount;
- /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
- /* generation feature does not get disabled. */
- if( 0 == lCycles )
- {
- lCycles++;
- }
-
- Set_system_register( AVR32_COMPARE, lCycles );
- }
-
- #pragma optimize = no_inline
- static void prvScheduleNextTick( void )
- {
- uint32_t lCycles, lCount;
-
- lCycles = Get_system_register( AVR32_COMPARE );
- lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
-
- /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
- /* generation feature does not get disabled. */
- if( 0 == lCycles )
- {
- lCycles++;
- }
-
- lCount = Get_system_register( AVR32_COUNT );
-
- if( lCycles < lCount )
- { /* We missed a tick, recover for the next. */
- lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
- }
-
- Set_system_register( AVR32_COMPARE, lCycles );
- }
-#else /* if ( configTICK_USE_TC == 0 ) */
- #pragma optimize = no_inline
- static void prvClearTcInt( void )
- {
- AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr;
- }
-#endif /* if ( configTICK_USE_TC == 0 ) */
+ lCycles = Get_system_register(AVR32_COMPARE);
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+ // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+ // generation feature does not get disabled.
+ if(0 == lCycles)
+ {
+ lCycles++;
+ }
+ lCount = Get_system_register(AVR32_COUNT);
+ if( lCycles < lCount )
+ { // We missed a tick, recover for the next.
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+ }
+ Set_system_register(AVR32_COMPARE, lCycles);
+ }
+#else
+ #pragma optimize = no_inline
+ static void prvClearTcInt(void)
+ {
+ AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
+ }
+#endif
/*-----------------------------------------------------------*/
/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void )
+static void prvSetupTimerInterrupt(void)
{
- #if ( configTICK_USE_TC == 1 )
- volatile avr32_tc_t * tc = &AVR32_TC;
+ #if( configTICK_USE_TC==1 )
- /* Options for waveform genration. */
- tc_waveform_opt_t waveform_opt =
- {
- .channel = configTICK_TC_CHANNEL, /* Channel selection. */
+ volatile avr32_tc_t *tc = &AVR32_TC;
- .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
- .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
- .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
- .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
+ // Options for waveform genration.
+ tc_waveform_opt_t waveform_opt =
+ {
+ .channel = configTICK_TC_CHANNEL, /* Channel selection. */
- .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
- .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
- .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
- .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
+ .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
+ .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
+ .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
+ .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
- .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode without automatic trigger on RC compare. */
- .enetrg = FALSE, /* External event trigger enable. */
- .eevt = 0, /* External event selection. */
- .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
- .cpcdis = FALSE, /* Counter disable when RC compare. */
- .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
+ .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
+ .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
+ .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
+ .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
- .burst = FALSE, /* Burst signal selection. */
- .clki = FALSE, /* Clock inversion. */
- .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
- };
+ .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
+ .enetrg = FALSE, /* External event trigger enable. */
+ .eevt = 0, /* External event selection. */
+ .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
+ .cpcdis = FALSE, /* Counter disable when RC compare. */
+ .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
- tc_interrupt_t tc_interrupt =
- {
- .etrgs = 0,
- .ldrbs = 0,
- .ldras = 0,
- .cpcs = 1,
- .cpbs = 0,
- .cpas = 0,
- .lovrs = 0,
- .covfs = 0,
- };
- #endif /* if ( configTICK_USE_TC == 1 ) */
+ .burst = FALSE, /* Burst signal selection. */
+ .clki = FALSE, /* Clock inversion. */
+ .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
+ };
- /* Disable all interrupt/exception. */
- portDISABLE_INTERRUPTS();
+ tc_interrupt_t tc_interrupt =
+ {
+ .etrgs=0,
+ .ldrbs=0,
+ .ldras=0,
+ .cpcs =1,
+ .cpbs =0,
+ .cpas =0,
+ .lovrs=0,
+ .covfs=0,
+ };
- /* Register the compare interrupt handler to the interrupt controller and
- * enable the compare interrupt. */
+ #endif
- #if ( configTICK_USE_TC == 1 )
- {
- INTC_register_interrupt( ( __int_handler ) & vTick, configTICK_TC_IRQ, INT0 );
+ /* Disable all interrupt/exception. */
+ portDISABLE_INTERRUPTS();
- /* Initialize the timer/counter. */
- tc_init_waveform( tc, &waveform_opt );
+ /* Register the compare interrupt handler to the interrupt controller and
+ enable the compare interrupt. */
- /* Set the compare triggers.
- * Remember TC counter is 16-bits, so counting second is not possible!
- * That's why we configure it to count ms. */
- tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ );
+ #if( configTICK_USE_TC==1 )
+ {
+ INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
- tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
+ /* Initialize the timer/counter. */
+ tc_init_waveform(tc, &waveform_opt);
- /* Start the timer/counter. */
- tc_start( tc, configTICK_TC_CHANNEL );
- }
- #else /* if ( configTICK_USE_TC == 1 ) */
- {
- INTC_register_interrupt( ( __int_handler ) & vTick, AVR32_CORE_COMPARE_IRQ, INT0 );
- prvScheduleFirstTick();
- }
- #endif /* if ( configTICK_USE_TC == 1 ) */
+ /* Set the compare triggers.
+ Remember TC counter is 16-bits, so counting second is not possible!
+ That's why we configure it to count ms. */
+ tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
+
+ tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
+
+ /* Start the timer/counter. */
+ tc_start(tc, configTICK_TC_CHANNEL);
+ }
+ #else
+ {
+ INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
+ prvScheduleFirstTick();
+ }
+ #endif
}
diff --git a/portable/IAR/AVR32_UC3/portmacro.h b/portable/IAR/AVR32_UC3/portmacro.h
index 27f5e6c..ef7d1df 100644
--- a/portable/IAR/AVR32_UC3/portmacro.h
+++ b/portable/IAR/AVR32_UC3/portmacro.h
@@ -1,5 +1,4 @@
/*This file has been prepared for Doxygen automatic documentation generation.*/
-
/*! \file *********************************************************************
*
* \brief FreeRTOS port header for AVR32 UC3.
@@ -43,7 +42,7 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
@@ -54,63 +53,63 @@
* These settings should not be altered.
*-----------------------------------------------------------
*/
- #include <avr32/io.h>
- #include "intc.h"
- #include "compiler.h"
+#include <avr32/io.h>
+#include "intc.h"
+#include "compiler.h"
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #define TASK_DELAY_MS( x ) ( ( x ) / portTICK_PERIOD_MS )
- #define TASK_DELAY_S( x ) ( ( x ) * 1000 / portTICK_PERIOD_MS )
- #define TASK_DELAY_MIN( x ) ( ( x ) * 60 * 1000 / portTICK_PERIOD_MS )
+#define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS )
+#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS )
+#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS )
- #define configTICK_TC_IRQ ATPASTE2( AVR32_TC_IRQ, configTICK_TC_CHANNEL )
+#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 4
- #define portNOP() { __asm__ __volatile__ ( "nop" ); }
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() {__asm__ __volatile__ ("nop");}
/*-----------------------------------------------------------*/
/*-----------------------------------------------------------*/
/* INTC-specific. */
- #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
- #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
+#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
+#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
- #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
- #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
+#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
+#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
- #define DISABLE_INT_LEVEL( int_lev ) Disable_interrupt_level( int_lev )
- #define ENABLE_INT_LEVEL( int_lev ) Enable_interrupt_level( int_lev )
+#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
+#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
/*
@@ -126,33 +125,32 @@
* SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
* which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
*/
- #if configDBG
- #define portDBG_TRACE( ... ) \
- { \
- fputs( __FILE__ ":" ASTRINGZ( __LINE__ ) ": ", stdout ); \
- printf( __VA_ARGS__ ); \
- fputs( "\r\n", stdout ); \
- }
- #else
- #define portDBG_TRACE( ... )
- #endif
+#if configDBG
+ #define portDBG_TRACE(...) \
+ { \
+ fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \
+ printf(__VA_ARGS__); \
+ fputs("\r\n", stdout); \
+ }
+#else
+ #define portDBG_TRACE(...)
+#endif
/* Critical section management. */
- #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
- #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
+#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
+#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
/* Added as there is no such function in FreeRTOS. */
- extern void * pvPortRealloc( void * pv,
- size_t xSize );
+extern void *pvPortRealloc( void *pv, size_t xSize );
/*-----------------------------------------------------------*/
@@ -161,44 +159,44 @@
/*
* Restore Context for cases other than INTi.
*/
- #define portRESTORE_CONTEXT() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- __asm__ __volatile__ ( \
- /* Set SP to point to new stack */ \
- "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "ld.w r0, r8[0] \n\t" \
- "ld.w sp, r0[0] \n\t" \
- \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t" \
- "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "st.w r8[0], r0 \n\t" \
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t" \
- /* R0-R7 should not be used below this line */ \
- /* Skip PC and SR (will do it at the end) */ \
- "sub sp, -2*4 \n\t" \
- /* Restore R8..R12 and LR */ \
- "ldm sp++, r8-r12, lr \n\t" \
- /* Restore SR */ \
- "ld.w r0, sp[-8*4] \n\t"/* R0 is modified, is restored later. */\
- "mtsr "ASTRINGZ ( AVR32_SR ) ", r0 \n\t" \
- /* Restore r0 */ \
- "ld.w r0, sp[-9*4] \n\t"\
- /* Restore PC */ \
- "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
- ); \
- \
- /* Force import of global symbols from assembly */ \
- ulCriticalNesting; \
- pxCurrentTCB; \
- }
+#define portRESTORE_CONTEXT() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ __asm__ __volatile__ ( \
+ /* Set SP to point to new stack */ \
+ "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0] \n\t"\
+ \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t"\
+ "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ /* R0-R7 should not be used below this line */ \
+ /* Skip PC and SR (will do it at the end) */ \
+ "sub sp, -2*4 \n\t"\
+ /* Restore R8..R12 and LR */ \
+ "ldm sp++, r8-r12, lr \n\t"\
+ /* Restore SR */ \
+ "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\
+ "mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\
+ /* Restore r0 */ \
+ "ld.w r0, sp[-9*4] \n\t"\
+ /* Restore PC */ \
+ "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
+ ); \
+ \
+ /* Force import of global symbols from assembly */ \
+ ulCriticalNesting; \
+ pxCurrentTCB; \
+}
/*
@@ -209,168 +207,168 @@
* are not the same between INT0..3 exceptions and the scall exception.
*/
-/* Task context stack layout: */
-/* R8 (*) */
-/* R9 (*) */
-/* R10 (*) */
-/* R11 (*) */
-/* R12 (*) */
-/* R14/LR (*) */
-/* R15/PC (*) */
-/* SR (*) */
-/* R0 */
-/* R1 */
-/* R2 */
-/* R3 */
-/* R4 */
-/* R5 */
-/* R6 */
-/* R7 */
-/* ulCriticalNesting */
-/* (*) automatically done for INT0..INT3, but not for SCALL */
+// Task context stack layout:
+ // R8 (*)
+ // R9 (*)
+ // R10 (*)
+ // R11 (*)
+ // R12 (*)
+ // R14/LR (*)
+ // R15/PC (*)
+ // SR (*)
+ // R0
+ // R1
+ // R2
+ // R3
+ // R4
+ // R5
+ // R6
+ // R7
+ // ulCriticalNesting
+// (*) automatically done for INT0..INT3, but not for SCALL
/*
* The ISR used for the scheduler tick depends on whether the cooperative or
* the preemptive scheduler is being used.
*/
- #if configUSE_PREEMPTION == 0
+#if configUSE_PREEMPTION == 0
/*
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
*/
- #define portSAVE_CONTEXT_OS_INT() \
- { \
- /* Save R0..R7 */ \
- __asm__ __volatile__ ( "stm --sp, r0-r7" ); \
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context save. */ \
- }
+#define portSAVE_CONTEXT_OS_INT() \
+{ \
+ /* Save R0..R7 */ \
+ __asm__ __volatile__ ("stm --sp, r0-r7"); \
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context save. */ \
+}
/*
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
*/
- #define portRESTORE_CONTEXT_OS_INT() \
- { \
- __asm__ __volatile__ ( \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context restore. */ \
- "rete" \
- ); \
- }
+#define portRESTORE_CONTEXT_OS_INT() \
+{ \
+ __asm__ __volatile__ ( \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context restore. */ \
+ "rete" \
+ ); \
+}
- #else /* if configUSE_PREEMPTION == 0 */
+#else
/*
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
*/
- #define portSAVE_CONTEXT_OS_INT() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- /* When we come here */ \
- /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
- \
- __asm__ __volatile__ ( \
- /* Save R0..R7 */ \
- "stm --sp, r0-r7 \n\t" \
- \
- /* Save ulCriticalNesting variable - R0 is overwritten */ \
- "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "ld.w r0, r8[0] \n\t" \
- "st.w --sp, r0 \n\t" \
- \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case we don't want to do a task switch because we don't know what the stack */ \
- /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
- /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
- /* will just be restoring the interrupt handler, no way!!! */ \
- /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
- "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \
- "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \
- "cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */ \
- "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) " \n\t" \
- \
- /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
- /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
- /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
- /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
- /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
- "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "st.w r0[0], sp \n"\
- \
- "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":" \
- ); \
- }
+#define portSAVE_CONTEXT_OS_INT() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* When we come here */ \
+ /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
+ \
+ __asm__ __volatile__ ( \
+ /* Save R0..R7 */ \
+ "stm --sp, r0-r7 \n\t"\
+ \
+ /* Save ulCriticalNesting variable - R0 is overwritten */ \
+ "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w --sp, r0 \n\t"\
+ \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case we don't want to do a task switch because we don't know what the stack */ \
+ /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
+ /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
+ /* will just be restoring the interrupt handler, no way!!! */ \
+ /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
+ "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
+ "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
+ "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+ "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
+ \
+ /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
+ /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
+ /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
+ /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
+ /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
+ "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w r0[0], sp \n"\
+ \
+ "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
+ ); \
+}
/*
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
*/
- #define portRESTORE_CONTEXT_OS_INT() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case we don't want to do a task switch because we don't know what the stack */ \
- /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
- /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
- /* will just be restoring the interrupt handler, no way!!! */ \
- __asm__ __volatile__ ( \
- "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \
- "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \
- "cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */ \
- "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) \
- ); \
- \
- /* Else */ \
- /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
- /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
- portENTER_CRITICAL(); \
- vTaskSwitchContext(); \
- portEXIT_CRITICAL(); \
- \
- /* Restore all registers */ \
- \
- __asm__ __volatile__ ( \
- /* Set SP to point to new stack */ \
- "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "ld.w r0, r8[0] \n\t" \
- "ld.w sp, r0[0] \n" \
- \
- "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ": \n\t" \
- \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t" \
- "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t"\
- "st.w r8[0], r0 \n\t"\
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- /* Now, the stack should be R8..R12, LR, PC and SR */ \
- "rete" \
- ); \
- \
- /* Force import of global symbols from assembly */ \
- ulCriticalNesting; \
- pxCurrentTCB; \
- }
+#define portRESTORE_CONTEXT_OS_INT() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case we don't want to do a task switch because we don't know what the stack */ \
+ /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
+ /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
+ /* will just be restoring the interrupt handler, no way!!! */ \
+ __asm__ __volatile__ ( \
+ "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
+ "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
+ "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+ "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \
+ ); \
+ \
+ /* Else */ \
+ /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
+ /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+ portENTER_CRITICAL(); \
+ vTaskSwitchContext(); \
+ portEXIT_CRITICAL(); \
+ \
+ /* Restore all registers */ \
+ \
+ __asm__ __volatile__ ( \
+ /* Set SP to point to new stack */ \
+ "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0] \n"\
+ \
+ "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
+ \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t"\
+ "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ /* Now, the stack should be R8..R12, LR, PC and SR */ \
+ "rete" \
+ ); \
+ \
+ /* Force import of global symbols from assembly */ \
+ ulCriticalNesting; \
+ pxCurrentTCB; \
+}
- #endif /* if configUSE_PREEMPTION == 0 */
+#endif
/*
@@ -379,278 +377,278 @@
* NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
*
*/
- #define portSAVE_CONTEXT_SCALL() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
- /* If SR[M2:M0] == 001 */ \
- /* PC and SR are on the stack. */ \
- /* Else (other modes) */ \
- /* Nothing on the stack. */ \
- \
- /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
- /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
- /* in an interrupt|exception handler. */ \
- \
- __asm__ __volatile__ ( \
- /* in order to save R0-R7 */ \
- "sub sp, 6*4 \n\t" \
- /* Save R0..R7 */ \
- "stm --sp, r0-r7 \n\t" \
- \
- /* in order to save R8-R12 and LR */ \
- /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
- "sub r7, sp,-16*4 \n\t" \
- /* Copy PC and SR in other places in the stack. */ \
- "ld.w r0, r7[-2*4] \n\t"/* Read SR */ \
- "st.w r7[-8*4], r0 \n\t"/* Copy SR */ \
- "ld.w r0, r7[-1*4] \n\t"/* Read PC */ \
- "st.w r7[-7*4], r0 \n\t"/* Copy PC */ \
- \
- /* Save R8..R12 and LR on the stack. */ \
- "stm --r7, r8-r12, lr \n\t" \
- \
- /* Arriving here we have the following stack organizations: */ \
- /* R8..R12, LR, PC, SR, R0..R7. */ \
- \
- /* Now we can finalize the save. */ \
- \
- /* Save ulCriticalNesting variable - R0 is overwritten */ \
- "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "st.w --sp, r0" \
- ); \
- \
- /* Disable the its which may cause a context switch (i.e. cause a change of */ \
- /* pxCurrentTCB). */ \
- /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
- /* critical section because it is a global structure. */ \
- portENTER_CRITICAL(); \
- \
- /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
- __asm__ __volatile__ ( \
- "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "st.w r0[0], sp" \
- ); \
- }
+#define portSAVE_CONTEXT_SCALL() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
+ /* If SR[M2:M0] == 001 */ \
+ /* PC and SR are on the stack. */ \
+ /* Else (other modes) */ \
+ /* Nothing on the stack. */ \
+ \
+ /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
+ /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
+ /* in an interrupt|exception handler. */ \
+ \
+ __asm__ __volatile__ ( \
+ /* in order to save R0-R7 */ \
+ "sub sp, 6*4 \n\t"\
+ /* Save R0..R7 */ \
+ "stm --sp, r0-r7 \n\t"\
+ \
+ /* in order to save R8-R12 and LR */ \
+ /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
+ "sub r7, sp,-16*4 \n\t"\
+ /* Copy PC and SR in other places in the stack. */ \
+ "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
+ "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
+ "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
+ "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
+ \
+ /* Save R8..R12 and LR on the stack. */ \
+ "stm --r7, r8-r12, lr \n\t"\
+ \
+ /* Arriving here we have the following stack organizations: */ \
+ /* R8..R12, LR, PC, SR, R0..R7. */ \
+ \
+ /* Now we can finalize the save. */ \
+ \
+ /* Save ulCriticalNesting variable - R0 is overwritten */ \
+ "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w --sp, r0" \
+ ); \
+ \
+ /* Disable the its which may cause a context switch (i.e. cause a change of */ \
+ /* pxCurrentTCB). */ \
+ /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
+ /* critical section because it is a global structure. */ \
+ portENTER_CRITICAL(); \
+ \
+ /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
+ __asm__ __volatile__ ( \
+ "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w r0[0], sp" \
+ ); \
+}
/*
* portRESTORE_CONTEXT() for SupervisorCALL exception.
*/
- #define portRESTORE_CONTEXT_SCALL() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- /* Restore all registers */ \
- \
- /* Set SP to point to new stack */ \
- __asm__ __volatile__ ( \
- "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "ld.w r0, r8[0] \n\t"\
- "ld.w sp, r0[0]" \
- ); \
- \
- /* Leave pxCurrentTCB variable access critical section */ \
- portEXIT_CRITICAL(); \
- \
- __asm__ __volatile__ ( \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t" \
- "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "st.w r8[0], r0 \n\t"\
- \
- /* skip PC and SR */ \
- /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
- "sub r7, sp, -10*4 \n\t"\
- /* Restore r8-r12 and LR */ \
- "ldm r7++, r8-r12, lr \n\t"\
- \
- /* RETS will take care of the extra PC and SR restore. */ \
- /* So, we have to prepare the stack for this. */ \
- "ld.w r0, r7[-8*4] \n\t"/* Read SR */\
- "st.w r7[-2*4], r0 \n\t"/* Copy SR */\
- "ld.w r0, r7[-7*4] \n\t"/* Read PC */\
- "st.w r7[-1*4], r0 \n\t"/* Copy PC */\
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- "sub sp, -6*4 \n\t"\
- \
- "rets" \
- ); \
- \
- /* Force import of global symbols from assembly */ \
- ulCriticalNesting; \
- pxCurrentTCB; \
- }
+#define portRESTORE_CONTEXT_SCALL() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* Restore all registers */ \
+ \
+ /* Set SP to point to new stack */ \
+ __asm__ __volatile__ ( \
+ "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0]" \
+ ); \
+ \
+ /* Leave pxCurrentTCB variable access critical section */ \
+ portEXIT_CRITICAL(); \
+ \
+ __asm__ __volatile__ ( \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t"\
+ "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* skip PC and SR */ \
+ /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
+ "sub r7, sp, -10*4 \n\t"\
+ /* Restore r8-r12 and LR */ \
+ "ldm r7++, r8-r12, lr \n\t"\
+ \
+ /* RETS will take care of the extra PC and SR restore. */ \
+ /* So, we have to prepare the stack for this. */ \
+ "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
+ "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
+ "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
+ "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ "sub sp, -6*4 \n\t"\
+ \
+ "rets" \
+ ); \
+ \
+ /* Force import of global symbols from assembly */ \
+ ulCriticalNesting; \
+ pxCurrentTCB; \
+}
/*
* The ISR used depends on whether the cooperative or
* the preemptive scheduler is being used.
*/
- #if configUSE_PREEMPTION == 0
+#if configUSE_PREEMPTION == 0
/*
* ISR entry and exit macros. These are only required if a task switch
* is required from the ISR.
*/
- #define portENTER_SWITCHING_ISR() \
- { \
- /* Save R0..R7 */ \
- __asm__ __volatile__ ( "stm --sp, r0-r7" ); \
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context save. */ \
- }
+#define portENTER_SWITCHING_ISR() \
+{ \
+ /* Save R0..R7 */ \
+ __asm__ __volatile__ ("stm --sp, r0-r7"); \
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context save. */ \
+}
/*
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
*/
- #define portEXIT_SWITCHING_ISR() \
- { \
- __asm__ __volatile__ ( \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context restore. */ \
- "rete" \
- ); \
- }
+#define portEXIT_SWITCHING_ISR() \
+{ \
+ __asm__ __volatile__ ( \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context restore. */ \
+ "rete" \
+ ); \
+}
- #else /* if configUSE_PREEMPTION == 0 */
+#else
/*
* ISR entry and exit macros. These are only required if a task switch
* is required from the ISR.
*/
- #define portENTER_SWITCHING_ISR() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- /* When we come here */ \
- /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
- \
- __asm__ __volatile__ ( \
- /* Save R0..R7 */ \
- "stm --sp, r0-r7 \n\t" \
- \
- /* Save ulCriticalNesting variable - R0 is overwritten */ \
- "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "ld.w r0, r8[0] \n\t" \
- "st.w --sp, r0 \n\t" \
- \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case we don't want to do a task switch because we don't know what the stack */ \
- /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
- /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
- /* will just be restoring the interrupt handler, no way!!! */ \
- /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
- "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \
- "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \
- "cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */ \
- "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) " \n\t" \
- \
- /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
- "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "st.w r0[0], sp \n"\
- \
- "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":" \
- ); \
- }
+#define portENTER_SWITCHING_ISR() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* When we come here */ \
+ /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
+ \
+ __asm__ __volatile__ ( \
+ /* Save R0..R7 */ \
+ "stm --sp, r0-r7 \n\t"\
+ \
+ /* Save ulCriticalNesting variable - R0 is overwritten */ \
+ "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w --sp, r0 \n\t"\
+ \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case we don't want to do a task switch because we don't know what the stack */ \
+ /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
+ /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
+ /* will just be restoring the interrupt handler, no way!!! */ \
+ /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
+ "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
+ "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
+ "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+ "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
+ \
+ /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
+ "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w r0[0], sp \n"\
+ \
+ "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
+ ); \
+}
/*
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
*/
- #define portEXIT_SWITCHING_ISR() \
- { \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void * volatile pxCurrentTCB; \
- \
- __asm__ __volatile__ ( \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
- /* did not previously save SP in its TCB. */ \
- "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \
- "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \
- "cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */ \
- "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) " \n\t" \
- \
- /* If a switch is required then we just need to call */ \
- /* vTaskSwitchContext() as the context has already been */ \
- /* saved. */ \
- "cp.w r12, 1 \n\t"/* Check if Switch context is required. */ \
- "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":C" \
- ); \
- \
- /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
- portENTER_CRITICAL(); \
- vTaskSwitchContext(); \
- portEXIT_CRITICAL(); \
- \
- __asm__ __volatile__ ( \
- "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ": \n\t" \
- /* Restore the context of which ever task is now the highest */ \
- /* priority that is ready to run. */ \
- \
- /* Restore all registers */ \
- \
- /* Set SP to point to new stack */ \
- "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \
- "ld.w r0, r8[0] \n\t" \
- "ld.w sp, r0[0] \n" \
- \
- "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ": \n\t" \
- \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t" \
- "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \
- "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t"\
- "st.w r8[0], r0 \n\t"\
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- /* Now, the stack should be R8..R12, LR, PC and SR */ \
- "rete" \
- ); \
- \
- /* Force import of global symbols from assembly */ \
- ulCriticalNesting; \
- pxCurrentTCB; \
- }
+#define portEXIT_SWITCHING_ISR() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ __asm__ __volatile__ ( \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
+ /* did not previously save SP in its TCB. */ \
+ "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
+ "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
+ "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+ "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
+ \
+ /* If a switch is required then we just need to call */ \
+ /* vTaskSwitchContext() as the context has already been */ \
+ /* saved. */ \
+ "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
+ "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \
+ ); \
+ \
+ /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+ portENTER_CRITICAL(); \
+ vTaskSwitchContext(); \
+ portEXIT_CRITICAL(); \
+ \
+ __asm__ __volatile__ ( \
+ "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
+ /* Restore the context of which ever task is now the highest */ \
+ /* priority that is ready to run. */ \
+ \
+ /* Restore all registers */ \
+ \
+ /* Set SP to point to new stack */ \
+ "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0] \n"\
+ \
+ "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
+ \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t"\
+ "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ /* Now, the stack should be R8..R12, LR, PC and SR */ \
+ "rete" \
+ ); \
+ \
+ /* Force import of global symbols from assembly */ \
+ ulCriticalNesting; \
+ pxCurrentTCB; \
+}
- #endif /* if configUSE_PREEMPTION == 0 */
+#endif
- #define portYIELD() { __asm__ __volatile__ ( "scall" ); }
+#define portYIELD() {__asm__ __volatile__ ("scall");}
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
diff --git a/portable/IAR/AVR32_UC3/read.c b/portable/IAR/AVR32_UC3/read.c
index b42ff93..30b5ee8 100644
--- a/portable/IAR/AVR32_UC3/read.c
+++ b/portable/IAR/AVR32_UC3/read.c
@@ -1,18 +1,17 @@
/*This file is prepared for Doxygen automatic documentation generation.*/
-
/*! \file *********************************************************************
-*
-* \brief System-specific implementation of the \ref __read function used by
-* the standard library.
-*
-* - Compiler: IAR EWAVR32
-* - Supported devices: All AVR32 devices with a USART module can be used.
-* - AppNote:
-*
-* \author Atmel Corporation: http://www.atmel.com \n
-* Support and FAQ: http://support.atmel.no/
-*
-******************************************************************************/
+ *
+ * \brief System-specific implementation of the \ref __read function used by
+ the standard library.
+ *
+ * - Compiler: IAR EWAVR32
+ * - Supported devices: All AVR32 devices with a USART module can be used.
+ * - AppNote:
+ *
+ * \author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
*
@@ -53,7 +52,7 @@
#pragma module_name = "?__read"
-extern volatile avr32_usart_t * volatile stdio_usart_base;
+extern volatile avr32_usart_t *volatile stdio_usart_base;
/*! \brief Reads a number of bytes, at most \a size, into the memory area
@@ -66,33 +65,28 @@
* \return The number of bytes read, \c 0 at the end of the file, or
* \c _LLIO_ERROR on failure.
*/
-size_t __read( int handle,
- uint8_t * buffer,
- size_t size )
+size_t __read(int handle, uint8_t *buffer, size_t size)
{
- int nChars = 0;
+ int nChars = 0;
- /* This implementation only reads from stdin. */
- /* For all other file handles, it returns failure. */
- if( handle != _LLIO_STDIN )
- {
- return _LLIO_ERROR;
- }
+ // This implementation only reads from stdin.
+ // For all other file handles, it returns failure.
+ if (handle != _LLIO_STDIN)
+ {
+ return _LLIO_ERROR;
+ }
- for( ; size > 0; --size )
- {
- int c = usart_getchar( stdio_usart_base );
+ for (; size > 0; --size)
+ {
+ int c = usart_getchar(stdio_usart_base);
+ if (c < 0)
+ break;
- if( c < 0 )
- {
- break;
- }
+ *buffer++ = c;
+ ++nChars;
+ }
- *buffer++ = c;
- ++nChars;
- }
-
- return nChars;
+ return nChars;
}
diff --git a/portable/IAR/AVR32_UC3/write.c b/portable/IAR/AVR32_UC3/write.c
index e8ac4a6..859487e 100644
--- a/portable/IAR/AVR32_UC3/write.c
+++ b/portable/IAR/AVR32_UC3/write.c
@@ -1,18 +1,17 @@
/*This file is prepared for Doxygen automatic documentation generation.*/
-
/*! \file *********************************************************************
-*
-* \brief System-specific implementation of the \ref __write function used by
-* the standard library.
-*
-* - Compiler: IAR EWAVR32
-* - Supported devices: All AVR32 devices with a USART module can be used.
-* - AppNote:
-*
-* \author Atmel Corporation: http://www.atmel.com \n
-* Support and FAQ: http://support.atmel.no/
-*
-******************************************************************************/
+ *
+ * \brief System-specific implementation of the \ref __write function used by
+ the standard library.
+ *
+ * - Compiler: IAR EWAVR32
+ * - Supported devices: All AVR32 devices with a USART module can be used.
+ * - AppNote:
+ *
+ * \author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
*
@@ -53,8 +52,8 @@
#pragma module_name = "?__write"
-/*! Pointer to the base of the USART module instance to use for stdio. */
-__no_init volatile avr32_usart_t * volatile stdio_usart_base;
+//! Pointer to the base of the USART module instance to use for stdio.
+__no_init volatile avr32_usart_t *volatile stdio_usart_base;
/*! \brief Writes a number of bytes, at most \a size, from the memory area
@@ -70,36 +69,34 @@
*
* \return The number of bytes written, or \c _LLIO_ERROR on failure.
*/
-size_t __write( int handle,
- const uint8_t * buffer,
- size_t size )
+size_t __write(int handle, const uint8_t *buffer, size_t size)
{
- size_t nChars = 0;
+ size_t nChars = 0;
- if( buffer == 0 )
+ if (buffer == 0)
+ {
+ // This means that we should flush internal buffers.
+ return 0;
+ }
+
+ // This implementation only writes to stdout and stderr.
+ // For all other file handles, it returns failure.
+ if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR)
+ {
+ return _LLIO_ERROR;
+ }
+
+ for (; size != 0; --size)
+ {
+ if (usart_putchar(stdio_usart_base, *buffer++) < 0)
{
- /* This means that we should flush internal buffers. */
- return 0;
+ return _LLIO_ERROR;
}
- /* This implementation only writes to stdout and stderr. */
- /* For all other file handles, it returns failure. */
- if( ( handle != _LLIO_STDOUT ) && ( handle != _LLIO_STDERR ) )
- {
- return _LLIO_ERROR;
- }
+ ++nChars;
+ }
- for( ; size != 0; --size )
- {
- if( usart_putchar( stdio_usart_base, *buffer++ ) < 0 )
- {
- return _LLIO_ERROR;
- }
-
- ++nChars;
- }
-
- return nChars;
+ return nChars;
}
diff --git a/portable/IAR/AVR_AVRDx/port.c b/portable/IAR/AVR_AVRDx/port.c
index 824c1aa..e723603 100644
--- a/portable/IAR/AVR_AVRDx/port.c
+++ b/portable/IAR/AVR_AVRDx/port.c
@@ -32,11 +32,11 @@
#include "task.h"
/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the AVR port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
/* Start tasks with interrupts enables. */
-#define portFLAGS_INT_ENABLED ((StackType_t) 0x80)
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
/*-----------------------------------------------------------*/
@@ -45,12 +45,13 @@
#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 )
/* Stores the critical section nesting. This must not be initialised to 0.
-It will be initialised when a task starts. */
+ * It will be initialised when a task starts. */
UBaseType_t uxCriticalNesting = 0x50;
+
/*
* Setup timer to generate a tick interrupt.
*/
-static void prvSetupTimerInterrupt(void);
+static void prvSetupTimerInterrupt( void );
/*
* The IAR compiler does not have full support for inline assembler, so
@@ -64,37 +65,40 @@
/*
* See header file for description.
*/
-StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters)
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
{
-uint16_t usAddress;
-StackType_t *pxTopOfHardwareStack;
+ uint16_t usAddress;
+ StackType_t * pxTopOfHardwareStack;
+
/* Simulate how the stack would look after a call to vPortYield(). */
/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
/* The IAR compiler requires two stacks per task. First there is the
- hardware call stack which uses the AVR stack pointer. Second there is the
- software stack (local variables, parameter passing, etc.) which uses the
- AVR Y register.
- This function places both stacks within the memory block passed in as the
- first parameter. The hardware stack is placed at the bottom of the memory
- block. A gap is then left for the hardware stack to grow. Next the software
- stack is placed. The amount of space between the software and hardware
- stacks is defined by configCALL_STACK_SIZE.
- The first part of the stack is the hardware stack. Place the start
- address of the task on the hardware stack. */
+ * hardware call stack which uses the AVR stack pointer. Second there is the
+ * software stack (local variables, parameter passing, etc.) which uses the
+ * AVR Y register.
+ * This function places both stacks within the memory block passed in as the
+ * first parameter. The hardware stack is placed at the bottom of the memory
+ * block. A gap is then left for the hardware stack to grow. Next the software
+ * stack is placed. The amount of space between the software and hardware
+ * stacks is defined by configCALL_STACK_SIZE.
+ * The first part of the stack is the hardware stack. Place the start
+ * address of the task on the hardware stack. */
/* Place a few bytes of known values on the bottom of the stack.
- This is just useful for debugging. */
- //*pxTopOfStack = 0x11;
- //pxTopOfStack--;
- //*pxTopOfStack = 0x22;
- //pxTopOfStack--;
- //*pxTopOfStack = 0x33;
- //pxTopOfStack--;
-
+ * This is just useful for debugging. */
+ /**pxTopOfStack = 0x11; */
+ /*pxTopOfStack--; */
+ /**pxTopOfStack = 0x22; */
+ /*pxTopOfStack--; */
+ /**pxTopOfStack = 0x33; */
+ /*pxTopOfStack--; */
+
/* Remember where the top of the hardware stack is - this is required
- below. */
+ * below. */
pxTopOfHardwareStack = pxTopOfStack;
usAddress = ( uint16_t ) pxCode;
@@ -104,25 +108,25 @@
usAddress >>= 8;
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
-
+
/* Leave enough space for the hardware stack before starting the software
- stack. The '- 2' is because we have already used two spaces for the
- address of the start of the task. */
+ * stack. The '- 2' is because we have already used two spaces for the
+ * address of the start of the task. */
pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );
/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
- portSAVE_CONTEXT places the flags on the stack immediately after r0
- to ensure the interrupts get disabled as soon as possible, and so ensuring
- the stack use is minimal should a context switch interrupt occur. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+ * portSAVE_CONTEXT places the flags on the stack immediately after r0
+ * to ensure the interrupts get disabled as soon as possible, and so ensuring
+ * the stack use is minimal should a context switch interrupt occur. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
pxTopOfStack--;
-
+
/* Next place the address of the hardware stack. This is required so
- the AVR stack pointer can be restored to point to the hardware stack. */
+ * the AVR stack pointer can be restored to point to the hardware stack. */
pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;
usAddress = ( uint16_t ) pxTopOfHardwareStack;
@@ -136,91 +140,91 @@
pxTopOfStack--;
/* Now the remaining registers. */
- *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */
+ *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
+ *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
+ *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
+ *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
pxTopOfStack--;
/* Place the parameter on the stack in the expected location. */
- usAddress = (uint16_t) pvParameters;
- *pxTopOfStack = (StackType_t) (usAddress & (uint16_t) 0x00ff);
+ usAddress = ( uint16_t ) pvParameters;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
usAddress >>= 8;
- *pxTopOfStack = (StackType_t) (usAddress & (uint16_t) 0x00ff);
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
+ *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
+ *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
+ *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
+ *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */
+ *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */
+ *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
+ *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
+ *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
pxTopOfStack--;
/* The Y register is not stored as it is used as the software stack and
- gets saved into the task control block. */
+ * gets saved into the task control block. */
- *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */
+ *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
+ *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
pxTopOfStack--;
- *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */
-
+ *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */
+
/*lint +e950 +e611 +e923 */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
-BaseType_t xPortStartScheduler(void)
+BaseType_t xPortStartScheduler( void )
{
/* Setup the hardware to generate the tick. */
prvSetupTimerInterrupt();
/* Restore the context of the first task that is going to run.
- Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
- compiler does not fully support inline assembler we have to make a call.*/
+ * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
+ * compiler does not fully support inline assembler we have to make a call.*/
vPortStart();
/* Should not get here. */
@@ -228,7 +232,7 @@
}
/*-----------------------------------------------------------*/
-void vPortEndScheduler(void)
+void vPortEndScheduler( void )
{
/* vPortEndScheduler is not implemented in this port. */
}
@@ -238,7 +242,7 @@
/*
* Setup timer to generate a tick interrupt.
*/
-static void prvSetupTimerInterrupt(void)
+static void prvSetupTimerInterrupt( void )
{
TICK_init();
}
@@ -246,32 +250,34 @@
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 1
+
/*
* Tick ISR for preemptive scheduler. We can use a naked attribute as
* the context is saved at the start of vPortYieldFromTick(). The tick
* count is incremented after the context is saved.
*/
-__task void TICK_INT(void)
-{
- vPortYieldFromTick();
- asm("reti");
-}
+ __task void TICK_INT( void )
+ {
+ vPortYieldFromTick();
+ asm ( "reti" );
+ }
#else
+
/*
* Tick ISR for the cooperative scheduler. All this does is increment the
* tick count. We don't need to switch context, this can only be done by
* manual calls to taskYIELD();
*/
-__interrupt void TICK_INT(void)
-{
- /* Clear tick interrupt flag. */
- INT_FLAGS = INT_MASK;
+ __interrupt void TICK_INT( void )
+ {
+ /* Clear tick interrupt flag. */
+ INT_FLAGS = INT_MASK;
- xTaskIncrementTick();
-}
-#endif
+ xTaskIncrementTick();
+ }
+#endif /* if configUSE_PREEMPTION == 1 */
/*-----------------------------------------------------------*/
@@ -286,6 +292,7 @@
void vPortExitCritical( void )
{
uxCriticalNesting--;
+
if( uxCriticalNesting == portNO_CRITICAL_NESTING )
{
portENABLE_INTERRUPTS();
diff --git a/portable/IAR/AVR_AVRDx/porthardware.h b/portable/IAR/AVR_AVRDx/porthardware.h
index 195d881..2d17b42 100644
--- a/portable/IAR/AVR_AVRDx/porthardware.h
+++ b/portable/IAR/AVR_AVRDx/porthardware.h
@@ -8,86 +8,92 @@
#if ( configUSE_TIMER_INSTANCE == 0 )
- #define TICK_INT_vect TCB0_INT_vect
- #define INT_FLAGS TCB0_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
-
- #define TICK_init() { \
- TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB0.INTCTRL = TCB_CAPT_bm; \
- TCB0.CTRLA = TCB_ENABLE_bm; \
- }
+ #define TICK_INT_vect TCB0_INT_vect
+ #define INT_FLAGS TCB0_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
+
+ #define TICK_init() \
+ { \
+ TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB0.INTCTRL = TCB_CAPT_bm; \
+ TCB0.CTRLA = TCB_ENABLE_bm; \
+ }
#elif ( configUSE_TIMER_INSTANCE == 1 )
- #define TICK_INT_vect TCB1_INT_vect
- #define INT_FLAGS TCB1_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
-
- #define TICK_init() { \
- TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB1.INTCTRL = TCB_CAPT_bm; \
- TCB1.CTRLA = TCB_ENABLE_bm; \
- }
-
+ #define TICK_INT_vect TCB1_INT_vect
+ #define INT_FLAGS TCB1_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
+
+ #define TICK_init() \
+ { \
+ TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB1.INTCTRL = TCB_CAPT_bm; \
+ TCB1.CTRLA = TCB_ENABLE_bm; \
+ }
+
#elif ( configUSE_TIMER_INSTANCE == 2 )
- #define TICK_INT_vect TCB2_INT_vect
- #define INT_FLAGS TCB2_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB2_INT_vect
+ #define INT_FLAGS TCB2_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB2.INTCTRL = TCB_CAPT_bm; \
- TCB2.CTRLA = TCB_ENABLE_bm; \
- }
-
+ #define TICK_init() \
+ { \
+ TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB2.INTCTRL = TCB_CAPT_bm; \
+ TCB2.CTRLA = TCB_ENABLE_bm; \
+ }
+
#elif ( configUSE_TIMER_INSTANCE == 3 )
- #define TICK_INT_vect TCB3_INT_vect
- #define INT_FLAGS TCB3_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
-
- #define TICK_init() { \
- TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB3.INTCTRL = TCB_CAPT_bm; \
- TCB3.CTRLA = TCB_ENABLE_bm; \
- }
-
+ #define TICK_INT_vect TCB3_INT_vect
+ #define INT_FLAGS TCB3_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
+
+ #define TICK_init() \
+ { \
+ TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB3.INTCTRL = TCB_CAPT_bm; \
+ TCB3.CTRLA = TCB_ENABLE_bm; \
+ }
+
#elif ( configUSE_TIMER_INSTANCE == 4 )
- #define TICK_INT_vect TCB4_INT_vect
- #define INT_FLAGS TCB4_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
-
- #define TICK_init() { \
- TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB4.INTCTRL = TCB_CAPT_bm; \
- TCB4.CTRLA = TCB_ENABLE_bm; \
- }
-
-#elif ( configUSE_TIMER_INSTANCE == 5 )
-
- #define TICK_INT_vect RTC_CNT_vect
- #define INT_FLAGS RTC_INTFLAGS
- #define INT_MASK RTC_OVF_bm
-
- /* Hertz to period for RTC setup */
- #define RTC_PERIOD_HZ(x) ( 32768 * ( ( 1.0 / x ) ) )
- #define TICK_init() { \
- while (RTC.STATUS > 0); \
- RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
- RTC.PER = RTC_PERIOD_HZ(configTICK_RATE_HZ); \
- RTC.INTCTRL |= 1 << RTC_OVF_bp; \
- }
+ #define TICK_INT_vect TCB4_INT_vect
+ #define INT_FLAGS TCB4_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
-#else
+ #define TICK_init() \
+ { \
+ TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB4.INTCTRL = TCB_CAPT_bm; \
+ TCB4.CTRLA = TCB_ENABLE_bm; \
+ }
+
+#elif ( configUSE_TIMER_INSTANCE == 5 )
+
+ #define TICK_INT_vect RTC_CNT_vect
+ #define INT_FLAGS RTC_INTFLAGS
+ #define INT_MASK RTC_OVF_bm
+
+/* Hertz to period for RTC setup */
+ #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) )
+ #define TICK_init() \
+ { \
+ while( RTC.STATUS > 0 ) {; } \
+ RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
+ RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \
+ RTC.INTCTRL |= 1 << RTC_OVF_bp; \
+ }
+
+#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
#undef TICK_INT_vect
#undef INT_FLAGS
#undef INT_MASK
#undef TICK_init()
#error Invalid timer setting.
-#endif
+#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
/*-----------------------------------------------------------*/
diff --git a/portable/IAR/AVR_AVRDx/portmacro.h b/portable/IAR/AVR_AVRDx/portmacro.h
index 555f41e..1c383b9 100644
--- a/portable/IAR/AVR_AVRDx/portmacro.h
+++ b/portable/IAR/AVR_AVRDx/portmacro.h
@@ -29,9 +29,11 @@
#ifndef PORTMACRO_H
#define PORTMACRO_H
+/* *INDENT-OFF* */
#ifdef __cplusplus
-extern "C" {
+ extern "C" {
#endif
+/* *INDENT-ON* */
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,26 +46,26 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint8_t
-#define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
-#define portPOINTER_SIZE_TYPE uint16_t
+#define portPOINTER_SIZE_TYPE uint16_t
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
-#if (configUSE_16_BIT_TICKS == 1)
- typedef uint16_t TickType_t;
- #define portMAX_DELAY (TickType_t)0xffff
+#if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY (TickType_t)0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
@@ -75,31 +77,33 @@
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
-#define portDISABLE_INTERRUPTS() asm( "cli" )
-#define portENABLE_INTERRUPTS() asm( "sei" )
+#define portDISABLE_INTERRUPTS() asm ( "cli" )
+#define portENABLE_INTERRUPTS() asm ( "sei" )
/*-----------------------------------------------------------*/
/* Architecture specifics. */
-#define portSTACK_GROWTH (-1)
-#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
-#define portBYTE_ALIGNMENT 1
-#define portNOP() asm( "nop" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 1
+#define portNOP() asm ( "nop" )
/*-----------------------------------------------------------*/
/* Kernel utilities. */
-extern void vPortYield(void);
-#define portYIELD() vPortYield()
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
-extern void vPortYieldFromISR(void);
-#define portYIELD_FROM_ISR() vPortYieldFromISR()
+extern void vPortYieldFromISR( void );
+#define portYIELD_FROM_ISR() vPortYieldFromISR()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
-#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/* *INDENT-OFF* */
#ifdef __cplusplus
-}
+ }
#endif
+/* *INDENT-ON* */
#endif /* PORTMACRO_H */
diff --git a/portable/IAR/AVR_Mega0/port.c b/portable/IAR/AVR_Mega0/port.c
index 9e34e1b..b2d3563 100644
--- a/portable/IAR/AVR_Mega0/port.c
+++ b/portable/IAR/AVR_Mega0/port.c
@@ -32,11 +32,11 @@
#include "task.h"
/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the AVR port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
/* Start tasks with interrupts enables. */
-#define portFLAGS_INT_ENABLED ((StackType_t) 0x80)
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
/*-----------------------------------------------------------*/
@@ -45,12 +45,13 @@
#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 )
/* Stores the critical section nesting. This must not be initialised to 0.
-It will be initialised when a task starts. */
+ * It will be initialised when a task starts. */
UBaseType_t uxCriticalNesting = 0x50;
+
/*
* Setup timer to generate a tick interrupt.
*/
-static void prvSetupTimerInterrupt(void);
+static void prvSetupTimerInterrupt( void );
/*
* The IAR compiler does not have full support for inline assembler, so
@@ -64,37 +65,40 @@
/*
* See header file for description.
*/
-StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters)
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
{
-uint16_t usAddress;
-StackType_t *pxTopOfHardwareStack;
+ uint16_t usAddress;
+ StackType_t * pxTopOfHardwareStack;
+
/* Simulate how the stack would look after a call to vPortYield(). */
/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
-
+
/* The IAR compiler requires two stacks per task. First there is the
- hardware call stack which uses the AVR stack pointer. Second there is the
- software stack (local variables, parameter passing, etc.) which uses the
- AVR Y register.
- This function places both stacks within the memory block passed in as the
- first parameter. The hardware stack is placed at the bottom of the memory
- block. A gap is then left for the hardware stack to grow. Next the software
- stack is placed. The amount of space between the software and hardware
- stacks is defined by configCALL_STACK_SIZE.
- The first part of the stack is the hardware stack. Place the start
- address of the task on the hardware stack. */
-
+ * hardware call stack which uses the AVR stack pointer. Second there is the
+ * software stack (local variables, parameter passing, etc.) which uses the
+ * AVR Y register.
+ * This function places both stacks within the memory block passed in as the
+ * first parameter. The hardware stack is placed at the bottom of the memory
+ * block. A gap is then left for the hardware stack to grow. Next the software
+ * stack is placed. The amount of space between the software and hardware
+ * stacks is defined by configCALL_STACK_SIZE.
+ * The first part of the stack is the hardware stack. Place the start
+ * address of the task on the hardware stack. */
+
/* Place a few bytes of known values on the bottom of the stack.
- This is just useful for debugging. */
- //*pxTopOfStack = 0x11;
- //pxTopOfStack--;
- //*pxTopOfStack = 0x22;
- //pxTopOfStack--;
- //*pxTopOfStack = 0x33;
- //pxTopOfStack--;
-
+ * This is just useful for debugging. */
+ /**pxTopOfStack = 0x11; */
+ /*pxTopOfStack--; */
+ /**pxTopOfStack = 0x22; */
+ /*pxTopOfStack--; */
+ /**pxTopOfStack = 0x33; */
+ /*pxTopOfStack--; */
+
/* Remember where the top of the hardware stack is - this is required
- below. */
+ * below. */
pxTopOfHardwareStack = pxTopOfStack;
usAddress = ( uint16_t ) pxCode;
@@ -106,21 +110,21 @@
pxTopOfStack--;
/* Leave enough space for the hardware stack before starting the software
- stack. The '- 2' is because we have already used two spaces for the
- address of the start of the task. */
+ * stack. The '- 2' is because we have already used two spaces for the
+ * address of the start of the task. */
pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );
/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
- portSAVE_CONTEXT places the flags on the stack immediately after r0
- to ensure the interrupts get disabled as soon as possible, and so ensuring
- the stack use is minimal should a context switch interrupt occur. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+ * portSAVE_CONTEXT places the flags on the stack immediately after r0
+ * to ensure the interrupts get disabled as soon as possible, and so ensuring
+ * the stack use is minimal should a context switch interrupt occur. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
pxTopOfStack--;
/* Next place the address of the hardware stack. This is required so
- the AVR stack pointer can be restored to point to the hardware stack. */
+ * the AVR stack pointer can be restored to point to the hardware stack. */
pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;
usAddress = ( uint16_t ) pxTopOfHardwareStack;
@@ -134,76 +138,76 @@
pxTopOfStack--;
/* Now the remaining registers. */
- *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */
+ *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
+ *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
+ *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
+ *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
pxTopOfStack--;
/* Place the parameter on the stack in the expected location. */
- usAddress = (uint16_t) pvParameters;
- *pxTopOfStack = (StackType_t) (usAddress & (uint16_t) 0x00ff);
+ usAddress = ( uint16_t ) pvParameters;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
usAddress >>= 8;
- *pxTopOfStack = (StackType_t) (usAddress & (uint16_t) 0x00ff);
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
+ *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
+ *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
+ *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
+ *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */
+ *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */
+ *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
+ *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
+ *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
pxTopOfStack--;
/* The Y register is not stored as it is used as the software stack and
- gets saved into the task control block. */
+ * gets saved into the task control block. */
- *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */
+ *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
-
- pxTopOfStack--;
- *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */
+ *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
+
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */
/*lint +e950 +e611 +e923 */
@@ -211,14 +215,14 @@
}
/*-----------------------------------------------------------*/
-BaseType_t xPortStartScheduler(void)
+BaseType_t xPortStartScheduler( void )
{
/* Setup the hardware to generate the tick. */
prvSetupTimerInterrupt();
/* Restore the context of the first task that is going to run.
- Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
- compiler does not fully support inline assembler we have to make a call.*/
+ * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
+ * compiler does not fully support inline assembler we have to make a call.*/
vPortStart();
/* Should not get here. */
@@ -226,7 +230,7 @@
}
/*-----------------------------------------------------------*/
-void vPortEndScheduler(void)
+void vPortEndScheduler( void )
{
/* vPortEndScheduler is not implemented in this port. */
}
@@ -236,7 +240,7 @@
/*
* Setup timer to generate a tick interrupt.
*/
-static void prvSetupTimerInterrupt(void)
+static void prvSetupTimerInterrupt( void )
{
TICK_init();
}
@@ -244,32 +248,34 @@
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 1
+
/*
* Tick ISR for preemptive scheduler. We can use a naked attribute as
* the context is saved at the start of vPortYieldFromTick(). The tick
* count is incremented after the context is saved.
*/
-__task void TICK_INT(void)
-{
- vPortYieldFromTick();
- asm("reti");
-}
+ __task void TICK_INT( void )
+ {
+ vPortYieldFromTick();
+ asm ( "reti" );
+ }
#else
+
/*
* Tick ISR for the cooperative scheduler. All this does is increment the
* tick count. We don't need to switch context, this can only be done by
* manual calls to taskYIELD();
*/
-__interrupt void TICK_INT(void)
-{
- /* Clear tick interrupt flag. */
- INT_FLAGS = INT_MASK;
-
- xTaskIncrementTick();
-}
-#endif
+ __interrupt void TICK_INT( void )
+ {
+ /* Clear tick interrupt flag. */
+ INT_FLAGS = INT_MASK;
+
+ xTaskIncrementTick();
+ }
+#endif /* if configUSE_PREEMPTION == 1 */
/*-----------------------------------------------------------*/
@@ -284,6 +290,7 @@
void vPortExitCritical( void )
{
uxCriticalNesting--;
+
if( uxCriticalNesting == portNO_CRITICAL_NESTING )
{
portENABLE_INTERRUPTS();
diff --git a/portable/IAR/AVR_Mega0/porthardware.h b/portable/IAR/AVR_Mega0/porthardware.h
index 5468bda..4188ae2 100644
--- a/portable/IAR/AVR_Mega0/porthardware.h
+++ b/portable/IAR/AVR_Mega0/porthardware.h
@@ -8,74 +8,79 @@
#if ( configUSE_TIMER_INSTANCE == 0 )
- #define TICK_INT_vect TCB0_INT_vect
- #define INT_FLAGS TCB0_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
+ #define TICK_INT_vect TCB0_INT_vect
+ #define INT_FLAGS TCB0_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
- #define TICK_init() { \
- TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB0.INTCTRL = TCB_CAPT_bm; \
- TCB0.CTRLA = TCB_ENABLE_bm; \
- }
+ #define TICK_init() \
+ { \
+ TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB0.INTCTRL = TCB_CAPT_bm; \
+ TCB0.CTRLA = TCB_ENABLE_bm; \
+ }
#elif ( configUSE_TIMER_INSTANCE == 1 )
- #define TICK_INT_vect TCB1_INT_vect
- #define INT_FLAGS TCB1_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
-
- #define TICK_init() { \
- TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB1.INTCTRL = TCB_CAPT_bm; \
- TCB1.CTRLA = TCB_ENABLE_bm; \
- }
+ #define TICK_INT_vect TCB1_INT_vect
+ #define INT_FLAGS TCB1_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
+
+ #define TICK_init() \
+ { \
+ TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB1.INTCTRL = TCB_CAPT_bm; \
+ TCB1.CTRLA = TCB_ENABLE_bm; \
+ }
#elif ( configUSE_TIMER_INSTANCE == 2 )
- #define TICK_INT_vect TCB2_INT_vect
- #define INT_FLAGS TCB2_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
-
- #define TICK_init() { \
- TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB2.INTCTRL = TCB_CAPT_bm; \
- TCB2.CTRLA = TCB_ENABLE_bm; \
- }
-
+ #define TICK_INT_vect TCB2_INT_vect
+ #define INT_FLAGS TCB2_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
+
+ #define TICK_init() \
+ { \
+ TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB2.INTCTRL = TCB_CAPT_bm; \
+ TCB2.CTRLA = TCB_ENABLE_bm; \
+ }
+
#elif ( configUSE_TIMER_INSTANCE == 3 )
- #define TICK_INT_vect TCB3_INT_vect
- #define INT_FLAGS TCB3_INTFLAGS
- #define INT_MASK TCB_CAPT_bm
-
- #define TICK_init() { \
- TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
- TCB3.INTCTRL = TCB_CAPT_bm; \
- TCB3.CTRLA = TCB_ENABLE_bm; \
- }
+ #define TICK_INT_vect TCB3_INT_vect
+ #define INT_FLAGS TCB3_INTFLAGS
+ #define INT_MASK TCB_CAPT_bm
+
+ #define TICK_init() \
+ { \
+ TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+ TCB3.INTCTRL = TCB_CAPT_bm; \
+ TCB3.CTRLA = TCB_ENABLE_bm; \
+ }
#elif ( configUSE_TIMER_INSTANCE == 4 )
- #define TICK_INT_vect RTC_CNT_vect
- #define INT_FLAGS RTC_INTFLAGS
- #define INT_MASK RTC_OVF_bm
-
- /* Hertz to period for RTC setup */
- #define RTC_PERIOD_HZ(x) ( 32768 * ( ( 1.0 / x ) ) )
- #define TICK_init() { \
- while (RTC.STATUS > 0); \
- RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
- RTC.PER = RTC_PERIOD_HZ(configTICK_RATE_HZ); \
- RTC.INTCTRL |= 1 << RTC_OVF_bp; \
- }
+ #define TICK_INT_vect RTC_CNT_vect
+ #define INT_FLAGS RTC_INTFLAGS
+ #define INT_MASK RTC_OVF_bm
-#else
+/* Hertz to period for RTC setup */
+ #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) )
+ #define TICK_init() \
+ { \
+ while( RTC.STATUS > 0 ) {; } \
+ RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
+ RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \
+ RTC.INTCTRL |= 1 << RTC_OVF_bp; \
+ }
+
+#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
#undef TICK_INT_vect
#undef INT_FLAGS
#undef INT_MASK
#undef TICK_init()
#error Invalid timer setting.
-#endif
+#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
/*-----------------------------------------------------------*/
diff --git a/portable/IAR/AVR_Mega0/portmacro.h b/portable/IAR/AVR_Mega0/portmacro.h
index 555f41e..1c383b9 100644
--- a/portable/IAR/AVR_Mega0/portmacro.h
+++ b/portable/IAR/AVR_Mega0/portmacro.h
@@ -29,9 +29,11 @@
#ifndef PORTMACRO_H
#define PORTMACRO_H
+/* *INDENT-OFF* */
#ifdef __cplusplus
-extern "C" {
+ extern "C" {
#endif
+/* *INDENT-ON* */
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,26 +46,26 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint8_t
-#define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
-#define portPOINTER_SIZE_TYPE uint16_t
+#define portPOINTER_SIZE_TYPE uint16_t
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
-#if (configUSE_16_BIT_TICKS == 1)
- typedef uint16_t TickType_t;
- #define portMAX_DELAY (TickType_t)0xffff
+#if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY (TickType_t)0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
@@ -75,31 +77,33 @@
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
-#define portDISABLE_INTERRUPTS() asm( "cli" )
-#define portENABLE_INTERRUPTS() asm( "sei" )
+#define portDISABLE_INTERRUPTS() asm ( "cli" )
+#define portENABLE_INTERRUPTS() asm ( "sei" )
/*-----------------------------------------------------------*/
/* Architecture specifics. */
-#define portSTACK_GROWTH (-1)
-#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
-#define portBYTE_ALIGNMENT 1
-#define portNOP() asm( "nop" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 1
+#define portNOP() asm ( "nop" )
/*-----------------------------------------------------------*/
/* Kernel utilities. */
-extern void vPortYield(void);
-#define portYIELD() vPortYield()
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
-extern void vPortYieldFromISR(void);
-#define portYIELD_FROM_ISR() vPortYieldFromISR()
+extern void vPortYieldFromISR( void );
+#define portYIELD_FROM_ISR() vPortYieldFromISR()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
-#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/* *INDENT-OFF* */
#ifdef __cplusplus
-}
+ }
#endif
+/* *INDENT-ON* */
#endif /* PORTMACRO_H */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
index d3bc477..8f9ddb4 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
@@ -1,1936 +1,1914 @@
-/* ---------------------------------------------------------------------------- */
-/* ATMEL Microcontroller Software Support - ROUSSET - */
-/* ---------------------------------------------------------------------------- */
-/* The software is delivered "AS IS" without warranty or condition of any */
-/* kind, either express, implied or statutory. This includes without */
-/* limitation any warranty or condition with respect to merchantability or */
-/* fitness for any particular purpose, or against the infringements of */
-/* intellectual property rights of others. */
-/* ---------------------------------------------------------------------------- */
-/* File Name : AT91SAM7S64.h */
-/* Object : AT91SAM7S64 definitions */
-/* Generated : AT91 SW Application Group 07/16/2004 (07:43:08) */
-/* */
-/* CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// */
-/* CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// */
-/* CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// */
-/* CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// */
-/* CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */
-/* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */
-/* CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */
-/* CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// */
-/* CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// */
-/* CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// */
-/* CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// */
-/* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
-/* CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// */
-/* CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// */
-/* CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// */
-/* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
-/* ---------------------------------------------------------------------------- */
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// The software is delivered "AS IS" without warranty or condition of any
+// kind, either express, implied or statutory. This includes without
+// limitation any warranty or condition with respect to merchantability or
+// fitness for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM7S64.h
+// Object : AT91SAM7S64 definitions
+// Generated : AT91 SW Application Group 07/16/2004 (07:43:08)
+//
+// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
+// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
+// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
+// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002//
+// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
+// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
+// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
+// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
+// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002//
+// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003//
+// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
+// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
+// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+// ----------------------------------------------------------------------------
#ifndef AT91SAM7S64_H
#define AT91SAM7S64_H
-typedef volatile unsigned int AT91_REG; /* Hardware register definition */
+typedef volatile unsigned int AT91_REG;// Hardware register definition
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR System Peripherals */
-/* ***************************************************************************** */
-typedef struct _AT91S_SYSC
-{
- AT91_REG SYSC_AIC_SMR[ 32 ]; /* Source Mode Register */
- AT91_REG SYSC_AIC_SVR[ 32 ]; /* Source Vector Register */
- AT91_REG SYSC_AIC_IVR; /* IRQ Vector Register */
- AT91_REG SYSC_AIC_FVR; /* FIQ Vector Register */
- AT91_REG SYSC_AIC_ISR; /* Interrupt Status Register */
- AT91_REG SYSC_AIC_IPR; /* Interrupt Pending Register */
- AT91_REG SYSC_AIC_IMR; /* Interrupt Mask Register */
- AT91_REG SYSC_AIC_CISR; /* Core Interrupt Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG SYSC_AIC_IECR; /* Interrupt Enable Command Register */
- AT91_REG SYSC_AIC_IDCR; /* Interrupt Disable Command Register */
- AT91_REG SYSC_AIC_ICCR; /* Interrupt Clear Command Register */
- AT91_REG SYSC_AIC_ISCR; /* Interrupt Set Command Register */
- AT91_REG SYSC_AIC_EOICR; /* End of Interrupt Command Register */
- AT91_REG SYSC_AIC_SPU; /* Spurious Vector Register */
- AT91_REG SYSC_AIC_DCR; /* Debug Control Register (Protect) */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG SYSC_AIC_FFER; /* Fast Forcing Enable Register */
- AT91_REG SYSC_AIC_FFDR; /* Fast Forcing Disable Register */
- AT91_REG SYSC_AIC_FFSR; /* Fast Forcing Status Register */
- AT91_REG Reserved2[ 45 ]; /* */
- AT91_REG SYSC_DBGU_CR; /* Control Register */
- AT91_REG SYSC_DBGU_MR; /* Mode Register */
- AT91_REG SYSC_DBGU_IER; /* Interrupt Enable Register */
- AT91_REG SYSC_DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG SYSC_DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG SYSC_DBGU_CSR; /* Channel Status Register */
- AT91_REG SYSC_DBGU_RHR; /* Receiver Holding Register */
- AT91_REG SYSC_DBGU_THR; /* Transmitter Holding Register */
- AT91_REG SYSC_DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved3[ 7 ]; /* */
- AT91_REG SYSC_DBGU_C1R; /* Chip ID1 Register */
- AT91_REG SYSC_DBGU_C2R; /* Chip ID2 Register */
- AT91_REG SYSC_DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved4[ 45 ]; /* */
- AT91_REG SYSC_DBGU_RPR; /* Receive Pointer Register */
- AT91_REG SYSC_DBGU_RCR; /* Receive Counter Register */
- AT91_REG SYSC_DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG SYSC_DBGU_TCR; /* Transmit Counter Register */
- AT91_REG SYSC_DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG SYSC_DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG SYSC_DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SYSC_DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG SYSC_DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG SYSC_DBGU_PTSR; /* PDC Transfer Status Register */
- AT91_REG Reserved5[ 54 ]; /* */
- AT91_REG SYSC_PIOA_PER; /* PIO Enable Register */
- AT91_REG SYSC_PIOA_PDR; /* PIO Disable Register */
- AT91_REG SYSC_PIOA_PSR; /* PIO Status Register */
- AT91_REG Reserved6[ 1 ]; /* */
- AT91_REG SYSC_PIOA_OER; /* Output Enable Register */
- AT91_REG SYSC_PIOA_ODR; /* Output Disable Registerr */
- AT91_REG SYSC_PIOA_OSR; /* Output Status Register */
- AT91_REG Reserved7[ 1 ]; /* */
- AT91_REG SYSC_PIOA_IFER; /* Input Filter Enable Register */
- AT91_REG SYSC_PIOA_IFDR; /* Input Filter Disable Register */
- AT91_REG SYSC_PIOA_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved8[ 1 ]; /* */
- AT91_REG SYSC_PIOA_SODR; /* Set Output Data Register */
- AT91_REG SYSC_PIOA_CODR; /* Clear Output Data Register */
- AT91_REG SYSC_PIOA_ODSR; /* Output Data Status Register */
- AT91_REG SYSC_PIOA_PDSR; /* Pin Data Status Register */
- AT91_REG SYSC_PIOA_IER; /* Interrupt Enable Register */
- AT91_REG SYSC_PIOA_IDR; /* Interrupt Disable Register */
- AT91_REG SYSC_PIOA_IMR; /* Interrupt Mask Register */
- AT91_REG SYSC_PIOA_ISR; /* Interrupt Status Register */
- AT91_REG SYSC_PIOA_MDER; /* Multi-driver Enable Register */
- AT91_REG SYSC_PIOA_MDDR; /* Multi-driver Disable Register */
- AT91_REG SYSC_PIOA_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved9[ 1 ]; /* */
- AT91_REG SYSC_PIOA_PPUDR; /* Pull-up Disable Register */
- AT91_REG SYSC_PIOA_PPUER; /* Pull-up Enable Register */
- AT91_REG SYSC_PIOA_PPUSR; /* Pad Pull-up Status Register */
- AT91_REG Reserved10[ 1 ]; /* */
- AT91_REG SYSC_PIOA_ASR; /* Select A Register */
- AT91_REG SYSC_PIOA_BSR; /* Select B Register */
- AT91_REG SYSC_PIOA_ABSR; /* AB Select Status Register */
- AT91_REG Reserved11[ 9 ]; /* */
- AT91_REG SYSC_PIOA_OWER; /* Output Write Enable Register */
- AT91_REG SYSC_PIOA_OWDR; /* Output Write Disable Register */
- AT91_REG SYSC_PIOA_OWSR; /* Output Write Status Register */
- AT91_REG Reserved12[ 469 ]; /* */
- AT91_REG SYSC_PMC_SCER; /* System Clock Enable Register */
- AT91_REG SYSC_PMC_SCDR; /* System Clock Disable Register */
- AT91_REG SYSC_PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved13[ 1 ]; /* */
- AT91_REG SYSC_PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG SYSC_PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG SYSC_PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved14[ 1 ]; /* */
- AT91_REG SYSC_PMC_MOR; /* Main Oscillator Register */
- AT91_REG SYSC_PMC_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved15[ 1 ]; /* */
- AT91_REG SYSC_PMC_PLLR; /* PLL Register */
- AT91_REG SYSC_PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved16[ 3 ]; /* */
- AT91_REG SYSC_PMC_PCKR[ 8 ]; /* Programmable Clock Register */
- AT91_REG SYSC_PMC_IER; /* Interrupt Enable Register */
- AT91_REG SYSC_PMC_IDR; /* Interrupt Disable Register */
- AT91_REG SYSC_PMC_SR; /* Status Register */
- AT91_REG SYSC_PMC_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved17[ 36 ]; /* */
- AT91_REG SYSC_RSTC_RCR; /* Reset Control Register */
- AT91_REG SYSC_RSTC_RSR; /* Reset Status Register */
- AT91_REG SYSC_RSTC_RMR; /* Reset Mode Register */
- AT91_REG Reserved18[ 5 ]; /* */
- AT91_REG SYSC_RTTC_RTMR; /* Real-time Mode Register */
- AT91_REG SYSC_RTTC_RTAR; /* Real-time Alarm Register */
- AT91_REG SYSC_RTTC_RTVR; /* Real-time Value Register */
- AT91_REG SYSC_RTTC_RTSR; /* Real-time Status Register */
- AT91_REG SYSC_PITC_PIMR; /* Period Interval Mode Register */
- AT91_REG SYSC_PITC_PISR; /* Period Interval Status Register */
- AT91_REG SYSC_PITC_PIVR; /* Period Interval Value Register */
- AT91_REG SYSC_PITC_PIIR; /* Period Interval Image Register */
- AT91_REG SYSC_WDTC_WDCR; /* Watchdog Control Register */
- AT91_REG SYSC_WDTC_WDMR; /* Watchdog Mode Register */
- AT91_REG SYSC_WDTC_WDSR; /* Watchdog Status Register */
- AT91_REG Reserved19[ 5 ]; /* */
- AT91_REG SYSC_SYSC_VRPM; /* Voltage Regulator Power Mode Register */
-} AT91S_SYSC, * AT91PS_SYSC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYSC {
+ AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register
+ AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register
+ AT91_REG SYSC_AIC_IVR; // IRQ Vector Register
+ AT91_REG SYSC_AIC_FVR; // FIQ Vector Register
+ AT91_REG SYSC_AIC_ISR; // Interrupt Status Register
+ AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register
+ AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register
+ AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG SYSC_AIC_SPU; // Spurious Vector Register
+ AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved2[45]; //
+ AT91_REG SYSC_DBGU_CR; // Control Register
+ AT91_REG SYSC_DBGU_MR; // Mode Register
+ AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register
+ AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register
+ AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register
+ AT91_REG SYSC_DBGU_CSR; // Channel Status Register
+ AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register
+ AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register
+ AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved3[7]; //
+ AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register
+ AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register
+ AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved4[45]; //
+ AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register
+ AT91_REG SYSC_DBGU_RCR; // Receive Counter Register
+ AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register
+ AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register
+ AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved5[54]; //
+ AT91_REG SYSC_PIOA_PER; // PIO Enable Register
+ AT91_REG SYSC_PIOA_PDR; // PIO Disable Register
+ AT91_REG SYSC_PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved6[1]; //
+ AT91_REG SYSC_PIOA_OER; // Output Enable Register
+ AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr
+ AT91_REG SYSC_PIOA_OSR; // Output Status Register
+ AT91_REG Reserved7[1]; //
+ AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register
+ AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved8[1]; //
+ AT91_REG SYSC_PIOA_SODR; // Set Output Data Register
+ AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register
+ AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register
+ AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register
+ AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register
+ AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register
+ AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register
+ AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register
+ AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved9[1]; //
+ AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register
+ AT91_REG Reserved10[1]; //
+ AT91_REG SYSC_PIOA_ASR; // Select A Register
+ AT91_REG SYSC_PIOA_BSR; // Select B Register
+ AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved11[9]; //
+ AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register
+ AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register
+ AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved12[469]; //
+ AT91_REG SYSC_PMC_SCER; // System Clock Enable Register
+ AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register
+ AT91_REG SYSC_PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG SYSC_PMC_MOR; // Main Oscillator Register
+ AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG SYSC_PMC_PLLR; // PLL Register
+ AT91_REG SYSC_PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved16[3]; //
+ AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register
+ AT91_REG SYSC_PMC_IER; // Interrupt Enable Register
+ AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register
+ AT91_REG SYSC_PMC_SR; // Status Register
+ AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved17[36]; //
+ AT91_REG SYSC_RSTC_RCR; // Reset Control Register
+ AT91_REG SYSC_RSTC_RSR; // Reset Status Register
+ AT91_REG SYSC_RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved18[5]; //
+ AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register
+ AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register
+ AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register
+ AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register
+ AT91_REG SYSC_PITC_PISR; // Period Interval Status Register
+ AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register
+ AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register
+ AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register
+ AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved19[5]; //
+ AT91_REG SYSC_SYSC_VRPM; // Voltage Regulator Power Mode Register
+} AT91S_SYSC, *AT91PS_SYSC;
-/* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- */
-#define AT91C_SYSC_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (SYSC) Voltage Regulator Power Mode */
+// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register --------
+#define AT91C_SYSC_PSTDBY ((unsigned int) 0x1 << 0) // (SYSC) Voltage Regulator Power Mode
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_AIC
-{
- AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
- AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
- AT91_REG AIC_IVR; /* IRQ Vector Register */
- AT91_REG AIC_FVR; /* FIQ Vector Register */
- AT91_REG AIC_ISR; /* Interrupt Status Register */
- AT91_REG AIC_IPR; /* Interrupt Pending Register */
- AT91_REG AIC_IMR; /* Interrupt Mask Register */
- AT91_REG AIC_CISR; /* Core Interrupt Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
- AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
- AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
- AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
- AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
- AT91_REG AIC_SPU; /* Spurious Vector Register */
- AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
- AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
- AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
-} AT91S_AIC, * AT91PS_AIC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
-/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
-#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
-#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */
-#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */
-#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
-#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label Level Sensitive */
-#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Edge triggered */
-#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) External Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) External Sources Code Label Positive Edge triggered */
-/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
-#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
-#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
-/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
-#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
-#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/* ***************************************************************************** */
-typedef struct _AT91S_DBGU
-{
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved0[ 7 ]; /* */
- AT91_REG DBGU_C1R; /* Chip ID1 Register */
- AT91_REG DBGU_C2R; /* Chip ID2 Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved1[ 45 ]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
-} AT91S_DBGU, * AT91PS_DBGU;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_C1R; // Chip ID1 Register
+ AT91_REG DBGU_C2R; // Chip ID2 Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */
-/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */
-#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */
-#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */
-#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */
-#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */
-#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
-#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
-#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
-#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
-#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
-/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
-/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
-#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_PDC
-{
- AT91_REG PDC_RPR; /* Receive Pointer Register */
- AT91_REG PDC_RCR; /* Receive Counter Register */
- AT91_REG PDC_TPR; /* Transmit Pointer Register */
- AT91_REG PDC_TCR; /* Transmit Counter Register */
- AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
- AT91_REG PDC_RNCR; /* Receive Next Counter Register */
- AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
- AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
- AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
-} AT91S_PDC, * AT91PS_PDC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral Data Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PIO
-{
- AT91_REG PIO_PER; /* PIO Enable Register */
- AT91_REG PIO_PDR; /* PIO Disable Register */
- AT91_REG PIO_PSR; /* PIO Status Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG PIO_OER; /* Output Enable Register */
- AT91_REG PIO_ODR; /* Output Disable Registerr */
- AT91_REG PIO_OSR; /* Output Status Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG PIO_IFER; /* Input Filter Enable Register */
- AT91_REG PIO_IFDR; /* Input Filter Disable Register */
- AT91_REG PIO_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG PIO_SODR; /* Set Output Data Register */
- AT91_REG PIO_CODR; /* Clear Output Data Register */
- AT91_REG PIO_ODSR; /* Output Data Status Register */
- AT91_REG PIO_PDSR; /* Pin Data Status Register */
- AT91_REG PIO_IER; /* Interrupt Enable Register */
- AT91_REG PIO_IDR; /* Interrupt Disable Register */
- AT91_REG PIO_IMR; /* Interrupt Mask Register */
- AT91_REG PIO_ISR; /* Interrupt Status Register */
- AT91_REG PIO_MDER; /* Multi-driver Enable Register */
- AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIO_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved3[ 1 ]; /* */
- AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIO_PPUER; /* Pull-up Enable Register */
- AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */
- AT91_REG Reserved4[ 1 ]; /* */
- AT91_REG PIO_ASR; /* Select A Register */
- AT91_REG PIO_BSR; /* Select B Register */
- AT91_REG PIO_ABSR; /* AB Select Status Register */
- AT91_REG Reserved5[ 9 ]; /* */
- AT91_REG PIO_OWER; /* Output Write Enable Register */
- AT91_REG PIO_OWDR; /* Output Write Disable Register */
- AT91_REG PIO_OWSR; /* Output Write Status Register */
-} AT91S_PIO, * AT91PS_PIO;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pad Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_CKGR
-{
- AT91_REG CKGR_MOR; /* Main Oscillator Register */
- AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG CKGR_PLLR; /* PLL Register */
-} AT91S_CKGR, * AT91PS_CKGR;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG CKGR_PLLR; // PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */
-#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */
-/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */
-#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */
-#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
-#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */
-#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */
-#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */
-#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PMC
-{
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG PMC_MOR; /* Main Oscillator Register */
- AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG PMC_PLLR; /* PLL Register */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved3[ 3 ]; /* */
- AT91_REG PMC_PCKR[ 8 ]; /* Programmable Clock Register */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
-} AT91S_PMC, * AT91PS_PMC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved3[3]; //
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
-/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
-#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
-/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
-/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
-/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
-/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
-/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
-/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
-#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */
-#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
-/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
-/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
-#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
-/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
-/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Reset Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_RSTC
-{
- AT91_REG RSTC_RCR; /* Reset Control Register */
- AT91_REG RSTC_RSR; /* Reset Status Register */
- AT91_REG RSTC_RMR; /* Reset Mode Register */
-} AT91S_RSTC, * AT91PS_RSTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
-/* -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
-#define AT91C_SYSC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */
-#define AT91C_SYSC_ICERST ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) ICE Interface Reset */
-#define AT91C_SYSC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */
-#define AT91C_SYSC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */
-#define AT91C_SYSC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
-/* -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
-#define AT91C_SYSC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */
-#define AT91C_SYSC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brown-out Detection Status */
-#define AT91C_SYSC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */
-#define AT91C_SYSC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */
-#define AT91C_SYSC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occured. */
-#define AT91C_SYSC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */
-#define AT91C_SYSC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */
-#define AT91C_SYSC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brown-out Reset. */
-#define AT91C_SYSC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */
-#define AT91C_SYSC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */
-/* -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
-#define AT91C_SYSC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */
-#define AT91C_SYSC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */
-#define AT91C_SYSC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */
-#define AT91C_SYSC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brown-out Detection Interrupt Enable */
+// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_SYSC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_SYSC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset
+#define AT91C_SYSC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_SYSC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
+#define AT91C_SYSC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_SYSC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_SYSC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brown-out Detection Status
+#define AT91C_SYSC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
+#define AT91C_SYSC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_SYSC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_SYSC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_SYSC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_SYSC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brown-out Reset.
+#define AT91C_SYSC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_SYSC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_SYSC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_SYSC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_SYSC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_SYSC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_RTTC
-{
- AT91_REG RTTC_RTMR; /* Real-time Mode Register */
- AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
- AT91_REG RTTC_RTVR; /* Real-time Value Register */
- AT91_REG RTTC_RTSR; /* Real-time Status Register */
-} AT91S_RTTC, * AT91PS_RTTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
-/* -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
-#define AT91C_SYSC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
-#define AT91C_SYSC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */
-#define AT91C_SYSC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */
-#define AT91C_SYSC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */
-/* -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
-#define AT91C_SYSC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */
-/* -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
-#define AT91C_SYSC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */
-/* -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
-#define AT91C_SYSC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */
-#define AT91C_SYSC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */
+// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_SYSC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_SYSC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_SYSC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_SYSC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_SYSC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
+// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_SYSC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
+// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_SYSC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_SYSC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PITC
-{
- AT91_REG PITC_PIMR; /* Period Interval Mode Register */
- AT91_REG PITC_PISR; /* Period Interval Status Register */
- AT91_REG PITC_PIVR; /* Period Interval Value Register */
- AT91_REG PITC_PIIR; /* Period Interval Image Register */
-} AT91S_PITC, * AT91PS_PITC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
-/* -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
-#define AT91C_SYSC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
-#define AT91C_SYSC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */
-#define AT91C_SYSC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */
-/* -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
-#define AT91C_SYSC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */
-/* -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
-#define AT91C_SYSC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
-#define AT91C_SYSC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */
-/* -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
+// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_SYSC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_SYSC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_SYSC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_SYSC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_SYSC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_SYSC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_WDTC
-{
- AT91_REG WDTC_WDCR; /* Watchdog Control Register */
- AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
- AT91_REG WDTC_WDSR; /* Watchdog Status Register */
-} AT91S_WDTC, * AT91PS_WDTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
-/* -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
-#define AT91C_SYSC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */
-/* -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
-#define AT91C_SYSC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_SYSC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */
-#define AT91C_SYSC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */
-#define AT91C_SYSC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_SYSC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */
-#define AT91C_SYSC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
-#define AT91C_SYSC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */
-#define AT91C_SYSC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */
-/* -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
-#define AT91C_SYSC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */
-#define AT91C_SYSC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */
+// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_SYSC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
+// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_SYSC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_SYSC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_SYSC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_SYSC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_SYSC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_SYSC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_SYSC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_SYSC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Memory Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_MC
-{
- AT91_REG MC_RCR; /* MC Remap Control Register */
- AT91_REG MC_ASR; /* MC Abort Status Register */
- AT91_REG MC_AASR; /* MC Abort Address Status Register */
- AT91_REG Reserved0[ 21 ]; /* */
- AT91_REG MC_FMR; /* MC Flash Mode Register */
- AT91_REG MC_FCR; /* MC Flash Command Register */
- AT91_REG MC_FSR; /* MC Flash Status Register */
-} AT91S_MC, * AT91PS_MC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved0[21]; //
+ AT91_REG MC_FMR; // MC Flash Mode Register
+ AT91_REG MC_FCR; // MC Flash Command Register
+ AT91_REG MC_FSR; // MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
-/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
-#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
-/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
-#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
-#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
-#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
-#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */
-#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */
-#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */
-#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */
-#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */
-#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */
-#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */
-#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */
-#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */
-/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
-#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */
-#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */
-#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */
-#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */
-#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */
-#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */
-#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */
-#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
-/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
-#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */
-#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */
-#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
-#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
-#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */
-#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */
-#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */
-#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
-#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
-/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
-#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */
-#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */
-#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */
-#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */
-#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */
-#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */
-#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */
-#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */
-#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SPI
-{
- AT91_REG SPI_CR; /* Control Register */
- AT91_REG SPI_MR; /* Mode Register */
- AT91_REG SPI_RDR; /* Receive Data Register */
- AT91_REG SPI_TDR; /* Transmit Data Register */
- AT91_REG SPI_SR; /* Status Register */
- AT91_REG SPI_IER; /* Interrupt Enable Register */
- AT91_REG SPI_IDR; /* Interrupt Disable Register */
- AT91_REG SPI_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved0[ 4 ]; /* */
- AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */
- AT91_REG Reserved1[ 48 ]; /* */
- AT91_REG SPI_RPR; /* Receive Pointer Register */
- AT91_REG SPI_RCR; /* Receive Counter Register */
- AT91_REG SPI_TPR; /* Transmit Pointer Register */
- AT91_REG SPI_TCR; /* Transmit Counter Register */
- AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
- AT91_REG SPI_RNCR; /* Receive Next Counter Register */
- AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
- AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
- AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
-} AT91S_SPI, * AT91PS_SPI;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */
-#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */
-#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */
-#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */
-#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Active After Transfer */
-#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 2) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
-/* ***************************************************************************** */
-typedef struct _AT91S_ADC
-{
- AT91_REG ADC_CR; /* ADC Control Register */
- AT91_REG ADC_MR; /* ADC Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG ADC_CHER; /* ADC Channel Enable Register */
- AT91_REG ADC_CHDR; /* ADC Channel Disable Register */
- AT91_REG ADC_CHSR; /* ADC Channel Status Register */
- AT91_REG ADC_SR; /* ADC Status Register */
- AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */
- AT91_REG ADC_IER; /* ADC Interrupt Enable Register */
- AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */
- AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */
- AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */
- AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */
- AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */
- AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */
- AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */
- AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */
- AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */
- AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */
- AT91_REG Reserved1[ 44 ]; /* */
- AT91_REG ADC_RPR; /* Receive Pointer Register */
- AT91_REG ADC_RCR; /* Receive Counter Register */
- AT91_REG ADC_TPR; /* Transmit Pointer Register */
- AT91_REG ADC_TCR; /* Transmit Counter Register */
- AT91_REG ADC_RNPR; /* Receive Next Pointer Register */
- AT91_REG ADC_RNCR; /* Receive Next Counter Register */
- AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG ADC_TNCR; /* Transmit Next Counter Register */
- AT91_REG ADC_PTCR; /* PDC Transfer Control Register */
- AT91_REG ADC_PTSR; /* PDC Transfer Status Register */
-} AT91S_ADC, * AT91PS_ADC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+ AT91_REG ADC_CR; // ADC Control Register
+ AT91_REG ADC_MR; // ADC Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
+ AT91_REG ADC_SR; // ADC Status Register
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
+ AT91_REG Reserved1[44]; //
+ AT91_REG ADC_RPR; // Receive Pointer Register
+ AT91_REG ADC_RCR; // Receive Counter Register
+ AT91_REG ADC_TPR; // Transmit Pointer Register
+ AT91_REG ADC_TCR; // Transmit Counter Register
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
-/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
-#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */
-#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */
-/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
-#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */
-#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software */
-#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
-#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */
-#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */
-#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */
-#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */
-#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */
-#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */
-#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */
-#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */
-#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */
-#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */
-#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */
-#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */
-#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */
-#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
-#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */
-/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
-#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */
-#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */
-#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */
-#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */
-#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */
-#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */
-#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */
-#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */
-/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
-/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
-/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
-#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */
-#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */
-#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */
-#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */
-/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
-#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
-/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
-/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
-/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
-/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
-#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */
-/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
-/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
-/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
-/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
-/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
-/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
-/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SSC
-{
- AT91_REG SSC_CR; /* Control Register */
- AT91_REG SSC_CMR; /* Clock Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */
- AT91_REG SSC_RFMR; /* Receive Frame Mode Register */
- AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */
- AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */
- AT91_REG SSC_RHR; /* Receive Holding Register */
- AT91_REG SSC_THR; /* Transmit Holding Register */
- AT91_REG Reserved1[ 2 ]; /* */
- AT91_REG SSC_RSHR; /* Receive Sync Holding Register */
- AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */
- AT91_REG SSC_RC0R; /* Receive Compare 0 Register */
- AT91_REG SSC_RC1R; /* Receive Compare 1 Register */
- AT91_REG SSC_SR; /* Status Register */
- AT91_REG SSC_IER; /* Interrupt Enable Register */
- AT91_REG SSC_IDR; /* Interrupt Disable Register */
- AT91_REG SSC_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved2[ 44 ]; /* */
- AT91_REG SSC_RPR; /* Receive Pointer Register */
- AT91_REG SSC_RCR; /* Receive Counter Register */
- AT91_REG SSC_TPR; /* Transmit Pointer Register */
- AT91_REG SSC_TCR; /* Transmit Counter Register */
- AT91_REG SSC_RNPR; /* Receive Next Pointer Register */
- AT91_REG SSC_RNCR; /* Receive Next Counter Register */
- AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SSC_TNCR; /* Transmit Next Counter Register */
- AT91_REG SSC_PTCR; /* PDC Transfer Control Register */
- AT91_REG SSC_PTSR; /* PDC Transfer Status Register */
-} AT91S_SSC, * AT91PS_SSC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG SSC_RC0R; // Receive Compare 0 Register
+ AT91_REG SSC_RC1R; // Receive Compare 1 Register
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
-/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
-#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */
-#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */
-#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */
-#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */
-/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
-#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */
-#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */
-#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */
-#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */
-#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */
-#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
-#define AT91C_SSC_CKO_CONTINOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
-#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
-#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */
-#define AT91C_SSC_CKG ( ( unsigned int ) 0x3 << 6 ) /* (SSC) Receive/Transmit Clock Gating Selection */
-#define AT91C_SSC_CKG_NONE ( ( unsigned int ) 0x0 << 6 ) /* (SSC) Receive/Transmit Clock Gating: None, continuous clock */
-#define AT91C_SSC_CKG_LOW ( ( unsigned int ) 0x1 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF Low */
-#define AT91C_SSC_CKG_HIGH ( ( unsigned int ) 0x2 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF High */
-#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */
-#define AT91C_SSC_START_CONTINOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
-#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */
-#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */
-#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */
-#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */
-#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */
-#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */
-#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */
-#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */
-#define AT91C_SSC_STOP ( ( unsigned int ) 0x1 << 12 ) /* (SSC) Receive Stop Selection */
-#define AT91C_SSC_STTOUT ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Receive/Transmit Start Output Selection */
-#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
-#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
-/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
-#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */
-#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */
-#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */
-#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */
-#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */
-#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */
-#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
-#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
-#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
-#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
-#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
-#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
-#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */
-/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
-/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
-#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */
-#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
-/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
-#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */
-#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */
-#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */
-#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */
-#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */
-#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */
-#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */
-#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */
-#define AT91C_SSC_CP0 ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Compare 0 */
-#define AT91C_SSC_CP1 ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Compare 1 */
-#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
-#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
-#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
-/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
-/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
+#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0
+#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Usart */
-/* ***************************************************************************** */
-typedef struct _AT91S_USART
-{
- AT91_REG US_CR; /* Control Register */
- AT91_REG US_MR; /* Mode Register */
- AT91_REG US_IER; /* Interrupt Enable Register */
- AT91_REG US_IDR; /* Interrupt Disable Register */
- AT91_REG US_IMR; /* Interrupt Mask Register */
- AT91_REG US_CSR; /* Channel Status Register */
- AT91_REG US_RHR; /* Receiver Holding Register */
- AT91_REG US_THR; /* Transmitter Holding Register */
- AT91_REG US_BRGR; /* Baud Rate Generator Register */
- AT91_REG US_RTOR; /* Receiver Time-out Register */
- AT91_REG US_TTGR; /* Transmitter Time-guard Register */
- AT91_REG Reserved0[ 5 ]; /* */
- AT91_REG US_FIDI; /* FI_DI_Ratio Register */
- AT91_REG US_NER; /* Nb Errors Register */
- AT91_REG US_XXR; /* XON_XOFF Register */
- AT91_REG US_IF; /* IRDA_FILTER Register */
- AT91_REG Reserved1[ 44 ]; /* */
- AT91_REG US_RPR; /* Receive Pointer Register */
- AT91_REG US_RCR; /* Receive Counter Register */
- AT91_REG US_TPR; /* Transmit Pointer Register */
- AT91_REG US_TCR; /* Transmit Counter Register */
- AT91_REG US_RNPR; /* Receive Next Pointer Register */
- AT91_REG US_RNCR; /* Receive Next Counter Register */
- AT91_REG US_TNPR; /* Transmit Next Pointer Register */
- AT91_REG US_TNCR; /* Transmit Next Counter Register */
- AT91_REG US_PTCR; /* PDC Transfer Control Register */
- AT91_REG US_PTSR; /* PDC Transfer Status Register */
-} AT91S_USART, * AT91PS_USART;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG US_XXR; // XON_XOFF Register
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved1[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
-/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (USART) Reset Status Bits */
-#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */
-#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
-#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
-#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
-#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
-#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
-#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
-#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
-#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
-#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
-#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
-/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */
-#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */
-#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */
-#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */
-#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */
-#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */
-#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */
-#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */
-#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */
-#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */
-#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */
-#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
-#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
-#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
-#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
-#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
-#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
-#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
-#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
-#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
-#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
-/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */
-#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */
-#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
-#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
-#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
-#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
-#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
-#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
-/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
-#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */
-#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */
-#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */
-#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TWI
-{
- AT91_REG TWI_CR; /* Control Register */
- AT91_REG TWI_MMR; /* Master Mode Register */
- AT91_REG TWI_SMR; /* Slave Mode Register */
- AT91_REG TWI_IADR; /* Internal Address Register */
- AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
- AT91_REG Reserved0[ 3 ]; /* */
- AT91_REG TWI_SR; /* Status Register */
- AT91_REG TWI_IER; /* Interrupt Enable Register */
- AT91_REG TWI_IDR; /* Interrupt Disable Register */
- AT91_REG TWI_IMR; /* Interrupt Mask Register */
- AT91_REG TWI_RHR; /* Receive Holding Register */
- AT91_REG TWI_THR; /* Transmit Holding Register */
-} AT91S_TWI, * AT91PS_TWI;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG TWI_SMR; // Slave Mode Register
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved0[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
-/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
-#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */
-#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */
-#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */
-#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */
-#define AT91C_TWI_SVEN ( ( unsigned int ) 0x1 << 4 ) /* (TWI) TWI Slave Transfer Enabled */
-#define AT91C_TWI_SVDIS ( ( unsigned int ) 0x1 << 5 ) /* (TWI) TWI Slave Transfer Disabled */
-#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
-#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */
-#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */
-#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */
-#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */
-#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */
-#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */
-#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
-/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */
-#define AT91C_TWI_SADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Slave Device Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
-#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */
-#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */
-#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
-#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */
-#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */
-#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */
-#define AT91C_TWI_SVREAD ( ( unsigned int ) 0x1 << 3 ) /* (TWI) Slave Read */
-#define AT91C_TWI_SVACC ( ( unsigned int ) 0x1 << 4 ) /* (TWI) Slave Access */
-#define AT91C_TWI_GCACC ( ( unsigned int ) 0x1 << 5 ) /* (TWI) General Call Access */
-#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */
-#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */
-#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */
-#define AT91C_TWI_ARBLST ( ( unsigned int ) 0x1 << 9 ) /* (TWI) Arbitration Lost */
-/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
-/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled
+#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
+#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read
+#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access
+#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TC
-{
- AT91_REG TC_CCR; /* Channel Control Register */
- AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG TC_CV; /* Counter Value */
- AT91_REG TC_RA; /* Register A */
- AT91_REG TC_RB; /* Register B */
- AT91_REG TC_RC; /* Register C */
- AT91_REG TC_SR; /* Status Register */
- AT91_REG TC_IER; /* Interrupt Enable Register */
- AT91_REG TC_IDR; /* Interrupt Disable Register */
- AT91_REG TC_IMR; /* Interrupt Mask Register */
-} AT91S_TC, * AT91PS_TC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
-/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
-#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */
-#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */
-/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
-#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */
-#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */
-#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */
-#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */
-#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */
-#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */
-#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */
-#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */
-#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */
-#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */
-#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */
-#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */
-#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */
-#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */
-#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
-#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */
-#define AT91C_TC_EEVT_NONE ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
-#define AT91C_TC_EEVT_RISING ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
-#define AT91C_TC_EEVT_FALLING ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
-#define AT91C_TC_EEVT_BOTH ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
-#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
-#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */
-#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
-#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
-#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
-#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
-#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
-#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
-#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
-#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
-#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
-#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
-#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
-#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
-#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
-#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
-#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
-#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
-#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
-#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
-#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
-#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
-#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
-#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
-#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
-#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
-#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
-#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
-#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
-#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
-/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
-#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */
-#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */
-#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */
-#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */
-#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */
-#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */
-#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */
-#define AT91C_TC_ETRCS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */
-#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
-#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
-#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
-/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
-/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
-/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TCB
-{
- AT91S_TC TCB_TC0; /* TC Channel 0 */
- AT91_REG Reserved0[ 4 ]; /* */
- AT91S_TC TCB_TC1; /* TC Channel 1 */
- AT91_REG Reserved1[ 4 ]; /* */
- AT91S_TC TCB_TC2; /* TC Channel 2 */
- AT91_REG Reserved2[ 4 ]; /* */
- AT91_REG TCB_BCR; /* TC Block Control Register */
- AT91_REG TCB_BMR; /* TC Block Mode Register */
-} AT91S_TCB, * AT91PS_TCB;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
-/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
-#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
-/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
-#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x1 << 0 ) /* (TCB) External Clock Signal 0 Selection */
-#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */
-#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x1 << 2 ) /* (TCB) External Clock Signal 1 Selection */
-#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
-#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x1 << 4 ) /* (TCB) External Clock Signal 2 Selection */
-#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA2 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PWMC_CH
-{
- AT91_REG PWMC_CMR; /* Channel Mode Register */
- AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */
- AT91_REG PWMC_CPRDR; /* Channel Period Register */
- AT91_REG PWMC_CCNTR; /* Channel Counter Register */
- AT91_REG PWMC_CUPDR; /* Channel Update Register */
- AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
-} AT91S_PWMC_CH, * AT91PS_PWMC_CH;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+ AT91_REG PWMC_CMR; // Channel Mode Register
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
+ AT91_REG PWMC_CPRDR; // Channel Period Register
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
+ AT91_REG PWMC_CUPDR; // Channel Update Register
+ AT91_REG PWMC_Reserved[3]; // Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
-#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
-#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */
-#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */
-#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */
-#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
-/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
-#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */
-/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
-#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */
-/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
-#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */
-/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
-#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PWMC
-{
- AT91_REG PWMC_MR; /* PWMC Mode Register */
- AT91_REG PWMC_ENA; /* PWMC Enable Register */
- AT91_REG PWMC_DIS; /* PWMC Disable Register */
- AT91_REG PWMC_SR; /* PWMC Status Register */
- AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */
- AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */
- AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */
- AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */
- AT91_REG Reserved0[ 55 ]; /* */
- AT91_REG PWMC_VR; /* PWMC Version Register */
- AT91_REG Reserved1[ 64 ]; /* */
- AT91S_PWMC_CH PWMC_CH[ 32 ]; /* PWMC Channel 0 */
-} AT91S_PWMC, * AT91PS_PWMC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+ AT91_REG PWMC_MR; // PWMC Mode Register
+ AT91_REG PWMC_ENA; // PWMC Enable Register
+ AT91_REG PWMC_DIS; // PWMC Disable Register
+ AT91_REG PWMC_SR; // PWMC Status Register
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
+ AT91_REG Reserved0[55]; //
+ AT91_REG PWMC_VR; // PWMC Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0
+} AT91S_PWMC, *AT91PS_PWMC;
-/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
-#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */
-#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */
-#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */
-#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
-#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */
-#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */
-/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
-#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
-#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
-#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
-#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
-#define AT91C_PWMC_CHID4 ( ( unsigned int ) 0x1 << 4 ) /* (PWMC) Channel ID 4 */
-#define AT91C_PWMC_CHID5 ( ( unsigned int ) 0x1 << 5 ) /* (PWMC) Channel ID 5 */
-#define AT91C_PWMC_CHID6 ( ( unsigned int ) 0x1 << 6 ) /* (PWMC) Channel ID 6 */
-#define AT91C_PWMC_CHID7 ( ( unsigned int ) 0x1 << 7 ) /* (PWMC) Channel ID 7 */
-/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
-/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
-/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
-/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
-/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
-/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
+#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4
+#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5
+#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6
+#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR USB Device Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_UDP
-{
- AT91_REG UDP_NUM; /* Frame Number Register */
- AT91_REG UDP_GLBSTATE; /* Global State Register */
- AT91_REG UDP_FADDR; /* Function Address Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG UDP_IER; /* Interrupt Enable Register */
- AT91_REG UDP_IDR; /* Interrupt Disable Register */
- AT91_REG UDP_IMR; /* Interrupt Mask Register */
- AT91_REG UDP_ISR; /* Interrupt Status Register */
- AT91_REG UDP_ICR; /* Interrupt Clear Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG UDP_RSTEP; /* Reset Endpoint Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG UDP_CSR[ 8 ]; /* Endpoint Control and Status Register */
- AT91_REG UDP_FDR[ 8 ]; /* Endpoint FIFO Data Register */
-} AT91S_UDP, * AT91PS_UDP;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register
+ AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register
+} AT91S_UDP, *AT91PS_UDP;
-/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
-#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
-#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */
-#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */
-/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
-#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */
-#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */
-#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Remote Wake Up Enable */
-#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */
-/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
-#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */
-#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */
-/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
-#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
-#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */
-#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */
-#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */
-#define AT91C_UDP_EPINT6 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Endpoint 6 Interrupt */
-#define AT91C_UDP_EPINT7 ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Endpoint 7 Interrupt */
-#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */
-#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */
-#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */
-#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */
-#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */
-/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
-/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
-/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
-#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
-/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
-/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
-#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */
-#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */
-#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */
-#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */
-#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */
-#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */
-#define AT91C_UDP_EP6 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Reset Endpoint 6 */
-#define AT91C_UDP_EP7 ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Reset Endpoint 7 */
-/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
-#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */
-#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */
-#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */
-#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */
-#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */
-#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
-#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
-#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */
-#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */
-#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */
-#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */
-#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */
-#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */
-#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */
-#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */
-#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */
-#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */
-#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */
-#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-/* ***************************************************************************** */
-/* REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 */
-/* ***************************************************************************** */
-/* ========== Register definition for SYSC peripheral ========== */
-#define AT91C_SYSC_SYSC_VRPM ( ( AT91_REG * ) 0xFFFFFD60 ) /* (SYSC) Voltage Regulator Power Mode Register */
-/* ========== Register definition for AIC peripheral ========== */
-#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
-#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
-#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
-#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
-#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
-#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
-#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
-#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
-#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
-#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
-#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
-#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
-#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
-#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
-#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
-#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
-#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
-#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
-/* ========== Register definition for DBGU peripheral ========== */
-#define AT91C_DBGU_C2R ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID2 Register */
-#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
-#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
-#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
-#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
-#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
-#define AT91C_DBGU_C1R ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID1 Register */
-#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
-#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
-#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
-#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
-#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
-/* ========== Register definition for PDC_DBGU peripheral ========== */
-#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
-#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
-#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
-#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
-#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
-#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
-#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
-#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
-#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
-#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
-/* ========== Register definition for PIOA peripheral ========== */
-#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
-#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
-#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
-#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
-#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
-#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
-#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
-#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
-#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
-#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
-#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
-#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
-#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
-#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
-#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
-#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
-#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pad Pull-up Status Register */
-#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
-#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
-#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
-#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
-#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
-#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
-#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
-#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
-#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
-#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
-/* ========== Register definition for CKGR peripheral ========== */
-#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
-#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */
-#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
-/* ========== Register definition for PMC peripheral ========== */
-#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
-#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
-#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
-#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
-#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
-#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
-#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
-#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
-#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
-#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
-#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
-#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
-#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */
-#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
-/* ========== Register definition for RSTC peripheral ========== */
-#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
-#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
-#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
-/* ========== Register definition for RTTC peripheral ========== */
-#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
-#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
-#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
-#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
-/* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
-#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
-#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
-#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
-/* ========== Register definition for WDTC peripheral ========== */
-#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
-#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
-#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
-/* ========== Register definition for MC peripheral ========== */
-#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
-#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
-#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
-#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
-#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
-#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
-/* ========== Register definition for PDC_SPI peripheral ========== */
-#define AT91C_SPI_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI) PDC Transfer Control Register */
-#define AT91C_SPI_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI) Transmit Next Pointer Register */
-#define AT91C_SPI_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI) Receive Next Pointer Register */
-#define AT91C_SPI_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI) Transmit Pointer Register */
-#define AT91C_SPI_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI) Receive Pointer Register */
-#define AT91C_SPI_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI) PDC Transfer Status Register */
-#define AT91C_SPI_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI) Transmit Next Counter Register */
-#define AT91C_SPI_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI) Receive Next Counter Register */
-#define AT91C_SPI_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI) Transmit Counter Register */
-#define AT91C_SPI_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI) Receive Counter Register */
-/* ========== Register definition for SPI peripheral ========== */
-#define AT91C_SPI_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI) Chip Select Register */
-#define AT91C_SPI_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI) Interrupt Disable Register */
-#define AT91C_SPI_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI) Status Register */
-#define AT91C_SPI_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI) Receive Data Register */
-#define AT91C_SPI_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI) Control Register */
-#define AT91C_SPI_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI) Interrupt Mask Register */
-#define AT91C_SPI_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI) Interrupt Enable Register */
-#define AT91C_SPI_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI) Transmit Data Register */
-#define AT91C_SPI_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI) Mode Register */
-/* ========== Register definition for PDC_ADC peripheral ========== */
-#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
-#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
-#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
-#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
-#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
-#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
-#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
-#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
-#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
-#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
-/* ========== Register definition for ADC peripheral ========== */
-#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
-#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
-#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
-#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
-#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
-#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
-#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
-#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
-#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
-#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
-#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
-#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
-#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
-#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
-#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
-#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
-#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
-#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
-/* ========== Register definition for PDC_SSC peripheral ========== */
-#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
-#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
-#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
-#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
-#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
-#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
-#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
-#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
-#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
-#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
-/* ========== Register definition for SSC peripheral ========== */
-#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
-#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
-#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
-#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
-#define AT91C_SSC_RC0R ( ( AT91_REG * ) 0xFFFD4038 ) /* (SSC) Receive Compare 0 Register */
-#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
-#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
-#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
-#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
-#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
-#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
-#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
-#define AT91C_SSC_RC1R ( ( AT91_REG * ) 0xFFFD403C ) /* (SSC) Receive Compare 1 Register */
-#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
-#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
-#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
-/* ========== Register definition for PDC_US1 peripheral ========== */
-#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
-#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
-#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
-#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
-#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
-#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
-#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
-#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
-#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
-#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
-/* ========== Register definition for US1 peripheral ========== */
-#define AT91C_US1_XXR ( ( AT91_REG * ) 0xFFFC4048 ) /* (US1) XON_XOFF Register */
-#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
-#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
-#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
-#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
-#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
-#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
-#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
-#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
-#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
-#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
-#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
-#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
-#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
-#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
-/* ========== Register definition for PDC_US0 peripheral ========== */
-#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
-#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
-#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
-#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
-#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
-#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
-#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
-#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
-#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
-#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
-/* ========== Register definition for US0 peripheral ========== */
-#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
-#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
-#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
-#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
-#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
-#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
-#define AT91C_US0_XXR ( ( AT91_REG * ) 0xFFFC0048 ) /* (US0) XON_XOFF Register */
-#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
-#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
-#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
-#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
-#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
-#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
-#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
-#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
-/* ========== Register definition for TWI peripheral ========== */
-#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
-#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
-#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
-#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
-#define AT91C_TWI_SMR ( ( AT91_REG * ) 0xFFFB8008 ) /* (TWI) Slave Mode Register */
-#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
-#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
-#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
-#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
-#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
-#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
-/* ========== Register definition for TC2 peripheral ========== */
-#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
-#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
-#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
-#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
-#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
-#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
-#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
-#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
-#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
-/* ========== Register definition for TC1 peripheral ========== */
-#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
-#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
-#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
-#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
-#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
-#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
-#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
-#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
-#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
-/* ========== Register definition for TC0 peripheral ========== */
-#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
-#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
-#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
-#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
-#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
-#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
-#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
-#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
-#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
-/* ========== Register definition for TCB peripheral ========== */
-#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
-#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
-/* ========== Register definition for PWMC_CH3 peripheral ========== */
-#define AT91C_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
-#define AT91C_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
-#define AT91C_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
-#define AT91C_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
-#define AT91C_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
-#define AT91C_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH2 peripheral ========== */
-#define AT91C_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
-#define AT91C_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
-#define AT91C_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
-#define AT91C_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
-#define AT91C_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
-#define AT91C_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH1 peripheral ========== */
-#define AT91C_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
-#define AT91C_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
-#define AT91C_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
-#define AT91C_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
-#define AT91C_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
-#define AT91C_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH0 peripheral ========== */
-#define AT91C_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
-#define AT91C_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
-#define AT91C_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
-#define AT91C_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
-#define AT91C_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
-#define AT91C_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC peripheral ========== */
-#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
-#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
-#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
-#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
-#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
-#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
-#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
-#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
-#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
-/* ========== Register definition for UDP peripheral ========== */
-#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
-#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
-#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
-#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
-#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
-#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
-#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
-#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
-#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
-#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
-#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
+// *****************************************************************************
+// ========== Register definition for SYSC peripheral ==========
+#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
+// ========== Register definition for PDC_SPI peripheral ==========
+#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
+#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
+#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
+// ========== Register definition for SPI peripheral ==========
+#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
+#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register
+#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
+#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register
+#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
+#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC) Receive Compare 0 Register
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC) Receive Compare 1 Register
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-/* ***************************************************************************** */
-/* PIO DEFINITIONS FOR AT91SAM7S64 */
-/* ***************************************************************************** */
-#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */
-#define AT91C_PA0_PWM0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* PWM Channel 0 */
-#define AT91C_PA0_TIOA0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */
-#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */
-#define AT91C_PA1_PWM1 ( ( unsigned int ) AT91C_PIO_PA1 ) /* PWM Channel 1 */
-#define AT91C_PA1_TIOB0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */
-#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */
-#define AT91C_PA10_DTXD ( ( unsigned int ) AT91C_PIO_PA10 ) /* DBGU Debug Transmit Data */
-#define AT91C_PA10_NPCS2 ( ( unsigned int ) AT91C_PIO_PA10 ) /* SPI Peripheral Chip Select 2 */
-#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */
-#define AT91C_PA11_NPCS0 ( ( unsigned int ) AT91C_PIO_PA11 ) /* SPI Peripheral Chip Select 0 */
-#define AT91C_PA11_PWM0 ( ( unsigned int ) AT91C_PIO_PA11 ) /* PWM Channel 0 */
-#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */
-#define AT91C_PA12_MISO ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI Master In Slave */
-#define AT91C_PA12_PWM1 ( ( unsigned int ) AT91C_PIO_PA12 ) /* PWM Channel 1 */
-#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */
-#define AT91C_PA13_MOSI ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI Master Out Slave */
-#define AT91C_PA13_PWM2 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PWM Channel 2 */
-#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */
-#define AT91C_PA14_SPCK ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI Serial Clock */
-#define AT91C_PA14_PWM3 ( ( unsigned int ) AT91C_PIO_PA14 ) /* PWM Channel 3 */
-#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */
-#define AT91C_PA15_TF ( ( unsigned int ) AT91C_PIO_PA15 ) /* SSC Transmit Frame Sync */
-#define AT91C_PA15_TIOA1 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */
-#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */
-#define AT91C_PA16_TK ( ( unsigned int ) AT91C_PIO_PA16 ) /* SSC Transmit Clock */
-#define AT91C_PA16_TIOB1 ( ( unsigned int ) AT91C_PIO_PA16 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */
-#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */
-#define AT91C_PA17_TD ( ( unsigned int ) AT91C_PIO_PA17 ) /* SSC Transmit data */
-#define AT91C_PA17_PCK1 ( ( unsigned int ) AT91C_PIO_PA17 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */
-#define AT91C_PA18_RD ( ( unsigned int ) AT91C_PIO_PA18 ) /* SSC Receive Data */
-#define AT91C_PA18_PCK2 ( ( unsigned int ) AT91C_PIO_PA18 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */
-#define AT91C_PA19_RK ( ( unsigned int ) AT91C_PIO_PA19 ) /* SSC Receive Clock */
-#define AT91C_PA19_FIQ ( ( unsigned int ) AT91C_PIO_PA19 ) /* AIC Fast Interrupt Input */
-#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */
-#define AT91C_PA2_PWM2 ( ( unsigned int ) AT91C_PIO_PA2 ) /* PWM Channel 2 */
-#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */
-#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */
-#define AT91C_PA20_RF ( ( unsigned int ) AT91C_PIO_PA20 ) /* SSC Receive Frame Sync */
-#define AT91C_PA20_IRQ0 ( ( unsigned int ) AT91C_PIO_PA20 ) /* External Interrupt 0 */
-#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */
-#define AT91C_PA21_RXD1 ( ( unsigned int ) AT91C_PIO_PA21 ) /* USART 1 Receive Data */
-#define AT91C_PA21_PCK1 ( ( unsigned int ) AT91C_PIO_PA21 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */
-#define AT91C_PA22_TXD1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* USART 1 Transmit Data */
-#define AT91C_PA22_NPCS3 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI Peripheral Chip Select 3 */
-#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */
-#define AT91C_PA23_SCK1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* USART 1 Serial Clock */
-#define AT91C_PA23_PWM0 ( ( unsigned int ) AT91C_PIO_PA23 ) /* PWM Channel 0 */
-#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */
-#define AT91C_PA24_RTS1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* USART 1 Ready To Send */
-#define AT91C_PA24_PWM1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* PWM Channel 1 */
-#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */
-#define AT91C_PA25_CTS1 ( ( unsigned int ) AT91C_PIO_PA25 ) /* USART 1 Clear To Send */
-#define AT91C_PA25_PWM2 ( ( unsigned int ) AT91C_PIO_PA25 ) /* PWM Channel 2 */
-#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */
-#define AT91C_PA26_DCD1 ( ( unsigned int ) AT91C_PIO_PA26 ) /* USART 1 Data Carrier Detect */
-#define AT91C_PA26_TIOA2 ( ( unsigned int ) AT91C_PIO_PA26 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */
-#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */
-#define AT91C_PA27_DTR1 ( ( unsigned int ) AT91C_PIO_PA27 ) /* USART 1 Data Terminal ready */
-#define AT91C_PA27_TIOB2 ( ( unsigned int ) AT91C_PIO_PA27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */
-#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */
-#define AT91C_PA28_DSR1 ( ( unsigned int ) AT91C_PIO_PA28 ) /* USART 1 Data Set ready */
-#define AT91C_PA28_TCLK1 ( ( unsigned int ) AT91C_PIO_PA28 ) /* Timer Counter 1 external clock input */
-#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */
-#define AT91C_PA29_RI1 ( ( unsigned int ) AT91C_PIO_PA29 ) /* USART 1 Ring Indicator */
-#define AT91C_PA29_TCLK2 ( ( unsigned int ) AT91C_PIO_PA29 ) /* Timer Counter 2 external clock input */
-#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */
-#define AT91C_PA3_TWD ( ( unsigned int ) AT91C_PIO_PA3 ) /* TWI Two-wire Serial Data */
-#define AT91C_PA3_NPCS3 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI Peripheral Chip Select 3 */
-#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */
-#define AT91C_PA30_IRQ1 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 1 */
-#define AT91C_PA30_NPCS2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* SPI Peripheral Chip Select 2 */
-#define AT91C_PIO_PA31 ( ( unsigned int ) 1 << 31 ) /* Pin Controlled by PA31 */
-#define AT91C_PA31_NPCS1 ( ( unsigned int ) AT91C_PIO_PA31 ) /* SPI Peripheral Chip Select 1 */
-#define AT91C_PA31_PCK2 ( ( unsigned int ) AT91C_PIO_PA31 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */
-#define AT91C_PA4_TWCK ( ( unsigned int ) AT91C_PIO_PA4 ) /* TWI Two-wire Serial Clock */
-#define AT91C_PA4_TCLK0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* Timer Counter 0 external clock input */
-#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */
-#define AT91C_PA5_RXD0 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 0 Receive Data */
-#define AT91C_PA5_NPCS3 ( ( unsigned int ) AT91C_PIO_PA5 ) /* SPI Peripheral Chip Select 3 */
-#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */
-#define AT91C_PA6_TXD0 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 0 Transmit Data */
-#define AT91C_PA6_PCK0 ( ( unsigned int ) AT91C_PIO_PA6 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */
-#define AT91C_PA7_RTS0 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 0 Ready To Send */
-#define AT91C_PA7_PWM3 ( ( unsigned int ) AT91C_PIO_PA7 ) /* PWM Channel 3 */
-#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */
-#define AT91C_PA8_CTS0 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 0 Clear To Send */
-#define AT91C_PA8_ADTRG ( ( unsigned int ) AT91C_PIO_PA8 ) /* ADC External Trigger */
-#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */
-#define AT91C_PA9_DRXD ( ( unsigned int ) AT91C_PIO_PA9 ) /* DBGU Debug Receive Data */
-#define AT91C_PA9_NPCS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI Peripheral Chip Select 1 */
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0
+#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1
+#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data
+#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
+#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave
+#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave
+#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock
+#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync
+#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock
+#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data
+#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data
+#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock
+#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync
+#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data
+#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data
+#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock
+#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send
+#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send
+#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect
+#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready
+#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready
+#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator
+#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data
+#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1
+#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
+#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock
+#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data
+#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data
+#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send
+#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send
+#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data
+#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
-/* ***************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */
-/* ***************************************************************************** */
-#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */
-#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller */
-#define AT91C_ID_3_Reserved ( ( unsigned int ) 3 ) /* Reserved */
-#define AT91C_ID_ADC ( ( unsigned int ) 4 ) /* Analog-to-Digital Converter */
-#define AT91C_ID_SPI ( ( unsigned int ) 5 ) /* Serial Peripheral Interface */
-#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */
-#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */
-#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */
-#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */
-#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */
-#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */
-#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */
-#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */
-#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */
-#define AT91C_ID_15_Reserved ( ( unsigned int ) 15 ) /* Reserved */
-#define AT91C_ID_16_Reserved ( ( unsigned int ) 16 ) /* Reserved */
-#define AT91C_ID_17_Reserved ( ( unsigned int ) 17 ) /* Reserved */
-#define AT91C_ID_18_Reserved ( ( unsigned int ) 18 ) /* Reserved */
-#define AT91C_ID_19_Reserved ( ( unsigned int ) 19 ) /* Reserved */
-#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */
-#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */
-#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */
-#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */
-#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */
-#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */
-#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */
-#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */
-#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */
-#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */
-#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller
+#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved
+#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter
+#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved
+#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved
+#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved
+#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
+#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-/* ***************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 */
-/* ***************************************************************************** */
-#define AT91C_BASE_SYSC ( ( AT91PS_SYSC ) 0xFFFFF000 ) /* (SYSC) Base Address */
-#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */
-#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */
-#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */
-#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */
-#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */
-#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */
-#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */
-#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */
-#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */
-#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */
-#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */
-#define AT91C_BASE_PDC_SPI ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI) Base Address */
-#define AT91C_BASE_SPI ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI) Base Address */
-#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */
-#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */
-#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */
-#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */
-#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */
-#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */
-#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */
-#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */
-#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */
-#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */
-#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */
-#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */
-#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */
-#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
-#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
-#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
-#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
-#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */
-#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_BASE_SYSC ((AT91PS_SYSC) 0xFFFFF000) // (SYSC) Base Address
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-/* ***************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 */
-/* ***************************************************************************** */
-#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */
-#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00004000 ) /* Internal SRAM size in byte (16 Kbyte) */
-#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */
-#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal ROM size in byte (64 Kbyte) */
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte)
-#endif /* ifndef AT91SAM7S64_H */
+#endif
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
index 2c7a899..7d2657a 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
@@ -1,1810 +1,1812 @@
-/* ---------------------------------------------------------------------------- */
-/* ATMEL Microcontroller Software Support - ROUSSET - */
-/* ---------------------------------------------------------------------------- */
-/* The software is delivered "AS IS" without warranty or condition of any */
-/* kind, either express, implied or statutory. This includes without */
-/* limitation any warranty or condition with respect to merchantability or */
-/* fitness for any particular purpose, or against the infringements of */
-/* intellectual property rights of others. */
-/* ---------------------------------------------------------------------------- */
-/* File Name : AT91SAM7S64.h */
-/* Object : AT91SAM7S64 definitions */
-/* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) */
-/* */
-/* CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// */
-/* CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// */
-/* CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// */
-/* CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// */
-/* CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */
-/* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */
-/* CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */
-/* CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// */
-/* CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// */
-/* CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// */
-/* CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// */
-/* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
-/* CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// */
-/* CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// */
-/* CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// */
-/* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
-/* ---------------------------------------------------------------------------- */
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// The software is delivered "AS IS" without warranty or condition of any
+// kind, either express, implied or statutory. This includes without
+// limitation any warranty or condition with respect to merchantability or
+// fitness for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM7S64.h
+// Object : AT91SAM7S64 definitions
+// Generated : AT91 SW Application Group 07/16/2004 (07:43:09)
+//
+// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
+// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
+// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
+// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002//
+// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
+// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
+// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
+// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
+// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002//
+// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003//
+// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
+// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
+// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+// ----------------------------------------------------------------------------
-/* Hardware register definition */
+// Hardware register definition
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR System Peripherals */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_SYSC structure *** */
-#define SYSC_AIC_SMR ( 0 ) /* Source Mode Register */
-#define SYSC_AIC_SVR ( 128 ) /* Source Vector Register */
-#define SYSC_AIC_IVR ( 256 ) /* IRQ Vector Register */
-#define SYSC_AIC_FVR ( 260 ) /* FIQ Vector Register */
-#define SYSC_AIC_ISR ( 264 ) /* Interrupt Status Register */
-#define SYSC_AIC_IPR ( 268 ) /* Interrupt Pending Register */
-#define SYSC_AIC_IMR ( 272 ) /* Interrupt Mask Register */
-#define SYSC_AIC_CISR ( 276 ) /* Core Interrupt Status Register */
-#define SYSC_AIC_IECR ( 288 ) /* Interrupt Enable Command Register */
-#define SYSC_AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */
-#define SYSC_AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */
-#define SYSC_AIC_ISCR ( 300 ) /* Interrupt Set Command Register */
-#define SYSC_AIC_EOICR ( 304 ) /* End of Interrupt Command Register */
-#define SYSC_AIC_SPU ( 308 ) /* Spurious Vector Register */
-#define SYSC_AIC_DCR ( 312 ) /* Debug Control Register (Protect) */
-#define SYSC_AIC_FFER ( 320 ) /* Fast Forcing Enable Register */
-#define SYSC_AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */
-#define SYSC_AIC_FFSR ( 328 ) /* Fast Forcing Status Register */
-#define SYSC_DBGU_CR ( 512 ) /* Control Register */
-#define SYSC_DBGU_MR ( 516 ) /* Mode Register */
-#define SYSC_DBGU_IER ( 520 ) /* Interrupt Enable Register */
-#define SYSC_DBGU_IDR ( 524 ) /* Interrupt Disable Register */
-#define SYSC_DBGU_IMR ( 528 ) /* Interrupt Mask Register */
-#define SYSC_DBGU_CSR ( 532 ) /* Channel Status Register */
-#define SYSC_DBGU_RHR ( 536 ) /* Receiver Holding Register */
-#define SYSC_DBGU_THR ( 540 ) /* Transmitter Holding Register */
-#define SYSC_DBGU_BRGR ( 544 ) /* Baud Rate Generator Register */
-#define SYSC_DBGU_C1R ( 576 ) /* Chip ID1 Register */
-#define SYSC_DBGU_C2R ( 580 ) /* Chip ID2 Register */
-#define SYSC_DBGU_FNTR ( 584 ) /* Force NTRST Register */
-#define SYSC_DBGU_RPR ( 768 ) /* Receive Pointer Register */
-#define SYSC_DBGU_RCR ( 772 ) /* Receive Counter Register */
-#define SYSC_DBGU_TPR ( 776 ) /* Transmit Pointer Register */
-#define SYSC_DBGU_TCR ( 780 ) /* Transmit Counter Register */
-#define SYSC_DBGU_RNPR ( 784 ) /* Receive Next Pointer Register */
-#define SYSC_DBGU_RNCR ( 788 ) /* Receive Next Counter Register */
-#define SYSC_DBGU_TNPR ( 792 ) /* Transmit Next Pointer Register */
-#define SYSC_DBGU_TNCR ( 796 ) /* Transmit Next Counter Register */
-#define SYSC_DBGU_PTCR ( 800 ) /* PDC Transfer Control Register */
-#define SYSC_DBGU_PTSR ( 804 ) /* PDC Transfer Status Register */
-#define SYSC_PIOA_PER ( 1024 ) /* PIO Enable Register */
-#define SYSC_PIOA_PDR ( 1028 ) /* PIO Disable Register */
-#define SYSC_PIOA_PSR ( 1032 ) /* PIO Status Register */
-#define SYSC_PIOA_OER ( 1040 ) /* Output Enable Register */
-#define SYSC_PIOA_ODR ( 1044 ) /* Output Disable Registerr */
-#define SYSC_PIOA_OSR ( 1048 ) /* Output Status Register */
-#define SYSC_PIOA_IFER ( 1056 ) /* Input Filter Enable Register */
-#define SYSC_PIOA_IFDR ( 1060 ) /* Input Filter Disable Register */
-#define SYSC_PIOA_IFSR ( 1064 ) /* Input Filter Status Register */
-#define SYSC_PIOA_SODR ( 1072 ) /* Set Output Data Register */
-#define SYSC_PIOA_CODR ( 1076 ) /* Clear Output Data Register */
-#define SYSC_PIOA_ODSR ( 1080 ) /* Output Data Status Register */
-#define SYSC_PIOA_PDSR ( 1084 ) /* Pin Data Status Register */
-#define SYSC_PIOA_IER ( 1088 ) /* Interrupt Enable Register */
-#define SYSC_PIOA_IDR ( 1092 ) /* Interrupt Disable Register */
-#define SYSC_PIOA_IMR ( 1096 ) /* Interrupt Mask Register */
-#define SYSC_PIOA_ISR ( 1100 ) /* Interrupt Status Register */
-#define SYSC_PIOA_MDER ( 1104 ) /* Multi-driver Enable Register */
-#define SYSC_PIOA_MDDR ( 1108 ) /* Multi-driver Disable Register */
-#define SYSC_PIOA_MDSR ( 1112 ) /* Multi-driver Status Register */
-#define SYSC_PIOA_PPUDR ( 1120 ) /* Pull-up Disable Register */
-#define SYSC_PIOA_PPUER ( 1124 ) /* Pull-up Enable Register */
-#define SYSC_PIOA_PPUSR ( 1128 ) /* Pad Pull-up Status Register */
-#define SYSC_PIOA_ASR ( 1136 ) /* Select A Register */
-#define SYSC_PIOA_BSR ( 1140 ) /* Select B Register */
-#define SYSC_PIOA_ABSR ( 1144 ) /* AB Select Status Register */
-#define SYSC_PIOA_OWER ( 1184 ) /* Output Write Enable Register */
-#define SYSC_PIOA_OWDR ( 1188 ) /* Output Write Disable Register */
-#define SYSC_PIOA_OWSR ( 1192 ) /* Output Write Status Register */
-#define SYSC_PMC_SCER ( 3072 ) /* System Clock Enable Register */
-#define SYSC_PMC_SCDR ( 3076 ) /* System Clock Disable Register */
-#define SYSC_PMC_SCSR ( 3080 ) /* System Clock Status Register */
-#define SYSC_PMC_PCER ( 3088 ) /* Peripheral Clock Enable Register */
-#define SYSC_PMC_PCDR ( 3092 ) /* Peripheral Clock Disable Register */
-#define SYSC_PMC_PCSR ( 3096 ) /* Peripheral Clock Status Register */
-#define SYSC_PMC_MOR ( 3104 ) /* Main Oscillator Register */
-#define SYSC_PMC_MCFR ( 3108 ) /* Main Clock Frequency Register */
-#define SYSC_PMC_PLLR ( 3116 ) /* PLL Register */
-#define SYSC_PMC_MCKR ( 3120 ) /* Master Clock Register */
-#define SYSC_PMC_PCKR ( 3136 ) /* Programmable Clock Register */
-#define SYSC_PMC_IER ( 3168 ) /* Interrupt Enable Register */
-#define SYSC_PMC_IDR ( 3172 ) /* Interrupt Disable Register */
-#define SYSC_PMC_SR ( 3176 ) /* Status Register */
-#define SYSC_PMC_IMR ( 3180 ) /* Interrupt Mask Register */
-#define SYSC_RSTC_RCR ( 3328 ) /* Reset Control Register */
-#define SYSC_RSTC_RSR ( 3332 ) /* Reset Status Register */
-#define SYSC_RSTC_RMR ( 3336 ) /* Reset Mode Register */
-#define SYSC_RTTC_RTMR ( 3360 ) /* Real-time Mode Register */
-#define SYSC_RTTC_RTAR ( 3364 ) /* Real-time Alarm Register */
-#define SYSC_RTTC_RTVR ( 3368 ) /* Real-time Value Register */
-#define SYSC_RTTC_RTSR ( 3372 ) /* Real-time Status Register */
-#define SYSC_PITC_PIMR ( 3376 ) /* Period Interval Mode Register */
-#define SYSC_PITC_PISR ( 3380 ) /* Period Interval Status Register */
-#define SYSC_PITC_PIVR ( 3384 ) /* Period Interval Value Register */
-#define SYSC_PITC_PIIR ( 3388 ) /* Period Interval Image Register */
-#define SYSC_WDTC_WDCR ( 3392 ) /* Watchdog Control Register */
-#define SYSC_WDTC_WDMR ( 3396 ) /* Watchdog Mode Register */
-#define SYSC_WDTC_WDSR ( 3400 ) /* Watchdog Status Register */
-#define SYSC_SYSC_VRPM ( 3424 ) /* Voltage Regulator Power Mode Register */
-/* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- */
-#define AT91C_SYSC_PSTDBY ( 0x1 << 0 ) /* (SYSC) Voltage Regulator Power Mode */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+// *** Register offset in AT91S_SYSC structure ***
+#define SYSC_AIC_SMR ( 0) // Source Mode Register
+#define SYSC_AIC_SVR (128) // Source Vector Register
+#define SYSC_AIC_IVR (256) // IRQ Vector Register
+#define SYSC_AIC_FVR (260) // FIQ Vector Register
+#define SYSC_AIC_ISR (264) // Interrupt Status Register
+#define SYSC_AIC_IPR (268) // Interrupt Pending Register
+#define SYSC_AIC_IMR (272) // Interrupt Mask Register
+#define SYSC_AIC_CISR (276) // Core Interrupt Status Register
+#define SYSC_AIC_IECR (288) // Interrupt Enable Command Register
+#define SYSC_AIC_IDCR (292) // Interrupt Disable Command Register
+#define SYSC_AIC_ICCR (296) // Interrupt Clear Command Register
+#define SYSC_AIC_ISCR (300) // Interrupt Set Command Register
+#define SYSC_AIC_EOICR (304) // End of Interrupt Command Register
+#define SYSC_AIC_SPU (308) // Spurious Vector Register
+#define SYSC_AIC_DCR (312) // Debug Control Register (Protect)
+#define SYSC_AIC_FFER (320) // Fast Forcing Enable Register
+#define SYSC_AIC_FFDR (324) // Fast Forcing Disable Register
+#define SYSC_AIC_FFSR (328) // Fast Forcing Status Register
+#define SYSC_DBGU_CR (512) // Control Register
+#define SYSC_DBGU_MR (516) // Mode Register
+#define SYSC_DBGU_IER (520) // Interrupt Enable Register
+#define SYSC_DBGU_IDR (524) // Interrupt Disable Register
+#define SYSC_DBGU_IMR (528) // Interrupt Mask Register
+#define SYSC_DBGU_CSR (532) // Channel Status Register
+#define SYSC_DBGU_RHR (536) // Receiver Holding Register
+#define SYSC_DBGU_THR (540) // Transmitter Holding Register
+#define SYSC_DBGU_BRGR (544) // Baud Rate Generator Register
+#define SYSC_DBGU_C1R (576) // Chip ID1 Register
+#define SYSC_DBGU_C2R (580) // Chip ID2 Register
+#define SYSC_DBGU_FNTR (584) // Force NTRST Register
+#define SYSC_DBGU_RPR (768) // Receive Pointer Register
+#define SYSC_DBGU_RCR (772) // Receive Counter Register
+#define SYSC_DBGU_TPR (776) // Transmit Pointer Register
+#define SYSC_DBGU_TCR (780) // Transmit Counter Register
+#define SYSC_DBGU_RNPR (784) // Receive Next Pointer Register
+#define SYSC_DBGU_RNCR (788) // Receive Next Counter Register
+#define SYSC_DBGU_TNPR (792) // Transmit Next Pointer Register
+#define SYSC_DBGU_TNCR (796) // Transmit Next Counter Register
+#define SYSC_DBGU_PTCR (800) // PDC Transfer Control Register
+#define SYSC_DBGU_PTSR (804) // PDC Transfer Status Register
+#define SYSC_PIOA_PER (1024) // PIO Enable Register
+#define SYSC_PIOA_PDR (1028) // PIO Disable Register
+#define SYSC_PIOA_PSR (1032) // PIO Status Register
+#define SYSC_PIOA_OER (1040) // Output Enable Register
+#define SYSC_PIOA_ODR (1044) // Output Disable Registerr
+#define SYSC_PIOA_OSR (1048) // Output Status Register
+#define SYSC_PIOA_IFER (1056) // Input Filter Enable Register
+#define SYSC_PIOA_IFDR (1060) // Input Filter Disable Register
+#define SYSC_PIOA_IFSR (1064) // Input Filter Status Register
+#define SYSC_PIOA_SODR (1072) // Set Output Data Register
+#define SYSC_PIOA_CODR (1076) // Clear Output Data Register
+#define SYSC_PIOA_ODSR (1080) // Output Data Status Register
+#define SYSC_PIOA_PDSR (1084) // Pin Data Status Register
+#define SYSC_PIOA_IER (1088) // Interrupt Enable Register
+#define SYSC_PIOA_IDR (1092) // Interrupt Disable Register
+#define SYSC_PIOA_IMR (1096) // Interrupt Mask Register
+#define SYSC_PIOA_ISR (1100) // Interrupt Status Register
+#define SYSC_PIOA_MDER (1104) // Multi-driver Enable Register
+#define SYSC_PIOA_MDDR (1108) // Multi-driver Disable Register
+#define SYSC_PIOA_MDSR (1112) // Multi-driver Status Register
+#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register
+#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register
+#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register
+#define SYSC_PIOA_ASR (1136) // Select A Register
+#define SYSC_PIOA_BSR (1140) // Select B Register
+#define SYSC_PIOA_ABSR (1144) // AB Select Status Register
+#define SYSC_PIOA_OWER (1184) // Output Write Enable Register
+#define SYSC_PIOA_OWDR (1188) // Output Write Disable Register
+#define SYSC_PIOA_OWSR (1192) // Output Write Status Register
+#define SYSC_PMC_SCER (3072) // System Clock Enable Register
+#define SYSC_PMC_SCDR (3076) // System Clock Disable Register
+#define SYSC_PMC_SCSR (3080) // System Clock Status Register
+#define SYSC_PMC_PCER (3088) // Peripheral Clock Enable Register
+#define SYSC_PMC_PCDR (3092) // Peripheral Clock Disable Register
+#define SYSC_PMC_PCSR (3096) // Peripheral Clock Status Register
+#define SYSC_PMC_MOR (3104) // Main Oscillator Register
+#define SYSC_PMC_MCFR (3108) // Main Clock Frequency Register
+#define SYSC_PMC_PLLR (3116) // PLL Register
+#define SYSC_PMC_MCKR (3120) // Master Clock Register
+#define SYSC_PMC_PCKR (3136) // Programmable Clock Register
+#define SYSC_PMC_IER (3168) // Interrupt Enable Register
+#define SYSC_PMC_IDR (3172) // Interrupt Disable Register
+#define SYSC_PMC_SR (3176) // Status Register
+#define SYSC_PMC_IMR (3180) // Interrupt Mask Register
+#define SYSC_RSTC_RCR (3328) // Reset Control Register
+#define SYSC_RSTC_RSR (3332) // Reset Status Register
+#define SYSC_RSTC_RMR (3336) // Reset Mode Register
+#define SYSC_RTTC_RTMR (3360) // Real-time Mode Register
+#define SYSC_RTTC_RTAR (3364) // Real-time Alarm Register
+#define SYSC_RTTC_RTVR (3368) // Real-time Value Register
+#define SYSC_RTTC_RTSR (3372) // Real-time Status Register
+#define SYSC_PITC_PIMR (3376) // Period Interval Mode Register
+#define SYSC_PITC_PISR (3380) // Period Interval Status Register
+#define SYSC_PITC_PIVR (3384) // Period Interval Value Register
+#define SYSC_PITC_PIIR (3388) // Period Interval Image Register
+#define SYSC_WDTC_WDCR (3392) // Watchdog Control Register
+#define SYSC_WDTC_WDMR (3396) // Watchdog Mode Register
+#define SYSC_WDTC_WDSR (3400) // Watchdog Status Register
+#define SYSC_SYSC_VRPM (3424) // Voltage Regulator Power Mode Register
+// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register --------
+#define AT91C_SYSC_PSTDBY (0x1 << 0) // (SYSC) Voltage Regulator Power Mode
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_AIC structure *** */
-#define AIC_SMR ( 0 ) /* Source Mode Register */
-#define AIC_SVR ( 128 ) /* Source Vector Register */
-#define AIC_IVR ( 256 ) /* IRQ Vector Register */
-#define AIC_FVR ( 260 ) /* FIQ Vector Register */
-#define AIC_ISR ( 264 ) /* Interrupt Status Register */
-#define AIC_IPR ( 268 ) /* Interrupt Pending Register */
-#define AIC_IMR ( 272 ) /* Interrupt Mask Register */
-#define AIC_CISR ( 276 ) /* Core Interrupt Status Register */
-#define AIC_IECR ( 288 ) /* Interrupt Enable Command Register */
-#define AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */
-#define AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */
-#define AIC_ISCR ( 300 ) /* Interrupt Set Command Register */
-#define AIC_EOICR ( 304 ) /* End of Interrupt Command Register */
-#define AIC_SPU ( 308 ) /* Spurious Vector Register */
-#define AIC_DCR ( 312 ) /* Debug Control Register (Protect) */
-#define AIC_FFER ( 320 ) /* Fast Forcing Enable Register */
-#define AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */
-#define AIC_FFSR ( 328 ) /* Fast Forcing Status Register */
-/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
-#define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */
-#define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */
-#define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */
-#define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */
-#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label Level Sensitive */
-#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Edge triggered */
-#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) External Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) External Sources Code Label Positive Edge triggered */
-/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
-#define AT91C_AIC_NFIQ ( 0x1 << 0 ) /* (AIC) NFIQ Status */
-#define AT91C_AIC_NIRQ ( 0x1 << 1 ) /* (AIC) NIRQ Status */
-/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
-#define AT91C_AIC_DCR_PROT ( 0x1 << 0 ) /* (AIC) Protection Mode */
-#define AT91C_AIC_DCR_GMSK ( 0x1 << 1 ) /* (AIC) General Mask */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+// *** Register offset in AT91S_AIC structure ***
+#define AIC_SMR ( 0) // Source Mode Register
+#define AIC_SVR (128) // Source Vector Register
+#define AIC_IVR (256) // IRQ Vector Register
+#define AIC_FVR (260) // FIQ Vector Register
+#define AIC_ISR (264) // Interrupt Status Register
+#define AIC_IPR (268) // Interrupt Pending Register
+#define AIC_IMR (272) // Interrupt Mask Register
+#define AIC_CISR (276) // Core Interrupt Status Register
+#define AIC_IECR (288) // Interrupt Enable Command Register
+#define AIC_IDCR (292) // Interrupt Disable Command Register
+#define AIC_ICCR (296) // Interrupt Clear Command Register
+#define AIC_ISCR (300) // Interrupt Set Command Register
+#define AIC_EOICR (304) // End of Interrupt Command Register
+#define AIC_SPU (308) // Spurious Vector Register
+#define AIC_DCR (312) // Debug Control Register (Protect)
+#define AIC_FFER (320) // Fast Forcing Enable Register
+#define AIC_FFDR (324) // Fast Forcing Disable Register
+#define AIC_FFSR (328) // Fast Forcing Status Register
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_DBGU structure *** */
-#define DBGU_CR ( 0 ) /* Control Register */
-#define DBGU_MR ( 4 ) /* Mode Register */
-#define DBGU_IER ( 8 ) /* Interrupt Enable Register */
-#define DBGU_IDR ( 12 ) /* Interrupt Disable Register */
-#define DBGU_IMR ( 16 ) /* Interrupt Mask Register */
-#define DBGU_CSR ( 20 ) /* Channel Status Register */
-#define DBGU_RHR ( 24 ) /* Receiver Holding Register */
-#define DBGU_THR ( 28 ) /* Transmitter Holding Register */
-#define DBGU_BRGR ( 32 ) /* Baud Rate Generator Register */
-#define DBGU_C1R ( 64 ) /* Chip ID1 Register */
-#define DBGU_C2R ( 68 ) /* Chip ID2 Register */
-#define DBGU_FNTR ( 72 ) /* Force NTRST Register */
-#define DBGU_RPR ( 256 ) /* Receive Pointer Register */
-#define DBGU_RCR ( 260 ) /* Receive Counter Register */
-#define DBGU_TPR ( 264 ) /* Transmit Pointer Register */
-#define DBGU_TCR ( 268 ) /* Transmit Counter Register */
-#define DBGU_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define DBGU_RNCR ( 276 ) /* Receive Next Counter Register */
-#define DBGU_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define DBGU_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define DBGU_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define DBGU_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ( 0x1 << 2 ) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ( 0x1 << 3 ) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ( 0x1 << 4 ) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ( 0x1 << 6 ) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ( 0x1 << 7 ) /* (DBGU) Transmitter Disable */
-/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_PAR ( 0x7 << 9 ) /* (DBGU) Parity type */
-#define AT91C_US_PAR_EVEN ( 0x0 << 9 ) /* (DBGU) Even Parity */
-#define AT91C_US_PAR_ODD ( 0x1 << 9 ) /* (DBGU) Odd Parity */
-#define AT91C_US_PAR_SPACE ( 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK ( 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE ( 0x4 << 9 ) /* (DBGU) No Parity */
-#define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9 ) /* (DBGU) Multi-drop mode */
-#define AT91C_US_CHMODE ( 0x3 << 14 ) /* (DBGU) Channel Mode */
-#define AT91C_US_CHMODE_NORMAL ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
-#define AT91C_US_CHMODE_AUTO ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
-#define AT91C_US_CHMODE_LOCAL ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
-#define AT91C_US_CHMODE_REMOTE ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ( 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ( 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ( 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ( 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ( 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ( 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ( 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
-/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
-/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
-#define AT91C_US_FORCE_NTRST ( 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+// *** Register offset in AT91S_DBGU structure ***
+#define DBGU_CR ( 0) // Control Register
+#define DBGU_MR ( 4) // Mode Register
+#define DBGU_IER ( 8) // Interrupt Enable Register
+#define DBGU_IDR (12) // Interrupt Disable Register
+#define DBGU_IMR (16) // Interrupt Mask Register
+#define DBGU_CSR (20) // Channel Status Register
+#define DBGU_RHR (24) // Receiver Holding Register
+#define DBGU_THR (28) // Transmitter Holding Register
+#define DBGU_BRGR (32) // Baud Rate Generator Register
+#define DBGU_C1R (64) // Chip ID1 Register
+#define DBGU_C2R (68) // Chip ID2 Register
+#define DBGU_FNTR (72) // Force NTRST Register
+#define DBGU_RPR (256) // Receive Pointer Register
+#define DBGU_RCR (260) // Receive Counter Register
+#define DBGU_TPR (264) // Transmit Pointer Register
+#define DBGU_TCR (268) // Transmit Counter Register
+#define DBGU_RNPR (272) // Receive Next Pointer Register
+#define DBGU_RNCR (276) // Receive Next Counter Register
+#define DBGU_TNPR (280) // Transmit Next Pointer Register
+#define DBGU_TNCR (284) // Transmit Next Counter Register
+#define DBGU_PTCR (288) // PDC Transfer Control Register
+#define DBGU_PTSR (292) // PDC Transfer Status Register
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PDC structure *** */
-#define PDC_RPR ( 0 ) /* Receive Pointer Register */
-#define PDC_RCR ( 4 ) /* Receive Counter Register */
-#define PDC_TPR ( 8 ) /* Transmit Pointer Register */
-#define PDC_TCR ( 12 ) /* Transmit Counter Register */
-#define PDC_RNPR ( 16 ) /* Receive Next Pointer Register */
-#define PDC_RNCR ( 20 ) /* Receive Next Counter Register */
-#define PDC_TNPR ( 24 ) /* Transmit Next Pointer Register */
-#define PDC_TNCR ( 28 ) /* Transmit Next Counter Register */
-#define PDC_PTCR ( 32 ) /* PDC Transfer Control Register */
-#define PDC_PTSR ( 36 ) /* PDC Transfer Status Register */
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral Data Controller
+// *****************************************************************************
+// *** Register offset in AT91S_PDC structure ***
+#define PDC_RPR ( 0) // Receive Pointer Register
+#define PDC_RCR ( 4) // Receive Counter Register
+#define PDC_TPR ( 8) // Transmit Pointer Register
+#define PDC_TCR (12) // Transmit Counter Register
+#define PDC_RNPR (16) // Receive Next Pointer Register
+#define PDC_RNCR (20) // Receive Next Counter Register
+#define PDC_TNPR (24) // Transmit Next Pointer Register
+#define PDC_TNCR (28) // Transmit Next Counter Register
+#define PDC_PTCR (32) // PDC Transfer Control Register
+#define PDC_PTSR (36) // PDC Transfer Status Register
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PIO structure *** */
-#define PIO_PER ( 0 ) /* PIO Enable Register */
-#define PIO_PDR ( 4 ) /* PIO Disable Register */
-#define PIO_PSR ( 8 ) /* PIO Status Register */
-#define PIO_OER ( 16 ) /* Output Enable Register */
-#define PIO_ODR ( 20 ) /* Output Disable Registerr */
-#define PIO_OSR ( 24 ) /* Output Status Register */
-#define PIO_IFER ( 32 ) /* Input Filter Enable Register */
-#define PIO_IFDR ( 36 ) /* Input Filter Disable Register */
-#define PIO_IFSR ( 40 ) /* Input Filter Status Register */
-#define PIO_SODR ( 48 ) /* Set Output Data Register */
-#define PIO_CODR ( 52 ) /* Clear Output Data Register */
-#define PIO_ODSR ( 56 ) /* Output Data Status Register */
-#define PIO_PDSR ( 60 ) /* Pin Data Status Register */
-#define PIO_IER ( 64 ) /* Interrupt Enable Register */
-#define PIO_IDR ( 68 ) /* Interrupt Disable Register */
-#define PIO_IMR ( 72 ) /* Interrupt Mask Register */
-#define PIO_ISR ( 76 ) /* Interrupt Status Register */
-#define PIO_MDER ( 80 ) /* Multi-driver Enable Register */
-#define PIO_MDDR ( 84 ) /* Multi-driver Disable Register */
-#define PIO_MDSR ( 88 ) /* Multi-driver Status Register */
-#define PIO_PPUDR ( 96 ) /* Pull-up Disable Register */
-#define PIO_PPUER ( 100 ) /* Pull-up Enable Register */
-#define PIO_PPUSR ( 104 ) /* Pad Pull-up Status Register */
-#define PIO_ASR ( 112 ) /* Select A Register */
-#define PIO_BSR ( 116 ) /* Select B Register */
-#define PIO_ABSR ( 120 ) /* AB Select Status Register */
-#define PIO_OWER ( 160 ) /* Output Write Enable Register */
-#define PIO_OWDR ( 164 ) /* Output Write Disable Register */
-#define PIO_OWSR ( 168 ) /* Output Write Status Register */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PIO structure ***
+#define PIO_PER ( 0) // PIO Enable Register
+#define PIO_PDR ( 4) // PIO Disable Register
+#define PIO_PSR ( 8) // PIO Status Register
+#define PIO_OER (16) // Output Enable Register
+#define PIO_ODR (20) // Output Disable Registerr
+#define PIO_OSR (24) // Output Status Register
+#define PIO_IFER (32) // Input Filter Enable Register
+#define PIO_IFDR (36) // Input Filter Disable Register
+#define PIO_IFSR (40) // Input Filter Status Register
+#define PIO_SODR (48) // Set Output Data Register
+#define PIO_CODR (52) // Clear Output Data Register
+#define PIO_ODSR (56) // Output Data Status Register
+#define PIO_PDSR (60) // Pin Data Status Register
+#define PIO_IER (64) // Interrupt Enable Register
+#define PIO_IDR (68) // Interrupt Disable Register
+#define PIO_IMR (72) // Interrupt Mask Register
+#define PIO_ISR (76) // Interrupt Status Register
+#define PIO_MDER (80) // Multi-driver Enable Register
+#define PIO_MDDR (84) // Multi-driver Disable Register
+#define PIO_MDSR (88) // Multi-driver Status Register
+#define PIO_PPUDR (96) // Pull-up Disable Register
+#define PIO_PPUER (100) // Pull-up Enable Register
+#define PIO_PPUSR (104) // Pad Pull-up Status Register
+#define PIO_ASR (112) // Select A Register
+#define PIO_BSR (116) // Select B Register
+#define PIO_ABSR (120) // AB Select Status Register
+#define PIO_OWER (160) // Output Write Enable Register
+#define PIO_OWDR (164) // Output Write Disable Register
+#define PIO_OWSR (168) // Output Write Status Register
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_CKGR structure *** */
-#define CKGR_MOR ( 0 ) /* Main Oscillator Register */
-#define CKGR_MCFR ( 4 ) /* Main Clock Frequency Register */
-#define CKGR_PLLR ( 12 ) /* PLL Register */
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN ( 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCBYPASS ( 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */
-#define AT91C_CKGR_OSCOUNT ( 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY ( 0x1 << 16 ) /* (CKGR) Main Clock Ready */
-/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIV ( 0xFF << 0 ) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIV_0 ( 0x0 ) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIV_BYPASS ( 0x1 ) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLCOUNT ( 0x3F << 8 ) /* (CKGR) PLL Counter */
-#define AT91C_CKGR_OUT ( 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */
-#define AT91C_CKGR_OUT_0 ( 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_1 ( 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_2 ( 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_3 ( 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_MUL ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
-#define AT91C_CKGR_USBDIV ( 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */
-#define AT91C_CKGR_USBDIV_0 ( 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */
-#define AT91C_CKGR_USBDIV_1 ( 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */
-#define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+// *** Register offset in AT91S_CKGR structure ***
+#define CKGR_MOR ( 0) // Main Oscillator Register
+#define CKGR_MCFR ( 4) // Main Clock Frequency Register
+#define CKGR_PLLR (12) // PLL Register
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PMC structure *** */
-#define PMC_SCER ( 0 ) /* System Clock Enable Register */
-#define PMC_SCDR ( 4 ) /* System Clock Disable Register */
-#define PMC_SCSR ( 8 ) /* System Clock Status Register */
-#define PMC_PCER ( 16 ) /* Peripheral Clock Enable Register */
-#define PMC_PCDR ( 20 ) /* Peripheral Clock Disable Register */
-#define PMC_PCSR ( 24 ) /* Peripheral Clock Status Register */
-#define PMC_MOR ( 32 ) /* Main Oscillator Register */
-#define PMC_MCFR ( 36 ) /* Main Clock Frequency Register */
-#define PMC_PLLR ( 44 ) /* PLL Register */
-#define PMC_MCKR ( 48 ) /* Master Clock Register */
-#define PMC_PCKR ( 64 ) /* Programmable Clock Register */
-#define PMC_IER ( 96 ) /* Interrupt Enable Register */
-#define PMC_IDR ( 100 ) /* Interrupt Disable Register */
-#define PMC_SR ( 104 ) /* Status Register */
-#define PMC_IMR ( 108 ) /* Interrupt Mask Register */
-/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
-#define AT91C_PMC_PCK ( 0x1 << 0 ) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP ( 0x1 << 7 ) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_PCK0 ( 0x1 << 8 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1 ( 0x1 << 9 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2 ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3 ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */
-/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
-/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
-/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
-/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
-/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
-/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
-#define AT91C_PMC_CSS ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ( 0x0 ) /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ( 0x1 ) /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLL_CLK ( 0x3 ) /* (PMC) Clock from PLL is selected */
-#define AT91C_PMC_PRES ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK ( 0x0 << 2 ) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2 ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4 ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8 ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16 ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32 ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64 ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
-/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
-/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
-#define AT91C_PMC_MOSCS ( 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCK ( 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY ( 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY ( 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY ( 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
-/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
-/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PMC structure ***
+#define PMC_SCER ( 0) // System Clock Enable Register
+#define PMC_SCDR ( 4) // System Clock Disable Register
+#define PMC_SCSR ( 8) // System Clock Status Register
+#define PMC_PCER (16) // Peripheral Clock Enable Register
+#define PMC_PCDR (20) // Peripheral Clock Disable Register
+#define PMC_PCSR (24) // Peripheral Clock Status Register
+#define PMC_MOR (32) // Main Oscillator Register
+#define PMC_MCFR (36) // Main Clock Frequency Register
+#define PMC_PLLR (44) // PLL Register
+#define PMC_MCKR (48) // Master Clock Register
+#define PMC_PCKR (64) // Programmable Clock Register
+#define PMC_IER (96) // Interrupt Enable Register
+#define PMC_IDR (100) // Interrupt Disable Register
+#define PMC_SR (104) // Status Register
+#define PMC_IMR (108) // Interrupt Mask Register
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Reset Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_RSTC structure *** */
-#define RSTC_RCR ( 0 ) /* Reset Control Register */
-#define RSTC_RSR ( 4 ) /* Reset Status Register */
-#define RSTC_RMR ( 8 ) /* Reset Mode Register */
-/* -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
-#define AT91C_SYSC_PROCRST ( 0x1 << 0 ) /* (RSTC) Processor Reset */
-#define AT91C_SYSC_ICERST ( 0x1 << 1 ) /* (RSTC) ICE Interface Reset */
-#define AT91C_SYSC_PERRST ( 0x1 << 2 ) /* (RSTC) Peripheral Reset */
-#define AT91C_SYSC_EXTRST ( 0x1 << 3 ) /* (RSTC) External Reset */
-#define AT91C_SYSC_KEY ( 0xFF << 24 ) /* (RSTC) Password */
-/* -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
-#define AT91C_SYSC_URSTS ( 0x1 << 0 ) /* (RSTC) User Reset Status */
-#define AT91C_SYSC_BODSTS ( 0x1 << 1 ) /* (RSTC) Brown-out Detection Status */
-#define AT91C_SYSC_RSTTYP ( 0x7 << 8 ) /* (RSTC) Reset Type */
-#define AT91C_SYSC_RSTTYP_POWERUP ( 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */
-#define AT91C_SYSC_RSTTYP_WATCHDOG ( 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occured. */
-#define AT91C_SYSC_RSTTYP_SOFTWARE ( 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */
-#define AT91C_SYSC_RSTTYP_USER ( 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */
-#define AT91C_SYSC_RSTTYP_BROWNOUT ( 0x5 << 8 ) /* (RSTC) Brown-out Reset. */
-#define AT91C_SYSC_NRSTL ( 0x1 << 16 ) /* (RSTC) NRST pin level */
-#define AT91C_SYSC_SRCMP ( 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */
-/* -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
-#define AT91C_SYSC_URSTEN ( 0x1 << 0 ) /* (RSTC) User Reset Enable */
-#define AT91C_SYSC_URSTIEN ( 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */
-#define AT91C_SYSC_ERSTL ( 0xF << 8 ) /* (RSTC) User Reset Enable */
-#define AT91C_SYSC_BODIEN ( 0x1 << 16 ) /* (RSTC) Brown-out Detection Interrupt Enable */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RSTC structure ***
+#define RSTC_RCR ( 0) // Reset Control Register
+#define RSTC_RSR ( 4) // Reset Status Register
+#define RSTC_RMR ( 8) // Reset Mode Register
+// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
+#define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset
+#define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password
+// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status
+#define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
+#define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset.
+#define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_RTTC structure *** */
-#define RTTC_RTMR ( 0 ) /* Real-time Mode Register */
-#define RTTC_RTAR ( 4 ) /* Real-time Alarm Register */
-#define RTTC_RTVR ( 8 ) /* Real-time Value Register */
-#define RTTC_RTSR ( 12 ) /* Real-time Status Register */
-/* -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
-#define AT91C_SYSC_RTPRES ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
-#define AT91C_SYSC_ALMIEN ( 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */
-#define AT91C_SYSC_RTTINCIEN ( 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */
-#define AT91C_SYSC_RTTRST ( 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */
-/* -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
-#define AT91C_SYSC_ALMV ( 0x0 << 0 ) /* (RTTC) Alarm Value */
-/* -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
-#define AT91C_SYSC_CRTV ( 0x0 << 0 ) /* (RTTC) Current Real-time Value */
-/* -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
-#define AT91C_SYSC_ALMS ( 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */
-#define AT91C_SYSC_RTTINC ( 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RTTC structure ***
+#define RTTC_RTMR ( 0) // Real-time Mode Register
+#define RTTC_RTAR ( 4) // Real-time Alarm Register
+#define RTTC_RTVR ( 8) // Real-time Value Register
+#define RTTC_RTSR (12) // Real-time Status Register
+// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value
+// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
+// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PITC structure *** */
-#define PITC_PIMR ( 0 ) /* Period Interval Mode Register */
-#define PITC_PISR ( 4 ) /* Period Interval Status Register */
-#define PITC_PIVR ( 8 ) /* Period Interval Value Register */
-#define PITC_PIIR ( 12 ) /* Period Interval Image Register */
-/* -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
-#define AT91C_SYSC_PIV ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
-#define AT91C_SYSC_PITEN ( 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */
-#define AT91C_SYSC_PITIEN ( 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */
-/* -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
-#define AT91C_SYSC_PITS ( 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */
-/* -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
-#define AT91C_SYSC_CPIV ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
-#define AT91C_SYSC_PICNT ( 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */
-/* -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PITC structure ***
+#define PITC_PIMR ( 0) // Period Interval Mode Register
+#define PITC_PISR ( 4) // Period Interval Status Register
+#define PITC_PIVR ( 8) // Period Interval Value Register
+#define PITC_PIIR (12) // Period Interval Image Register
+// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_WDTC structure *** */
-#define WDTC_WDCR ( 0 ) /* Watchdog Control Register */
-#define WDTC_WDMR ( 4 ) /* Watchdog Mode Register */
-#define WDTC_WDSR ( 8 ) /* Watchdog Status Register */
-/* -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
-#define AT91C_SYSC_WDRSTT ( 0x1 << 0 ) /* (WDTC) Watchdog Restart */
-/* -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
-#define AT91C_SYSC_WDV ( 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_SYSC_WDFIEN ( 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */
-#define AT91C_SYSC_WDRSTEN ( 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */
-#define AT91C_SYSC_WDRPROC ( 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_SYSC_WDDIS ( 0x1 << 15 ) /* (WDTC) Watchdog Disable */
-#define AT91C_SYSC_WDD ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
-#define AT91C_SYSC_WDDBGHLT ( 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */
-#define AT91C_SYSC_WDIDLEHLT ( 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */
-/* -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
-#define AT91C_SYSC_WDUNF ( 0x1 << 0 ) /* (WDTC) Watchdog Underflow */
-#define AT91C_SYSC_WDERR ( 0x1 << 1 ) /* (WDTC) Watchdog Error */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_WDTC structure ***
+#define WDTC_WDCR ( 0) // Watchdog Control Register
+#define WDTC_WDMR ( 4) // Watchdog Mode Register
+#define WDTC_WDSR ( 8) // Watchdog Status Register
+// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
+// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Memory Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_MC structure *** */
-#define MC_RCR ( 0 ) /* MC Remap Control Register */
-#define MC_ASR ( 4 ) /* MC Abort Status Register */
-#define MC_AASR ( 8 ) /* MC Abort Address Status Register */
-#define MC_FMR ( 96 ) /* MC Flash Mode Register */
-#define MC_FCR ( 100 ) /* MC Flash Command Register */
-#define MC_FSR ( 104 ) /* MC Flash Status Register */
-/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
-#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */
-/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
-#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */
-#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */
-#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */
-#define AT91C_MC_ABTSZ_WORD ( 0x2 << 8 ) /* (MC) Word */
-#define AT91C_MC_ABTTYP ( 0x3 << 10 ) /* (MC) Abort Type Status */
-#define AT91C_MC_ABTTYP_DATAR ( 0x0 << 10 ) /* (MC) Data Read */
-#define AT91C_MC_ABTTYP_DATAW ( 0x1 << 10 ) /* (MC) Data Write */
-#define AT91C_MC_ABTTYP_FETCH ( 0x2 << 10 ) /* (MC) Code Fetch */
-#define AT91C_MC_MST0 ( 0x1 << 16 ) /* (MC) Master 0 Abort Source */
-#define AT91C_MC_MST1 ( 0x1 << 17 ) /* (MC) Master 1 Abort Source */
-#define AT91C_MC_SVMST0 ( 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */
-#define AT91C_MC_SVMST1 ( 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */
-/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
-#define AT91C_MC_FRDY ( 0x1 << 0 ) /* (MC) Flash Ready */
-#define AT91C_MC_LOCKE ( 0x1 << 2 ) /* (MC) Lock Error */
-#define AT91C_MC_PROGE ( 0x1 << 3 ) /* (MC) Programming Error */
-#define AT91C_MC_NEBP ( 0x1 << 7 ) /* (MC) No Erase Before Programming */
-#define AT91C_MC_FWS ( 0x3 << 8 ) /* (MC) Flash Wait State */
-#define AT91C_MC_FWS_0FWS ( 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */
-#define AT91C_MC_FWS_1FWS ( 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */
-#define AT91C_MC_FWS_2FWS ( 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FWS_3FWS ( 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FMCN ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
-/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
-#define AT91C_MC_FCMD ( 0xF << 0 ) /* (MC) Flash Command */
-#define AT91C_MC_FCMD_START_PROG ( 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */
-#define AT91C_MC_FCMD_LOCK ( 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_PROG_AND_LOCK ( 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
-#define AT91C_MC_FCMD_UNLOCK ( 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_ERASE_ALL ( 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
-#define AT91C_MC_FCMD_SET_GP_NVM ( 0xB ) /* (MC) Set General Purpose NVM bits. */
-#define AT91C_MC_FCMD_CLR_GP_NVM ( 0xD ) /* (MC) Clear General Purpose NVM bits. */
-#define AT91C_MC_FCMD_SET_SECURITY ( 0xF ) /* (MC) Set Security Bit. */
-#define AT91C_MC_PAGEN ( 0x3FF << 8 ) /* (MC) Page Number */
-#define AT91C_MC_KEY ( 0xFF << 24 ) /* (MC) Writing Protect Key */
-/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
-#define AT91C_MC_SECURITY ( 0x1 << 4 ) /* (MC) Security Bit Status */
-#define AT91C_MC_GPNVM0 ( 0x1 << 8 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_GPNVM1 ( 0x1 << 9 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_GPNVM2 ( 0x1 << 10 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_GPNVM3 ( 0x1 << 11 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_GPNVM4 ( 0x1 << 12 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_GPNVM6 ( 0x1 << 14 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_GPNVM7 ( 0x1 << 15 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS0 ( 0x1 << 16 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_LOCKS1 ( 0x1 << 17 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_LOCKS2 ( 0x1 << 18 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_LOCKS3 ( 0x1 << 19 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_LOCKS4 ( 0x1 << 20 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_LOCKS6 ( 0x1 << 22 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_LOCKS7 ( 0x1 << 23 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS8 ( 0x1 << 24 ) /* (MC) Sector 8 Lock Status */
-#define AT91C_MC_LOCKS9 ( 0x1 << 25 ) /* (MC) Sector 9 Lock Status */
-#define AT91C_MC_LOCKS10 ( 0x1 << 26 ) /* (MC) Sector 10 Lock Status */
-#define AT91C_MC_LOCKS11 ( 0x1 << 27 ) /* (MC) Sector 11 Lock Status */
-#define AT91C_MC_LOCKS12 ( 0x1 << 28 ) /* (MC) Sector 12 Lock Status */
-#define AT91C_MC_LOCKS13 ( 0x1 << 29 ) /* (MC) Sector 13 Lock Status */
-#define AT91C_MC_LOCKS14 ( 0x1 << 30 ) /* (MC) Sector 14 Lock Status */
-#define AT91C_MC_LOCKS15 ( 0x1 << 31 ) /* (MC) Sector 15 Lock Status */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_MC structure ***
+#define MC_RCR ( 0) // MC Remap Control Register
+#define MC_ASR ( 4) // MC Abort Status Register
+#define MC_AASR ( 8) // MC Abort Address Status Register
+#define MC_FMR (96) // MC Flash Mode Register
+#define MC_FCR (100) // MC Flash Command Register
+#define MC_FSR (104) // MC Flash Status Register
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_SPI structure *** */
-#define SPI_CR ( 0 ) /* Control Register */
-#define SPI_MR ( 4 ) /* Mode Register */
-#define SPI_RDR ( 8 ) /* Receive Data Register */
-#define SPI_TDR ( 12 ) /* Transmit Data Register */
-#define SPI_SR ( 16 ) /* Status Register */
-#define SPI_IER ( 20 ) /* Interrupt Enable Register */
-#define SPI_IDR ( 24 ) /* Interrupt Disable Register */
-#define SPI_IMR ( 28 ) /* Interrupt Mask Register */
-#define SPI_CSR ( 48 ) /* Chip Select Register */
-#define SPI_RPR ( 256 ) /* Receive Pointer Register */
-#define SPI_RCR ( 260 ) /* Receive Counter Register */
-#define SPI_TPR ( 264 ) /* Transmit Pointer Register */
-#define SPI_TCR ( 268 ) /* Transmit Counter Register */
-#define SPI_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define SPI_RNCR ( 276 ) /* Receive Next Counter Register */
-#define SPI_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define SPI_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define SPI_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define SPI_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN ( 0x1 << 0 ) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS ( 0x1 << 1 ) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST ( 0x1 << 7 ) /* (SPI) SPI Software reset */
-#define AT91C_SPI_LASTXFER ( 0x1 << 24 ) /* (SPI) SPI Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR ( 0x1 << 0 ) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS ( 0x1 << 1 ) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED ( 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE ( 0x1 << 1 ) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC ( 0x1 << 2 ) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_FDIV ( 0x1 << 3 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS ( 0x1 << 4 ) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB ( 0x1 << 7 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS ( 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD ( 0xFFFF << 0 ) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD ( 0xFFFF << 0 ) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF ( 0x1 << 0 ) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE ( 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF ( 0x1 << 2 ) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES ( 0x1 << 3 ) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_ENDRX ( 0x1 << 4 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF ( 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE ( 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_NSSR ( 0x1 << 8 ) /* (SPI) NSSR Interrupt */
-#define AT91C_SPI_TXEMPTY ( 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */
-#define AT91C_SPI_SPIENS ( 0x1 << 16 ) /* (SPI) Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL ( 0x1 << 0 ) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA ( 0x1 << 1 ) /* (SPI) Clock Phase */
-#define AT91C_SPI_CSAAT ( 0x1 << 2 ) /* (SPI) Chip Select Active After Transfer */
-#define AT91C_SPI_BITS ( 0xF << 4 ) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8 ( 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9 ( 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10 ( 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11 ( 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12 ( 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13 ( 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14 ( 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15 ( 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16 ( 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR ( 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS ( 0xFF << 16 ) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBCT ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SPI structure ***
+#define SPI_CR ( 0) // Control Register
+#define SPI_MR ( 4) // Mode Register
+#define SPI_RDR ( 8) // Receive Data Register
+#define SPI_TDR (12) // Transmit Data Register
+#define SPI_SR (16) // Status Register
+#define SPI_IER (20) // Interrupt Enable Register
+#define SPI_IDR (24) // Interrupt Disable Register
+#define SPI_IMR (28) // Interrupt Mask Register
+#define SPI_CSR (48) // Chip Select Register
+#define SPI_RPR (256) // Receive Pointer Register
+#define SPI_RCR (260) // Receive Counter Register
+#define SPI_TPR (264) // Transmit Pointer Register
+#define SPI_TCR (268) // Transmit Counter Register
+#define SPI_RNPR (272) // Receive Next Pointer Register
+#define SPI_RNCR (276) // Receive Next Counter Register
+#define SPI_TNPR (280) // Transmit Next Pointer Register
+#define SPI_TNCR (284) // Transmit Next Counter Register
+#define SPI_PTCR (288) // PDC Transfer Control Register
+#define SPI_PTSR (292) // PDC Transfer Status Register
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT (0x1 << 2) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_ADC structure *** */
-#define ADC_CR ( 0 ) /* ADC Control Register */
-#define ADC_MR ( 4 ) /* ADC Mode Register */
-#define ADC_CHER ( 16 ) /* ADC Channel Enable Register */
-#define ADC_CHDR ( 20 ) /* ADC Channel Disable Register */
-#define ADC_CHSR ( 24 ) /* ADC Channel Status Register */
-#define ADC_SR ( 28 ) /* ADC Status Register */
-#define ADC_LCDR ( 32 ) /* ADC Last Converted Data Register */
-#define ADC_IER ( 36 ) /* ADC Interrupt Enable Register */
-#define ADC_IDR ( 40 ) /* ADC Interrupt Disable Register */
-#define ADC_IMR ( 44 ) /* ADC Interrupt Mask Register */
-#define ADC_CDR0 ( 48 ) /* ADC Channel Data Register 0 */
-#define ADC_CDR1 ( 52 ) /* ADC Channel Data Register 1 */
-#define ADC_CDR2 ( 56 ) /* ADC Channel Data Register 2 */
-#define ADC_CDR3 ( 60 ) /* ADC Channel Data Register 3 */
-#define ADC_CDR4 ( 64 ) /* ADC Channel Data Register 4 */
-#define ADC_CDR5 ( 68 ) /* ADC Channel Data Register 5 */
-#define ADC_CDR6 ( 72 ) /* ADC Channel Data Register 6 */
-#define ADC_CDR7 ( 76 ) /* ADC Channel Data Register 7 */
-#define ADC_RPR ( 256 ) /* Receive Pointer Register */
-#define ADC_RCR ( 260 ) /* Receive Counter Register */
-#define ADC_TPR ( 264 ) /* Transmit Pointer Register */
-#define ADC_TCR ( 268 ) /* Transmit Counter Register */
-#define ADC_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define ADC_RNCR ( 276 ) /* Receive Next Counter Register */
-#define ADC_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define ADC_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define ADC_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define ADC_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
-#define AT91C_ADC_SWRST ( 0x1 << 0 ) /* (ADC) Software Reset */
-#define AT91C_ADC_START ( 0x1 << 1 ) /* (ADC) Start Conversion */
-/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
-#define AT91C_ADC_TRGEN ( 0x1 << 0 ) /* (ADC) Trigger Enable */
-#define AT91C_ADC_TRGEN_DIS ( 0x0 ) /* (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software */
-#define AT91C_ADC_TRGEN_EN ( 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
-#define AT91C_ADC_TRGSEL ( 0x7 << 1 ) /* (ADC) Trigger Selection */
-#define AT91C_ADC_TRGSEL_TIOA0 ( 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */
-#define AT91C_ADC_TRGSEL_TIOA1 ( 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */
-#define AT91C_ADC_TRGSEL_TIOA2 ( 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */
-#define AT91C_ADC_TRGSEL_TIOA3 ( 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */
-#define AT91C_ADC_TRGSEL_TIOA4 ( 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */
-#define AT91C_ADC_TRGSEL_TIOA5 ( 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */
-#define AT91C_ADC_TRGSEL_EXT ( 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */
-#define AT91C_ADC_LOWRES ( 0x1 << 4 ) /* (ADC) Resolution. */
-#define AT91C_ADC_LOWRES_10_BIT ( 0x0 << 4 ) /* (ADC) 10-bit resolution */
-#define AT91C_ADC_LOWRES_8_BIT ( 0x1 << 4 ) /* (ADC) 8-bit resolution */
-#define AT91C_ADC_SLEEP ( 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_SLEEP_NORMAL_MODE ( 0x0 << 5 ) /* (ADC) Normal Mode */
-#define AT91C_ADC_SLEEP_MODE ( 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_PRESCAL ( 0x3F << 8 ) /* (ADC) Prescaler rate selection */
-#define AT91C_ADC_STARTUP ( 0x1F << 16 ) /* (ADC) Startup Time */
-#define AT91C_ADC_SHTIM ( 0xF << 24 ) /* (ADC) Sample & Hold Time */
-/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
-#define AT91C_ADC_CH0 ( 0x1 << 0 ) /* (ADC) Channel 0 */
-#define AT91C_ADC_CH1 ( 0x1 << 1 ) /* (ADC) Channel 1 */
-#define AT91C_ADC_CH2 ( 0x1 << 2 ) /* (ADC) Channel 2 */
-#define AT91C_ADC_CH3 ( 0x1 << 3 ) /* (ADC) Channel 3 */
-#define AT91C_ADC_CH4 ( 0x1 << 4 ) /* (ADC) Channel 4 */
-#define AT91C_ADC_CH5 ( 0x1 << 5 ) /* (ADC) Channel 5 */
-#define AT91C_ADC_CH6 ( 0x1 << 6 ) /* (ADC) Channel 6 */
-#define AT91C_ADC_CH7 ( 0x1 << 7 ) /* (ADC) Channel 7 */
-/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
-/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
-/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
-#define AT91C_ADC_EOC0 ( 0x1 << 0 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC1 ( 0x1 << 1 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC2 ( 0x1 << 2 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC3 ( 0x1 << 3 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC4 ( 0x1 << 4 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC5 ( 0x1 << 5 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC6 ( 0x1 << 6 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC7 ( 0x1 << 7 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_OVRE0 ( 0x1 << 8 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE1 ( 0x1 << 9 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE2 ( 0x1 << 10 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE3 ( 0x1 << 11 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE4 ( 0x1 << 12 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE5 ( 0x1 << 13 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE6 ( 0x1 << 14 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE7 ( 0x1 << 15 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_DRDY ( 0x1 << 16 ) /* (ADC) Data Ready */
-#define AT91C_ADC_GOVRE ( 0x1 << 17 ) /* (ADC) General Overrun */
-#define AT91C_ADC_ENDRX ( 0x1 << 18 ) /* (ADC) End of Receiver Transfer */
-#define AT91C_ADC_RXBUFF ( 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */
-/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
-#define AT91C_ADC_LDATA ( 0x3FF << 0 ) /* (ADC) Last Data Converted */
-/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
-/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
-/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
-/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
-#define AT91C_ADC_DATA ( 0x3FF << 0 ) /* (ADC) Converted Data */
-/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
-/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
-/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
-/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
-/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
-/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
-/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+// *** Register offset in AT91S_ADC structure ***
+#define ADC_CR ( 0) // ADC Control Register
+#define ADC_MR ( 4) // ADC Mode Register
+#define ADC_CHER (16) // ADC Channel Enable Register
+#define ADC_CHDR (20) // ADC Channel Disable Register
+#define ADC_CHSR (24) // ADC Channel Status Register
+#define ADC_SR (28) // ADC Status Register
+#define ADC_LCDR (32) // ADC Last Converted Data Register
+#define ADC_IER (36) // ADC Interrupt Enable Register
+#define ADC_IDR (40) // ADC Interrupt Disable Register
+#define ADC_IMR (44) // ADC Interrupt Mask Register
+#define ADC_CDR0 (48) // ADC Channel Data Register 0
+#define ADC_CDR1 (52) // ADC Channel Data Register 1
+#define ADC_CDR2 (56) // ADC Channel Data Register 2
+#define ADC_CDR3 (60) // ADC Channel Data Register 3
+#define ADC_CDR4 (64) // ADC Channel Data Register 4
+#define ADC_CDR5 (68) // ADC Channel Data Register 5
+#define ADC_CDR6 (72) // ADC Channel Data Register 6
+#define ADC_CDR7 (76) // ADC Channel Data Register 7
+#define ADC_RPR (256) // Receive Pointer Register
+#define ADC_RCR (260) // Receive Counter Register
+#define ADC_TPR (264) // Transmit Pointer Register
+#define ADC_TCR (268) // Transmit Counter Register
+#define ADC_RNPR (272) // Receive Next Pointer Register
+#define ADC_RNCR (276) // Receive Next Counter Register
+#define ADC_TNPR (280) // Transmit Next Pointer Register
+#define ADC_TNCR (284) // Transmit Next Counter Register
+#define ADC_PTCR (288) // PDC Transfer Control Register
+#define ADC_PTSR (292) // PDC Transfer Status Register
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_SSC structure *** */
-#define SSC_CR ( 0 ) /* Control Register */
-#define SSC_CMR ( 4 ) /* Clock Mode Register */
-#define SSC_RCMR ( 16 ) /* Receive Clock ModeRegister */
-#define SSC_RFMR ( 20 ) /* Receive Frame Mode Register */
-#define SSC_TCMR ( 24 ) /* Transmit Clock Mode Register */
-#define SSC_TFMR ( 28 ) /* Transmit Frame Mode Register */
-#define SSC_RHR ( 32 ) /* Receive Holding Register */
-#define SSC_THR ( 36 ) /* Transmit Holding Register */
-#define SSC_RSHR ( 48 ) /* Receive Sync Holding Register */
-#define SSC_TSHR ( 52 ) /* Transmit Sync Holding Register */
-#define SSC_RC0R ( 56 ) /* Receive Compare 0 Register */
-#define SSC_RC1R ( 60 ) /* Receive Compare 1 Register */
-#define SSC_SR ( 64 ) /* Status Register */
-#define SSC_IER ( 68 ) /* Interrupt Enable Register */
-#define SSC_IDR ( 72 ) /* Interrupt Disable Register */
-#define SSC_IMR ( 76 ) /* Interrupt Mask Register */
-#define SSC_RPR ( 256 ) /* Receive Pointer Register */
-#define SSC_RCR ( 260 ) /* Receive Counter Register */
-#define SSC_TPR ( 264 ) /* Transmit Pointer Register */
-#define SSC_TCR ( 268 ) /* Transmit Counter Register */
-#define SSC_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define SSC_RNCR ( 276 ) /* Receive Next Counter Register */
-#define SSC_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define SSC_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define SSC_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define SSC_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
-#define AT91C_SSC_RXEN ( 0x1 << 0 ) /* (SSC) Receive Enable */
-#define AT91C_SSC_RXDIS ( 0x1 << 1 ) /* (SSC) Receive Disable */
-#define AT91C_SSC_TXEN ( 0x1 << 8 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_TXDIS ( 0x1 << 9 ) /* (SSC) Transmit Disable */
-#define AT91C_SSC_SWRST ( 0x1 << 15 ) /* (SSC) Software Reset */
-/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
-#define AT91C_SSC_CKS ( 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */
-#define AT91C_SSC_CKS_DIV ( 0x0 ) /* (SSC) Divided Clock */
-#define AT91C_SSC_CKS_TK ( 0x1 ) /* (SSC) TK Clock signal */
-#define AT91C_SSC_CKS_RK ( 0x2 ) /* (SSC) RK pin */
-#define AT91C_SSC_CKO ( 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */
-#define AT91C_SSC_CKO_NONE ( 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
-#define AT91C_SSC_CKO_CONTINOUS ( 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
-#define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
-#define AT91C_SSC_CKI ( 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */
-#define AT91C_SSC_CKG ( 0x3 << 6 ) /* (SSC) Receive/Transmit Clock Gating Selection */
-#define AT91C_SSC_CKG_NONE ( 0x0 << 6 ) /* (SSC) Receive/Transmit Clock Gating: None, continuous clock */
-#define AT91C_SSC_CKG_LOW ( 0x1 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF Low */
-#define AT91C_SSC_CKG_HIGH ( 0x2 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF High */
-#define AT91C_SSC_START ( 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */
-#define AT91C_SSC_START_CONTINOUS ( 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
-#define AT91C_SSC_START_TX ( 0x1 << 8 ) /* (SSC) Transmit/Receive start */
-#define AT91C_SSC_START_LOW_RF ( 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */
-#define AT91C_SSC_START_HIGH_RF ( 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */
-#define AT91C_SSC_START_FALL_RF ( 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */
-#define AT91C_SSC_START_RISE_RF ( 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */
-#define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */
-#define AT91C_SSC_START_EDGE_RF ( 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */
-#define AT91C_SSC_START_0 ( 0x8 << 8 ) /* (SSC) Compare 0 */
-#define AT91C_SSC_STOP ( 0x1 << 12 ) /* (SSC) Receive Stop Selection */
-#define AT91C_SSC_STTOUT ( 0x1 << 15 ) /* (SSC) Receive/Transmit Start Output Selection */
-#define AT91C_SSC_STTDLY ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
-#define AT91C_SSC_PERIOD ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
-/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
-#define AT91C_SSC_DATLEN ( 0x1F << 0 ) /* (SSC) Data Length */
-#define AT91C_SSC_LOOP ( 0x1 << 5 ) /* (SSC) Loop Mode */
-#define AT91C_SSC_MSBF ( 0x1 << 7 ) /* (SSC) Most Significant Bit First */
-#define AT91C_SSC_DATNB ( 0xF << 8 ) /* (SSC) Data Number per Frame */
-#define AT91C_SSC_FSLEN ( 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */
-#define AT91C_SSC_FSOS ( 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */
-#define AT91C_SSC_FSOS_NONE ( 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
-#define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
-#define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
-#define AT91C_SSC_FSOS_LOW ( 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
-#define AT91C_SSC_FSOS_HIGH ( 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
-#define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
-#define AT91C_SSC_FSEDGE ( 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */
-/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
-/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
-#define AT91C_SSC_DATDEF ( 0x1 << 5 ) /* (SSC) Data Default Value */
-#define AT91C_SSC_FSDEN ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
-/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
-#define AT91C_SSC_TXRDY ( 0x1 << 0 ) /* (SSC) Transmit Ready */
-#define AT91C_SSC_TXEMPTY ( 0x1 << 1 ) /* (SSC) Transmit Empty */
-#define AT91C_SSC_ENDTX ( 0x1 << 2 ) /* (SSC) End Of Transmission */
-#define AT91C_SSC_TXBUFE ( 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */
-#define AT91C_SSC_RXRDY ( 0x1 << 4 ) /* (SSC) Receive Ready */
-#define AT91C_SSC_OVRUN ( 0x1 << 5 ) /* (SSC) Receive Overrun */
-#define AT91C_SSC_ENDRX ( 0x1 << 6 ) /* (SSC) End of Reception */
-#define AT91C_SSC_RXBUFF ( 0x1 << 7 ) /* (SSC) Receive Buffer Full */
-#define AT91C_SSC_CP0 ( 0x1 << 8 ) /* (SSC) Compare 0 */
-#define AT91C_SSC_CP1 ( 0x1 << 9 ) /* (SSC) Compare 1 */
-#define AT91C_SSC_TXSYN ( 0x1 << 10 ) /* (SSC) Transmit Sync */
-#define AT91C_SSC_RXSYN ( 0x1 << 11 ) /* (SSC) Receive Sync */
-#define AT91C_SSC_TXENA ( 0x1 << 16 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_RXENA ( 0x1 << 17 ) /* (SSC) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
-/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
-/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SSC structure ***
+#define SSC_CR ( 0) // Control Register
+#define SSC_CMR ( 4) // Clock Mode Register
+#define SSC_RCMR (16) // Receive Clock ModeRegister
+#define SSC_RFMR (20) // Receive Frame Mode Register
+#define SSC_TCMR (24) // Transmit Clock Mode Register
+#define SSC_TFMR (28) // Transmit Frame Mode Register
+#define SSC_RHR (32) // Receive Holding Register
+#define SSC_THR (36) // Transmit Holding Register
+#define SSC_RSHR (48) // Receive Sync Holding Register
+#define SSC_TSHR (52) // Transmit Sync Holding Register
+#define SSC_RC0R (56) // Receive Compare 0 Register
+#define SSC_RC1R (60) // Receive Compare 1 Register
+#define SSC_SR (64) // Status Register
+#define SSC_IER (68) // Interrupt Enable Register
+#define SSC_IDR (72) // Interrupt Disable Register
+#define SSC_IMR (76) // Interrupt Mask Register
+#define SSC_RPR (256) // Receive Pointer Register
+#define SSC_RCR (260) // Receive Counter Register
+#define SSC_TPR (264) // Transmit Pointer Register
+#define SSC_TCR (268) // Transmit Counter Register
+#define SSC_RNPR (272) // Receive Next Pointer Register
+#define SSC_RNCR (276) // Receive Next Counter Register
+#define SSC_TNPR (280) // Transmit Next Pointer Register
+#define SSC_TNCR (284) // Transmit Next Counter Register
+#define SSC_PTCR (288) // PDC Transfer Control Register
+#define SSC_PTSR (292) // PDC Transfer Status Register
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
+#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0
+#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Usart */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_USART structure *** */
-#define US_CR ( 0 ) /* Control Register */
-#define US_MR ( 4 ) /* Mode Register */
-#define US_IER ( 8 ) /* Interrupt Enable Register */
-#define US_IDR ( 12 ) /* Interrupt Disable Register */
-#define US_IMR ( 16 ) /* Interrupt Mask Register */
-#define US_CSR ( 20 ) /* Channel Status Register */
-#define US_RHR ( 24 ) /* Receiver Holding Register */
-#define US_THR ( 28 ) /* Transmitter Holding Register */
-#define US_BRGR ( 32 ) /* Baud Rate Generator Register */
-#define US_RTOR ( 36 ) /* Receiver Time-out Register */
-#define US_TTGR ( 40 ) /* Transmitter Time-guard Register */
-#define US_FIDI ( 64 ) /* FI_DI_Ratio Register */
-#define US_NER ( 68 ) /* Nb Errors Register */
-#define US_XXR ( 72 ) /* XON_XOFF Register */
-#define US_IF ( 76 ) /* IRDA_FILTER Register */
-#define US_RPR ( 256 ) /* Receive Pointer Register */
-#define US_RCR ( 260 ) /* Receive Counter Register */
-#define US_TPR ( 264 ) /* Transmit Pointer Register */
-#define US_TCR ( 268 ) /* Transmit Counter Register */
-#define US_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define US_RNCR ( 276 ) /* Receive Next Counter Register */
-#define US_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define US_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define US_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define US_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTSTA ( 0x1 << 8 ) /* (USART) Reset Status Bits */
-#define AT91C_US_STTBRK ( 0x1 << 9 ) /* (USART) Start Break */
-#define AT91C_US_STPBRK ( 0x1 << 10 ) /* (USART) Stop Break */
-#define AT91C_US_STTTO ( 0x1 << 11 ) /* (USART) Start Time-out */
-#define AT91C_US_SENDA ( 0x1 << 12 ) /* (USART) Send Address */
-#define AT91C_US_RSTIT ( 0x1 << 13 ) /* (USART) Reset Iterations */
-#define AT91C_US_RSTNACK ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
-#define AT91C_US_RETTO ( 0x1 << 15 ) /* (USART) Rearm Time-out */
-#define AT91C_US_DTREN ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
-#define AT91C_US_DTRDIS ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
-#define AT91C_US_RTSEN ( 0x1 << 18 ) /* (USART) Request to Send enable */
-#define AT91C_US_RTSDIS ( 0x1 << 19 ) /* (USART) Request to Send Disable */
-/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_USMODE ( 0xF << 0 ) /* (USART) Usart mode */
-#define AT91C_US_USMODE_NORMAL ( 0x0 ) /* (USART) Normal */
-#define AT91C_US_USMODE_RS485 ( 0x1 ) /* (USART) RS485 */
-#define AT91C_US_USMODE_HWHSH ( 0x2 ) /* (USART) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM ( 0x3 ) /* (USART) Modem */
-#define AT91C_US_USMODE_ISO7816_0 ( 0x4 ) /* (USART) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1 ( 0x6 ) /* (USART) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA ( 0x8 ) /* (USART) IrDA */
-#define AT91C_US_USMODE_SWHSH ( 0xC ) /* (USART) Software Handshaking */
-#define AT91C_US_CLKS ( 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CLKS_CLOCK ( 0x0 << 4 ) /* (USART) Clock */
-#define AT91C_US_CLKS_FDIV1 ( 0x1 << 4 ) /* (USART) fdiv1 */
-#define AT91C_US_CLKS_SLOW ( 0x2 << 4 ) /* (USART) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT ( 0x3 << 4 ) /* (USART) External (SCK) */
-#define AT91C_US_CHRL ( 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CHRL_5_BITS ( 0x0 << 6 ) /* (USART) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS ( 0x1 << 6 ) /* (USART) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS ( 0x2 << 6 ) /* (USART) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS ( 0x3 << 6 ) /* (USART) Character Length: 8 bits */
-#define AT91C_US_SYNC ( 0x1 << 8 ) /* (USART) Synchronous Mode Select */
-#define AT91C_US_NBSTOP ( 0x3 << 12 ) /* (USART) Number of Stop bits */
-#define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12 ) /* (USART) 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12 ) /* (USART) 2 stop bits */
-#define AT91C_US_MSBF ( 0x1 << 16 ) /* (USART) Bit Order */
-#define AT91C_US_MODE9 ( 0x1 << 17 ) /* (USART) 9-bit Character length */
-#define AT91C_US_CKLO ( 0x1 << 18 ) /* (USART) Clock Output Select */
-#define AT91C_US_OVER ( 0x1 << 19 ) /* (USART) Over Sampling Mode */
-#define AT91C_US_INACK ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
-#define AT91C_US_DSNACK ( 0x1 << 21 ) /* (USART) Disable Successive NACK */
-#define AT91C_US_MAX_ITER ( 0x1 << 24 ) /* (USART) Number of Repetitions */
-#define AT91C_US_FILTER ( 0x1 << 28 ) /* (USART) Receive Line Filter */
-/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXBRK ( 0x1 << 2 ) /* (USART) Break Received/End of Break */
-#define AT91C_US_TIMEOUT ( 0x1 << 8 ) /* (USART) Receiver Time-out */
-#define AT91C_US_ITERATION ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
-#define AT91C_US_NACK ( 0x1 << 13 ) /* (USART) Non Acknowledge */
-#define AT91C_US_RIIC ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
-#define AT91C_US_DSRIC ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
-#define AT91C_US_DCDIC ( 0x1 << 18 ) /* (USART) Data Carrier Flag */
-#define AT91C_US_CTSIC ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
-/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
-#define AT91C_US_RI ( 0x1 << 20 ) /* (USART) Image of RI Input */
-#define AT91C_US_DSR ( 0x1 << 21 ) /* (USART) Image of DSR Input */
-#define AT91C_US_DCD ( 0x1 << 22 ) /* (USART) Image of DCD Input */
-#define AT91C_US_CTS ( 0x1 << 23 ) /* (USART) Image of CTS Input */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+// *** Register offset in AT91S_USART structure ***
+#define US_CR ( 0) // Control Register
+#define US_MR ( 4) // Mode Register
+#define US_IER ( 8) // Interrupt Enable Register
+#define US_IDR (12) // Interrupt Disable Register
+#define US_IMR (16) // Interrupt Mask Register
+#define US_CSR (20) // Channel Status Register
+#define US_RHR (24) // Receiver Holding Register
+#define US_THR (28) // Transmitter Holding Register
+#define US_BRGR (32) // Baud Rate Generator Register
+#define US_RTOR (36) // Receiver Time-out Register
+#define US_TTGR (40) // Transmitter Time-guard Register
+#define US_FIDI (64) // FI_DI_Ratio Register
+#define US_NER (68) // Nb Errors Register
+#define US_XXR (72) // XON_XOFF Register
+#define US_IF (76) // IRDA_FILTER Register
+#define US_RPR (256) // Receive Pointer Register
+#define US_RCR (260) // Receive Counter Register
+#define US_TPR (264) // Transmit Pointer Register
+#define US_TCR (268) // Transmit Counter Register
+#define US_RNPR (272) // Receive Next Pointer Register
+#define US_RNCR (276) // Receive Next Counter Register
+#define US_TNPR (280) // Transmit Next Pointer Register
+#define US_TNCR (284) // Transmit Next Counter Register
+#define US_PTCR (288) // PDC Transfer Control Register
+#define US_PTSR (292) // PDC Transfer Status Register
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TWI structure *** */
-#define TWI_CR ( 0 ) /* Control Register */
-#define TWI_MMR ( 4 ) /* Master Mode Register */
-#define TWI_SMR ( 8 ) /* Slave Mode Register */
-#define TWI_IADR ( 12 ) /* Internal Address Register */
-#define TWI_CWGR ( 16 ) /* Clock Waveform Generator Register */
-#define TWI_SR ( 32 ) /* Status Register */
-#define TWI_IER ( 36 ) /* Interrupt Enable Register */
-#define TWI_IDR ( 40 ) /* Interrupt Disable Register */
-#define TWI_IMR ( 44 ) /* Interrupt Mask Register */
-#define TWI_RHR ( 48 ) /* Receive Holding Register */
-#define TWI_THR ( 52 ) /* Transmit Holding Register */
-/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
-#define AT91C_TWI_START ( 0x1 << 0 ) /* (TWI) Send a START Condition */
-#define AT91C_TWI_STOP ( 0x1 << 1 ) /* (TWI) Send a STOP Condition */
-#define AT91C_TWI_MSEN ( 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */
-#define AT91C_TWI_MSDIS ( 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */
-#define AT91C_TWI_SVEN ( 0x1 << 4 ) /* (TWI) TWI Slave Transfer Enabled */
-#define AT91C_TWI_SVDIS ( 0x1 << 5 ) /* (TWI) TWI Slave Transfer Disabled */
-#define AT91C_TWI_SWRST ( 0x1 << 7 ) /* (TWI) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
-#define AT91C_TWI_IADRSZ ( 0x3 << 8 ) /* (TWI) Internal Device Address Size */
-#define AT91C_TWI_IADRSZ_NO ( 0x0 << 8 ) /* (TWI) No internal device address */
-#define AT91C_TWI_IADRSZ_1_BYTE ( 0x1 << 8 ) /* (TWI) One-byte internal device address */
-#define AT91C_TWI_IADRSZ_2_BYTE ( 0x2 << 8 ) /* (TWI) Two-byte internal device address */
-#define AT91C_TWI_IADRSZ_3_BYTE ( 0x3 << 8 ) /* (TWI) Three-byte internal device address */
-#define AT91C_TWI_MREAD ( 0x1 << 12 ) /* (TWI) Master Read Direction */
-#define AT91C_TWI_DADR ( 0x7F << 16 ) /* (TWI) Device Address */
-/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */
-#define AT91C_TWI_SADR ( 0x7F << 16 ) /* (TWI) Slave Device Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
-#define AT91C_TWI_CLDIV ( 0xFF << 0 ) /* (TWI) Clock Low Divider */
-#define AT91C_TWI_CHDIV ( 0xFF << 8 ) /* (TWI) Clock High Divider */
-#define AT91C_TWI_CKDIV ( 0x7 << 16 ) /* (TWI) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
-#define AT91C_TWI_TXCOMP ( 0x1 << 0 ) /* (TWI) Transmission Completed */
-#define AT91C_TWI_RXRDY ( 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */
-#define AT91C_TWI_TXRDY ( 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */
-#define AT91C_TWI_SVREAD ( 0x1 << 3 ) /* (TWI) Slave Read */
-#define AT91C_TWI_SVACC ( 0x1 << 4 ) /* (TWI) Slave Access */
-#define AT91C_TWI_GCACC ( 0x1 << 5 ) /* (TWI) General Call Access */
-#define AT91C_TWI_OVRE ( 0x1 << 6 ) /* (TWI) Overrun Error */
-#define AT91C_TWI_UNRE ( 0x1 << 7 ) /* (TWI) Underrun Error */
-#define AT91C_TWI_NACK ( 0x1 << 8 ) /* (TWI) Not Acknowledged */
-#define AT91C_TWI_ARBLST ( 0x1 << 9 ) /* (TWI) Arbitration Lost */
-/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
-/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TWI structure ***
+#define TWI_CR ( 0) // Control Register
+#define TWI_MMR ( 4) // Master Mode Register
+#define TWI_SMR ( 8) // Slave Mode Register
+#define TWI_IADR (12) // Internal Address Register
+#define TWI_CWGR (16) // Clock Waveform Generator Register
+#define TWI_SR (32) // Status Register
+#define TWI_IER (36) // Interrupt Enable Register
+#define TWI_IDR (40) // Interrupt Disable Register
+#define TWI_IMR (44) // Interrupt Mask Register
+#define TWI_RHR (48) // Receive Holding Register
+#define TWI_THR (52) // Transmit Holding Register
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled
+#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
+#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read
+#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access
+#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TC structure *** */
-#define TC_CCR ( 0 ) /* Channel Control Register */
-#define TC_CMR ( 4 ) /* Channel Mode Register (Capture Mode / Waveform Mode) */
-#define TC_CV ( 16 ) /* Counter Value */
-#define TC_RA ( 20 ) /* Register A */
-#define TC_RB ( 24 ) /* Register B */
-#define TC_RC ( 28 ) /* Register C */
-#define TC_SR ( 32 ) /* Status Register */
-#define TC_IER ( 36 ) /* Interrupt Enable Register */
-#define TC_IDR ( 40 ) /* Interrupt Disable Register */
-#define TC_IMR ( 44 ) /* Interrupt Mask Register */
-/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
-#define AT91C_TC_CLKEN ( 0x1 << 0 ) /* (TC) Counter Clock Enable Command */
-#define AT91C_TC_CLKDIS ( 0x1 << 1 ) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ( 0x1 << 2 ) /* (TC) Software Trigger Command */
-/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
-#define AT91C_TC_CLKS ( 0x7 << 0 ) /* (TC) Clock Selection */
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */
-#define AT91C_TC_CLKS_XC0 ( 0x5 ) /* (TC) Clock selected: XC0 */
-#define AT91C_TC_CLKS_XC1 ( 0x6 ) /* (TC) Clock selected: XC1 */
-#define AT91C_TC_CLKS_XC2 ( 0x7 ) /* (TC) Clock selected: XC2 */
-#define AT91C_TC_CLKI ( 0x1 << 3 ) /* (TC) Clock Invert */
-#define AT91C_TC_BURST ( 0x3 << 4 ) /* (TC) Burst Signal Selection */
-#define AT91C_TC_BURST_NONE ( 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */
-#define AT91C_TC_BURST_XC0 ( 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC1 ( 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC2 ( 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */
-#define AT91C_TC_CPCSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */
-#define AT91C_TC_LDBSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */
-#define AT91C_TC_LDBDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */
-#define AT91C_TC_CPCDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */
-#define AT91C_TC_ETRGEDG ( 0x3 << 8 ) /* (TC) External Trigger Edge Selection */
-#define AT91C_TC_ETRGEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_ETRGEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_ETRGEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_ETRGEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVTEDG ( 0x3 << 8 ) /* (TC) External Event Edge Selection */
-#define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_ABETRG ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
-#define AT91C_TC_EEVT ( 0x3 << 10 ) /* (TC) External Event Selection */
-#define AT91C_TC_EEVT_NONE ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
-#define AT91C_TC_EEVT_RISING ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
-#define AT91C_TC_EEVT_FALLING ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
-#define AT91C_TC_EEVT_BOTH ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
-#define AT91C_TC_ENETRG ( 0x1 << 12 ) /* (TC) External Event Trigger enable */
-#define AT91C_TC_WAVESEL ( 0x3 << 13 ) /* (TC) Waveform Selection */
-#define AT91C_TC_WAVESEL_UP ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UP_AUTO ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
-#define AT91C_TC_CPCTRG ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
-#define AT91C_TC_WAVE ( 0x1 << 15 ) /* (TC) */
-#define AT91C_TC_LDRA ( 0x3 << 16 ) /* (TC) RA Loading Selection */
-#define AT91C_TC_LDRA_NONE ( 0x0 << 16 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRA_RISING ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRA_FALLING ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRA_BOTH ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_ACPA ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
-#define AT91C_TC_ACPA_NONE ( 0x0 << 16 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPA_SET ( 0x1 << 16 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPA_CLEAR ( 0x2 << 16 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRB ( 0x3 << 18 ) /* (TC) RB Loading Selection */
-#define AT91C_TC_LDRB_NONE ( 0x0 << 18 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRB_RISING ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRB_FALLING ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRB_BOTH ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_ACPC ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
-#define AT91C_TC_ACPC_NONE ( 0x0 << 18 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPC_SET ( 0x1 << 18 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPC_CLEAR ( 0x2 << 18 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18 ) /* (TC) Effect: toggle */
-#define AT91C_TC_AEEVT ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
-#define AT91C_TC_AEEVT_NONE ( 0x0 << 20 ) /* (TC) Effect: none */
-#define AT91C_TC_AEEVT_SET ( 0x1 << 20 ) /* (TC) Effect: set */
-#define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20 ) /* (TC) Effect: clear */
-#define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20 ) /* (TC) Effect: toggle */
-#define AT91C_TC_ASWTRG ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
-#define AT91C_TC_ASWTRG_NONE ( 0x0 << 22 ) /* (TC) Effect: none */
-#define AT91C_TC_ASWTRG_SET ( 0x1 << 22 ) /* (TC) Effect: set */
-#define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22 ) /* (TC) Effect: clear */
-#define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPB ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
-#define AT91C_TC_BCPB_NONE ( 0x0 << 24 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPB_SET ( 0x1 << 24 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPB_CLEAR ( 0x2 << 24 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPC ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
-#define AT91C_TC_BCPC_NONE ( 0x0 << 26 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPC_SET ( 0x1 << 26 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPC_CLEAR ( 0x2 << 26 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BEEVT ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
-#define AT91C_TC_BEEVT_NONE ( 0x0 << 28 ) /* (TC) Effect: none */
-#define AT91C_TC_BEEVT_SET ( 0x1 << 28 ) /* (TC) Effect: set */
-#define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28 ) /* (TC) Effect: clear */
-#define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BSWTRG ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
-#define AT91C_TC_BSWTRG_NONE ( 0x0 << 30 ) /* (TC) Effect: none */
-#define AT91C_TC_BSWTRG_SET ( 0x1 << 30 ) /* (TC) Effect: set */
-#define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30 ) /* (TC) Effect: clear */
-#define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30 ) /* (TC) Effect: toggle */
-/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
-#define AT91C_TC_COVFS ( 0x1 << 0 ) /* (TC) Counter Overflow */
-#define AT91C_TC_LOVRS ( 0x1 << 1 ) /* (TC) Load Overrun */
-#define AT91C_TC_CPAS ( 0x1 << 2 ) /* (TC) RA Compare */
-#define AT91C_TC_CPBS ( 0x1 << 3 ) /* (TC) RB Compare */
-#define AT91C_TC_CPCS ( 0x1 << 4 ) /* (TC) RC Compare */
-#define AT91C_TC_LDRAS ( 0x1 << 5 ) /* (TC) RA Loading */
-#define AT91C_TC_LDRBS ( 0x1 << 6 ) /* (TC) RB Loading */
-#define AT91C_TC_ETRCS ( 0x1 << 7 ) /* (TC) External Trigger */
-#define AT91C_TC_ETRGS ( 0x1 << 16 ) /* (TC) Clock Enabling */
-#define AT91C_TC_MTIOA ( 0x1 << 17 ) /* (TC) TIOA Mirror */
-#define AT91C_TC_MTIOB ( 0x1 << 18 ) /* (TC) TIOA Mirror */
-/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
-/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
-/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TC structure ***
+#define TC_CCR ( 0) // Channel Control Register
+#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV (16) // Counter Value
+#define TC_RA (20) // Register A
+#define TC_RB (24) // Register B
+#define TC_RC (28) // Register C
+#define TC_SR (32) // Status Register
+#define TC_IER (36) // Interrupt Enable Register
+#define TC_IDR (40) // Interrupt Disable Register
+#define TC_IMR (44) // Interrupt Mask Register
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE (0x1 << 15) // (TC)
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TCB structure *** */
-#define TCB_TC0 ( 0 ) /* TC Channel 0 */
-#define TCB_TC1 ( 64 ) /* TC Channel 1 */
-#define TCB_TC2 ( 128 ) /* TC Channel 2 */
-#define TCB_BCR ( 192 ) /* TC Block Control Register */
-#define TCB_BMR ( 196 ) /* TC Block Mode Register */
-/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
-#define AT91C_TCB_SYNC ( 0x1 << 0 ) /* (TCB) Synchro Command */
-/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
-#define AT91C_TCB_TC0XC0S ( 0x1 << 0 ) /* (TCB) External Clock Signal 0 Selection */
-#define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0 ) /* (TCB) TCLK0 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_NONE ( 0x1 ) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2 ) /* (TCB) TIOA1 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3 ) /* (TCB) TIOA2 connected to XC0 */
-#define AT91C_TCB_TC1XC1S ( 0x1 << 2 ) /* (TCB) External Clock Signal 1 Selection */
-#define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
-#define AT91C_TCB_TC2XC2S ( 0x1 << 4 ) /* (TCB) External Clock Signal 2 Selection */
-#define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA2 ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TCB structure ***
+#define TCB_TC0 ( 0) // TC Channel 0
+#define TCB_TC1 (64) // TC Channel 1
+#define TCB_TC2 (128) // TC Channel 2
+#define TCB_BCR (192) // TC Block Control Register
+#define TCB_BMR (196) // TC Block Mode Register
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PWMC_CH structure *** */
-#define PWMC_CMR ( 0 ) /* Channel Mode Register */
-#define PWMC_CDTYR ( 4 ) /* Channel Duty Cycle Register */
-#define PWMC_CPRDR ( 8 ) /* Channel Period Register */
-#define PWMC_CCNTR ( 12 ) /* Channel Counter Register */
-#define PWMC_CUPDR ( 16 ) /* Channel Update Register */
-#define PWMC_Reserved ( 20 ) /* Reserved */
-/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
-#define AT91C_PWMC_CPRE ( 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
-#define AT91C_PWMC_CPRE_MCK ( 0x0 ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKA ( 0xB ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKB ( 0xC ) /* (PWMC_CH) */
-#define AT91C_PWMC_CALG ( 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */
-#define AT91C_PWMC_CPOL ( 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */
-#define AT91C_PWMC_CPD ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
-/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
-#define AT91C_PWMC_CDTY ( 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */
-/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
-#define AT91C_PWMC_CPRD ( 0x0 << 0 ) /* (PWMC_CH) Channel Period */
-/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
-#define AT91C_PWMC_CCNT ( 0x0 << 0 ) /* (PWMC_CH) Channel Counter */
-/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
-#define AT91C_PWMC_CUPD ( 0x0 << 0 ) /* (PWMC_CH) Channel Update */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC_CH structure ***
+#define PWMC_CMR ( 0) // Channel Mode Register
+#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register
+#define PWMC_CPRDR ( 8) // Channel Period Register
+#define PWMC_CCNTR (12) // Channel Counter Register
+#define PWMC_CUPDR (16) // Channel Update Register
+#define PWMC_Reserved (20) // Reserved
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PWMC structure *** */
-#define PWMC_MR ( 0 ) /* PWMC Mode Register */
-#define PWMC_ENA ( 4 ) /* PWMC Enable Register */
-#define PWMC_DIS ( 8 ) /* PWMC Disable Register */
-#define PWMC_SR ( 12 ) /* PWMC Status Register */
-#define PWMC_IER ( 16 ) /* PWMC Interrupt Enable Register */
-#define PWMC_IDR ( 20 ) /* PWMC Interrupt Disable Register */
-#define PWMC_IMR ( 24 ) /* PWMC Interrupt Mask Register */
-#define PWMC_ISR ( 28 ) /* PWMC Interrupt Status Register */
-#define PWMC_VR ( 252 ) /* PWMC Version Register */
-#define PWMC_CH ( 512 ) /* PWMC Channel 0 */
-/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
-#define AT91C_PWMC_DIVA ( 0xFF << 0 ) /* (PWMC) CLKA divide factor. */
-#define AT91C_PWMC_PREA ( 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */
-#define AT91C_PWMC_PREA_MCK ( 0x0 << 8 ) /* (PWMC) */
-#define AT91C_PWMC_DIVB ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
-#define AT91C_PWMC_PREB ( 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */
-#define AT91C_PWMC_PREB_MCK ( 0x0 << 24 ) /* (PWMC) */
-/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
-#define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */
-#define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */
-#define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */
-#define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */
-#define AT91C_PWMC_CHID4 ( 0x1 << 4 ) /* (PWMC) Channel ID 4 */
-#define AT91C_PWMC_CHID5 ( 0x1 << 5 ) /* (PWMC) Channel ID 5 */
-#define AT91C_PWMC_CHID6 ( 0x1 << 6 ) /* (PWMC) Channel ID 6 */
-#define AT91C_PWMC_CHID7 ( 0x1 << 7 ) /* (PWMC) Channel ID 7 */
-/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
-/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
-/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
-/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
-/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
-/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC structure ***
+#define PWMC_MR ( 0) // PWMC Mode Register
+#define PWMC_ENA ( 4) // PWMC Enable Register
+#define PWMC_DIS ( 8) // PWMC Disable Register
+#define PWMC_SR (12) // PWMC Status Register
+#define PWMC_IER (16) // PWMC Interrupt Enable Register
+#define PWMC_IDR (20) // PWMC Interrupt Disable Register
+#define PWMC_IMR (24) // PWMC Interrupt Mask Register
+#define PWMC_ISR (28) // PWMC Interrupt Status Register
+#define PWMC_VR (252) // PWMC Version Register
+#define PWMC_CH (512) // PWMC Channel 0
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
+#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4
+#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5
+#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6
+#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR USB Device Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_UDP structure *** */
-#define UDP_NUM ( 0 ) /* Frame Number Register */
-#define UDP_GLBSTATE ( 4 ) /* Global State Register */
-#define UDP_FADDR ( 8 ) /* Function Address Register */
-#define UDP_IER ( 16 ) /* Interrupt Enable Register */
-#define UDP_IDR ( 20 ) /* Interrupt Disable Register */
-#define UDP_IMR ( 24 ) /* Interrupt Mask Register */
-#define UDP_ISR ( 28 ) /* Interrupt Status Register */
-#define UDP_ICR ( 32 ) /* Interrupt Clear Register */
-#define UDP_RSTEP ( 40 ) /* Reset Endpoint Register */
-#define UDP_CSR ( 48 ) /* Endpoint Control and Status Register */
-#define UDP_FDR ( 80 ) /* Endpoint FIFO Data Register */
-/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
-#define AT91C_UDP_FRM_NUM ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
-#define AT91C_UDP_FRM_ERR ( 0x1 << 16 ) /* (UDP) Frame Error */
-#define AT91C_UDP_FRM_OK ( 0x1 << 17 ) /* (UDP) Frame OK */
-/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
-#define AT91C_UDP_FADDEN ( 0x1 << 0 ) /* (UDP) Function Address Enable */
-#define AT91C_UDP_CONFG ( 0x1 << 1 ) /* (UDP) Configured */
-#define AT91C_UDP_RMWUPE ( 0x1 << 2 ) /* (UDP) Remote Wake Up Enable */
-#define AT91C_UDP_RSMINPR ( 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */
-/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
-#define AT91C_UDP_FADD ( 0xFF << 0 ) /* (UDP) Function Address Value */
-#define AT91C_UDP_FEN ( 0x1 << 8 ) /* (UDP) Function Enable */
-/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
-#define AT91C_UDP_EPINT0 ( 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT1 ( 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT2 ( 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
-#define AT91C_UDP_EPINT3 ( 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */
-#define AT91C_UDP_EPINT4 ( 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */
-#define AT91C_UDP_EPINT5 ( 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */
-#define AT91C_UDP_EPINT6 ( 0x1 << 6 ) /* (UDP) Endpoint 6 Interrupt */
-#define AT91C_UDP_EPINT7 ( 0x1 << 7 ) /* (UDP) Endpoint 7 Interrupt */
-#define AT91C_UDP_RXSUSP ( 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */
-#define AT91C_UDP_RXRSM ( 0x1 << 9 ) /* (UDP) USB Resume Interrupt */
-#define AT91C_UDP_EXTRSM ( 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */
-#define AT91C_UDP_SOFINT ( 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */
-#define AT91C_UDP_WAKEUP ( 0x1 << 13 ) /* (UDP) USB Resume Interrupt */
-/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
-/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
-/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
-#define AT91C_UDP_ENDBUSRES ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
-/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
-/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
-#define AT91C_UDP_EP0 ( 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */
-#define AT91C_UDP_EP1 ( 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */
-#define AT91C_UDP_EP2 ( 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */
-#define AT91C_UDP_EP3 ( 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */
-#define AT91C_UDP_EP4 ( 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */
-#define AT91C_UDP_EP5 ( 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */
-#define AT91C_UDP_EP6 ( 0x1 << 6 ) /* (UDP) Reset Endpoint 6 */
-#define AT91C_UDP_EP7 ( 0x1 << 7 ) /* (UDP) Reset Endpoint 7 */
-/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
-#define AT91C_UDP_TXCOMP ( 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */
-#define AT91C_UDP_RX_DATA_BK0 ( 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */
-#define AT91C_UDP_RXSETUP ( 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */
-#define AT91C_UDP_ISOERROR ( 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */
-#define AT91C_UDP_TXPKTRDY ( 0x1 << 4 ) /* (UDP) Transmit Packet Ready */
-#define AT91C_UDP_FORCESTALL ( 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
-#define AT91C_UDP_RX_DATA_BK1 ( 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
-#define AT91C_UDP_DIR ( 0x1 << 7 ) /* (UDP) Transfer Direction */
-#define AT91C_UDP_EPTYPE ( 0x7 << 8 ) /* (UDP) Endpoint type */
-#define AT91C_UDP_EPTYPE_CTRL ( 0x0 << 8 ) /* (UDP) Control */
-#define AT91C_UDP_EPTYPE_ISO_OUT ( 0x1 << 8 ) /* (UDP) Isochronous OUT */
-#define AT91C_UDP_EPTYPE_BULK_OUT ( 0x2 << 8 ) /* (UDP) Bulk OUT */
-#define AT91C_UDP_EPTYPE_INT_OUT ( 0x3 << 8 ) /* (UDP) Interrupt OUT */
-#define AT91C_UDP_EPTYPE_ISO_IN ( 0x5 << 8 ) /* (UDP) Isochronous IN */
-#define AT91C_UDP_EPTYPE_BULK_IN ( 0x6 << 8 ) /* (UDP) Bulk IN */
-#define AT91C_UDP_EPTYPE_INT_IN ( 0x7 << 8 ) /* (UDP) Interrupt IN */
-#define AT91C_UDP_DTGLE ( 0x1 << 11 ) /* (UDP) Data Toggle */
-#define AT91C_UDP_EPEDS ( 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */
-#define AT91C_UDP_RXBYTECNT ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+// *** Register offset in AT91S_UDP structure ***
+#define UDP_NUM ( 0) // Frame Number Register
+#define UDP_GLBSTATE ( 4) // Global State Register
+#define UDP_FADDR ( 8) // Function Address Register
+#define UDP_IER (16) // Interrupt Enable Register
+#define UDP_IDR (20) // Interrupt Disable Register
+#define UDP_IMR (24) // Interrupt Mask Register
+#define UDP_ISR (28) // Interrupt Status Register
+#define UDP_ICR (32) // Interrupt Clear Register
+#define UDP_RSTEP (40) // Reset Endpoint Register
+#define UDP_CSR (48) // Endpoint Control and Status Register
+#define UDP_FDR (80) // Endpoint FIFO Data Register
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-/* ***************************************************************************** */
-/* REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 */
-/* ***************************************************************************** */
-/* ========== Register definition for SYSC peripheral ========== */
-#define AT91C_SYSC_SYSC_VRPM ( 0xFFFFFD60 ) /* (SYSC) Voltage Regulator Power Mode Register */
-/* ========== Register definition for AIC peripheral ========== */
-#define AT91C_AIC_ICCR ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
-#define AT91C_AIC_IECR ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
-#define AT91C_AIC_SMR ( 0xFFFFF000 ) /* (AIC) Source Mode Register */
-#define AT91C_AIC_ISCR ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
-#define AT91C_AIC_EOICR ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
-#define AT91C_AIC_DCR ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
-#define AT91C_AIC_FFER ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
-#define AT91C_AIC_SVR ( 0xFFFFF080 ) /* (AIC) Source Vector Register */
-#define AT91C_AIC_SPU ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
-#define AT91C_AIC_FFDR ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
-#define AT91C_AIC_FVR ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
-#define AT91C_AIC_FFSR ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
-#define AT91C_AIC_IMR ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
-#define AT91C_AIC_ISR ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
-#define AT91C_AIC_IVR ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
-#define AT91C_AIC_IDCR ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
-#define AT91C_AIC_CISR ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
-#define AT91C_AIC_IPR ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
-/* ========== Register definition for DBGU peripheral ========== */
-#define AT91C_DBGU_C2R ( 0xFFFFF244 ) /* (DBGU) Chip ID2 Register */
-#define AT91C_DBGU_THR ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
-#define AT91C_DBGU_CSR ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */
-#define AT91C_DBGU_IDR ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
-#define AT91C_DBGU_MR ( 0xFFFFF204 ) /* (DBGU) Mode Register */
-#define AT91C_DBGU_FNTR ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
-#define AT91C_DBGU_C1R ( 0xFFFFF240 ) /* (DBGU) Chip ID1 Register */
-#define AT91C_DBGU_BRGR ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
-#define AT91C_DBGU_RHR ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
-#define AT91C_DBGU_IMR ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
-#define AT91C_DBGU_IER ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
-#define AT91C_DBGU_CR ( 0xFFFFF200 ) /* (DBGU) Control Register */
-/* ========== Register definition for PDC_DBGU peripheral ========== */
-#define AT91C_DBGU_TNCR ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
-#define AT91C_DBGU_RNCR ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
-#define AT91C_DBGU_PTCR ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
-#define AT91C_DBGU_PTSR ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
-#define AT91C_DBGU_RCR ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
-#define AT91C_DBGU_TCR ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
-#define AT91C_DBGU_RPR ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
-#define AT91C_DBGU_TPR ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
-#define AT91C_DBGU_RNPR ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
-#define AT91C_DBGU_TNPR ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
-/* ========== Register definition for PIOA peripheral ========== */
-#define AT91C_PIOA_IMR ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
-#define AT91C_PIOA_IER ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
-#define AT91C_PIOA_OWDR ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
-#define AT91C_PIOA_ISR ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
-#define AT91C_PIOA_PPUDR ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
-#define AT91C_PIOA_MDSR ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
-#define AT91C_PIOA_MDER ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
-#define AT91C_PIOA_PER ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_PSR ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */
-#define AT91C_PIOA_OER ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */
-#define AT91C_PIOA_BSR ( 0xFFFFF474 ) /* (PIOA) Select B Register */
-#define AT91C_PIOA_PPUER ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
-#define AT91C_PIOA_MDDR ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
-#define AT91C_PIOA_PDR ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_ODR ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
-#define AT91C_PIOA_IFDR ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
-#define AT91C_PIOA_ABSR ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
-#define AT91C_PIOA_ASR ( 0xFFFFF470 ) /* (PIOA) Select A Register */
-#define AT91C_PIOA_PPUSR ( 0xFFFFF468 ) /* (PIOA) Pad Pull-up Status Register */
-#define AT91C_PIOA_ODSR ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
-#define AT91C_PIOA_SODR ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
-#define AT91C_PIOA_IFSR ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
-#define AT91C_PIOA_IFER ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
-#define AT91C_PIOA_OSR ( 0xFFFFF418 ) /* (PIOA) Output Status Register */
-#define AT91C_PIOA_IDR ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
-#define AT91C_PIOA_PDSR ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
-#define AT91C_PIOA_CODR ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
-#define AT91C_PIOA_OWSR ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
-#define AT91C_PIOA_OWER ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
-/* ========== Register definition for CKGR peripheral ========== */
-#define AT91C_CKGR_PLLR ( 0xFFFFFC2C ) /* (CKGR) PLL Register */
-#define AT91C_CKGR_MCFR ( 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */
-#define AT91C_CKGR_MOR ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
-/* ========== Register definition for PMC peripheral ========== */
-#define AT91C_PMC_SCSR ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
-#define AT91C_PMC_SCER ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
-#define AT91C_PMC_IMR ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
-#define AT91C_PMC_IDR ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
-#define AT91C_PMC_PCDR ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
-#define AT91C_PMC_SCDR ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
-#define AT91C_PMC_SR ( 0xFFFFFC68 ) /* (PMC) Status Register */
-#define AT91C_PMC_IER ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
-#define AT91C_PMC_MCKR ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */
-#define AT91C_PMC_MOR ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
-#define AT91C_PMC_PCER ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCSR ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
-#define AT91C_PMC_PLLR ( 0xFFFFFC2C ) /* (PMC) PLL Register */
-#define AT91C_PMC_MCFR ( 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */
-#define AT91C_PMC_PCKR ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
-/* ========== Register definition for RSTC peripheral ========== */
-#define AT91C_RSTC_RSR ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
-#define AT91C_RSTC_RMR ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
-#define AT91C_RSTC_RCR ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
-/* ========== Register definition for RTTC peripheral ========== */
-#define AT91C_RTTC_RTSR ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
-#define AT91C_RTTC_RTAR ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
-#define AT91C_RTTC_RTVR ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
-#define AT91C_RTTC_RTMR ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
-/* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIIR ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
-#define AT91C_PITC_PISR ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
-#define AT91C_PITC_PIVR ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
-#define AT91C_PITC_PIMR ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
-/* ========== Register definition for WDTC peripheral ========== */
-#define AT91C_WDTC_WDMR ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
-#define AT91C_WDTC_WDSR ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
-#define AT91C_WDTC_WDCR ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
-/* ========== Register definition for MC peripheral ========== */
-#define AT91C_MC_FCR ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
-#define AT91C_MC_ASR ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
-#define AT91C_MC_FSR ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
-#define AT91C_MC_FMR ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
-#define AT91C_MC_AASR ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
-#define AT91C_MC_RCR ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
-/* ========== Register definition for PDC_SPI peripheral ========== */
-#define AT91C_SPI_PTCR ( 0xFFFE0120 ) /* (PDC_SPI) PDC Transfer Control Register */
-#define AT91C_SPI_TNPR ( 0xFFFE0118 ) /* (PDC_SPI) Transmit Next Pointer Register */
-#define AT91C_SPI_RNPR ( 0xFFFE0110 ) /* (PDC_SPI) Receive Next Pointer Register */
-#define AT91C_SPI_TPR ( 0xFFFE0108 ) /* (PDC_SPI) Transmit Pointer Register */
-#define AT91C_SPI_RPR ( 0xFFFE0100 ) /* (PDC_SPI) Receive Pointer Register */
-#define AT91C_SPI_PTSR ( 0xFFFE0124 ) /* (PDC_SPI) PDC Transfer Status Register */
-#define AT91C_SPI_TNCR ( 0xFFFE011C ) /* (PDC_SPI) Transmit Next Counter Register */
-#define AT91C_SPI_RNCR ( 0xFFFE0114 ) /* (PDC_SPI) Receive Next Counter Register */
-#define AT91C_SPI_TCR ( 0xFFFE010C ) /* (PDC_SPI) Transmit Counter Register */
-#define AT91C_SPI_RCR ( 0xFFFE0104 ) /* (PDC_SPI) Receive Counter Register */
-/* ========== Register definition for SPI peripheral ========== */
-#define AT91C_SPI_CSR ( 0xFFFE0030 ) /* (SPI) Chip Select Register */
-#define AT91C_SPI_IDR ( 0xFFFE0018 ) /* (SPI) Interrupt Disable Register */
-#define AT91C_SPI_SR ( 0xFFFE0010 ) /* (SPI) Status Register */
-#define AT91C_SPI_RDR ( 0xFFFE0008 ) /* (SPI) Receive Data Register */
-#define AT91C_SPI_CR ( 0xFFFE0000 ) /* (SPI) Control Register */
-#define AT91C_SPI_IMR ( 0xFFFE001C ) /* (SPI) Interrupt Mask Register */
-#define AT91C_SPI_IER ( 0xFFFE0014 ) /* (SPI) Interrupt Enable Register */
-#define AT91C_SPI_TDR ( 0xFFFE000C ) /* (SPI) Transmit Data Register */
-#define AT91C_SPI_MR ( 0xFFFE0004 ) /* (SPI) Mode Register */
-/* ========== Register definition for PDC_ADC peripheral ========== */
-#define AT91C_ADC_PTCR ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
-#define AT91C_ADC_TNPR ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
-#define AT91C_ADC_RNPR ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
-#define AT91C_ADC_TPR ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
-#define AT91C_ADC_RPR ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
-#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
-#define AT91C_ADC_TNCR ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
-#define AT91C_ADC_RNCR ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
-#define AT91C_ADC_TCR ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
-#define AT91C_ADC_RCR ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
-/* ========== Register definition for ADC peripheral ========== */
-#define AT91C_ADC_IMR ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
-#define AT91C_ADC_CDR4 ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
-#define AT91C_ADC_CDR2 ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
-#define AT91C_ADC_CDR0 ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
-#define AT91C_ADC_CDR7 ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
-#define AT91C_ADC_CDR1 ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
-#define AT91C_ADC_CDR3 ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
-#define AT91C_ADC_CDR5 ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
-#define AT91C_ADC_MR ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */
-#define AT91C_ADC_CDR6 ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
-#define AT91C_ADC_CR ( 0xFFFD8000 ) /* (ADC) ADC Control Register */
-#define AT91C_ADC_CHER ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
-#define AT91C_ADC_CHSR ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
-#define AT91C_ADC_IER ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
-#define AT91C_ADC_SR ( 0xFFFD801C ) /* (ADC) ADC Status Register */
-#define AT91C_ADC_CHDR ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
-#define AT91C_ADC_IDR ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
-#define AT91C_ADC_LCDR ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
-/* ========== Register definition for PDC_SSC peripheral ========== */
-#define AT91C_SSC_PTCR ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
-#define AT91C_SSC_TNPR ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
-#define AT91C_SSC_RNPR ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
-#define AT91C_SSC_TPR ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
-#define AT91C_SSC_RPR ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
-#define AT91C_SSC_PTSR ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
-#define AT91C_SSC_TNCR ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
-#define AT91C_SSC_RNCR ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
-#define AT91C_SSC_TCR ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
-#define AT91C_SSC_RCR ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
-/* ========== Register definition for SSC peripheral ========== */
-#define AT91C_SSC_RFMR ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
-#define AT91C_SSC_CMR ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */
-#define AT91C_SSC_IDR ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
-#define AT91C_SSC_SR ( 0xFFFD4040 ) /* (SSC) Status Register */
-#define AT91C_SSC_RC0R ( 0xFFFD4038 ) /* (SSC) Receive Compare 0 Register */
-#define AT91C_SSC_RSHR ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
-#define AT91C_SSC_RHR ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */
-#define AT91C_SSC_TCMR ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
-#define AT91C_SSC_RCMR ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
-#define AT91C_SSC_CR ( 0xFFFD4000 ) /* (SSC) Control Register */
-#define AT91C_SSC_IMR ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
-#define AT91C_SSC_IER ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
-#define AT91C_SSC_RC1R ( 0xFFFD403C ) /* (SSC) Receive Compare 1 Register */
-#define AT91C_SSC_TSHR ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
-#define AT91C_SSC_THR ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
-#define AT91C_SSC_TFMR ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
-/* ========== Register definition for PDC_US1 peripheral ========== */
-#define AT91C_US1_PTSR ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
-#define AT91C_US1_TNCR ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
-#define AT91C_US1_RNCR ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
-#define AT91C_US1_TCR ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
-#define AT91C_US1_RCR ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
-#define AT91C_US1_PTCR ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
-#define AT91C_US1_TNPR ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
-#define AT91C_US1_RNPR ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
-#define AT91C_US1_TPR ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
-#define AT91C_US1_RPR ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
-/* ========== Register definition for US1 peripheral ========== */
-#define AT91C_US1_XXR ( 0xFFFC4048 ) /* (US1) XON_XOFF Register */
-#define AT91C_US1_RHR ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */
-#define AT91C_US1_IMR ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
-#define AT91C_US1_IER ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
-#define AT91C_US1_CR ( 0xFFFC4000 ) /* (US1) Control Register */
-#define AT91C_US1_RTOR ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
-#define AT91C_US1_THR ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */
-#define AT91C_US1_CSR ( 0xFFFC4014 ) /* (US1) Channel Status Register */
-#define AT91C_US1_IDR ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */
-#define AT91C_US1_FIDI ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
-#define AT91C_US1_BRGR ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
-#define AT91C_US1_TTGR ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
-#define AT91C_US1_IF ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
-#define AT91C_US1_NER ( 0xFFFC4044 ) /* (US1) Nb Errors Register */
-#define AT91C_US1_MR ( 0xFFFC4004 ) /* (US1) Mode Register */
-/* ========== Register definition for PDC_US0 peripheral ========== */
-#define AT91C_US0_PTCR ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
-#define AT91C_US0_TNPR ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
-#define AT91C_US0_RNPR ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
-#define AT91C_US0_TPR ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
-#define AT91C_US0_RPR ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
-#define AT91C_US0_PTSR ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
-#define AT91C_US0_TNCR ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
-#define AT91C_US0_RNCR ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
-#define AT91C_US0_TCR ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
-#define AT91C_US0_RCR ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
-/* ========== Register definition for US0 peripheral ========== */
-#define AT91C_US0_TTGR ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
-#define AT91C_US0_BRGR ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
-#define AT91C_US0_RHR ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */
-#define AT91C_US0_IMR ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
-#define AT91C_US0_NER ( 0xFFFC0044 ) /* (US0) Nb Errors Register */
-#define AT91C_US0_RTOR ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
-#define AT91C_US0_XXR ( 0xFFFC0048 ) /* (US0) XON_XOFF Register */
-#define AT91C_US0_FIDI ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
-#define AT91C_US0_CR ( 0xFFFC0000 ) /* (US0) Control Register */
-#define AT91C_US0_IER ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
-#define AT91C_US0_IF ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
-#define AT91C_US0_MR ( 0xFFFC0004 ) /* (US0) Mode Register */
-#define AT91C_US0_IDR ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */
-#define AT91C_US0_CSR ( 0xFFFC0014 ) /* (US0) Channel Status Register */
-#define AT91C_US0_THR ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */
-/* ========== Register definition for TWI peripheral ========== */
-#define AT91C_TWI_RHR ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */
-#define AT91C_TWI_IDR ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
-#define AT91C_TWI_SR ( 0xFFFB8020 ) /* (TWI) Status Register */
-#define AT91C_TWI_CWGR ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
-#define AT91C_TWI_SMR ( 0xFFFB8008 ) /* (TWI) Slave Mode Register */
-#define AT91C_TWI_CR ( 0xFFFB8000 ) /* (TWI) Control Register */
-#define AT91C_TWI_THR ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
-#define AT91C_TWI_IMR ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
-#define AT91C_TWI_IER ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
-#define AT91C_TWI_IADR ( 0xFFFB800C ) /* (TWI) Internal Address Register */
-#define AT91C_TWI_MMR ( 0xFFFB8004 ) /* (TWI) Master Mode Register */
-/* ========== Register definition for TC2 peripheral ========== */
-#define AT91C_TC2_IMR ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
-#define AT91C_TC2_IER ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
-#define AT91C_TC2_RC ( 0xFFFA009C ) /* (TC2) Register C */
-#define AT91C_TC2_RA ( 0xFFFA0094 ) /* (TC2) Register A */
-#define AT91C_TC2_CMR ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC2_IDR ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
-#define AT91C_TC2_SR ( 0xFFFA00A0 ) /* (TC2) Status Register */
-#define AT91C_TC2_RB ( 0xFFFA0098 ) /* (TC2) Register B */
-#define AT91C_TC2_CV ( 0xFFFA0090 ) /* (TC2) Counter Value */
-#define AT91C_TC2_CCR ( 0xFFFA0080 ) /* (TC2) Channel Control Register */
-/* ========== Register definition for TC1 peripheral ========== */
-#define AT91C_TC1_IMR ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
-#define AT91C_TC1_IER ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
-#define AT91C_TC1_RC ( 0xFFFA005C ) /* (TC1) Register C */
-#define AT91C_TC1_RA ( 0xFFFA0054 ) /* (TC1) Register A */
-#define AT91C_TC1_CMR ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC1_IDR ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
-#define AT91C_TC1_SR ( 0xFFFA0060 ) /* (TC1) Status Register */
-#define AT91C_TC1_RB ( 0xFFFA0058 ) /* (TC1) Register B */
-#define AT91C_TC1_CV ( 0xFFFA0050 ) /* (TC1) Counter Value */
-#define AT91C_TC1_CCR ( 0xFFFA0040 ) /* (TC1) Channel Control Register */
-/* ========== Register definition for TC0 peripheral ========== */
-#define AT91C_TC0_IMR ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
-#define AT91C_TC0_IER ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
-#define AT91C_TC0_RC ( 0xFFFA001C ) /* (TC0) Register C */
-#define AT91C_TC0_RA ( 0xFFFA0014 ) /* (TC0) Register A */
-#define AT91C_TC0_CMR ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC0_IDR ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
-#define AT91C_TC0_SR ( 0xFFFA0020 ) /* (TC0) Status Register */
-#define AT91C_TC0_RB ( 0xFFFA0018 ) /* (TC0) Register B */
-#define AT91C_TC0_CV ( 0xFFFA0010 ) /* (TC0) Counter Value */
-#define AT91C_TC0_CCR ( 0xFFFA0000 ) /* (TC0) Channel Control Register */
-/* ========== Register definition for TCB peripheral ========== */
-#define AT91C_TCB_BMR ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
-#define AT91C_TCB_BCR ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
-/* ========== Register definition for PWMC_CH3 peripheral ========== */
-#define AT91C_CH3_CUPDR ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
-#define AT91C_CH3_CPRDR ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
-#define AT91C_CH3_CMR ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
-#define AT91C_CH3_Reserved ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
-#define AT91C_CH3_CCNTR ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
-#define AT91C_CH3_CDTYR ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH2 peripheral ========== */
-#define AT91C_CH2_CUPDR ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
-#define AT91C_CH2_CPRDR ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
-#define AT91C_CH2_CMR ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
-#define AT91C_CH2_Reserved ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
-#define AT91C_CH2_CCNTR ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
-#define AT91C_CH2_CDTYR ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH1 peripheral ========== */
-#define AT91C_CH1_CUPDR ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
-#define AT91C_CH1_CPRDR ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
-#define AT91C_CH1_CMR ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
-#define AT91C_CH1_Reserved ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
-#define AT91C_CH1_CCNTR ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
-#define AT91C_CH1_CDTYR ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH0 peripheral ========== */
-#define AT91C_CH0_CUPDR ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
-#define AT91C_CH0_CPRDR ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
-#define AT91C_CH0_CMR ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
-#define AT91C_CH0_Reserved ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
-#define AT91C_CH0_CCNTR ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
-#define AT91C_CH0_CDTYR ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC peripheral ========== */
-#define AT91C_PWMC_VR ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
-#define AT91C_PWMC_ISR ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
-#define AT91C_PWMC_IDR ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
-#define AT91C_PWMC_SR ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
-#define AT91C_PWMC_ENA ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
-#define AT91C_PWMC_IMR ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
-#define AT91C_PWMC_MR ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
-#define AT91C_PWMC_DIS ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
-#define AT91C_PWMC_IER ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
-/* ========== Register definition for UDP peripheral ========== */
-#define AT91C_UDP_ISR ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */
-#define AT91C_UDP_IDR ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
-#define AT91C_UDP_GLBSTATE ( 0xFFFB0004 ) /* (UDP) Global State Register */
-#define AT91C_UDP_FDR ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
-#define AT91C_UDP_CSR ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
-#define AT91C_UDP_RSTEP ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
-#define AT91C_UDP_ICR ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
-#define AT91C_UDP_IMR ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
-#define AT91C_UDP_IER ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
-#define AT91C_UDP_FADDR ( 0xFFFB0008 ) /* (UDP) Function Address Register */
-#define AT91C_UDP_NUM ( 0xFFFB0000 ) /* (UDP) Frame Number Register */
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
+// *****************************************************************************
+// ========== Register definition for SYSC peripheral ==========
+#define AT91C_SYSC_SYSC_VRPM (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
+#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register
+#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register
+#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register
+#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register
+#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register
+#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
+#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
+#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
+#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
+#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register
+#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register
+// ========== Register definition for PDC_SPI peripheral ==========
+#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
+#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
+#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register
+// ========== Register definition for SPI peripheral ==========
+#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register
+#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register
+#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register
+#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register
+#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register
+#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register
+#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_RC0R (0xFFFD4038) // (SSC) Receive Compare 0 Register
+#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_RC1R (0xFFFD403C) // (SSC) Receive Compare 1 Register
+#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register
+#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register
+#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register
+#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register
+#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register
+#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value
+#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register
+#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+#define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+#define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+#define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register
+#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register
-/* ***************************************************************************** */
-/* PIO DEFINITIONS FOR AT91SAM7S64 */
-/* ***************************************************************************** */
-#define AT91C_PIO_PA0 ( 1 << 0 ) /* Pin Controlled by PA0 */
-#define AT91C_PA0_PWM0 ( AT91C_PIO_PA0 ) /* PWM Channel 0 */
-#define AT91C_PA0_TIOA0 ( AT91C_PIO_PA0 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */
-#define AT91C_PIO_PA1 ( 1 << 1 ) /* Pin Controlled by PA1 */
-#define AT91C_PA1_PWM1 ( AT91C_PIO_PA1 ) /* PWM Channel 1 */
-#define AT91C_PA1_TIOB0 ( AT91C_PIO_PA1 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */
-#define AT91C_PIO_PA10 ( 1 << 10 ) /* Pin Controlled by PA10 */
-#define AT91C_PA10_DTXD ( AT91C_PIO_PA10 ) /* DBGU Debug Transmit Data */
-#define AT91C_PA10_NPCS2 ( AT91C_PIO_PA10 ) /* SPI Peripheral Chip Select 2 */
-#define AT91C_PIO_PA11 ( 1 << 11 ) /* Pin Controlled by PA11 */
-#define AT91C_PA11_NPCS0 ( AT91C_PIO_PA11 ) /* SPI Peripheral Chip Select 0 */
-#define AT91C_PA11_PWM0 ( AT91C_PIO_PA11 ) /* PWM Channel 0 */
-#define AT91C_PIO_PA12 ( 1 << 12 ) /* Pin Controlled by PA12 */
-#define AT91C_PA12_MISO ( AT91C_PIO_PA12 ) /* SPI Master In Slave */
-#define AT91C_PA12_PWM1 ( AT91C_PIO_PA12 ) /* PWM Channel 1 */
-#define AT91C_PIO_PA13 ( 1 << 13 ) /* Pin Controlled by PA13 */
-#define AT91C_PA13_MOSI ( AT91C_PIO_PA13 ) /* SPI Master Out Slave */
-#define AT91C_PA13_PWM2 ( AT91C_PIO_PA13 ) /* PWM Channel 2 */
-#define AT91C_PIO_PA14 ( 1 << 14 ) /* Pin Controlled by PA14 */
-#define AT91C_PA14_SPCK ( AT91C_PIO_PA14 ) /* SPI Serial Clock */
-#define AT91C_PA14_PWM3 ( AT91C_PIO_PA14 ) /* PWM Channel 3 */
-#define AT91C_PIO_PA15 ( 1 << 15 ) /* Pin Controlled by PA15 */
-#define AT91C_PA15_TF ( AT91C_PIO_PA15 ) /* SSC Transmit Frame Sync */
-#define AT91C_PA15_TIOA1 ( AT91C_PIO_PA15 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */
-#define AT91C_PIO_PA16 ( 1 << 16 ) /* Pin Controlled by PA16 */
-#define AT91C_PA16_TK ( AT91C_PIO_PA16 ) /* SSC Transmit Clock */
-#define AT91C_PA16_TIOB1 ( AT91C_PIO_PA16 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */
-#define AT91C_PIO_PA17 ( 1 << 17 ) /* Pin Controlled by PA17 */
-#define AT91C_PA17_TD ( AT91C_PIO_PA17 ) /* SSC Transmit data */
-#define AT91C_PA17_PCK1 ( AT91C_PIO_PA17 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PA18 ( 1 << 18 ) /* Pin Controlled by PA18 */
-#define AT91C_PA18_RD ( AT91C_PIO_PA18 ) /* SSC Receive Data */
-#define AT91C_PA18_PCK2 ( AT91C_PIO_PA18 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PA19 ( 1 << 19 ) /* Pin Controlled by PA19 */
-#define AT91C_PA19_RK ( AT91C_PIO_PA19 ) /* SSC Receive Clock */
-#define AT91C_PA19_FIQ ( AT91C_PIO_PA19 ) /* AIC Fast Interrupt Input */
-#define AT91C_PIO_PA2 ( 1 << 2 ) /* Pin Controlled by PA2 */
-#define AT91C_PA2_PWM2 ( AT91C_PIO_PA2 ) /* PWM Channel 2 */
-#define AT91C_PA2_SCK0 ( AT91C_PIO_PA2 ) /* USART 0 Serial Clock */
-#define AT91C_PIO_PA20 ( 1 << 20 ) /* Pin Controlled by PA20 */
-#define AT91C_PA20_RF ( AT91C_PIO_PA20 ) /* SSC Receive Frame Sync */
-#define AT91C_PA20_IRQ0 ( AT91C_PIO_PA20 ) /* External Interrupt 0 */
-#define AT91C_PIO_PA21 ( 1 << 21 ) /* Pin Controlled by PA21 */
-#define AT91C_PA21_RXD1 ( AT91C_PIO_PA21 ) /* USART 1 Receive Data */
-#define AT91C_PA21_PCK1 ( AT91C_PIO_PA21 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PA22 ( 1 << 22 ) /* Pin Controlled by PA22 */
-#define AT91C_PA22_TXD1 ( AT91C_PIO_PA22 ) /* USART 1 Transmit Data */
-#define AT91C_PA22_NPCS3 ( AT91C_PIO_PA22 ) /* SPI Peripheral Chip Select 3 */
-#define AT91C_PIO_PA23 ( 1 << 23 ) /* Pin Controlled by PA23 */
-#define AT91C_PA23_SCK1 ( AT91C_PIO_PA23 ) /* USART 1 Serial Clock */
-#define AT91C_PA23_PWM0 ( AT91C_PIO_PA23 ) /* PWM Channel 0 */
-#define AT91C_PIO_PA24 ( 1 << 24 ) /* Pin Controlled by PA24 */
-#define AT91C_PA24_RTS1 ( AT91C_PIO_PA24 ) /* USART 1 Ready To Send */
-#define AT91C_PA24_PWM1 ( AT91C_PIO_PA24 ) /* PWM Channel 1 */
-#define AT91C_PIO_PA25 ( 1 << 25 ) /* Pin Controlled by PA25 */
-#define AT91C_PA25_CTS1 ( AT91C_PIO_PA25 ) /* USART 1 Clear To Send */
-#define AT91C_PA25_PWM2 ( AT91C_PIO_PA25 ) /* PWM Channel 2 */
-#define AT91C_PIO_PA26 ( 1 << 26 ) /* Pin Controlled by PA26 */
-#define AT91C_PA26_DCD1 ( AT91C_PIO_PA26 ) /* USART 1 Data Carrier Detect */
-#define AT91C_PA26_TIOA2 ( AT91C_PIO_PA26 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */
-#define AT91C_PIO_PA27 ( 1 << 27 ) /* Pin Controlled by PA27 */
-#define AT91C_PA27_DTR1 ( AT91C_PIO_PA27 ) /* USART 1 Data Terminal ready */
-#define AT91C_PA27_TIOB2 ( AT91C_PIO_PA27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */
-#define AT91C_PIO_PA28 ( 1 << 28 ) /* Pin Controlled by PA28 */
-#define AT91C_PA28_DSR1 ( AT91C_PIO_PA28 ) /* USART 1 Data Set ready */
-#define AT91C_PA28_TCLK1 ( AT91C_PIO_PA28 ) /* Timer Counter 1 external clock input */
-#define AT91C_PIO_PA29 ( 1 << 29 ) /* Pin Controlled by PA29 */
-#define AT91C_PA29_RI1 ( AT91C_PIO_PA29 ) /* USART 1 Ring Indicator */
-#define AT91C_PA29_TCLK2 ( AT91C_PIO_PA29 ) /* Timer Counter 2 external clock input */
-#define AT91C_PIO_PA3 ( 1 << 3 ) /* Pin Controlled by PA3 */
-#define AT91C_PA3_TWD ( AT91C_PIO_PA3 ) /* TWI Two-wire Serial Data */
-#define AT91C_PA3_NPCS3 ( AT91C_PIO_PA3 ) /* SPI Peripheral Chip Select 3 */
-#define AT91C_PIO_PA30 ( 1 << 30 ) /* Pin Controlled by PA30 */
-#define AT91C_PA30_IRQ1 ( AT91C_PIO_PA30 ) /* External Interrupt 1 */
-#define AT91C_PA30_NPCS2 ( AT91C_PIO_PA30 ) /* SPI Peripheral Chip Select 2 */
-#define AT91C_PIO_PA31 ( 1 << 31 ) /* Pin Controlled by PA31 */
-#define AT91C_PA31_NPCS1 ( AT91C_PIO_PA31 ) /* SPI Peripheral Chip Select 1 */
-#define AT91C_PA31_PCK2 ( AT91C_PIO_PA31 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PA4 ( 1 << 4 ) /* Pin Controlled by PA4 */
-#define AT91C_PA4_TWCK ( AT91C_PIO_PA4 ) /* TWI Two-wire Serial Clock */
-#define AT91C_PA4_TCLK0 ( AT91C_PIO_PA4 ) /* Timer Counter 0 external clock input */
-#define AT91C_PIO_PA5 ( 1 << 5 ) /* Pin Controlled by PA5 */
-#define AT91C_PA5_RXD0 ( AT91C_PIO_PA5 ) /* USART 0 Receive Data */
-#define AT91C_PA5_NPCS3 ( AT91C_PIO_PA5 ) /* SPI Peripheral Chip Select 3 */
-#define AT91C_PIO_PA6 ( 1 << 6 ) /* Pin Controlled by PA6 */
-#define AT91C_PA6_TXD0 ( AT91C_PIO_PA6 ) /* USART 0 Transmit Data */
-#define AT91C_PA6_PCK0 ( AT91C_PIO_PA6 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PA7 ( 1 << 7 ) /* Pin Controlled by PA7 */
-#define AT91C_PA7_RTS0 ( AT91C_PIO_PA7 ) /* USART 0 Ready To Send */
-#define AT91C_PA7_PWM3 ( AT91C_PIO_PA7 ) /* PWM Channel 3 */
-#define AT91C_PIO_PA8 ( 1 << 8 ) /* Pin Controlled by PA8 */
-#define AT91C_PA8_CTS0 ( AT91C_PIO_PA8 ) /* USART 0 Clear To Send */
-#define AT91C_PA8_ADTRG ( AT91C_PIO_PA8 ) /* ADC External Trigger */
-#define AT91C_PIO_PA9 ( 1 << 9 ) /* Pin Controlled by PA9 */
-#define AT91C_PA9_DRXD ( AT91C_PIO_PA9 ) /* DBGU Debug Receive Data */
-#define AT91C_PA9_NPCS1 ( AT91C_PIO_PA9 ) /* SPI Peripheral Chip Select 1 */
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0
+#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1
+#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data
+#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
+#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave
+#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave
+#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock
+#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync
+#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock
+#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data
+#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data
+#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock
+#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2
+#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync
+#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data
+#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data
+#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock
+#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send
+#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send
+#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect
+#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready
+#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready
+#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator
+#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data
+#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1
+#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
+#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock
+#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data
+#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data
+#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send
+#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send
+#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data
+#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
-/* ***************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */
-/* ***************************************************************************** */
-#define AT91C_ID_FIQ ( 0 ) /* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS ( 1 ) /* System Peripheral */
-#define AT91C_ID_PIOA ( 2 ) /* Parallel IO Controller */
-#define AT91C_ID_3_Reserved ( 3 ) /* Reserved */
-#define AT91C_ID_ADC ( 4 ) /* Analog-to-Digital Converter */
-#define AT91C_ID_SPI ( 5 ) /* Serial Peripheral Interface */
-#define AT91C_ID_US0 ( 6 ) /* USART 0 */
-#define AT91C_ID_US1 ( 7 ) /* USART 1 */
-#define AT91C_ID_SSC ( 8 ) /* Serial Synchronous Controller */
-#define AT91C_ID_TWI ( 9 ) /* Two-Wire Interface */
-#define AT91C_ID_PWMC ( 10 ) /* PWM Controller */
-#define AT91C_ID_UDP ( 11 ) /* USB Device Port */
-#define AT91C_ID_TC0 ( 12 ) /* Timer Counter 0 */
-#define AT91C_ID_TC1 ( 13 ) /* Timer Counter 1 */
-#define AT91C_ID_TC2 ( 14 ) /* Timer Counter 2 */
-#define AT91C_ID_15_Reserved ( 15 ) /* Reserved */
-#define AT91C_ID_16_Reserved ( 16 ) /* Reserved */
-#define AT91C_ID_17_Reserved ( 17 ) /* Reserved */
-#define AT91C_ID_18_Reserved ( 18 ) /* Reserved */
-#define AT91C_ID_19_Reserved ( 19 ) /* Reserved */
-#define AT91C_ID_20_Reserved ( 20 ) /* Reserved */
-#define AT91C_ID_21_Reserved ( 21 ) /* Reserved */
-#define AT91C_ID_22_Reserved ( 22 ) /* Reserved */
-#define AT91C_ID_23_Reserved ( 23 ) /* Reserved */
-#define AT91C_ID_24_Reserved ( 24 ) /* Reserved */
-#define AT91C_ID_25_Reserved ( 25 ) /* Reserved */
-#define AT91C_ID_26_Reserved ( 26 ) /* Reserved */
-#define AT91C_ID_27_Reserved ( 27 ) /* Reserved */
-#define AT91C_ID_28_Reserved ( 28 ) /* Reserved */
-#define AT91C_ID_29_Reserved ( 29 ) /* Reserved */
-#define AT91C_ID_IRQ0 ( 30 ) /* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1 ( 31 ) /* Advanced Interrupt Controller (IRQ1) */
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ( 1) // System Peripheral
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller
+#define AT91C_ID_3_Reserved ( 3) // Reserved
+#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter
+#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface
+#define AT91C_ID_US0 ( 6) // USART 0
+#define AT91C_ID_US1 ( 7) // USART 1
+#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ( 9) // Two-Wire Interface
+#define AT91C_ID_PWMC (10) // PWM Controller
+#define AT91C_ID_UDP (11) // USB Device Port
+#define AT91C_ID_TC0 (12) // Timer Counter 0
+#define AT91C_ID_TC1 (13) // Timer Counter 1
+#define AT91C_ID_TC2 (14) // Timer Counter 2
+#define AT91C_ID_15_Reserved (15) // Reserved
+#define AT91C_ID_16_Reserved (16) // Reserved
+#define AT91C_ID_17_Reserved (17) // Reserved
+#define AT91C_ID_18_Reserved (18) // Reserved
+#define AT91C_ID_19_Reserved (19) // Reserved
+#define AT91C_ID_20_Reserved (20) // Reserved
+#define AT91C_ID_21_Reserved (21) // Reserved
+#define AT91C_ID_22_Reserved (22) // Reserved
+#define AT91C_ID_23_Reserved (23) // Reserved
+#define AT91C_ID_24_Reserved (24) // Reserved
+#define AT91C_ID_25_Reserved (25) // Reserved
+#define AT91C_ID_26_Reserved (26) // Reserved
+#define AT91C_ID_27_Reserved (27) // Reserved
+#define AT91C_ID_28_Reserved (28) // Reserved
+#define AT91C_ID_29_Reserved (29) // Reserved
+#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
-/* ***************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 */
-/* ***************************************************************************** */
-#define AT91C_BASE_SYSC ( 0xFFFFF000 ) /* (SYSC) Base Address */
-#define AT91C_BASE_AIC ( 0xFFFFF000 ) /* (AIC) Base Address */
-#define AT91C_BASE_DBGU ( 0xFFFFF200 ) /* (DBGU) Base Address */
-#define AT91C_BASE_PDC_DBGU ( 0xFFFFF300 ) /* (PDC_DBGU) Base Address */
-#define AT91C_BASE_PIOA ( 0xFFFFF400 ) /* (PIOA) Base Address */
-#define AT91C_BASE_CKGR ( 0xFFFFFC20 ) /* (CKGR) Base Address */
-#define AT91C_BASE_PMC ( 0xFFFFFC00 ) /* (PMC) Base Address */
-#define AT91C_BASE_RSTC ( 0xFFFFFD00 ) /* (RSTC) Base Address */
-#define AT91C_BASE_RTTC ( 0xFFFFFD20 ) /* (RTTC) Base Address */
-#define AT91C_BASE_PITC ( 0xFFFFFD30 ) /* (PITC) Base Address */
-#define AT91C_BASE_WDTC ( 0xFFFFFD40 ) /* (WDTC) Base Address */
-#define AT91C_BASE_MC ( 0xFFFFFF00 ) /* (MC) Base Address */
-#define AT91C_BASE_PDC_SPI ( 0xFFFE0100 ) /* (PDC_SPI) Base Address */
-#define AT91C_BASE_SPI ( 0xFFFE0000 ) /* (SPI) Base Address */
-#define AT91C_BASE_PDC_ADC ( 0xFFFD8100 ) /* (PDC_ADC) Base Address */
-#define AT91C_BASE_ADC ( 0xFFFD8000 ) /* (ADC) Base Address */
-#define AT91C_BASE_PDC_SSC ( 0xFFFD4100 ) /* (PDC_SSC) Base Address */
-#define AT91C_BASE_SSC ( 0xFFFD4000 ) /* (SSC) Base Address */
-#define AT91C_BASE_PDC_US1 ( 0xFFFC4100 ) /* (PDC_US1) Base Address */
-#define AT91C_BASE_US1 ( 0xFFFC4000 ) /* (US1) Base Address */
-#define AT91C_BASE_PDC_US0 ( 0xFFFC0100 ) /* (PDC_US0) Base Address */
-#define AT91C_BASE_US0 ( 0xFFFC0000 ) /* (US0) Base Address */
-#define AT91C_BASE_TWI ( 0xFFFB8000 ) /* (TWI) Base Address */
-#define AT91C_BASE_TC2 ( 0xFFFA0080 ) /* (TC2) Base Address */
-#define AT91C_BASE_TC1 ( 0xFFFA0040 ) /* (TC1) Base Address */
-#define AT91C_BASE_TC0 ( 0xFFFA0000 ) /* (TC0) Base Address */
-#define AT91C_BASE_TCB ( 0xFFFA0000 ) /* (TCB) Base Address */
-#define AT91C_BASE_PWMC_CH3 ( 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
-#define AT91C_BASE_PWMC_CH2 ( 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
-#define AT91C_BASE_PWMC_CH1 ( 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
-#define AT91C_BASE_PWMC_CH0 ( 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
-#define AT91C_BASE_PWMC ( 0xFFFCC000 ) /* (PWMC) Base Address */
-#define AT91C_BASE_UDP ( 0xFFFB0000 ) /* (UDP) Base Address */
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address
+#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address
-/* ***************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 */
-/* ***************************************************************************** */
-#define AT91C_ISRAM ( 0x00200000 ) /* Internal SRAM base address */
-#define AT91C_ISRAM_SIZE ( 0x00004000 ) /* Internal SRAM size in byte (16 Kbyte) */
-#define AT91C_IFLASH ( 0x00100000 ) /* Internal ROM base address */
-#define AT91C_IFLASH_SIZE ( 0x00010000 ) /* Internal ROM size in byte (64 Kbyte) */
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte)
+#define AT91C_IFLASH (0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte)
+
+
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
index 9164d0c..ae4f35f 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
@@ -1,2743 +1,2715 @@
-/* ---------------------------------------------------------------------------- */
-/* ATMEL Microcontroller Software Support - ROUSSET - */
-/* ---------------------------------------------------------------------------- */
-/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* ---------------------------------------------------------------------------- */
-/* File Name : AT91SAM7X128.h */
-/* Object : AT91SAM7X128 definitions */
-/* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) */
-/* */
-/* CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// */
-/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */
-/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
-/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */
-/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */
-/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
-/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
-/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
-/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */
-/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */
-/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */
-/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */
-/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */
-/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */
-/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
-/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
-/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
-/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
-/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
-/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
-/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */
-/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */
-/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
-/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */
-/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
-/* ---------------------------------------------------------------------------- */
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM7X128.h
+// Object : AT91SAM7X128 definitions
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:23)
+//
+// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// ----------------------------------------------------------------------------
#ifndef AT91SAM7X128_H
#define AT91SAM7X128_H
-typedef volatile unsigned int AT91_REG; /* Hardware register definition */
+typedef volatile unsigned int AT91_REG;// Hardware register definition
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR System Peripherals */
-/* ***************************************************************************** */
-typedef struct _AT91S_SYS
-{
- AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
- AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
- AT91_REG AIC_IVR; /* IRQ Vector Register */
- AT91_REG AIC_FVR; /* FIQ Vector Register */
- AT91_REG AIC_ISR; /* Interrupt Status Register */
- AT91_REG AIC_IPR; /* Interrupt Pending Register */
- AT91_REG AIC_IMR; /* Interrupt Mask Register */
- AT91_REG AIC_CISR; /* Core Interrupt Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
- AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
- AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
- AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
- AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
- AT91_REG AIC_SPU; /* Spurious Vector Register */
- AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
- AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
- AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
- AT91_REG Reserved2[ 45 ]; /* */
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved3[ 7 ]; /* */
- AT91_REG DBGU_CIDR; /* Chip ID Register */
- AT91_REG DBGU_EXID; /* Chip ID Extension Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved4[ 45 ]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
- AT91_REG Reserved5[ 54 ]; /* */
- AT91_REG PIOA_PER; /* PIO Enable Register */
- AT91_REG PIOA_PDR; /* PIO Disable Register */
- AT91_REG PIOA_PSR; /* PIO Status Register */
- AT91_REG Reserved6[ 1 ]; /* */
- AT91_REG PIOA_OER; /* Output Enable Register */
- AT91_REG PIOA_ODR; /* Output Disable Registerr */
- AT91_REG PIOA_OSR; /* Output Status Register */
- AT91_REG Reserved7[ 1 ]; /* */
- AT91_REG PIOA_IFER; /* Input Filter Enable Register */
- AT91_REG PIOA_IFDR; /* Input Filter Disable Register */
- AT91_REG PIOA_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved8[ 1 ]; /* */
- AT91_REG PIOA_SODR; /* Set Output Data Register */
- AT91_REG PIOA_CODR; /* Clear Output Data Register */
- AT91_REG PIOA_ODSR; /* Output Data Status Register */
- AT91_REG PIOA_PDSR; /* Pin Data Status Register */
- AT91_REG PIOA_IER; /* Interrupt Enable Register */
- AT91_REG PIOA_IDR; /* Interrupt Disable Register */
- AT91_REG PIOA_IMR; /* Interrupt Mask Register */
- AT91_REG PIOA_ISR; /* Interrupt Status Register */
- AT91_REG PIOA_MDER; /* Multi-driver Enable Register */
- AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIOA_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved9[ 1 ]; /* */
- AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIOA_PPUER; /* Pull-up Enable Register */
- AT91_REG PIOA_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved10[ 1 ]; /* */
- AT91_REG PIOA_ASR; /* Select A Register */
- AT91_REG PIOA_BSR; /* Select B Register */
- AT91_REG PIOA_ABSR; /* AB Select Status Register */
- AT91_REG Reserved11[ 9 ]; /* */
- AT91_REG PIOA_OWER; /* Output Write Enable Register */
- AT91_REG PIOA_OWDR; /* Output Write Disable Register */
- AT91_REG PIOA_OWSR; /* Output Write Status Register */
- AT91_REG Reserved12[ 85 ]; /* */
- AT91_REG PIOB_PER; /* PIO Enable Register */
- AT91_REG PIOB_PDR; /* PIO Disable Register */
- AT91_REG PIOB_PSR; /* PIO Status Register */
- AT91_REG Reserved13[ 1 ]; /* */
- AT91_REG PIOB_OER; /* Output Enable Register */
- AT91_REG PIOB_ODR; /* Output Disable Registerr */
- AT91_REG PIOB_OSR; /* Output Status Register */
- AT91_REG Reserved14[ 1 ]; /* */
- AT91_REG PIOB_IFER; /* Input Filter Enable Register */
- AT91_REG PIOB_IFDR; /* Input Filter Disable Register */
- AT91_REG PIOB_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved15[ 1 ]; /* */
- AT91_REG PIOB_SODR; /* Set Output Data Register */
- AT91_REG PIOB_CODR; /* Clear Output Data Register */
- AT91_REG PIOB_ODSR; /* Output Data Status Register */
- AT91_REG PIOB_PDSR; /* Pin Data Status Register */
- AT91_REG PIOB_IER; /* Interrupt Enable Register */
- AT91_REG PIOB_IDR; /* Interrupt Disable Register */
- AT91_REG PIOB_IMR; /* Interrupt Mask Register */
- AT91_REG PIOB_ISR; /* Interrupt Status Register */
- AT91_REG PIOB_MDER; /* Multi-driver Enable Register */
- AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIOB_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved16[ 1 ]; /* */
- AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIOB_PPUER; /* Pull-up Enable Register */
- AT91_REG PIOB_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved17[ 1 ]; /* */
- AT91_REG PIOB_ASR; /* Select A Register */
- AT91_REG PIOB_BSR; /* Select B Register */
- AT91_REG PIOB_ABSR; /* AB Select Status Register */
- AT91_REG Reserved18[ 9 ]; /* */
- AT91_REG PIOB_OWER; /* Output Write Enable Register */
- AT91_REG PIOB_OWDR; /* Output Write Disable Register */
- AT91_REG PIOB_OWSR; /* Output Write Status Register */
- AT91_REG Reserved19[ 341 ]; /* */
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved20[ 1 ]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved21[ 1 ]; /* */
- AT91_REG PMC_MOR; /* Main Oscillator Register */
- AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved22[ 1 ]; /* */
- AT91_REG PMC_PLLR; /* PLL Register */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved23[ 3 ]; /* */
- AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */
- AT91_REG Reserved24[ 4 ]; /* */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved25[ 36 ]; /* */
- AT91_REG RSTC_RCR; /* Reset Control Register */
- AT91_REG RSTC_RSR; /* Reset Status Register */
- AT91_REG RSTC_RMR; /* Reset Mode Register */
- AT91_REG Reserved26[ 5 ]; /* */
- AT91_REG RTTC_RTMR; /* Real-time Mode Register */
- AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
- AT91_REG RTTC_RTVR; /* Real-time Value Register */
- AT91_REG RTTC_RTSR; /* Real-time Status Register */
- AT91_REG PITC_PIMR; /* Period Interval Mode Register */
- AT91_REG PITC_PISR; /* Period Interval Status Register */
- AT91_REG PITC_PIVR; /* Period Interval Value Register */
- AT91_REG PITC_PIIR; /* Period Interval Image Register */
- AT91_REG WDTC_WDCR; /* Watchdog Control Register */
- AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
- AT91_REG WDTC_WDSR; /* Watchdog Status Register */
- AT91_REG Reserved27[ 5 ]; /* */
- AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
-} AT91S_SYS, * AT91PS_SYS;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved2[45]; //
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved3[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved4[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved5[54]; //
+ AT91_REG PIOA_PER; // PIO Enable Register
+ AT91_REG PIOA_PDR; // PIO Disable Register
+ AT91_REG PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved6[1]; //
+ AT91_REG PIOA_OER; // Output Enable Register
+ AT91_REG PIOA_ODR; // Output Disable Registerr
+ AT91_REG PIOA_OSR; // Output Status Register
+ AT91_REG Reserved7[1]; //
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved8[1]; //
+ AT91_REG PIOA_SODR; // Set Output Data Register
+ AT91_REG PIOA_CODR; // Clear Output Data Register
+ AT91_REG PIOA_ODSR; // Output Data Status Register
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
+ AT91_REG PIOA_IER; // Interrupt Enable Register
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
+ AT91_REG PIOA_ISR; // Interrupt Status Register
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved9[1]; //
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved10[1]; //
+ AT91_REG PIOA_ASR; // Select A Register
+ AT91_REG PIOA_BSR; // Select B Register
+ AT91_REG PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved11[9]; //
+ AT91_REG PIOA_OWER; // Output Write Enable Register
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
+ AT91_REG PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved12[85]; //
+ AT91_REG PIOB_PER; // PIO Enable Register
+ AT91_REG PIOB_PDR; // PIO Disable Register
+ AT91_REG PIOB_PSR; // PIO Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG PIOB_OER; // Output Enable Register
+ AT91_REG PIOB_ODR; // Output Disable Registerr
+ AT91_REG PIOB_OSR; // Output Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG PIOB_IFER; // Input Filter Enable Register
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register
+ AT91_REG PIOB_IFSR; // Input Filter Status Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG PIOB_SODR; // Set Output Data Register
+ AT91_REG PIOB_CODR; // Clear Output Data Register
+ AT91_REG PIOB_ODSR; // Output Data Status Register
+ AT91_REG PIOB_PDSR; // Pin Data Status Register
+ AT91_REG PIOB_IER; // Interrupt Enable Register
+ AT91_REG PIOB_IDR; // Interrupt Disable Register
+ AT91_REG PIOB_IMR; // Interrupt Mask Register
+ AT91_REG PIOB_ISR; // Interrupt Status Register
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved16[1]; //
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved17[1]; //
+ AT91_REG PIOB_ASR; // Select A Register
+ AT91_REG PIOB_BSR; // Select B Register
+ AT91_REG PIOB_ABSR; // AB Select Status Register
+ AT91_REG Reserved18[9]; //
+ AT91_REG PIOB_OWER; // Output Write Enable Register
+ AT91_REG PIOB_OWDR; // Output Write Disable Register
+ AT91_REG PIOB_OWSR; // Output Write Status Register
+ AT91_REG Reserved19[341]; //
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved20[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved21[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved22[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved23[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved24[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved25[36]; //
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved26[5]; //
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved27[5]; //
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_AIC
-{
- AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
- AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
- AT91_REG AIC_IVR; /* IRQ Vector Register */
- AT91_REG AIC_FVR; /* FIQ Vector Register */
- AT91_REG AIC_ISR; /* Interrupt Status Register */
- AT91_REG AIC_IPR; /* Interrupt Pending Register */
- AT91_REG AIC_IMR; /* Interrupt Mask Register */
- AT91_REG AIC_CISR; /* Core Interrupt Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
- AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
- AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
- AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
- AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
- AT91_REG AIC_SPU; /* Spurious Vector Register */
- AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
- AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
- AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
-} AT91S_AIC, * AT91PS_AIC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
-/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
-#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
-#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */
-#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */
-#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
-/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
-#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
-#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
-/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
-#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
-#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_PDC
-{
- AT91_REG PDC_RPR; /* Receive Pointer Register */
- AT91_REG PDC_RCR; /* Receive Counter Register */
- AT91_REG PDC_TPR; /* Transmit Pointer Register */
- AT91_REG PDC_TCR; /* Transmit Counter Register */
- AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
- AT91_REG PDC_RNCR; /* Receive Next Counter Register */
- AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
- AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
- AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
-} AT91S_PDC, * AT91PS_PDC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/* ***************************************************************************** */
-typedef struct _AT91S_DBGU
-{
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved0[ 7 ]; /* */
- AT91_REG DBGU_CIDR; /* Chip ID Register */
- AT91_REG DBGU_EXID; /* Chip ID Extension Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved1[ 45 ]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
-} AT91S_DBGU, * AT91PS_DBGU;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */
-#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */
-/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */
-#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */
-#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */
-#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */
-#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */
-#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
-#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
-#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
-#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
-#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
-/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
-/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
-#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PIO
-{
- AT91_REG PIO_PER; /* PIO Enable Register */
- AT91_REG PIO_PDR; /* PIO Disable Register */
- AT91_REG PIO_PSR; /* PIO Status Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG PIO_OER; /* Output Enable Register */
- AT91_REG PIO_ODR; /* Output Disable Registerr */
- AT91_REG PIO_OSR; /* Output Status Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG PIO_IFER; /* Input Filter Enable Register */
- AT91_REG PIO_IFDR; /* Input Filter Disable Register */
- AT91_REG PIO_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG PIO_SODR; /* Set Output Data Register */
- AT91_REG PIO_CODR; /* Clear Output Data Register */
- AT91_REG PIO_ODSR; /* Output Data Status Register */
- AT91_REG PIO_PDSR; /* Pin Data Status Register */
- AT91_REG PIO_IER; /* Interrupt Enable Register */
- AT91_REG PIO_IDR; /* Interrupt Disable Register */
- AT91_REG PIO_IMR; /* Interrupt Mask Register */
- AT91_REG PIO_ISR; /* Interrupt Status Register */
- AT91_REG PIO_MDER; /* Multi-driver Enable Register */
- AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIO_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved3[ 1 ]; /* */
- AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIO_PPUER; /* Pull-up Enable Register */
- AT91_REG PIO_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved4[ 1 ]; /* */
- AT91_REG PIO_ASR; /* Select A Register */
- AT91_REG PIO_BSR; /* Select B Register */
- AT91_REG PIO_ABSR; /* AB Select Status Register */
- AT91_REG Reserved5[ 9 ]; /* */
- AT91_REG PIO_OWER; /* Output Write Enable Register */
- AT91_REG PIO_OWDR; /* Output Write Disable Register */
- AT91_REG PIO_OWSR; /* Output Write Status Register */
-} AT91S_PIO, * AT91PS_PIO;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_CKGR
-{
- AT91_REG CKGR_MOR; /* Main Oscillator Register */
- AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG CKGR_PLLR; /* PLL Register */
-} AT91S_CKGR, * AT91PS_CKGR;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG CKGR_PLLR; // PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */
-#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */
-/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */
-#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */
-#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
-#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */
-#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */
-#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */
-#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PMC
-{
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG PMC_MOR; /* Main Oscillator Register */
- AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG PMC_PLLR; /* PLL Register */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved3[ 3 ]; /* */
- AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */
- AT91_REG Reserved4[ 4 ]; /* */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
-} AT91S_PMC, * AT91PS_PMC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved3[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved4[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
-/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
-#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
-/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
-/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
-/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
-/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
-/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
-/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
-#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */
-#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
-/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
-/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
-#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
-/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
-/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Reset Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_RSTC
-{
- AT91_REG RSTC_RCR; /* Reset Control Register */
- AT91_REG RSTC_RSR; /* Reset Status Register */
- AT91_REG RSTC_RMR; /* Reset Mode Register */
-} AT91S_RSTC, * AT91PS_RSTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
-/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
-#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */
-#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */
-#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */
-#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
-/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
-#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */
-#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */
-#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */
-#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occured. */
-#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */
-#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */
-#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occured. */
-#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */
-#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */
-/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
-#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */
-#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_RTTC
-{
- AT91_REG RTTC_RTMR; /* Real-time Mode Register */
- AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
- AT91_REG RTTC_RTVR; /* Real-time Value Register */
- AT91_REG RTTC_RTSR; /* Real-time Status Register */
-} AT91S_RTTC, * AT91PS_RTTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
-/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
-#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
-#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */
-#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */
-#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */
-/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
-#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */
-/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
-#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */
-/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
-#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */
-#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PITC
-{
- AT91_REG PITC_PIMR; /* Period Interval Mode Register */
- AT91_REG PITC_PISR; /* Period Interval Status Register */
- AT91_REG PITC_PIVR; /* Period Interval Value Register */
- AT91_REG PITC_PIIR; /* Period Interval Image Register */
-} AT91S_PITC, * AT91PS_PITC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
-/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
-#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
-#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */
-#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */
-/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
-#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */
-/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
-#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
-#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */
-/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_WDTC
-{
- AT91_REG WDTC_WDCR; /* Watchdog Control Register */
- AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
- AT91_REG WDTC_WDSR; /* Watchdog Status Register */
-} AT91S_WDTC, * AT91PS_WDTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
-/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
-#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */
-#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */
-/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
-#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */
-#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */
-#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */
-#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
-#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */
-#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */
-/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
-#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */
-#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_VREG
-{
- AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
-} AT91S_VREG, * AT91PS_VREG;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
-/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
-#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Memory Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_MC
-{
- AT91_REG MC_RCR; /* MC Remap Control Register */
- AT91_REG MC_ASR; /* MC Abort Status Register */
- AT91_REG MC_AASR; /* MC Abort Address Status Register */
- AT91_REG Reserved0[ 21 ]; /* */
- AT91_REG MC_FMR; /* MC Flash Mode Register */
- AT91_REG MC_FCR; /* MC Flash Command Register */
- AT91_REG MC_FSR; /* MC Flash Status Register */
-} AT91S_MC, * AT91PS_MC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved0[21]; //
+ AT91_REG MC_FMR; // MC Flash Mode Register
+ AT91_REG MC_FCR; // MC Flash Command Register
+ AT91_REG MC_FSR; // MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
-/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
-#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
-/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
-#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
-#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
-#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
-#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */
-#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */
-#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */
-#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */
-#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */
-#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */
-#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */
-#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */
-#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */
-/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
-#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */
-#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */
-#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */
-#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */
-#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */
-#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */
-#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */
-#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
-/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
-#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */
-#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */
-#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
-#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
-#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */
-#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */
-#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */
-#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
-#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
-/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
-#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */
-#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */
-#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */
-#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */
-#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */
-#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */
-#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */
-#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */
-#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SPI
-{
- AT91_REG SPI_CR; /* Control Register */
- AT91_REG SPI_MR; /* Mode Register */
- AT91_REG SPI_RDR; /* Receive Data Register */
- AT91_REG SPI_TDR; /* Transmit Data Register */
- AT91_REG SPI_SR; /* Status Register */
- AT91_REG SPI_IER; /* Interrupt Enable Register */
- AT91_REG SPI_IDR; /* Interrupt Disable Register */
- AT91_REG SPI_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved0[ 4 ]; /* */
- AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */
- AT91_REG Reserved1[ 48 ]; /* */
- AT91_REG SPI_RPR; /* Receive Pointer Register */
- AT91_REG SPI_RCR; /* Receive Counter Register */
- AT91_REG SPI_TPR; /* Transmit Pointer Register */
- AT91_REG SPI_TCR; /* Transmit Counter Register */
- AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
- AT91_REG SPI_RNCR; /* Receive Next Counter Register */
- AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
- AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
- AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
-} AT91S_SPI, * AT91PS_SPI;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */
-#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */
-#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */
-#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */
-#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */
-#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */
-#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Usart */
-/* ***************************************************************************** */
-typedef struct _AT91S_USART
-{
- AT91_REG US_CR; /* Control Register */
- AT91_REG US_MR; /* Mode Register */
- AT91_REG US_IER; /* Interrupt Enable Register */
- AT91_REG US_IDR; /* Interrupt Disable Register */
- AT91_REG US_IMR; /* Interrupt Mask Register */
- AT91_REG US_CSR; /* Channel Status Register */
- AT91_REG US_RHR; /* Receiver Holding Register */
- AT91_REG US_THR; /* Transmitter Holding Register */
- AT91_REG US_BRGR; /* Baud Rate Generator Register */
- AT91_REG US_RTOR; /* Receiver Time-out Register */
- AT91_REG US_TTGR; /* Transmitter Time-guard Register */
- AT91_REG Reserved0[ 5 ]; /* */
- AT91_REG US_FIDI; /* FI_DI_Ratio Register */
- AT91_REG US_NER; /* Nb Errors Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG US_IF; /* IRDA_FILTER Register */
- AT91_REG Reserved2[ 44 ]; /* */
- AT91_REG US_RPR; /* Receive Pointer Register */
- AT91_REG US_RCR; /* Receive Counter Register */
- AT91_REG US_TPR; /* Transmit Pointer Register */
- AT91_REG US_TCR; /* Transmit Counter Register */
- AT91_REG US_RNPR; /* Receive Next Pointer Register */
- AT91_REG US_RNCR; /* Receive Next Counter Register */
- AT91_REG US_TNPR; /* Transmit Next Pointer Register */
- AT91_REG US_TNCR; /* Transmit Next Counter Register */
- AT91_REG US_PTCR; /* PDC Transfer Control Register */
- AT91_REG US_PTSR; /* PDC Transfer Status Register */
-} AT91S_USART, * AT91PS_USART;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
-/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */
-#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
-#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
-#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
-#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
-#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
-#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
-#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
-#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
-#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
-#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
-/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */
-#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */
-#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */
-#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */
-#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */
-#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */
-#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */
-#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */
-#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */
-#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */
-#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */
-#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
-#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
-#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
-#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
-#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
-#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
-#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
-#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
-#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
-#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
-/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */
-#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */
-#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
-#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
-#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
-#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
-#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
-#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
-/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
-#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */
-#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */
-#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */
-#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SSC
-{
- AT91_REG SSC_CR; /* Control Register */
- AT91_REG SSC_CMR; /* Clock Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */
- AT91_REG SSC_RFMR; /* Receive Frame Mode Register */
- AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */
- AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */
- AT91_REG SSC_RHR; /* Receive Holding Register */
- AT91_REG SSC_THR; /* Transmit Holding Register */
- AT91_REG Reserved1[ 2 ]; /* */
- AT91_REG SSC_RSHR; /* Receive Sync Holding Register */
- AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */
- AT91_REG Reserved2[ 2 ]; /* */
- AT91_REG SSC_SR; /* Status Register */
- AT91_REG SSC_IER; /* Interrupt Enable Register */
- AT91_REG SSC_IDR; /* Interrupt Disable Register */
- AT91_REG SSC_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved3[ 44 ]; /* */
- AT91_REG SSC_RPR; /* Receive Pointer Register */
- AT91_REG SSC_RCR; /* Receive Counter Register */
- AT91_REG SSC_TPR; /* Transmit Pointer Register */
- AT91_REG SSC_TCR; /* Transmit Counter Register */
- AT91_REG SSC_RNPR; /* Receive Next Pointer Register */
- AT91_REG SSC_RNCR; /* Receive Next Counter Register */
- AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SSC_TNCR; /* Transmit Next Counter Register */
- AT91_REG SSC_PTCR; /* PDC Transfer Control Register */
- AT91_REG SSC_PTSR; /* PDC Transfer Status Register */
-} AT91S_SSC, * AT91PS_SSC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved3[44]; //
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
-/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
-#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */
-#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */
-#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */
-#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */
-/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
-#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */
-#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */
-#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */
-#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */
-#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */
-#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
-#define AT91C_SSC_CKO_CONTINOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
-#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
-#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */
-#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */
-#define AT91C_SSC_START_CONTINOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
-#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */
-#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */
-#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */
-#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */
-#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */
-#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */
-#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */
-#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */
-#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
-#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
-/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
-#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */
-#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */
-#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */
-#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */
-#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */
-#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */
-#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
-#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
-#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
-#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
-#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
-#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
-#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */
-/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
-/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
-#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */
-#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
-/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
-#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */
-#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */
-#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */
-#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */
-#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */
-#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */
-#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */
-#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */
-#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
-#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
-#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
-/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
-/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TWI
-{
- AT91_REG TWI_CR; /* Control Register */
- AT91_REG TWI_MMR; /* Master Mode Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG TWI_IADR; /* Internal Address Register */
- AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
- AT91_REG Reserved1[ 3 ]; /* */
- AT91_REG TWI_SR; /* Status Register */
- AT91_REG TWI_IER; /* Interrupt Enable Register */
- AT91_REG TWI_IDR; /* Interrupt Disable Register */
- AT91_REG TWI_IMR; /* Interrupt Mask Register */
- AT91_REG TWI_RHR; /* Receive Holding Register */
- AT91_REG TWI_THR; /* Transmit Holding Register */
-} AT91S_TWI, * AT91PS_TWI;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved1[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
-/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
-#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */
-#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */
-#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */
-#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */
-#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
-#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */
-#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */
-#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */
-#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */
-#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */
-#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */
-#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
-#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */
-#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */
-#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
-#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */
-#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */
-#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */
-#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */
-#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */
-#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */
-/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
-/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PWMC_CH
-{
- AT91_REG PWMC_CMR; /* Channel Mode Register */
- AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */
- AT91_REG PWMC_CPRDR; /* Channel Period Register */
- AT91_REG PWMC_CCNTR; /* Channel Counter Register */
- AT91_REG PWMC_CUPDR; /* Channel Update Register */
- AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
-} AT91S_PWMC_CH, * AT91PS_PWMC_CH;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+ AT91_REG PWMC_CMR; // Channel Mode Register
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
+ AT91_REG PWMC_CPRDR; // Channel Period Register
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
+ AT91_REG PWMC_CUPDR; // Channel Update Register
+ AT91_REG PWMC_Reserved[3]; // Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
-#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
-#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */
-#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */
-#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */
-#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
-/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
-#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */
-/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
-#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */
-/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
-#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */
-/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
-#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PWMC
-{
- AT91_REG PWMC_MR; /* PWMC Mode Register */
- AT91_REG PWMC_ENA; /* PWMC Enable Register */
- AT91_REG PWMC_DIS; /* PWMC Disable Register */
- AT91_REG PWMC_SR; /* PWMC Status Register */
- AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */
- AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */
- AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */
- AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */
- AT91_REG Reserved0[ 55 ]; /* */
- AT91_REG PWMC_VR; /* PWMC Version Register */
- AT91_REG Reserved1[ 64 ]; /* */
- AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */
-} AT91S_PWMC, * AT91PS_PWMC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+ AT91_REG PWMC_MR; // PWMC Mode Register
+ AT91_REG PWMC_ENA; // PWMC Enable Register
+ AT91_REG PWMC_DIS; // PWMC Disable Register
+ AT91_REG PWMC_SR; // PWMC Status Register
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
+ AT91_REG Reserved0[55]; //
+ AT91_REG PWMC_VR; // PWMC Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
-/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
-#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */
-#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */
-#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */
-#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
-#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */
-#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */
-/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
-#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
-#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
-#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
-#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
-/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
-/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
-/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
-/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
-/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
-/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR USB Device Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_UDP
-{
- AT91_REG UDP_NUM; /* Frame Number Register */
- AT91_REG UDP_GLBSTATE; /* Global State Register */
- AT91_REG UDP_FADDR; /* Function Address Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG UDP_IER; /* Interrupt Enable Register */
- AT91_REG UDP_IDR; /* Interrupt Disable Register */
- AT91_REG UDP_IMR; /* Interrupt Mask Register */
- AT91_REG UDP_ISR; /* Interrupt Status Register */
- AT91_REG UDP_ICR; /* Interrupt Clear Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG UDP_RSTEP; /* Reset Endpoint Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */
- AT91_REG Reserved3[ 2 ]; /* */
- AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */
- AT91_REG Reserved4[ 3 ]; /* */
- AT91_REG UDP_TXVC; /* Transceiver Control Register */
-} AT91S_UDP, * AT91PS_UDP;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
+ AT91_REG Reserved4[3]; //
+ AT91_REG UDP_TXVC; // Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
-/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
-#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
-#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */
-#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */
-/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
-#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */
-#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */
-#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */
-#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */
-#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */
-/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
-#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */
-#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */
-/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
-#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
-#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */
-#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */
-#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */
-#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */
-#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */
-#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */
-#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */
-#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */
-/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
-/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
-/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
-#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
-/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
-/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
-#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */
-#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */
-#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */
-#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */
-#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */
-#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */
-/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
-#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */
-#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */
-#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */
-#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */
-#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */
-#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
-#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
-#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */
-#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */
-#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */
-#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */
-#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */
-#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */
-#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */
-#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */
-#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */
-#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */
-#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */
-#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
-/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
-#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */
-#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TC
-{
- AT91_REG TC_CCR; /* Channel Control Register */
- AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG TC_CV; /* Counter Value */
- AT91_REG TC_RA; /* Register A */
- AT91_REG TC_RB; /* Register B */
- AT91_REG TC_RC; /* Register C */
- AT91_REG TC_SR; /* Status Register */
- AT91_REG TC_IER; /* Interrupt Enable Register */
- AT91_REG TC_IDR; /* Interrupt Disable Register */
- AT91_REG TC_IMR; /* Interrupt Mask Register */
-} AT91S_TC, * AT91PS_TC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
-/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
-#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */
-#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */
-/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
-#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */
-#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */
-#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */
-#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */
-#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */
-#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */
-#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */
-#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */
-#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */
-#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */
-#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */
-#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */
-#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */
-#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */
-#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */
-#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
-#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
-#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
-#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
-#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
-#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
-#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */
-#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
-#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
-#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
-#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
-#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
-#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
-#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
-#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
-#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
-#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
-#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
-#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
-#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
-#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
-#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
-#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
-#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
-#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
-#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
-#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
-#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
-#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
-#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
-#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
-#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
-#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
-#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
-/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
-#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */
-#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */
-#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */
-#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */
-#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */
-#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */
-#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */
-#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */
-#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
-#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
-#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
-/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
-/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
-/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TCB
-{
- AT91S_TC TCB_TC0; /* TC Channel 0 */
- AT91_REG Reserved0[ 4 ]; /* */
- AT91S_TC TCB_TC1; /* TC Channel 1 */
- AT91_REG Reserved1[ 4 ]; /* */
- AT91S_TC TCB_TC2; /* TC Channel 2 */
- AT91_REG Reserved2[ 4 ]; /* */
- AT91_REG TCB_BCR; /* TC Block Control Register */
- AT91_REG TCB_BMR; /* TC Block Mode Register */
-} AT91S_TCB, * AT91PS_TCB;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
-/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
-#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
-/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
-#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
-#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */
-#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
-#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
-#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
-#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_CAN_MB
-{
- AT91_REG CAN_MB_MMR; /* MailBox Mode Register */
- AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */
- AT91_REG CAN_MB_MID; /* MailBox ID Register */
- AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
- AT91_REG CAN_MB_MSR; /* MailBox Status Register */
- AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */
- AT91_REG CAN_MB_MDH; /* MailBox Data High Register */
- AT91_REG CAN_MB_MCR; /* MailBox Control Register */
-} AT91S_CAN_MB, * AT91PS_CAN_MB;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
+ AT91_REG CAN_MB_MID; // MailBox ID Register
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register
+ AT91_REG CAN_MB_MSR; // MailBox Status Register
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register
+ AT91_REG CAN_MB_MCR; // MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
-/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
-#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */
-#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */
-#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */
-#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */
-/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
-#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
-#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */
-#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */
-/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
-/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
-/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
-#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
-#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */
-#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */
-#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */
-#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */
-#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */
-/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
-/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
-/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
-#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
-#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_CAN
-{
- AT91_REG CAN_MR; /* Mode Register */
- AT91_REG CAN_IER; /* Interrupt Enable Register */
- AT91_REG CAN_IDR; /* Interrupt Disable Register */
- AT91_REG CAN_IMR; /* Interrupt Mask Register */
- AT91_REG CAN_SR; /* Status Register */
- AT91_REG CAN_BR; /* Baudrate Register */
- AT91_REG CAN_TIM; /* Timer Register */
- AT91_REG CAN_TIMESTP; /* Time Stamp Register */
- AT91_REG CAN_ECR; /* Error Counter Register */
- AT91_REG CAN_TCR; /* Transfer Command Register */
- AT91_REG CAN_ACR; /* Abort Command Register */
- AT91_REG Reserved0[ 52 ]; /* */
- AT91_REG CAN_VR; /* Version Register */
- AT91_REG Reserved1[ 64 ]; /* */
- AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */
- AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */
- AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */
- AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */
- AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */
- AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */
- AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */
- AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */
- AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */
- AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */
- AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */
- AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */
- AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */
- AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */
- AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */
- AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */
-} AT91S_CAN, * AT91PS_CAN;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+ AT91_REG CAN_MR; // Mode Register
+ AT91_REG CAN_IER; // Interrupt Enable Register
+ AT91_REG CAN_IDR; // Interrupt Disable Register
+ AT91_REG CAN_IMR; // Interrupt Mask Register
+ AT91_REG CAN_SR; // Status Register
+ AT91_REG CAN_BR; // Baudrate Register
+ AT91_REG CAN_TIM; // Timer Register
+ AT91_REG CAN_TIMESTP; // Time Stamp Register
+ AT91_REG CAN_ECR; // Error Counter Register
+ AT91_REG CAN_TCR; // Transfer Command Register
+ AT91_REG CAN_ACR; // Abort Command Register
+ AT91_REG Reserved0[52]; //
+ AT91_REG CAN_VR; // Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
-/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
-#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */
-#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */
-#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */
-#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */
-#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */
-#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */
-#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */
-#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */
-/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
-#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */
-#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */
-#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */
-#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */
-#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */
-#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */
-#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */
-#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */
-#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */
-#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */
-#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
-#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
-#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
-#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
-#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
-#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
-#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
-#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */
-#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
-#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
-#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */
-#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */
-#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
-#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */
-#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */
-#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */
-#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */
-#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */
-#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */
-/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
-/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
-/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
-#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */
-#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */
-#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */
-/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
-#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */
-#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */
-#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */
-#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */
-#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */
-#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */
-/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
-#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */
-/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
-/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
-#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */
-#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */
-/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
-#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */
-/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
-/* ***************************************************************************** */
-typedef struct _AT91S_EMAC
-{
- AT91_REG EMAC_NCR; /* Network Control Register */
- AT91_REG EMAC_NCFGR; /* Network Configuration Register */
- AT91_REG EMAC_NSR; /* Network Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG EMAC_TSR; /* Transmit Status Register */
- AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
- AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */
- AT91_REG EMAC_RSR; /* Receive Status Register */
- AT91_REG EMAC_ISR; /* Interrupt Status Register */
- AT91_REG EMAC_IER; /* Interrupt Enable Register */
- AT91_REG EMAC_IDR; /* Interrupt Disable Register */
- AT91_REG EMAC_IMR; /* Interrupt Mask Register */
- AT91_REG EMAC_MAN; /* PHY Maintenance Register */
- AT91_REG EMAC_PTR; /* Pause Time Register */
- AT91_REG EMAC_PFR; /* Pause Frames received Register */
- AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */
- AT91_REG EMAC_SCF; /* Single Collision Frame Register */
- AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */
- AT91_REG EMAC_FRO; /* Frames Received OK Register */
- AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */
- AT91_REG EMAC_ALE; /* Alignment Error Register */
- AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */
- AT91_REG EMAC_LCOL; /* Late Collision Register */
- AT91_REG EMAC_ECOL; /* Excessive Collision Register */
- AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
- AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
- AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
- AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
- AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
- AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
- AT91_REG EMAC_RJA; /* Receive Jabbers Register */
- AT91_REG EMAC_USF; /* Undersize Frames Register */
- AT91_REG EMAC_STE; /* SQE Test Error Register */
- AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */
- AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */
- AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */
- AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */
- AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */
- AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */
- AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */
- AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */
- AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */
- AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */
- AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */
- AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */
- AT91_REG EMAC_TID; /* Type ID Checking Register */
- AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */
- AT91_REG EMAC_USRIO; /* USER Input/Output Register */
- AT91_REG EMAC_WOL; /* Wake On LAN Register */
- AT91_REG Reserved1[ 13 ]; /* */
- AT91_REG EMAC_REV; /* Revision Register */
-} AT91S_EMAC, * AT91PS_EMAC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+ AT91_REG EMAC_NCR; // Network Control Register
+ AT91_REG EMAC_NCFGR; // Network Configuration Register
+ AT91_REG EMAC_NSR; // Network Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG EMAC_TSR; // Transmit Status Register
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
+ AT91_REG EMAC_RSR; // Receive Status Register
+ AT91_REG EMAC_ISR; // Interrupt Status Register
+ AT91_REG EMAC_IER; // Interrupt Enable Register
+ AT91_REG EMAC_IDR; // Interrupt Disable Register
+ AT91_REG EMAC_IMR; // Interrupt Mask Register
+ AT91_REG EMAC_MAN; // PHY Maintenance Register
+ AT91_REG EMAC_PTR; // Pause Time Register
+ AT91_REG EMAC_PFR; // Pause Frames received Register
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register
+ AT91_REG EMAC_SCF; // Single Collision Frame Register
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register
+ AT91_REG EMAC_FRO; // Frames Received OK Register
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
+ AT91_REG EMAC_ALE; // Alignment Error Register
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
+ AT91_REG EMAC_LCOL; // Late Collision Register
+ AT91_REG EMAC_ECOL; // Excessive Collision Register
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register
+ AT91_REG EMAC_RJA; // Receive Jabbers Register
+ AT91_REG EMAC_USF; // Undersize Frames Register
+ AT91_REG EMAC_STE; // SQE Test Error Register
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
+ AT91_REG EMAC_TID; // Type ID Checking Register
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
+ AT91_REG EMAC_USRIO; // USER Input/Output Register
+ AT91_REG EMAC_WOL; // Wake On LAN Register
+ AT91_REG Reserved1[13]; //
+ AT91_REG EMAC_REV; // Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
-/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */
-#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */
-#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */
-#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */
-#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */
-#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
-/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
-#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */
-#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */
-#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
-#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
-#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
-#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */
-#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
-/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
-#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
-#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */
-#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */
-#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
-/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
-#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */
-#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */
-#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
-#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */
-#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */
-#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */
-#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
-/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */
-#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */
-#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */
-#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */
-#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */
-/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
-#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */
-/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
-#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */
-#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */
-#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */
-#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */
-/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
-#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */
+// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
-/* ***************************************************************************** */
-typedef struct _AT91S_ADC
-{
- AT91_REG ADC_CR; /* ADC Control Register */
- AT91_REG ADC_MR; /* ADC Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG ADC_CHER; /* ADC Channel Enable Register */
- AT91_REG ADC_CHDR; /* ADC Channel Disable Register */
- AT91_REG ADC_CHSR; /* ADC Channel Status Register */
- AT91_REG ADC_SR; /* ADC Status Register */
- AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */
- AT91_REG ADC_IER; /* ADC Interrupt Enable Register */
- AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */
- AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */
- AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */
- AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */
- AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */
- AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */
- AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */
- AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */
- AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */
- AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */
- AT91_REG Reserved1[ 44 ]; /* */
- AT91_REG ADC_RPR; /* Receive Pointer Register */
- AT91_REG ADC_RCR; /* Receive Counter Register */
- AT91_REG ADC_TPR; /* Transmit Pointer Register */
- AT91_REG ADC_TCR; /* Transmit Counter Register */
- AT91_REG ADC_RNPR; /* Receive Next Pointer Register */
- AT91_REG ADC_RNCR; /* Receive Next Counter Register */
- AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG ADC_TNCR; /* Transmit Next Counter Register */
- AT91_REG ADC_PTCR; /* PDC Transfer Control Register */
- AT91_REG ADC_PTSR; /* PDC Transfer Status Register */
-} AT91S_ADC, * AT91PS_ADC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+ AT91_REG ADC_CR; // ADC Control Register
+ AT91_REG ADC_MR; // ADC Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
+ AT91_REG ADC_SR; // ADC Status Register
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
+ AT91_REG Reserved1[44]; //
+ AT91_REG ADC_RPR; // Receive Pointer Register
+ AT91_REG ADC_RCR; // Receive Counter Register
+ AT91_REG ADC_TPR; // Transmit Pointer Register
+ AT91_REG ADC_TCR; // Transmit Counter Register
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
-/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
-#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */
-#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */
-/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
-#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */
-#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software */
-#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
-#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */
-#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */
-#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */
-#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */
-#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */
-#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */
-#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */
-#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */
-#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */
-#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */
-#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */
-#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */
-#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */
-#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
-#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */
-/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
-#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */
-#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */
-#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */
-#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */
-#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */
-#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */
-#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */
-#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */
-/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
-/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
-/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
-#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */
-#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */
-#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */
-#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */
-/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
-#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
-/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
-/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
-/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
-/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
-#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */
-/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
-/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
-/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
-/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
-/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
-/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
-/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
-/* ***************************************************************************** */
-typedef struct _AT91S_AES
-{
- AT91_REG AES_CR; /* Control Register */
- AT91_REG AES_MR; /* Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AES_IER; /* Interrupt Enable Register */
- AT91_REG AES_IDR; /* Interrupt Disable Register */
- AT91_REG AES_IMR; /* Interrupt Mask Register */
- AT91_REG AES_ISR; /* Interrupt Status Register */
- AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */
- AT91_REG Reserved1[ 4 ]; /* */
- AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */
- AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */
- AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */
- AT91_REG Reserved2[ 35 ]; /* */
- AT91_REG AES_VR; /* AES Version Register */
- AT91_REG AES_RPR; /* Receive Pointer Register */
- AT91_REG AES_RCR; /* Receive Counter Register */
- AT91_REG AES_TPR; /* Transmit Pointer Register */
- AT91_REG AES_TCR; /* Transmit Counter Register */
- AT91_REG AES_RNPR; /* Receive Next Pointer Register */
- AT91_REG AES_RNCR; /* Receive Next Counter Register */
- AT91_REG AES_TNPR; /* Transmit Next Pointer Register */
- AT91_REG AES_TNCR; /* Transmit Next Counter Register */
- AT91_REG AES_PTCR; /* PDC Transfer Control Register */
- AT91_REG AES_PTSR; /* PDC Transfer Status Register */
-} AT91S_AES, * AT91PS_AES;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+ AT91_REG AES_CR; // Control Register
+ AT91_REG AES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AES_IER; // Interrupt Enable Register
+ AT91_REG AES_IDR; // Interrupt Disable Register
+ AT91_REG AES_IMR; // Interrupt Mask Register
+ AT91_REG AES_ISR; // Interrupt Status Register
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register
+ AT91_REG Reserved1[4]; //
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register
+ AT91_REG Reserved2[35]; //
+ AT91_REG AES_VR; // AES Version Register
+ AT91_REG AES_RPR; // Receive Pointer Register
+ AT91_REG AES_RCR; // Receive Counter Register
+ AT91_REG AES_TPR; // Transmit Pointer Register
+ AT91_REG AES_TCR; // Transmit Counter Register
+ AT91_REG AES_RNPR; // Receive Next Pointer Register
+ AT91_REG AES_RNCR; // Receive Next Counter Register
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register
+ AT91_REG AES_TNCR; // Transmit Next Counter Register
+ AT91_REG AES_PTCR; // PDC Transfer Control Register
+ AT91_REG AES_PTSR; // PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
-/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
-#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */
-#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */
-#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */
-/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
-#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */
-#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */
-#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */
-#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
-#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
-#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */
-#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */
-#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */
-#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */
-#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */
-#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */
-#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */
-#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */
-#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */
-#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */
-#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */
-#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */
-#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */
-#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */
-#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */
-#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */
-#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */
-#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */
-#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */
-#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */
-#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
-/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */
-#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */
-#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */
-#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */
-#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */
-#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */
-/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
-#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
-#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
-#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
-#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
-#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
-#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */
+// -------- AES_CR : (AES Offset: 0x0) Control Register --------
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
-/* ***************************************************************************** */
-typedef struct _AT91S_TDES
-{
- AT91_REG TDES_CR; /* Control Register */
- AT91_REG TDES_MR; /* Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG TDES_IER; /* Interrupt Enable Register */
- AT91_REG TDES_IDR; /* Interrupt Disable Register */
- AT91_REG TDES_IMR; /* Interrupt Mask Register */
- AT91_REG TDES_ISR; /* Interrupt Status Register */
- AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */
- AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */
- AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */
- AT91_REG Reserved1[ 2 ]; /* */
- AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */
- AT91_REG Reserved2[ 2 ]; /* */
- AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */
- AT91_REG Reserved3[ 2 ]; /* */
- AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */
- AT91_REG Reserved4[ 37 ]; /* */
- AT91_REG TDES_VR; /* TDES Version Register */
- AT91_REG TDES_RPR; /* Receive Pointer Register */
- AT91_REG TDES_RCR; /* Receive Counter Register */
- AT91_REG TDES_TPR; /* Transmit Pointer Register */
- AT91_REG TDES_TCR; /* Transmit Counter Register */
- AT91_REG TDES_RNPR; /* Receive Next Pointer Register */
- AT91_REG TDES_RNCR; /* Receive Next Counter Register */
- AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */
- AT91_REG TDES_TNCR; /* Transmit Next Counter Register */
- AT91_REG TDES_PTCR; /* PDC Transfer Control Register */
- AT91_REG TDES_PTSR; /* PDC Transfer Status Register */
-} AT91S_TDES, * AT91PS_TDES;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+ AT91_REG TDES_CR; // Control Register
+ AT91_REG TDES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG TDES_IER; // Interrupt Enable Register
+ AT91_REG TDES_IDR; // Interrupt Disable Register
+ AT91_REG TDES_IMR; // Interrupt Mask Register
+ AT91_REG TDES_ISR; // Interrupt Status Register
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
+ AT91_REG Reserved4[37]; //
+ AT91_REG TDES_VR; // TDES Version Register
+ AT91_REG TDES_RPR; // Receive Pointer Register
+ AT91_REG TDES_RCR; // Receive Counter Register
+ AT91_REG TDES_TPR; // Transmit Pointer Register
+ AT91_REG TDES_TCR; // Transmit Counter Register
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register
+ AT91_REG TDES_RNCR; // Receive Next Counter Register
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
-/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
-#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */
-#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */
-/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
-#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */
-#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */
-#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */
-#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */
-#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
-#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
-#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */
-#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */
-#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
-#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
-#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
-#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
-#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */
-#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
-#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */
-#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */
-#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */
-#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */
-/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */
-#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */
-#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */
-#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */
-#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */
-#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */
-/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
-#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
-#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
-#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
-#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-/* ***************************************************************************** */
-/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 */
-/* ***************************************************************************** */
-/* ========== Register definition for SYS peripheral ========== */
-/* ========== Register definition for AIC peripheral ========== */
-#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
-#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
-#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
-#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
-#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
-#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
-#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
-#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
-#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
-#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
-#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
-#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
-#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
-#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
-#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
-#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
-#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
-#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
-/* ========== Register definition for PDC_DBGU peripheral ========== */
-#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
-#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
-#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
-#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
-#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
-#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
-#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
-#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
-#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
-#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
-/* ========== Register definition for DBGU peripheral ========== */
-#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
-#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
-#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
-#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
-#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */
-#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
-#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
-#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
-#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
-#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
-#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
-#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
-/* ========== Register definition for PIOA peripheral ========== */
-#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
-#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
-#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
-#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
-#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
-#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
-#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
-#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
-#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
-#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
-#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
-#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
-#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
-#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
-#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
-#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
-#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
-#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
-#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
-#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
-#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
-#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
-#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
-#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
-#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
-#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
-#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
-/* ========== Register definition for PIOB peripheral ========== */
-#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
-#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
-#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
-#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
-#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */
-#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
-#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */
-#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
-#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
-#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
-#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
-#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
-#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
-#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
-#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
-#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
-#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
-#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
-#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
-#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
-#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
-#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */
-#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
-#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
-#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */
-#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
-#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */
-#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
-/* ========== Register definition for CKGR peripheral ========== */
-#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
-#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
-#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */
-/* ========== Register definition for PMC peripheral ========== */
-#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
-#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
-#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
-#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
-#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
-#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
-#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
-#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
-#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
-#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */
-#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
-#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
-#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
-#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
-/* ========== Register definition for RSTC peripheral ========== */
-#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
-#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
-#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
-/* ========== Register definition for RTTC peripheral ========== */
-#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
-#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
-#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
-#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
-/* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
-#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
-#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
-#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
-/* ========== Register definition for WDTC peripheral ========== */
-#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
-#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
-#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
-/* ========== Register definition for VREG peripheral ========== */
-#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
-/* ========== Register definition for MC peripheral ========== */
-#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
-#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
-#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
-#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
-#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
-#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
-/* ========== Register definition for PDC_SPI1 peripheral ========== */
-#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
-#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
-#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
-#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
-#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
-#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
-#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
-#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
-#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
-#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
-/* ========== Register definition for SPI1 peripheral ========== */
-#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
-#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
-#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */
-#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */
-#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
-#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */
-#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */
-#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */
-#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */
-/* ========== Register definition for PDC_SPI0 peripheral ========== */
-#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
-#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
-#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
-#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
-#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
-#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
-#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
-#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
-#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
-#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
-/* ========== Register definition for SPI0 peripheral ========== */
-#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
-#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */
-#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
-#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */
-#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */
-#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
-#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */
-#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */
-#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */
-/* ========== Register definition for PDC_US1 peripheral ========== */
-#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
-#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
-#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
-#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
-#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
-#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
-#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
-#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
-#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
-#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
-/* ========== Register definition for US1 peripheral ========== */
-#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
-#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
-#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
-#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
-#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
-#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
-#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
-#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
-#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
-#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
-#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
-#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
-#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
-#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
-/* ========== Register definition for PDC_US0 peripheral ========== */
-#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
-#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
-#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
-#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
-#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
-#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
-#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
-#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
-#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
-#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
-/* ========== Register definition for US0 peripheral ========== */
-#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
-#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
-#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
-#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
-#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
-#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
-#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
-#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
-#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
-#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
-#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
-#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
-#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
-#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
-/* ========== Register definition for PDC_SSC peripheral ========== */
-#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
-#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
-#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
-#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
-#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
-#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
-#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
-#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
-#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
-#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
-/* ========== Register definition for SSC peripheral ========== */
-#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
-#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
-#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
-#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
-#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
-#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
-#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
-#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
-#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
-#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
-#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
-#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
-#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
-#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
-/* ========== Register definition for TWI peripheral ========== */
-#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
-#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
-#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
-#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
-#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
-#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
-#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
-#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
-#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
-#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
-/* ========== Register definition for PWMC_CH3 peripheral ========== */
-#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
-#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
-#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
-#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
-#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
-/* ========== Register definition for PWMC_CH2 peripheral ========== */
-#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
-#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
-#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
-#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
-#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
-#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH1 peripheral ========== */
-#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
-#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
-#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
-#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
-#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
-/* ========== Register definition for PWMC_CH0 peripheral ========== */
-#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
-#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
-#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
-#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
-#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
-/* ========== Register definition for PWMC peripheral ========== */
-#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
-#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
-#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
-#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
-#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
-#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
-#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
-#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
-#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
-/* ========== Register definition for UDP peripheral ========== */
-#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
-#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
-#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
-#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
-#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
-#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
-#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
-#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
-#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
-#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
-#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
-#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
-/* ========== Register definition for TC0 peripheral ========== */
-#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
-#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
-#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
-#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
-#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
-#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
-#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
-#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
-#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
-/* ========== Register definition for TC1 peripheral ========== */
-#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
-#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
-#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
-#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
-#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
-#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
-#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
-#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
-#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
-/* ========== Register definition for TC2 peripheral ========== */
-#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
-#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
-#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
-#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
-#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
-#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
-#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
-#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
-#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
-/* ========== Register definition for TCB peripheral ========== */
-#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
-#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
-/* ========== Register definition for CAN_MB0 peripheral ========== */
-#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
-#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
-#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
-#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
-#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
-#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
-#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
-/* ========== Register definition for CAN_MB1 peripheral ========== */
-#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
-#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
-#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
-#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
-#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
-#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
-#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
-/* ========== Register definition for CAN_MB2 peripheral ========== */
-#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
-#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
-#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
-#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
-#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
-#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
-#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
-/* ========== Register definition for CAN_MB3 peripheral ========== */
-#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
-#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
-#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
-#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
-#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
-#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
-#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
-/* ========== Register definition for CAN_MB4 peripheral ========== */
-#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
-#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
-#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
-#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
-#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
-#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
-#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
-#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB5 peripheral ========== */
-#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
-#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
-#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
-#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
-#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
-#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
-#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
-#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB6 peripheral ========== */
-#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
-#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
-#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
-#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
-#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
-#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
-#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
-/* ========== Register definition for CAN_MB7 peripheral ========== */
-#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
-#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
-#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
-#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
-#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
-#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
-#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
-/* ========== Register definition for CAN peripheral ========== */
-#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */
-#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
-#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
-#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */
-#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */
-#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */
-#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
-#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */
-#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */
-#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */
-#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */
-#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */
-/* ========== Register definition for EMAC peripheral ========== */
-#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
-#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
-#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
-#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
-#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */
-#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
-#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
-#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
-#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
-#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */
-#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
-#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */
-#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
-#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
-#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
-#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
-#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
-#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
-#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
-#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
-#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
-#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */
-#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
-#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
-#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
-#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
-#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
-#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
-#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
-#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
-#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
-#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
-#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
-#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
-#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
-#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */
-#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
-#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
-#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
-#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
-#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */
-#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
-#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
-#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
-#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
-#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
-#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
-#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
-/* ========== Register definition for PDC_ADC peripheral ========== */
-#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
-#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
-#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
-#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
-#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
-#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
-#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
-#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
-#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
-#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
-/* ========== Register definition for ADC peripheral ========== */
-#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
-#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
-#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
-#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
-#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
-#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
-#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
-#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
-#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
-#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
-#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
-#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
-#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
-#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
-#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
-#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
-#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
-#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
-/* ========== Register definition for PDC_AES peripheral ========== */
-#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
-#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
-#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
-#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
-#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
-#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
-#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
-#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
-#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
-#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
-/* ========== Register definition for AES peripheral ========== */
-#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
-#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */
-#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */
-#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */
-#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */
-#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */
-#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
-#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
-#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
-#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */
-#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */
-/* ========== Register definition for PDC_TDES peripheral ========== */
-#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
-#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
-#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
-#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
-#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
-#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
-#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
-#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
-#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
-#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
-/* ========== Register definition for TDES peripheral ========== */
-#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
-#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
-#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
-#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */
-#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
-#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */
-#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
-#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */
-#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */
-#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
-#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */
-#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */
-#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ==========
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ==========
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ==========
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ==========
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ==========
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ==========
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ==========
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ==========
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ==========
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ==========
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ==========
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ==========
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ==========
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ==========
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ==========
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ==========
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ==========
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ==========
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
-/* ***************************************************************************** */
-/* PIO DEFINITIONS FOR AT91SAM7X128 */
-/* ***************************************************************************** */
-#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */
-#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */
-#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */
-#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */
-#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */
-#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */
-#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */
-#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */
-#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */
-#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */
-#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */
-#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */
-#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */
-#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */
-#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */
-#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */
-#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */
-#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */
-#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */
-#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */
-#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */
-#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */
-#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */
-#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */
-#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */
-#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */
-#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */
-#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */
-#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */
-#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */
-#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */
-#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */
-#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */
-#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */
-#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */
-#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */
-#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */
-#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */
-#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */
-#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */
-#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */
-#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */
-#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */
-#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */
-#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */
-#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */
-#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */
-#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */
-#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */
-#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */
-#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */
-#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */
-#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */
-#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */
-#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */
-#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */
-#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */
-#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */
-#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */
-#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */
-#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */
-#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */
-#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */
-#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */
-#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */
-#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */
-#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */
-#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */
-#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */
-#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */
-#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */
-#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */
-#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */
-#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */
-#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */
-#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */
-#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */
-#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */
-#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */
-#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */
-#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */
-#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */
-#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */
-#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */
-#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */
-#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */
-#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */
-#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */
-#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */
-#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */
-#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */
-#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */
-#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */
-#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */
-#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */
-#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */
-#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */
-#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */
-#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */
-#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */
-#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */
-#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */
-#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */
-#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */
-#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */
-#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */
-#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */
-#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */
-#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */
-#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */
-#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */
-#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */
-#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */
-#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */
-#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */
-#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */
-#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */
-#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */
-#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */
-#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */
-#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */
-#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */
-#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */
-#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */
-#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-/* ***************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 */
-/* ***************************************************************************** */
-#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */
-#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */
-#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */
-#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */
-#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */
-#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */
-#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */
-#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */
-#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */
-#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */
-#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */
-#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */
-#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */
-#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */
-#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */
-#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */
-#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */
-#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */
-#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */
-#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */
-#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */
-#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */
-#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */
-#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */
-#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */
-#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */
-#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */
-#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */
-#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */
-#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-/* ***************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 */
-/* ***************************************************************************** */
-#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */
-#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */
-#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */
-#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */
-#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */
-#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */
-#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */
-#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */
-#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */
-#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */
-#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */
-#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */
-#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */
-#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */
-#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */
-#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */
-#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */
-#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */
-#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */
-#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */
-#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */
-#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */
-#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */
-#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */
-#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */
-#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
-#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
-#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
-#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
-#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */
-#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */
-#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */
-#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */
-#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */
-#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */
-#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */
-#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */
-#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */
-#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */
-#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */
-#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */
-#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */
-#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */
-#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */
-#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */
-#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */
-#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */
-#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */
-#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */
-#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */
-#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
-/* ***************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 */
-/* ***************************************************************************** */
-#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */
-#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00008000 ) /* Internal SRAM size in byte (32 Kbyte) */
-#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */
-#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00020000 ) /* Internal ROM size in byte (128 Kbyte) */
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
-#endif /* ifndef AT91SAM7X128_H */
+#endif
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
index b9f2eff..96b680a 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
@@ -1,2444 +1,2446 @@
-/* ---------------------------------------------------------------------------- */
-/* ATMEL Microcontroller Software Support - ROUSSET - */
-/* ---------------------------------------------------------------------------- */
-/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* ---------------------------------------------------------------------------- */
-/* File Name : AT91SAM7X128.h */
-/* Object : AT91SAM7X128 definitions */
-/* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) */
-/* */
-/* CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// */
-/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */
-/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
-/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */
-/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */
-/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
-/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
-/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
-/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */
-/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */
-/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */
-/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */
-/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */
-/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */
-/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
-/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
-/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
-/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
-/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
-/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
-/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */
-/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */
-/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
-/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */
-/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
-/* ---------------------------------------------------------------------------- */
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM7X128.h
+// Object : AT91SAM7X128 definitions
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:23)
+//
+// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// ----------------------------------------------------------------------------
-/* Hardware register definition */
+// Hardware register definition
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR System Peripherals */
-/* ***************************************************************************** */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_AIC structure *** */
-#define AIC_SMR ( 0 ) /* Source Mode Register */
-#define AIC_SVR ( 128 ) /* Source Vector Register */
-#define AIC_IVR ( 256 ) /* IRQ Vector Register */
-#define AIC_FVR ( 260 ) /* FIQ Vector Register */
-#define AIC_ISR ( 264 ) /* Interrupt Status Register */
-#define AIC_IPR ( 268 ) /* Interrupt Pending Register */
-#define AIC_IMR ( 272 ) /* Interrupt Mask Register */
-#define AIC_CISR ( 276 ) /* Core Interrupt Status Register */
-#define AIC_IECR ( 288 ) /* Interrupt Enable Command Register */
-#define AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */
-#define AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */
-#define AIC_ISCR ( 300 ) /* Interrupt Set Command Register */
-#define AIC_EOICR ( 304 ) /* End of Interrupt Command Register */
-#define AIC_SPU ( 308 ) /* Spurious Vector Register */
-#define AIC_DCR ( 312 ) /* Debug Control Register (Protect) */
-#define AIC_FFER ( 320 ) /* Fast Forcing Enable Register */
-#define AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */
-#define AIC_FFSR ( 328 ) /* Fast Forcing Status Register */
-/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
-#define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */
-#define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */
-#define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */
-#define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
-/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
-#define AT91C_AIC_NFIQ ( 0x1 << 0 ) /* (AIC) NFIQ Status */
-#define AT91C_AIC_NIRQ ( 0x1 << 1 ) /* (AIC) NIRQ Status */
-/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
-#define AT91C_AIC_DCR_PROT ( 0x1 << 0 ) /* (AIC) Protection Mode */
-#define AT91C_AIC_DCR_GMSK ( 0x1 << 1 ) /* (AIC) General Mask */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+// *** Register offset in AT91S_AIC structure ***
+#define AIC_SMR ( 0) // Source Mode Register
+#define AIC_SVR (128) // Source Vector Register
+#define AIC_IVR (256) // IRQ Vector Register
+#define AIC_FVR (260) // FIQ Vector Register
+#define AIC_ISR (264) // Interrupt Status Register
+#define AIC_IPR (268) // Interrupt Pending Register
+#define AIC_IMR (272) // Interrupt Mask Register
+#define AIC_CISR (276) // Core Interrupt Status Register
+#define AIC_IECR (288) // Interrupt Enable Command Register
+#define AIC_IDCR (292) // Interrupt Disable Command Register
+#define AIC_ICCR (296) // Interrupt Clear Command Register
+#define AIC_ISCR (300) // Interrupt Set Command Register
+#define AIC_EOICR (304) // End of Interrupt Command Register
+#define AIC_SPU (308) // Spurious Vector Register
+#define AIC_DCR (312) // Debug Control Register (Protect)
+#define AIC_FFER (320) // Fast Forcing Enable Register
+#define AIC_FFDR (324) // Fast Forcing Disable Register
+#define AIC_FFSR (328) // Fast Forcing Status Register
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PDC structure *** */
-#define PDC_RPR ( 0 ) /* Receive Pointer Register */
-#define PDC_RCR ( 4 ) /* Receive Counter Register */
-#define PDC_TPR ( 8 ) /* Transmit Pointer Register */
-#define PDC_TCR ( 12 ) /* Transmit Counter Register */
-#define PDC_RNPR ( 16 ) /* Receive Next Pointer Register */
-#define PDC_RNCR ( 20 ) /* Receive Next Counter Register */
-#define PDC_TNPR ( 24 ) /* Transmit Next Pointer Register */
-#define PDC_TNCR ( 28 ) /* Transmit Next Counter Register */
-#define PDC_PTCR ( 32 ) /* PDC Transfer Control Register */
-#define PDC_PTSR ( 36 ) /* PDC Transfer Status Register */
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+// *** Register offset in AT91S_PDC structure ***
+#define PDC_RPR ( 0) // Receive Pointer Register
+#define PDC_RCR ( 4) // Receive Counter Register
+#define PDC_TPR ( 8) // Transmit Pointer Register
+#define PDC_TCR (12) // Transmit Counter Register
+#define PDC_RNPR (16) // Receive Next Pointer Register
+#define PDC_RNCR (20) // Receive Next Counter Register
+#define PDC_TNPR (24) // Transmit Next Pointer Register
+#define PDC_TNCR (28) // Transmit Next Counter Register
+#define PDC_PTCR (32) // PDC Transfer Control Register
+#define PDC_PTSR (36) // PDC Transfer Status Register
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_DBGU structure *** */
-#define DBGU_CR ( 0 ) /* Control Register */
-#define DBGU_MR ( 4 ) /* Mode Register */
-#define DBGU_IER ( 8 ) /* Interrupt Enable Register */
-#define DBGU_IDR ( 12 ) /* Interrupt Disable Register */
-#define DBGU_IMR ( 16 ) /* Interrupt Mask Register */
-#define DBGU_CSR ( 20 ) /* Channel Status Register */
-#define DBGU_RHR ( 24 ) /* Receiver Holding Register */
-#define DBGU_THR ( 28 ) /* Transmitter Holding Register */
-#define DBGU_BRGR ( 32 ) /* Baud Rate Generator Register */
-#define DBGU_CIDR ( 64 ) /* Chip ID Register */
-#define DBGU_EXID ( 68 ) /* Chip ID Extension Register */
-#define DBGU_FNTR ( 72 ) /* Force NTRST Register */
-#define DBGU_RPR ( 256 ) /* Receive Pointer Register */
-#define DBGU_RCR ( 260 ) /* Receive Counter Register */
-#define DBGU_TPR ( 264 ) /* Transmit Pointer Register */
-#define DBGU_TCR ( 268 ) /* Transmit Counter Register */
-#define DBGU_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define DBGU_RNCR ( 276 ) /* Receive Next Counter Register */
-#define DBGU_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define DBGU_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define DBGU_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define DBGU_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ( 0x1 << 2 ) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ( 0x1 << 3 ) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ( 0x1 << 4 ) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ( 0x1 << 6 ) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ( 0x1 << 7 ) /* (DBGU) Transmitter Disable */
-#define AT91C_US_RSTSTA ( 0x1 << 8 ) /* (DBGU) Reset Status Bits */
-/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_PAR ( 0x7 << 9 ) /* (DBGU) Parity type */
-#define AT91C_US_PAR_EVEN ( 0x0 << 9 ) /* (DBGU) Even Parity */
-#define AT91C_US_PAR_ODD ( 0x1 << 9 ) /* (DBGU) Odd Parity */
-#define AT91C_US_PAR_SPACE ( 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK ( 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE ( 0x4 << 9 ) /* (DBGU) No Parity */
-#define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9 ) /* (DBGU) Multi-drop mode */
-#define AT91C_US_CHMODE ( 0x3 << 14 ) /* (DBGU) Channel Mode */
-#define AT91C_US_CHMODE_NORMAL ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
-#define AT91C_US_CHMODE_AUTO ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
-#define AT91C_US_CHMODE_LOCAL ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
-#define AT91C_US_CHMODE_REMOTE ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ( 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ( 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ( 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ( 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ( 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ( 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ( 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
-/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
-/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
-#define AT91C_US_FORCE_NTRST ( 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+// *** Register offset in AT91S_DBGU structure ***
+#define DBGU_CR ( 0) // Control Register
+#define DBGU_MR ( 4) // Mode Register
+#define DBGU_IER ( 8) // Interrupt Enable Register
+#define DBGU_IDR (12) // Interrupt Disable Register
+#define DBGU_IMR (16) // Interrupt Mask Register
+#define DBGU_CSR (20) // Channel Status Register
+#define DBGU_RHR (24) // Receiver Holding Register
+#define DBGU_THR (28) // Transmitter Holding Register
+#define DBGU_BRGR (32) // Baud Rate Generator Register
+#define DBGU_CIDR (64) // Chip ID Register
+#define DBGU_EXID (68) // Chip ID Extension Register
+#define DBGU_FNTR (72) // Force NTRST Register
+#define DBGU_RPR (256) // Receive Pointer Register
+#define DBGU_RCR (260) // Receive Counter Register
+#define DBGU_TPR (264) // Transmit Pointer Register
+#define DBGU_TCR (268) // Transmit Counter Register
+#define DBGU_RNPR (272) // Receive Next Pointer Register
+#define DBGU_RNCR (276) // Receive Next Counter Register
+#define DBGU_TNPR (280) // Transmit Next Pointer Register
+#define DBGU_TNCR (284) // Transmit Next Counter Register
+#define DBGU_PTCR (288) // PDC Transfer Control Register
+#define DBGU_PTSR (292) // PDC Transfer Status Register
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PIO structure *** */
-#define PIO_PER ( 0 ) /* PIO Enable Register */
-#define PIO_PDR ( 4 ) /* PIO Disable Register */
-#define PIO_PSR ( 8 ) /* PIO Status Register */
-#define PIO_OER ( 16 ) /* Output Enable Register */
-#define PIO_ODR ( 20 ) /* Output Disable Registerr */
-#define PIO_OSR ( 24 ) /* Output Status Register */
-#define PIO_IFER ( 32 ) /* Input Filter Enable Register */
-#define PIO_IFDR ( 36 ) /* Input Filter Disable Register */
-#define PIO_IFSR ( 40 ) /* Input Filter Status Register */
-#define PIO_SODR ( 48 ) /* Set Output Data Register */
-#define PIO_CODR ( 52 ) /* Clear Output Data Register */
-#define PIO_ODSR ( 56 ) /* Output Data Status Register */
-#define PIO_PDSR ( 60 ) /* Pin Data Status Register */
-#define PIO_IER ( 64 ) /* Interrupt Enable Register */
-#define PIO_IDR ( 68 ) /* Interrupt Disable Register */
-#define PIO_IMR ( 72 ) /* Interrupt Mask Register */
-#define PIO_ISR ( 76 ) /* Interrupt Status Register */
-#define PIO_MDER ( 80 ) /* Multi-driver Enable Register */
-#define PIO_MDDR ( 84 ) /* Multi-driver Disable Register */
-#define PIO_MDSR ( 88 ) /* Multi-driver Status Register */
-#define PIO_PPUDR ( 96 ) /* Pull-up Disable Register */
-#define PIO_PPUER ( 100 ) /* Pull-up Enable Register */
-#define PIO_PPUSR ( 104 ) /* Pull-up Status Register */
-#define PIO_ASR ( 112 ) /* Select A Register */
-#define PIO_BSR ( 116 ) /* Select B Register */
-#define PIO_ABSR ( 120 ) /* AB Select Status Register */
-#define PIO_OWER ( 160 ) /* Output Write Enable Register */
-#define PIO_OWDR ( 164 ) /* Output Write Disable Register */
-#define PIO_OWSR ( 168 ) /* Output Write Status Register */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PIO structure ***
+#define PIO_PER ( 0) // PIO Enable Register
+#define PIO_PDR ( 4) // PIO Disable Register
+#define PIO_PSR ( 8) // PIO Status Register
+#define PIO_OER (16) // Output Enable Register
+#define PIO_ODR (20) // Output Disable Registerr
+#define PIO_OSR (24) // Output Status Register
+#define PIO_IFER (32) // Input Filter Enable Register
+#define PIO_IFDR (36) // Input Filter Disable Register
+#define PIO_IFSR (40) // Input Filter Status Register
+#define PIO_SODR (48) // Set Output Data Register
+#define PIO_CODR (52) // Clear Output Data Register
+#define PIO_ODSR (56) // Output Data Status Register
+#define PIO_PDSR (60) // Pin Data Status Register
+#define PIO_IER (64) // Interrupt Enable Register
+#define PIO_IDR (68) // Interrupt Disable Register
+#define PIO_IMR (72) // Interrupt Mask Register
+#define PIO_ISR (76) // Interrupt Status Register
+#define PIO_MDER (80) // Multi-driver Enable Register
+#define PIO_MDDR (84) // Multi-driver Disable Register
+#define PIO_MDSR (88) // Multi-driver Status Register
+#define PIO_PPUDR (96) // Pull-up Disable Register
+#define PIO_PPUER (100) // Pull-up Enable Register
+#define PIO_PPUSR (104) // Pull-up Status Register
+#define PIO_ASR (112) // Select A Register
+#define PIO_BSR (116) // Select B Register
+#define PIO_ABSR (120) // AB Select Status Register
+#define PIO_OWER (160) // Output Write Enable Register
+#define PIO_OWDR (164) // Output Write Disable Register
+#define PIO_OWSR (168) // Output Write Status Register
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_CKGR structure *** */
-#define CKGR_MOR ( 0 ) /* Main Oscillator Register */
-#define CKGR_MCFR ( 4 ) /* Main Clock Frequency Register */
-#define CKGR_PLLR ( 12 ) /* PLL Register */
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN ( 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCBYPASS ( 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */
-#define AT91C_CKGR_OSCOUNT ( 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY ( 0x1 << 16 ) /* (CKGR) Main Clock Ready */
-/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIV ( 0xFF << 0 ) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIV_0 ( 0x0 ) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIV_BYPASS ( 0x1 ) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLCOUNT ( 0x3F << 8 ) /* (CKGR) PLL Counter */
-#define AT91C_CKGR_OUT ( 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */
-#define AT91C_CKGR_OUT_0 ( 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_1 ( 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_2 ( 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_3 ( 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_MUL ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
-#define AT91C_CKGR_USBDIV ( 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */
-#define AT91C_CKGR_USBDIV_0 ( 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */
-#define AT91C_CKGR_USBDIV_1 ( 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */
-#define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+// *** Register offset in AT91S_CKGR structure ***
+#define CKGR_MOR ( 0) // Main Oscillator Register
+#define CKGR_MCFR ( 4) // Main Clock Frequency Register
+#define CKGR_PLLR (12) // PLL Register
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PMC structure *** */
-#define PMC_SCER ( 0 ) /* System Clock Enable Register */
-#define PMC_SCDR ( 4 ) /* System Clock Disable Register */
-#define PMC_SCSR ( 8 ) /* System Clock Status Register */
-#define PMC_PCER ( 16 ) /* Peripheral Clock Enable Register */
-#define PMC_PCDR ( 20 ) /* Peripheral Clock Disable Register */
-#define PMC_PCSR ( 24 ) /* Peripheral Clock Status Register */
-#define PMC_MOR ( 32 ) /* Main Oscillator Register */
-#define PMC_MCFR ( 36 ) /* Main Clock Frequency Register */
-#define PMC_PLLR ( 44 ) /* PLL Register */
-#define PMC_MCKR ( 48 ) /* Master Clock Register */
-#define PMC_PCKR ( 64 ) /* Programmable Clock Register */
-#define PMC_IER ( 96 ) /* Interrupt Enable Register */
-#define PMC_IDR ( 100 ) /* Interrupt Disable Register */
-#define PMC_SR ( 104 ) /* Status Register */
-#define PMC_IMR ( 108 ) /* Interrupt Mask Register */
-/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
-#define AT91C_PMC_PCK ( 0x1 << 0 ) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP ( 0x1 << 7 ) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_PCK0 ( 0x1 << 8 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1 ( 0x1 << 9 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2 ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3 ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */
-/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
-/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
-/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
-/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
-/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
-/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
-#define AT91C_PMC_CSS ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ( 0x0 ) /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ( 0x1 ) /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLL_CLK ( 0x3 ) /* (PMC) Clock from PLL is selected */
-#define AT91C_PMC_PRES ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK ( 0x0 << 2 ) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2 ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4 ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8 ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16 ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32 ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64 ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
-/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
-/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
-#define AT91C_PMC_MOSCS ( 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCK ( 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY ( 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY ( 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY ( 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
-/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
-/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PMC structure ***
+#define PMC_SCER ( 0) // System Clock Enable Register
+#define PMC_SCDR ( 4) // System Clock Disable Register
+#define PMC_SCSR ( 8) // System Clock Status Register
+#define PMC_PCER (16) // Peripheral Clock Enable Register
+#define PMC_PCDR (20) // Peripheral Clock Disable Register
+#define PMC_PCSR (24) // Peripheral Clock Status Register
+#define PMC_MOR (32) // Main Oscillator Register
+#define PMC_MCFR (36) // Main Clock Frequency Register
+#define PMC_PLLR (44) // PLL Register
+#define PMC_MCKR (48) // Master Clock Register
+#define PMC_PCKR (64) // Programmable Clock Register
+#define PMC_IER (96) // Interrupt Enable Register
+#define PMC_IDR (100) // Interrupt Disable Register
+#define PMC_SR (104) // Status Register
+#define PMC_IMR (108) // Interrupt Mask Register
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Reset Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_RSTC structure *** */
-#define RSTC_RCR ( 0 ) /* Reset Control Register */
-#define RSTC_RSR ( 4 ) /* Reset Status Register */
-#define RSTC_RMR ( 8 ) /* Reset Mode Register */
-/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
-#define AT91C_RSTC_PROCRST ( 0x1 << 0 ) /* (RSTC) Processor Reset */
-#define AT91C_RSTC_PERRST ( 0x1 << 2 ) /* (RSTC) Peripheral Reset */
-#define AT91C_RSTC_EXTRST ( 0x1 << 3 ) /* (RSTC) External Reset */
-#define AT91C_RSTC_KEY ( 0xFF << 24 ) /* (RSTC) Password */
-/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
-#define AT91C_RSTC_URSTS ( 0x1 << 0 ) /* (RSTC) User Reset Status */
-#define AT91C_RSTC_BODSTS ( 0x1 << 1 ) /* (RSTC) Brownout Detection Status */
-#define AT91C_RSTC_RSTTYP ( 0x7 << 8 ) /* (RSTC) Reset Type */
-#define AT91C_RSTC_RSTTYP_POWERUP ( 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WAKEUP ( 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WATCHDOG ( 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occured. */
-#define AT91C_RSTC_RSTTYP_SOFTWARE ( 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */
-#define AT91C_RSTC_RSTTYP_USER ( 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */
-#define AT91C_RSTC_RSTTYP_BROWNOUT ( 0x5 << 8 ) /* (RSTC) Brownout Reset occured. */
-#define AT91C_RSTC_NRSTL ( 0x1 << 16 ) /* (RSTC) NRST pin level */
-#define AT91C_RSTC_SRCMP ( 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */
-/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
-#define AT91C_RSTC_URSTEN ( 0x1 << 0 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_URSTIEN ( 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */
-#define AT91C_RSTC_ERSTL ( 0xF << 8 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_BODIEN ( 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RSTC structure ***
+#define RSTC_RCR ( 0) // Reset Control Register
+#define RSTC_RSR ( 4) // Reset Status Register
+#define RSTC_RMR ( 8) // Reset Mode Register
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_RTTC structure *** */
-#define RTTC_RTMR ( 0 ) /* Real-time Mode Register */
-#define RTTC_RTAR ( 4 ) /* Real-time Alarm Register */
-#define RTTC_RTVR ( 8 ) /* Real-time Value Register */
-#define RTTC_RTSR ( 12 ) /* Real-time Status Register */
-/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
-#define AT91C_RTTC_RTPRES ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
-#define AT91C_RTTC_ALMIEN ( 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */
-#define AT91C_RTTC_RTTINCIEN ( 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */
-#define AT91C_RTTC_RTTRST ( 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */
-/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
-#define AT91C_RTTC_ALMV ( 0x0 << 0 ) /* (RTTC) Alarm Value */
-/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
-#define AT91C_RTTC_CRTV ( 0x0 << 0 ) /* (RTTC) Current Real-time Value */
-/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
-#define AT91C_RTTC_ALMS ( 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */
-#define AT91C_RTTC_RTTINC ( 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RTTC structure ***
+#define RTTC_RTMR ( 0) // Real-time Mode Register
+#define RTTC_RTAR ( 4) // Real-time Alarm Register
+#define RTTC_RTVR ( 8) // Real-time Value Register
+#define RTTC_RTSR (12) // Real-time Status Register
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PITC structure *** */
-#define PITC_PIMR ( 0 ) /* Period Interval Mode Register */
-#define PITC_PISR ( 4 ) /* Period Interval Status Register */
-#define PITC_PIVR ( 8 ) /* Period Interval Value Register */
-#define PITC_PIIR ( 12 ) /* Period Interval Image Register */
-/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
-#define AT91C_PITC_PIV ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
-#define AT91C_PITC_PITEN ( 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */
-#define AT91C_PITC_PITIEN ( 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */
-/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
-#define AT91C_PITC_PITS ( 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */
-/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
-#define AT91C_PITC_CPIV ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
-#define AT91C_PITC_PICNT ( 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */
-/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PITC structure ***
+#define PITC_PIMR ( 0) // Period Interval Mode Register
+#define PITC_PISR ( 4) // Period Interval Status Register
+#define PITC_PIVR ( 8) // Period Interval Value Register
+#define PITC_PIIR (12) // Period Interval Image Register
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_WDTC structure *** */
-#define WDTC_WDCR ( 0 ) /* Watchdog Control Register */
-#define WDTC_WDMR ( 4 ) /* Watchdog Mode Register */
-#define WDTC_WDSR ( 8 ) /* Watchdog Status Register */
-/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
-#define AT91C_WDTC_WDRSTT ( 0x1 << 0 ) /* (WDTC) Watchdog Restart */
-#define AT91C_WDTC_KEY ( 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */
-/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
-#define AT91C_WDTC_WDV ( 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDFIEN ( 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */
-#define AT91C_WDTC_WDRSTEN ( 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */
-#define AT91C_WDTC_WDRPROC ( 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDDIS ( 0x1 << 15 ) /* (WDTC) Watchdog Disable */
-#define AT91C_WDTC_WDD ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
-#define AT91C_WDTC_WDDBGHLT ( 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */
-#define AT91C_WDTC_WDIDLEHLT ( 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */
-/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
-#define AT91C_WDTC_WDUNF ( 0x1 << 0 ) /* (WDTC) Watchdog Underflow */
-#define AT91C_WDTC_WDERR ( 0x1 << 1 ) /* (WDTC) Watchdog Error */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_WDTC structure ***
+#define WDTC_WDCR ( 0) // Watchdog Control Register
+#define WDTC_WDMR ( 4) // Watchdog Mode Register
+#define WDTC_WDSR ( 8) // Watchdog Status Register
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_VREG structure *** */
-#define VREG_MR ( 0 ) /* Voltage Regulator Mode Register */
-/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
-#define AT91C_VREG_PSTDBY ( 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_VREG structure ***
+#define VREG_MR ( 0) // Voltage Regulator Mode Register
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Memory Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_MC structure *** */
-#define MC_RCR ( 0 ) /* MC Remap Control Register */
-#define MC_ASR ( 4 ) /* MC Abort Status Register */
-#define MC_AASR ( 8 ) /* MC Abort Address Status Register */
-#define MC_FMR ( 96 ) /* MC Flash Mode Register */
-#define MC_FCR ( 100 ) /* MC Flash Command Register */
-#define MC_FSR ( 104 ) /* MC Flash Status Register */
-/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
-#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */
-/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
-#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */
-#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */
-#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */
-#define AT91C_MC_ABTSZ_WORD ( 0x2 << 8 ) /* (MC) Word */
-#define AT91C_MC_ABTTYP ( 0x3 << 10 ) /* (MC) Abort Type Status */
-#define AT91C_MC_ABTTYP_DATAR ( 0x0 << 10 ) /* (MC) Data Read */
-#define AT91C_MC_ABTTYP_DATAW ( 0x1 << 10 ) /* (MC) Data Write */
-#define AT91C_MC_ABTTYP_FETCH ( 0x2 << 10 ) /* (MC) Code Fetch */
-#define AT91C_MC_MST0 ( 0x1 << 16 ) /* (MC) Master 0 Abort Source */
-#define AT91C_MC_MST1 ( 0x1 << 17 ) /* (MC) Master 1 Abort Source */
-#define AT91C_MC_SVMST0 ( 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */
-#define AT91C_MC_SVMST1 ( 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */
-/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
-#define AT91C_MC_FRDY ( 0x1 << 0 ) /* (MC) Flash Ready */
-#define AT91C_MC_LOCKE ( 0x1 << 2 ) /* (MC) Lock Error */
-#define AT91C_MC_PROGE ( 0x1 << 3 ) /* (MC) Programming Error */
-#define AT91C_MC_NEBP ( 0x1 << 7 ) /* (MC) No Erase Before Programming */
-#define AT91C_MC_FWS ( 0x3 << 8 ) /* (MC) Flash Wait State */
-#define AT91C_MC_FWS_0FWS ( 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */
-#define AT91C_MC_FWS_1FWS ( 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */
-#define AT91C_MC_FWS_2FWS ( 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FWS_3FWS ( 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FMCN ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
-/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
-#define AT91C_MC_FCMD ( 0xF << 0 ) /* (MC) Flash Command */
-#define AT91C_MC_FCMD_START_PROG ( 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */
-#define AT91C_MC_FCMD_LOCK ( 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_PROG_AND_LOCK ( 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
-#define AT91C_MC_FCMD_UNLOCK ( 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_ERASE_ALL ( 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
-#define AT91C_MC_FCMD_SET_GP_NVM ( 0xB ) /* (MC) Set General Purpose NVM bits. */
-#define AT91C_MC_FCMD_CLR_GP_NVM ( 0xD ) /* (MC) Clear General Purpose NVM bits. */
-#define AT91C_MC_FCMD_SET_SECURITY ( 0xF ) /* (MC) Set Security Bit. */
-#define AT91C_MC_PAGEN ( 0x3FF << 8 ) /* (MC) Page Number */
-#define AT91C_MC_KEY ( 0xFF << 24 ) /* (MC) Writing Protect Key */
-/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
-#define AT91C_MC_SECURITY ( 0x1 << 4 ) /* (MC) Security Bit Status */
-#define AT91C_MC_GPNVM0 ( 0x1 << 8 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_GPNVM1 ( 0x1 << 9 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_GPNVM2 ( 0x1 << 10 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_GPNVM3 ( 0x1 << 11 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_GPNVM4 ( 0x1 << 12 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_GPNVM6 ( 0x1 << 14 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_GPNVM7 ( 0x1 << 15 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS0 ( 0x1 << 16 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_LOCKS1 ( 0x1 << 17 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_LOCKS2 ( 0x1 << 18 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_LOCKS3 ( 0x1 << 19 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_LOCKS4 ( 0x1 << 20 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_LOCKS6 ( 0x1 << 22 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_LOCKS7 ( 0x1 << 23 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS8 ( 0x1 << 24 ) /* (MC) Sector 8 Lock Status */
-#define AT91C_MC_LOCKS9 ( 0x1 << 25 ) /* (MC) Sector 9 Lock Status */
-#define AT91C_MC_LOCKS10 ( 0x1 << 26 ) /* (MC) Sector 10 Lock Status */
-#define AT91C_MC_LOCKS11 ( 0x1 << 27 ) /* (MC) Sector 11 Lock Status */
-#define AT91C_MC_LOCKS12 ( 0x1 << 28 ) /* (MC) Sector 12 Lock Status */
-#define AT91C_MC_LOCKS13 ( 0x1 << 29 ) /* (MC) Sector 13 Lock Status */
-#define AT91C_MC_LOCKS14 ( 0x1 << 30 ) /* (MC) Sector 14 Lock Status */
-#define AT91C_MC_LOCKS15 ( 0x1 << 31 ) /* (MC) Sector 15 Lock Status */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_MC structure ***
+#define MC_RCR ( 0) // MC Remap Control Register
+#define MC_ASR ( 4) // MC Abort Status Register
+#define MC_AASR ( 8) // MC Abort Address Status Register
+#define MC_FMR (96) // MC Flash Mode Register
+#define MC_FCR (100) // MC Flash Command Register
+#define MC_FSR (104) // MC Flash Status Register
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_SPI structure *** */
-#define SPI_CR ( 0 ) /* Control Register */
-#define SPI_MR ( 4 ) /* Mode Register */
-#define SPI_RDR ( 8 ) /* Receive Data Register */
-#define SPI_TDR ( 12 ) /* Transmit Data Register */
-#define SPI_SR ( 16 ) /* Status Register */
-#define SPI_IER ( 20 ) /* Interrupt Enable Register */
-#define SPI_IDR ( 24 ) /* Interrupt Disable Register */
-#define SPI_IMR ( 28 ) /* Interrupt Mask Register */
-#define SPI_CSR ( 48 ) /* Chip Select Register */
-#define SPI_RPR ( 256 ) /* Receive Pointer Register */
-#define SPI_RCR ( 260 ) /* Receive Counter Register */
-#define SPI_TPR ( 264 ) /* Transmit Pointer Register */
-#define SPI_TCR ( 268 ) /* Transmit Counter Register */
-#define SPI_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define SPI_RNCR ( 276 ) /* Receive Next Counter Register */
-#define SPI_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define SPI_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define SPI_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define SPI_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN ( 0x1 << 0 ) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS ( 0x1 << 1 ) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST ( 0x1 << 7 ) /* (SPI) SPI Software reset */
-#define AT91C_SPI_LASTXFER ( 0x1 << 24 ) /* (SPI) SPI Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR ( 0x1 << 0 ) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS ( 0x1 << 1 ) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED ( 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE ( 0x1 << 1 ) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC ( 0x1 << 2 ) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_FDIV ( 0x1 << 3 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS ( 0x1 << 4 ) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB ( 0x1 << 7 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS ( 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD ( 0xFFFF << 0 ) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD ( 0xFFFF << 0 ) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF ( 0x1 << 0 ) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE ( 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF ( 0x1 << 2 ) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES ( 0x1 << 3 ) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_ENDRX ( 0x1 << 4 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF ( 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE ( 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_NSSR ( 0x1 << 8 ) /* (SPI) NSSR Interrupt */
-#define AT91C_SPI_TXEMPTY ( 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */
-#define AT91C_SPI_SPIENS ( 0x1 << 16 ) /* (SPI) Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL ( 0x1 << 0 ) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA ( 0x1 << 1 ) /* (SPI) Clock Phase */
-#define AT91C_SPI_CSAAT ( 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */
-#define AT91C_SPI_BITS ( 0xF << 4 ) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8 ( 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9 ( 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10 ( 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11 ( 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12 ( 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13 ( 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14 ( 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15 ( 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16 ( 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR ( 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS ( 0xFF << 16 ) /* (SPI) Delay Before SPCK */
-#define AT91C_SPI_DLYBCT ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SPI structure ***
+#define SPI_CR ( 0) // Control Register
+#define SPI_MR ( 4) // Mode Register
+#define SPI_RDR ( 8) // Receive Data Register
+#define SPI_TDR (12) // Transmit Data Register
+#define SPI_SR (16) // Status Register
+#define SPI_IER (20) // Interrupt Enable Register
+#define SPI_IDR (24) // Interrupt Disable Register
+#define SPI_IMR (28) // Interrupt Mask Register
+#define SPI_CSR (48) // Chip Select Register
+#define SPI_RPR (256) // Receive Pointer Register
+#define SPI_RCR (260) // Receive Counter Register
+#define SPI_TPR (264) // Transmit Pointer Register
+#define SPI_TCR (268) // Transmit Counter Register
+#define SPI_RNPR (272) // Receive Next Pointer Register
+#define SPI_RNCR (276) // Receive Next Counter Register
+#define SPI_TNPR (280) // Transmit Next Pointer Register
+#define SPI_TNCR (284) // Transmit Next Counter Register
+#define SPI_PTCR (288) // PDC Transfer Control Register
+#define SPI_PTSR (292) // PDC Transfer Status Register
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Usart */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_USART structure *** */
-#define US_CR ( 0 ) /* Control Register */
-#define US_MR ( 4 ) /* Mode Register */
-#define US_IER ( 8 ) /* Interrupt Enable Register */
-#define US_IDR ( 12 ) /* Interrupt Disable Register */
-#define US_IMR ( 16 ) /* Interrupt Mask Register */
-#define US_CSR ( 20 ) /* Channel Status Register */
-#define US_RHR ( 24 ) /* Receiver Holding Register */
-#define US_THR ( 28 ) /* Transmitter Holding Register */
-#define US_BRGR ( 32 ) /* Baud Rate Generator Register */
-#define US_RTOR ( 36 ) /* Receiver Time-out Register */
-#define US_TTGR ( 40 ) /* Transmitter Time-guard Register */
-#define US_FIDI ( 64 ) /* FI_DI_Ratio Register */
-#define US_NER ( 68 ) /* Nb Errors Register */
-#define US_IF ( 76 ) /* IRDA_FILTER Register */
-#define US_RPR ( 256 ) /* Receive Pointer Register */
-#define US_RCR ( 260 ) /* Receive Counter Register */
-#define US_TPR ( 264 ) /* Transmit Pointer Register */
-#define US_TCR ( 268 ) /* Transmit Counter Register */
-#define US_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define US_RNCR ( 276 ) /* Receive Next Counter Register */
-#define US_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define US_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define US_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define US_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_STTBRK ( 0x1 << 9 ) /* (USART) Start Break */
-#define AT91C_US_STPBRK ( 0x1 << 10 ) /* (USART) Stop Break */
-#define AT91C_US_STTTO ( 0x1 << 11 ) /* (USART) Start Time-out */
-#define AT91C_US_SENDA ( 0x1 << 12 ) /* (USART) Send Address */
-#define AT91C_US_RSTIT ( 0x1 << 13 ) /* (USART) Reset Iterations */
-#define AT91C_US_RSTNACK ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
-#define AT91C_US_RETTO ( 0x1 << 15 ) /* (USART) Rearm Time-out */
-#define AT91C_US_DTREN ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
-#define AT91C_US_DTRDIS ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
-#define AT91C_US_RTSEN ( 0x1 << 18 ) /* (USART) Request to Send enable */
-#define AT91C_US_RTSDIS ( 0x1 << 19 ) /* (USART) Request to Send Disable */
-/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_USMODE ( 0xF << 0 ) /* (USART) Usart mode */
-#define AT91C_US_USMODE_NORMAL ( 0x0 ) /* (USART) Normal */
-#define AT91C_US_USMODE_RS485 ( 0x1 ) /* (USART) RS485 */
-#define AT91C_US_USMODE_HWHSH ( 0x2 ) /* (USART) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM ( 0x3 ) /* (USART) Modem */
-#define AT91C_US_USMODE_ISO7816_0 ( 0x4 ) /* (USART) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1 ( 0x6 ) /* (USART) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA ( 0x8 ) /* (USART) IrDA */
-#define AT91C_US_USMODE_SWHSH ( 0xC ) /* (USART) Software Handshaking */
-#define AT91C_US_CLKS ( 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CLKS_CLOCK ( 0x0 << 4 ) /* (USART) Clock */
-#define AT91C_US_CLKS_FDIV1 ( 0x1 << 4 ) /* (USART) fdiv1 */
-#define AT91C_US_CLKS_SLOW ( 0x2 << 4 ) /* (USART) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT ( 0x3 << 4 ) /* (USART) External (SCK) */
-#define AT91C_US_CHRL ( 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CHRL_5_BITS ( 0x0 << 6 ) /* (USART) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS ( 0x1 << 6 ) /* (USART) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS ( 0x2 << 6 ) /* (USART) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS ( 0x3 << 6 ) /* (USART) Character Length: 8 bits */
-#define AT91C_US_SYNC ( 0x1 << 8 ) /* (USART) Synchronous Mode Select */
-#define AT91C_US_NBSTOP ( 0x3 << 12 ) /* (USART) Number of Stop bits */
-#define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12 ) /* (USART) 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12 ) /* (USART) 2 stop bits */
-#define AT91C_US_MSBF ( 0x1 << 16 ) /* (USART) Bit Order */
-#define AT91C_US_MODE9 ( 0x1 << 17 ) /* (USART) 9-bit Character length */
-#define AT91C_US_CKLO ( 0x1 << 18 ) /* (USART) Clock Output Select */
-#define AT91C_US_OVER ( 0x1 << 19 ) /* (USART) Over Sampling Mode */
-#define AT91C_US_INACK ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
-#define AT91C_US_DSNACK ( 0x1 << 21 ) /* (USART) Disable Successive NACK */
-#define AT91C_US_MAX_ITER ( 0x1 << 24 ) /* (USART) Number of Repetitions */
-#define AT91C_US_FILTER ( 0x1 << 28 ) /* (USART) Receive Line Filter */
-/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXBRK ( 0x1 << 2 ) /* (USART) Break Received/End of Break */
-#define AT91C_US_TIMEOUT ( 0x1 << 8 ) /* (USART) Receiver Time-out */
-#define AT91C_US_ITERATION ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
-#define AT91C_US_NACK ( 0x1 << 13 ) /* (USART) Non Acknowledge */
-#define AT91C_US_RIIC ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
-#define AT91C_US_DSRIC ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
-#define AT91C_US_DCDIC ( 0x1 << 18 ) /* (USART) Data Carrier Flag */
-#define AT91C_US_CTSIC ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
-/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
-#define AT91C_US_RI ( 0x1 << 20 ) /* (USART) Image of RI Input */
-#define AT91C_US_DSR ( 0x1 << 21 ) /* (USART) Image of DSR Input */
-#define AT91C_US_DCD ( 0x1 << 22 ) /* (USART) Image of DCD Input */
-#define AT91C_US_CTS ( 0x1 << 23 ) /* (USART) Image of CTS Input */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+// *** Register offset in AT91S_USART structure ***
+#define US_CR ( 0) // Control Register
+#define US_MR ( 4) // Mode Register
+#define US_IER ( 8) // Interrupt Enable Register
+#define US_IDR (12) // Interrupt Disable Register
+#define US_IMR (16) // Interrupt Mask Register
+#define US_CSR (20) // Channel Status Register
+#define US_RHR (24) // Receiver Holding Register
+#define US_THR (28) // Transmitter Holding Register
+#define US_BRGR (32) // Baud Rate Generator Register
+#define US_RTOR (36) // Receiver Time-out Register
+#define US_TTGR (40) // Transmitter Time-guard Register
+#define US_FIDI (64) // FI_DI_Ratio Register
+#define US_NER (68) // Nb Errors Register
+#define US_IF (76) // IRDA_FILTER Register
+#define US_RPR (256) // Receive Pointer Register
+#define US_RCR (260) // Receive Counter Register
+#define US_TPR (264) // Transmit Pointer Register
+#define US_TCR (268) // Transmit Counter Register
+#define US_RNPR (272) // Receive Next Pointer Register
+#define US_RNCR (276) // Receive Next Counter Register
+#define US_TNPR (280) // Transmit Next Pointer Register
+#define US_TNCR (284) // Transmit Next Counter Register
+#define US_PTCR (288) // PDC Transfer Control Register
+#define US_PTSR (292) // PDC Transfer Status Register
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_SSC structure *** */
-#define SSC_CR ( 0 ) /* Control Register */
-#define SSC_CMR ( 4 ) /* Clock Mode Register */
-#define SSC_RCMR ( 16 ) /* Receive Clock ModeRegister */
-#define SSC_RFMR ( 20 ) /* Receive Frame Mode Register */
-#define SSC_TCMR ( 24 ) /* Transmit Clock Mode Register */
-#define SSC_TFMR ( 28 ) /* Transmit Frame Mode Register */
-#define SSC_RHR ( 32 ) /* Receive Holding Register */
-#define SSC_THR ( 36 ) /* Transmit Holding Register */
-#define SSC_RSHR ( 48 ) /* Receive Sync Holding Register */
-#define SSC_TSHR ( 52 ) /* Transmit Sync Holding Register */
-#define SSC_SR ( 64 ) /* Status Register */
-#define SSC_IER ( 68 ) /* Interrupt Enable Register */
-#define SSC_IDR ( 72 ) /* Interrupt Disable Register */
-#define SSC_IMR ( 76 ) /* Interrupt Mask Register */
-#define SSC_RPR ( 256 ) /* Receive Pointer Register */
-#define SSC_RCR ( 260 ) /* Receive Counter Register */
-#define SSC_TPR ( 264 ) /* Transmit Pointer Register */
-#define SSC_TCR ( 268 ) /* Transmit Counter Register */
-#define SSC_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define SSC_RNCR ( 276 ) /* Receive Next Counter Register */
-#define SSC_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define SSC_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define SSC_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define SSC_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
-#define AT91C_SSC_RXEN ( 0x1 << 0 ) /* (SSC) Receive Enable */
-#define AT91C_SSC_RXDIS ( 0x1 << 1 ) /* (SSC) Receive Disable */
-#define AT91C_SSC_TXEN ( 0x1 << 8 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_TXDIS ( 0x1 << 9 ) /* (SSC) Transmit Disable */
-#define AT91C_SSC_SWRST ( 0x1 << 15 ) /* (SSC) Software Reset */
-/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
-#define AT91C_SSC_CKS ( 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */
-#define AT91C_SSC_CKS_DIV ( 0x0 ) /* (SSC) Divided Clock */
-#define AT91C_SSC_CKS_TK ( 0x1 ) /* (SSC) TK Clock signal */
-#define AT91C_SSC_CKS_RK ( 0x2 ) /* (SSC) RK pin */
-#define AT91C_SSC_CKO ( 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */
-#define AT91C_SSC_CKO_NONE ( 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
-#define AT91C_SSC_CKO_CONTINOUS ( 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
-#define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
-#define AT91C_SSC_CKI ( 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */
-#define AT91C_SSC_START ( 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */
-#define AT91C_SSC_START_CONTINOUS ( 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
-#define AT91C_SSC_START_TX ( 0x1 << 8 ) /* (SSC) Transmit/Receive start */
-#define AT91C_SSC_START_LOW_RF ( 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */
-#define AT91C_SSC_START_HIGH_RF ( 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */
-#define AT91C_SSC_START_FALL_RF ( 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */
-#define AT91C_SSC_START_RISE_RF ( 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */
-#define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */
-#define AT91C_SSC_START_EDGE_RF ( 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */
-#define AT91C_SSC_START_0 ( 0x8 << 8 ) /* (SSC) Compare 0 */
-#define AT91C_SSC_STTDLY ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
-#define AT91C_SSC_PERIOD ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
-/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
-#define AT91C_SSC_DATLEN ( 0x1F << 0 ) /* (SSC) Data Length */
-#define AT91C_SSC_LOOP ( 0x1 << 5 ) /* (SSC) Loop Mode */
-#define AT91C_SSC_MSBF ( 0x1 << 7 ) /* (SSC) Most Significant Bit First */
-#define AT91C_SSC_DATNB ( 0xF << 8 ) /* (SSC) Data Number per Frame */
-#define AT91C_SSC_FSLEN ( 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */
-#define AT91C_SSC_FSOS ( 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */
-#define AT91C_SSC_FSOS_NONE ( 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
-#define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
-#define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
-#define AT91C_SSC_FSOS_LOW ( 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
-#define AT91C_SSC_FSOS_HIGH ( 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
-#define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
-#define AT91C_SSC_FSEDGE ( 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */
-/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
-/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
-#define AT91C_SSC_DATDEF ( 0x1 << 5 ) /* (SSC) Data Default Value */
-#define AT91C_SSC_FSDEN ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
-/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
-#define AT91C_SSC_TXRDY ( 0x1 << 0 ) /* (SSC) Transmit Ready */
-#define AT91C_SSC_TXEMPTY ( 0x1 << 1 ) /* (SSC) Transmit Empty */
-#define AT91C_SSC_ENDTX ( 0x1 << 2 ) /* (SSC) End Of Transmission */
-#define AT91C_SSC_TXBUFE ( 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */
-#define AT91C_SSC_RXRDY ( 0x1 << 4 ) /* (SSC) Receive Ready */
-#define AT91C_SSC_OVRUN ( 0x1 << 5 ) /* (SSC) Receive Overrun */
-#define AT91C_SSC_ENDRX ( 0x1 << 6 ) /* (SSC) End of Reception */
-#define AT91C_SSC_RXBUFF ( 0x1 << 7 ) /* (SSC) Receive Buffer Full */
-#define AT91C_SSC_TXSYN ( 0x1 << 10 ) /* (SSC) Transmit Sync */
-#define AT91C_SSC_RXSYN ( 0x1 << 11 ) /* (SSC) Receive Sync */
-#define AT91C_SSC_TXENA ( 0x1 << 16 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_RXENA ( 0x1 << 17 ) /* (SSC) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
-/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
-/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SSC structure ***
+#define SSC_CR ( 0) // Control Register
+#define SSC_CMR ( 4) // Clock Mode Register
+#define SSC_RCMR (16) // Receive Clock ModeRegister
+#define SSC_RFMR (20) // Receive Frame Mode Register
+#define SSC_TCMR (24) // Transmit Clock Mode Register
+#define SSC_TFMR (28) // Transmit Frame Mode Register
+#define SSC_RHR (32) // Receive Holding Register
+#define SSC_THR (36) // Transmit Holding Register
+#define SSC_RSHR (48) // Receive Sync Holding Register
+#define SSC_TSHR (52) // Transmit Sync Holding Register
+#define SSC_SR (64) // Status Register
+#define SSC_IER (68) // Interrupt Enable Register
+#define SSC_IDR (72) // Interrupt Disable Register
+#define SSC_IMR (76) // Interrupt Mask Register
+#define SSC_RPR (256) // Receive Pointer Register
+#define SSC_RCR (260) // Receive Counter Register
+#define SSC_TPR (264) // Transmit Pointer Register
+#define SSC_TCR (268) // Transmit Counter Register
+#define SSC_RNPR (272) // Receive Next Pointer Register
+#define SSC_RNCR (276) // Receive Next Counter Register
+#define SSC_TNPR (280) // Transmit Next Pointer Register
+#define SSC_TNCR (284) // Transmit Next Counter Register
+#define SSC_PTCR (288) // PDC Transfer Control Register
+#define SSC_PTSR (292) // PDC Transfer Status Register
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TWI structure *** */
-#define TWI_CR ( 0 ) /* Control Register */
-#define TWI_MMR ( 4 ) /* Master Mode Register */
-#define TWI_IADR ( 12 ) /* Internal Address Register */
-#define TWI_CWGR ( 16 ) /* Clock Waveform Generator Register */
-#define TWI_SR ( 32 ) /* Status Register */
-#define TWI_IER ( 36 ) /* Interrupt Enable Register */
-#define TWI_IDR ( 40 ) /* Interrupt Disable Register */
-#define TWI_IMR ( 44 ) /* Interrupt Mask Register */
-#define TWI_RHR ( 48 ) /* Receive Holding Register */
-#define TWI_THR ( 52 ) /* Transmit Holding Register */
-/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
-#define AT91C_TWI_START ( 0x1 << 0 ) /* (TWI) Send a START Condition */
-#define AT91C_TWI_STOP ( 0x1 << 1 ) /* (TWI) Send a STOP Condition */
-#define AT91C_TWI_MSEN ( 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */
-#define AT91C_TWI_MSDIS ( 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */
-#define AT91C_TWI_SWRST ( 0x1 << 7 ) /* (TWI) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
-#define AT91C_TWI_IADRSZ ( 0x3 << 8 ) /* (TWI) Internal Device Address Size */
-#define AT91C_TWI_IADRSZ_NO ( 0x0 << 8 ) /* (TWI) No internal device address */
-#define AT91C_TWI_IADRSZ_1_BYTE ( 0x1 << 8 ) /* (TWI) One-byte internal device address */
-#define AT91C_TWI_IADRSZ_2_BYTE ( 0x2 << 8 ) /* (TWI) Two-byte internal device address */
-#define AT91C_TWI_IADRSZ_3_BYTE ( 0x3 << 8 ) /* (TWI) Three-byte internal device address */
-#define AT91C_TWI_MREAD ( 0x1 << 12 ) /* (TWI) Master Read Direction */
-#define AT91C_TWI_DADR ( 0x7F << 16 ) /* (TWI) Device Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
-#define AT91C_TWI_CLDIV ( 0xFF << 0 ) /* (TWI) Clock Low Divider */
-#define AT91C_TWI_CHDIV ( 0xFF << 8 ) /* (TWI) Clock High Divider */
-#define AT91C_TWI_CKDIV ( 0x7 << 16 ) /* (TWI) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
-#define AT91C_TWI_TXCOMP ( 0x1 << 0 ) /* (TWI) Transmission Completed */
-#define AT91C_TWI_RXRDY ( 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */
-#define AT91C_TWI_TXRDY ( 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */
-#define AT91C_TWI_OVRE ( 0x1 << 6 ) /* (TWI) Overrun Error */
-#define AT91C_TWI_UNRE ( 0x1 << 7 ) /* (TWI) Underrun Error */
-#define AT91C_TWI_NACK ( 0x1 << 8 ) /* (TWI) Not Acknowledged */
-/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
-/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TWI structure ***
+#define TWI_CR ( 0) // Control Register
+#define TWI_MMR ( 4) // Master Mode Register
+#define TWI_IADR (12) // Internal Address Register
+#define TWI_CWGR (16) // Clock Waveform Generator Register
+#define TWI_SR (32) // Status Register
+#define TWI_IER (36) // Interrupt Enable Register
+#define TWI_IDR (40) // Interrupt Disable Register
+#define TWI_IMR (44) // Interrupt Mask Register
+#define TWI_RHR (48) // Receive Holding Register
+#define TWI_THR (52) // Transmit Holding Register
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PWMC_CH structure *** */
-#define PWMC_CMR ( 0 ) /* Channel Mode Register */
-#define PWMC_CDTYR ( 4 ) /* Channel Duty Cycle Register */
-#define PWMC_CPRDR ( 8 ) /* Channel Period Register */
-#define PWMC_CCNTR ( 12 ) /* Channel Counter Register */
-#define PWMC_CUPDR ( 16 ) /* Channel Update Register */
-#define PWMC_Reserved ( 20 ) /* Reserved */
-/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
-#define AT91C_PWMC_CPRE ( 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
-#define AT91C_PWMC_CPRE_MCK ( 0x0 ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKA ( 0xB ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKB ( 0xC ) /* (PWMC_CH) */
-#define AT91C_PWMC_CALG ( 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */
-#define AT91C_PWMC_CPOL ( 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */
-#define AT91C_PWMC_CPD ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
-/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
-#define AT91C_PWMC_CDTY ( 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */
-/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
-#define AT91C_PWMC_CPRD ( 0x0 << 0 ) /* (PWMC_CH) Channel Period */
-/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
-#define AT91C_PWMC_CCNT ( 0x0 << 0 ) /* (PWMC_CH) Channel Counter */
-/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
-#define AT91C_PWMC_CUPD ( 0x0 << 0 ) /* (PWMC_CH) Channel Update */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC_CH structure ***
+#define PWMC_CMR ( 0) // Channel Mode Register
+#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register
+#define PWMC_CPRDR ( 8) // Channel Period Register
+#define PWMC_CCNTR (12) // Channel Counter Register
+#define PWMC_CUPDR (16) // Channel Update Register
+#define PWMC_Reserved (20) // Reserved
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PWMC structure *** */
-#define PWMC_MR ( 0 ) /* PWMC Mode Register */
-#define PWMC_ENA ( 4 ) /* PWMC Enable Register */
-#define PWMC_DIS ( 8 ) /* PWMC Disable Register */
-#define PWMC_SR ( 12 ) /* PWMC Status Register */
-#define PWMC_IER ( 16 ) /* PWMC Interrupt Enable Register */
-#define PWMC_IDR ( 20 ) /* PWMC Interrupt Disable Register */
-#define PWMC_IMR ( 24 ) /* PWMC Interrupt Mask Register */
-#define PWMC_ISR ( 28 ) /* PWMC Interrupt Status Register */
-#define PWMC_VR ( 252 ) /* PWMC Version Register */
-#define PWMC_CH ( 512 ) /* PWMC Channel */
-/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
-#define AT91C_PWMC_DIVA ( 0xFF << 0 ) /* (PWMC) CLKA divide factor. */
-#define AT91C_PWMC_PREA ( 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */
-#define AT91C_PWMC_PREA_MCK ( 0x0 << 8 ) /* (PWMC) */
-#define AT91C_PWMC_DIVB ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
-#define AT91C_PWMC_PREB ( 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */
-#define AT91C_PWMC_PREB_MCK ( 0x0 << 24 ) /* (PWMC) */
-/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
-#define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */
-#define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */
-#define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */
-#define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */
-/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
-/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
-/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
-/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
-/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
-/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC structure ***
+#define PWMC_MR ( 0) // PWMC Mode Register
+#define PWMC_ENA ( 4) // PWMC Enable Register
+#define PWMC_DIS ( 8) // PWMC Disable Register
+#define PWMC_SR (12) // PWMC Status Register
+#define PWMC_IER (16) // PWMC Interrupt Enable Register
+#define PWMC_IDR (20) // PWMC Interrupt Disable Register
+#define PWMC_IMR (24) // PWMC Interrupt Mask Register
+#define PWMC_ISR (28) // PWMC Interrupt Status Register
+#define PWMC_VR (252) // PWMC Version Register
+#define PWMC_CH (512) // PWMC Channel
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR USB Device Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_UDP structure *** */
-#define UDP_NUM ( 0 ) /* Frame Number Register */
-#define UDP_GLBSTATE ( 4 ) /* Global State Register */
-#define UDP_FADDR ( 8 ) /* Function Address Register */
-#define UDP_IER ( 16 ) /* Interrupt Enable Register */
-#define UDP_IDR ( 20 ) /* Interrupt Disable Register */
-#define UDP_IMR ( 24 ) /* Interrupt Mask Register */
-#define UDP_ISR ( 28 ) /* Interrupt Status Register */
-#define UDP_ICR ( 32 ) /* Interrupt Clear Register */
-#define UDP_RSTEP ( 40 ) /* Reset Endpoint Register */
-#define UDP_CSR ( 48 ) /* Endpoint Control and Status Register */
-#define UDP_FDR ( 80 ) /* Endpoint FIFO Data Register */
-#define UDP_TXVC ( 116 ) /* Transceiver Control Register */
-/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
-#define AT91C_UDP_FRM_NUM ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
-#define AT91C_UDP_FRM_ERR ( 0x1 << 16 ) /* (UDP) Frame Error */
-#define AT91C_UDP_FRM_OK ( 0x1 << 17 ) /* (UDP) Frame OK */
-/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
-#define AT91C_UDP_FADDEN ( 0x1 << 0 ) /* (UDP) Function Address Enable */
-#define AT91C_UDP_CONFG ( 0x1 << 1 ) /* (UDP) Configured */
-#define AT91C_UDP_ESR ( 0x1 << 2 ) /* (UDP) Enable Send Resume */
-#define AT91C_UDP_RSMINPR ( 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */
-#define AT91C_UDP_RMWUPE ( 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */
-/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
-#define AT91C_UDP_FADD ( 0xFF << 0 ) /* (UDP) Function Address Value */
-#define AT91C_UDP_FEN ( 0x1 << 8 ) /* (UDP) Function Enable */
-/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
-#define AT91C_UDP_EPINT0 ( 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT1 ( 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT2 ( 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
-#define AT91C_UDP_EPINT3 ( 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */
-#define AT91C_UDP_EPINT4 ( 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */
-#define AT91C_UDP_EPINT5 ( 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */
-#define AT91C_UDP_RXSUSP ( 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */
-#define AT91C_UDP_RXRSM ( 0x1 << 9 ) /* (UDP) USB Resume Interrupt */
-#define AT91C_UDP_EXTRSM ( 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */
-#define AT91C_UDP_SOFINT ( 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */
-#define AT91C_UDP_WAKEUP ( 0x1 << 13 ) /* (UDP) USB Resume Interrupt */
-/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
-/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
-/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
-#define AT91C_UDP_ENDBUSRES ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
-/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
-/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
-#define AT91C_UDP_EP0 ( 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */
-#define AT91C_UDP_EP1 ( 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */
-#define AT91C_UDP_EP2 ( 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */
-#define AT91C_UDP_EP3 ( 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */
-#define AT91C_UDP_EP4 ( 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */
-#define AT91C_UDP_EP5 ( 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */
-/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
-#define AT91C_UDP_TXCOMP ( 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */
-#define AT91C_UDP_RX_DATA_BK0 ( 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */
-#define AT91C_UDP_RXSETUP ( 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */
-#define AT91C_UDP_ISOERROR ( 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */
-#define AT91C_UDP_TXPKTRDY ( 0x1 << 4 ) /* (UDP) Transmit Packet Ready */
-#define AT91C_UDP_FORCESTALL ( 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
-#define AT91C_UDP_RX_DATA_BK1 ( 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
-#define AT91C_UDP_DIR ( 0x1 << 7 ) /* (UDP) Transfer Direction */
-#define AT91C_UDP_EPTYPE ( 0x7 << 8 ) /* (UDP) Endpoint type */
-#define AT91C_UDP_EPTYPE_CTRL ( 0x0 << 8 ) /* (UDP) Control */
-#define AT91C_UDP_EPTYPE_ISO_OUT ( 0x1 << 8 ) /* (UDP) Isochronous OUT */
-#define AT91C_UDP_EPTYPE_BULK_OUT ( 0x2 << 8 ) /* (UDP) Bulk OUT */
-#define AT91C_UDP_EPTYPE_INT_OUT ( 0x3 << 8 ) /* (UDP) Interrupt OUT */
-#define AT91C_UDP_EPTYPE_ISO_IN ( 0x5 << 8 ) /* (UDP) Isochronous IN */
-#define AT91C_UDP_EPTYPE_BULK_IN ( 0x6 << 8 ) /* (UDP) Bulk IN */
-#define AT91C_UDP_EPTYPE_INT_IN ( 0x7 << 8 ) /* (UDP) Interrupt IN */
-#define AT91C_UDP_DTGLE ( 0x1 << 11 ) /* (UDP) Data Toggle */
-#define AT91C_UDP_EPEDS ( 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */
-#define AT91C_UDP_RXBYTECNT ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
-/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
-#define AT91C_UDP_TXVDIS ( 0x1 << 8 ) /* (UDP) */
-#define AT91C_UDP_PUON ( 0x1 << 9 ) /* (UDP) Pull-up ON */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+// *** Register offset in AT91S_UDP structure ***
+#define UDP_NUM ( 0) // Frame Number Register
+#define UDP_GLBSTATE ( 4) // Global State Register
+#define UDP_FADDR ( 8) // Function Address Register
+#define UDP_IER (16) // Interrupt Enable Register
+#define UDP_IDR (20) // Interrupt Disable Register
+#define UDP_IMR (24) // Interrupt Mask Register
+#define UDP_ISR (28) // Interrupt Status Register
+#define UDP_ICR (32) // Interrupt Clear Register
+#define UDP_RSTEP (40) // Reset Endpoint Register
+#define UDP_CSR (48) // Endpoint Control and Status Register
+#define UDP_FDR (80) // Endpoint FIFO Data Register
+#define UDP_TXVC (116) // Transceiver Control Register
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TC structure *** */
-#define TC_CCR ( 0 ) /* Channel Control Register */
-#define TC_CMR ( 4 ) /* Channel Mode Register (Capture Mode / Waveform Mode) */
-#define TC_CV ( 16 ) /* Counter Value */
-#define TC_RA ( 20 ) /* Register A */
-#define TC_RB ( 24 ) /* Register B */
-#define TC_RC ( 28 ) /* Register C */
-#define TC_SR ( 32 ) /* Status Register */
-#define TC_IER ( 36 ) /* Interrupt Enable Register */
-#define TC_IDR ( 40 ) /* Interrupt Disable Register */
-#define TC_IMR ( 44 ) /* Interrupt Mask Register */
-/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
-#define AT91C_TC_CLKEN ( 0x1 << 0 ) /* (TC) Counter Clock Enable Command */
-#define AT91C_TC_CLKDIS ( 0x1 << 1 ) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ( 0x1 << 2 ) /* (TC) Software Trigger Command */
-/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
-#define AT91C_TC_CLKS ( 0x7 << 0 ) /* (TC) Clock Selection */
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */
-#define AT91C_TC_CLKS_XC0 ( 0x5 ) /* (TC) Clock selected: XC0 */
-#define AT91C_TC_CLKS_XC1 ( 0x6 ) /* (TC) Clock selected: XC1 */
-#define AT91C_TC_CLKS_XC2 ( 0x7 ) /* (TC) Clock selected: XC2 */
-#define AT91C_TC_CLKI ( 0x1 << 3 ) /* (TC) Clock Invert */
-#define AT91C_TC_BURST ( 0x3 << 4 ) /* (TC) Burst Signal Selection */
-#define AT91C_TC_BURST_NONE ( 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */
-#define AT91C_TC_BURST_XC0 ( 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC1 ( 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC2 ( 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */
-#define AT91C_TC_CPCSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */
-#define AT91C_TC_LDBSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */
-#define AT91C_TC_CPCDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */
-#define AT91C_TC_LDBDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */
-#define AT91C_TC_ETRGEDG ( 0x3 << 8 ) /* (TC) External Trigger Edge Selection */
-#define AT91C_TC_ETRGEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_ETRGEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_ETRGEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_ETRGEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVTEDG ( 0x3 << 8 ) /* (TC) External Event Edge Selection */
-#define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVT ( 0x3 << 10 ) /* (TC) External Event Selection */
-#define AT91C_TC_EEVT_TIOB ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
-#define AT91C_TC_EEVT_XC0 ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
-#define AT91C_TC_EEVT_XC1 ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
-#define AT91C_TC_EEVT_XC2 ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
-#define AT91C_TC_ABETRG ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
-#define AT91C_TC_ENETRG ( 0x1 << 12 ) /* (TC) External Event Trigger enable */
-#define AT91C_TC_WAVESEL ( 0x3 << 13 ) /* (TC) Waveform Selection */
-#define AT91C_TC_WAVESEL_UP ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UP_AUTO ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
-#define AT91C_TC_CPCTRG ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
-#define AT91C_TC_WAVE ( 0x1 << 15 ) /* (TC) */
-#define AT91C_TC_ACPA ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
-#define AT91C_TC_ACPA_NONE ( 0x0 << 16 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPA_SET ( 0x1 << 16 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPA_CLEAR ( 0x2 << 16 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRA ( 0x3 << 16 ) /* (TC) RA Loading Selection */
-#define AT91C_TC_LDRA_NONE ( 0x0 << 16 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRA_RISING ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRA_FALLING ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRA_BOTH ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_ACPC ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
-#define AT91C_TC_ACPC_NONE ( 0x0 << 18 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPC_SET ( 0x1 << 18 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPC_CLEAR ( 0x2 << 18 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRB ( 0x3 << 18 ) /* (TC) RB Loading Selection */
-#define AT91C_TC_LDRB_NONE ( 0x0 << 18 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRB_RISING ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRB_FALLING ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRB_BOTH ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_AEEVT ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
-#define AT91C_TC_AEEVT_NONE ( 0x0 << 20 ) /* (TC) Effect: none */
-#define AT91C_TC_AEEVT_SET ( 0x1 << 20 ) /* (TC) Effect: set */
-#define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20 ) /* (TC) Effect: clear */
-#define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20 ) /* (TC) Effect: toggle */
-#define AT91C_TC_ASWTRG ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
-#define AT91C_TC_ASWTRG_NONE ( 0x0 << 22 ) /* (TC) Effect: none */
-#define AT91C_TC_ASWTRG_SET ( 0x1 << 22 ) /* (TC) Effect: set */
-#define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22 ) /* (TC) Effect: clear */
-#define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPB ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
-#define AT91C_TC_BCPB_NONE ( 0x0 << 24 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPB_SET ( 0x1 << 24 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPB_CLEAR ( 0x2 << 24 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPC ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
-#define AT91C_TC_BCPC_NONE ( 0x0 << 26 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPC_SET ( 0x1 << 26 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPC_CLEAR ( 0x2 << 26 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BEEVT ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
-#define AT91C_TC_BEEVT_NONE ( 0x0 << 28 ) /* (TC) Effect: none */
-#define AT91C_TC_BEEVT_SET ( 0x1 << 28 ) /* (TC) Effect: set */
-#define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28 ) /* (TC) Effect: clear */
-#define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BSWTRG ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
-#define AT91C_TC_BSWTRG_NONE ( 0x0 << 30 ) /* (TC) Effect: none */
-#define AT91C_TC_BSWTRG_SET ( 0x1 << 30 ) /* (TC) Effect: set */
-#define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30 ) /* (TC) Effect: clear */
-#define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30 ) /* (TC) Effect: toggle */
-/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
-#define AT91C_TC_COVFS ( 0x1 << 0 ) /* (TC) Counter Overflow */
-#define AT91C_TC_LOVRS ( 0x1 << 1 ) /* (TC) Load Overrun */
-#define AT91C_TC_CPAS ( 0x1 << 2 ) /* (TC) RA Compare */
-#define AT91C_TC_CPBS ( 0x1 << 3 ) /* (TC) RB Compare */
-#define AT91C_TC_CPCS ( 0x1 << 4 ) /* (TC) RC Compare */
-#define AT91C_TC_LDRAS ( 0x1 << 5 ) /* (TC) RA Loading */
-#define AT91C_TC_LDRBS ( 0x1 << 6 ) /* (TC) RB Loading */
-#define AT91C_TC_ETRGS ( 0x1 << 7 ) /* (TC) External Trigger */
-#define AT91C_TC_CLKSTA ( 0x1 << 16 ) /* (TC) Clock Enabling */
-#define AT91C_TC_MTIOA ( 0x1 << 17 ) /* (TC) TIOA Mirror */
-#define AT91C_TC_MTIOB ( 0x1 << 18 ) /* (TC) TIOA Mirror */
-/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
-/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
-/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TC structure ***
+#define TC_CCR ( 0) // Channel Control Register
+#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV (16) // Counter Value
+#define TC_RA (20) // Register A
+#define TC_RB (24) // Register B
+#define TC_RC (28) // Register C
+#define TC_SR (32) // Status Register
+#define TC_IER (36) // Interrupt Enable Register
+#define TC_IDR (40) // Interrupt Disable Register
+#define TC_IMR (44) // Interrupt Mask Register
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE (0x1 << 15) // (TC)
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TCB structure *** */
-#define TCB_TC0 ( 0 ) /* TC Channel 0 */
-#define TCB_TC1 ( 64 ) /* TC Channel 1 */
-#define TCB_TC2 ( 128 ) /* TC Channel 2 */
-#define TCB_BCR ( 192 ) /* TC Block Control Register */
-#define TCB_BMR ( 196 ) /* TC Block Mode Register */
-/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
-#define AT91C_TCB_SYNC ( 0x1 << 0 ) /* (TCB) Synchro Command */
-/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
-#define AT91C_TCB_TC0XC0S ( 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
-#define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0 ) /* (TCB) TCLK0 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_NONE ( 0x1 ) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2 ) /* (TCB) TIOA1 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3 ) /* (TCB) TIOA2 connected to XC0 */
-#define AT91C_TCB_TC1XC1S ( 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
-#define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
-#define AT91C_TCB_TC2XC2S ( 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
-#define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA1 ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TCB structure ***
+#define TCB_TC0 ( 0) // TC Channel 0
+#define TCB_TC1 (64) // TC Channel 1
+#define TCB_TC2 (128) // TC Channel 2
+#define TCB_BCR (192) // TC Block Control Register
+#define TCB_BMR (196) // TC Block Mode Register
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_CAN_MB structure *** */
-#define CAN_MB_MMR ( 0 ) /* MailBox Mode Register */
-#define CAN_MB_MAM ( 4 ) /* MailBox Acceptance Mask Register */
-#define CAN_MB_MID ( 8 ) /* MailBox ID Register */
-#define CAN_MB_MFID ( 12 ) /* MailBox Family ID Register */
-#define CAN_MB_MSR ( 16 ) /* MailBox Status Register */
-#define CAN_MB_MDL ( 20 ) /* MailBox Data Low Register */
-#define CAN_MB_MDH ( 24 ) /* MailBox Data High Register */
-#define CAN_MB_MCR ( 28 ) /* MailBox Control Register */
-/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
-#define AT91C_CAN_MTIMEMARK ( 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */
-#define AT91C_CAN_PRIOR ( 0xF << 16 ) /* (CAN_MB) Mailbox Priority */
-#define AT91C_CAN_MOT ( 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */
-#define AT91C_CAN_MOT_DIS ( 0x0 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RX ( 0x1 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RXOVERWRITE ( 0x2 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_TX ( 0x3 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_CONSUMER ( 0x4 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_PRODUCER ( 0x5 << 24 ) /* (CAN_MB) */
-/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
-#define AT91C_CAN_MIDvB ( 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
-#define AT91C_CAN_MIDvA ( 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */
-#define AT91C_CAN_MIDE ( 0x1 << 29 ) /* (CAN_MB) Identifier Version */
-/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
-/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
-/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
-#define AT91C_CAN_MTIMESTAMP ( 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
-#define AT91C_CAN_MDLC ( 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */
-#define AT91C_CAN_MRTR ( 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */
-#define AT91C_CAN_MABT ( 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */
-#define AT91C_CAN_MRDY ( 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */
-#define AT91C_CAN_MMI ( 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */
-/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
-/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
-/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
-#define AT91C_CAN_MACR ( 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
-#define AT91C_CAN_MTCR ( 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN_MB structure ***
+#define CAN_MB_MMR ( 0) // MailBox Mode Register
+#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register
+#define CAN_MB_MID ( 8) // MailBox ID Register
+#define CAN_MB_MFID (12) // MailBox Family ID Register
+#define CAN_MB_MSR (16) // MailBox Status Register
+#define CAN_MB_MDL (20) // MailBox Data Low Register
+#define CAN_MB_MDH (24) // MailBox Data High Register
+#define CAN_MB_MCR (28) // MailBox Control Register
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
+#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
+#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
+#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
+#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_CAN structure *** */
-#define CAN_MR ( 0 ) /* Mode Register */
-#define CAN_IER ( 4 ) /* Interrupt Enable Register */
-#define CAN_IDR ( 8 ) /* Interrupt Disable Register */
-#define CAN_IMR ( 12 ) /* Interrupt Mask Register */
-#define CAN_SR ( 16 ) /* Status Register */
-#define CAN_BR ( 20 ) /* Baudrate Register */
-#define CAN_TIM ( 24 ) /* Timer Register */
-#define CAN_TIMESTP ( 28 ) /* Time Stamp Register */
-#define CAN_ECR ( 32 ) /* Error Counter Register */
-#define CAN_TCR ( 36 ) /* Transfer Command Register */
-#define CAN_ACR ( 40 ) /* Abort Command Register */
-#define CAN_VR ( 252 ) /* Version Register */
-#define CAN_MB0 ( 512 ) /* CAN Mailbox 0 */
-#define CAN_MB1 ( 544 ) /* CAN Mailbox 1 */
-#define CAN_MB2 ( 576 ) /* CAN Mailbox 2 */
-#define CAN_MB3 ( 608 ) /* CAN Mailbox 3 */
-#define CAN_MB4 ( 640 ) /* CAN Mailbox 4 */
-#define CAN_MB5 ( 672 ) /* CAN Mailbox 5 */
-#define CAN_MB6 ( 704 ) /* CAN Mailbox 6 */
-#define CAN_MB7 ( 736 ) /* CAN Mailbox 7 */
-#define CAN_MB8 ( 768 ) /* CAN Mailbox 8 */
-#define CAN_MB9 ( 800 ) /* CAN Mailbox 9 */
-#define CAN_MB10 ( 832 ) /* CAN Mailbox 10 */
-#define CAN_MB11 ( 864 ) /* CAN Mailbox 11 */
-#define CAN_MB12 ( 896 ) /* CAN Mailbox 12 */
-#define CAN_MB13 ( 928 ) /* CAN Mailbox 13 */
-#define CAN_MB14 ( 960 ) /* CAN Mailbox 14 */
-#define CAN_MB15 ( 992 ) /* CAN Mailbox 15 */
-/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
-#define AT91C_CAN_CANEN ( 0x1 << 0 ) /* (CAN) CAN Controller Enable */
-#define AT91C_CAN_LPM ( 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */
-#define AT91C_CAN_ABM ( 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */
-#define AT91C_CAN_OVL ( 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */
-#define AT91C_CAN_TEOF ( 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */
-#define AT91C_CAN_TTM ( 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */
-#define AT91C_CAN_TIMFRZ ( 0x1 << 6 ) /* (CAN) Enable Timer Freeze */
-#define AT91C_CAN_DRPT ( 0x1 << 7 ) /* (CAN) Disable Repeat */
-/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
-#define AT91C_CAN_MB0 ( 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */
-#define AT91C_CAN_MB1 ( 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */
-#define AT91C_CAN_MB2 ( 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */
-#define AT91C_CAN_MB3 ( 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */
-#define AT91C_CAN_MB4 ( 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */
-#define AT91C_CAN_MB5 ( 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */
-#define AT91C_CAN_MB6 ( 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */
-#define AT91C_CAN_MB7 ( 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */
-#define AT91C_CAN_MB8 ( 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */
-#define AT91C_CAN_MB9 ( 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */
-#define AT91C_CAN_MB10 ( 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
-#define AT91C_CAN_MB11 ( 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
-#define AT91C_CAN_MB12 ( 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
-#define AT91C_CAN_MB13 ( 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
-#define AT91C_CAN_MB14 ( 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
-#define AT91C_CAN_MB15 ( 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
-#define AT91C_CAN_ERRA ( 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
-#define AT91C_CAN_WARN ( 0x1 << 17 ) /* (CAN) Warning Limit Flag */
-#define AT91C_CAN_ERRP ( 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
-#define AT91C_CAN_BOFF ( 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
-#define AT91C_CAN_SLEEP ( 0x1 << 20 ) /* (CAN) Sleep Flag */
-#define AT91C_CAN_WAKEUP ( 0x1 << 21 ) /* (CAN) Wakeup Flag */
-#define AT91C_CAN_TOVF ( 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
-#define AT91C_CAN_TSTP ( 0x1 << 23 ) /* (CAN) Timestamp Flag */
-#define AT91C_CAN_CERR ( 0x1 << 24 ) /* (CAN) CRC Error */
-#define AT91C_CAN_SERR ( 0x1 << 25 ) /* (CAN) Stuffing Error */
-#define AT91C_CAN_AERR ( 0x1 << 26 ) /* (CAN) Acknowledgment Error */
-#define AT91C_CAN_FERR ( 0x1 << 27 ) /* (CAN) Form Error */
-#define AT91C_CAN_BERR ( 0x1 << 28 ) /* (CAN) Bit Error */
-/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
-/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
-/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
-#define AT91C_CAN_RBSY ( 0x1 << 29 ) /* (CAN) Receiver Busy */
-#define AT91C_CAN_TBSY ( 0x1 << 30 ) /* (CAN) Transmitter Busy */
-#define AT91C_CAN_OVLY ( 0x1 << 31 ) /* (CAN) Overload Busy */
-/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
-#define AT91C_CAN_PHASE2 ( 0x7 << 0 ) /* (CAN) Phase 2 segment */
-#define AT91C_CAN_PHASE1 ( 0x7 << 4 ) /* (CAN) Phase 1 segment */
-#define AT91C_CAN_PROPAG ( 0x7 << 8 ) /* (CAN) Programmation time segment */
-#define AT91C_CAN_SYNC ( 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */
-#define AT91C_CAN_BRP ( 0x7F << 16 ) /* (CAN) Baudrate Prescaler */
-#define AT91C_CAN_SMP ( 0x1 << 24 ) /* (CAN) Sampling mode */
-/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
-#define AT91C_CAN_TIMER ( 0xFFFF << 0 ) /* (CAN) Timer field */
-/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
-/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
-#define AT91C_CAN_REC ( 0xFF << 0 ) /* (CAN) Receive Error Counter */
-#define AT91C_CAN_TEC ( 0xFF << 16 ) /* (CAN) Transmit Error Counter */
-/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
-#define AT91C_CAN_TIMRST ( 0x1 << 31 ) /* (CAN) Timer Reset Field */
-/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN structure ***
+#define CAN_MR ( 0) // Mode Register
+#define CAN_IER ( 4) // Interrupt Enable Register
+#define CAN_IDR ( 8) // Interrupt Disable Register
+#define CAN_IMR (12) // Interrupt Mask Register
+#define CAN_SR (16) // Status Register
+#define CAN_BR (20) // Baudrate Register
+#define CAN_TIM (24) // Timer Register
+#define CAN_TIMESTP (28) // Time Stamp Register
+#define CAN_ECR (32) // Error Counter Register
+#define CAN_TCR (36) // Transfer Command Register
+#define CAN_ACR (40) // Abort Command Register
+#define CAN_VR (252) // Version Register
+#define CAN_MB0 (512) // CAN Mailbox 0
+#define CAN_MB1 (544) // CAN Mailbox 1
+#define CAN_MB2 (576) // CAN Mailbox 2
+#define CAN_MB3 (608) // CAN Mailbox 3
+#define CAN_MB4 (640) // CAN Mailbox 4
+#define CAN_MB5 (672) // CAN Mailbox 5
+#define CAN_MB6 (704) // CAN Mailbox 6
+#define CAN_MB7 (736) // CAN Mailbox 7
+#define CAN_MB8 (768) // CAN Mailbox 8
+#define CAN_MB9 (800) // CAN Mailbox 9
+#define CAN_MB10 (832) // CAN Mailbox 10
+#define CAN_MB11 (864) // CAN Mailbox 11
+#define CAN_MB12 (896) // CAN Mailbox 12
+#define CAN_MB13 (928) // CAN Mailbox 13
+#define CAN_MB14 (960) // CAN Mailbox 14
+#define CAN_MB15 (992) // CAN Mailbox 15
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
+#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
+#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
+#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
+#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
+#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
+#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
+#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_EMAC structure *** */
-#define EMAC_NCR ( 0 ) /* Network Control Register */
-#define EMAC_NCFGR ( 4 ) /* Network Configuration Register */
-#define EMAC_NSR ( 8 ) /* Network Status Register */
-#define EMAC_TSR ( 20 ) /* Transmit Status Register */
-#define EMAC_RBQP ( 24 ) /* Receive Buffer Queue Pointer */
-#define EMAC_TBQP ( 28 ) /* Transmit Buffer Queue Pointer */
-#define EMAC_RSR ( 32 ) /* Receive Status Register */
-#define EMAC_ISR ( 36 ) /* Interrupt Status Register */
-#define EMAC_IER ( 40 ) /* Interrupt Enable Register */
-#define EMAC_IDR ( 44 ) /* Interrupt Disable Register */
-#define EMAC_IMR ( 48 ) /* Interrupt Mask Register */
-#define EMAC_MAN ( 52 ) /* PHY Maintenance Register */
-#define EMAC_PTR ( 56 ) /* Pause Time Register */
-#define EMAC_PFR ( 60 ) /* Pause Frames received Register */
-#define EMAC_FTO ( 64 ) /* Frames Transmitted OK Register */
-#define EMAC_SCF ( 68 ) /* Single Collision Frame Register */
-#define EMAC_MCF ( 72 ) /* Multiple Collision Frame Register */
-#define EMAC_FRO ( 76 ) /* Frames Received OK Register */
-#define EMAC_FCSE ( 80 ) /* Frame Check Sequence Error Register */
-#define EMAC_ALE ( 84 ) /* Alignment Error Register */
-#define EMAC_DTF ( 88 ) /* Deferred Transmission Frame Register */
-#define EMAC_LCOL ( 92 ) /* Late Collision Register */
-#define EMAC_ECOL ( 96 ) /* Excessive Collision Register */
-#define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */
-#define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */
-#define EMAC_RRE ( 108 ) /* Receive Ressource Error Register */
-#define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */
-#define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */
-#define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */
-#define EMAC_RJA ( 124 ) /* Receive Jabbers Register */
-#define EMAC_USF ( 128 ) /* Undersize Frames Register */
-#define EMAC_STE ( 132 ) /* SQE Test Error Register */
-#define EMAC_RLE ( 136 ) /* Receive Length Field Mismatch Register */
-#define EMAC_TPF ( 140 ) /* Transmitted Pause Frames Register */
-#define EMAC_HRB ( 144 ) /* Hash Address Bottom[31:0] */
-#define EMAC_HRT ( 148 ) /* Hash Address Top[63:32] */
-#define EMAC_SA1L ( 152 ) /* Specific Address 1 Bottom, First 4 bytes */
-#define EMAC_SA1H ( 156 ) /* Specific Address 1 Top, Last 2 bytes */
-#define EMAC_SA2L ( 160 ) /* Specific Address 2 Bottom, First 4 bytes */
-#define EMAC_SA2H ( 164 ) /* Specific Address 2 Top, Last 2 bytes */
-#define EMAC_SA3L ( 168 ) /* Specific Address 3 Bottom, First 4 bytes */
-#define EMAC_SA3H ( 172 ) /* Specific Address 3 Top, Last 2 bytes */
-#define EMAC_SA4L ( 176 ) /* Specific Address 4 Bottom, First 4 bytes */
-#define EMAC_SA4H ( 180 ) /* Specific Address 4 Top, Last 2 bytes */
-#define EMAC_TID ( 184 ) /* Type ID Checking Register */
-#define EMAC_TPQ ( 188 ) /* Transmit Pause Quantum Register */
-#define EMAC_USRIO ( 192 ) /* USER Input/Output Register */
-#define EMAC_WOL ( 196 ) /* Wake On LAN Register */
-#define EMAC_REV ( 252 ) /* Revision Register */
-/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */
-#define AT91C_EMAC_LB ( 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LLB ( 0x1 << 1 ) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE ( 0x1 << 2 ) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE ( 0x1 << 3 ) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE ( 0x1 << 4 ) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CLRSTAT ( 0x1 << 5 ) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_INCSTAT ( 0x1 << 6 ) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WESTAT ( 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP ( 0x1 << 8 ) /* (EMAC) Back pressure. */
-#define AT91C_EMAC_TSTART ( 0x1 << 9 ) /* (EMAC) Start Transmission. */
-#define AT91C_EMAC_THALT ( 0x1 << 10 ) /* (EMAC) Transmission Halt. */
-#define AT91C_EMAC_TPFR ( 0x1 << 11 ) /* (EMAC) Transmit pause frame */
-#define AT91C_EMAC_TZQ ( 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
-/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
-#define AT91C_EMAC_SPD ( 0x1 << 0 ) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD ( 0x1 << 1 ) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_JFRAME ( 0x1 << 3 ) /* (EMAC) Jumbo Frames. */
-#define AT91C_EMAC_CAF ( 0x1 << 4 ) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC ( 0x1 << 5 ) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI ( 0x1 << 6 ) /* (EMAC) Multicast hash event enable */
-#define AT91C_EMAC_UNI ( 0x1 << 7 ) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG ( 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE ( 0x1 << 9 ) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK ( 0x3 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8 ( 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16 ( 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32 ( 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64 ( 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY ( 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PAE ( 0x1 << 13 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF ( 0x3 << 14 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF_OFFSET_0 ( 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_1 ( 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_2 ( 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_3 ( 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
-#define AT91C_EMAC_RLCE ( 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
-#define AT91C_EMAC_DRFCS ( 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
-#define AT91C_EMAC_EFRHD ( 0x1 << 18 ) /* (EMAC) */
-#define AT91C_EMAC_IRXFCS ( 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
-/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
-#define AT91C_EMAC_LINKR ( 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_MDIO ( 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_IDLE ( 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
-#define AT91C_EMAC_UBR ( 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_COL ( 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RLES ( 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TGO ( 0x1 << 3 ) /* (EMAC) Transmit Go */
-#define AT91C_EMAC_BEX ( 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */
-#define AT91C_EMAC_COMP ( 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_UND ( 0x1 << 6 ) /* (EMAC) */
-/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA ( 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_REC ( 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_OVR ( 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
-#define AT91C_EMAC_MFD ( 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_RCOMP ( 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RXUBR ( 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TXUBR ( 0x1 << 3 ) /* (EMAC) */
-#define AT91C_EMAC_TUNDR ( 0x1 << 4 ) /* (EMAC) */
-#define AT91C_EMAC_RLEX ( 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_TXERR ( 0x1 << 6 ) /* (EMAC) */
-#define AT91C_EMAC_TCOMP ( 0x1 << 7 ) /* (EMAC) */
-#define AT91C_EMAC_LINK ( 0x1 << 9 ) /* (EMAC) */
-#define AT91C_EMAC_ROVR ( 0x1 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_HRESP ( 0x1 << 11 ) /* (EMAC) */
-#define AT91C_EMAC_PFRE ( 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PTZ ( 0x1 << 13 ) /* (EMAC) */
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
-/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA ( 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_CODE ( 0x3 << 16 ) /* (EMAC) */
-#define AT91C_EMAC_REGA ( 0x1F << 18 ) /* (EMAC) */
-#define AT91C_EMAC_PHYA ( 0x1F << 23 ) /* (EMAC) */
-#define AT91C_EMAC_RW ( 0x3 << 28 ) /* (EMAC) */
-#define AT91C_EMAC_SOF ( 0x3 << 30 ) /* (EMAC) */
-/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
-#define AT91C_EMAC_RMII ( 0x1 << 0 ) /* (EMAC) Reduce MII */
-/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
-#define AT91C_EMAC_IP ( 0xFFFF << 0 ) /* (EMAC) ARP request IP address */
-#define AT91C_EMAC_MAG ( 0x1 << 16 ) /* (EMAC) Magic packet event enable */
-#define AT91C_EMAC_ARP ( 0x1 << 17 ) /* (EMAC) ARP request event enable */
-#define AT91C_EMAC_SA1 ( 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */
-/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
-#define AT91C_EMAC_REVREF ( 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_PARTREF ( 0xFFFF << 16 ) /* (EMAC) */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
+// *****************************************************************************
+// *** Register offset in AT91S_EMAC structure ***
+#define EMAC_NCR ( 0) // Network Control Register
+#define EMAC_NCFGR ( 4) // Network Configuration Register
+#define EMAC_NSR ( 8) // Network Status Register
+#define EMAC_TSR (20) // Transmit Status Register
+#define EMAC_RBQP (24) // Receive Buffer Queue Pointer
+#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer
+#define EMAC_RSR (32) // Receive Status Register
+#define EMAC_ISR (36) // Interrupt Status Register
+#define EMAC_IER (40) // Interrupt Enable Register
+#define EMAC_IDR (44) // Interrupt Disable Register
+#define EMAC_IMR (48) // Interrupt Mask Register
+#define EMAC_MAN (52) // PHY Maintenance Register
+#define EMAC_PTR (56) // Pause Time Register
+#define EMAC_PFR (60) // Pause Frames received Register
+#define EMAC_FTO (64) // Frames Transmitted OK Register
+#define EMAC_SCF (68) // Single Collision Frame Register
+#define EMAC_MCF (72) // Multiple Collision Frame Register
+#define EMAC_FRO (76) // Frames Received OK Register
+#define EMAC_FCSE (80) // Frame Check Sequence Error Register
+#define EMAC_ALE (84) // Alignment Error Register
+#define EMAC_DTF (88) // Deferred Transmission Frame Register
+#define EMAC_LCOL (92) // Late Collision Register
+#define EMAC_ECOL (96) // Excessive Collision Register
+#define EMAC_TUND (100) // Transmit Underrun Error Register
+#define EMAC_CSE (104) // Carrier Sense Error Register
+#define EMAC_RRE (108) // Receive Ressource Error Register
+#define EMAC_ROV (112) // Receive Overrun Errors Register
+#define EMAC_RSE (116) // Receive Symbol Errors Register
+#define EMAC_ELE (120) // Excessive Length Errors Register
+#define EMAC_RJA (124) // Receive Jabbers Register
+#define EMAC_USF (128) // Undersize Frames Register
+#define EMAC_STE (132) // SQE Test Error Register
+#define EMAC_RLE (136) // Receive Length Field Mismatch Register
+#define EMAC_TPF (140) // Transmitted Pause Frames Register
+#define EMAC_HRB (144) // Hash Address Bottom[31:0]
+#define EMAC_HRT (148) // Hash Address Top[63:32]
+#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes
+#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes
+#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes
+#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes
+#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes
+#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes
+#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes
+#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes
+#define EMAC_TID (184) // Type ID Checking Register
+#define EMAC_TPQ (188) // Transmit Pause Quantum Register
+#define EMAC_USRIO (192) // USER Input/Output Register
+#define EMAC_WOL (196) // Wake On LAN Register
+#define EMAC_REV (252) // Revision Register
+// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
+#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
+#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
+#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
+#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
+#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
+#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
+#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
+#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
+#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
+#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
+#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
+#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
+#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
+#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
+#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
+#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
+#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
+#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
+#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
+#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
+#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
+#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
+#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
+#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
+#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
+#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
+#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
+#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
+#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
+#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
+#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
+#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
+#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
+#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
+#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
+#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
+#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
+#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
+#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
+#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
+#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
+#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
+#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
+#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
+#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
+#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
+#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
+#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
+#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
+#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
+#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
+#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_ADC structure *** */
-#define ADC_CR ( 0 ) /* ADC Control Register */
-#define ADC_MR ( 4 ) /* ADC Mode Register */
-#define ADC_CHER ( 16 ) /* ADC Channel Enable Register */
-#define ADC_CHDR ( 20 ) /* ADC Channel Disable Register */
-#define ADC_CHSR ( 24 ) /* ADC Channel Status Register */
-#define ADC_SR ( 28 ) /* ADC Status Register */
-#define ADC_LCDR ( 32 ) /* ADC Last Converted Data Register */
-#define ADC_IER ( 36 ) /* ADC Interrupt Enable Register */
-#define ADC_IDR ( 40 ) /* ADC Interrupt Disable Register */
-#define ADC_IMR ( 44 ) /* ADC Interrupt Mask Register */
-#define ADC_CDR0 ( 48 ) /* ADC Channel Data Register 0 */
-#define ADC_CDR1 ( 52 ) /* ADC Channel Data Register 1 */
-#define ADC_CDR2 ( 56 ) /* ADC Channel Data Register 2 */
-#define ADC_CDR3 ( 60 ) /* ADC Channel Data Register 3 */
-#define ADC_CDR4 ( 64 ) /* ADC Channel Data Register 4 */
-#define ADC_CDR5 ( 68 ) /* ADC Channel Data Register 5 */
-#define ADC_CDR6 ( 72 ) /* ADC Channel Data Register 6 */
-#define ADC_CDR7 ( 76 ) /* ADC Channel Data Register 7 */
-#define ADC_RPR ( 256 ) /* Receive Pointer Register */
-#define ADC_RCR ( 260 ) /* Receive Counter Register */
-#define ADC_TPR ( 264 ) /* Transmit Pointer Register */
-#define ADC_TCR ( 268 ) /* Transmit Counter Register */
-#define ADC_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define ADC_RNCR ( 276 ) /* Receive Next Counter Register */
-#define ADC_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define ADC_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define ADC_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define ADC_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
-#define AT91C_ADC_SWRST ( 0x1 << 0 ) /* (ADC) Software Reset */
-#define AT91C_ADC_START ( 0x1 << 1 ) /* (ADC) Start Conversion */
-/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
-#define AT91C_ADC_TRGEN ( 0x1 << 0 ) /* (ADC) Trigger Enable */
-#define AT91C_ADC_TRGEN_DIS ( 0x0 ) /* (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software */
-#define AT91C_ADC_TRGEN_EN ( 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
-#define AT91C_ADC_TRGSEL ( 0x7 << 1 ) /* (ADC) Trigger Selection */
-#define AT91C_ADC_TRGSEL_TIOA0 ( 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */
-#define AT91C_ADC_TRGSEL_TIOA1 ( 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */
-#define AT91C_ADC_TRGSEL_TIOA2 ( 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */
-#define AT91C_ADC_TRGSEL_TIOA3 ( 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */
-#define AT91C_ADC_TRGSEL_TIOA4 ( 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */
-#define AT91C_ADC_TRGSEL_TIOA5 ( 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */
-#define AT91C_ADC_TRGSEL_EXT ( 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */
-#define AT91C_ADC_LOWRES ( 0x1 << 4 ) /* (ADC) Resolution. */
-#define AT91C_ADC_LOWRES_10_BIT ( 0x0 << 4 ) /* (ADC) 10-bit resolution */
-#define AT91C_ADC_LOWRES_8_BIT ( 0x1 << 4 ) /* (ADC) 8-bit resolution */
-#define AT91C_ADC_SLEEP ( 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_SLEEP_NORMAL_MODE ( 0x0 << 5 ) /* (ADC) Normal Mode */
-#define AT91C_ADC_SLEEP_MODE ( 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_PRESCAL ( 0x3F << 8 ) /* (ADC) Prescaler rate selection */
-#define AT91C_ADC_STARTUP ( 0x1F << 16 ) /* (ADC) Startup Time */
-#define AT91C_ADC_SHTIM ( 0xF << 24 ) /* (ADC) Sample & Hold Time */
-/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
-#define AT91C_ADC_CH0 ( 0x1 << 0 ) /* (ADC) Channel 0 */
-#define AT91C_ADC_CH1 ( 0x1 << 1 ) /* (ADC) Channel 1 */
-#define AT91C_ADC_CH2 ( 0x1 << 2 ) /* (ADC) Channel 2 */
-#define AT91C_ADC_CH3 ( 0x1 << 3 ) /* (ADC) Channel 3 */
-#define AT91C_ADC_CH4 ( 0x1 << 4 ) /* (ADC) Channel 4 */
-#define AT91C_ADC_CH5 ( 0x1 << 5 ) /* (ADC) Channel 5 */
-#define AT91C_ADC_CH6 ( 0x1 << 6 ) /* (ADC) Channel 6 */
-#define AT91C_ADC_CH7 ( 0x1 << 7 ) /* (ADC) Channel 7 */
-/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
-/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
-/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
-#define AT91C_ADC_EOC0 ( 0x1 << 0 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC1 ( 0x1 << 1 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC2 ( 0x1 << 2 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC3 ( 0x1 << 3 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC4 ( 0x1 << 4 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC5 ( 0x1 << 5 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC6 ( 0x1 << 6 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC7 ( 0x1 << 7 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_OVRE0 ( 0x1 << 8 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE1 ( 0x1 << 9 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE2 ( 0x1 << 10 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE3 ( 0x1 << 11 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE4 ( 0x1 << 12 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE5 ( 0x1 << 13 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE6 ( 0x1 << 14 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE7 ( 0x1 << 15 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_DRDY ( 0x1 << 16 ) /* (ADC) Data Ready */
-#define AT91C_ADC_GOVRE ( 0x1 << 17 ) /* (ADC) General Overrun */
-#define AT91C_ADC_ENDRX ( 0x1 << 18 ) /* (ADC) End of Receiver Transfer */
-#define AT91C_ADC_RXBUFF ( 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */
-/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
-#define AT91C_ADC_LDATA ( 0x3FF << 0 ) /* (ADC) Last Data Converted */
-/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
-/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
-/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
-/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
-#define AT91C_ADC_DATA ( 0x3FF << 0 ) /* (ADC) Converted Data */
-/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
-/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
-/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
-/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
-/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
-/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
-/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+// *** Register offset in AT91S_ADC structure ***
+#define ADC_CR ( 0) // ADC Control Register
+#define ADC_MR ( 4) // ADC Mode Register
+#define ADC_CHER (16) // ADC Channel Enable Register
+#define ADC_CHDR (20) // ADC Channel Disable Register
+#define ADC_CHSR (24) // ADC Channel Status Register
+#define ADC_SR (28) // ADC Status Register
+#define ADC_LCDR (32) // ADC Last Converted Data Register
+#define ADC_IER (36) // ADC Interrupt Enable Register
+#define ADC_IDR (40) // ADC Interrupt Disable Register
+#define ADC_IMR (44) // ADC Interrupt Mask Register
+#define ADC_CDR0 (48) // ADC Channel Data Register 0
+#define ADC_CDR1 (52) // ADC Channel Data Register 1
+#define ADC_CDR2 (56) // ADC Channel Data Register 2
+#define ADC_CDR3 (60) // ADC Channel Data Register 3
+#define ADC_CDR4 (64) // ADC Channel Data Register 4
+#define ADC_CDR5 (68) // ADC Channel Data Register 5
+#define ADC_CDR6 (72) // ADC Channel Data Register 6
+#define ADC_CDR7 (76) // ADC Channel Data Register 7
+#define ADC_RPR (256) // Receive Pointer Register
+#define ADC_RCR (260) // Receive Counter Register
+#define ADC_TPR (264) // Transmit Pointer Register
+#define ADC_TCR (268) // Transmit Counter Register
+#define ADC_RNPR (272) // Receive Next Pointer Register
+#define ADC_RNCR (276) // Receive Next Counter Register
+#define ADC_TNPR (280) // Transmit Next Pointer Register
+#define ADC_TNCR (284) // Transmit Next Counter Register
+#define ADC_PTCR (288) // PDC Transfer Control Register
+#define ADC_PTSR (292) // PDC Transfer Status Register
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_AES structure *** */
-#define AES_CR ( 0 ) /* Control Register */
-#define AES_MR ( 4 ) /* Mode Register */
-#define AES_IER ( 16 ) /* Interrupt Enable Register */
-#define AES_IDR ( 20 ) /* Interrupt Disable Register */
-#define AES_IMR ( 24 ) /* Interrupt Mask Register */
-#define AES_ISR ( 28 ) /* Interrupt Status Register */
-#define AES_KEYWxR ( 32 ) /* Key Word x Register */
-#define AES_IDATAxR ( 64 ) /* Input Data x Register */
-#define AES_ODATAxR ( 80 ) /* Output Data x Register */
-#define AES_IVxR ( 96 ) /* Initialization Vector x Register */
-#define AES_VR ( 252 ) /* AES Version Register */
-#define AES_RPR ( 256 ) /* Receive Pointer Register */
-#define AES_RCR ( 260 ) /* Receive Counter Register */
-#define AES_TPR ( 264 ) /* Transmit Pointer Register */
-#define AES_TCR ( 268 ) /* Transmit Counter Register */
-#define AES_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define AES_RNCR ( 276 ) /* Receive Next Counter Register */
-#define AES_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define AES_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define AES_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define AES_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
-#define AT91C_AES_START ( 0x1 << 0 ) /* (AES) Starts Processing */
-#define AT91C_AES_SWRST ( 0x1 << 8 ) /* (AES) Software Reset */
-#define AT91C_AES_LOADSEED ( 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */
-/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
-#define AT91C_AES_CIPHER ( 0x1 << 0 ) /* (AES) Processing Mode */
-#define AT91C_AES_PROCDLY ( 0xF << 4 ) /* (AES) Processing Delay */
-#define AT91C_AES_SMOD ( 0x3 << 8 ) /* (AES) Start Mode */
-#define AT91C_AES_SMOD_MANUAL ( 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
-#define AT91C_AES_SMOD_AUTO ( 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
-#define AT91C_AES_SMOD_PDC ( 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */
-#define AT91C_AES_OPMOD ( 0x7 << 12 ) /* (AES) Operation Mode */
-#define AT91C_AES_OPMOD_ECB ( 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */
-#define AT91C_AES_OPMOD_CBC ( 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */
-#define AT91C_AES_OPMOD_OFB ( 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */
-#define AT91C_AES_OPMOD_CFB ( 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */
-#define AT91C_AES_OPMOD_CTR ( 0x4 << 12 ) /* (AES) CTR Counter mode. */
-#define AT91C_AES_LOD ( 0x1 << 15 ) /* (AES) Last Output Data Mode */
-#define AT91C_AES_CFBS ( 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */
-#define AT91C_AES_CFBS_128_BIT ( 0x0 << 16 ) /* (AES) 128-bit. */
-#define AT91C_AES_CFBS_64_BIT ( 0x1 << 16 ) /* (AES) 64-bit. */
-#define AT91C_AES_CFBS_32_BIT ( 0x2 << 16 ) /* (AES) 32-bit. */
-#define AT91C_AES_CFBS_16_BIT ( 0x3 << 16 ) /* (AES) 16-bit. */
-#define AT91C_AES_CFBS_8_BIT ( 0x4 << 16 ) /* (AES) 8-bit. */
-#define AT91C_AES_CKEY ( 0xF << 20 ) /* (AES) Countermeasure Key */
-#define AT91C_AES_CTYPE ( 0x1F << 24 ) /* (AES) Countermeasure Type */
-#define AT91C_AES_CTYPE_TYPE1_EN ( 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */
-#define AT91C_AES_CTYPE_TYPE2_EN ( 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */
-#define AT91C_AES_CTYPE_TYPE3_EN ( 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */
-#define AT91C_AES_CTYPE_TYPE4_EN ( 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */
-#define AT91C_AES_CTYPE_TYPE5_EN ( 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
-/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_AES_DATRDY ( 0x1 << 0 ) /* (AES) DATRDY */
-#define AT91C_AES_ENDRX ( 0x1 << 1 ) /* (AES) PDC Read Buffer End */
-#define AT91C_AES_ENDTX ( 0x1 << 2 ) /* (AES) PDC Write Buffer End */
-#define AT91C_AES_RXBUFF ( 0x1 << 3 ) /* (AES) PDC Read Buffer Full */
-#define AT91C_AES_TXBUFE ( 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */
-#define AT91C_AES_URAD ( 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */
-/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_AES_URAT ( 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
-#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
-#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
-#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
-#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
-#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
-#define AT91C_AES_URAT_WO_REG_READ ( 0x5 << 12 ) /* (AES) Write-only register read access. */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_AES structure ***
+#define AES_CR ( 0) // Control Register
+#define AES_MR ( 4) // Mode Register
+#define AES_IER (16) // Interrupt Enable Register
+#define AES_IDR (20) // Interrupt Disable Register
+#define AES_IMR (24) // Interrupt Mask Register
+#define AES_ISR (28) // Interrupt Status Register
+#define AES_KEYWxR (32) // Key Word x Register
+#define AES_IDATAxR (64) // Input Data x Register
+#define AES_ODATAxR (80) // Output Data x Register
+#define AES_IVxR (96) // Initialization Vector x Register
+#define AES_VR (252) // AES Version Register
+#define AES_RPR (256) // Receive Pointer Register
+#define AES_RCR (260) // Receive Counter Register
+#define AES_TPR (264) // Transmit Pointer Register
+#define AES_TCR (268) // Transmit Counter Register
+#define AES_RNPR (272) // Receive Next Pointer Register
+#define AES_RNCR (276) // Receive Next Counter Register
+#define AES_TNPR (280) // Transmit Next Pointer Register
+#define AES_TNCR (284) // Transmit Next Counter Register
+#define AES_PTCR (288) // PDC Transfer Control Register
+#define AES_PTSR (292) // PDC Transfer Status Register
+// -------- AES_CR : (AES Offset: 0x0) Control Register --------
+#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing
+#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
+#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay
+#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode
+#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode
+#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode.
+#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size
+#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit.
+#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit.
+#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit.
+#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit.
+#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type
+#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY
+#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access.
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TDES structure *** */
-#define TDES_CR ( 0 ) /* Control Register */
-#define TDES_MR ( 4 ) /* Mode Register */
-#define TDES_IER ( 16 ) /* Interrupt Enable Register */
-#define TDES_IDR ( 20 ) /* Interrupt Disable Register */
-#define TDES_IMR ( 24 ) /* Interrupt Mask Register */
-#define TDES_ISR ( 28 ) /* Interrupt Status Register */
-#define TDES_KEY1WxR ( 32 ) /* Key 1 Word x Register */
-#define TDES_KEY2WxR ( 40 ) /* Key 2 Word x Register */
-#define TDES_KEY3WxR ( 48 ) /* Key 3 Word x Register */
-#define TDES_IDATAxR ( 64 ) /* Input Data x Register */
-#define TDES_ODATAxR ( 80 ) /* Output Data x Register */
-#define TDES_IVxR ( 96 ) /* Initialization Vector x Register */
-#define TDES_VR ( 252 ) /* TDES Version Register */
-#define TDES_RPR ( 256 ) /* Receive Pointer Register */
-#define TDES_RCR ( 260 ) /* Receive Counter Register */
-#define TDES_TPR ( 264 ) /* Transmit Pointer Register */
-#define TDES_TCR ( 268 ) /* Transmit Counter Register */
-#define TDES_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define TDES_RNCR ( 276 ) /* Receive Next Counter Register */
-#define TDES_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define TDES_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define TDES_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define TDES_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
-#define AT91C_TDES_START ( 0x1 << 0 ) /* (TDES) Starts Processing */
-#define AT91C_TDES_SWRST ( 0x1 << 8 ) /* (TDES) Software Reset */
-/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
-#define AT91C_TDES_CIPHER ( 0x1 << 0 ) /* (TDES) Processing Mode */
-#define AT91C_TDES_TDESMOD ( 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */
-#define AT91C_TDES_KEYMOD ( 0x1 << 4 ) /* (TDES) Key Mode */
-#define AT91C_TDES_SMOD ( 0x3 << 8 ) /* (TDES) Start Mode */
-#define AT91C_TDES_SMOD_MANUAL ( 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
-#define AT91C_TDES_SMOD_AUTO ( 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
-#define AT91C_TDES_SMOD_PDC ( 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */
-#define AT91C_TDES_OPMOD ( 0x3 << 12 ) /* (TDES) Operation Mode */
-#define AT91C_TDES_OPMOD_ECB ( 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
-#define AT91C_TDES_OPMOD_CBC ( 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
-#define AT91C_TDES_OPMOD_OFB ( 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
-#define AT91C_TDES_OPMOD_CFB ( 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
-#define AT91C_TDES_LOD ( 0x1 << 15 ) /* (TDES) Last Output Data Mode */
-#define AT91C_TDES_CFBS ( 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
-#define AT91C_TDES_CFBS_64_BIT ( 0x0 << 16 ) /* (TDES) 64-bit. */
-#define AT91C_TDES_CFBS_32_BIT ( 0x1 << 16 ) /* (TDES) 32-bit. */
-#define AT91C_TDES_CFBS_16_BIT ( 0x2 << 16 ) /* (TDES) 16-bit. */
-#define AT91C_TDES_CFBS_8_BIT ( 0x3 << 16 ) /* (TDES) 8-bit. */
-/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_TDES_DATRDY ( 0x1 << 0 ) /* (TDES) DATRDY */
-#define AT91C_TDES_ENDRX ( 0x1 << 1 ) /* (TDES) PDC Read Buffer End */
-#define AT91C_TDES_ENDTX ( 0x1 << 2 ) /* (TDES) PDC Write Buffer End */
-#define AT91C_TDES_RXBUFF ( 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */
-#define AT91C_TDES_TXBUFE ( 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */
-#define AT91C_TDES_URAD ( 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */
-/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_TDES_URAT ( 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
-#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
-#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
-#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
-#define AT91C_TDES_URAT_WO_REG_READ ( 0x3 << 12 ) /* (TDES) Write-only register read access. */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_TDES structure ***
+#define TDES_CR ( 0) // Control Register
+#define TDES_MR ( 4) // Mode Register
+#define TDES_IER (16) // Interrupt Enable Register
+#define TDES_IDR (20) // Interrupt Disable Register
+#define TDES_IMR (24) // Interrupt Mask Register
+#define TDES_ISR (28) // Interrupt Status Register
+#define TDES_KEY1WxR (32) // Key 1 Word x Register
+#define TDES_KEY2WxR (40) // Key 2 Word x Register
+#define TDES_KEY3WxR (48) // Key 3 Word x Register
+#define TDES_IDATAxR (64) // Input Data x Register
+#define TDES_ODATAxR (80) // Output Data x Register
+#define TDES_IVxR (96) // Initialization Vector x Register
+#define TDES_VR (252) // TDES Version Register
+#define TDES_RPR (256) // Receive Pointer Register
+#define TDES_RCR (260) // Receive Counter Register
+#define TDES_TPR (264) // Transmit Pointer Register
+#define TDES_TCR (268) // Transmit Counter Register
+#define TDES_RNPR (272) // Receive Next Pointer Register
+#define TDES_RNCR (276) // Receive Next Counter Register
+#define TDES_TNPR (280) // Transmit Next Pointer Register
+#define TDES_TNCR (284) // Transmit Next Counter Register
+#define TDES_PTCR (288) // PDC Transfer Control Register
+#define TDES_PTSR (292) // PDC Transfer Status Register
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
+#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
+#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode
+#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode
+#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit.
+#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit.
+#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit.
+#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
+#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access.
-/* ***************************************************************************** */
-/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 */
-/* ***************************************************************************** */
-/* ========== Register definition for SYS peripheral ========== */
-/* ========== Register definition for AIC peripheral ========== */
-#define AT91C_AIC_IVR ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
-#define AT91C_AIC_SMR ( 0xFFFFF000 ) /* (AIC) Source Mode Register */
-#define AT91C_AIC_FVR ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
-#define AT91C_AIC_DCR ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
-#define AT91C_AIC_EOICR ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
-#define AT91C_AIC_SVR ( 0xFFFFF080 ) /* (AIC) Source Vector Register */
-#define AT91C_AIC_FFSR ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
-#define AT91C_AIC_ICCR ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
-#define AT91C_AIC_ISR ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
-#define AT91C_AIC_IMR ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
-#define AT91C_AIC_IPR ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
-#define AT91C_AIC_FFER ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
-#define AT91C_AIC_IECR ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
-#define AT91C_AIC_ISCR ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
-#define AT91C_AIC_FFDR ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
-#define AT91C_AIC_CISR ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
-#define AT91C_AIC_IDCR ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
-#define AT91C_AIC_SPU ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
-/* ========== Register definition for PDC_DBGU peripheral ========== */
-#define AT91C_DBGU_TCR ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
-#define AT91C_DBGU_RNPR ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
-#define AT91C_DBGU_TNPR ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
-#define AT91C_DBGU_TPR ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
-#define AT91C_DBGU_RPR ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
-#define AT91C_DBGU_RCR ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
-#define AT91C_DBGU_RNCR ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
-#define AT91C_DBGU_PTCR ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
-#define AT91C_DBGU_PTSR ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
-#define AT91C_DBGU_TNCR ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
-/* ========== Register definition for DBGU peripheral ========== */
-#define AT91C_DBGU_EXID ( 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
-#define AT91C_DBGU_BRGR ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
-#define AT91C_DBGU_IDR ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
-#define AT91C_DBGU_CSR ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */
-#define AT91C_DBGU_CIDR ( 0xFFFFF240 ) /* (DBGU) Chip ID Register */
-#define AT91C_DBGU_MR ( 0xFFFFF204 ) /* (DBGU) Mode Register */
-#define AT91C_DBGU_IMR ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
-#define AT91C_DBGU_CR ( 0xFFFFF200 ) /* (DBGU) Control Register */
-#define AT91C_DBGU_FNTR ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
-#define AT91C_DBGU_THR ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
-#define AT91C_DBGU_RHR ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
-#define AT91C_DBGU_IER ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
-/* ========== Register definition for PIOA peripheral ========== */
-#define AT91C_PIOA_ODR ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
-#define AT91C_PIOA_SODR ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
-#define AT91C_PIOA_ISR ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
-#define AT91C_PIOA_ABSR ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
-#define AT91C_PIOA_IER ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
-#define AT91C_PIOA_PPUDR ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
-#define AT91C_PIOA_IMR ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
-#define AT91C_PIOA_PER ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_IFDR ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
-#define AT91C_PIOA_OWDR ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
-#define AT91C_PIOA_MDSR ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
-#define AT91C_PIOA_IDR ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
-#define AT91C_PIOA_ODSR ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
-#define AT91C_PIOA_PPUSR ( 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
-#define AT91C_PIOA_OWSR ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
-#define AT91C_PIOA_BSR ( 0xFFFFF474 ) /* (PIOA) Select B Register */
-#define AT91C_PIOA_OWER ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
-#define AT91C_PIOA_IFER ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
-#define AT91C_PIOA_PDSR ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
-#define AT91C_PIOA_PPUER ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
-#define AT91C_PIOA_OSR ( 0xFFFFF418 ) /* (PIOA) Output Status Register */
-#define AT91C_PIOA_ASR ( 0xFFFFF470 ) /* (PIOA) Select A Register */
-#define AT91C_PIOA_MDDR ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
-#define AT91C_PIOA_CODR ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
-#define AT91C_PIOA_MDER ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
-#define AT91C_PIOA_PDR ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_IFSR ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
-#define AT91C_PIOA_OER ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */
-#define AT91C_PIOA_PSR ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */
-/* ========== Register definition for PIOB peripheral ========== */
-#define AT91C_PIOB_OWDR ( 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
-#define AT91C_PIOB_MDER ( 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
-#define AT91C_PIOB_PPUSR ( 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
-#define AT91C_PIOB_IMR ( 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
-#define AT91C_PIOB_ASR ( 0xFFFFF670 ) /* (PIOB) Select A Register */
-#define AT91C_PIOB_PPUDR ( 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
-#define AT91C_PIOB_PSR ( 0xFFFFF608 ) /* (PIOB) PIO Status Register */
-#define AT91C_PIOB_IER ( 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
-#define AT91C_PIOB_CODR ( 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
-#define AT91C_PIOB_OWER ( 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
-#define AT91C_PIOB_ABSR ( 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
-#define AT91C_PIOB_IFDR ( 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
-#define AT91C_PIOB_PDSR ( 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
-#define AT91C_PIOB_IDR ( 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
-#define AT91C_PIOB_OWSR ( 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
-#define AT91C_PIOB_PDR ( 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
-#define AT91C_PIOB_ODR ( 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_IFSR ( 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
-#define AT91C_PIOB_PPUER ( 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
-#define AT91C_PIOB_SODR ( 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
-#define AT91C_PIOB_ISR ( 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
-#define AT91C_PIOB_ODSR ( 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
-#define AT91C_PIOB_OSR ( 0xFFFFF618 ) /* (PIOB) Output Status Register */
-#define AT91C_PIOB_MDSR ( 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
-#define AT91C_PIOB_IFER ( 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
-#define AT91C_PIOB_BSR ( 0xFFFFF674 ) /* (PIOB) Select B Register */
-#define AT91C_PIOB_MDDR ( 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
-#define AT91C_PIOB_OER ( 0xFFFFF610 ) /* (PIOB) Output Enable Register */
-#define AT91C_PIOB_PER ( 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
-/* ========== Register definition for CKGR peripheral ========== */
-#define AT91C_CKGR_MOR ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
-#define AT91C_CKGR_PLLR ( 0xFFFFFC2C ) /* (CKGR) PLL Register */
-#define AT91C_CKGR_MCFR ( 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */
-/* ========== Register definition for PMC peripheral ========== */
-#define AT91C_PMC_IDR ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
-#define AT91C_PMC_MOR ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
-#define AT91C_PMC_PLLR ( 0xFFFFFC2C ) /* (PMC) PLL Register */
-#define AT91C_PMC_PCER ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCKR ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
-#define AT91C_PMC_MCKR ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */
-#define AT91C_PMC_SCDR ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
-#define AT91C_PMC_PCDR ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
-#define AT91C_PMC_SCSR ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
-#define AT91C_PMC_PCSR ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
-#define AT91C_PMC_MCFR ( 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */
-#define AT91C_PMC_SCER ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
-#define AT91C_PMC_IMR ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
-#define AT91C_PMC_IER ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
-#define AT91C_PMC_SR ( 0xFFFFFC68 ) /* (PMC) Status Register */
-/* ========== Register definition for RSTC peripheral ========== */
-#define AT91C_RSTC_RCR ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
-#define AT91C_RSTC_RMR ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
-#define AT91C_RSTC_RSR ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
-/* ========== Register definition for RTTC peripheral ========== */
-#define AT91C_RTTC_RTSR ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
-#define AT91C_RTTC_RTMR ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
-#define AT91C_RTTC_RTVR ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
-#define AT91C_RTTC_RTAR ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
-/* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIVR ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
-#define AT91C_PITC_PISR ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
-#define AT91C_PITC_PIIR ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
-#define AT91C_PITC_PIMR ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
-/* ========== Register definition for WDTC peripheral ========== */
-#define AT91C_WDTC_WDCR ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
-#define AT91C_WDTC_WDSR ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
-#define AT91C_WDTC_WDMR ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
-/* ========== Register definition for VREG peripheral ========== */
-#define AT91C_VREG_MR ( 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
-/* ========== Register definition for MC peripheral ========== */
-#define AT91C_MC_ASR ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
-#define AT91C_MC_RCR ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
-#define AT91C_MC_FCR ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
-#define AT91C_MC_AASR ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
-#define AT91C_MC_FSR ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
-#define AT91C_MC_FMR ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
-/* ========== Register definition for PDC_SPI1 peripheral ========== */
-#define AT91C_SPI1_PTCR ( 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
-#define AT91C_SPI1_RPR ( 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
-#define AT91C_SPI1_TNCR ( 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
-#define AT91C_SPI1_TPR ( 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
-#define AT91C_SPI1_TNPR ( 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
-#define AT91C_SPI1_TCR ( 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
-#define AT91C_SPI1_RCR ( 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
-#define AT91C_SPI1_RNPR ( 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
-#define AT91C_SPI1_RNCR ( 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
-#define AT91C_SPI1_PTSR ( 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
-/* ========== Register definition for SPI1 peripheral ========== */
-#define AT91C_SPI1_IMR ( 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
-#define AT91C_SPI1_IER ( 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
-#define AT91C_SPI1_MR ( 0xFFFE4004 ) /* (SPI1) Mode Register */
-#define AT91C_SPI1_RDR ( 0xFFFE4008 ) /* (SPI1) Receive Data Register */
-#define AT91C_SPI1_IDR ( 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
-#define AT91C_SPI1_SR ( 0xFFFE4010 ) /* (SPI1) Status Register */
-#define AT91C_SPI1_TDR ( 0xFFFE400C ) /* (SPI1) Transmit Data Register */
-#define AT91C_SPI1_CR ( 0xFFFE4000 ) /* (SPI1) Control Register */
-#define AT91C_SPI1_CSR ( 0xFFFE4030 ) /* (SPI1) Chip Select Register */
-/* ========== Register definition for PDC_SPI0 peripheral ========== */
-#define AT91C_SPI0_PTCR ( 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
-#define AT91C_SPI0_TPR ( 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
-#define AT91C_SPI0_TCR ( 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
-#define AT91C_SPI0_RCR ( 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
-#define AT91C_SPI0_PTSR ( 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
-#define AT91C_SPI0_RNPR ( 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
-#define AT91C_SPI0_RPR ( 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
-#define AT91C_SPI0_TNCR ( 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
-#define AT91C_SPI0_RNCR ( 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
-#define AT91C_SPI0_TNPR ( 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
-/* ========== Register definition for SPI0 peripheral ========== */
-#define AT91C_SPI0_IER ( 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
-#define AT91C_SPI0_SR ( 0xFFFE0010 ) /* (SPI0) Status Register */
-#define AT91C_SPI0_IDR ( 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
-#define AT91C_SPI0_CR ( 0xFFFE0000 ) /* (SPI0) Control Register */
-#define AT91C_SPI0_MR ( 0xFFFE0004 ) /* (SPI0) Mode Register */
-#define AT91C_SPI0_IMR ( 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
-#define AT91C_SPI0_TDR ( 0xFFFE000C ) /* (SPI0) Transmit Data Register */
-#define AT91C_SPI0_RDR ( 0xFFFE0008 ) /* (SPI0) Receive Data Register */
-#define AT91C_SPI0_CSR ( 0xFFFE0030 ) /* (SPI0) Chip Select Register */
-/* ========== Register definition for PDC_US1 peripheral ========== */
-#define AT91C_US1_RNCR ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
-#define AT91C_US1_PTCR ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
-#define AT91C_US1_TCR ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
-#define AT91C_US1_PTSR ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
-#define AT91C_US1_TNPR ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
-#define AT91C_US1_RCR ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
-#define AT91C_US1_RNPR ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
-#define AT91C_US1_RPR ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
-#define AT91C_US1_TNCR ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
-#define AT91C_US1_TPR ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
-/* ========== Register definition for US1 peripheral ========== */
-#define AT91C_US1_IF ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
-#define AT91C_US1_NER ( 0xFFFC4044 ) /* (US1) Nb Errors Register */
-#define AT91C_US1_RTOR ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
-#define AT91C_US1_CSR ( 0xFFFC4014 ) /* (US1) Channel Status Register */
-#define AT91C_US1_IDR ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */
-#define AT91C_US1_IER ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
-#define AT91C_US1_THR ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */
-#define AT91C_US1_TTGR ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
-#define AT91C_US1_RHR ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */
-#define AT91C_US1_BRGR ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
-#define AT91C_US1_IMR ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
-#define AT91C_US1_FIDI ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
-#define AT91C_US1_CR ( 0xFFFC4000 ) /* (US1) Control Register */
-#define AT91C_US1_MR ( 0xFFFC4004 ) /* (US1) Mode Register */
-/* ========== Register definition for PDC_US0 peripheral ========== */
-#define AT91C_US0_TNPR ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
-#define AT91C_US0_RNPR ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
-#define AT91C_US0_TCR ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
-#define AT91C_US0_PTCR ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
-#define AT91C_US0_PTSR ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
-#define AT91C_US0_TNCR ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
-#define AT91C_US0_TPR ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
-#define AT91C_US0_RCR ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
-#define AT91C_US0_RPR ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
-#define AT91C_US0_RNCR ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
-/* ========== Register definition for US0 peripheral ========== */
-#define AT91C_US0_BRGR ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
-#define AT91C_US0_NER ( 0xFFFC0044 ) /* (US0) Nb Errors Register */
-#define AT91C_US0_CR ( 0xFFFC0000 ) /* (US0) Control Register */
-#define AT91C_US0_IMR ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
-#define AT91C_US0_FIDI ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
-#define AT91C_US0_TTGR ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
-#define AT91C_US0_MR ( 0xFFFC0004 ) /* (US0) Mode Register */
-#define AT91C_US0_RTOR ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
-#define AT91C_US0_CSR ( 0xFFFC0014 ) /* (US0) Channel Status Register */
-#define AT91C_US0_RHR ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */
-#define AT91C_US0_IDR ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */
-#define AT91C_US0_THR ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */
-#define AT91C_US0_IF ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
-#define AT91C_US0_IER ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
-/* ========== Register definition for PDC_SSC peripheral ========== */
-#define AT91C_SSC_TNCR ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
-#define AT91C_SSC_RPR ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
-#define AT91C_SSC_RNCR ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
-#define AT91C_SSC_TPR ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
-#define AT91C_SSC_PTCR ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
-#define AT91C_SSC_TCR ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
-#define AT91C_SSC_RCR ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
-#define AT91C_SSC_RNPR ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
-#define AT91C_SSC_TNPR ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
-#define AT91C_SSC_PTSR ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
-/* ========== Register definition for SSC peripheral ========== */
-#define AT91C_SSC_RHR ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */
-#define AT91C_SSC_RSHR ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
-#define AT91C_SSC_TFMR ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
-#define AT91C_SSC_IDR ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
-#define AT91C_SSC_THR ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
-#define AT91C_SSC_RCMR ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
-#define AT91C_SSC_IER ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
-#define AT91C_SSC_TSHR ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
-#define AT91C_SSC_SR ( 0xFFFD4040 ) /* (SSC) Status Register */
-#define AT91C_SSC_CMR ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */
-#define AT91C_SSC_TCMR ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
-#define AT91C_SSC_CR ( 0xFFFD4000 ) /* (SSC) Control Register */
-#define AT91C_SSC_IMR ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
-#define AT91C_SSC_RFMR ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
-/* ========== Register definition for TWI peripheral ========== */
-#define AT91C_TWI_IER ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
-#define AT91C_TWI_CR ( 0xFFFB8000 ) /* (TWI) Control Register */
-#define AT91C_TWI_SR ( 0xFFFB8020 ) /* (TWI) Status Register */
-#define AT91C_TWI_IMR ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
-#define AT91C_TWI_THR ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
-#define AT91C_TWI_IDR ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
-#define AT91C_TWI_IADR ( 0xFFFB800C ) /* (TWI) Internal Address Register */
-#define AT91C_TWI_MMR ( 0xFFFB8004 ) /* (TWI) Master Mode Register */
-#define AT91C_TWI_CWGR ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
-#define AT91C_TWI_RHR ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */
-/* ========== Register definition for PWMC_CH3 peripheral ========== */
-#define AT91C_PWMC_CH3_CUPDR ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
-#define AT91C_PWMC_CH3_Reserved ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
-#define AT91C_PWMC_CH3_CPRDR ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
-#define AT91C_PWMC_CH3_CDTYR ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH3_CCNTR ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
-#define AT91C_PWMC_CH3_CMR ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
-/* ========== Register definition for PWMC_CH2 peripheral ========== */
-#define AT91C_PWMC_CH2_Reserved ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
-#define AT91C_PWMC_CH2_CMR ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
-#define AT91C_PWMC_CH2_CCNTR ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
-#define AT91C_PWMC_CH2_CPRDR ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
-#define AT91C_PWMC_CH2_CUPDR ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
-#define AT91C_PWMC_CH2_CDTYR ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH1 peripheral ========== */
-#define AT91C_PWMC_CH1_Reserved ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
-#define AT91C_PWMC_CH1_CUPDR ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
-#define AT91C_PWMC_CH1_CPRDR ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
-#define AT91C_PWMC_CH1_CCNTR ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
-#define AT91C_PWMC_CH1_CDTYR ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH1_CMR ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
-/* ========== Register definition for PWMC_CH0 peripheral ========== */
-#define AT91C_PWMC_CH0_Reserved ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
-#define AT91C_PWMC_CH0_CPRDR ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
-#define AT91C_PWMC_CH0_CDTYR ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH0_CMR ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
-#define AT91C_PWMC_CH0_CUPDR ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
-#define AT91C_PWMC_CH0_CCNTR ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
-/* ========== Register definition for PWMC peripheral ========== */
-#define AT91C_PWMC_IDR ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
-#define AT91C_PWMC_DIS ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
-#define AT91C_PWMC_IER ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
-#define AT91C_PWMC_VR ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
-#define AT91C_PWMC_ISR ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
-#define AT91C_PWMC_SR ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
-#define AT91C_PWMC_IMR ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
-#define AT91C_PWMC_MR ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
-#define AT91C_PWMC_ENA ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
-/* ========== Register definition for UDP peripheral ========== */
-#define AT91C_UDP_IMR ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
-#define AT91C_UDP_FADDR ( 0xFFFB0008 ) /* (UDP) Function Address Register */
-#define AT91C_UDP_NUM ( 0xFFFB0000 ) /* (UDP) Frame Number Register */
-#define AT91C_UDP_FDR ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
-#define AT91C_UDP_ISR ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */
-#define AT91C_UDP_CSR ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
-#define AT91C_UDP_IDR ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
-#define AT91C_UDP_ICR ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
-#define AT91C_UDP_RSTEP ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
-#define AT91C_UDP_TXVC ( 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
-#define AT91C_UDP_GLBSTATE ( 0xFFFB0004 ) /* (UDP) Global State Register */
-#define AT91C_UDP_IER ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
-/* ========== Register definition for TC0 peripheral ========== */
-#define AT91C_TC0_SR ( 0xFFFA0020 ) /* (TC0) Status Register */
-#define AT91C_TC0_RC ( 0xFFFA001C ) /* (TC0) Register C */
-#define AT91C_TC0_RB ( 0xFFFA0018 ) /* (TC0) Register B */
-#define AT91C_TC0_CCR ( 0xFFFA0000 ) /* (TC0) Channel Control Register */
-#define AT91C_TC0_CMR ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC0_IER ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
-#define AT91C_TC0_RA ( 0xFFFA0014 ) /* (TC0) Register A */
-#define AT91C_TC0_IDR ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
-#define AT91C_TC0_CV ( 0xFFFA0010 ) /* (TC0) Counter Value */
-#define AT91C_TC0_IMR ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
-/* ========== Register definition for TC1 peripheral ========== */
-#define AT91C_TC1_RB ( 0xFFFA0058 ) /* (TC1) Register B */
-#define AT91C_TC1_CCR ( 0xFFFA0040 ) /* (TC1) Channel Control Register */
-#define AT91C_TC1_IER ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
-#define AT91C_TC1_IDR ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
-#define AT91C_TC1_SR ( 0xFFFA0060 ) /* (TC1) Status Register */
-#define AT91C_TC1_CMR ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC1_RA ( 0xFFFA0054 ) /* (TC1) Register A */
-#define AT91C_TC1_RC ( 0xFFFA005C ) /* (TC1) Register C */
-#define AT91C_TC1_IMR ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
-#define AT91C_TC1_CV ( 0xFFFA0050 ) /* (TC1) Counter Value */
-/* ========== Register definition for TC2 peripheral ========== */
-#define AT91C_TC2_CMR ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC2_CCR ( 0xFFFA0080 ) /* (TC2) Channel Control Register */
-#define AT91C_TC2_CV ( 0xFFFA0090 ) /* (TC2) Counter Value */
-#define AT91C_TC2_RA ( 0xFFFA0094 ) /* (TC2) Register A */
-#define AT91C_TC2_RB ( 0xFFFA0098 ) /* (TC2) Register B */
-#define AT91C_TC2_IDR ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
-#define AT91C_TC2_IMR ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
-#define AT91C_TC2_RC ( 0xFFFA009C ) /* (TC2) Register C */
-#define AT91C_TC2_IER ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
-#define AT91C_TC2_SR ( 0xFFFA00A0 ) /* (TC2) Status Register */
-/* ========== Register definition for TCB peripheral ========== */
-#define AT91C_TCB_BMR ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
-#define AT91C_TCB_BCR ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
-/* ========== Register definition for CAN_MB0 peripheral ========== */
-#define AT91C_CAN_MB0_MDL ( 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
-#define AT91C_CAN_MB0_MAM ( 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB0_MCR ( 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
-#define AT91C_CAN_MB0_MID ( 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
-#define AT91C_CAN_MB0_MSR ( 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
-#define AT91C_CAN_MB0_MFID ( 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
-#define AT91C_CAN_MB0_MDH ( 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
-#define AT91C_CAN_MB0_MMR ( 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
-/* ========== Register definition for CAN_MB1 peripheral ========== */
-#define AT91C_CAN_MB1_MDL ( 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
-#define AT91C_CAN_MB1_MID ( 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
-#define AT91C_CAN_MB1_MMR ( 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
-#define AT91C_CAN_MB1_MSR ( 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
-#define AT91C_CAN_MB1_MAM ( 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB1_MDH ( 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
-#define AT91C_CAN_MB1_MCR ( 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
-#define AT91C_CAN_MB1_MFID ( 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
-/* ========== Register definition for CAN_MB2 peripheral ========== */
-#define AT91C_CAN_MB2_MCR ( 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
-#define AT91C_CAN_MB2_MDH ( 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
-#define AT91C_CAN_MB2_MID ( 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
-#define AT91C_CAN_MB2_MDL ( 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
-#define AT91C_CAN_MB2_MMR ( 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
-#define AT91C_CAN_MB2_MAM ( 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB2_MFID ( 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
-#define AT91C_CAN_MB2_MSR ( 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
-/* ========== Register definition for CAN_MB3 peripheral ========== */
-#define AT91C_CAN_MB3_MFID ( 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
-#define AT91C_CAN_MB3_MAM ( 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB3_MID ( 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
-#define AT91C_CAN_MB3_MCR ( 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
-#define AT91C_CAN_MB3_MMR ( 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
-#define AT91C_CAN_MB3_MSR ( 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
-#define AT91C_CAN_MB3_MDL ( 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
-#define AT91C_CAN_MB3_MDH ( 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
-/* ========== Register definition for CAN_MB4 peripheral ========== */
-#define AT91C_CAN_MB4_MID ( 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
-#define AT91C_CAN_MB4_MMR ( 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
-#define AT91C_CAN_MB4_MDH ( 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
-#define AT91C_CAN_MB4_MFID ( 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
-#define AT91C_CAN_MB4_MSR ( 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
-#define AT91C_CAN_MB4_MCR ( 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
-#define AT91C_CAN_MB4_MDL ( 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
-#define AT91C_CAN_MB4_MAM ( 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB5 peripheral ========== */
-#define AT91C_CAN_MB5_MSR ( 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
-#define AT91C_CAN_MB5_MCR ( 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
-#define AT91C_CAN_MB5_MFID ( 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
-#define AT91C_CAN_MB5_MDH ( 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
-#define AT91C_CAN_MB5_MID ( 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
-#define AT91C_CAN_MB5_MMR ( 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
-#define AT91C_CAN_MB5_MDL ( 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
-#define AT91C_CAN_MB5_MAM ( 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB6 peripheral ========== */
-#define AT91C_CAN_MB6_MFID ( 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
-#define AT91C_CAN_MB6_MID ( 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
-#define AT91C_CAN_MB6_MAM ( 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB6_MSR ( 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
-#define AT91C_CAN_MB6_MDL ( 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
-#define AT91C_CAN_MB6_MCR ( 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
-#define AT91C_CAN_MB6_MDH ( 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
-#define AT91C_CAN_MB6_MMR ( 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
-/* ========== Register definition for CAN_MB7 peripheral ========== */
-#define AT91C_CAN_MB7_MCR ( 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
-#define AT91C_CAN_MB7_MDH ( 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
-#define AT91C_CAN_MB7_MFID ( 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
-#define AT91C_CAN_MB7_MDL ( 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
-#define AT91C_CAN_MB7_MID ( 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
-#define AT91C_CAN_MB7_MMR ( 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
-#define AT91C_CAN_MB7_MAM ( 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB7_MSR ( 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
-/* ========== Register definition for CAN peripheral ========== */
-#define AT91C_CAN_TCR ( 0xFFFD0024 ) /* (CAN) Transfer Command Register */
-#define AT91C_CAN_IMR ( 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
-#define AT91C_CAN_IER ( 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
-#define AT91C_CAN_ECR ( 0xFFFD0020 ) /* (CAN) Error Counter Register */
-#define AT91C_CAN_TIMESTP ( 0xFFFD001C ) /* (CAN) Time Stamp Register */
-#define AT91C_CAN_MR ( 0xFFFD0000 ) /* (CAN) Mode Register */
-#define AT91C_CAN_IDR ( 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
-#define AT91C_CAN_ACR ( 0xFFFD0028 ) /* (CAN) Abort Command Register */
-#define AT91C_CAN_TIM ( 0xFFFD0018 ) /* (CAN) Timer Register */
-#define AT91C_CAN_SR ( 0xFFFD0010 ) /* (CAN) Status Register */
-#define AT91C_CAN_BR ( 0xFFFD0014 ) /* (CAN) Baudrate Register */
-#define AT91C_CAN_VR ( 0xFFFD00FC ) /* (CAN) Version Register */
-/* ========== Register definition for EMAC peripheral ========== */
-#define AT91C_EMAC_ISR ( 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
-#define AT91C_EMAC_SA4H ( 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
-#define AT91C_EMAC_SA1L ( 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
-#define AT91C_EMAC_ELE ( 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
-#define AT91C_EMAC_LCOL ( 0xFFFDC05C ) /* (EMAC) Late Collision Register */
-#define AT91C_EMAC_RLE ( 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
-#define AT91C_EMAC_WOL ( 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
-#define AT91C_EMAC_DTF ( 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
-#define AT91C_EMAC_TUND ( 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
-#define AT91C_EMAC_NCR ( 0xFFFDC000 ) /* (EMAC) Network Control Register */
-#define AT91C_EMAC_SA4L ( 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
-#define AT91C_EMAC_RSR ( 0xFFFDC020 ) /* (EMAC) Receive Status Register */
-#define AT91C_EMAC_SA3L ( 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
-#define AT91C_EMAC_TSR ( 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
-#define AT91C_EMAC_IDR ( 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
-#define AT91C_EMAC_RSE ( 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
-#define AT91C_EMAC_ECOL ( 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
-#define AT91C_EMAC_TID ( 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
-#define AT91C_EMAC_HRB ( 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
-#define AT91C_EMAC_TBQP ( 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
-#define AT91C_EMAC_USRIO ( 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
-#define AT91C_EMAC_PTR ( 0xFFFDC038 ) /* (EMAC) Pause Time Register */
-#define AT91C_EMAC_SA2H ( 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
-#define AT91C_EMAC_ROV ( 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
-#define AT91C_EMAC_ALE ( 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
-#define AT91C_EMAC_RJA ( 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
-#define AT91C_EMAC_RBQP ( 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
-#define AT91C_EMAC_TPF ( 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
-#define AT91C_EMAC_NCFGR ( 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
-#define AT91C_EMAC_HRT ( 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
-#define AT91C_EMAC_USF ( 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
-#define AT91C_EMAC_FCSE ( 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
-#define AT91C_EMAC_TPQ ( 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
-#define AT91C_EMAC_MAN ( 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
-#define AT91C_EMAC_FTO ( 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
-#define AT91C_EMAC_REV ( 0xFFFDC0FC ) /* (EMAC) Revision Register */
-#define AT91C_EMAC_IMR ( 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
-#define AT91C_EMAC_SCF ( 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
-#define AT91C_EMAC_PFR ( 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
-#define AT91C_EMAC_MCF ( 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
-#define AT91C_EMAC_NSR ( 0xFFFDC008 ) /* (EMAC) Network Status Register */
-#define AT91C_EMAC_SA2L ( 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
-#define AT91C_EMAC_FRO ( 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
-#define AT91C_EMAC_IER ( 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
-#define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
-#define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
-#define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
-#define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
-/* ========== Register definition for PDC_ADC peripheral ========== */
-#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
-#define AT91C_ADC_PTCR ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
-#define AT91C_ADC_TNPR ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
-#define AT91C_ADC_TNCR ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
-#define AT91C_ADC_RNPR ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
-#define AT91C_ADC_RNCR ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
-#define AT91C_ADC_RPR ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
-#define AT91C_ADC_TCR ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
-#define AT91C_ADC_TPR ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
-#define AT91C_ADC_RCR ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
-/* ========== Register definition for ADC peripheral ========== */
-#define AT91C_ADC_CDR2 ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
-#define AT91C_ADC_CDR3 ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
-#define AT91C_ADC_CDR0 ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
-#define AT91C_ADC_CDR5 ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
-#define AT91C_ADC_CHDR ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
-#define AT91C_ADC_SR ( 0xFFFD801C ) /* (ADC) ADC Status Register */
-#define AT91C_ADC_CDR4 ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
-#define AT91C_ADC_CDR1 ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
-#define AT91C_ADC_LCDR ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
-#define AT91C_ADC_IDR ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
-#define AT91C_ADC_CR ( 0xFFFD8000 ) /* (ADC) ADC Control Register */
-#define AT91C_ADC_CDR7 ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
-#define AT91C_ADC_CDR6 ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
-#define AT91C_ADC_IER ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
-#define AT91C_ADC_CHER ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
-#define AT91C_ADC_CHSR ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
-#define AT91C_ADC_MR ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */
-#define AT91C_ADC_IMR ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
-/* ========== Register definition for PDC_AES peripheral ========== */
-#define AT91C_AES_TPR ( 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
-#define AT91C_AES_PTCR ( 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
-#define AT91C_AES_RNPR ( 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
-#define AT91C_AES_TNCR ( 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
-#define AT91C_AES_TCR ( 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
-#define AT91C_AES_RCR ( 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
-#define AT91C_AES_RNCR ( 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
-#define AT91C_AES_TNPR ( 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
-#define AT91C_AES_RPR ( 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
-#define AT91C_AES_PTSR ( 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
-/* ========== Register definition for AES peripheral ========== */
-#define AT91C_AES_IVxR ( 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
-#define AT91C_AES_MR ( 0xFFFA4004 ) /* (AES) Mode Register */
-#define AT91C_AES_VR ( 0xFFFA40FC ) /* (AES) AES Version Register */
-#define AT91C_AES_ODATAxR ( 0xFFFA4050 ) /* (AES) Output Data x Register */
-#define AT91C_AES_IDATAxR ( 0xFFFA4040 ) /* (AES) Input Data x Register */
-#define AT91C_AES_CR ( 0xFFFA4000 ) /* (AES) Control Register */
-#define AT91C_AES_IDR ( 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
-#define AT91C_AES_IMR ( 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
-#define AT91C_AES_IER ( 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
-#define AT91C_AES_KEYWxR ( 0xFFFA4020 ) /* (AES) Key Word x Register */
-#define AT91C_AES_ISR ( 0xFFFA401C ) /* (AES) Interrupt Status Register */
-/* ========== Register definition for PDC_TDES peripheral ========== */
-#define AT91C_TDES_RNCR ( 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
-#define AT91C_TDES_TCR ( 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
-#define AT91C_TDES_RCR ( 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
-#define AT91C_TDES_TNPR ( 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
-#define AT91C_TDES_RNPR ( 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
-#define AT91C_TDES_RPR ( 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
-#define AT91C_TDES_TNCR ( 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
-#define AT91C_TDES_TPR ( 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
-#define AT91C_TDES_PTSR ( 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
-#define AT91C_TDES_PTCR ( 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
-/* ========== Register definition for TDES peripheral ========== */
-#define AT91C_TDES_KEY2WxR ( 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
-#define AT91C_TDES_KEY3WxR ( 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
-#define AT91C_TDES_IDR ( 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
-#define AT91C_TDES_VR ( 0xFFFA80FC ) /* (TDES) TDES Version Register */
-#define AT91C_TDES_IVxR ( 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
-#define AT91C_TDES_ODATAxR ( 0xFFFA8050 ) /* (TDES) Output Data x Register */
-#define AT91C_TDES_IMR ( 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
-#define AT91C_TDES_MR ( 0xFFFA8004 ) /* (TDES) Mode Register */
-#define AT91C_TDES_CR ( 0xFFFA8000 ) /* (TDES) Control Register */
-#define AT91C_TDES_IER ( 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
-#define AT91C_TDES_ISR ( 0xFFFA801C ) /* (TDES) Interrupt Status Register */
-#define AT91C_TDES_IDATAxR ( 0xFFFA8040 ) /* (TDES) Input Data x Register */
-#define AT91C_TDES_KEY1WxR ( 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ==========
+#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ==========
+#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ==========
+#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ==========
+#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ==========
+#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ==========
+#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ==========
+#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ==========
+#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ==========
+#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ==========
+#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ==========
+#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ==========
+#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ==========
+#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ==========
+#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ==========
+#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ==========
+#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ==========
+#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ==========
+#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register
-/* ***************************************************************************** */
-/* PIO DEFINITIONS FOR AT91SAM7X128 */
-/* ***************************************************************************** */
-#define AT91C_PIO_PA0 ( 1 << 0 ) /* Pin Controlled by PA0 */
-#define AT91C_PA0_RXD0 ( AT91C_PIO_PA0 ) /* USART 0 Receive Data */
-#define AT91C_PIO_PA1 ( 1 << 1 ) /* Pin Controlled by PA1 */
-#define AT91C_PA1_TXD0 ( AT91C_PIO_PA1 ) /* USART 0 Transmit Data */
-#define AT91C_PIO_PA10 ( 1 << 10 ) /* Pin Controlled by PA10 */
-#define AT91C_PA10_TWD ( AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */
-#define AT91C_PIO_PA11 ( 1 << 11 ) /* Pin Controlled by PA11 */
-#define AT91C_PA11_TWCK ( AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */
-#define AT91C_PIO_PA12 ( 1 << 12 ) /* Pin Controlled by PA12 */
-#define AT91C_PA12_NPCS00 ( AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA13 ( 1 << 13 ) /* Pin Controlled by PA13 */
-#define AT91C_PA13_NPCS01 ( AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PA13_PCK1 ( AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PA14 ( 1 << 14 ) /* Pin Controlled by PA14 */
-#define AT91C_PA14_NPCS02 ( AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PA14_IRQ1 ( AT91C_PIO_PA14 ) /* External Interrupt 1 */
-#define AT91C_PIO_PA15 ( 1 << 15 ) /* Pin Controlled by PA15 */
-#define AT91C_PA15_NPCS03 ( AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PA15_TCLK2 ( AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */
-#define AT91C_PIO_PA16 ( 1 << 16 ) /* Pin Controlled by PA16 */
-#define AT91C_PA16_MISO0 ( AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */
-#define AT91C_PIO_PA17 ( 1 << 17 ) /* Pin Controlled by PA17 */
-#define AT91C_PA17_MOSI0 ( AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */
-#define AT91C_PIO_PA18 ( 1 << 18 ) /* Pin Controlled by PA18 */
-#define AT91C_PA18_SPCK0 ( AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */
-#define AT91C_PIO_PA19 ( 1 << 19 ) /* Pin Controlled by PA19 */
-#define AT91C_PA19_CANRX ( AT91C_PIO_PA19 ) /* CAN Receive */
-#define AT91C_PIO_PA2 ( 1 << 2 ) /* Pin Controlled by PA2 */
-#define AT91C_PA2_SCK0 ( AT91C_PIO_PA2 ) /* USART 0 Serial Clock */
-#define AT91C_PA2_NPCS11 ( AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA20 ( 1 << 20 ) /* Pin Controlled by PA20 */
-#define AT91C_PA20_CANTX ( AT91C_PIO_PA20 ) /* CAN Transmit */
-#define AT91C_PIO_PA21 ( 1 << 21 ) /* Pin Controlled by PA21 */
-#define AT91C_PA21_TF ( AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */
-#define AT91C_PA21_NPCS10 ( AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA22 ( 1 << 22 ) /* Pin Controlled by PA22 */
-#define AT91C_PA22_TK ( AT91C_PIO_PA22 ) /* SSC Transmit Clock */
-#define AT91C_PA22_SPCK1 ( AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */
-#define AT91C_PIO_PA23 ( 1 << 23 ) /* Pin Controlled by PA23 */
-#define AT91C_PA23_TD ( AT91C_PIO_PA23 ) /* SSC Transmit data */
-#define AT91C_PA23_MOSI1 ( AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */
-#define AT91C_PIO_PA24 ( 1 << 24 ) /* Pin Controlled by PA24 */
-#define AT91C_PA24_RD ( AT91C_PIO_PA24 ) /* SSC Receive Data */
-#define AT91C_PA24_MISO1 ( AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */
-#define AT91C_PIO_PA25 ( 1 << 25 ) /* Pin Controlled by PA25 */
-#define AT91C_PA25_RK ( AT91C_PIO_PA25 ) /* SSC Receive Clock */
-#define AT91C_PA25_NPCS11 ( AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA26 ( 1 << 26 ) /* Pin Controlled by PA26 */
-#define AT91C_PA26_RF ( AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */
-#define AT91C_PA26_NPCS12 ( AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA27 ( 1 << 27 ) /* Pin Controlled by PA27 */
-#define AT91C_PA27_DRXD ( AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */
-#define AT91C_PA27_PCK3 ( AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */
-#define AT91C_PIO_PA28 ( 1 << 28 ) /* Pin Controlled by PA28 */
-#define AT91C_PA28_DTXD ( AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA29 ( 1 << 29 ) /* Pin Controlled by PA29 */
-#define AT91C_PA29_FIQ ( AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */
-#define AT91C_PA29_NPCS13 ( AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA3 ( 1 << 3 ) /* Pin Controlled by PA3 */
-#define AT91C_PA3_RTS0 ( AT91C_PIO_PA3 ) /* USART 0 Ready To Send */
-#define AT91C_PA3_NPCS12 ( AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA30 ( 1 << 30 ) /* Pin Controlled by PA30 */
-#define AT91C_PA30_IRQ0 ( AT91C_PIO_PA30 ) /* External Interrupt 0 */
-#define AT91C_PA30_PCK2 ( AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PA4 ( 1 << 4 ) /* Pin Controlled by PA4 */
-#define AT91C_PA4_CTS0 ( AT91C_PIO_PA4 ) /* USART 0 Clear To Send */
-#define AT91C_PA4_NPCS13 ( AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA5 ( 1 << 5 ) /* Pin Controlled by PA5 */
-#define AT91C_PA5_RXD1 ( AT91C_PIO_PA5 ) /* USART 1 Receive Data */
-#define AT91C_PIO_PA6 ( 1 << 6 ) /* Pin Controlled by PA6 */
-#define AT91C_PA6_TXD1 ( AT91C_PIO_PA6 ) /* USART 1 Transmit Data */
-#define AT91C_PIO_PA7 ( 1 << 7 ) /* Pin Controlled by PA7 */
-#define AT91C_PA7_SCK1 ( AT91C_PIO_PA7 ) /* USART 1 Serial Clock */
-#define AT91C_PA7_NPCS01 ( AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA8 ( 1 << 8 ) /* Pin Controlled by PA8 */
-#define AT91C_PA8_RTS1 ( AT91C_PIO_PA8 ) /* USART 1 Ready To Send */
-#define AT91C_PA8_NPCS02 ( AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA9 ( 1 << 9 ) /* Pin Controlled by PA9 */
-#define AT91C_PA9_CTS1 ( AT91C_PIO_PA9 ) /* USART 1 Clear To Send */
-#define AT91C_PA9_NPCS03 ( AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB0 ( 1 << 0 ) /* Pin Controlled by PB0 */
-#define AT91C_PB0_ETXCK_EREFCK ( AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */
-#define AT91C_PB0_PCK0 ( AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB1 ( 1 << 1 ) /* Pin Controlled by PB1 */
-#define AT91C_PB1_ETXEN ( AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PB10 ( 1 << 10 ) /* Pin Controlled by PB10 */
-#define AT91C_PB10_ETX2 ( AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */
-#define AT91C_PB10_NPCS11 ( AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB11 ( 1 << 11 ) /* Pin Controlled by PB11 */
-#define AT91C_PB11_ETX3 ( AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */
-#define AT91C_PB11_NPCS12 ( AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB12 ( 1 << 12 ) /* Pin Controlled by PB12 */
-#define AT91C_PB12_ETXER ( AT91C_PIO_PB12 ) /* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PB12_TCLK0 ( AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */
-#define AT91C_PIO_PB13 ( 1 << 13 ) /* Pin Controlled by PB13 */
-#define AT91C_PB13_ERX2 ( AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */
-#define AT91C_PB13_NPCS01 ( AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB14 ( 1 << 14 ) /* Pin Controlled by PB14 */
-#define AT91C_PB14_ERX3 ( AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */
-#define AT91C_PB14_NPCS02 ( AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB15 ( 1 << 15 ) /* Pin Controlled by PB15 */
-#define AT91C_PB15_ERXDV ( AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16 ( 1 << 16 ) /* Pin Controlled by PB16 */
-#define AT91C_PB16_ECOL ( AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */
-#define AT91C_PB16_NPCS13 ( AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB17 ( 1 << 17 ) /* Pin Controlled by PB17 */
-#define AT91C_PB17_ERXCK ( AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */
-#define AT91C_PB17_NPCS03 ( AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB18 ( 1 << 18 ) /* Pin Controlled by PB18 */
-#define AT91C_PB18_EF100 ( AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */
-#define AT91C_PB18_ADTRG ( AT91C_PIO_PB18 ) /* ADC External Trigger */
-#define AT91C_PIO_PB19 ( 1 << 19 ) /* Pin Controlled by PB19 */
-#define AT91C_PB19_PWM0 ( AT91C_PIO_PB19 ) /* PWM Channel 0 */
-#define AT91C_PB19_TCLK1 ( AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */
-#define AT91C_PIO_PB2 ( 1 << 2 ) /* Pin Controlled by PB2 */
-#define AT91C_PB2_ETX0 ( AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PB20 ( 1 << 20 ) /* Pin Controlled by PB20 */
-#define AT91C_PB20_PWM1 ( AT91C_PIO_PB20 ) /* PWM Channel 1 */
-#define AT91C_PB20_PCK0 ( AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB21 ( 1 << 21 ) /* Pin Controlled by PB21 */
-#define AT91C_PB21_PWM2 ( AT91C_PIO_PB21 ) /* PWM Channel 2 */
-#define AT91C_PB21_PCK1 ( AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PB22 ( 1 << 22 ) /* Pin Controlled by PB22 */
-#define AT91C_PB22_PWM3 ( AT91C_PIO_PB22 ) /* PWM Channel 3 */
-#define AT91C_PB22_PCK2 ( AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PB23 ( 1 << 23 ) /* Pin Controlled by PB23 */
-#define AT91C_PB23_TIOA0 ( AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */
-#define AT91C_PB23_DCD1 ( AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */
-#define AT91C_PIO_PB24 ( 1 << 24 ) /* Pin Controlled by PB24 */
-#define AT91C_PB24_TIOB0 ( AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */
-#define AT91C_PB24_DSR1 ( AT91C_PIO_PB24 ) /* USART 1 Data Set ready */
-#define AT91C_PIO_PB25 ( 1 << 25 ) /* Pin Controlled by PB25 */
-#define AT91C_PB25_TIOA1 ( AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */
-#define AT91C_PB25_DTR1 ( AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */
-#define AT91C_PIO_PB26 ( 1 << 26 ) /* Pin Controlled by PB26 */
-#define AT91C_PB26_TIOB1 ( AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */
-#define AT91C_PB26_RI1 ( AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */
-#define AT91C_PIO_PB27 ( 1 << 27 ) /* Pin Controlled by PB27 */
-#define AT91C_PB27_TIOA2 ( AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */
-#define AT91C_PB27_PWM0 ( AT91C_PIO_PB27 ) /* PWM Channel 0 */
-#define AT91C_PIO_PB28 ( 1 << 28 ) /* Pin Controlled by PB28 */
-#define AT91C_PB28_TIOB2 ( AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */
-#define AT91C_PB28_PWM1 ( AT91C_PIO_PB28 ) /* PWM Channel 1 */
-#define AT91C_PIO_PB29 ( 1 << 29 ) /* Pin Controlled by PB29 */
-#define AT91C_PB29_PCK1 ( AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PB29_PWM2 ( AT91C_PIO_PB29 ) /* PWM Channel 2 */
-#define AT91C_PIO_PB3 ( 1 << 3 ) /* Pin Controlled by PB3 */
-#define AT91C_PB3_ETX1 ( AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PB30 ( 1 << 30 ) /* Pin Controlled by PB30 */
-#define AT91C_PB30_PCK2 ( AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PB30_PWM3 ( AT91C_PIO_PB30 ) /* PWM Channel 3 */
-#define AT91C_PIO_PB4 ( 1 << 4 ) /* Pin Controlled by PB4 */
-#define AT91C_PB4_ECRS_ECRSDV ( AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PB5 ( 1 << 5 ) /* Pin Controlled by PB5 */
-#define AT91C_PB5_ERX0 ( AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PB6 ( 1 << 6 ) /* Pin Controlled by PB6 */
-#define AT91C_PB6_ERX1 ( AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PB7 ( 1 << 7 ) /* Pin Controlled by PB7 */
-#define AT91C_PB7_ERXER ( AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */
-#define AT91C_PIO_PB8 ( 1 << 8 ) /* Pin Controlled by PB8 */
-#define AT91C_PB8_EMDC ( AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PB9 ( 1 << 9 ) /* Pin Controlled by PB9 */
-#define AT91C_PB9_EMDIO ( AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock
+#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data
+#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data
+#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock
+#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data
+#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send
+#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0
+#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send
+#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock
+#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send
+#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send
+#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input
+#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger
+#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0
+#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input
+#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1
+#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2
+#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3
+#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready
+#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready
+#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator
+#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0
+#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1
+#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2
+#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3
+#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error
+#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-/* ***************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 */
-/* ***************************************************************************** */
-#define AT91C_ID_FIQ ( 0 ) /* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS ( 1 ) /* System Peripheral */
-#define AT91C_ID_PIOA ( 2 ) /* Parallel IO Controller A */
-#define AT91C_ID_PIOB ( 3 ) /* Parallel IO Controller B */
-#define AT91C_ID_SPI0 ( 4 ) /* Serial Peripheral Interface 0 */
-#define AT91C_ID_SPI1 ( 5 ) /* Serial Peripheral Interface 1 */
-#define AT91C_ID_US0 ( 6 ) /* USART 0 */
-#define AT91C_ID_US1 ( 7 ) /* USART 1 */
-#define AT91C_ID_SSC ( 8 ) /* Serial Synchronous Controller */
-#define AT91C_ID_TWI ( 9 ) /* Two-Wire Interface */
-#define AT91C_ID_PWMC ( 10 ) /* PWM Controller */
-#define AT91C_ID_UDP ( 11 ) /* USB Device Port */
-#define AT91C_ID_TC0 ( 12 ) /* Timer Counter 0 */
-#define AT91C_ID_TC1 ( 13 ) /* Timer Counter 1 */
-#define AT91C_ID_TC2 ( 14 ) /* Timer Counter 2 */
-#define AT91C_ID_CAN ( 15 ) /* Control Area Network Controller */
-#define AT91C_ID_EMAC ( 16 ) /* Ethernet MAC */
-#define AT91C_ID_ADC ( 17 ) /* Analog-to-Digital Converter */
-#define AT91C_ID_AES ( 18 ) /* Advanced Encryption Standard 128-bit */
-#define AT91C_ID_TDES ( 19 ) /* Triple Data Encryption Standard */
-#define AT91C_ID_20_Reserved ( 20 ) /* Reserved */
-#define AT91C_ID_21_Reserved ( 21 ) /* Reserved */
-#define AT91C_ID_22_Reserved ( 22 ) /* Reserved */
-#define AT91C_ID_23_Reserved ( 23 ) /* Reserved */
-#define AT91C_ID_24_Reserved ( 24 ) /* Reserved */
-#define AT91C_ID_25_Reserved ( 25 ) /* Reserved */
-#define AT91C_ID_26_Reserved ( 26 ) /* Reserved */
-#define AT91C_ID_27_Reserved ( 27 ) /* Reserved */
-#define AT91C_ID_28_Reserved ( 28 ) /* Reserved */
-#define AT91C_ID_29_Reserved ( 29 ) /* Reserved */
-#define AT91C_ID_IRQ0 ( 30 ) /* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1 ( 31 ) /* Advanced Interrupt Controller (IRQ1) */
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ( 1) // System Peripheral
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0 ( 6) // USART 0
+#define AT91C_ID_US1 ( 7) // USART 1
+#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ( 9) // Two-Wire Interface
+#define AT91C_ID_PWMC (10) // PWM Controller
+#define AT91C_ID_UDP (11) // USB Device Port
+#define AT91C_ID_TC0 (12) // Timer Counter 0
+#define AT91C_ID_TC1 (13) // Timer Counter 1
+#define AT91C_ID_TC2 (14) // Timer Counter 2
+#define AT91C_ID_CAN (15) // Control Area Network Controller
+#define AT91C_ID_EMAC (16) // Ethernet MAC
+#define AT91C_ID_ADC (17) // Analog-to-Digital Converter
+#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES (19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved (20) // Reserved
+#define AT91C_ID_21_Reserved (21) // Reserved
+#define AT91C_ID_22_Reserved (22) // Reserved
+#define AT91C_ID_23_Reserved (23) // Reserved
+#define AT91C_ID_24_Reserved (24) // Reserved
+#define AT91C_ID_25_Reserved (25) // Reserved
+#define AT91C_ID_26_Reserved (26) // Reserved
+#define AT91C_ID_27_Reserved (27) // Reserved
+#define AT91C_ID_28_Reserved (28) // Reserved
+#define AT91C_ID_29_Reserved (29) // Reserved
+#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
-/* ***************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 */
-/* ***************************************************************************** */
-#define AT91C_BASE_SYS ( 0xFFFFF000 ) /* (SYS) Base Address */
-#define AT91C_BASE_AIC ( 0xFFFFF000 ) /* (AIC) Base Address */
-#define AT91C_BASE_PDC_DBGU ( 0xFFFFF300 ) /* (PDC_DBGU) Base Address */
-#define AT91C_BASE_DBGU ( 0xFFFFF200 ) /* (DBGU) Base Address */
-#define AT91C_BASE_PIOA ( 0xFFFFF400 ) /* (PIOA) Base Address */
-#define AT91C_BASE_PIOB ( 0xFFFFF600 ) /* (PIOB) Base Address */
-#define AT91C_BASE_CKGR ( 0xFFFFFC20 ) /* (CKGR) Base Address */
-#define AT91C_BASE_PMC ( 0xFFFFFC00 ) /* (PMC) Base Address */
-#define AT91C_BASE_RSTC ( 0xFFFFFD00 ) /* (RSTC) Base Address */
-#define AT91C_BASE_RTTC ( 0xFFFFFD20 ) /* (RTTC) Base Address */
-#define AT91C_BASE_PITC ( 0xFFFFFD30 ) /* (PITC) Base Address */
-#define AT91C_BASE_WDTC ( 0xFFFFFD40 ) /* (WDTC) Base Address */
-#define AT91C_BASE_VREG ( 0xFFFFFD60 ) /* (VREG) Base Address */
-#define AT91C_BASE_MC ( 0xFFFFFF00 ) /* (MC) Base Address */
-#define AT91C_BASE_PDC_SPI1 ( 0xFFFE4100 ) /* (PDC_SPI1) Base Address */
-#define AT91C_BASE_SPI1 ( 0xFFFE4000 ) /* (SPI1) Base Address */
-#define AT91C_BASE_PDC_SPI0 ( 0xFFFE0100 ) /* (PDC_SPI0) Base Address */
-#define AT91C_BASE_SPI0 ( 0xFFFE0000 ) /* (SPI0) Base Address */
-#define AT91C_BASE_PDC_US1 ( 0xFFFC4100 ) /* (PDC_US1) Base Address */
-#define AT91C_BASE_US1 ( 0xFFFC4000 ) /* (US1) Base Address */
-#define AT91C_BASE_PDC_US0 ( 0xFFFC0100 ) /* (PDC_US0) Base Address */
-#define AT91C_BASE_US0 ( 0xFFFC0000 ) /* (US0) Base Address */
-#define AT91C_BASE_PDC_SSC ( 0xFFFD4100 ) /* (PDC_SSC) Base Address */
-#define AT91C_BASE_SSC ( 0xFFFD4000 ) /* (SSC) Base Address */
-#define AT91C_BASE_TWI ( 0xFFFB8000 ) /* (TWI) Base Address */
-#define AT91C_BASE_PWMC_CH3 ( 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
-#define AT91C_BASE_PWMC_CH2 ( 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
-#define AT91C_BASE_PWMC_CH1 ( 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
-#define AT91C_BASE_PWMC_CH0 ( 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
-#define AT91C_BASE_PWMC ( 0xFFFCC000 ) /* (PWMC) Base Address */
-#define AT91C_BASE_UDP ( 0xFFFB0000 ) /* (UDP) Base Address */
-#define AT91C_BASE_TC0 ( 0xFFFA0000 ) /* (TC0) Base Address */
-#define AT91C_BASE_TC1 ( 0xFFFA0040 ) /* (TC1) Base Address */
-#define AT91C_BASE_TC2 ( 0xFFFA0080 ) /* (TC2) Base Address */
-#define AT91C_BASE_TCB ( 0xFFFA0000 ) /* (TCB) Base Address */
-#define AT91C_BASE_CAN_MB0 ( 0xFFFD0200 ) /* (CAN_MB0) Base Address */
-#define AT91C_BASE_CAN_MB1 ( 0xFFFD0220 ) /* (CAN_MB1) Base Address */
-#define AT91C_BASE_CAN_MB2 ( 0xFFFD0240 ) /* (CAN_MB2) Base Address */
-#define AT91C_BASE_CAN_MB3 ( 0xFFFD0260 ) /* (CAN_MB3) Base Address */
-#define AT91C_BASE_CAN_MB4 ( 0xFFFD0280 ) /* (CAN_MB4) Base Address */
-#define AT91C_BASE_CAN_MB5 ( 0xFFFD02A0 ) /* (CAN_MB5) Base Address */
-#define AT91C_BASE_CAN_MB6 ( 0xFFFD02C0 ) /* (CAN_MB6) Base Address */
-#define AT91C_BASE_CAN_MB7 ( 0xFFFD02E0 ) /* (CAN_MB7) Base Address */
-#define AT91C_BASE_CAN ( 0xFFFD0000 ) /* (CAN) Base Address */
-#define AT91C_BASE_EMAC ( 0xFFFDC000 ) /* (EMAC) Base Address */
-#define AT91C_BASE_PDC_ADC ( 0xFFFD8100 ) /* (PDC_ADC) Base Address */
-#define AT91C_BASE_ADC ( 0xFFFD8000 ) /* (ADC) Base Address */
-#define AT91C_BASE_PDC_AES ( 0xFFFA4100 ) /* (PDC_AES) Base Address */
-#define AT91C_BASE_AES ( 0xFFFA4000 ) /* (AES) Base Address */
-#define AT91C_BASE_PDC_TDES ( 0xFFFA8100 ) /* (PDC_TDES) Base Address */
-#define AT91C_BASE_TDES ( 0xFFFA8000 ) /* (TDES) Base Address */
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address
-/* ***************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 */
-/* ***************************************************************************** */
-#define AT91C_ISRAM ( 0x00200000 ) /* Internal SRAM base address */
-#define AT91C_ISRAM_SIZE ( 0x00008000 ) /* Internal SRAM size in byte (32 Kbyte) */
-#define AT91C_IFLASH ( 0x00100000 ) /* Internal ROM base address */
-#define AT91C_IFLASH_SIZE ( 0x00020000 ) /* Internal ROM size in byte (128 Kbyte) */
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbyte)
+#define AT91C_IFLASH (0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte)
+
+
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
index aa9584c..6b73f8a 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
@@ -1,2743 +1,2715 @@
-/* ---------------------------------------------------------------------------- */
-/* ATMEL Microcontroller Software Support - ROUSSET - */
-/* ---------------------------------------------------------------------------- */
-/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* ---------------------------------------------------------------------------- */
-/* File Name : AT91SAM7X256.h */
-/* Object : AT91SAM7X256 definitions */
-/* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */
-/* */
-/* CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */
-/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */
-/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
-/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */
-/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */
-/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
-/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
-/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
-/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */
-/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */
-/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */
-/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */
-/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */
-/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */
-/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
-/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
-/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
-/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
-/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
-/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
-/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */
-/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */
-/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
-/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */
-/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
-/* ---------------------------------------------------------------------------- */
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM7X256.h
+// Object : AT91SAM7X256 definitions
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+//
+// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// ----------------------------------------------------------------------------
#ifndef AT91SAM7X256_H
#define AT91SAM7X256_H
-typedef volatile unsigned int AT91_REG; /* Hardware register definition */
+typedef volatile unsigned int AT91_REG;// Hardware register definition
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR System Peripherals */
-/* ***************************************************************************** */
-typedef struct _AT91S_SYS
-{
- AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
- AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
- AT91_REG AIC_IVR; /* IRQ Vector Register */
- AT91_REG AIC_FVR; /* FIQ Vector Register */
- AT91_REG AIC_ISR; /* Interrupt Status Register */
- AT91_REG AIC_IPR; /* Interrupt Pending Register */
- AT91_REG AIC_IMR; /* Interrupt Mask Register */
- AT91_REG AIC_CISR; /* Core Interrupt Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
- AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
- AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
- AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
- AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
- AT91_REG AIC_SPU; /* Spurious Vector Register */
- AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
- AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
- AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
- AT91_REG Reserved2[ 45 ]; /* */
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved3[ 7 ]; /* */
- AT91_REG DBGU_CIDR; /* Chip ID Register */
- AT91_REG DBGU_EXID; /* Chip ID Extension Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved4[ 45 ]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
- AT91_REG Reserved5[ 54 ]; /* */
- AT91_REG PIOA_PER; /* PIO Enable Register */
- AT91_REG PIOA_PDR; /* PIO Disable Register */
- AT91_REG PIOA_PSR; /* PIO Status Register */
- AT91_REG Reserved6[ 1 ]; /* */
- AT91_REG PIOA_OER; /* Output Enable Register */
- AT91_REG PIOA_ODR; /* Output Disable Registerr */
- AT91_REG PIOA_OSR; /* Output Status Register */
- AT91_REG Reserved7[ 1 ]; /* */
- AT91_REG PIOA_IFER; /* Input Filter Enable Register */
- AT91_REG PIOA_IFDR; /* Input Filter Disable Register */
- AT91_REG PIOA_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved8[ 1 ]; /* */
- AT91_REG PIOA_SODR; /* Set Output Data Register */
- AT91_REG PIOA_CODR; /* Clear Output Data Register */
- AT91_REG PIOA_ODSR; /* Output Data Status Register */
- AT91_REG PIOA_PDSR; /* Pin Data Status Register */
- AT91_REG PIOA_IER; /* Interrupt Enable Register */
- AT91_REG PIOA_IDR; /* Interrupt Disable Register */
- AT91_REG PIOA_IMR; /* Interrupt Mask Register */
- AT91_REG PIOA_ISR; /* Interrupt Status Register */
- AT91_REG PIOA_MDER; /* Multi-driver Enable Register */
- AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIOA_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved9[ 1 ]; /* */
- AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIOA_PPUER; /* Pull-up Enable Register */
- AT91_REG PIOA_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved10[ 1 ]; /* */
- AT91_REG PIOA_ASR; /* Select A Register */
- AT91_REG PIOA_BSR; /* Select B Register */
- AT91_REG PIOA_ABSR; /* AB Select Status Register */
- AT91_REG Reserved11[ 9 ]; /* */
- AT91_REG PIOA_OWER; /* Output Write Enable Register */
- AT91_REG PIOA_OWDR; /* Output Write Disable Register */
- AT91_REG PIOA_OWSR; /* Output Write Status Register */
- AT91_REG Reserved12[ 85 ]; /* */
- AT91_REG PIOB_PER; /* PIO Enable Register */
- AT91_REG PIOB_PDR; /* PIO Disable Register */
- AT91_REG PIOB_PSR; /* PIO Status Register */
- AT91_REG Reserved13[ 1 ]; /* */
- AT91_REG PIOB_OER; /* Output Enable Register */
- AT91_REG PIOB_ODR; /* Output Disable Registerr */
- AT91_REG PIOB_OSR; /* Output Status Register */
- AT91_REG Reserved14[ 1 ]; /* */
- AT91_REG PIOB_IFER; /* Input Filter Enable Register */
- AT91_REG PIOB_IFDR; /* Input Filter Disable Register */
- AT91_REG PIOB_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved15[ 1 ]; /* */
- AT91_REG PIOB_SODR; /* Set Output Data Register */
- AT91_REG PIOB_CODR; /* Clear Output Data Register */
- AT91_REG PIOB_ODSR; /* Output Data Status Register */
- AT91_REG PIOB_PDSR; /* Pin Data Status Register */
- AT91_REG PIOB_IER; /* Interrupt Enable Register */
- AT91_REG PIOB_IDR; /* Interrupt Disable Register */
- AT91_REG PIOB_IMR; /* Interrupt Mask Register */
- AT91_REG PIOB_ISR; /* Interrupt Status Register */
- AT91_REG PIOB_MDER; /* Multi-driver Enable Register */
- AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIOB_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved16[ 1 ]; /* */
- AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIOB_PPUER; /* Pull-up Enable Register */
- AT91_REG PIOB_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved17[ 1 ]; /* */
- AT91_REG PIOB_ASR; /* Select A Register */
- AT91_REG PIOB_BSR; /* Select B Register */
- AT91_REG PIOB_ABSR; /* AB Select Status Register */
- AT91_REG Reserved18[ 9 ]; /* */
- AT91_REG PIOB_OWER; /* Output Write Enable Register */
- AT91_REG PIOB_OWDR; /* Output Write Disable Register */
- AT91_REG PIOB_OWSR; /* Output Write Status Register */
- AT91_REG Reserved19[ 341 ]; /* */
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved20[ 1 ]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved21[ 1 ]; /* */
- AT91_REG PMC_MOR; /* Main Oscillator Register */
- AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved22[ 1 ]; /* */
- AT91_REG PMC_PLLR; /* PLL Register */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved23[ 3 ]; /* */
- AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */
- AT91_REG Reserved24[ 4 ]; /* */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved25[ 36 ]; /* */
- AT91_REG RSTC_RCR; /* Reset Control Register */
- AT91_REG RSTC_RSR; /* Reset Status Register */
- AT91_REG RSTC_RMR; /* Reset Mode Register */
- AT91_REG Reserved26[ 5 ]; /* */
- AT91_REG RTTC_RTMR; /* Real-time Mode Register */
- AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
- AT91_REG RTTC_RTVR; /* Real-time Value Register */
- AT91_REG RTTC_RTSR; /* Real-time Status Register */
- AT91_REG PITC_PIMR; /* Period Interval Mode Register */
- AT91_REG PITC_PISR; /* Period Interval Status Register */
- AT91_REG PITC_PIVR; /* Period Interval Value Register */
- AT91_REG PITC_PIIR; /* Period Interval Image Register */
- AT91_REG WDTC_WDCR; /* Watchdog Control Register */
- AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
- AT91_REG WDTC_WDSR; /* Watchdog Status Register */
- AT91_REG Reserved27[ 5 ]; /* */
- AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
-} AT91S_SYS, * AT91PS_SYS;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved2[45]; //
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved3[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved4[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved5[54]; //
+ AT91_REG PIOA_PER; // PIO Enable Register
+ AT91_REG PIOA_PDR; // PIO Disable Register
+ AT91_REG PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved6[1]; //
+ AT91_REG PIOA_OER; // Output Enable Register
+ AT91_REG PIOA_ODR; // Output Disable Registerr
+ AT91_REG PIOA_OSR; // Output Status Register
+ AT91_REG Reserved7[1]; //
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved8[1]; //
+ AT91_REG PIOA_SODR; // Set Output Data Register
+ AT91_REG PIOA_CODR; // Clear Output Data Register
+ AT91_REG PIOA_ODSR; // Output Data Status Register
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
+ AT91_REG PIOA_IER; // Interrupt Enable Register
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
+ AT91_REG PIOA_ISR; // Interrupt Status Register
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved9[1]; //
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved10[1]; //
+ AT91_REG PIOA_ASR; // Select A Register
+ AT91_REG PIOA_BSR; // Select B Register
+ AT91_REG PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved11[9]; //
+ AT91_REG PIOA_OWER; // Output Write Enable Register
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
+ AT91_REG PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved12[85]; //
+ AT91_REG PIOB_PER; // PIO Enable Register
+ AT91_REG PIOB_PDR; // PIO Disable Register
+ AT91_REG PIOB_PSR; // PIO Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG PIOB_OER; // Output Enable Register
+ AT91_REG PIOB_ODR; // Output Disable Registerr
+ AT91_REG PIOB_OSR; // Output Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG PIOB_IFER; // Input Filter Enable Register
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register
+ AT91_REG PIOB_IFSR; // Input Filter Status Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG PIOB_SODR; // Set Output Data Register
+ AT91_REG PIOB_CODR; // Clear Output Data Register
+ AT91_REG PIOB_ODSR; // Output Data Status Register
+ AT91_REG PIOB_PDSR; // Pin Data Status Register
+ AT91_REG PIOB_IER; // Interrupt Enable Register
+ AT91_REG PIOB_IDR; // Interrupt Disable Register
+ AT91_REG PIOB_IMR; // Interrupt Mask Register
+ AT91_REG PIOB_ISR; // Interrupt Status Register
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved16[1]; //
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved17[1]; //
+ AT91_REG PIOB_ASR; // Select A Register
+ AT91_REG PIOB_BSR; // Select B Register
+ AT91_REG PIOB_ABSR; // AB Select Status Register
+ AT91_REG Reserved18[9]; //
+ AT91_REG PIOB_OWER; // Output Write Enable Register
+ AT91_REG PIOB_OWDR; // Output Write Disable Register
+ AT91_REG PIOB_OWSR; // Output Write Status Register
+ AT91_REG Reserved19[341]; //
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved20[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved21[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved22[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved23[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved24[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved25[36]; //
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved26[5]; //
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved27[5]; //
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_AIC
-{
- AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
- AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
- AT91_REG AIC_IVR; /* IRQ Vector Register */
- AT91_REG AIC_FVR; /* FIQ Vector Register */
- AT91_REG AIC_ISR; /* Interrupt Status Register */
- AT91_REG AIC_IPR; /* Interrupt Pending Register */
- AT91_REG AIC_IMR; /* Interrupt Mask Register */
- AT91_REG AIC_CISR; /* Core Interrupt Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
- AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
- AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
- AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
- AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
- AT91_REG AIC_SPU; /* Spurious Vector Register */
- AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
- AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
- AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
-} AT91S_AIC, * AT91PS_AIC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
-/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
-#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
-#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */
-#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */
-#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
-/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
-#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
-#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
-/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
-#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
-#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
-/* ***************************************************************************** */
-typedef struct _AT91S_PDC
-{
- AT91_REG PDC_RPR; /* Receive Pointer Register */
- AT91_REG PDC_RCR; /* Receive Counter Register */
- AT91_REG PDC_TPR; /* Transmit Pointer Register */
- AT91_REG PDC_TCR; /* Transmit Counter Register */
- AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
- AT91_REG PDC_RNCR; /* Receive Next Counter Register */
- AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
- AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
- AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
-} AT91S_PDC, * AT91PS_PDC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/* ***************************************************************************** */
-typedef struct _AT91S_DBGU
-{
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved0[ 7 ]; /* */
- AT91_REG DBGU_CIDR; /* Chip ID Register */
- AT91_REG DBGU_EXID; /* Chip ID Extension Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved1[ 45 ]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
-} AT91S_DBGU, * AT91PS_DBGU;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */
-#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */
-/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */
-#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */
-#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */
-#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */
-#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */
-#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
-#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
-#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
-#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
-#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
-/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
-/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
-#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PIO
-{
- AT91_REG PIO_PER; /* PIO Enable Register */
- AT91_REG PIO_PDR; /* PIO Disable Register */
- AT91_REG PIO_PSR; /* PIO Status Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG PIO_OER; /* Output Enable Register */
- AT91_REG PIO_ODR; /* Output Disable Registerr */
- AT91_REG PIO_OSR; /* Output Status Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG PIO_IFER; /* Input Filter Enable Register */
- AT91_REG PIO_IFDR; /* Input Filter Disable Register */
- AT91_REG PIO_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG PIO_SODR; /* Set Output Data Register */
- AT91_REG PIO_CODR; /* Clear Output Data Register */
- AT91_REG PIO_ODSR; /* Output Data Status Register */
- AT91_REG PIO_PDSR; /* Pin Data Status Register */
- AT91_REG PIO_IER; /* Interrupt Enable Register */
- AT91_REG PIO_IDR; /* Interrupt Disable Register */
- AT91_REG PIO_IMR; /* Interrupt Mask Register */
- AT91_REG PIO_ISR; /* Interrupt Status Register */
- AT91_REG PIO_MDER; /* Multi-driver Enable Register */
- AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIO_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved3[ 1 ]; /* */
- AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIO_PPUER; /* Pull-up Enable Register */
- AT91_REG PIO_PPUSR; /* Pull-up Status Register */
- AT91_REG Reserved4[ 1 ]; /* */
- AT91_REG PIO_ASR; /* Select A Register */
- AT91_REG PIO_BSR; /* Select B Register */
- AT91_REG PIO_ABSR; /* AB Select Status Register */
- AT91_REG Reserved5[ 9 ]; /* */
- AT91_REG PIO_OWER; /* Output Write Enable Register */
- AT91_REG PIO_OWDR; /* Output Write Disable Register */
- AT91_REG PIO_OWSR; /* Output Write Status Register */
-} AT91S_PIO, * AT91PS_PIO;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_CKGR
-{
- AT91_REG CKGR_MOR; /* Main Oscillator Register */
- AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG CKGR_PLLR; /* PLL Register */
-} AT91S_CKGR, * AT91PS_CKGR;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG CKGR_PLLR; // PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */
-#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */
-/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */
-#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */
-#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
-#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */
-#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */
-#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */
-#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/* ***************************************************************************** */
-typedef struct _AT91S_PMC
-{
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG PMC_MOR; /* Main Oscillator Register */
- AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG PMC_PLLR; /* PLL Register */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved3[ 3 ]; /* */
- AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */
- AT91_REG Reserved4[ 4 ]; /* */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
-} AT91S_PMC, * AT91PS_PMC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved3[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved4[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
-/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
-#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
-/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
-/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
-/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
-/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
-/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
-/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
-#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */
-#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
-/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
-/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
-#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
-/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
-/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Reset Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_RSTC
-{
- AT91_REG RSTC_RCR; /* Reset Control Register */
- AT91_REG RSTC_RSR; /* Reset Status Register */
- AT91_REG RSTC_RMR; /* Reset Mode Register */
-} AT91S_RSTC, * AT91PS_RSTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
-/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
-#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */
-#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */
-#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */
-#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
-/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
-#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */
-#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */
-#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */
-#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occured. */
-#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */
-#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */
-#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occured. */
-#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */
-#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */
-/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
-#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */
-#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_RTTC
-{
- AT91_REG RTTC_RTMR; /* Real-time Mode Register */
- AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
- AT91_REG RTTC_RTVR; /* Real-time Value Register */
- AT91_REG RTTC_RTSR; /* Real-time Status Register */
-} AT91S_RTTC, * AT91PS_RTTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
-/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
-#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
-#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */
-#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */
-#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */
-/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
-#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */
-/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
-#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */
-/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
-#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */
-#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PITC
-{
- AT91_REG PITC_PIMR; /* Period Interval Mode Register */
- AT91_REG PITC_PISR; /* Period Interval Status Register */
- AT91_REG PITC_PIVR; /* Period Interval Value Register */
- AT91_REG PITC_PIIR; /* Period Interval Image Register */
-} AT91S_PITC, * AT91PS_PITC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
-/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
-#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
-#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */
-#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */
-/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
-#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */
-/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
-#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
-#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */
-/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_WDTC
-{
- AT91_REG WDTC_WDCR; /* Watchdog Control Register */
- AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
- AT91_REG WDTC_WDSR; /* Watchdog Status Register */
-} AT91S_WDTC, * AT91PS_WDTC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
-/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
-#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */
-#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */
-/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
-#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */
-#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */
-#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */
-#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
-#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */
-#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */
-/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
-#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */
-#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_VREG
-{
- AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
-} AT91S_VREG, * AT91PS_VREG;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
-/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
-#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Memory Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_MC
-{
- AT91_REG MC_RCR; /* MC Remap Control Register */
- AT91_REG MC_ASR; /* MC Abort Status Register */
- AT91_REG MC_AASR; /* MC Abort Address Status Register */
- AT91_REG Reserved0[ 21 ]; /* */
- AT91_REG MC_FMR; /* MC Flash Mode Register */
- AT91_REG MC_FCR; /* MC Flash Command Register */
- AT91_REG MC_FSR; /* MC Flash Status Register */
-} AT91S_MC, * AT91PS_MC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved0[21]; //
+ AT91_REG MC_FMR; // MC Flash Mode Register
+ AT91_REG MC_FCR; // MC Flash Command Register
+ AT91_REG MC_FSR; // MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
-/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
-#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
-/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
-#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
-#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
-#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
-#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */
-#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */
-#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */
-#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */
-#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */
-#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */
-#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */
-#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */
-#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */
-/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
-#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */
-#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */
-#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */
-#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */
-#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */
-#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */
-#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */
-#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
-/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
-#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */
-#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */
-#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
-#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
-#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */
-#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */
-#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */
-#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
-#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
-/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
-#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */
-#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */
-#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */
-#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */
-#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */
-#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */
-#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */
-#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */
-#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SPI
-{
- AT91_REG SPI_CR; /* Control Register */
- AT91_REG SPI_MR; /* Mode Register */
- AT91_REG SPI_RDR; /* Receive Data Register */
- AT91_REG SPI_TDR; /* Transmit Data Register */
- AT91_REG SPI_SR; /* Status Register */
- AT91_REG SPI_IER; /* Interrupt Enable Register */
- AT91_REG SPI_IDR; /* Interrupt Disable Register */
- AT91_REG SPI_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved0[ 4 ]; /* */
- AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */
- AT91_REG Reserved1[ 48 ]; /* */
- AT91_REG SPI_RPR; /* Receive Pointer Register */
- AT91_REG SPI_RCR; /* Receive Counter Register */
- AT91_REG SPI_TPR; /* Transmit Pointer Register */
- AT91_REG SPI_TCR; /* Transmit Counter Register */
- AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
- AT91_REG SPI_RNCR; /* Receive Next Counter Register */
- AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
- AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
- AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
-} AT91S_SPI, * AT91PS_SPI;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */
-#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */
-#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */
-#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */
-#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */
-#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */
-#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Usart */
-/* ***************************************************************************** */
-typedef struct _AT91S_USART
-{
- AT91_REG US_CR; /* Control Register */
- AT91_REG US_MR; /* Mode Register */
- AT91_REG US_IER; /* Interrupt Enable Register */
- AT91_REG US_IDR; /* Interrupt Disable Register */
- AT91_REG US_IMR; /* Interrupt Mask Register */
- AT91_REG US_CSR; /* Channel Status Register */
- AT91_REG US_RHR; /* Receiver Holding Register */
- AT91_REG US_THR; /* Transmitter Holding Register */
- AT91_REG US_BRGR; /* Baud Rate Generator Register */
- AT91_REG US_RTOR; /* Receiver Time-out Register */
- AT91_REG US_TTGR; /* Transmitter Time-guard Register */
- AT91_REG Reserved0[ 5 ]; /* */
- AT91_REG US_FIDI; /* FI_DI_Ratio Register */
- AT91_REG US_NER; /* Nb Errors Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG US_IF; /* IRDA_FILTER Register */
- AT91_REG Reserved2[ 44 ]; /* */
- AT91_REG US_RPR; /* Receive Pointer Register */
- AT91_REG US_RCR; /* Receive Counter Register */
- AT91_REG US_TPR; /* Transmit Pointer Register */
- AT91_REG US_TCR; /* Transmit Counter Register */
- AT91_REG US_RNPR; /* Receive Next Pointer Register */
- AT91_REG US_RNCR; /* Receive Next Counter Register */
- AT91_REG US_TNPR; /* Transmit Next Pointer Register */
- AT91_REG US_TNCR; /* Transmit Next Counter Register */
- AT91_REG US_PTCR; /* PDC Transfer Control Register */
- AT91_REG US_PTSR; /* PDC Transfer Status Register */
-} AT91S_USART, * AT91PS_USART;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
-/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */
-#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
-#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
-#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
-#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
-#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
-#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
-#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
-#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
-#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
-#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
-/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */
-#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */
-#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */
-#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */
-#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */
-#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */
-#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */
-#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */
-#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */
-#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */
-#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */
-#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
-#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
-#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
-#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
-#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
-#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
-#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
-#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
-#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
-#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
-/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */
-#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */
-#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
-#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
-#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
-#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
-#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
-#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
-/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
-#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */
-#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */
-#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */
-#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_SSC
-{
- AT91_REG SSC_CR; /* Control Register */
- AT91_REG SSC_CMR; /* Clock Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */
- AT91_REG SSC_RFMR; /* Receive Frame Mode Register */
- AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */
- AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */
- AT91_REG SSC_RHR; /* Receive Holding Register */
- AT91_REG SSC_THR; /* Transmit Holding Register */
- AT91_REG Reserved1[ 2 ]; /* */
- AT91_REG SSC_RSHR; /* Receive Sync Holding Register */
- AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */
- AT91_REG Reserved2[ 2 ]; /* */
- AT91_REG SSC_SR; /* Status Register */
- AT91_REG SSC_IER; /* Interrupt Enable Register */
- AT91_REG SSC_IDR; /* Interrupt Disable Register */
- AT91_REG SSC_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved3[ 44 ]; /* */
- AT91_REG SSC_RPR; /* Receive Pointer Register */
- AT91_REG SSC_RCR; /* Receive Counter Register */
- AT91_REG SSC_TPR; /* Transmit Pointer Register */
- AT91_REG SSC_TCR; /* Transmit Counter Register */
- AT91_REG SSC_RNPR; /* Receive Next Pointer Register */
- AT91_REG SSC_RNCR; /* Receive Next Counter Register */
- AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SSC_TNCR; /* Transmit Next Counter Register */
- AT91_REG SSC_PTCR; /* PDC Transfer Control Register */
- AT91_REG SSC_PTSR; /* PDC Transfer Status Register */
-} AT91S_SSC, * AT91PS_SSC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved3[44]; //
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
-/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
-#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */
-#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */
-#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */
-#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */
-/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
-#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */
-#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */
-#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */
-#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */
-#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */
-#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
-#define AT91C_SSC_CKO_CONTINOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
-#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
-#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */
-#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */
-#define AT91C_SSC_START_CONTINOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
-#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */
-#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */
-#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */
-#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */
-#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */
-#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */
-#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */
-#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */
-#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
-#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
-/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
-#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */
-#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */
-#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */
-#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */
-#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */
-#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */
-#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
-#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
-#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
-#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
-#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
-#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
-#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */
-/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
-/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
-#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */
-#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
-/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
-#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */
-#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */
-#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */
-#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */
-#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */
-#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */
-#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */
-#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */
-#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
-#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
-#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
-/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
-/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TWI
-{
- AT91_REG TWI_CR; /* Control Register */
- AT91_REG TWI_MMR; /* Master Mode Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG TWI_IADR; /* Internal Address Register */
- AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
- AT91_REG Reserved1[ 3 ]; /* */
- AT91_REG TWI_SR; /* Status Register */
- AT91_REG TWI_IER; /* Interrupt Enable Register */
- AT91_REG TWI_IDR; /* Interrupt Disable Register */
- AT91_REG TWI_IMR; /* Interrupt Mask Register */
- AT91_REG TWI_RHR; /* Receive Holding Register */
- AT91_REG TWI_THR; /* Transmit Holding Register */
-} AT91S_TWI, * AT91PS_TWI;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved1[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
-/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
-#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */
-#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */
-#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */
-#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */
-#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
-#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */
-#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */
-#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */
-#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */
-#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */
-#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */
-#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
-#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */
-#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */
-#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
-#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */
-#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */
-#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */
-#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */
-#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */
-#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */
-/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
-/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PWMC_CH
-{
- AT91_REG PWMC_CMR; /* Channel Mode Register */
- AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */
- AT91_REG PWMC_CPRDR; /* Channel Period Register */
- AT91_REG PWMC_CCNTR; /* Channel Counter Register */
- AT91_REG PWMC_CUPDR; /* Channel Update Register */
- AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
-} AT91S_PWMC_CH, * AT91PS_PWMC_CH;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+ AT91_REG PWMC_CMR; // Channel Mode Register
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
+ AT91_REG PWMC_CPRDR; // Channel Period Register
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
+ AT91_REG PWMC_CUPDR; // Channel Update Register
+ AT91_REG PWMC_Reserved[3]; // Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
-#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
-#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */
-#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */
-#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */
-#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
-/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
-#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */
-/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
-#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */
-/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
-#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */
-/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
-#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_PWMC
-{
- AT91_REG PWMC_MR; /* PWMC Mode Register */
- AT91_REG PWMC_ENA; /* PWMC Enable Register */
- AT91_REG PWMC_DIS; /* PWMC Disable Register */
- AT91_REG PWMC_SR; /* PWMC Status Register */
- AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */
- AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */
- AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */
- AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */
- AT91_REG Reserved0[ 55 ]; /* */
- AT91_REG PWMC_VR; /* PWMC Version Register */
- AT91_REG Reserved1[ 64 ]; /* */
- AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */
-} AT91S_PWMC, * AT91PS_PWMC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+ AT91_REG PWMC_MR; // PWMC Mode Register
+ AT91_REG PWMC_ENA; // PWMC Enable Register
+ AT91_REG PWMC_DIS; // PWMC Disable Register
+ AT91_REG PWMC_SR; // PWMC Status Register
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
+ AT91_REG Reserved0[55]; //
+ AT91_REG PWMC_VR; // PWMC Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
-/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
-#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */
-#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */
-#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */
-#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
-#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */
-#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */
-/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
-#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
-#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
-#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
-#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
-/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
-/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
-/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
-/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
-/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
-/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR USB Device Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_UDP
-{
- AT91_REG UDP_NUM; /* Frame Number Register */
- AT91_REG UDP_GLBSTATE; /* Global State Register */
- AT91_REG UDP_FADDR; /* Function Address Register */
- AT91_REG Reserved0[ 1 ]; /* */
- AT91_REG UDP_IER; /* Interrupt Enable Register */
- AT91_REG UDP_IDR; /* Interrupt Disable Register */
- AT91_REG UDP_IMR; /* Interrupt Mask Register */
- AT91_REG UDP_ISR; /* Interrupt Status Register */
- AT91_REG UDP_ICR; /* Interrupt Clear Register */
- AT91_REG Reserved1[ 1 ]; /* */
- AT91_REG UDP_RSTEP; /* Reset Endpoint Register */
- AT91_REG Reserved2[ 1 ]; /* */
- AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */
- AT91_REG Reserved3[ 2 ]; /* */
- AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */
- AT91_REG Reserved4[ 3 ]; /* */
- AT91_REG UDP_TXVC; /* Transceiver Control Register */
-} AT91S_UDP, * AT91PS_UDP;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
+ AT91_REG Reserved4[3]; //
+ AT91_REG UDP_TXVC; // Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
-/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
-#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
-#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */
-#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */
-/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
-#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */
-#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */
-#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */
-#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */
-#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */
-/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
-#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */
-#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */
-/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
-#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
-#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */
-#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */
-#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */
-#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */
-#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */
-#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */
-#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */
-#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */
-/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
-/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
-/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
-#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
-/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
-/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
-#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */
-#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */
-#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */
-#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */
-#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */
-#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */
-/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
-#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */
-#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */
-#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */
-#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */
-#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */
-#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
-#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
-#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */
-#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */
-#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */
-#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */
-#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */
-#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */
-#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */
-#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */
-#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */
-#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */
-#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */
-#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
-/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
-#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */
-#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TC
-{
- AT91_REG TC_CCR; /* Channel Control Register */
- AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG TC_CV; /* Counter Value */
- AT91_REG TC_RA; /* Register A */
- AT91_REG TC_RB; /* Register B */
- AT91_REG TC_RC; /* Register C */
- AT91_REG TC_SR; /* Status Register */
- AT91_REG TC_IER; /* Interrupt Enable Register */
- AT91_REG TC_IDR; /* Interrupt Disable Register */
- AT91_REG TC_IMR; /* Interrupt Mask Register */
-} AT91S_TC, * AT91PS_TC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
-/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
-#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */
-#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */
-/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
-#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */
-#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */
-#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */
-#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */
-#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */
-#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */
-#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */
-#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */
-#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */
-#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */
-#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */
-#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */
-#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */
-#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */
-#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */
-#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
-#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
-#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
-#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
-#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
-#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
-#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */
-#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
-#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
-#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
-#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
-#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
-#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
-#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
-#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
-#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
-#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
-#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
-#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
-#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
-#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
-#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
-#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
-#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
-#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
-#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
-#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
-#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
-#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
-#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
-#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
-#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
-#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
-#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
-/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
-#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */
-#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */
-#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */
-#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */
-#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */
-#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */
-#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */
-#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */
-#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
-#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
-#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
-/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
-/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
-/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_TCB
-{
- AT91S_TC TCB_TC0; /* TC Channel 0 */
- AT91_REG Reserved0[ 4 ]; /* */
- AT91S_TC TCB_TC1; /* TC Channel 1 */
- AT91_REG Reserved1[ 4 ]; /* */
- AT91S_TC TCB_TC2; /* TC Channel 2 */
- AT91_REG Reserved2[ 4 ]; /* */
- AT91_REG TCB_BCR; /* TC Block Control Register */
- AT91_REG TCB_BMR; /* TC Block Mode Register */
-} AT91S_TCB, * AT91PS_TCB;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
-/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
-#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
-/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
-#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
-#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */
-#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
-#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
-#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
-#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_CAN_MB
-{
- AT91_REG CAN_MB_MMR; /* MailBox Mode Register */
- AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */
- AT91_REG CAN_MB_MID; /* MailBox ID Register */
- AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
- AT91_REG CAN_MB_MSR; /* MailBox Status Register */
- AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */
- AT91_REG CAN_MB_MDH; /* MailBox Data High Register */
- AT91_REG CAN_MB_MCR; /* MailBox Control Register */
-} AT91S_CAN_MB, * AT91PS_CAN_MB;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
+ AT91_REG CAN_MB_MID; // MailBox ID Register
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register
+ AT91_REG CAN_MB_MSR; // MailBox Status Register
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register
+ AT91_REG CAN_MB_MCR; // MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
-/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
-#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */
-#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */
-#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */
-#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */
-/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
-#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
-#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */
-#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */
-/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
-/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
-/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
-#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
-#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */
-#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */
-#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */
-#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */
-#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */
-/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
-/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
-/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
-#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
-#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network Interface */
-/* ***************************************************************************** */
-typedef struct _AT91S_CAN
-{
- AT91_REG CAN_MR; /* Mode Register */
- AT91_REG CAN_IER; /* Interrupt Enable Register */
- AT91_REG CAN_IDR; /* Interrupt Disable Register */
- AT91_REG CAN_IMR; /* Interrupt Mask Register */
- AT91_REG CAN_SR; /* Status Register */
- AT91_REG CAN_BR; /* Baudrate Register */
- AT91_REG CAN_TIM; /* Timer Register */
- AT91_REG CAN_TIMESTP; /* Time Stamp Register */
- AT91_REG CAN_ECR; /* Error Counter Register */
- AT91_REG CAN_TCR; /* Transfer Command Register */
- AT91_REG CAN_ACR; /* Abort Command Register */
- AT91_REG Reserved0[ 52 ]; /* */
- AT91_REG CAN_VR; /* Version Register */
- AT91_REG Reserved1[ 64 ]; /* */
- AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */
- AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */
- AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */
- AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */
- AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */
- AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */
- AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */
- AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */
- AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */
- AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */
- AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */
- AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */
- AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */
- AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */
- AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */
- AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */
-} AT91S_CAN, * AT91PS_CAN;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+ AT91_REG CAN_MR; // Mode Register
+ AT91_REG CAN_IER; // Interrupt Enable Register
+ AT91_REG CAN_IDR; // Interrupt Disable Register
+ AT91_REG CAN_IMR; // Interrupt Mask Register
+ AT91_REG CAN_SR; // Status Register
+ AT91_REG CAN_BR; // Baudrate Register
+ AT91_REG CAN_TIM; // Timer Register
+ AT91_REG CAN_TIMESTP; // Time Stamp Register
+ AT91_REG CAN_ECR; // Error Counter Register
+ AT91_REG CAN_TCR; // Transfer Command Register
+ AT91_REG CAN_ACR; // Abort Command Register
+ AT91_REG Reserved0[52]; //
+ AT91_REG CAN_VR; // Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
-/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
-#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */
-#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */
-#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */
-#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */
-#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */
-#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */
-#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */
-#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */
-/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
-#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */
-#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */
-#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */
-#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */
-#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */
-#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */
-#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */
-#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */
-#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */
-#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */
-#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
-#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
-#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
-#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
-#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
-#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
-#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
-#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */
-#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
-#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
-#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */
-#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */
-#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
-#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */
-#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */
-#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */
-#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */
-#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */
-#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */
-/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
-/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
-/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
-#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */
-#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */
-#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */
-/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
-#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */
-#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */
-#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */
-#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */
-#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */
-#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */
-/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
-#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */
-/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
-/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
-#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */
-#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */
-/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
-#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */
-/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
-/* ***************************************************************************** */
-typedef struct _AT91S_EMAC
-{
- AT91_REG EMAC_NCR; /* Network Control Register */
- AT91_REG EMAC_NCFGR; /* Network Configuration Register */
- AT91_REG EMAC_NSR; /* Network Status Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG EMAC_TSR; /* Transmit Status Register */
- AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
- AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */
- AT91_REG EMAC_RSR; /* Receive Status Register */
- AT91_REG EMAC_ISR; /* Interrupt Status Register */
- AT91_REG EMAC_IER; /* Interrupt Enable Register */
- AT91_REG EMAC_IDR; /* Interrupt Disable Register */
- AT91_REG EMAC_IMR; /* Interrupt Mask Register */
- AT91_REG EMAC_MAN; /* PHY Maintenance Register */
- AT91_REG EMAC_PTR; /* Pause Time Register */
- AT91_REG EMAC_PFR; /* Pause Frames received Register */
- AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */
- AT91_REG EMAC_SCF; /* Single Collision Frame Register */
- AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */
- AT91_REG EMAC_FRO; /* Frames Received OK Register */
- AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */
- AT91_REG EMAC_ALE; /* Alignment Error Register */
- AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */
- AT91_REG EMAC_LCOL; /* Late Collision Register */
- AT91_REG EMAC_ECOL; /* Excessive Collision Register */
- AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
- AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
- AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
- AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
- AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
- AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
- AT91_REG EMAC_RJA; /* Receive Jabbers Register */
- AT91_REG EMAC_USF; /* Undersize Frames Register */
- AT91_REG EMAC_STE; /* SQE Test Error Register */
- AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */
- AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */
- AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */
- AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */
- AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */
- AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */
- AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */
- AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */
- AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */
- AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */
- AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */
- AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */
- AT91_REG EMAC_TID; /* Type ID Checking Register */
- AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */
- AT91_REG EMAC_USRIO; /* USER Input/Output Register */
- AT91_REG EMAC_WOL; /* Wake On LAN Register */
- AT91_REG Reserved1[ 13 ]; /* */
- AT91_REG EMAC_REV; /* Revision Register */
-} AT91S_EMAC, * AT91PS_EMAC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+ AT91_REG EMAC_NCR; // Network Control Register
+ AT91_REG EMAC_NCFGR; // Network Configuration Register
+ AT91_REG EMAC_NSR; // Network Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG EMAC_TSR; // Transmit Status Register
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
+ AT91_REG EMAC_RSR; // Receive Status Register
+ AT91_REG EMAC_ISR; // Interrupt Status Register
+ AT91_REG EMAC_IER; // Interrupt Enable Register
+ AT91_REG EMAC_IDR; // Interrupt Disable Register
+ AT91_REG EMAC_IMR; // Interrupt Mask Register
+ AT91_REG EMAC_MAN; // PHY Maintenance Register
+ AT91_REG EMAC_PTR; // Pause Time Register
+ AT91_REG EMAC_PFR; // Pause Frames received Register
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register
+ AT91_REG EMAC_SCF; // Single Collision Frame Register
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register
+ AT91_REG EMAC_FRO; // Frames Received OK Register
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
+ AT91_REG EMAC_ALE; // Alignment Error Register
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
+ AT91_REG EMAC_LCOL; // Late Collision Register
+ AT91_REG EMAC_ECOL; // Excessive Collision Register
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register
+ AT91_REG EMAC_RJA; // Receive Jabbers Register
+ AT91_REG EMAC_USF; // Undersize Frames Register
+ AT91_REG EMAC_STE; // SQE Test Error Register
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
+ AT91_REG EMAC_TID; // Type ID Checking Register
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
+ AT91_REG EMAC_USRIO; // USER Input/Output Register
+ AT91_REG EMAC_WOL; // Wake On LAN Register
+ AT91_REG Reserved1[13]; //
+ AT91_REG EMAC_REV; // Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
-/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */
-#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */
-#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */
-#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */
-#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */
-#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
-/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
-#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */
-#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */
-#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
-#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
-#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
-#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */
-#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
-/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
-#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
-#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */
-#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */
-#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
-/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
-#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */
-#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */
-#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
-#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */
-#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */
-#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */
-#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
-/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */
-#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */
-#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */
-#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */
-#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */
-/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
-#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */
-/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
-#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */
-#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */
-#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */
-#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */
-/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
-#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */
+// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
-/* ***************************************************************************** */
-typedef struct _AT91S_ADC
-{
- AT91_REG ADC_CR; /* ADC Control Register */
- AT91_REG ADC_MR; /* ADC Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG ADC_CHER; /* ADC Channel Enable Register */
- AT91_REG ADC_CHDR; /* ADC Channel Disable Register */
- AT91_REG ADC_CHSR; /* ADC Channel Status Register */
- AT91_REG ADC_SR; /* ADC Status Register */
- AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */
- AT91_REG ADC_IER; /* ADC Interrupt Enable Register */
- AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */
- AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */
- AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */
- AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */
- AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */
- AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */
- AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */
- AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */
- AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */
- AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */
- AT91_REG Reserved1[ 44 ]; /* */
- AT91_REG ADC_RPR; /* Receive Pointer Register */
- AT91_REG ADC_RCR; /* Receive Counter Register */
- AT91_REG ADC_TPR; /* Transmit Pointer Register */
- AT91_REG ADC_TCR; /* Transmit Counter Register */
- AT91_REG ADC_RNPR; /* Receive Next Pointer Register */
- AT91_REG ADC_RNCR; /* Receive Next Counter Register */
- AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG ADC_TNCR; /* Transmit Next Counter Register */
- AT91_REG ADC_PTCR; /* PDC Transfer Control Register */
- AT91_REG ADC_PTSR; /* PDC Transfer Status Register */
-} AT91S_ADC, * AT91PS_ADC;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+ AT91_REG ADC_CR; // ADC Control Register
+ AT91_REG ADC_MR; // ADC Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
+ AT91_REG ADC_SR; // ADC Status Register
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
+ AT91_REG Reserved1[44]; //
+ AT91_REG ADC_RPR; // Receive Pointer Register
+ AT91_REG ADC_RCR; // Receive Counter Register
+ AT91_REG ADC_TPR; // Transmit Pointer Register
+ AT91_REG ADC_TCR; // Transmit Counter Register
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
-/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
-#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */
-#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */
-/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
-#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */
-#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software */
-#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
-#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */
-#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */
-#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */
-#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */
-#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */
-#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */
-#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */
-#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */
-#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */
-#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */
-#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */
-#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */
-#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */
-#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
-#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */
-/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
-#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */
-#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */
-#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */
-#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */
-#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */
-#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */
-#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */
-#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */
-/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
-/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
-/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
-#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */
-#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */
-#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */
-#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */
-/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
-#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
-/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
-/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
-/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
-/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
-#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */
-/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
-/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
-/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
-/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
-/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
-/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
-/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
-/* ***************************************************************************** */
-typedef struct _AT91S_AES
-{
- AT91_REG AES_CR; /* Control Register */
- AT91_REG AES_MR; /* Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG AES_IER; /* Interrupt Enable Register */
- AT91_REG AES_IDR; /* Interrupt Disable Register */
- AT91_REG AES_IMR; /* Interrupt Mask Register */
- AT91_REG AES_ISR; /* Interrupt Status Register */
- AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */
- AT91_REG Reserved1[ 4 ]; /* */
- AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */
- AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */
- AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */
- AT91_REG Reserved2[ 35 ]; /* */
- AT91_REG AES_VR; /* AES Version Register */
- AT91_REG AES_RPR; /* Receive Pointer Register */
- AT91_REG AES_RCR; /* Receive Counter Register */
- AT91_REG AES_TPR; /* Transmit Pointer Register */
- AT91_REG AES_TCR; /* Transmit Counter Register */
- AT91_REG AES_RNPR; /* Receive Next Pointer Register */
- AT91_REG AES_RNCR; /* Receive Next Counter Register */
- AT91_REG AES_TNPR; /* Transmit Next Pointer Register */
- AT91_REG AES_TNCR; /* Transmit Next Counter Register */
- AT91_REG AES_PTCR; /* PDC Transfer Control Register */
- AT91_REG AES_PTSR; /* PDC Transfer Status Register */
-} AT91S_AES, * AT91PS_AES;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+ AT91_REG AES_CR; // Control Register
+ AT91_REG AES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AES_IER; // Interrupt Enable Register
+ AT91_REG AES_IDR; // Interrupt Disable Register
+ AT91_REG AES_IMR; // Interrupt Mask Register
+ AT91_REG AES_ISR; // Interrupt Status Register
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register
+ AT91_REG Reserved1[4]; //
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register
+ AT91_REG Reserved2[35]; //
+ AT91_REG AES_VR; // AES Version Register
+ AT91_REG AES_RPR; // Receive Pointer Register
+ AT91_REG AES_RCR; // Receive Counter Register
+ AT91_REG AES_TPR; // Transmit Pointer Register
+ AT91_REG AES_TCR; // Transmit Counter Register
+ AT91_REG AES_RNPR; // Receive Next Pointer Register
+ AT91_REG AES_RNCR; // Receive Next Counter Register
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register
+ AT91_REG AES_TNCR; // Transmit Next Counter Register
+ AT91_REG AES_PTCR; // PDC Transfer Control Register
+ AT91_REG AES_PTSR; // PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
-/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
-#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */
-#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */
-#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */
-/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
-#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */
-#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */
-#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */
-#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
-#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
-#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */
-#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */
-#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */
-#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */
-#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */
-#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */
-#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */
-#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */
-#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */
-#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */
-#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */
-#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */
-#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */
-#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */
-#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */
-#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */
-#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */
-#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */
-#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */
-#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */
-#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
-/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */
-#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */
-#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */
-#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */
-#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */
-#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */
-/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
-#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
-#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
-#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
-#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
-#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
-#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */
+// -------- AES_CR : (AES Offset: 0x0) Control Register --------
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
-/* ***************************************************************************** */
-typedef struct _AT91S_TDES
-{
- AT91_REG TDES_CR; /* Control Register */
- AT91_REG TDES_MR; /* Mode Register */
- AT91_REG Reserved0[ 2 ]; /* */
- AT91_REG TDES_IER; /* Interrupt Enable Register */
- AT91_REG TDES_IDR; /* Interrupt Disable Register */
- AT91_REG TDES_IMR; /* Interrupt Mask Register */
- AT91_REG TDES_ISR; /* Interrupt Status Register */
- AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */
- AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */
- AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */
- AT91_REG Reserved1[ 2 ]; /* */
- AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */
- AT91_REG Reserved2[ 2 ]; /* */
- AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */
- AT91_REG Reserved3[ 2 ]; /* */
- AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */
- AT91_REG Reserved4[ 37 ]; /* */
- AT91_REG TDES_VR; /* TDES Version Register */
- AT91_REG TDES_RPR; /* Receive Pointer Register */
- AT91_REG TDES_RCR; /* Receive Counter Register */
- AT91_REG TDES_TPR; /* Transmit Pointer Register */
- AT91_REG TDES_TCR; /* Transmit Counter Register */
- AT91_REG TDES_RNPR; /* Receive Next Pointer Register */
- AT91_REG TDES_RNCR; /* Receive Next Counter Register */
- AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */
- AT91_REG TDES_TNCR; /* Transmit Next Counter Register */
- AT91_REG TDES_PTCR; /* PDC Transfer Control Register */
- AT91_REG TDES_PTSR; /* PDC Transfer Status Register */
-} AT91S_TDES, * AT91PS_TDES;
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+ AT91_REG TDES_CR; // Control Register
+ AT91_REG TDES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG TDES_IER; // Interrupt Enable Register
+ AT91_REG TDES_IDR; // Interrupt Disable Register
+ AT91_REG TDES_IMR; // Interrupt Mask Register
+ AT91_REG TDES_ISR; // Interrupt Status Register
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
+ AT91_REG Reserved4[37]; //
+ AT91_REG TDES_VR; // TDES Version Register
+ AT91_REG TDES_RPR; // Receive Pointer Register
+ AT91_REG TDES_RCR; // Receive Counter Register
+ AT91_REG TDES_TPR; // Transmit Pointer Register
+ AT91_REG TDES_TCR; // Transmit Counter Register
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register
+ AT91_REG TDES_RNCR; // Receive Next Counter Register
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
-/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
-#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */
-#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */
-/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
-#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */
-#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */
-#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */
-#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */
-#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
-#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
-#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */
-#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */
-#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
-#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
-#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
-#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
-#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */
-#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
-#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */
-#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */
-#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */
-#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */
-/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */
-#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */
-#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */
-#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */
-#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */
-#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */
-/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
-#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
-#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
-#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
-#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-/* ***************************************************************************** */
-/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-/* ========== Register definition for SYS peripheral ========== */
-/* ========== Register definition for AIC peripheral ========== */
-#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
-#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
-#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
-#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
-#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
-#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
-#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
-#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
-#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
-#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
-#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
-#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
-#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
-#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
-#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
-#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
-#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
-#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
-/* ========== Register definition for PDC_DBGU peripheral ========== */
-#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
-#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
-#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
-#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
-#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
-#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
-#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
-#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
-#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
-#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
-/* ========== Register definition for DBGU peripheral ========== */
-#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
-#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
-#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
-#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
-#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */
-#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
-#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
-#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
-#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
-#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
-#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
-#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
-/* ========== Register definition for PIOA peripheral ========== */
-#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
-#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
-#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
-#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
-#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
-#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
-#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
-#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
-#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
-#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
-#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
-#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
-#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
-#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
-#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
-#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
-#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
-#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
-#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
-#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
-#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
-#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
-#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
-#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
-#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
-#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
-#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
-/* ========== Register definition for PIOB peripheral ========== */
-#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
-#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
-#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
-#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
-#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */
-#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
-#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */
-#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
-#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
-#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
-#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
-#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
-#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
-#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
-#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
-#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
-#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
-#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
-#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
-#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
-#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
-#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */
-#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
-#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
-#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */
-#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
-#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */
-#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
-/* ========== Register definition for CKGR peripheral ========== */
-#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
-#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
-#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */
-/* ========== Register definition for PMC peripheral ========== */
-#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
-#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
-#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
-#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
-#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
-#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
-#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
-#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
-#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
-#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */
-#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
-#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
-#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
-#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
-/* ========== Register definition for RSTC peripheral ========== */
-#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
-#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
-#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
-/* ========== Register definition for RTTC peripheral ========== */
-#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
-#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
-#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
-#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
-/* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
-#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
-#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
-#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
-/* ========== Register definition for WDTC peripheral ========== */
-#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
-#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
-#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
-/* ========== Register definition for VREG peripheral ========== */
-#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
-/* ========== Register definition for MC peripheral ========== */
-#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
-#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
-#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
-#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
-#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
-#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
-/* ========== Register definition for PDC_SPI1 peripheral ========== */
-#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
-#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
-#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
-#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
-#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
-#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
-#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
-#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
-#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
-#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
-/* ========== Register definition for SPI1 peripheral ========== */
-#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
-#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
-#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */
-#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */
-#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
-#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */
-#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */
-#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */
-#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */
-/* ========== Register definition for PDC_SPI0 peripheral ========== */
-#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
-#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
-#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
-#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
-#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
-#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
-#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
-#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
-#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
-#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
-/* ========== Register definition for SPI0 peripheral ========== */
-#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
-#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */
-#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
-#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */
-#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */
-#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
-#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */
-#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */
-#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */
-/* ========== Register definition for PDC_US1 peripheral ========== */
-#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
-#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
-#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
-#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
-#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
-#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
-#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
-#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
-#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
-#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
-/* ========== Register definition for US1 peripheral ========== */
-#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
-#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
-#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
-#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
-#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
-#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
-#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
-#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
-#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
-#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
-#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
-#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
-#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
-#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
-/* ========== Register definition for PDC_US0 peripheral ========== */
-#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
-#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
-#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
-#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
-#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
-#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
-#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
-#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
-#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
-#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
-/* ========== Register definition for US0 peripheral ========== */
-#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
-#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
-#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
-#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
-#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
-#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
-#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
-#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
-#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
-#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
-#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
-#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
-#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
-#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
-/* ========== Register definition for PDC_SSC peripheral ========== */
-#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
-#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
-#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
-#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
-#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
-#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
-#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
-#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
-#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
-#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
-/* ========== Register definition for SSC peripheral ========== */
-#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
-#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
-#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
-#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
-#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
-#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
-#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
-#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
-#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
-#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
-#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
-#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
-#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
-#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
-/* ========== Register definition for TWI peripheral ========== */
-#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
-#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
-#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
-#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
-#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
-#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
-#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
-#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
-#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
-#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
-/* ========== Register definition for PWMC_CH3 peripheral ========== */
-#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
-#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
-#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
-#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
-#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
-/* ========== Register definition for PWMC_CH2 peripheral ========== */
-#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
-#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
-#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
-#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
-#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
-#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH1 peripheral ========== */
-#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
-#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
-#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
-#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
-#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
-/* ========== Register definition for PWMC_CH0 peripheral ========== */
-#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
-#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
-#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
-#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
-#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
-/* ========== Register definition for PWMC peripheral ========== */
-#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
-#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
-#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
-#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
-#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
-#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
-#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
-#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
-#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
-/* ========== Register definition for UDP peripheral ========== */
-#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
-#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
-#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
-#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
-#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
-#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
-#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
-#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
-#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
-#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
-#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
-#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
-/* ========== Register definition for TC0 peripheral ========== */
-#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
-#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
-#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
-#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
-#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
-#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
-#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
-#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
-#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
-/* ========== Register definition for TC1 peripheral ========== */
-#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
-#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
-#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
-#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
-#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
-#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
-#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
-#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
-#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
-/* ========== Register definition for TC2 peripheral ========== */
-#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
-#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
-#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
-#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
-#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
-#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
-#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
-#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
-#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
-/* ========== Register definition for TCB peripheral ========== */
-#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
-#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
-/* ========== Register definition for CAN_MB0 peripheral ========== */
-#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
-#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
-#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
-#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
-#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
-#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
-#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
-/* ========== Register definition for CAN_MB1 peripheral ========== */
-#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
-#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
-#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
-#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
-#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
-#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
-#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
-/* ========== Register definition for CAN_MB2 peripheral ========== */
-#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
-#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
-#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
-#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
-#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
-#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
-#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
-/* ========== Register definition for CAN_MB3 peripheral ========== */
-#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
-#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
-#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
-#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
-#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
-#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
-#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
-/* ========== Register definition for CAN_MB4 peripheral ========== */
-#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
-#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
-#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
-#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
-#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
-#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
-#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
-#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB5 peripheral ========== */
-#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
-#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
-#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
-#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
-#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
-#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
-#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
-#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB6 peripheral ========== */
-#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
-#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
-#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
-#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
-#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
-#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
-#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
-/* ========== Register definition for CAN_MB7 peripheral ========== */
-#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
-#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
-#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
-#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
-#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
-#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
-#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
-/* ========== Register definition for CAN peripheral ========== */
-#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */
-#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
-#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
-#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */
-#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */
-#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */
-#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
-#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */
-#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */
-#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */
-#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */
-#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */
-/* ========== Register definition for EMAC peripheral ========== */
-#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
-#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
-#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
-#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
-#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */
-#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
-#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
-#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
-#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
-#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */
-#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
-#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */
-#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
-#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
-#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
-#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
-#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
-#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
-#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
-#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
-#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
-#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */
-#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
-#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
-#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
-#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
-#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
-#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
-#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
-#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
-#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
-#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
-#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
-#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
-#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
-#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */
-#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
-#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
-#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
-#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
-#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */
-#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
-#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
-#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
-#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
-#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
-#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
-#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
-/* ========== Register definition for PDC_ADC peripheral ========== */
-#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
-#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
-#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
-#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
-#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
-#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
-#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
-#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
-#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
-#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
-/* ========== Register definition for ADC peripheral ========== */
-#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
-#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
-#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
-#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
-#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
-#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
-#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
-#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
-#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
-#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
-#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
-#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
-#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
-#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
-#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
-#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
-#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
-#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
-/* ========== Register definition for PDC_AES peripheral ========== */
-#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
-#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
-#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
-#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
-#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
-#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
-#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
-#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
-#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
-#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
-/* ========== Register definition for AES peripheral ========== */
-#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
-#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */
-#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */
-#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */
-#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */
-#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */
-#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
-#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
-#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
-#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */
-#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */
-/* ========== Register definition for PDC_TDES peripheral ========== */
-#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
-#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
-#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
-#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
-#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
-#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
-#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
-#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
-#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
-#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
-/* ========== Register definition for TDES peripheral ========== */
-#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
-#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
-#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
-#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */
-#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
-#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */
-#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
-#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */
-#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */
-#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
-#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */
-#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */
-#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ==========
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ==========
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ==========
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ==========
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ==========
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ==========
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ==========
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ==========
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ==========
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ==========
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ==========
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ==========
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ==========
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ==========
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ==========
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ==========
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ==========
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ==========
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
-/* ***************************************************************************** */
-/* PIO DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */
-#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */
-#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */
-#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */
-#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */
-#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */
-#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */
-#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */
-#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */
-#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */
-#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */
-#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */
-#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */
-#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */
-#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */
-#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */
-#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */
-#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */
-#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */
-#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */
-#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */
-#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */
-#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */
-#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */
-#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */
-#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */
-#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */
-#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */
-#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */
-#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */
-#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */
-#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */
-#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */
-#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */
-#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */
-#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */
-#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */
-#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */
-#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */
-#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */
-#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */
-#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */
-#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */
-#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */
-#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */
-#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */
-#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */
-#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */
-#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */
-#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */
-#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */
-#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */
-#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */
-#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */
-#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */
-#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */
-#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */
-#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */
-#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */
-#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */
-#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */
-#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */
-#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */
-#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */
-#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */
-#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */
-#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */
-#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */
-#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */
-#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */
-#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */
-#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */
-#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */
-#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */
-#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */
-#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */
-#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */
-#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */
-#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */
-#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */
-#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */
-#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */
-#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */
-#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */
-#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */
-#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */
-#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */
-#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */
-#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */
-#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */
-#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */
-#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */
-#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */
-#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */
-#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */
-#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */
-#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */
-#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */
-#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */
-#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */
-#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */
-#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */
-#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */
-#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */
-#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */
-#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */
-#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */
-#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */
-#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */
-#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */
-#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */
-#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */
-#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */
-#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */
-#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */
-#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */
-#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */
-#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */
-#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */
-#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */
-#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */
-#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */
-#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */
-#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */
-#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-/* ***************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */
-#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */
-#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */
-#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */
-#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */
-#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */
-#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */
-#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */
-#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */
-#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */
-#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */
-#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */
-#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */
-#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */
-#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */
-#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */
-#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */
-#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */
-#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */
-#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */
-#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */
-#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */
-#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */
-#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */
-#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */
-#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */
-#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */
-#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */
-#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */
-#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-/* ***************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */
-#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */
-#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */
-#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */
-#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */
-#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */
-#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */
-#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */
-#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */
-#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */
-#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */
-#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */
-#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */
-#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */
-#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */
-#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */
-#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */
-#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */
-#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */
-#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */
-#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */
-#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */
-#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */
-#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */
-#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */
-#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
-#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
-#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
-#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
-#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */
-#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */
-#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */
-#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */
-#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */
-#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */
-#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */
-#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */
-#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */
-#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */
-#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */
-#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */
-#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */
-#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */
-#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */
-#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */
-#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */
-#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */
-#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */
-#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */
-#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */
-#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
-/* ***************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */
-#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */
-#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */
-#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
-#endif /* ifndef AT91SAM7X256_H */
+#endif
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
index e50bd82..5b8dfe8 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
@@ -1,2444 +1,2446 @@
-/* ---------------------------------------------------------------------------- */
-/* ATMEL Microcontroller Software Support - ROUSSET - */
-/* ---------------------------------------------------------------------------- */
-/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* ---------------------------------------------------------------------------- */
-/* File Name : AT91SAM7X256.h */
-/* Object : AT91SAM7X256 definitions */
-/* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */
-/* */
-/* CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */
-/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */
-/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
-/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */
-/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */
-/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
-/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
-/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
-/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */
-/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */
-/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */
-/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */
-/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */
-/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */
-/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
-/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
-/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
-/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
-/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
-/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
-/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */
-/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */
-/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
-/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */
-/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
-/* ---------------------------------------------------------------------------- */
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM7X256.h
+// Object : AT91SAM7X256 definitions
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+//
+// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// ----------------------------------------------------------------------------
-/* Hardware register definition */
+// Hardware register definition
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR System Peripherals */
-/* ***************************************************************************** */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_AIC structure *** */
-#define AIC_SMR ( 0 ) /* Source Mode Register */
-#define AIC_SVR ( 128 ) /* Source Vector Register */
-#define AIC_IVR ( 256 ) /* IRQ Vector Register */
-#define AIC_FVR ( 260 ) /* FIQ Vector Register */
-#define AIC_ISR ( 264 ) /* Interrupt Status Register */
-#define AIC_IPR ( 268 ) /* Interrupt Pending Register */
-#define AIC_IMR ( 272 ) /* Interrupt Mask Register */
-#define AIC_CISR ( 276 ) /* Core Interrupt Status Register */
-#define AIC_IECR ( 288 ) /* Interrupt Enable Command Register */
-#define AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */
-#define AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */
-#define AIC_ISCR ( 300 ) /* Interrupt Set Command Register */
-#define AIC_EOICR ( 304 ) /* End of Interrupt Command Register */
-#define AIC_SPU ( 308 ) /* Spurious Vector Register */
-#define AIC_DCR ( 312 ) /* Debug Control Register (Protect) */
-#define AIC_FFER ( 320 ) /* Fast Forcing Enable Register */
-#define AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */
-#define AIC_FFSR ( 328 ) /* Fast Forcing Status Register */
-/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
-#define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */
-#define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */
-#define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */
-#define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
-/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
-#define AT91C_AIC_NFIQ ( 0x1 << 0 ) /* (AIC) NFIQ Status */
-#define AT91C_AIC_NIRQ ( 0x1 << 1 ) /* (AIC) NIRQ Status */
-/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
-#define AT91C_AIC_DCR_PROT ( 0x1 << 0 ) /* (AIC) Protection Mode */
-#define AT91C_AIC_DCR_GMSK ( 0x1 << 1 ) /* (AIC) General Mask */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+// *** Register offset in AT91S_AIC structure ***
+#define AIC_SMR ( 0) // Source Mode Register
+#define AIC_SVR (128) // Source Vector Register
+#define AIC_IVR (256) // IRQ Vector Register
+#define AIC_FVR (260) // FIQ Vector Register
+#define AIC_ISR (264) // Interrupt Status Register
+#define AIC_IPR (268) // Interrupt Pending Register
+#define AIC_IMR (272) // Interrupt Mask Register
+#define AIC_CISR (276) // Core Interrupt Status Register
+#define AIC_IECR (288) // Interrupt Enable Command Register
+#define AIC_IDCR (292) // Interrupt Disable Command Register
+#define AIC_ICCR (296) // Interrupt Clear Command Register
+#define AIC_ISCR (300) // Interrupt Set Command Register
+#define AIC_EOICR (304) // End of Interrupt Command Register
+#define AIC_SPU (308) // Spurious Vector Register
+#define AIC_DCR (312) // Debug Control Register (Protect)
+#define AIC_FFER (320) // Fast Forcing Enable Register
+#define AIC_FFDR (324) // Fast Forcing Disable Register
+#define AIC_FFSR (328) // Fast Forcing Status Register
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PDC structure *** */
-#define PDC_RPR ( 0 ) /* Receive Pointer Register */
-#define PDC_RCR ( 4 ) /* Receive Counter Register */
-#define PDC_TPR ( 8 ) /* Transmit Pointer Register */
-#define PDC_TCR ( 12 ) /* Transmit Counter Register */
-#define PDC_RNPR ( 16 ) /* Receive Next Pointer Register */
-#define PDC_RNCR ( 20 ) /* Receive Next Counter Register */
-#define PDC_TNPR ( 24 ) /* Transmit Next Pointer Register */
-#define PDC_TNCR ( 28 ) /* Transmit Next Counter Register */
-#define PDC_PTCR ( 32 ) /* PDC Transfer Control Register */
-#define PDC_PTSR ( 36 ) /* PDC Transfer Status Register */
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+// *** Register offset in AT91S_PDC structure ***
+#define PDC_RPR ( 0) // Receive Pointer Register
+#define PDC_RCR ( 4) // Receive Counter Register
+#define PDC_TPR ( 8) // Transmit Pointer Register
+#define PDC_TCR (12) // Transmit Counter Register
+#define PDC_RNPR (16) // Receive Next Pointer Register
+#define PDC_RNCR (20) // Receive Next Counter Register
+#define PDC_TNPR (24) // Transmit Next Pointer Register
+#define PDC_TNCR (28) // Transmit Next Counter Register
+#define PDC_PTCR (32) // PDC Transfer Control Register
+#define PDC_PTSR (36) // PDC Transfer Status Register
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_DBGU structure *** */
-#define DBGU_CR ( 0 ) /* Control Register */
-#define DBGU_MR ( 4 ) /* Mode Register */
-#define DBGU_IER ( 8 ) /* Interrupt Enable Register */
-#define DBGU_IDR ( 12 ) /* Interrupt Disable Register */
-#define DBGU_IMR ( 16 ) /* Interrupt Mask Register */
-#define DBGU_CSR ( 20 ) /* Channel Status Register */
-#define DBGU_RHR ( 24 ) /* Receiver Holding Register */
-#define DBGU_THR ( 28 ) /* Transmitter Holding Register */
-#define DBGU_BRGR ( 32 ) /* Baud Rate Generator Register */
-#define DBGU_CIDR ( 64 ) /* Chip ID Register */
-#define DBGU_EXID ( 68 ) /* Chip ID Extension Register */
-#define DBGU_FNTR ( 72 ) /* Force NTRST Register */
-#define DBGU_RPR ( 256 ) /* Receive Pointer Register */
-#define DBGU_RCR ( 260 ) /* Receive Counter Register */
-#define DBGU_TPR ( 264 ) /* Transmit Pointer Register */
-#define DBGU_TCR ( 268 ) /* Transmit Counter Register */
-#define DBGU_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define DBGU_RNCR ( 276 ) /* Receive Next Counter Register */
-#define DBGU_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define DBGU_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define DBGU_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define DBGU_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ( 0x1 << 2 ) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ( 0x1 << 3 ) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ( 0x1 << 4 ) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ( 0x1 << 6 ) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ( 0x1 << 7 ) /* (DBGU) Transmitter Disable */
-#define AT91C_US_RSTSTA ( 0x1 << 8 ) /* (DBGU) Reset Status Bits */
-/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_PAR ( 0x7 << 9 ) /* (DBGU) Parity type */
-#define AT91C_US_PAR_EVEN ( 0x0 << 9 ) /* (DBGU) Even Parity */
-#define AT91C_US_PAR_ODD ( 0x1 << 9 ) /* (DBGU) Odd Parity */
-#define AT91C_US_PAR_SPACE ( 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK ( 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE ( 0x4 << 9 ) /* (DBGU) No Parity */
-#define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9 ) /* (DBGU) Multi-drop mode */
-#define AT91C_US_CHMODE ( 0x3 << 14 ) /* (DBGU) Channel Mode */
-#define AT91C_US_CHMODE_NORMAL ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
-#define AT91C_US_CHMODE_AUTO ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
-#define AT91C_US_CHMODE_LOCAL ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
-#define AT91C_US_CHMODE_REMOTE ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ( 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ( 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ( 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ( 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ( 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ( 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ( 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
-/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
-/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
-#define AT91C_US_FORCE_NTRST ( 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+// *** Register offset in AT91S_DBGU structure ***
+#define DBGU_CR ( 0) // Control Register
+#define DBGU_MR ( 4) // Mode Register
+#define DBGU_IER ( 8) // Interrupt Enable Register
+#define DBGU_IDR (12) // Interrupt Disable Register
+#define DBGU_IMR (16) // Interrupt Mask Register
+#define DBGU_CSR (20) // Channel Status Register
+#define DBGU_RHR (24) // Receiver Holding Register
+#define DBGU_THR (28) // Transmitter Holding Register
+#define DBGU_BRGR (32) // Baud Rate Generator Register
+#define DBGU_CIDR (64) // Chip ID Register
+#define DBGU_EXID (68) // Chip ID Extension Register
+#define DBGU_FNTR (72) // Force NTRST Register
+#define DBGU_RPR (256) // Receive Pointer Register
+#define DBGU_RCR (260) // Receive Counter Register
+#define DBGU_TPR (264) // Transmit Pointer Register
+#define DBGU_TCR (268) // Transmit Counter Register
+#define DBGU_RNPR (272) // Receive Next Pointer Register
+#define DBGU_RNCR (276) // Receive Next Counter Register
+#define DBGU_TNPR (280) // Transmit Next Pointer Register
+#define DBGU_TNCR (284) // Transmit Next Counter Register
+#define DBGU_PTCR (288) // PDC Transfer Control Register
+#define DBGU_PTSR (292) // PDC Transfer Status Register
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PIO structure *** */
-#define PIO_PER ( 0 ) /* PIO Enable Register */
-#define PIO_PDR ( 4 ) /* PIO Disable Register */
-#define PIO_PSR ( 8 ) /* PIO Status Register */
-#define PIO_OER ( 16 ) /* Output Enable Register */
-#define PIO_ODR ( 20 ) /* Output Disable Registerr */
-#define PIO_OSR ( 24 ) /* Output Status Register */
-#define PIO_IFER ( 32 ) /* Input Filter Enable Register */
-#define PIO_IFDR ( 36 ) /* Input Filter Disable Register */
-#define PIO_IFSR ( 40 ) /* Input Filter Status Register */
-#define PIO_SODR ( 48 ) /* Set Output Data Register */
-#define PIO_CODR ( 52 ) /* Clear Output Data Register */
-#define PIO_ODSR ( 56 ) /* Output Data Status Register */
-#define PIO_PDSR ( 60 ) /* Pin Data Status Register */
-#define PIO_IER ( 64 ) /* Interrupt Enable Register */
-#define PIO_IDR ( 68 ) /* Interrupt Disable Register */
-#define PIO_IMR ( 72 ) /* Interrupt Mask Register */
-#define PIO_ISR ( 76 ) /* Interrupt Status Register */
-#define PIO_MDER ( 80 ) /* Multi-driver Enable Register */
-#define PIO_MDDR ( 84 ) /* Multi-driver Disable Register */
-#define PIO_MDSR ( 88 ) /* Multi-driver Status Register */
-#define PIO_PPUDR ( 96 ) /* Pull-up Disable Register */
-#define PIO_PPUER ( 100 ) /* Pull-up Enable Register */
-#define PIO_PPUSR ( 104 ) /* Pull-up Status Register */
-#define PIO_ASR ( 112 ) /* Select A Register */
-#define PIO_BSR ( 116 ) /* Select B Register */
-#define PIO_ABSR ( 120 ) /* AB Select Status Register */
-#define PIO_OWER ( 160 ) /* Output Write Enable Register */
-#define PIO_OWDR ( 164 ) /* Output Write Disable Register */
-#define PIO_OWSR ( 168 ) /* Output Write Status Register */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PIO structure ***
+#define PIO_PER ( 0) // PIO Enable Register
+#define PIO_PDR ( 4) // PIO Disable Register
+#define PIO_PSR ( 8) // PIO Status Register
+#define PIO_OER (16) // Output Enable Register
+#define PIO_ODR (20) // Output Disable Registerr
+#define PIO_OSR (24) // Output Status Register
+#define PIO_IFER (32) // Input Filter Enable Register
+#define PIO_IFDR (36) // Input Filter Disable Register
+#define PIO_IFSR (40) // Input Filter Status Register
+#define PIO_SODR (48) // Set Output Data Register
+#define PIO_CODR (52) // Clear Output Data Register
+#define PIO_ODSR (56) // Output Data Status Register
+#define PIO_PDSR (60) // Pin Data Status Register
+#define PIO_IER (64) // Interrupt Enable Register
+#define PIO_IDR (68) // Interrupt Disable Register
+#define PIO_IMR (72) // Interrupt Mask Register
+#define PIO_ISR (76) // Interrupt Status Register
+#define PIO_MDER (80) // Multi-driver Enable Register
+#define PIO_MDDR (84) // Multi-driver Disable Register
+#define PIO_MDSR (88) // Multi-driver Status Register
+#define PIO_PPUDR (96) // Pull-up Disable Register
+#define PIO_PPUER (100) // Pull-up Enable Register
+#define PIO_PPUSR (104) // Pull-up Status Register
+#define PIO_ASR (112) // Select A Register
+#define PIO_BSR (116) // Select B Register
+#define PIO_ABSR (120) // AB Select Status Register
+#define PIO_OWER (160) // Output Write Enable Register
+#define PIO_OWDR (164) // Output Write Disable Register
+#define PIO_OWSR (168) // Output Write Status Register
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_CKGR structure *** */
-#define CKGR_MOR ( 0 ) /* Main Oscillator Register */
-#define CKGR_MCFR ( 4 ) /* Main Clock Frequency Register */
-#define CKGR_PLLR ( 12 ) /* PLL Register */
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN ( 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCBYPASS ( 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */
-#define AT91C_CKGR_OSCOUNT ( 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY ( 0x1 << 16 ) /* (CKGR) Main Clock Ready */
-/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIV ( 0xFF << 0 ) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIV_0 ( 0x0 ) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIV_BYPASS ( 0x1 ) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLCOUNT ( 0x3F << 8 ) /* (CKGR) PLL Counter */
-#define AT91C_CKGR_OUT ( 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */
-#define AT91C_CKGR_OUT_0 ( 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_1 ( 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_2 ( 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_OUT_3 ( 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
-#define AT91C_CKGR_MUL ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
-#define AT91C_CKGR_USBDIV ( 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */
-#define AT91C_CKGR_USBDIV_0 ( 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */
-#define AT91C_CKGR_USBDIV_1 ( 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */
-#define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+// *** Register offset in AT91S_CKGR structure ***
+#define CKGR_MOR ( 0) // Main Oscillator Register
+#define CKGR_MCFR ( 4) // Main Clock Frequency Register
+#define CKGR_PLLR (12) // PLL Register
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PMC structure *** */
-#define PMC_SCER ( 0 ) /* System Clock Enable Register */
-#define PMC_SCDR ( 4 ) /* System Clock Disable Register */
-#define PMC_SCSR ( 8 ) /* System Clock Status Register */
-#define PMC_PCER ( 16 ) /* Peripheral Clock Enable Register */
-#define PMC_PCDR ( 20 ) /* Peripheral Clock Disable Register */
-#define PMC_PCSR ( 24 ) /* Peripheral Clock Status Register */
-#define PMC_MOR ( 32 ) /* Main Oscillator Register */
-#define PMC_MCFR ( 36 ) /* Main Clock Frequency Register */
-#define PMC_PLLR ( 44 ) /* PLL Register */
-#define PMC_MCKR ( 48 ) /* Master Clock Register */
-#define PMC_PCKR ( 64 ) /* Programmable Clock Register */
-#define PMC_IER ( 96 ) /* Interrupt Enable Register */
-#define PMC_IDR ( 100 ) /* Interrupt Disable Register */
-#define PMC_SR ( 104 ) /* Status Register */
-#define PMC_IMR ( 108 ) /* Interrupt Mask Register */
-/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
-#define AT91C_PMC_PCK ( 0x1 << 0 ) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP ( 0x1 << 7 ) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_PCK0 ( 0x1 << 8 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1 ( 0x1 << 9 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2 ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3 ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */
-/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
-/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
-/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
-/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
-/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
-/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
-#define AT91C_PMC_CSS ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ( 0x0 ) /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ( 0x1 ) /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLL_CLK ( 0x3 ) /* (PMC) Clock from PLL is selected */
-#define AT91C_PMC_PRES ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK ( 0x0 << 2 ) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2 ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4 ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8 ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16 ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32 ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64 ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
-/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
-/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
-#define AT91C_PMC_MOSCS ( 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCK ( 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY ( 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY ( 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY ( 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
-/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
-/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PMC structure ***
+#define PMC_SCER ( 0) // System Clock Enable Register
+#define PMC_SCDR ( 4) // System Clock Disable Register
+#define PMC_SCSR ( 8) // System Clock Status Register
+#define PMC_PCER (16) // Peripheral Clock Enable Register
+#define PMC_PCDR (20) // Peripheral Clock Disable Register
+#define PMC_PCSR (24) // Peripheral Clock Status Register
+#define PMC_MOR (32) // Main Oscillator Register
+#define PMC_MCFR (36) // Main Clock Frequency Register
+#define PMC_PLLR (44) // PLL Register
+#define PMC_MCKR (48) // Master Clock Register
+#define PMC_PCKR (64) // Programmable Clock Register
+#define PMC_IER (96) // Interrupt Enable Register
+#define PMC_IDR (100) // Interrupt Disable Register
+#define PMC_SR (104) // Status Register
+#define PMC_IMR (108) // Interrupt Mask Register
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Reset Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_RSTC structure *** */
-#define RSTC_RCR ( 0 ) /* Reset Control Register */
-#define RSTC_RSR ( 4 ) /* Reset Status Register */
-#define RSTC_RMR ( 8 ) /* Reset Mode Register */
-/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
-#define AT91C_RSTC_PROCRST ( 0x1 << 0 ) /* (RSTC) Processor Reset */
-#define AT91C_RSTC_PERRST ( 0x1 << 2 ) /* (RSTC) Peripheral Reset */
-#define AT91C_RSTC_EXTRST ( 0x1 << 3 ) /* (RSTC) External Reset */
-#define AT91C_RSTC_KEY ( 0xFF << 24 ) /* (RSTC) Password */
-/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
-#define AT91C_RSTC_URSTS ( 0x1 << 0 ) /* (RSTC) User Reset Status */
-#define AT91C_RSTC_BODSTS ( 0x1 << 1 ) /* (RSTC) Brownout Detection Status */
-#define AT91C_RSTC_RSTTYP ( 0x7 << 8 ) /* (RSTC) Reset Type */
-#define AT91C_RSTC_RSTTYP_POWERUP ( 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WAKEUP ( 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */
-#define AT91C_RSTC_RSTTYP_WATCHDOG ( 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occured. */
-#define AT91C_RSTC_RSTTYP_SOFTWARE ( 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */
-#define AT91C_RSTC_RSTTYP_USER ( 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */
-#define AT91C_RSTC_RSTTYP_BROWNOUT ( 0x5 << 8 ) /* (RSTC) Brownout Reset occured. */
-#define AT91C_RSTC_NRSTL ( 0x1 << 16 ) /* (RSTC) NRST pin level */
-#define AT91C_RSTC_SRCMP ( 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */
-/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
-#define AT91C_RSTC_URSTEN ( 0x1 << 0 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_URSTIEN ( 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */
-#define AT91C_RSTC_ERSTL ( 0xF << 8 ) /* (RSTC) User Reset Enable */
-#define AT91C_RSTC_BODIEN ( 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RSTC structure ***
+#define RSTC_RCR ( 0) // Reset Control Register
+#define RSTC_RSR ( 4) // Reset Status Register
+#define RSTC_RMR ( 8) // Reset Mode Register
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_RTTC structure *** */
-#define RTTC_RTMR ( 0 ) /* Real-time Mode Register */
-#define RTTC_RTAR ( 4 ) /* Real-time Alarm Register */
-#define RTTC_RTVR ( 8 ) /* Real-time Value Register */
-#define RTTC_RTSR ( 12 ) /* Real-time Status Register */
-/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
-#define AT91C_RTTC_RTPRES ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
-#define AT91C_RTTC_ALMIEN ( 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */
-#define AT91C_RTTC_RTTINCIEN ( 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */
-#define AT91C_RTTC_RTTRST ( 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */
-/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
-#define AT91C_RTTC_ALMV ( 0x0 << 0 ) /* (RTTC) Alarm Value */
-/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
-#define AT91C_RTTC_CRTV ( 0x0 << 0 ) /* (RTTC) Current Real-time Value */
-/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
-#define AT91C_RTTC_ALMS ( 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */
-#define AT91C_RTTC_RTTINC ( 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RTTC structure ***
+#define RTTC_RTMR ( 0) // Real-time Mode Register
+#define RTTC_RTAR ( 4) // Real-time Alarm Register
+#define RTTC_RTVR ( 8) // Real-time Value Register
+#define RTTC_RTSR (12) // Real-time Status Register
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PITC structure *** */
-#define PITC_PIMR ( 0 ) /* Period Interval Mode Register */
-#define PITC_PISR ( 4 ) /* Period Interval Status Register */
-#define PITC_PIVR ( 8 ) /* Period Interval Value Register */
-#define PITC_PIIR ( 12 ) /* Period Interval Image Register */
-/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
-#define AT91C_PITC_PIV ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
-#define AT91C_PITC_PITEN ( 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */
-#define AT91C_PITC_PITIEN ( 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */
-/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
-#define AT91C_PITC_PITS ( 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */
-/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
-#define AT91C_PITC_CPIV ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
-#define AT91C_PITC_PICNT ( 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */
-/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PITC structure ***
+#define PITC_PIMR ( 0) // Period Interval Mode Register
+#define PITC_PISR ( 4) // Period Interval Status Register
+#define PITC_PIVR ( 8) // Period Interval Value Register
+#define PITC_PIIR (12) // Period Interval Image Register
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_WDTC structure *** */
-#define WDTC_WDCR ( 0 ) /* Watchdog Control Register */
-#define WDTC_WDMR ( 4 ) /* Watchdog Mode Register */
-#define WDTC_WDSR ( 8 ) /* Watchdog Status Register */
-/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
-#define AT91C_WDTC_WDRSTT ( 0x1 << 0 ) /* (WDTC) Watchdog Restart */
-#define AT91C_WDTC_KEY ( 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */
-/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
-#define AT91C_WDTC_WDV ( 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDFIEN ( 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */
-#define AT91C_WDTC_WDRSTEN ( 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */
-#define AT91C_WDTC_WDRPROC ( 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */
-#define AT91C_WDTC_WDDIS ( 0x1 << 15 ) /* (WDTC) Watchdog Disable */
-#define AT91C_WDTC_WDD ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
-#define AT91C_WDTC_WDDBGHLT ( 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */
-#define AT91C_WDTC_WDIDLEHLT ( 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */
-/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
-#define AT91C_WDTC_WDUNF ( 0x1 << 0 ) /* (WDTC) Watchdog Underflow */
-#define AT91C_WDTC_WDERR ( 0x1 << 1 ) /* (WDTC) Watchdog Error */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_WDTC structure ***
+#define WDTC_WDCR ( 0) // Watchdog Control Register
+#define WDTC_WDMR ( 4) // Watchdog Mode Register
+#define WDTC_WDSR ( 8) // Watchdog Status Register
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_VREG structure *** */
-#define VREG_MR ( 0 ) /* Voltage Regulator Mode Register */
-/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
-#define AT91C_VREG_PSTDBY ( 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_VREG structure ***
+#define VREG_MR ( 0) // Voltage Regulator Mode Register
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Memory Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_MC structure *** */
-#define MC_RCR ( 0 ) /* MC Remap Control Register */
-#define MC_ASR ( 4 ) /* MC Abort Status Register */
-#define MC_AASR ( 8 ) /* MC Abort Address Status Register */
-#define MC_FMR ( 96 ) /* MC Flash Mode Register */
-#define MC_FCR ( 100 ) /* MC Flash Command Register */
-#define MC_FSR ( 104 ) /* MC Flash Status Register */
-/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
-#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */
-/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
-#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */
-#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */
-#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */
-#define AT91C_MC_ABTSZ_WORD ( 0x2 << 8 ) /* (MC) Word */
-#define AT91C_MC_ABTTYP ( 0x3 << 10 ) /* (MC) Abort Type Status */
-#define AT91C_MC_ABTTYP_DATAR ( 0x0 << 10 ) /* (MC) Data Read */
-#define AT91C_MC_ABTTYP_DATAW ( 0x1 << 10 ) /* (MC) Data Write */
-#define AT91C_MC_ABTTYP_FETCH ( 0x2 << 10 ) /* (MC) Code Fetch */
-#define AT91C_MC_MST0 ( 0x1 << 16 ) /* (MC) Master 0 Abort Source */
-#define AT91C_MC_MST1 ( 0x1 << 17 ) /* (MC) Master 1 Abort Source */
-#define AT91C_MC_SVMST0 ( 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */
-#define AT91C_MC_SVMST1 ( 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */
-/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
-#define AT91C_MC_FRDY ( 0x1 << 0 ) /* (MC) Flash Ready */
-#define AT91C_MC_LOCKE ( 0x1 << 2 ) /* (MC) Lock Error */
-#define AT91C_MC_PROGE ( 0x1 << 3 ) /* (MC) Programming Error */
-#define AT91C_MC_NEBP ( 0x1 << 7 ) /* (MC) No Erase Before Programming */
-#define AT91C_MC_FWS ( 0x3 << 8 ) /* (MC) Flash Wait State */
-#define AT91C_MC_FWS_0FWS ( 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */
-#define AT91C_MC_FWS_1FWS ( 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */
-#define AT91C_MC_FWS_2FWS ( 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FWS_3FWS ( 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */
-#define AT91C_MC_FMCN ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
-/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
-#define AT91C_MC_FCMD ( 0xF << 0 ) /* (MC) Flash Command */
-#define AT91C_MC_FCMD_START_PROG ( 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */
-#define AT91C_MC_FCMD_LOCK ( 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_PROG_AND_LOCK ( 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
-#define AT91C_MC_FCMD_UNLOCK ( 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
-#define AT91C_MC_FCMD_ERASE_ALL ( 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
-#define AT91C_MC_FCMD_SET_GP_NVM ( 0xB ) /* (MC) Set General Purpose NVM bits. */
-#define AT91C_MC_FCMD_CLR_GP_NVM ( 0xD ) /* (MC) Clear General Purpose NVM bits. */
-#define AT91C_MC_FCMD_SET_SECURITY ( 0xF ) /* (MC) Set Security Bit. */
-#define AT91C_MC_PAGEN ( 0x3FF << 8 ) /* (MC) Page Number */
-#define AT91C_MC_KEY ( 0xFF << 24 ) /* (MC) Writing Protect Key */
-/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
-#define AT91C_MC_SECURITY ( 0x1 << 4 ) /* (MC) Security Bit Status */
-#define AT91C_MC_GPNVM0 ( 0x1 << 8 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_GPNVM1 ( 0x1 << 9 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_GPNVM2 ( 0x1 << 10 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_GPNVM3 ( 0x1 << 11 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_GPNVM4 ( 0x1 << 12 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_GPNVM6 ( 0x1 << 14 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_GPNVM7 ( 0x1 << 15 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS0 ( 0x1 << 16 ) /* (MC) Sector 0 Lock Status */
-#define AT91C_MC_LOCKS1 ( 0x1 << 17 ) /* (MC) Sector 1 Lock Status */
-#define AT91C_MC_LOCKS2 ( 0x1 << 18 ) /* (MC) Sector 2 Lock Status */
-#define AT91C_MC_LOCKS3 ( 0x1 << 19 ) /* (MC) Sector 3 Lock Status */
-#define AT91C_MC_LOCKS4 ( 0x1 << 20 ) /* (MC) Sector 4 Lock Status */
-#define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */
-#define AT91C_MC_LOCKS6 ( 0x1 << 22 ) /* (MC) Sector 6 Lock Status */
-#define AT91C_MC_LOCKS7 ( 0x1 << 23 ) /* (MC) Sector 7 Lock Status */
-#define AT91C_MC_LOCKS8 ( 0x1 << 24 ) /* (MC) Sector 8 Lock Status */
-#define AT91C_MC_LOCKS9 ( 0x1 << 25 ) /* (MC) Sector 9 Lock Status */
-#define AT91C_MC_LOCKS10 ( 0x1 << 26 ) /* (MC) Sector 10 Lock Status */
-#define AT91C_MC_LOCKS11 ( 0x1 << 27 ) /* (MC) Sector 11 Lock Status */
-#define AT91C_MC_LOCKS12 ( 0x1 << 28 ) /* (MC) Sector 12 Lock Status */
-#define AT91C_MC_LOCKS13 ( 0x1 << 29 ) /* (MC) Sector 13 Lock Status */
-#define AT91C_MC_LOCKS14 ( 0x1 << 30 ) /* (MC) Sector 14 Lock Status */
-#define AT91C_MC_LOCKS15 ( 0x1 << 31 ) /* (MC) Sector 15 Lock Status */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_MC structure ***
+#define MC_RCR ( 0) // MC Remap Control Register
+#define MC_ASR ( 4) // MC Abort Status Register
+#define MC_AASR ( 8) // MC Abort Address Status Register
+#define MC_FMR (96) // MC Flash Mode Register
+#define MC_FCR (100) // MC Flash Command Register
+#define MC_FSR (104) // MC Flash Status Register
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_SPI structure *** */
-#define SPI_CR ( 0 ) /* Control Register */
-#define SPI_MR ( 4 ) /* Mode Register */
-#define SPI_RDR ( 8 ) /* Receive Data Register */
-#define SPI_TDR ( 12 ) /* Transmit Data Register */
-#define SPI_SR ( 16 ) /* Status Register */
-#define SPI_IER ( 20 ) /* Interrupt Enable Register */
-#define SPI_IDR ( 24 ) /* Interrupt Disable Register */
-#define SPI_IMR ( 28 ) /* Interrupt Mask Register */
-#define SPI_CSR ( 48 ) /* Chip Select Register */
-#define SPI_RPR ( 256 ) /* Receive Pointer Register */
-#define SPI_RCR ( 260 ) /* Receive Counter Register */
-#define SPI_TPR ( 264 ) /* Transmit Pointer Register */
-#define SPI_TCR ( 268 ) /* Transmit Counter Register */
-#define SPI_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define SPI_RNCR ( 276 ) /* Receive Next Counter Register */
-#define SPI_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define SPI_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define SPI_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define SPI_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN ( 0x1 << 0 ) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS ( 0x1 << 1 ) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST ( 0x1 << 7 ) /* (SPI) SPI Software reset */
-#define AT91C_SPI_LASTXFER ( 0x1 << 24 ) /* (SPI) SPI Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR ( 0x1 << 0 ) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS ( 0x1 << 1 ) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED ( 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE ( 0x1 << 1 ) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC ( 0x1 << 2 ) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_FDIV ( 0x1 << 3 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS ( 0x1 << 4 ) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB ( 0x1 << 7 ) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS ( 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD ( 0xFFFF << 0 ) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD ( 0xFFFF << 0 ) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF ( 0x1 << 0 ) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE ( 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF ( 0x1 << 2 ) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES ( 0x1 << 3 ) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_ENDRX ( 0x1 << 4 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF ( 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE ( 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_NSSR ( 0x1 << 8 ) /* (SPI) NSSR Interrupt */
-#define AT91C_SPI_TXEMPTY ( 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */
-#define AT91C_SPI_SPIENS ( 0x1 << 16 ) /* (SPI) Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL ( 0x1 << 0 ) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA ( 0x1 << 1 ) /* (SPI) Clock Phase */
-#define AT91C_SPI_CSAAT ( 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */
-#define AT91C_SPI_BITS ( 0xF << 4 ) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8 ( 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9 ( 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10 ( 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11 ( 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12 ( 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13 ( 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14 ( 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15 ( 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16 ( 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR ( 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS ( 0xFF << 16 ) /* (SPI) Delay Before SPCK */
-#define AT91C_SPI_DLYBCT ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SPI structure ***
+#define SPI_CR ( 0) // Control Register
+#define SPI_MR ( 4) // Mode Register
+#define SPI_RDR ( 8) // Receive Data Register
+#define SPI_TDR (12) // Transmit Data Register
+#define SPI_SR (16) // Status Register
+#define SPI_IER (20) // Interrupt Enable Register
+#define SPI_IDR (24) // Interrupt Disable Register
+#define SPI_IMR (28) // Interrupt Mask Register
+#define SPI_CSR (48) // Chip Select Register
+#define SPI_RPR (256) // Receive Pointer Register
+#define SPI_RCR (260) // Receive Counter Register
+#define SPI_TPR (264) // Transmit Pointer Register
+#define SPI_TCR (268) // Transmit Counter Register
+#define SPI_RNPR (272) // Receive Next Pointer Register
+#define SPI_RNCR (276) // Receive Next Counter Register
+#define SPI_TNPR (280) // Transmit Next Pointer Register
+#define SPI_TNCR (284) // Transmit Next Counter Register
+#define SPI_PTCR (288) // PDC Transfer Control Register
+#define SPI_PTSR (292) // PDC Transfer Status Register
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Usart */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_USART structure *** */
-#define US_CR ( 0 ) /* Control Register */
-#define US_MR ( 4 ) /* Mode Register */
-#define US_IER ( 8 ) /* Interrupt Enable Register */
-#define US_IDR ( 12 ) /* Interrupt Disable Register */
-#define US_IMR ( 16 ) /* Interrupt Mask Register */
-#define US_CSR ( 20 ) /* Channel Status Register */
-#define US_RHR ( 24 ) /* Receiver Holding Register */
-#define US_THR ( 28 ) /* Transmitter Holding Register */
-#define US_BRGR ( 32 ) /* Baud Rate Generator Register */
-#define US_RTOR ( 36 ) /* Receiver Time-out Register */
-#define US_TTGR ( 40 ) /* Transmitter Time-guard Register */
-#define US_FIDI ( 64 ) /* FI_DI_Ratio Register */
-#define US_NER ( 68 ) /* Nb Errors Register */
-#define US_IF ( 76 ) /* IRDA_FILTER Register */
-#define US_RPR ( 256 ) /* Receive Pointer Register */
-#define US_RCR ( 260 ) /* Receive Counter Register */
-#define US_TPR ( 264 ) /* Transmit Pointer Register */
-#define US_TCR ( 268 ) /* Transmit Counter Register */
-#define US_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define US_RNCR ( 276 ) /* Receive Next Counter Register */
-#define US_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define US_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define US_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define US_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_STTBRK ( 0x1 << 9 ) /* (USART) Start Break */
-#define AT91C_US_STPBRK ( 0x1 << 10 ) /* (USART) Stop Break */
-#define AT91C_US_STTTO ( 0x1 << 11 ) /* (USART) Start Time-out */
-#define AT91C_US_SENDA ( 0x1 << 12 ) /* (USART) Send Address */
-#define AT91C_US_RSTIT ( 0x1 << 13 ) /* (USART) Reset Iterations */
-#define AT91C_US_RSTNACK ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
-#define AT91C_US_RETTO ( 0x1 << 15 ) /* (USART) Rearm Time-out */
-#define AT91C_US_DTREN ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
-#define AT91C_US_DTRDIS ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
-#define AT91C_US_RTSEN ( 0x1 << 18 ) /* (USART) Request to Send enable */
-#define AT91C_US_RTSDIS ( 0x1 << 19 ) /* (USART) Request to Send Disable */
-/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
-#define AT91C_US_USMODE ( 0xF << 0 ) /* (USART) Usart mode */
-#define AT91C_US_USMODE_NORMAL ( 0x0 ) /* (USART) Normal */
-#define AT91C_US_USMODE_RS485 ( 0x1 ) /* (USART) RS485 */
-#define AT91C_US_USMODE_HWHSH ( 0x2 ) /* (USART) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM ( 0x3 ) /* (USART) Modem */
-#define AT91C_US_USMODE_ISO7816_0 ( 0x4 ) /* (USART) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1 ( 0x6 ) /* (USART) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA ( 0x8 ) /* (USART) IrDA */
-#define AT91C_US_USMODE_SWHSH ( 0xC ) /* (USART) Software Handshaking */
-#define AT91C_US_CLKS ( 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CLKS_CLOCK ( 0x0 << 4 ) /* (USART) Clock */
-#define AT91C_US_CLKS_FDIV1 ( 0x1 << 4 ) /* (USART) fdiv1 */
-#define AT91C_US_CLKS_SLOW ( 0x2 << 4 ) /* (USART) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT ( 0x3 << 4 ) /* (USART) External (SCK) */
-#define AT91C_US_CHRL ( 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
-#define AT91C_US_CHRL_5_BITS ( 0x0 << 6 ) /* (USART) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS ( 0x1 << 6 ) /* (USART) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS ( 0x2 << 6 ) /* (USART) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS ( 0x3 << 6 ) /* (USART) Character Length: 8 bits */
-#define AT91C_US_SYNC ( 0x1 << 8 ) /* (USART) Synchronous Mode Select */
-#define AT91C_US_NBSTOP ( 0x3 << 12 ) /* (USART) Number of Stop bits */
-#define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12 ) /* (USART) 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12 ) /* (USART) 2 stop bits */
-#define AT91C_US_MSBF ( 0x1 << 16 ) /* (USART) Bit Order */
-#define AT91C_US_MODE9 ( 0x1 << 17 ) /* (USART) 9-bit Character length */
-#define AT91C_US_CKLO ( 0x1 << 18 ) /* (USART) Clock Output Select */
-#define AT91C_US_OVER ( 0x1 << 19 ) /* (USART) Over Sampling Mode */
-#define AT91C_US_INACK ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
-#define AT91C_US_DSNACK ( 0x1 << 21 ) /* (USART) Disable Successive NACK */
-#define AT91C_US_MAX_ITER ( 0x1 << 24 ) /* (USART) Number of Repetitions */
-#define AT91C_US_FILTER ( 0x1 << 28 ) /* (USART) Receive Line Filter */
-/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXBRK ( 0x1 << 2 ) /* (USART) Break Received/End of Break */
-#define AT91C_US_TIMEOUT ( 0x1 << 8 ) /* (USART) Receiver Time-out */
-#define AT91C_US_ITERATION ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
-#define AT91C_US_NACK ( 0x1 << 13 ) /* (USART) Non Acknowledge */
-#define AT91C_US_RIIC ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
-#define AT91C_US_DSRIC ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
-#define AT91C_US_DCDIC ( 0x1 << 18 ) /* (USART) Data Carrier Flag */
-#define AT91C_US_CTSIC ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
-/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
-/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
-/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
-#define AT91C_US_RI ( 0x1 << 20 ) /* (USART) Image of RI Input */
-#define AT91C_US_DSR ( 0x1 << 21 ) /* (USART) Image of DSR Input */
-#define AT91C_US_DCD ( 0x1 << 22 ) /* (USART) Image of DCD Input */
-#define AT91C_US_CTS ( 0x1 << 23 ) /* (USART) Image of CTS Input */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+// *** Register offset in AT91S_USART structure ***
+#define US_CR ( 0) // Control Register
+#define US_MR ( 4) // Mode Register
+#define US_IER ( 8) // Interrupt Enable Register
+#define US_IDR (12) // Interrupt Disable Register
+#define US_IMR (16) // Interrupt Mask Register
+#define US_CSR (20) // Channel Status Register
+#define US_RHR (24) // Receiver Holding Register
+#define US_THR (28) // Transmitter Holding Register
+#define US_BRGR (32) // Baud Rate Generator Register
+#define US_RTOR (36) // Receiver Time-out Register
+#define US_TTGR (40) // Transmitter Time-guard Register
+#define US_FIDI (64) // FI_DI_Ratio Register
+#define US_NER (68) // Nb Errors Register
+#define US_IF (76) // IRDA_FILTER Register
+#define US_RPR (256) // Receive Pointer Register
+#define US_RCR (260) // Receive Counter Register
+#define US_TPR (264) // Transmit Pointer Register
+#define US_TCR (268) // Transmit Counter Register
+#define US_RNPR (272) // Receive Next Pointer Register
+#define US_RNCR (276) // Receive Next Counter Register
+#define US_TNPR (280) // Transmit Next Pointer Register
+#define US_TNCR (284) // Transmit Next Counter Register
+#define US_PTCR (288) // PDC Transfer Control Register
+#define US_PTSR (292) // PDC Transfer Status Register
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_SSC structure *** */
-#define SSC_CR ( 0 ) /* Control Register */
-#define SSC_CMR ( 4 ) /* Clock Mode Register */
-#define SSC_RCMR ( 16 ) /* Receive Clock ModeRegister */
-#define SSC_RFMR ( 20 ) /* Receive Frame Mode Register */
-#define SSC_TCMR ( 24 ) /* Transmit Clock Mode Register */
-#define SSC_TFMR ( 28 ) /* Transmit Frame Mode Register */
-#define SSC_RHR ( 32 ) /* Receive Holding Register */
-#define SSC_THR ( 36 ) /* Transmit Holding Register */
-#define SSC_RSHR ( 48 ) /* Receive Sync Holding Register */
-#define SSC_TSHR ( 52 ) /* Transmit Sync Holding Register */
-#define SSC_SR ( 64 ) /* Status Register */
-#define SSC_IER ( 68 ) /* Interrupt Enable Register */
-#define SSC_IDR ( 72 ) /* Interrupt Disable Register */
-#define SSC_IMR ( 76 ) /* Interrupt Mask Register */
-#define SSC_RPR ( 256 ) /* Receive Pointer Register */
-#define SSC_RCR ( 260 ) /* Receive Counter Register */
-#define SSC_TPR ( 264 ) /* Transmit Pointer Register */
-#define SSC_TCR ( 268 ) /* Transmit Counter Register */
-#define SSC_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define SSC_RNCR ( 276 ) /* Receive Next Counter Register */
-#define SSC_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define SSC_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define SSC_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define SSC_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
-#define AT91C_SSC_RXEN ( 0x1 << 0 ) /* (SSC) Receive Enable */
-#define AT91C_SSC_RXDIS ( 0x1 << 1 ) /* (SSC) Receive Disable */
-#define AT91C_SSC_TXEN ( 0x1 << 8 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_TXDIS ( 0x1 << 9 ) /* (SSC) Transmit Disable */
-#define AT91C_SSC_SWRST ( 0x1 << 15 ) /* (SSC) Software Reset */
-/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
-#define AT91C_SSC_CKS ( 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */
-#define AT91C_SSC_CKS_DIV ( 0x0 ) /* (SSC) Divided Clock */
-#define AT91C_SSC_CKS_TK ( 0x1 ) /* (SSC) TK Clock signal */
-#define AT91C_SSC_CKS_RK ( 0x2 ) /* (SSC) RK pin */
-#define AT91C_SSC_CKO ( 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */
-#define AT91C_SSC_CKO_NONE ( 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
-#define AT91C_SSC_CKO_CONTINOUS ( 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
-#define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
-#define AT91C_SSC_CKI ( 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */
-#define AT91C_SSC_START ( 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */
-#define AT91C_SSC_START_CONTINOUS ( 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
-#define AT91C_SSC_START_TX ( 0x1 << 8 ) /* (SSC) Transmit/Receive start */
-#define AT91C_SSC_START_LOW_RF ( 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */
-#define AT91C_SSC_START_HIGH_RF ( 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */
-#define AT91C_SSC_START_FALL_RF ( 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */
-#define AT91C_SSC_START_RISE_RF ( 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */
-#define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */
-#define AT91C_SSC_START_EDGE_RF ( 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */
-#define AT91C_SSC_START_0 ( 0x8 << 8 ) /* (SSC) Compare 0 */
-#define AT91C_SSC_STTDLY ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
-#define AT91C_SSC_PERIOD ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
-/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
-#define AT91C_SSC_DATLEN ( 0x1F << 0 ) /* (SSC) Data Length */
-#define AT91C_SSC_LOOP ( 0x1 << 5 ) /* (SSC) Loop Mode */
-#define AT91C_SSC_MSBF ( 0x1 << 7 ) /* (SSC) Most Significant Bit First */
-#define AT91C_SSC_DATNB ( 0xF << 8 ) /* (SSC) Data Number per Frame */
-#define AT91C_SSC_FSLEN ( 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */
-#define AT91C_SSC_FSOS ( 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */
-#define AT91C_SSC_FSOS_NONE ( 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
-#define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
-#define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
-#define AT91C_SSC_FSOS_LOW ( 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
-#define AT91C_SSC_FSOS_HIGH ( 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
-#define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
-#define AT91C_SSC_FSEDGE ( 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */
-/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
-/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
-#define AT91C_SSC_DATDEF ( 0x1 << 5 ) /* (SSC) Data Default Value */
-#define AT91C_SSC_FSDEN ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
-/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
-#define AT91C_SSC_TXRDY ( 0x1 << 0 ) /* (SSC) Transmit Ready */
-#define AT91C_SSC_TXEMPTY ( 0x1 << 1 ) /* (SSC) Transmit Empty */
-#define AT91C_SSC_ENDTX ( 0x1 << 2 ) /* (SSC) End Of Transmission */
-#define AT91C_SSC_TXBUFE ( 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */
-#define AT91C_SSC_RXRDY ( 0x1 << 4 ) /* (SSC) Receive Ready */
-#define AT91C_SSC_OVRUN ( 0x1 << 5 ) /* (SSC) Receive Overrun */
-#define AT91C_SSC_ENDRX ( 0x1 << 6 ) /* (SSC) End of Reception */
-#define AT91C_SSC_RXBUFF ( 0x1 << 7 ) /* (SSC) Receive Buffer Full */
-#define AT91C_SSC_TXSYN ( 0x1 << 10 ) /* (SSC) Transmit Sync */
-#define AT91C_SSC_RXSYN ( 0x1 << 11 ) /* (SSC) Receive Sync */
-#define AT91C_SSC_TXENA ( 0x1 << 16 ) /* (SSC) Transmit Enable */
-#define AT91C_SSC_RXENA ( 0x1 << 17 ) /* (SSC) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
-/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
-/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SSC structure ***
+#define SSC_CR ( 0) // Control Register
+#define SSC_CMR ( 4) // Clock Mode Register
+#define SSC_RCMR (16) // Receive Clock ModeRegister
+#define SSC_RFMR (20) // Receive Frame Mode Register
+#define SSC_TCMR (24) // Transmit Clock Mode Register
+#define SSC_TFMR (28) // Transmit Frame Mode Register
+#define SSC_RHR (32) // Receive Holding Register
+#define SSC_THR (36) // Transmit Holding Register
+#define SSC_RSHR (48) // Receive Sync Holding Register
+#define SSC_TSHR (52) // Transmit Sync Holding Register
+#define SSC_SR (64) // Status Register
+#define SSC_IER (68) // Interrupt Enable Register
+#define SSC_IDR (72) // Interrupt Disable Register
+#define SSC_IMR (76) // Interrupt Mask Register
+#define SSC_RPR (256) // Receive Pointer Register
+#define SSC_RCR (260) // Receive Counter Register
+#define SSC_TPR (264) // Transmit Pointer Register
+#define SSC_TCR (268) // Transmit Counter Register
+#define SSC_RNPR (272) // Receive Next Pointer Register
+#define SSC_RNCR (276) // Receive Next Counter Register
+#define SSC_TNPR (280) // Transmit Next Pointer Register
+#define SSC_TNCR (284) // Transmit Next Counter Register
+#define SSC_PTCR (288) // PDC Transfer Control Register
+#define SSC_PTSR (292) // PDC Transfer Status Register
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TWI structure *** */
-#define TWI_CR ( 0 ) /* Control Register */
-#define TWI_MMR ( 4 ) /* Master Mode Register */
-#define TWI_IADR ( 12 ) /* Internal Address Register */
-#define TWI_CWGR ( 16 ) /* Clock Waveform Generator Register */
-#define TWI_SR ( 32 ) /* Status Register */
-#define TWI_IER ( 36 ) /* Interrupt Enable Register */
-#define TWI_IDR ( 40 ) /* Interrupt Disable Register */
-#define TWI_IMR ( 44 ) /* Interrupt Mask Register */
-#define TWI_RHR ( 48 ) /* Receive Holding Register */
-#define TWI_THR ( 52 ) /* Transmit Holding Register */
-/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
-#define AT91C_TWI_START ( 0x1 << 0 ) /* (TWI) Send a START Condition */
-#define AT91C_TWI_STOP ( 0x1 << 1 ) /* (TWI) Send a STOP Condition */
-#define AT91C_TWI_MSEN ( 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */
-#define AT91C_TWI_MSDIS ( 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */
-#define AT91C_TWI_SWRST ( 0x1 << 7 ) /* (TWI) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
-#define AT91C_TWI_IADRSZ ( 0x3 << 8 ) /* (TWI) Internal Device Address Size */
-#define AT91C_TWI_IADRSZ_NO ( 0x0 << 8 ) /* (TWI) No internal device address */
-#define AT91C_TWI_IADRSZ_1_BYTE ( 0x1 << 8 ) /* (TWI) One-byte internal device address */
-#define AT91C_TWI_IADRSZ_2_BYTE ( 0x2 << 8 ) /* (TWI) Two-byte internal device address */
-#define AT91C_TWI_IADRSZ_3_BYTE ( 0x3 << 8 ) /* (TWI) Three-byte internal device address */
-#define AT91C_TWI_MREAD ( 0x1 << 12 ) /* (TWI) Master Read Direction */
-#define AT91C_TWI_DADR ( 0x7F << 16 ) /* (TWI) Device Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
-#define AT91C_TWI_CLDIV ( 0xFF << 0 ) /* (TWI) Clock Low Divider */
-#define AT91C_TWI_CHDIV ( 0xFF << 8 ) /* (TWI) Clock High Divider */
-#define AT91C_TWI_CKDIV ( 0x7 << 16 ) /* (TWI) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
-#define AT91C_TWI_TXCOMP ( 0x1 << 0 ) /* (TWI) Transmission Completed */
-#define AT91C_TWI_RXRDY ( 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */
-#define AT91C_TWI_TXRDY ( 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */
-#define AT91C_TWI_OVRE ( 0x1 << 6 ) /* (TWI) Overrun Error */
-#define AT91C_TWI_UNRE ( 0x1 << 7 ) /* (TWI) Underrun Error */
-#define AT91C_TWI_NACK ( 0x1 << 8 ) /* (TWI) Not Acknowledged */
-/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
-/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TWI structure ***
+#define TWI_CR ( 0) // Control Register
+#define TWI_MMR ( 4) // Master Mode Register
+#define TWI_IADR (12) // Internal Address Register
+#define TWI_CWGR (16) // Clock Waveform Generator Register
+#define TWI_SR (32) // Status Register
+#define TWI_IER (36) // Interrupt Enable Register
+#define TWI_IDR (40) // Interrupt Disable Register
+#define TWI_IMR (44) // Interrupt Mask Register
+#define TWI_RHR (48) // Receive Holding Register
+#define TWI_THR (52) // Transmit Holding Register
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PWMC_CH structure *** */
-#define PWMC_CMR ( 0 ) /* Channel Mode Register */
-#define PWMC_CDTYR ( 4 ) /* Channel Duty Cycle Register */
-#define PWMC_CPRDR ( 8 ) /* Channel Period Register */
-#define PWMC_CCNTR ( 12 ) /* Channel Counter Register */
-#define PWMC_CUPDR ( 16 ) /* Channel Update Register */
-#define PWMC_Reserved ( 20 ) /* Reserved */
-/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
-#define AT91C_PWMC_CPRE ( 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
-#define AT91C_PWMC_CPRE_MCK ( 0x0 ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKA ( 0xB ) /* (PWMC_CH) */
-#define AT91C_PWMC_CPRE_MCKB ( 0xC ) /* (PWMC_CH) */
-#define AT91C_PWMC_CALG ( 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */
-#define AT91C_PWMC_CPOL ( 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */
-#define AT91C_PWMC_CPD ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
-/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
-#define AT91C_PWMC_CDTY ( 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */
-/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
-#define AT91C_PWMC_CPRD ( 0x0 << 0 ) /* (PWMC_CH) Channel Period */
-/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
-#define AT91C_PWMC_CCNT ( 0x0 << 0 ) /* (PWMC_CH) Channel Counter */
-/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
-#define AT91C_PWMC_CUPD ( 0x0 << 0 ) /* (PWMC_CH) Channel Update */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC_CH structure ***
+#define PWMC_CMR ( 0) // Channel Mode Register
+#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register
+#define PWMC_CPRDR ( 8) // Channel Period Register
+#define PWMC_CCNTR (12) // Channel Counter Register
+#define PWMC_CUPDR (16) // Channel Update Register
+#define PWMC_Reserved (20) // Reserved
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_PWMC structure *** */
-#define PWMC_MR ( 0 ) /* PWMC Mode Register */
-#define PWMC_ENA ( 4 ) /* PWMC Enable Register */
-#define PWMC_DIS ( 8 ) /* PWMC Disable Register */
-#define PWMC_SR ( 12 ) /* PWMC Status Register */
-#define PWMC_IER ( 16 ) /* PWMC Interrupt Enable Register */
-#define PWMC_IDR ( 20 ) /* PWMC Interrupt Disable Register */
-#define PWMC_IMR ( 24 ) /* PWMC Interrupt Mask Register */
-#define PWMC_ISR ( 28 ) /* PWMC Interrupt Status Register */
-#define PWMC_VR ( 252 ) /* PWMC Version Register */
-#define PWMC_CH ( 512 ) /* PWMC Channel */
-/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
-#define AT91C_PWMC_DIVA ( 0xFF << 0 ) /* (PWMC) CLKA divide factor. */
-#define AT91C_PWMC_PREA ( 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */
-#define AT91C_PWMC_PREA_MCK ( 0x0 << 8 ) /* (PWMC) */
-#define AT91C_PWMC_DIVB ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
-#define AT91C_PWMC_PREB ( 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */
-#define AT91C_PWMC_PREB_MCK ( 0x0 << 24 ) /* (PWMC) */
-/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
-#define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */
-#define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */
-#define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */
-#define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */
-/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
-/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
-/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
-/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
-/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
-/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC structure ***
+#define PWMC_MR ( 0) // PWMC Mode Register
+#define PWMC_ENA ( 4) // PWMC Enable Register
+#define PWMC_DIS ( 8) // PWMC Disable Register
+#define PWMC_SR (12) // PWMC Status Register
+#define PWMC_IER (16) // PWMC Interrupt Enable Register
+#define PWMC_IDR (20) // PWMC Interrupt Disable Register
+#define PWMC_IMR (24) // PWMC Interrupt Mask Register
+#define PWMC_ISR (28) // PWMC Interrupt Status Register
+#define PWMC_VR (252) // PWMC Version Register
+#define PWMC_CH (512) // PWMC Channel
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR USB Device Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_UDP structure *** */
-#define UDP_NUM ( 0 ) /* Frame Number Register */
-#define UDP_GLBSTATE ( 4 ) /* Global State Register */
-#define UDP_FADDR ( 8 ) /* Function Address Register */
-#define UDP_IER ( 16 ) /* Interrupt Enable Register */
-#define UDP_IDR ( 20 ) /* Interrupt Disable Register */
-#define UDP_IMR ( 24 ) /* Interrupt Mask Register */
-#define UDP_ISR ( 28 ) /* Interrupt Status Register */
-#define UDP_ICR ( 32 ) /* Interrupt Clear Register */
-#define UDP_RSTEP ( 40 ) /* Reset Endpoint Register */
-#define UDP_CSR ( 48 ) /* Endpoint Control and Status Register */
-#define UDP_FDR ( 80 ) /* Endpoint FIFO Data Register */
-#define UDP_TXVC ( 116 ) /* Transceiver Control Register */
-/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
-#define AT91C_UDP_FRM_NUM ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
-#define AT91C_UDP_FRM_ERR ( 0x1 << 16 ) /* (UDP) Frame Error */
-#define AT91C_UDP_FRM_OK ( 0x1 << 17 ) /* (UDP) Frame OK */
-/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
-#define AT91C_UDP_FADDEN ( 0x1 << 0 ) /* (UDP) Function Address Enable */
-#define AT91C_UDP_CONFG ( 0x1 << 1 ) /* (UDP) Configured */
-#define AT91C_UDP_ESR ( 0x1 << 2 ) /* (UDP) Enable Send Resume */
-#define AT91C_UDP_RSMINPR ( 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */
-#define AT91C_UDP_RMWUPE ( 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */
-/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
-#define AT91C_UDP_FADD ( 0xFF << 0 ) /* (UDP) Function Address Value */
-#define AT91C_UDP_FEN ( 0x1 << 8 ) /* (UDP) Function Enable */
-/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
-#define AT91C_UDP_EPINT0 ( 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT1 ( 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */
-#define AT91C_UDP_EPINT2 ( 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
-#define AT91C_UDP_EPINT3 ( 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */
-#define AT91C_UDP_EPINT4 ( 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */
-#define AT91C_UDP_EPINT5 ( 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */
-#define AT91C_UDP_RXSUSP ( 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */
-#define AT91C_UDP_RXRSM ( 0x1 << 9 ) /* (UDP) USB Resume Interrupt */
-#define AT91C_UDP_EXTRSM ( 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */
-#define AT91C_UDP_SOFINT ( 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */
-#define AT91C_UDP_WAKEUP ( 0x1 << 13 ) /* (UDP) USB Resume Interrupt */
-/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
-/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
-/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
-#define AT91C_UDP_ENDBUSRES ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
-/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
-/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
-#define AT91C_UDP_EP0 ( 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */
-#define AT91C_UDP_EP1 ( 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */
-#define AT91C_UDP_EP2 ( 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */
-#define AT91C_UDP_EP3 ( 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */
-#define AT91C_UDP_EP4 ( 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */
-#define AT91C_UDP_EP5 ( 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */
-/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
-#define AT91C_UDP_TXCOMP ( 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */
-#define AT91C_UDP_RX_DATA_BK0 ( 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */
-#define AT91C_UDP_RXSETUP ( 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */
-#define AT91C_UDP_ISOERROR ( 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */
-#define AT91C_UDP_TXPKTRDY ( 0x1 << 4 ) /* (UDP) Transmit Packet Ready */
-#define AT91C_UDP_FORCESTALL ( 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
-#define AT91C_UDP_RX_DATA_BK1 ( 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
-#define AT91C_UDP_DIR ( 0x1 << 7 ) /* (UDP) Transfer Direction */
-#define AT91C_UDP_EPTYPE ( 0x7 << 8 ) /* (UDP) Endpoint type */
-#define AT91C_UDP_EPTYPE_CTRL ( 0x0 << 8 ) /* (UDP) Control */
-#define AT91C_UDP_EPTYPE_ISO_OUT ( 0x1 << 8 ) /* (UDP) Isochronous OUT */
-#define AT91C_UDP_EPTYPE_BULK_OUT ( 0x2 << 8 ) /* (UDP) Bulk OUT */
-#define AT91C_UDP_EPTYPE_INT_OUT ( 0x3 << 8 ) /* (UDP) Interrupt OUT */
-#define AT91C_UDP_EPTYPE_ISO_IN ( 0x5 << 8 ) /* (UDP) Isochronous IN */
-#define AT91C_UDP_EPTYPE_BULK_IN ( 0x6 << 8 ) /* (UDP) Bulk IN */
-#define AT91C_UDP_EPTYPE_INT_IN ( 0x7 << 8 ) /* (UDP) Interrupt IN */
-#define AT91C_UDP_DTGLE ( 0x1 << 11 ) /* (UDP) Data Toggle */
-#define AT91C_UDP_EPEDS ( 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */
-#define AT91C_UDP_RXBYTECNT ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
-/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
-#define AT91C_UDP_TXVDIS ( 0x1 << 8 ) /* (UDP) */
-#define AT91C_UDP_PUON ( 0x1 << 9 ) /* (UDP) Pull-up ON */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+// *** Register offset in AT91S_UDP structure ***
+#define UDP_NUM ( 0) // Frame Number Register
+#define UDP_GLBSTATE ( 4) // Global State Register
+#define UDP_FADDR ( 8) // Function Address Register
+#define UDP_IER (16) // Interrupt Enable Register
+#define UDP_IDR (20) // Interrupt Disable Register
+#define UDP_IMR (24) // Interrupt Mask Register
+#define UDP_ISR (28) // Interrupt Status Register
+#define UDP_ICR (32) // Interrupt Clear Register
+#define UDP_RSTEP (40) // Reset Endpoint Register
+#define UDP_CSR (48) // Endpoint Control and Status Register
+#define UDP_FDR (80) // Endpoint FIFO Data Register
+#define UDP_TXVC (116) // Transceiver Control Register
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TC structure *** */
-#define TC_CCR ( 0 ) /* Channel Control Register */
-#define TC_CMR ( 4 ) /* Channel Mode Register (Capture Mode / Waveform Mode) */
-#define TC_CV ( 16 ) /* Counter Value */
-#define TC_RA ( 20 ) /* Register A */
-#define TC_RB ( 24 ) /* Register B */
-#define TC_RC ( 28 ) /* Register C */
-#define TC_SR ( 32 ) /* Status Register */
-#define TC_IER ( 36 ) /* Interrupt Enable Register */
-#define TC_IDR ( 40 ) /* Interrupt Disable Register */
-#define TC_IMR ( 44 ) /* Interrupt Mask Register */
-/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
-#define AT91C_TC_CLKEN ( 0x1 << 0 ) /* (TC) Counter Clock Enable Command */
-#define AT91C_TC_CLKDIS ( 0x1 << 1 ) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ( 0x1 << 2 ) /* (TC) Software Trigger Command */
-/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
-#define AT91C_TC_CLKS ( 0x7 << 0 ) /* (TC) Clock Selection */
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */
-#define AT91C_TC_CLKS_XC0 ( 0x5 ) /* (TC) Clock selected: XC0 */
-#define AT91C_TC_CLKS_XC1 ( 0x6 ) /* (TC) Clock selected: XC1 */
-#define AT91C_TC_CLKS_XC2 ( 0x7 ) /* (TC) Clock selected: XC2 */
-#define AT91C_TC_CLKI ( 0x1 << 3 ) /* (TC) Clock Invert */
-#define AT91C_TC_BURST ( 0x3 << 4 ) /* (TC) Burst Signal Selection */
-#define AT91C_TC_BURST_NONE ( 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */
-#define AT91C_TC_BURST_XC0 ( 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC1 ( 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */
-#define AT91C_TC_BURST_XC2 ( 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */
-#define AT91C_TC_CPCSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */
-#define AT91C_TC_LDBSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */
-#define AT91C_TC_CPCDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */
-#define AT91C_TC_LDBDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */
-#define AT91C_TC_ETRGEDG ( 0x3 << 8 ) /* (TC) External Trigger Edge Selection */
-#define AT91C_TC_ETRGEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_ETRGEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_ETRGEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_ETRGEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVTEDG ( 0x3 << 8 ) /* (TC) External Event Edge Selection */
-#define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */
-#define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */
-#define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */
-#define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */
-#define AT91C_TC_EEVT ( 0x3 << 10 ) /* (TC) External Event Selection */
-#define AT91C_TC_EEVT_TIOB ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
-#define AT91C_TC_EEVT_XC0 ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
-#define AT91C_TC_EEVT_XC1 ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
-#define AT91C_TC_EEVT_XC2 ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
-#define AT91C_TC_ABETRG ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
-#define AT91C_TC_ENETRG ( 0x1 << 12 ) /* (TC) External Event Trigger enable */
-#define AT91C_TC_WAVESEL ( 0x3 << 13 ) /* (TC) Waveform Selection */
-#define AT91C_TC_WAVESEL_UP ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UP_AUTO ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
-#define AT91C_TC_CPCTRG ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
-#define AT91C_TC_WAVE ( 0x1 << 15 ) /* (TC) */
-#define AT91C_TC_ACPA ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
-#define AT91C_TC_ACPA_NONE ( 0x0 << 16 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPA_SET ( 0x1 << 16 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPA_CLEAR ( 0x2 << 16 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRA ( 0x3 << 16 ) /* (TC) RA Loading Selection */
-#define AT91C_TC_LDRA_NONE ( 0x0 << 16 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRA_RISING ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRA_FALLING ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRA_BOTH ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_ACPC ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
-#define AT91C_TC_ACPC_NONE ( 0x0 << 18 ) /* (TC) Effect: none */
-#define AT91C_TC_ACPC_SET ( 0x1 << 18 ) /* (TC) Effect: set */
-#define AT91C_TC_ACPC_CLEAR ( 0x2 << 18 ) /* (TC) Effect: clear */
-#define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18 ) /* (TC) Effect: toggle */
-#define AT91C_TC_LDRB ( 0x3 << 18 ) /* (TC) RB Loading Selection */
-#define AT91C_TC_LDRB_NONE ( 0x0 << 18 ) /* (TC) Edge: None */
-#define AT91C_TC_LDRB_RISING ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
-#define AT91C_TC_LDRB_FALLING ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
-#define AT91C_TC_LDRB_BOTH ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
-#define AT91C_TC_AEEVT ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
-#define AT91C_TC_AEEVT_NONE ( 0x0 << 20 ) /* (TC) Effect: none */
-#define AT91C_TC_AEEVT_SET ( 0x1 << 20 ) /* (TC) Effect: set */
-#define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20 ) /* (TC) Effect: clear */
-#define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20 ) /* (TC) Effect: toggle */
-#define AT91C_TC_ASWTRG ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
-#define AT91C_TC_ASWTRG_NONE ( 0x0 << 22 ) /* (TC) Effect: none */
-#define AT91C_TC_ASWTRG_SET ( 0x1 << 22 ) /* (TC) Effect: set */
-#define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22 ) /* (TC) Effect: clear */
-#define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPB ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
-#define AT91C_TC_BCPB_NONE ( 0x0 << 24 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPB_SET ( 0x1 << 24 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPB_CLEAR ( 0x2 << 24 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BCPC ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
-#define AT91C_TC_BCPC_NONE ( 0x0 << 26 ) /* (TC) Effect: none */
-#define AT91C_TC_BCPC_SET ( 0x1 << 26 ) /* (TC) Effect: set */
-#define AT91C_TC_BCPC_CLEAR ( 0x2 << 26 ) /* (TC) Effect: clear */
-#define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BEEVT ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
-#define AT91C_TC_BEEVT_NONE ( 0x0 << 28 ) /* (TC) Effect: none */
-#define AT91C_TC_BEEVT_SET ( 0x1 << 28 ) /* (TC) Effect: set */
-#define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28 ) /* (TC) Effect: clear */
-#define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28 ) /* (TC) Effect: toggle */
-#define AT91C_TC_BSWTRG ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
-#define AT91C_TC_BSWTRG_NONE ( 0x0 << 30 ) /* (TC) Effect: none */
-#define AT91C_TC_BSWTRG_SET ( 0x1 << 30 ) /* (TC) Effect: set */
-#define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30 ) /* (TC) Effect: clear */
-#define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30 ) /* (TC) Effect: toggle */
-/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
-#define AT91C_TC_COVFS ( 0x1 << 0 ) /* (TC) Counter Overflow */
-#define AT91C_TC_LOVRS ( 0x1 << 1 ) /* (TC) Load Overrun */
-#define AT91C_TC_CPAS ( 0x1 << 2 ) /* (TC) RA Compare */
-#define AT91C_TC_CPBS ( 0x1 << 3 ) /* (TC) RB Compare */
-#define AT91C_TC_CPCS ( 0x1 << 4 ) /* (TC) RC Compare */
-#define AT91C_TC_LDRAS ( 0x1 << 5 ) /* (TC) RA Loading */
-#define AT91C_TC_LDRBS ( 0x1 << 6 ) /* (TC) RB Loading */
-#define AT91C_TC_ETRGS ( 0x1 << 7 ) /* (TC) External Trigger */
-#define AT91C_TC_CLKSTA ( 0x1 << 16 ) /* (TC) Clock Enabling */
-#define AT91C_TC_MTIOA ( 0x1 << 17 ) /* (TC) TIOA Mirror */
-#define AT91C_TC_MTIOB ( 0x1 << 18 ) /* (TC) TIOA Mirror */
-/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
-/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
-/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TC structure ***
+#define TC_CCR ( 0) // Channel Control Register
+#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV (16) // Counter Value
+#define TC_RA (20) // Register A
+#define TC_RB (24) // Register B
+#define TC_RC (28) // Register C
+#define TC_SR (32) // Status Register
+#define TC_IER (36) // Interrupt Enable Register
+#define TC_IDR (40) // Interrupt Disable Register
+#define TC_IMR (44) // Interrupt Mask Register
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE (0x1 << 15) // (TC)
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Timer Counter Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TCB structure *** */
-#define TCB_TC0 ( 0 ) /* TC Channel 0 */
-#define TCB_TC1 ( 64 ) /* TC Channel 1 */
-#define TCB_TC2 ( 128 ) /* TC Channel 2 */
-#define TCB_BCR ( 192 ) /* TC Block Control Register */
-#define TCB_BMR ( 196 ) /* TC Block Mode Register */
-/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
-#define AT91C_TCB_SYNC ( 0x1 << 0 ) /* (TCB) Synchro Command */
-/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
-#define AT91C_TCB_TC0XC0S ( 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
-#define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0 ) /* (TCB) TCLK0 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_NONE ( 0x1 ) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2 ) /* (TCB) TIOA1 connected to XC0 */
-#define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3 ) /* (TCB) TIOA2 connected to XC0 */
-#define AT91C_TCB_TC1XC1S ( 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
-#define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
-#define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
-#define AT91C_TCB_TC2XC2S ( 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
-#define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
-#define AT91C_TCB_TC2XC2S_TIOA1 ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TCB structure ***
+#define TCB_TC0 ( 0) // TC Channel 0
+#define TCB_TC1 (64) // TC Channel 1
+#define TCB_TC2 (128) // TC Channel 2
+#define TCB_BCR (192) // TC Block Control Register
+#define TCB_BMR (196) // TC Block Mode Register
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_CAN_MB structure *** */
-#define CAN_MB_MMR ( 0 ) /* MailBox Mode Register */
-#define CAN_MB_MAM ( 4 ) /* MailBox Acceptance Mask Register */
-#define CAN_MB_MID ( 8 ) /* MailBox ID Register */
-#define CAN_MB_MFID ( 12 ) /* MailBox Family ID Register */
-#define CAN_MB_MSR ( 16 ) /* MailBox Status Register */
-#define CAN_MB_MDL ( 20 ) /* MailBox Data Low Register */
-#define CAN_MB_MDH ( 24 ) /* MailBox Data High Register */
-#define CAN_MB_MCR ( 28 ) /* MailBox Control Register */
-/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
-#define AT91C_CAN_MTIMEMARK ( 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */
-#define AT91C_CAN_PRIOR ( 0xF << 16 ) /* (CAN_MB) Mailbox Priority */
-#define AT91C_CAN_MOT ( 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */
-#define AT91C_CAN_MOT_DIS ( 0x0 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RX ( 0x1 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_RXOVERWRITE ( 0x2 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_TX ( 0x3 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_CONSUMER ( 0x4 << 24 ) /* (CAN_MB) */
-#define AT91C_CAN_MOT_PRODUCER ( 0x5 << 24 ) /* (CAN_MB) */
-/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
-#define AT91C_CAN_MIDvB ( 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
-#define AT91C_CAN_MIDvA ( 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */
-#define AT91C_CAN_MIDE ( 0x1 << 29 ) /* (CAN_MB) Identifier Version */
-/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
-/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
-/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
-#define AT91C_CAN_MTIMESTAMP ( 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
-#define AT91C_CAN_MDLC ( 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */
-#define AT91C_CAN_MRTR ( 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */
-#define AT91C_CAN_MABT ( 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */
-#define AT91C_CAN_MRDY ( 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */
-#define AT91C_CAN_MMI ( 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */
-/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
-/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
-/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
-#define AT91C_CAN_MACR ( 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
-#define AT91C_CAN_MTCR ( 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN_MB structure ***
+#define CAN_MB_MMR ( 0) // MailBox Mode Register
+#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register
+#define CAN_MB_MID ( 8) // MailBox ID Register
+#define CAN_MB_MFID (12) // MailBox Family ID Register
+#define CAN_MB_MSR (16) // MailBox Status Register
+#define CAN_MB_MDL (20) // MailBox Data Low Register
+#define CAN_MB_MDH (24) // MailBox Data High Register
+#define CAN_MB_MCR (28) // MailBox Control Register
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
+#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
+#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
+#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
+#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Control Area Network Interface */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_CAN structure *** */
-#define CAN_MR ( 0 ) /* Mode Register */
-#define CAN_IER ( 4 ) /* Interrupt Enable Register */
-#define CAN_IDR ( 8 ) /* Interrupt Disable Register */
-#define CAN_IMR ( 12 ) /* Interrupt Mask Register */
-#define CAN_SR ( 16 ) /* Status Register */
-#define CAN_BR ( 20 ) /* Baudrate Register */
-#define CAN_TIM ( 24 ) /* Timer Register */
-#define CAN_TIMESTP ( 28 ) /* Time Stamp Register */
-#define CAN_ECR ( 32 ) /* Error Counter Register */
-#define CAN_TCR ( 36 ) /* Transfer Command Register */
-#define CAN_ACR ( 40 ) /* Abort Command Register */
-#define CAN_VR ( 252 ) /* Version Register */
-#define CAN_MB0 ( 512 ) /* CAN Mailbox 0 */
-#define CAN_MB1 ( 544 ) /* CAN Mailbox 1 */
-#define CAN_MB2 ( 576 ) /* CAN Mailbox 2 */
-#define CAN_MB3 ( 608 ) /* CAN Mailbox 3 */
-#define CAN_MB4 ( 640 ) /* CAN Mailbox 4 */
-#define CAN_MB5 ( 672 ) /* CAN Mailbox 5 */
-#define CAN_MB6 ( 704 ) /* CAN Mailbox 6 */
-#define CAN_MB7 ( 736 ) /* CAN Mailbox 7 */
-#define CAN_MB8 ( 768 ) /* CAN Mailbox 8 */
-#define CAN_MB9 ( 800 ) /* CAN Mailbox 9 */
-#define CAN_MB10 ( 832 ) /* CAN Mailbox 10 */
-#define CAN_MB11 ( 864 ) /* CAN Mailbox 11 */
-#define CAN_MB12 ( 896 ) /* CAN Mailbox 12 */
-#define CAN_MB13 ( 928 ) /* CAN Mailbox 13 */
-#define CAN_MB14 ( 960 ) /* CAN Mailbox 14 */
-#define CAN_MB15 ( 992 ) /* CAN Mailbox 15 */
-/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
-#define AT91C_CAN_CANEN ( 0x1 << 0 ) /* (CAN) CAN Controller Enable */
-#define AT91C_CAN_LPM ( 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */
-#define AT91C_CAN_ABM ( 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */
-#define AT91C_CAN_OVL ( 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */
-#define AT91C_CAN_TEOF ( 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */
-#define AT91C_CAN_TTM ( 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */
-#define AT91C_CAN_TIMFRZ ( 0x1 << 6 ) /* (CAN) Enable Timer Freeze */
-#define AT91C_CAN_DRPT ( 0x1 << 7 ) /* (CAN) Disable Repeat */
-/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
-#define AT91C_CAN_MB0 ( 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */
-#define AT91C_CAN_MB1 ( 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */
-#define AT91C_CAN_MB2 ( 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */
-#define AT91C_CAN_MB3 ( 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */
-#define AT91C_CAN_MB4 ( 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */
-#define AT91C_CAN_MB5 ( 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */
-#define AT91C_CAN_MB6 ( 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */
-#define AT91C_CAN_MB7 ( 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */
-#define AT91C_CAN_MB8 ( 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */
-#define AT91C_CAN_MB9 ( 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */
-#define AT91C_CAN_MB10 ( 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
-#define AT91C_CAN_MB11 ( 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
-#define AT91C_CAN_MB12 ( 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
-#define AT91C_CAN_MB13 ( 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
-#define AT91C_CAN_MB14 ( 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
-#define AT91C_CAN_MB15 ( 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
-#define AT91C_CAN_ERRA ( 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
-#define AT91C_CAN_WARN ( 0x1 << 17 ) /* (CAN) Warning Limit Flag */
-#define AT91C_CAN_ERRP ( 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
-#define AT91C_CAN_BOFF ( 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
-#define AT91C_CAN_SLEEP ( 0x1 << 20 ) /* (CAN) Sleep Flag */
-#define AT91C_CAN_WAKEUP ( 0x1 << 21 ) /* (CAN) Wakeup Flag */
-#define AT91C_CAN_TOVF ( 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
-#define AT91C_CAN_TSTP ( 0x1 << 23 ) /* (CAN) Timestamp Flag */
-#define AT91C_CAN_CERR ( 0x1 << 24 ) /* (CAN) CRC Error */
-#define AT91C_CAN_SERR ( 0x1 << 25 ) /* (CAN) Stuffing Error */
-#define AT91C_CAN_AERR ( 0x1 << 26 ) /* (CAN) Acknowledgment Error */
-#define AT91C_CAN_FERR ( 0x1 << 27 ) /* (CAN) Form Error */
-#define AT91C_CAN_BERR ( 0x1 << 28 ) /* (CAN) Bit Error */
-/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
-/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
-/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
-#define AT91C_CAN_RBSY ( 0x1 << 29 ) /* (CAN) Receiver Busy */
-#define AT91C_CAN_TBSY ( 0x1 << 30 ) /* (CAN) Transmitter Busy */
-#define AT91C_CAN_OVLY ( 0x1 << 31 ) /* (CAN) Overload Busy */
-/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
-#define AT91C_CAN_PHASE2 ( 0x7 << 0 ) /* (CAN) Phase 2 segment */
-#define AT91C_CAN_PHASE1 ( 0x7 << 4 ) /* (CAN) Phase 1 segment */
-#define AT91C_CAN_PROPAG ( 0x7 << 8 ) /* (CAN) Programmation time segment */
-#define AT91C_CAN_SYNC ( 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */
-#define AT91C_CAN_BRP ( 0x7F << 16 ) /* (CAN) Baudrate Prescaler */
-#define AT91C_CAN_SMP ( 0x1 << 24 ) /* (CAN) Sampling mode */
-/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
-#define AT91C_CAN_TIMER ( 0xFFFF << 0 ) /* (CAN) Timer field */
-/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
-/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
-#define AT91C_CAN_REC ( 0xFF << 0 ) /* (CAN) Receive Error Counter */
-#define AT91C_CAN_TEC ( 0xFF << 16 ) /* (CAN) Transmit Error Counter */
-/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
-#define AT91C_CAN_TIMRST ( 0x1 << 31 ) /* (CAN) Timer Reset Field */
-/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN structure ***
+#define CAN_MR ( 0) // Mode Register
+#define CAN_IER ( 4) // Interrupt Enable Register
+#define CAN_IDR ( 8) // Interrupt Disable Register
+#define CAN_IMR (12) // Interrupt Mask Register
+#define CAN_SR (16) // Status Register
+#define CAN_BR (20) // Baudrate Register
+#define CAN_TIM (24) // Timer Register
+#define CAN_TIMESTP (28) // Time Stamp Register
+#define CAN_ECR (32) // Error Counter Register
+#define CAN_TCR (36) // Transfer Command Register
+#define CAN_ACR (40) // Abort Command Register
+#define CAN_VR (252) // Version Register
+#define CAN_MB0 (512) // CAN Mailbox 0
+#define CAN_MB1 (544) // CAN Mailbox 1
+#define CAN_MB2 (576) // CAN Mailbox 2
+#define CAN_MB3 (608) // CAN Mailbox 3
+#define CAN_MB4 (640) // CAN Mailbox 4
+#define CAN_MB5 (672) // CAN Mailbox 5
+#define CAN_MB6 (704) // CAN Mailbox 6
+#define CAN_MB7 (736) // CAN Mailbox 7
+#define CAN_MB8 (768) // CAN Mailbox 8
+#define CAN_MB9 (800) // CAN Mailbox 9
+#define CAN_MB10 (832) // CAN Mailbox 10
+#define CAN_MB11 (864) // CAN Mailbox 11
+#define CAN_MB12 (896) // CAN Mailbox 12
+#define CAN_MB13 (928) // CAN Mailbox 13
+#define CAN_MB14 (960) // CAN Mailbox 14
+#define CAN_MB15 (992) // CAN Mailbox 15
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
+#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
+#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
+#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
+#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
+#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
+#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
+#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_EMAC structure *** */
-#define EMAC_NCR ( 0 ) /* Network Control Register */
-#define EMAC_NCFGR ( 4 ) /* Network Configuration Register */
-#define EMAC_NSR ( 8 ) /* Network Status Register */
-#define EMAC_TSR ( 20 ) /* Transmit Status Register */
-#define EMAC_RBQP ( 24 ) /* Receive Buffer Queue Pointer */
-#define EMAC_TBQP ( 28 ) /* Transmit Buffer Queue Pointer */
-#define EMAC_RSR ( 32 ) /* Receive Status Register */
-#define EMAC_ISR ( 36 ) /* Interrupt Status Register */
-#define EMAC_IER ( 40 ) /* Interrupt Enable Register */
-#define EMAC_IDR ( 44 ) /* Interrupt Disable Register */
-#define EMAC_IMR ( 48 ) /* Interrupt Mask Register */
-#define EMAC_MAN ( 52 ) /* PHY Maintenance Register */
-#define EMAC_PTR ( 56 ) /* Pause Time Register */
-#define EMAC_PFR ( 60 ) /* Pause Frames received Register */
-#define EMAC_FTO ( 64 ) /* Frames Transmitted OK Register */
-#define EMAC_SCF ( 68 ) /* Single Collision Frame Register */
-#define EMAC_MCF ( 72 ) /* Multiple Collision Frame Register */
-#define EMAC_FRO ( 76 ) /* Frames Received OK Register */
-#define EMAC_FCSE ( 80 ) /* Frame Check Sequence Error Register */
-#define EMAC_ALE ( 84 ) /* Alignment Error Register */
-#define EMAC_DTF ( 88 ) /* Deferred Transmission Frame Register */
-#define EMAC_LCOL ( 92 ) /* Late Collision Register */
-#define EMAC_ECOL ( 96 ) /* Excessive Collision Register */
-#define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */
-#define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */
-#define EMAC_RRE ( 108 ) /* Receive Ressource Error Register */
-#define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */
-#define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */
-#define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */
-#define EMAC_RJA ( 124 ) /* Receive Jabbers Register */
-#define EMAC_USF ( 128 ) /* Undersize Frames Register */
-#define EMAC_STE ( 132 ) /* SQE Test Error Register */
-#define EMAC_RLE ( 136 ) /* Receive Length Field Mismatch Register */
-#define EMAC_TPF ( 140 ) /* Transmitted Pause Frames Register */
-#define EMAC_HRB ( 144 ) /* Hash Address Bottom[31:0] */
-#define EMAC_HRT ( 148 ) /* Hash Address Top[63:32] */
-#define EMAC_SA1L ( 152 ) /* Specific Address 1 Bottom, First 4 bytes */
-#define EMAC_SA1H ( 156 ) /* Specific Address 1 Top, Last 2 bytes */
-#define EMAC_SA2L ( 160 ) /* Specific Address 2 Bottom, First 4 bytes */
-#define EMAC_SA2H ( 164 ) /* Specific Address 2 Top, Last 2 bytes */
-#define EMAC_SA3L ( 168 ) /* Specific Address 3 Bottom, First 4 bytes */
-#define EMAC_SA3H ( 172 ) /* Specific Address 3 Top, Last 2 bytes */
-#define EMAC_SA4L ( 176 ) /* Specific Address 4 Bottom, First 4 bytes */
-#define EMAC_SA4H ( 180 ) /* Specific Address 4 Top, Last 2 bytes */
-#define EMAC_TID ( 184 ) /* Type ID Checking Register */
-#define EMAC_TPQ ( 188 ) /* Transmit Pause Quantum Register */
-#define EMAC_USRIO ( 192 ) /* USER Input/Output Register */
-#define EMAC_WOL ( 196 ) /* Wake On LAN Register */
-#define EMAC_REV ( 252 ) /* Revision Register */
-/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */
-#define AT91C_EMAC_LB ( 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LLB ( 0x1 << 1 ) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE ( 0x1 << 2 ) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE ( 0x1 << 3 ) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE ( 0x1 << 4 ) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CLRSTAT ( 0x1 << 5 ) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_INCSTAT ( 0x1 << 6 ) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WESTAT ( 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP ( 0x1 << 8 ) /* (EMAC) Back pressure. */
-#define AT91C_EMAC_TSTART ( 0x1 << 9 ) /* (EMAC) Start Transmission. */
-#define AT91C_EMAC_THALT ( 0x1 << 10 ) /* (EMAC) Transmission Halt. */
-#define AT91C_EMAC_TPFR ( 0x1 << 11 ) /* (EMAC) Transmit pause frame */
-#define AT91C_EMAC_TZQ ( 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
-/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
-#define AT91C_EMAC_SPD ( 0x1 << 0 ) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD ( 0x1 << 1 ) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_JFRAME ( 0x1 << 3 ) /* (EMAC) Jumbo Frames. */
-#define AT91C_EMAC_CAF ( 0x1 << 4 ) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC ( 0x1 << 5 ) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI ( 0x1 << 6 ) /* (EMAC) Multicast hash event enable */
-#define AT91C_EMAC_UNI ( 0x1 << 7 ) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG ( 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE ( 0x1 << 9 ) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK ( 0x3 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8 ( 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16 ( 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32 ( 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64 ( 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY ( 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PAE ( 0x1 << 13 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF ( 0x3 << 14 ) /* (EMAC) */
-#define AT91C_EMAC_RBOF_OFFSET_0 ( 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_1 ( 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_2 ( 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
-#define AT91C_EMAC_RBOF_OFFSET_3 ( 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
-#define AT91C_EMAC_RLCE ( 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
-#define AT91C_EMAC_DRFCS ( 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
-#define AT91C_EMAC_EFRHD ( 0x1 << 18 ) /* (EMAC) */
-#define AT91C_EMAC_IRXFCS ( 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
-/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
-#define AT91C_EMAC_LINKR ( 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_MDIO ( 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_IDLE ( 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
-#define AT91C_EMAC_UBR ( 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_COL ( 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RLES ( 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TGO ( 0x1 << 3 ) /* (EMAC) Transmit Go */
-#define AT91C_EMAC_BEX ( 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */
-#define AT91C_EMAC_COMP ( 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_UND ( 0x1 << 6 ) /* (EMAC) */
-/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA ( 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_REC ( 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_OVR ( 0x1 << 2 ) /* (EMAC) */
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
-#define AT91C_EMAC_MFD ( 0x1 << 0 ) /* (EMAC) */
-#define AT91C_EMAC_RCOMP ( 0x1 << 1 ) /* (EMAC) */
-#define AT91C_EMAC_RXUBR ( 0x1 << 2 ) /* (EMAC) */
-#define AT91C_EMAC_TXUBR ( 0x1 << 3 ) /* (EMAC) */
-#define AT91C_EMAC_TUNDR ( 0x1 << 4 ) /* (EMAC) */
-#define AT91C_EMAC_RLEX ( 0x1 << 5 ) /* (EMAC) */
-#define AT91C_EMAC_TXERR ( 0x1 << 6 ) /* (EMAC) */
-#define AT91C_EMAC_TCOMP ( 0x1 << 7 ) /* (EMAC) */
-#define AT91C_EMAC_LINK ( 0x1 << 9 ) /* (EMAC) */
-#define AT91C_EMAC_ROVR ( 0x1 << 10 ) /* (EMAC) */
-#define AT91C_EMAC_HRESP ( 0x1 << 11 ) /* (EMAC) */
-#define AT91C_EMAC_PFRE ( 0x1 << 12 ) /* (EMAC) */
-#define AT91C_EMAC_PTZ ( 0x1 << 13 ) /* (EMAC) */
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
-/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA ( 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_CODE ( 0x3 << 16 ) /* (EMAC) */
-#define AT91C_EMAC_REGA ( 0x1F << 18 ) /* (EMAC) */
-#define AT91C_EMAC_PHYA ( 0x1F << 23 ) /* (EMAC) */
-#define AT91C_EMAC_RW ( 0x3 << 28 ) /* (EMAC) */
-#define AT91C_EMAC_SOF ( 0x3 << 30 ) /* (EMAC) */
-/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
-#define AT91C_EMAC_RMII ( 0x1 << 0 ) /* (EMAC) Reduce MII */
-/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
-#define AT91C_EMAC_IP ( 0xFFFF << 0 ) /* (EMAC) ARP request IP address */
-#define AT91C_EMAC_MAG ( 0x1 << 16 ) /* (EMAC) Magic packet event enable */
-#define AT91C_EMAC_ARP ( 0x1 << 17 ) /* (EMAC) ARP request event enable */
-#define AT91C_EMAC_SA1 ( 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */
-/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
-#define AT91C_EMAC_REVREF ( 0xFFFF << 0 ) /* (EMAC) */
-#define AT91C_EMAC_PARTREF ( 0xFFFF << 16 ) /* (EMAC) */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
+// *****************************************************************************
+// *** Register offset in AT91S_EMAC structure ***
+#define EMAC_NCR ( 0) // Network Control Register
+#define EMAC_NCFGR ( 4) // Network Configuration Register
+#define EMAC_NSR ( 8) // Network Status Register
+#define EMAC_TSR (20) // Transmit Status Register
+#define EMAC_RBQP (24) // Receive Buffer Queue Pointer
+#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer
+#define EMAC_RSR (32) // Receive Status Register
+#define EMAC_ISR (36) // Interrupt Status Register
+#define EMAC_IER (40) // Interrupt Enable Register
+#define EMAC_IDR (44) // Interrupt Disable Register
+#define EMAC_IMR (48) // Interrupt Mask Register
+#define EMAC_MAN (52) // PHY Maintenance Register
+#define EMAC_PTR (56) // Pause Time Register
+#define EMAC_PFR (60) // Pause Frames received Register
+#define EMAC_FTO (64) // Frames Transmitted OK Register
+#define EMAC_SCF (68) // Single Collision Frame Register
+#define EMAC_MCF (72) // Multiple Collision Frame Register
+#define EMAC_FRO (76) // Frames Received OK Register
+#define EMAC_FCSE (80) // Frame Check Sequence Error Register
+#define EMAC_ALE (84) // Alignment Error Register
+#define EMAC_DTF (88) // Deferred Transmission Frame Register
+#define EMAC_LCOL (92) // Late Collision Register
+#define EMAC_ECOL (96) // Excessive Collision Register
+#define EMAC_TUND (100) // Transmit Underrun Error Register
+#define EMAC_CSE (104) // Carrier Sense Error Register
+#define EMAC_RRE (108) // Receive Ressource Error Register
+#define EMAC_ROV (112) // Receive Overrun Errors Register
+#define EMAC_RSE (116) // Receive Symbol Errors Register
+#define EMAC_ELE (120) // Excessive Length Errors Register
+#define EMAC_RJA (124) // Receive Jabbers Register
+#define EMAC_USF (128) // Undersize Frames Register
+#define EMAC_STE (132) // SQE Test Error Register
+#define EMAC_RLE (136) // Receive Length Field Mismatch Register
+#define EMAC_TPF (140) // Transmitted Pause Frames Register
+#define EMAC_HRB (144) // Hash Address Bottom[31:0]
+#define EMAC_HRT (148) // Hash Address Top[63:32]
+#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes
+#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes
+#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes
+#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes
+#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes
+#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes
+#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes
+#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes
+#define EMAC_TID (184) // Type ID Checking Register
+#define EMAC_TPQ (188) // Transmit Pause Quantum Register
+#define EMAC_USRIO (192) // USER Input/Output Register
+#define EMAC_WOL (196) // Wake On LAN Register
+#define EMAC_REV (252) // Revision Register
+// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
+#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
+#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
+#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
+#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
+#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
+#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
+#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
+#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
+#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
+#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
+#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
+#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
+#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
+#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
+#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
+#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
+#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
+#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
+#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
+#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
+#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
+#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
+#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
+#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
+#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
+#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
+#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
+#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
+#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
+#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
+#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
+#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
+#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
+#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
+#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
+#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
+#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
+#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
+#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
+#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
+#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
+#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
+#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
+#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
+#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
+#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
+#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
+#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
+#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
+#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
+#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
+#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_ADC structure *** */
-#define ADC_CR ( 0 ) /* ADC Control Register */
-#define ADC_MR ( 4 ) /* ADC Mode Register */
-#define ADC_CHER ( 16 ) /* ADC Channel Enable Register */
-#define ADC_CHDR ( 20 ) /* ADC Channel Disable Register */
-#define ADC_CHSR ( 24 ) /* ADC Channel Status Register */
-#define ADC_SR ( 28 ) /* ADC Status Register */
-#define ADC_LCDR ( 32 ) /* ADC Last Converted Data Register */
-#define ADC_IER ( 36 ) /* ADC Interrupt Enable Register */
-#define ADC_IDR ( 40 ) /* ADC Interrupt Disable Register */
-#define ADC_IMR ( 44 ) /* ADC Interrupt Mask Register */
-#define ADC_CDR0 ( 48 ) /* ADC Channel Data Register 0 */
-#define ADC_CDR1 ( 52 ) /* ADC Channel Data Register 1 */
-#define ADC_CDR2 ( 56 ) /* ADC Channel Data Register 2 */
-#define ADC_CDR3 ( 60 ) /* ADC Channel Data Register 3 */
-#define ADC_CDR4 ( 64 ) /* ADC Channel Data Register 4 */
-#define ADC_CDR5 ( 68 ) /* ADC Channel Data Register 5 */
-#define ADC_CDR6 ( 72 ) /* ADC Channel Data Register 6 */
-#define ADC_CDR7 ( 76 ) /* ADC Channel Data Register 7 */
-#define ADC_RPR ( 256 ) /* Receive Pointer Register */
-#define ADC_RCR ( 260 ) /* Receive Counter Register */
-#define ADC_TPR ( 264 ) /* Transmit Pointer Register */
-#define ADC_TCR ( 268 ) /* Transmit Counter Register */
-#define ADC_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define ADC_RNCR ( 276 ) /* Receive Next Counter Register */
-#define ADC_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define ADC_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define ADC_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define ADC_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
-#define AT91C_ADC_SWRST ( 0x1 << 0 ) /* (ADC) Software Reset */
-#define AT91C_ADC_START ( 0x1 << 1 ) /* (ADC) Start Conversion */
-/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
-#define AT91C_ADC_TRGEN ( 0x1 << 0 ) /* (ADC) Trigger Enable */
-#define AT91C_ADC_TRGEN_DIS ( 0x0 ) /* (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software */
-#define AT91C_ADC_TRGEN_EN ( 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
-#define AT91C_ADC_TRGSEL ( 0x7 << 1 ) /* (ADC) Trigger Selection */
-#define AT91C_ADC_TRGSEL_TIOA0 ( 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */
-#define AT91C_ADC_TRGSEL_TIOA1 ( 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */
-#define AT91C_ADC_TRGSEL_TIOA2 ( 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */
-#define AT91C_ADC_TRGSEL_TIOA3 ( 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */
-#define AT91C_ADC_TRGSEL_TIOA4 ( 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */
-#define AT91C_ADC_TRGSEL_TIOA5 ( 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */
-#define AT91C_ADC_TRGSEL_EXT ( 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */
-#define AT91C_ADC_LOWRES ( 0x1 << 4 ) /* (ADC) Resolution. */
-#define AT91C_ADC_LOWRES_10_BIT ( 0x0 << 4 ) /* (ADC) 10-bit resolution */
-#define AT91C_ADC_LOWRES_8_BIT ( 0x1 << 4 ) /* (ADC) 8-bit resolution */
-#define AT91C_ADC_SLEEP ( 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_SLEEP_NORMAL_MODE ( 0x0 << 5 ) /* (ADC) Normal Mode */
-#define AT91C_ADC_SLEEP_MODE ( 0x1 << 5 ) /* (ADC) Sleep Mode */
-#define AT91C_ADC_PRESCAL ( 0x3F << 8 ) /* (ADC) Prescaler rate selection */
-#define AT91C_ADC_STARTUP ( 0x1F << 16 ) /* (ADC) Startup Time */
-#define AT91C_ADC_SHTIM ( 0xF << 24 ) /* (ADC) Sample & Hold Time */
-/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
-#define AT91C_ADC_CH0 ( 0x1 << 0 ) /* (ADC) Channel 0 */
-#define AT91C_ADC_CH1 ( 0x1 << 1 ) /* (ADC) Channel 1 */
-#define AT91C_ADC_CH2 ( 0x1 << 2 ) /* (ADC) Channel 2 */
-#define AT91C_ADC_CH3 ( 0x1 << 3 ) /* (ADC) Channel 3 */
-#define AT91C_ADC_CH4 ( 0x1 << 4 ) /* (ADC) Channel 4 */
-#define AT91C_ADC_CH5 ( 0x1 << 5 ) /* (ADC) Channel 5 */
-#define AT91C_ADC_CH6 ( 0x1 << 6 ) /* (ADC) Channel 6 */
-#define AT91C_ADC_CH7 ( 0x1 << 7 ) /* (ADC) Channel 7 */
-/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
-/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
-/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
-#define AT91C_ADC_EOC0 ( 0x1 << 0 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC1 ( 0x1 << 1 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC2 ( 0x1 << 2 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC3 ( 0x1 << 3 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC4 ( 0x1 << 4 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC5 ( 0x1 << 5 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC6 ( 0x1 << 6 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_EOC7 ( 0x1 << 7 ) /* (ADC) End of Conversion */
-#define AT91C_ADC_OVRE0 ( 0x1 << 8 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE1 ( 0x1 << 9 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE2 ( 0x1 << 10 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE3 ( 0x1 << 11 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE4 ( 0x1 << 12 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE5 ( 0x1 << 13 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE6 ( 0x1 << 14 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_OVRE7 ( 0x1 << 15 ) /* (ADC) Overrun Error */
-#define AT91C_ADC_DRDY ( 0x1 << 16 ) /* (ADC) Data Ready */
-#define AT91C_ADC_GOVRE ( 0x1 << 17 ) /* (ADC) General Overrun */
-#define AT91C_ADC_ENDRX ( 0x1 << 18 ) /* (ADC) End of Receiver Transfer */
-#define AT91C_ADC_RXBUFF ( 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */
-/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
-#define AT91C_ADC_LDATA ( 0x3FF << 0 ) /* (ADC) Last Data Converted */
-/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
-/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
-/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
-/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
-#define AT91C_ADC_DATA ( 0x3FF << 0 ) /* (ADC) Converted Data */
-/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
-/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
-/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
-/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
-/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
-/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
-/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+// *** Register offset in AT91S_ADC structure ***
+#define ADC_CR ( 0) // ADC Control Register
+#define ADC_MR ( 4) // ADC Mode Register
+#define ADC_CHER (16) // ADC Channel Enable Register
+#define ADC_CHDR (20) // ADC Channel Disable Register
+#define ADC_CHSR (24) // ADC Channel Status Register
+#define ADC_SR (28) // ADC Status Register
+#define ADC_LCDR (32) // ADC Last Converted Data Register
+#define ADC_IER (36) // ADC Interrupt Enable Register
+#define ADC_IDR (40) // ADC Interrupt Disable Register
+#define ADC_IMR (44) // ADC Interrupt Mask Register
+#define ADC_CDR0 (48) // ADC Channel Data Register 0
+#define ADC_CDR1 (52) // ADC Channel Data Register 1
+#define ADC_CDR2 (56) // ADC Channel Data Register 2
+#define ADC_CDR3 (60) // ADC Channel Data Register 3
+#define ADC_CDR4 (64) // ADC Channel Data Register 4
+#define ADC_CDR5 (68) // ADC Channel Data Register 5
+#define ADC_CDR6 (72) // ADC Channel Data Register 6
+#define ADC_CDR7 (76) // ADC Channel Data Register 7
+#define ADC_RPR (256) // Receive Pointer Register
+#define ADC_RCR (260) // Receive Counter Register
+#define ADC_TPR (264) // Transmit Pointer Register
+#define ADC_TCR (268) // Transmit Counter Register
+#define ADC_RNPR (272) // Receive Next Pointer Register
+#define ADC_RNCR (276) // Receive Next Counter Register
+#define ADC_TNPR (280) // Transmit Next Pointer Register
+#define ADC_TNCR (284) // Transmit Next Counter Register
+#define ADC_PTCR (288) // PDC Transfer Control Register
+#define ADC_PTSR (292) // PDC Transfer Status Register
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_AES structure *** */
-#define AES_CR ( 0 ) /* Control Register */
-#define AES_MR ( 4 ) /* Mode Register */
-#define AES_IER ( 16 ) /* Interrupt Enable Register */
-#define AES_IDR ( 20 ) /* Interrupt Disable Register */
-#define AES_IMR ( 24 ) /* Interrupt Mask Register */
-#define AES_ISR ( 28 ) /* Interrupt Status Register */
-#define AES_KEYWxR ( 32 ) /* Key Word x Register */
-#define AES_IDATAxR ( 64 ) /* Input Data x Register */
-#define AES_ODATAxR ( 80 ) /* Output Data x Register */
-#define AES_IVxR ( 96 ) /* Initialization Vector x Register */
-#define AES_VR ( 252 ) /* AES Version Register */
-#define AES_RPR ( 256 ) /* Receive Pointer Register */
-#define AES_RCR ( 260 ) /* Receive Counter Register */
-#define AES_TPR ( 264 ) /* Transmit Pointer Register */
-#define AES_TCR ( 268 ) /* Transmit Counter Register */
-#define AES_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define AES_RNCR ( 276 ) /* Receive Next Counter Register */
-#define AES_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define AES_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define AES_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define AES_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
-#define AT91C_AES_START ( 0x1 << 0 ) /* (AES) Starts Processing */
-#define AT91C_AES_SWRST ( 0x1 << 8 ) /* (AES) Software Reset */
-#define AT91C_AES_LOADSEED ( 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */
-/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
-#define AT91C_AES_CIPHER ( 0x1 << 0 ) /* (AES) Processing Mode */
-#define AT91C_AES_PROCDLY ( 0xF << 4 ) /* (AES) Processing Delay */
-#define AT91C_AES_SMOD ( 0x3 << 8 ) /* (AES) Start Mode */
-#define AT91C_AES_SMOD_MANUAL ( 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
-#define AT91C_AES_SMOD_AUTO ( 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
-#define AT91C_AES_SMOD_PDC ( 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */
-#define AT91C_AES_OPMOD ( 0x7 << 12 ) /* (AES) Operation Mode */
-#define AT91C_AES_OPMOD_ECB ( 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */
-#define AT91C_AES_OPMOD_CBC ( 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */
-#define AT91C_AES_OPMOD_OFB ( 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */
-#define AT91C_AES_OPMOD_CFB ( 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */
-#define AT91C_AES_OPMOD_CTR ( 0x4 << 12 ) /* (AES) CTR Counter mode. */
-#define AT91C_AES_LOD ( 0x1 << 15 ) /* (AES) Last Output Data Mode */
-#define AT91C_AES_CFBS ( 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */
-#define AT91C_AES_CFBS_128_BIT ( 0x0 << 16 ) /* (AES) 128-bit. */
-#define AT91C_AES_CFBS_64_BIT ( 0x1 << 16 ) /* (AES) 64-bit. */
-#define AT91C_AES_CFBS_32_BIT ( 0x2 << 16 ) /* (AES) 32-bit. */
-#define AT91C_AES_CFBS_16_BIT ( 0x3 << 16 ) /* (AES) 16-bit. */
-#define AT91C_AES_CFBS_8_BIT ( 0x4 << 16 ) /* (AES) 8-bit. */
-#define AT91C_AES_CKEY ( 0xF << 20 ) /* (AES) Countermeasure Key */
-#define AT91C_AES_CTYPE ( 0x1F << 24 ) /* (AES) Countermeasure Type */
-#define AT91C_AES_CTYPE_TYPE1_EN ( 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */
-#define AT91C_AES_CTYPE_TYPE2_EN ( 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */
-#define AT91C_AES_CTYPE_TYPE3_EN ( 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */
-#define AT91C_AES_CTYPE_TYPE4_EN ( 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */
-#define AT91C_AES_CTYPE_TYPE5_EN ( 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
-/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_AES_DATRDY ( 0x1 << 0 ) /* (AES) DATRDY */
-#define AT91C_AES_ENDRX ( 0x1 << 1 ) /* (AES) PDC Read Buffer End */
-#define AT91C_AES_ENDTX ( 0x1 << 2 ) /* (AES) PDC Write Buffer End */
-#define AT91C_AES_RXBUFF ( 0x1 << 3 ) /* (AES) PDC Read Buffer Full */
-#define AT91C_AES_TXBUFE ( 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */
-#define AT91C_AES_URAD ( 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */
-/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_AES_URAT ( 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
-#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
-#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
-#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
-#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
-#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
-#define AT91C_AES_URAT_WO_REG_READ ( 0x5 << 12 ) /* (AES) Write-only register read access. */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_AES structure ***
+#define AES_CR ( 0) // Control Register
+#define AES_MR ( 4) // Mode Register
+#define AES_IER (16) // Interrupt Enable Register
+#define AES_IDR (20) // Interrupt Disable Register
+#define AES_IMR (24) // Interrupt Mask Register
+#define AES_ISR (28) // Interrupt Status Register
+#define AES_KEYWxR (32) // Key Word x Register
+#define AES_IDATAxR (64) // Input Data x Register
+#define AES_ODATAxR (80) // Output Data x Register
+#define AES_IVxR (96) // Initialization Vector x Register
+#define AES_VR (252) // AES Version Register
+#define AES_RPR (256) // Receive Pointer Register
+#define AES_RCR (260) // Receive Counter Register
+#define AES_TPR (264) // Transmit Pointer Register
+#define AES_TCR (268) // Transmit Counter Register
+#define AES_RNPR (272) // Receive Next Pointer Register
+#define AES_RNCR (276) // Receive Next Counter Register
+#define AES_TNPR (280) // Transmit Next Pointer Register
+#define AES_TNCR (284) // Transmit Next Counter Register
+#define AES_PTCR (288) // PDC Transfer Control Register
+#define AES_PTSR (292) // PDC Transfer Status Register
+// -------- AES_CR : (AES Offset: 0x0) Control Register --------
+#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing
+#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
+#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay
+#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode
+#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode
+#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode.
+#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size
+#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit.
+#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit.
+#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit.
+#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit.
+#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type
+#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY
+#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access.
-/* ***************************************************************************** */
-/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
-/* ***************************************************************************** */
-/* *** Register offset in AT91S_TDES structure *** */
-#define TDES_CR ( 0 ) /* Control Register */
-#define TDES_MR ( 4 ) /* Mode Register */
-#define TDES_IER ( 16 ) /* Interrupt Enable Register */
-#define TDES_IDR ( 20 ) /* Interrupt Disable Register */
-#define TDES_IMR ( 24 ) /* Interrupt Mask Register */
-#define TDES_ISR ( 28 ) /* Interrupt Status Register */
-#define TDES_KEY1WxR ( 32 ) /* Key 1 Word x Register */
-#define TDES_KEY2WxR ( 40 ) /* Key 2 Word x Register */
-#define TDES_KEY3WxR ( 48 ) /* Key 3 Word x Register */
-#define TDES_IDATAxR ( 64 ) /* Input Data x Register */
-#define TDES_ODATAxR ( 80 ) /* Output Data x Register */
-#define TDES_IVxR ( 96 ) /* Initialization Vector x Register */
-#define TDES_VR ( 252 ) /* TDES Version Register */
-#define TDES_RPR ( 256 ) /* Receive Pointer Register */
-#define TDES_RCR ( 260 ) /* Receive Counter Register */
-#define TDES_TPR ( 264 ) /* Transmit Pointer Register */
-#define TDES_TCR ( 268 ) /* Transmit Counter Register */
-#define TDES_RNPR ( 272 ) /* Receive Next Pointer Register */
-#define TDES_RNCR ( 276 ) /* Receive Next Counter Register */
-#define TDES_TNPR ( 280 ) /* Transmit Next Pointer Register */
-#define TDES_TNCR ( 284 ) /* Transmit Next Counter Register */
-#define TDES_PTCR ( 288 ) /* PDC Transfer Control Register */
-#define TDES_PTSR ( 292 ) /* PDC Transfer Status Register */
-/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
-#define AT91C_TDES_START ( 0x1 << 0 ) /* (TDES) Starts Processing */
-#define AT91C_TDES_SWRST ( 0x1 << 8 ) /* (TDES) Software Reset */
-/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
-#define AT91C_TDES_CIPHER ( 0x1 << 0 ) /* (TDES) Processing Mode */
-#define AT91C_TDES_TDESMOD ( 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */
-#define AT91C_TDES_KEYMOD ( 0x1 << 4 ) /* (TDES) Key Mode */
-#define AT91C_TDES_SMOD ( 0x3 << 8 ) /* (TDES) Start Mode */
-#define AT91C_TDES_SMOD_MANUAL ( 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
-#define AT91C_TDES_SMOD_AUTO ( 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
-#define AT91C_TDES_SMOD_PDC ( 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */
-#define AT91C_TDES_OPMOD ( 0x3 << 12 ) /* (TDES) Operation Mode */
-#define AT91C_TDES_OPMOD_ECB ( 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
-#define AT91C_TDES_OPMOD_CBC ( 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
-#define AT91C_TDES_OPMOD_OFB ( 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
-#define AT91C_TDES_OPMOD_CFB ( 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
-#define AT91C_TDES_LOD ( 0x1 << 15 ) /* (TDES) Last Output Data Mode */
-#define AT91C_TDES_CFBS ( 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
-#define AT91C_TDES_CFBS_64_BIT ( 0x0 << 16 ) /* (TDES) 64-bit. */
-#define AT91C_TDES_CFBS_32_BIT ( 0x1 << 16 ) /* (TDES) 32-bit. */
-#define AT91C_TDES_CFBS_16_BIT ( 0x2 << 16 ) /* (TDES) 16-bit. */
-#define AT91C_TDES_CFBS_8_BIT ( 0x3 << 16 ) /* (TDES) 8-bit. */
-/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
-#define AT91C_TDES_DATRDY ( 0x1 << 0 ) /* (TDES) DATRDY */
-#define AT91C_TDES_ENDRX ( 0x1 << 1 ) /* (TDES) PDC Read Buffer End */
-#define AT91C_TDES_ENDTX ( 0x1 << 2 ) /* (TDES) PDC Write Buffer End */
-#define AT91C_TDES_RXBUFF ( 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */
-#define AT91C_TDES_TXBUFE ( 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */
-#define AT91C_TDES_URAD ( 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */
-/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
-/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
-/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
-#define AT91C_TDES_URAT ( 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
-#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
-#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
-#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
-#define AT91C_TDES_URAT_WO_REG_READ ( 0x3 << 12 ) /* (TDES) Write-only register read access. */
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_TDES structure ***
+#define TDES_CR ( 0) // Control Register
+#define TDES_MR ( 4) // Mode Register
+#define TDES_IER (16) // Interrupt Enable Register
+#define TDES_IDR (20) // Interrupt Disable Register
+#define TDES_IMR (24) // Interrupt Mask Register
+#define TDES_ISR (28) // Interrupt Status Register
+#define TDES_KEY1WxR (32) // Key 1 Word x Register
+#define TDES_KEY2WxR (40) // Key 2 Word x Register
+#define TDES_KEY3WxR (48) // Key 3 Word x Register
+#define TDES_IDATAxR (64) // Input Data x Register
+#define TDES_ODATAxR (80) // Output Data x Register
+#define TDES_IVxR (96) // Initialization Vector x Register
+#define TDES_VR (252) // TDES Version Register
+#define TDES_RPR (256) // Receive Pointer Register
+#define TDES_RCR (260) // Receive Counter Register
+#define TDES_TPR (264) // Transmit Pointer Register
+#define TDES_TCR (268) // Transmit Counter Register
+#define TDES_RNPR (272) // Receive Next Pointer Register
+#define TDES_RNCR (276) // Receive Next Counter Register
+#define TDES_TNPR (280) // Transmit Next Pointer Register
+#define TDES_TNCR (284) // Transmit Next Counter Register
+#define TDES_PTCR (288) // PDC Transfer Control Register
+#define TDES_PTSR (292) // PDC Transfer Status Register
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
+#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
+#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode
+#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode
+#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit.
+#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit.
+#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit.
+#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
+#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access.
-/* ***************************************************************************** */
-/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-/* ========== Register definition for SYS peripheral ========== */
-/* ========== Register definition for AIC peripheral ========== */
-#define AT91C_AIC_IVR ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
-#define AT91C_AIC_SMR ( 0xFFFFF000 ) /* (AIC) Source Mode Register */
-#define AT91C_AIC_FVR ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
-#define AT91C_AIC_DCR ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
-#define AT91C_AIC_EOICR ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
-#define AT91C_AIC_SVR ( 0xFFFFF080 ) /* (AIC) Source Vector Register */
-#define AT91C_AIC_FFSR ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
-#define AT91C_AIC_ICCR ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
-#define AT91C_AIC_ISR ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
-#define AT91C_AIC_IMR ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
-#define AT91C_AIC_IPR ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
-#define AT91C_AIC_FFER ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
-#define AT91C_AIC_IECR ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
-#define AT91C_AIC_ISCR ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
-#define AT91C_AIC_FFDR ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
-#define AT91C_AIC_CISR ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
-#define AT91C_AIC_IDCR ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
-#define AT91C_AIC_SPU ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
-/* ========== Register definition for PDC_DBGU peripheral ========== */
-#define AT91C_DBGU_TCR ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
-#define AT91C_DBGU_RNPR ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
-#define AT91C_DBGU_TNPR ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
-#define AT91C_DBGU_TPR ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
-#define AT91C_DBGU_RPR ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
-#define AT91C_DBGU_RCR ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
-#define AT91C_DBGU_RNCR ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
-#define AT91C_DBGU_PTCR ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
-#define AT91C_DBGU_PTSR ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
-#define AT91C_DBGU_TNCR ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
-/* ========== Register definition for DBGU peripheral ========== */
-#define AT91C_DBGU_EXID ( 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
-#define AT91C_DBGU_BRGR ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
-#define AT91C_DBGU_IDR ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
-#define AT91C_DBGU_CSR ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */
-#define AT91C_DBGU_CIDR ( 0xFFFFF240 ) /* (DBGU) Chip ID Register */
-#define AT91C_DBGU_MR ( 0xFFFFF204 ) /* (DBGU) Mode Register */
-#define AT91C_DBGU_IMR ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
-#define AT91C_DBGU_CR ( 0xFFFFF200 ) /* (DBGU) Control Register */
-#define AT91C_DBGU_FNTR ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
-#define AT91C_DBGU_THR ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
-#define AT91C_DBGU_RHR ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
-#define AT91C_DBGU_IER ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
-/* ========== Register definition for PIOA peripheral ========== */
-#define AT91C_PIOA_ODR ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
-#define AT91C_PIOA_SODR ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
-#define AT91C_PIOA_ISR ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
-#define AT91C_PIOA_ABSR ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
-#define AT91C_PIOA_IER ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
-#define AT91C_PIOA_PPUDR ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
-#define AT91C_PIOA_IMR ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
-#define AT91C_PIOA_PER ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_IFDR ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
-#define AT91C_PIOA_OWDR ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
-#define AT91C_PIOA_MDSR ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
-#define AT91C_PIOA_IDR ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
-#define AT91C_PIOA_ODSR ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
-#define AT91C_PIOA_PPUSR ( 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
-#define AT91C_PIOA_OWSR ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
-#define AT91C_PIOA_BSR ( 0xFFFFF474 ) /* (PIOA) Select B Register */
-#define AT91C_PIOA_OWER ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
-#define AT91C_PIOA_IFER ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
-#define AT91C_PIOA_PDSR ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
-#define AT91C_PIOA_PPUER ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
-#define AT91C_PIOA_OSR ( 0xFFFFF418 ) /* (PIOA) Output Status Register */
-#define AT91C_PIOA_ASR ( 0xFFFFF470 ) /* (PIOA) Select A Register */
-#define AT91C_PIOA_MDDR ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
-#define AT91C_PIOA_CODR ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
-#define AT91C_PIOA_MDER ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
-#define AT91C_PIOA_PDR ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_IFSR ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
-#define AT91C_PIOA_OER ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */
-#define AT91C_PIOA_PSR ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */
-/* ========== Register definition for PIOB peripheral ========== */
-#define AT91C_PIOB_OWDR ( 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
-#define AT91C_PIOB_MDER ( 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
-#define AT91C_PIOB_PPUSR ( 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
-#define AT91C_PIOB_IMR ( 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
-#define AT91C_PIOB_ASR ( 0xFFFFF670 ) /* (PIOB) Select A Register */
-#define AT91C_PIOB_PPUDR ( 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
-#define AT91C_PIOB_PSR ( 0xFFFFF608 ) /* (PIOB) PIO Status Register */
-#define AT91C_PIOB_IER ( 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
-#define AT91C_PIOB_CODR ( 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
-#define AT91C_PIOB_OWER ( 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
-#define AT91C_PIOB_ABSR ( 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
-#define AT91C_PIOB_IFDR ( 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
-#define AT91C_PIOB_PDSR ( 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
-#define AT91C_PIOB_IDR ( 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
-#define AT91C_PIOB_OWSR ( 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
-#define AT91C_PIOB_PDR ( 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
-#define AT91C_PIOB_ODR ( 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_IFSR ( 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
-#define AT91C_PIOB_PPUER ( 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
-#define AT91C_PIOB_SODR ( 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
-#define AT91C_PIOB_ISR ( 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
-#define AT91C_PIOB_ODSR ( 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
-#define AT91C_PIOB_OSR ( 0xFFFFF618 ) /* (PIOB) Output Status Register */
-#define AT91C_PIOB_MDSR ( 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
-#define AT91C_PIOB_IFER ( 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
-#define AT91C_PIOB_BSR ( 0xFFFFF674 ) /* (PIOB) Select B Register */
-#define AT91C_PIOB_MDDR ( 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
-#define AT91C_PIOB_OER ( 0xFFFFF610 ) /* (PIOB) Output Enable Register */
-#define AT91C_PIOB_PER ( 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
-/* ========== Register definition for CKGR peripheral ========== */
-#define AT91C_CKGR_MOR ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
-#define AT91C_CKGR_PLLR ( 0xFFFFFC2C ) /* (CKGR) PLL Register */
-#define AT91C_CKGR_MCFR ( 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */
-/* ========== Register definition for PMC peripheral ========== */
-#define AT91C_PMC_IDR ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
-#define AT91C_PMC_MOR ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
-#define AT91C_PMC_PLLR ( 0xFFFFFC2C ) /* (PMC) PLL Register */
-#define AT91C_PMC_PCER ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCKR ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
-#define AT91C_PMC_MCKR ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */
-#define AT91C_PMC_SCDR ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
-#define AT91C_PMC_PCDR ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
-#define AT91C_PMC_SCSR ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
-#define AT91C_PMC_PCSR ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
-#define AT91C_PMC_MCFR ( 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */
-#define AT91C_PMC_SCER ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
-#define AT91C_PMC_IMR ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
-#define AT91C_PMC_IER ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
-#define AT91C_PMC_SR ( 0xFFFFFC68 ) /* (PMC) Status Register */
-/* ========== Register definition for RSTC peripheral ========== */
-#define AT91C_RSTC_RCR ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
-#define AT91C_RSTC_RMR ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
-#define AT91C_RSTC_RSR ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
-/* ========== Register definition for RTTC peripheral ========== */
-#define AT91C_RTTC_RTSR ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
-#define AT91C_RTTC_RTMR ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
-#define AT91C_RTTC_RTVR ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
-#define AT91C_RTTC_RTAR ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
-/* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIVR ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
-#define AT91C_PITC_PISR ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
-#define AT91C_PITC_PIIR ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
-#define AT91C_PITC_PIMR ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
-/* ========== Register definition for WDTC peripheral ========== */
-#define AT91C_WDTC_WDCR ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
-#define AT91C_WDTC_WDSR ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
-#define AT91C_WDTC_WDMR ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
-/* ========== Register definition for VREG peripheral ========== */
-#define AT91C_VREG_MR ( 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
-/* ========== Register definition for MC peripheral ========== */
-#define AT91C_MC_ASR ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
-#define AT91C_MC_RCR ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
-#define AT91C_MC_FCR ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
-#define AT91C_MC_AASR ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
-#define AT91C_MC_FSR ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
-#define AT91C_MC_FMR ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
-/* ========== Register definition for PDC_SPI1 peripheral ========== */
-#define AT91C_SPI1_PTCR ( 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
-#define AT91C_SPI1_RPR ( 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
-#define AT91C_SPI1_TNCR ( 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
-#define AT91C_SPI1_TPR ( 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
-#define AT91C_SPI1_TNPR ( 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
-#define AT91C_SPI1_TCR ( 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
-#define AT91C_SPI1_RCR ( 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
-#define AT91C_SPI1_RNPR ( 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
-#define AT91C_SPI1_RNCR ( 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
-#define AT91C_SPI1_PTSR ( 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
-/* ========== Register definition for SPI1 peripheral ========== */
-#define AT91C_SPI1_IMR ( 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
-#define AT91C_SPI1_IER ( 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
-#define AT91C_SPI1_MR ( 0xFFFE4004 ) /* (SPI1) Mode Register */
-#define AT91C_SPI1_RDR ( 0xFFFE4008 ) /* (SPI1) Receive Data Register */
-#define AT91C_SPI1_IDR ( 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
-#define AT91C_SPI1_SR ( 0xFFFE4010 ) /* (SPI1) Status Register */
-#define AT91C_SPI1_TDR ( 0xFFFE400C ) /* (SPI1) Transmit Data Register */
-#define AT91C_SPI1_CR ( 0xFFFE4000 ) /* (SPI1) Control Register */
-#define AT91C_SPI1_CSR ( 0xFFFE4030 ) /* (SPI1) Chip Select Register */
-/* ========== Register definition for PDC_SPI0 peripheral ========== */
-#define AT91C_SPI0_PTCR ( 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
-#define AT91C_SPI0_TPR ( 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
-#define AT91C_SPI0_TCR ( 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
-#define AT91C_SPI0_RCR ( 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
-#define AT91C_SPI0_PTSR ( 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
-#define AT91C_SPI0_RNPR ( 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
-#define AT91C_SPI0_RPR ( 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
-#define AT91C_SPI0_TNCR ( 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
-#define AT91C_SPI0_RNCR ( 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
-#define AT91C_SPI0_TNPR ( 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
-/* ========== Register definition for SPI0 peripheral ========== */
-#define AT91C_SPI0_IER ( 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
-#define AT91C_SPI0_SR ( 0xFFFE0010 ) /* (SPI0) Status Register */
-#define AT91C_SPI0_IDR ( 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
-#define AT91C_SPI0_CR ( 0xFFFE0000 ) /* (SPI0) Control Register */
-#define AT91C_SPI0_MR ( 0xFFFE0004 ) /* (SPI0) Mode Register */
-#define AT91C_SPI0_IMR ( 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
-#define AT91C_SPI0_TDR ( 0xFFFE000C ) /* (SPI0) Transmit Data Register */
-#define AT91C_SPI0_RDR ( 0xFFFE0008 ) /* (SPI0) Receive Data Register */
-#define AT91C_SPI0_CSR ( 0xFFFE0030 ) /* (SPI0) Chip Select Register */
-/* ========== Register definition for PDC_US1 peripheral ========== */
-#define AT91C_US1_RNCR ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
-#define AT91C_US1_PTCR ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
-#define AT91C_US1_TCR ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
-#define AT91C_US1_PTSR ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
-#define AT91C_US1_TNPR ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
-#define AT91C_US1_RCR ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
-#define AT91C_US1_RNPR ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
-#define AT91C_US1_RPR ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
-#define AT91C_US1_TNCR ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
-#define AT91C_US1_TPR ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
-/* ========== Register definition for US1 peripheral ========== */
-#define AT91C_US1_IF ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
-#define AT91C_US1_NER ( 0xFFFC4044 ) /* (US1) Nb Errors Register */
-#define AT91C_US1_RTOR ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
-#define AT91C_US1_CSR ( 0xFFFC4014 ) /* (US1) Channel Status Register */
-#define AT91C_US1_IDR ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */
-#define AT91C_US1_IER ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
-#define AT91C_US1_THR ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */
-#define AT91C_US1_TTGR ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
-#define AT91C_US1_RHR ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */
-#define AT91C_US1_BRGR ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
-#define AT91C_US1_IMR ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
-#define AT91C_US1_FIDI ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
-#define AT91C_US1_CR ( 0xFFFC4000 ) /* (US1) Control Register */
-#define AT91C_US1_MR ( 0xFFFC4004 ) /* (US1) Mode Register */
-/* ========== Register definition for PDC_US0 peripheral ========== */
-#define AT91C_US0_TNPR ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
-#define AT91C_US0_RNPR ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
-#define AT91C_US0_TCR ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
-#define AT91C_US0_PTCR ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
-#define AT91C_US0_PTSR ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
-#define AT91C_US0_TNCR ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
-#define AT91C_US0_TPR ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
-#define AT91C_US0_RCR ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
-#define AT91C_US0_RPR ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
-#define AT91C_US0_RNCR ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
-/* ========== Register definition for US0 peripheral ========== */
-#define AT91C_US0_BRGR ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
-#define AT91C_US0_NER ( 0xFFFC0044 ) /* (US0) Nb Errors Register */
-#define AT91C_US0_CR ( 0xFFFC0000 ) /* (US0) Control Register */
-#define AT91C_US0_IMR ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
-#define AT91C_US0_FIDI ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
-#define AT91C_US0_TTGR ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
-#define AT91C_US0_MR ( 0xFFFC0004 ) /* (US0) Mode Register */
-#define AT91C_US0_RTOR ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
-#define AT91C_US0_CSR ( 0xFFFC0014 ) /* (US0) Channel Status Register */
-#define AT91C_US0_RHR ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */
-#define AT91C_US0_IDR ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */
-#define AT91C_US0_THR ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */
-#define AT91C_US0_IF ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
-#define AT91C_US0_IER ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
-/* ========== Register definition for PDC_SSC peripheral ========== */
-#define AT91C_SSC_TNCR ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
-#define AT91C_SSC_RPR ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
-#define AT91C_SSC_RNCR ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
-#define AT91C_SSC_TPR ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
-#define AT91C_SSC_PTCR ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
-#define AT91C_SSC_TCR ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
-#define AT91C_SSC_RCR ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
-#define AT91C_SSC_RNPR ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
-#define AT91C_SSC_TNPR ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
-#define AT91C_SSC_PTSR ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
-/* ========== Register definition for SSC peripheral ========== */
-#define AT91C_SSC_RHR ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */
-#define AT91C_SSC_RSHR ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
-#define AT91C_SSC_TFMR ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
-#define AT91C_SSC_IDR ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
-#define AT91C_SSC_THR ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
-#define AT91C_SSC_RCMR ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
-#define AT91C_SSC_IER ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
-#define AT91C_SSC_TSHR ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
-#define AT91C_SSC_SR ( 0xFFFD4040 ) /* (SSC) Status Register */
-#define AT91C_SSC_CMR ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */
-#define AT91C_SSC_TCMR ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
-#define AT91C_SSC_CR ( 0xFFFD4000 ) /* (SSC) Control Register */
-#define AT91C_SSC_IMR ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
-#define AT91C_SSC_RFMR ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
-/* ========== Register definition for TWI peripheral ========== */
-#define AT91C_TWI_IER ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
-#define AT91C_TWI_CR ( 0xFFFB8000 ) /* (TWI) Control Register */
-#define AT91C_TWI_SR ( 0xFFFB8020 ) /* (TWI) Status Register */
-#define AT91C_TWI_IMR ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
-#define AT91C_TWI_THR ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
-#define AT91C_TWI_IDR ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
-#define AT91C_TWI_IADR ( 0xFFFB800C ) /* (TWI) Internal Address Register */
-#define AT91C_TWI_MMR ( 0xFFFB8004 ) /* (TWI) Master Mode Register */
-#define AT91C_TWI_CWGR ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
-#define AT91C_TWI_RHR ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */
-/* ========== Register definition for PWMC_CH3 peripheral ========== */
-#define AT91C_PWMC_CH3_CUPDR ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
-#define AT91C_PWMC_CH3_Reserved ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
-#define AT91C_PWMC_CH3_CPRDR ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
-#define AT91C_PWMC_CH3_CDTYR ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH3_CCNTR ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
-#define AT91C_PWMC_CH3_CMR ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
-/* ========== Register definition for PWMC_CH2 peripheral ========== */
-#define AT91C_PWMC_CH2_Reserved ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
-#define AT91C_PWMC_CH2_CMR ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
-#define AT91C_PWMC_CH2_CCNTR ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
-#define AT91C_PWMC_CH2_CPRDR ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
-#define AT91C_PWMC_CH2_CUPDR ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
-#define AT91C_PWMC_CH2_CDTYR ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
-/* ========== Register definition for PWMC_CH1 peripheral ========== */
-#define AT91C_PWMC_CH1_Reserved ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
-#define AT91C_PWMC_CH1_CUPDR ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
-#define AT91C_PWMC_CH1_CPRDR ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
-#define AT91C_PWMC_CH1_CCNTR ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
-#define AT91C_PWMC_CH1_CDTYR ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH1_CMR ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
-/* ========== Register definition for PWMC_CH0 peripheral ========== */
-#define AT91C_PWMC_CH0_Reserved ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
-#define AT91C_PWMC_CH0_CPRDR ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
-#define AT91C_PWMC_CH0_CDTYR ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
-#define AT91C_PWMC_CH0_CMR ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
-#define AT91C_PWMC_CH0_CUPDR ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
-#define AT91C_PWMC_CH0_CCNTR ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
-/* ========== Register definition for PWMC peripheral ========== */
-#define AT91C_PWMC_IDR ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
-#define AT91C_PWMC_DIS ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
-#define AT91C_PWMC_IER ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
-#define AT91C_PWMC_VR ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
-#define AT91C_PWMC_ISR ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
-#define AT91C_PWMC_SR ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
-#define AT91C_PWMC_IMR ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
-#define AT91C_PWMC_MR ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
-#define AT91C_PWMC_ENA ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
-/* ========== Register definition for UDP peripheral ========== */
-#define AT91C_UDP_IMR ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
-#define AT91C_UDP_FADDR ( 0xFFFB0008 ) /* (UDP) Function Address Register */
-#define AT91C_UDP_NUM ( 0xFFFB0000 ) /* (UDP) Frame Number Register */
-#define AT91C_UDP_FDR ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
-#define AT91C_UDP_ISR ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */
-#define AT91C_UDP_CSR ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
-#define AT91C_UDP_IDR ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
-#define AT91C_UDP_ICR ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
-#define AT91C_UDP_RSTEP ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
-#define AT91C_UDP_TXVC ( 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
-#define AT91C_UDP_GLBSTATE ( 0xFFFB0004 ) /* (UDP) Global State Register */
-#define AT91C_UDP_IER ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
-/* ========== Register definition for TC0 peripheral ========== */
-#define AT91C_TC0_SR ( 0xFFFA0020 ) /* (TC0) Status Register */
-#define AT91C_TC0_RC ( 0xFFFA001C ) /* (TC0) Register C */
-#define AT91C_TC0_RB ( 0xFFFA0018 ) /* (TC0) Register B */
-#define AT91C_TC0_CCR ( 0xFFFA0000 ) /* (TC0) Channel Control Register */
-#define AT91C_TC0_CMR ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC0_IER ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
-#define AT91C_TC0_RA ( 0xFFFA0014 ) /* (TC0) Register A */
-#define AT91C_TC0_IDR ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
-#define AT91C_TC0_CV ( 0xFFFA0010 ) /* (TC0) Counter Value */
-#define AT91C_TC0_IMR ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
-/* ========== Register definition for TC1 peripheral ========== */
-#define AT91C_TC1_RB ( 0xFFFA0058 ) /* (TC1) Register B */
-#define AT91C_TC1_CCR ( 0xFFFA0040 ) /* (TC1) Channel Control Register */
-#define AT91C_TC1_IER ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
-#define AT91C_TC1_IDR ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
-#define AT91C_TC1_SR ( 0xFFFA0060 ) /* (TC1) Status Register */
-#define AT91C_TC1_CMR ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC1_RA ( 0xFFFA0054 ) /* (TC1) Register A */
-#define AT91C_TC1_RC ( 0xFFFA005C ) /* (TC1) Register C */
-#define AT91C_TC1_IMR ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
-#define AT91C_TC1_CV ( 0xFFFA0050 ) /* (TC1) Counter Value */
-/* ========== Register definition for TC2 peripheral ========== */
-#define AT91C_TC2_CMR ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC2_CCR ( 0xFFFA0080 ) /* (TC2) Channel Control Register */
-#define AT91C_TC2_CV ( 0xFFFA0090 ) /* (TC2) Counter Value */
-#define AT91C_TC2_RA ( 0xFFFA0094 ) /* (TC2) Register A */
-#define AT91C_TC2_RB ( 0xFFFA0098 ) /* (TC2) Register B */
-#define AT91C_TC2_IDR ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
-#define AT91C_TC2_IMR ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
-#define AT91C_TC2_RC ( 0xFFFA009C ) /* (TC2) Register C */
-#define AT91C_TC2_IER ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
-#define AT91C_TC2_SR ( 0xFFFA00A0 ) /* (TC2) Status Register */
-/* ========== Register definition for TCB peripheral ========== */
-#define AT91C_TCB_BMR ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
-#define AT91C_TCB_BCR ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
-/* ========== Register definition for CAN_MB0 peripheral ========== */
-#define AT91C_CAN_MB0_MDL ( 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
-#define AT91C_CAN_MB0_MAM ( 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB0_MCR ( 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
-#define AT91C_CAN_MB0_MID ( 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
-#define AT91C_CAN_MB0_MSR ( 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
-#define AT91C_CAN_MB0_MFID ( 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
-#define AT91C_CAN_MB0_MDH ( 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
-#define AT91C_CAN_MB0_MMR ( 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
-/* ========== Register definition for CAN_MB1 peripheral ========== */
-#define AT91C_CAN_MB1_MDL ( 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
-#define AT91C_CAN_MB1_MID ( 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
-#define AT91C_CAN_MB1_MMR ( 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
-#define AT91C_CAN_MB1_MSR ( 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
-#define AT91C_CAN_MB1_MAM ( 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB1_MDH ( 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
-#define AT91C_CAN_MB1_MCR ( 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
-#define AT91C_CAN_MB1_MFID ( 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
-/* ========== Register definition for CAN_MB2 peripheral ========== */
-#define AT91C_CAN_MB2_MCR ( 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
-#define AT91C_CAN_MB2_MDH ( 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
-#define AT91C_CAN_MB2_MID ( 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
-#define AT91C_CAN_MB2_MDL ( 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
-#define AT91C_CAN_MB2_MMR ( 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
-#define AT91C_CAN_MB2_MAM ( 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB2_MFID ( 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
-#define AT91C_CAN_MB2_MSR ( 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
-/* ========== Register definition for CAN_MB3 peripheral ========== */
-#define AT91C_CAN_MB3_MFID ( 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
-#define AT91C_CAN_MB3_MAM ( 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB3_MID ( 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
-#define AT91C_CAN_MB3_MCR ( 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
-#define AT91C_CAN_MB3_MMR ( 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
-#define AT91C_CAN_MB3_MSR ( 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
-#define AT91C_CAN_MB3_MDL ( 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
-#define AT91C_CAN_MB3_MDH ( 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
-/* ========== Register definition for CAN_MB4 peripheral ========== */
-#define AT91C_CAN_MB4_MID ( 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
-#define AT91C_CAN_MB4_MMR ( 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
-#define AT91C_CAN_MB4_MDH ( 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
-#define AT91C_CAN_MB4_MFID ( 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
-#define AT91C_CAN_MB4_MSR ( 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
-#define AT91C_CAN_MB4_MCR ( 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
-#define AT91C_CAN_MB4_MDL ( 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
-#define AT91C_CAN_MB4_MAM ( 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB5 peripheral ========== */
-#define AT91C_CAN_MB5_MSR ( 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
-#define AT91C_CAN_MB5_MCR ( 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
-#define AT91C_CAN_MB5_MFID ( 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
-#define AT91C_CAN_MB5_MDH ( 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
-#define AT91C_CAN_MB5_MID ( 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
-#define AT91C_CAN_MB5_MMR ( 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
-#define AT91C_CAN_MB5_MDL ( 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
-#define AT91C_CAN_MB5_MAM ( 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
-/* ========== Register definition for CAN_MB6 peripheral ========== */
-#define AT91C_CAN_MB6_MFID ( 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
-#define AT91C_CAN_MB6_MID ( 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
-#define AT91C_CAN_MB6_MAM ( 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB6_MSR ( 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
-#define AT91C_CAN_MB6_MDL ( 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
-#define AT91C_CAN_MB6_MCR ( 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
-#define AT91C_CAN_MB6_MDH ( 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
-#define AT91C_CAN_MB6_MMR ( 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
-/* ========== Register definition for CAN_MB7 peripheral ========== */
-#define AT91C_CAN_MB7_MCR ( 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
-#define AT91C_CAN_MB7_MDH ( 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
-#define AT91C_CAN_MB7_MFID ( 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
-#define AT91C_CAN_MB7_MDL ( 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
-#define AT91C_CAN_MB7_MID ( 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
-#define AT91C_CAN_MB7_MMR ( 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
-#define AT91C_CAN_MB7_MAM ( 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
-#define AT91C_CAN_MB7_MSR ( 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
-/* ========== Register definition for CAN peripheral ========== */
-#define AT91C_CAN_TCR ( 0xFFFD0024 ) /* (CAN) Transfer Command Register */
-#define AT91C_CAN_IMR ( 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
-#define AT91C_CAN_IER ( 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
-#define AT91C_CAN_ECR ( 0xFFFD0020 ) /* (CAN) Error Counter Register */
-#define AT91C_CAN_TIMESTP ( 0xFFFD001C ) /* (CAN) Time Stamp Register */
-#define AT91C_CAN_MR ( 0xFFFD0000 ) /* (CAN) Mode Register */
-#define AT91C_CAN_IDR ( 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
-#define AT91C_CAN_ACR ( 0xFFFD0028 ) /* (CAN) Abort Command Register */
-#define AT91C_CAN_TIM ( 0xFFFD0018 ) /* (CAN) Timer Register */
-#define AT91C_CAN_SR ( 0xFFFD0010 ) /* (CAN) Status Register */
-#define AT91C_CAN_BR ( 0xFFFD0014 ) /* (CAN) Baudrate Register */
-#define AT91C_CAN_VR ( 0xFFFD00FC ) /* (CAN) Version Register */
-/* ========== Register definition for EMAC peripheral ========== */
-#define AT91C_EMAC_ISR ( 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
-#define AT91C_EMAC_SA4H ( 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
-#define AT91C_EMAC_SA1L ( 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
-#define AT91C_EMAC_ELE ( 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
-#define AT91C_EMAC_LCOL ( 0xFFFDC05C ) /* (EMAC) Late Collision Register */
-#define AT91C_EMAC_RLE ( 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
-#define AT91C_EMAC_WOL ( 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
-#define AT91C_EMAC_DTF ( 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
-#define AT91C_EMAC_TUND ( 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
-#define AT91C_EMAC_NCR ( 0xFFFDC000 ) /* (EMAC) Network Control Register */
-#define AT91C_EMAC_SA4L ( 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
-#define AT91C_EMAC_RSR ( 0xFFFDC020 ) /* (EMAC) Receive Status Register */
-#define AT91C_EMAC_SA3L ( 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
-#define AT91C_EMAC_TSR ( 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
-#define AT91C_EMAC_IDR ( 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
-#define AT91C_EMAC_RSE ( 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
-#define AT91C_EMAC_ECOL ( 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
-#define AT91C_EMAC_TID ( 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
-#define AT91C_EMAC_HRB ( 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
-#define AT91C_EMAC_TBQP ( 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
-#define AT91C_EMAC_USRIO ( 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
-#define AT91C_EMAC_PTR ( 0xFFFDC038 ) /* (EMAC) Pause Time Register */
-#define AT91C_EMAC_SA2H ( 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
-#define AT91C_EMAC_ROV ( 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
-#define AT91C_EMAC_ALE ( 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
-#define AT91C_EMAC_RJA ( 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
-#define AT91C_EMAC_RBQP ( 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
-#define AT91C_EMAC_TPF ( 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
-#define AT91C_EMAC_NCFGR ( 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
-#define AT91C_EMAC_HRT ( 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
-#define AT91C_EMAC_USF ( 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
-#define AT91C_EMAC_FCSE ( 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
-#define AT91C_EMAC_TPQ ( 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
-#define AT91C_EMAC_MAN ( 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
-#define AT91C_EMAC_FTO ( 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
-#define AT91C_EMAC_REV ( 0xFFFDC0FC ) /* (EMAC) Revision Register */
-#define AT91C_EMAC_IMR ( 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
-#define AT91C_EMAC_SCF ( 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
-#define AT91C_EMAC_PFR ( 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
-#define AT91C_EMAC_MCF ( 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
-#define AT91C_EMAC_NSR ( 0xFFFDC008 ) /* (EMAC) Network Status Register */
-#define AT91C_EMAC_SA2L ( 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
-#define AT91C_EMAC_FRO ( 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
-#define AT91C_EMAC_IER ( 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
-#define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
-#define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
-#define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
-#define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
-/* ========== Register definition for PDC_ADC peripheral ========== */
-#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
-#define AT91C_ADC_PTCR ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
-#define AT91C_ADC_TNPR ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
-#define AT91C_ADC_TNCR ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
-#define AT91C_ADC_RNPR ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
-#define AT91C_ADC_RNCR ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
-#define AT91C_ADC_RPR ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
-#define AT91C_ADC_TCR ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
-#define AT91C_ADC_TPR ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
-#define AT91C_ADC_RCR ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
-/* ========== Register definition for ADC peripheral ========== */
-#define AT91C_ADC_CDR2 ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
-#define AT91C_ADC_CDR3 ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
-#define AT91C_ADC_CDR0 ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
-#define AT91C_ADC_CDR5 ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
-#define AT91C_ADC_CHDR ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
-#define AT91C_ADC_SR ( 0xFFFD801C ) /* (ADC) ADC Status Register */
-#define AT91C_ADC_CDR4 ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
-#define AT91C_ADC_CDR1 ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
-#define AT91C_ADC_LCDR ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
-#define AT91C_ADC_IDR ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
-#define AT91C_ADC_CR ( 0xFFFD8000 ) /* (ADC) ADC Control Register */
-#define AT91C_ADC_CDR7 ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
-#define AT91C_ADC_CDR6 ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
-#define AT91C_ADC_IER ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
-#define AT91C_ADC_CHER ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
-#define AT91C_ADC_CHSR ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
-#define AT91C_ADC_MR ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */
-#define AT91C_ADC_IMR ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
-/* ========== Register definition for PDC_AES peripheral ========== */
-#define AT91C_AES_TPR ( 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
-#define AT91C_AES_PTCR ( 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
-#define AT91C_AES_RNPR ( 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
-#define AT91C_AES_TNCR ( 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
-#define AT91C_AES_TCR ( 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
-#define AT91C_AES_RCR ( 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
-#define AT91C_AES_RNCR ( 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
-#define AT91C_AES_TNPR ( 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
-#define AT91C_AES_RPR ( 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
-#define AT91C_AES_PTSR ( 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
-/* ========== Register definition for AES peripheral ========== */
-#define AT91C_AES_IVxR ( 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
-#define AT91C_AES_MR ( 0xFFFA4004 ) /* (AES) Mode Register */
-#define AT91C_AES_VR ( 0xFFFA40FC ) /* (AES) AES Version Register */
-#define AT91C_AES_ODATAxR ( 0xFFFA4050 ) /* (AES) Output Data x Register */
-#define AT91C_AES_IDATAxR ( 0xFFFA4040 ) /* (AES) Input Data x Register */
-#define AT91C_AES_CR ( 0xFFFA4000 ) /* (AES) Control Register */
-#define AT91C_AES_IDR ( 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
-#define AT91C_AES_IMR ( 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
-#define AT91C_AES_IER ( 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
-#define AT91C_AES_KEYWxR ( 0xFFFA4020 ) /* (AES) Key Word x Register */
-#define AT91C_AES_ISR ( 0xFFFA401C ) /* (AES) Interrupt Status Register */
-/* ========== Register definition for PDC_TDES peripheral ========== */
-#define AT91C_TDES_RNCR ( 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
-#define AT91C_TDES_TCR ( 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
-#define AT91C_TDES_RCR ( 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
-#define AT91C_TDES_TNPR ( 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
-#define AT91C_TDES_RNPR ( 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
-#define AT91C_TDES_RPR ( 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
-#define AT91C_TDES_TNCR ( 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
-#define AT91C_TDES_TPR ( 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
-#define AT91C_TDES_PTSR ( 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
-#define AT91C_TDES_PTCR ( 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
-/* ========== Register definition for TDES peripheral ========== */
-#define AT91C_TDES_KEY2WxR ( 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
-#define AT91C_TDES_KEY3WxR ( 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
-#define AT91C_TDES_IDR ( 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
-#define AT91C_TDES_VR ( 0xFFFA80FC ) /* (TDES) TDES Version Register */
-#define AT91C_TDES_IVxR ( 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
-#define AT91C_TDES_ODATAxR ( 0xFFFA8050 ) /* (TDES) Output Data x Register */
-#define AT91C_TDES_IMR ( 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
-#define AT91C_TDES_MR ( 0xFFFA8004 ) /* (TDES) Mode Register */
-#define AT91C_TDES_CR ( 0xFFFA8000 ) /* (TDES) Control Register */
-#define AT91C_TDES_IER ( 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
-#define AT91C_TDES_ISR ( 0xFFFA801C ) /* (TDES) Interrupt Status Register */
-#define AT91C_TDES_IDATAxR ( 0xFFFA8040 ) /* (TDES) Input Data x Register */
-#define AT91C_TDES_KEY1WxR ( 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ==========
+#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ==========
+#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ==========
+#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ==========
+#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ==========
+#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ==========
+#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ==========
+#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ==========
+#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ==========
+#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ==========
+#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ==========
+#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ==========
+#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ==========
+#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ==========
+#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ==========
+#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ==========
+#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ==========
+#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ==========
+#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register
-/* ***************************************************************************** */
-/* PIO DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_PIO_PA0 ( 1 << 0 ) /* Pin Controlled by PA0 */
-#define AT91C_PA0_RXD0 ( AT91C_PIO_PA0 ) /* USART 0 Receive Data */
-#define AT91C_PIO_PA1 ( 1 << 1 ) /* Pin Controlled by PA1 */
-#define AT91C_PA1_TXD0 ( AT91C_PIO_PA1 ) /* USART 0 Transmit Data */
-#define AT91C_PIO_PA10 ( 1 << 10 ) /* Pin Controlled by PA10 */
-#define AT91C_PA10_TWD ( AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */
-#define AT91C_PIO_PA11 ( 1 << 11 ) /* Pin Controlled by PA11 */
-#define AT91C_PA11_TWCK ( AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */
-#define AT91C_PIO_PA12 ( 1 << 12 ) /* Pin Controlled by PA12 */
-#define AT91C_PA12_NPCS00 ( AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA13 ( 1 << 13 ) /* Pin Controlled by PA13 */
-#define AT91C_PA13_NPCS01 ( AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PA13_PCK1 ( AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PA14 ( 1 << 14 ) /* Pin Controlled by PA14 */
-#define AT91C_PA14_NPCS02 ( AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PA14_IRQ1 ( AT91C_PIO_PA14 ) /* External Interrupt 1 */
-#define AT91C_PIO_PA15 ( 1 << 15 ) /* Pin Controlled by PA15 */
-#define AT91C_PA15_NPCS03 ( AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PA15_TCLK2 ( AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */
-#define AT91C_PIO_PA16 ( 1 << 16 ) /* Pin Controlled by PA16 */
-#define AT91C_PA16_MISO0 ( AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */
-#define AT91C_PIO_PA17 ( 1 << 17 ) /* Pin Controlled by PA17 */
-#define AT91C_PA17_MOSI0 ( AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */
-#define AT91C_PIO_PA18 ( 1 << 18 ) /* Pin Controlled by PA18 */
-#define AT91C_PA18_SPCK0 ( AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */
-#define AT91C_PIO_PA19 ( 1 << 19 ) /* Pin Controlled by PA19 */
-#define AT91C_PA19_CANRX ( AT91C_PIO_PA19 ) /* CAN Receive */
-#define AT91C_PIO_PA2 ( 1 << 2 ) /* Pin Controlled by PA2 */
-#define AT91C_PA2_SCK0 ( AT91C_PIO_PA2 ) /* USART 0 Serial Clock */
-#define AT91C_PA2_NPCS11 ( AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA20 ( 1 << 20 ) /* Pin Controlled by PA20 */
-#define AT91C_PA20_CANTX ( AT91C_PIO_PA20 ) /* CAN Transmit */
-#define AT91C_PIO_PA21 ( 1 << 21 ) /* Pin Controlled by PA21 */
-#define AT91C_PA21_TF ( AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */
-#define AT91C_PA21_NPCS10 ( AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */
-#define AT91C_PIO_PA22 ( 1 << 22 ) /* Pin Controlled by PA22 */
-#define AT91C_PA22_TK ( AT91C_PIO_PA22 ) /* SSC Transmit Clock */
-#define AT91C_PA22_SPCK1 ( AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */
-#define AT91C_PIO_PA23 ( 1 << 23 ) /* Pin Controlled by PA23 */
-#define AT91C_PA23_TD ( AT91C_PIO_PA23 ) /* SSC Transmit data */
-#define AT91C_PA23_MOSI1 ( AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */
-#define AT91C_PIO_PA24 ( 1 << 24 ) /* Pin Controlled by PA24 */
-#define AT91C_PA24_RD ( AT91C_PIO_PA24 ) /* SSC Receive Data */
-#define AT91C_PA24_MISO1 ( AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */
-#define AT91C_PIO_PA25 ( 1 << 25 ) /* Pin Controlled by PA25 */
-#define AT91C_PA25_RK ( AT91C_PIO_PA25 ) /* SSC Receive Clock */
-#define AT91C_PA25_NPCS11 ( AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA26 ( 1 << 26 ) /* Pin Controlled by PA26 */
-#define AT91C_PA26_RF ( AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */
-#define AT91C_PA26_NPCS12 ( AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA27 ( 1 << 27 ) /* Pin Controlled by PA27 */
-#define AT91C_PA27_DRXD ( AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */
-#define AT91C_PA27_PCK3 ( AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */
-#define AT91C_PIO_PA28 ( 1 << 28 ) /* Pin Controlled by PA28 */
-#define AT91C_PA28_DTXD ( AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA29 ( 1 << 29 ) /* Pin Controlled by PA29 */
-#define AT91C_PA29_FIQ ( AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */
-#define AT91C_PA29_NPCS13 ( AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA3 ( 1 << 3 ) /* Pin Controlled by PA3 */
-#define AT91C_PA3_RTS0 ( AT91C_PIO_PA3 ) /* USART 0 Ready To Send */
-#define AT91C_PA3_NPCS12 ( AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA30 ( 1 << 30 ) /* Pin Controlled by PA30 */
-#define AT91C_PA30_IRQ0 ( AT91C_PIO_PA30 ) /* External Interrupt 0 */
-#define AT91C_PA30_PCK2 ( AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PA4 ( 1 << 4 ) /* Pin Controlled by PA4 */
-#define AT91C_PA4_CTS0 ( AT91C_PIO_PA4 ) /* USART 0 Clear To Send */
-#define AT91C_PA4_NPCS13 ( AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PA5 ( 1 << 5 ) /* Pin Controlled by PA5 */
-#define AT91C_PA5_RXD1 ( AT91C_PIO_PA5 ) /* USART 1 Receive Data */
-#define AT91C_PIO_PA6 ( 1 << 6 ) /* Pin Controlled by PA6 */
-#define AT91C_PA6_TXD1 ( AT91C_PIO_PA6 ) /* USART 1 Transmit Data */
-#define AT91C_PIO_PA7 ( 1 << 7 ) /* Pin Controlled by PA7 */
-#define AT91C_PA7_SCK1 ( AT91C_PIO_PA7 ) /* USART 1 Serial Clock */
-#define AT91C_PA7_NPCS01 ( AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PA8 ( 1 << 8 ) /* Pin Controlled by PA8 */
-#define AT91C_PA8_RTS1 ( AT91C_PIO_PA8 ) /* USART 1 Ready To Send */
-#define AT91C_PA8_NPCS02 ( AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PA9 ( 1 << 9 ) /* Pin Controlled by PA9 */
-#define AT91C_PA9_CTS1 ( AT91C_PIO_PA9 ) /* USART 1 Clear To Send */
-#define AT91C_PA9_NPCS03 ( AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB0 ( 1 << 0 ) /* Pin Controlled by PB0 */
-#define AT91C_PB0_ETXCK_EREFCK ( AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */
-#define AT91C_PB0_PCK0 ( AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB1 ( 1 << 1 ) /* Pin Controlled by PB1 */
-#define AT91C_PB1_ETXEN ( AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PB10 ( 1 << 10 ) /* Pin Controlled by PB10 */
-#define AT91C_PB10_ETX2 ( AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */
-#define AT91C_PB10_NPCS11 ( AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB11 ( 1 << 11 ) /* Pin Controlled by PB11 */
-#define AT91C_PB11_ETX3 ( AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */
-#define AT91C_PB11_NPCS12 ( AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB12 ( 1 << 12 ) /* Pin Controlled by PB12 */
-#define AT91C_PB12_ETXER ( AT91C_PIO_PB12 ) /* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PB12_TCLK0 ( AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */
-#define AT91C_PIO_PB13 ( 1 << 13 ) /* Pin Controlled by PB13 */
-#define AT91C_PB13_ERX2 ( AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */
-#define AT91C_PB13_NPCS01 ( AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */
-#define AT91C_PIO_PB14 ( 1 << 14 ) /* Pin Controlled by PB14 */
-#define AT91C_PB14_ERX3 ( AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */
-#define AT91C_PB14_NPCS02 ( AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */
-#define AT91C_PIO_PB15 ( 1 << 15 ) /* Pin Controlled by PB15 */
-#define AT91C_PB15_ERXDV ( AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16 ( 1 << 16 ) /* Pin Controlled by PB16 */
-#define AT91C_PB16_ECOL ( AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */
-#define AT91C_PB16_NPCS13 ( AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB17 ( 1 << 17 ) /* Pin Controlled by PB17 */
-#define AT91C_PB17_ERXCK ( AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */
-#define AT91C_PB17_NPCS03 ( AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */
-#define AT91C_PIO_PB18 ( 1 << 18 ) /* Pin Controlled by PB18 */
-#define AT91C_PB18_EF100 ( AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */
-#define AT91C_PB18_ADTRG ( AT91C_PIO_PB18 ) /* ADC External Trigger */
-#define AT91C_PIO_PB19 ( 1 << 19 ) /* Pin Controlled by PB19 */
-#define AT91C_PB19_PWM0 ( AT91C_PIO_PB19 ) /* PWM Channel 0 */
-#define AT91C_PB19_TCLK1 ( AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */
-#define AT91C_PIO_PB2 ( 1 << 2 ) /* Pin Controlled by PB2 */
-#define AT91C_PB2_ETX0 ( AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PB20 ( 1 << 20 ) /* Pin Controlled by PB20 */
-#define AT91C_PB20_PWM1 ( AT91C_PIO_PB20 ) /* PWM Channel 1 */
-#define AT91C_PB20_PCK0 ( AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */
-#define AT91C_PIO_PB21 ( 1 << 21 ) /* Pin Controlled by PB21 */
-#define AT91C_PB21_PWM2 ( AT91C_PIO_PB21 ) /* PWM Channel 2 */
-#define AT91C_PB21_PCK1 ( AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PIO_PB22 ( 1 << 22 ) /* Pin Controlled by PB22 */
-#define AT91C_PB22_PWM3 ( AT91C_PIO_PB22 ) /* PWM Channel 3 */
-#define AT91C_PB22_PCK2 ( AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PIO_PB23 ( 1 << 23 ) /* Pin Controlled by PB23 */
-#define AT91C_PB23_TIOA0 ( AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */
-#define AT91C_PB23_DCD1 ( AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */
-#define AT91C_PIO_PB24 ( 1 << 24 ) /* Pin Controlled by PB24 */
-#define AT91C_PB24_TIOB0 ( AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */
-#define AT91C_PB24_DSR1 ( AT91C_PIO_PB24 ) /* USART 1 Data Set ready */
-#define AT91C_PIO_PB25 ( 1 << 25 ) /* Pin Controlled by PB25 */
-#define AT91C_PB25_TIOA1 ( AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */
-#define AT91C_PB25_DTR1 ( AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */
-#define AT91C_PIO_PB26 ( 1 << 26 ) /* Pin Controlled by PB26 */
-#define AT91C_PB26_TIOB1 ( AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */
-#define AT91C_PB26_RI1 ( AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */
-#define AT91C_PIO_PB27 ( 1 << 27 ) /* Pin Controlled by PB27 */
-#define AT91C_PB27_TIOA2 ( AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */
-#define AT91C_PB27_PWM0 ( AT91C_PIO_PB27 ) /* PWM Channel 0 */
-#define AT91C_PIO_PB28 ( 1 << 28 ) /* Pin Controlled by PB28 */
-#define AT91C_PB28_TIOB2 ( AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */
-#define AT91C_PB28_PWM1 ( AT91C_PIO_PB28 ) /* PWM Channel 1 */
-#define AT91C_PIO_PB29 ( 1 << 29 ) /* Pin Controlled by PB29 */
-#define AT91C_PB29_PCK1 ( AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */
-#define AT91C_PB29_PWM2 ( AT91C_PIO_PB29 ) /* PWM Channel 2 */
-#define AT91C_PIO_PB3 ( 1 << 3 ) /* Pin Controlled by PB3 */
-#define AT91C_PB3_ETX1 ( AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PB30 ( 1 << 30 ) /* Pin Controlled by PB30 */
-#define AT91C_PB30_PCK2 ( AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */
-#define AT91C_PB30_PWM3 ( AT91C_PIO_PB30 ) /* PWM Channel 3 */
-#define AT91C_PIO_PB4 ( 1 << 4 ) /* Pin Controlled by PB4 */
-#define AT91C_PB4_ECRS_ECRSDV ( AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PB5 ( 1 << 5 ) /* Pin Controlled by PB5 */
-#define AT91C_PB5_ERX0 ( AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PB6 ( 1 << 6 ) /* Pin Controlled by PB6 */
-#define AT91C_PB6_ERX1 ( AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PB7 ( 1 << 7 ) /* Pin Controlled by PB7 */
-#define AT91C_PB7_ERXER ( AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */
-#define AT91C_PIO_PB8 ( 1 << 8 ) /* Pin Controlled by PB8 */
-#define AT91C_PB8_EMDC ( AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PB9 ( 1 << 9 ) /* Pin Controlled by PB9 */
-#define AT91C_PB9_EMDIO ( AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock
+#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data
+#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data
+#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock
+#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data
+#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send
+#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0
+#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send
+#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock
+#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send
+#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send
+#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input
+#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger
+#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0
+#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input
+#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1
+#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2
+#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3
+#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready
+#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready
+#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator
+#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0
+#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1
+#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2
+#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3
+#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error
+#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-/* ***************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_ID_FIQ ( 0 ) /* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS ( 1 ) /* System Peripheral */
-#define AT91C_ID_PIOA ( 2 ) /* Parallel IO Controller A */
-#define AT91C_ID_PIOB ( 3 ) /* Parallel IO Controller B */
-#define AT91C_ID_SPI0 ( 4 ) /* Serial Peripheral Interface 0 */
-#define AT91C_ID_SPI1 ( 5 ) /* Serial Peripheral Interface 1 */
-#define AT91C_ID_US0 ( 6 ) /* USART 0 */
-#define AT91C_ID_US1 ( 7 ) /* USART 1 */
-#define AT91C_ID_SSC ( 8 ) /* Serial Synchronous Controller */
-#define AT91C_ID_TWI ( 9 ) /* Two-Wire Interface */
-#define AT91C_ID_PWMC ( 10 ) /* PWM Controller */
-#define AT91C_ID_UDP ( 11 ) /* USB Device Port */
-#define AT91C_ID_TC0 ( 12 ) /* Timer Counter 0 */
-#define AT91C_ID_TC1 ( 13 ) /* Timer Counter 1 */
-#define AT91C_ID_TC2 ( 14 ) /* Timer Counter 2 */
-#define AT91C_ID_CAN ( 15 ) /* Control Area Network Controller */
-#define AT91C_ID_EMAC ( 16 ) /* Ethernet MAC */
-#define AT91C_ID_ADC ( 17 ) /* Analog-to-Digital Converter */
-#define AT91C_ID_AES ( 18 ) /* Advanced Encryption Standard 128-bit */
-#define AT91C_ID_TDES ( 19 ) /* Triple Data Encryption Standard */
-#define AT91C_ID_20_Reserved ( 20 ) /* Reserved */
-#define AT91C_ID_21_Reserved ( 21 ) /* Reserved */
-#define AT91C_ID_22_Reserved ( 22 ) /* Reserved */
-#define AT91C_ID_23_Reserved ( 23 ) /* Reserved */
-#define AT91C_ID_24_Reserved ( 24 ) /* Reserved */
-#define AT91C_ID_25_Reserved ( 25 ) /* Reserved */
-#define AT91C_ID_26_Reserved ( 26 ) /* Reserved */
-#define AT91C_ID_27_Reserved ( 27 ) /* Reserved */
-#define AT91C_ID_28_Reserved ( 28 ) /* Reserved */
-#define AT91C_ID_29_Reserved ( 29 ) /* Reserved */
-#define AT91C_ID_IRQ0 ( 30 ) /* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1 ( 31 ) /* Advanced Interrupt Controller (IRQ1) */
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ( 1) // System Peripheral
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0 ( 6) // USART 0
+#define AT91C_ID_US1 ( 7) // USART 1
+#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ( 9) // Two-Wire Interface
+#define AT91C_ID_PWMC (10) // PWM Controller
+#define AT91C_ID_UDP (11) // USB Device Port
+#define AT91C_ID_TC0 (12) // Timer Counter 0
+#define AT91C_ID_TC1 (13) // Timer Counter 1
+#define AT91C_ID_TC2 (14) // Timer Counter 2
+#define AT91C_ID_CAN (15) // Control Area Network Controller
+#define AT91C_ID_EMAC (16) // Ethernet MAC
+#define AT91C_ID_ADC (17) // Analog-to-Digital Converter
+#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES (19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved (20) // Reserved
+#define AT91C_ID_21_Reserved (21) // Reserved
+#define AT91C_ID_22_Reserved (22) // Reserved
+#define AT91C_ID_23_Reserved (23) // Reserved
+#define AT91C_ID_24_Reserved (24) // Reserved
+#define AT91C_ID_25_Reserved (25) // Reserved
+#define AT91C_ID_26_Reserved (26) // Reserved
+#define AT91C_ID_27_Reserved (27) // Reserved
+#define AT91C_ID_28_Reserved (28) // Reserved
+#define AT91C_ID_29_Reserved (29) // Reserved
+#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
-/* ***************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_BASE_SYS ( 0xFFFFF000 ) /* (SYS) Base Address */
-#define AT91C_BASE_AIC ( 0xFFFFF000 ) /* (AIC) Base Address */
-#define AT91C_BASE_PDC_DBGU ( 0xFFFFF300 ) /* (PDC_DBGU) Base Address */
-#define AT91C_BASE_DBGU ( 0xFFFFF200 ) /* (DBGU) Base Address */
-#define AT91C_BASE_PIOA ( 0xFFFFF400 ) /* (PIOA) Base Address */
-#define AT91C_BASE_PIOB ( 0xFFFFF600 ) /* (PIOB) Base Address */
-#define AT91C_BASE_CKGR ( 0xFFFFFC20 ) /* (CKGR) Base Address */
-#define AT91C_BASE_PMC ( 0xFFFFFC00 ) /* (PMC) Base Address */
-#define AT91C_BASE_RSTC ( 0xFFFFFD00 ) /* (RSTC) Base Address */
-#define AT91C_BASE_RTTC ( 0xFFFFFD20 ) /* (RTTC) Base Address */
-#define AT91C_BASE_PITC ( 0xFFFFFD30 ) /* (PITC) Base Address */
-#define AT91C_BASE_WDTC ( 0xFFFFFD40 ) /* (WDTC) Base Address */
-#define AT91C_BASE_VREG ( 0xFFFFFD60 ) /* (VREG) Base Address */
-#define AT91C_BASE_MC ( 0xFFFFFF00 ) /* (MC) Base Address */
-#define AT91C_BASE_PDC_SPI1 ( 0xFFFE4100 ) /* (PDC_SPI1) Base Address */
-#define AT91C_BASE_SPI1 ( 0xFFFE4000 ) /* (SPI1) Base Address */
-#define AT91C_BASE_PDC_SPI0 ( 0xFFFE0100 ) /* (PDC_SPI0) Base Address */
-#define AT91C_BASE_SPI0 ( 0xFFFE0000 ) /* (SPI0) Base Address */
-#define AT91C_BASE_PDC_US1 ( 0xFFFC4100 ) /* (PDC_US1) Base Address */
-#define AT91C_BASE_US1 ( 0xFFFC4000 ) /* (US1) Base Address */
-#define AT91C_BASE_PDC_US0 ( 0xFFFC0100 ) /* (PDC_US0) Base Address */
-#define AT91C_BASE_US0 ( 0xFFFC0000 ) /* (US0) Base Address */
-#define AT91C_BASE_PDC_SSC ( 0xFFFD4100 ) /* (PDC_SSC) Base Address */
-#define AT91C_BASE_SSC ( 0xFFFD4000 ) /* (SSC) Base Address */
-#define AT91C_BASE_TWI ( 0xFFFB8000 ) /* (TWI) Base Address */
-#define AT91C_BASE_PWMC_CH3 ( 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
-#define AT91C_BASE_PWMC_CH2 ( 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
-#define AT91C_BASE_PWMC_CH1 ( 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
-#define AT91C_BASE_PWMC_CH0 ( 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
-#define AT91C_BASE_PWMC ( 0xFFFCC000 ) /* (PWMC) Base Address */
-#define AT91C_BASE_UDP ( 0xFFFB0000 ) /* (UDP) Base Address */
-#define AT91C_BASE_TC0 ( 0xFFFA0000 ) /* (TC0) Base Address */
-#define AT91C_BASE_TC1 ( 0xFFFA0040 ) /* (TC1) Base Address */
-#define AT91C_BASE_TC2 ( 0xFFFA0080 ) /* (TC2) Base Address */
-#define AT91C_BASE_TCB ( 0xFFFA0000 ) /* (TCB) Base Address */
-#define AT91C_BASE_CAN_MB0 ( 0xFFFD0200 ) /* (CAN_MB0) Base Address */
-#define AT91C_BASE_CAN_MB1 ( 0xFFFD0220 ) /* (CAN_MB1) Base Address */
-#define AT91C_BASE_CAN_MB2 ( 0xFFFD0240 ) /* (CAN_MB2) Base Address */
-#define AT91C_BASE_CAN_MB3 ( 0xFFFD0260 ) /* (CAN_MB3) Base Address */
-#define AT91C_BASE_CAN_MB4 ( 0xFFFD0280 ) /* (CAN_MB4) Base Address */
-#define AT91C_BASE_CAN_MB5 ( 0xFFFD02A0 ) /* (CAN_MB5) Base Address */
-#define AT91C_BASE_CAN_MB6 ( 0xFFFD02C0 ) /* (CAN_MB6) Base Address */
-#define AT91C_BASE_CAN_MB7 ( 0xFFFD02E0 ) /* (CAN_MB7) Base Address */
-#define AT91C_BASE_CAN ( 0xFFFD0000 ) /* (CAN) Base Address */
-#define AT91C_BASE_EMAC ( 0xFFFDC000 ) /* (EMAC) Base Address */
-#define AT91C_BASE_PDC_ADC ( 0xFFFD8100 ) /* (PDC_ADC) Base Address */
-#define AT91C_BASE_ADC ( 0xFFFD8000 ) /* (ADC) Base Address */
-#define AT91C_BASE_PDC_AES ( 0xFFFA4100 ) /* (PDC_AES) Base Address */
-#define AT91C_BASE_AES ( 0xFFFA4000 ) /* (AES) Base Address */
-#define AT91C_BASE_PDC_TDES ( 0xFFFA8100 ) /* (PDC_TDES) Base Address */
-#define AT91C_BASE_TDES ( 0xFFFA8000 ) /* (TDES) Base Address */
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address
-/* ***************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
-/* ***************************************************************************** */
-#define AT91C_ISRAM ( 0x00200000 ) /* Internal SRAM base address */
-#define AT91C_ISRAM_SIZE ( 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */
-#define AT91C_IFLASH ( 0x00100000 ) /* Internal ROM base address */
-#define AT91C_IFLASH_SIZE ( 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH (0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE (0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+
diff --git a/portable/IAR/AtmelSAM7S64/ISR_Support.h b/portable/IAR/AtmelSAM7S64/ISR_Support.h
index 72f4b15..360fff6 100644
--- a/portable/IAR/AtmelSAM7S64/ISR_Support.h
+++ b/portable/IAR/AtmelSAM7S64/ISR_Support.h
@@ -1,123 +1,105 @@
-; /*
- * ; * FreeRTOS Kernel V10.3.1
- * ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * ; *
- * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * ; * this software and associated documentation files (the "Software"), to deal in
- * ; * the Software without restriction, including without limitation the rights to
- * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * ; * the Software, and to permit persons to whom the Software is furnished to do so,
- * ; * subject to the following conditions:
- * ; *
- * ; * The above copyright notice and this permission notice shall be included in all
- * ; * copies or substantial portions of the Software.
- * ; *
- * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * ; *
- * ; * http://www.FreeRTOS.org
- * ; * http://aws.amazon.com/freertos
- * ; *
- * ; * 1 tab == 4 spaces!
- * ; */
+;/*
+; * FreeRTOS Kernel V10.3.1
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
-EXTERN pxCurrentTCB
-EXTERN ulCriticalNesting
+ EXTERN pxCurrentTCB
+ EXTERN ulCriticalNesting
-;
-Context save and restore macro definitions
-;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
-;
-Push R0 as we are going to use the register.
- STMDB SP !, { R0 }
+ ; Push R0 as we are going to use the register.
+ STMDB SP!, {R0}
-;
-Set R0 to point to the task stack pointer.
- STMDB SP, { SP } ^
-NOP
-SUB SP, SP, # 4
-LDMIA SP !, { R0 }
+ ; Set R0 to point to the task stack pointer.
+ STMDB SP, {SP}^
+ NOP
+ SUB SP, SP, #4
+ LDMIA SP!, {R0}
-;
-Push the return address onto the stack.
- STMDB R0 !, { LR }
+ ; Push the return address onto the stack.
+ STMDB R0!, {LR}
-;
+ ; Now we have saved LR we can use it instead of R0.
+ MOV LR, R0
-Now we have saved LR we can use it instead of R0.
- MOV LR, R0
+ ; Pop R0 so we can save it onto the system mode stack.
+ LDMIA SP!, {R0}
-;
-Pop R0 so we can save it onto the system mode stack.
- LDMIA SP !, { R0 }
+ ; Push all the system mode registers onto the task stack.
+ STMDB LR, {R0-LR}^
+ NOP
+ SUB LR, LR, #60
-;
-Push all the system mode registers onto the task stack.
- STMDB LR, { R0 - LR } ^
-NOP
-SUB LR, LR, # 60
+ ; Push the SPSR onto the task stack.
+ MRS R0, SPSR
+ STMDB LR!, {R0}
-;
-Push the SPSR onto the task stack.
- MRS R0, SPSR
-STMDB LR !, { R0 }
+ LDR R0, =ulCriticalNesting
+ LDR R0, [R0]
+ STMDB LR!, {R0}
-LDR R0, = ulCriticalNesting
- LDR R0, [ R0 ]
-STMDB LR !, { R0 }
+ ; Store the new top of stack for the task.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ STR LR, [R0]
-;
-Store the new top of stack for the task.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-STR LR, [ R0 ]
-
-ENDM
+ ENDM
portRESTORE_CONTEXT MACRO
-;
-Set the LR to the task stack.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-LDR LR, [ R0 ]
+ ; Set the LR to the task stack.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ LDR LR, [R0]
-;
-The critical nesting depth is the first item on the stack.
- ;
-Load it into the ulCriticalNesting variable.
- LDR R0, = ulCriticalNesting
- LDMFD LR !, { R1 }
-STR R1, [ R0 ]
+ ; The critical nesting depth is the first item on the stack.
+ ; Load it into the ulCriticalNesting variable.
+ LDR R0, =ulCriticalNesting
+ LDMFD LR!, {R1}
+ STR R1, [R0]
-;
-Get the SPSR from the stack.
- LDMFD LR !, { R0 }
-MSR SPSR_cxsf, R0
+ ; Get the SPSR from the stack.
+ LDMFD LR!, {R0}
+ MSR SPSR_cxsf, R0
-;
-Restore all system mode registers for the task.
- LDMFD LR, { R0 - R14 } ^
-NOP
+ ; Restore all system mode registers for the task.
+ LDMFD LR, {R0-R14}^
+ NOP
-;
-Restore the return address.
- LDR LR, [ LR, # + 60 ]
+ ; Restore the return address.
+ LDR LR, [LR, #+60]
-;
+ ; And return - correcting the offset in the LR to obtain the
+ ; correct address.
+ SUBS PC, LR, #4
-And return -correcting the offset in the LR to obtain the
-;
+ ENDM
-correct address.
- SUBS PC, LR, # 4
-
-ENDM
diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
index eaa2301..9d012c4 100644
--- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
+++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
@@ -1,3113 +1,3265 @@
-/**---------------------------------------------------------------------------- */
-/** ATMEL Microcontroller Software Support - ROUSSET - */
-/**---------------------------------------------------------------------------- */
-/** The software is delivered "AS IS" without warranty or condition of any */
-/** kind, either express, implied or statutory. This includes without */
-/** limitation any warranty or condition with respect to merchantability or */
-/** fitness for any particular purpose, or against the infringements of */
-/** intellectual property rights of others. */
-/**---------------------------------------------------------------------------- */
-/** File Name : lib_AT91SAM7S64.h */
-/** Object : AT91SAM7S64 inlined functions */
-/** Generated : AT91 SW Application Group 07/16/2004 (07:43:09) */
-/** */
-/** CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// */
-/** CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// */
-/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
-/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
-/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// */
-/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
-/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
-/** CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */
-/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// */
-/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
-/** CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// */
-/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
-/** CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// */
-/** CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// */
-/**---------------------------------------------------------------------------- */
+//*----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name : lib_AT91SAM7S64.h
+//* Object : AT91SAM7S64 inlined functions
+//* Generated : AT91 SW Application Group 07/16/2004 (07:43:09)
+//*
+//* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004//
+//* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003//
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003//
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003//
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003//
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003//
+//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002//
+//*----------------------------------------------------------------------------
#ifndef lib_AT91SAM7S64_H
#define lib_AT91SAM7S64_H
/* *****************************************************************************
-* SOFTWARE API FOR MC
-***************************************************************************** */
+ SOFTWARE API FOR MC
+ ***************************************************************************** */
-#define AT91C_MC_CORRECT_KEY ( ( unsigned int ) 0x5A << 24 ) /* (MC) Correct Protect Key */
+#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_Remap */
-/** \brief Make Remap */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_Remap( void ) /* */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void) //
{
- AT91PS_MC pMC = ( AT91PS_MC ) AT91C_BASE_MC;
-
+ AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+
pMC->MC_RCR = AT91C_MC_RCB;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_CfgModeReg */
-/** \brief Configure the EFC Mode Register of the MC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, /* pointer to a MC controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+ AT91PS_MC pMC, // pointer to a MC controller
+ unsigned int mode) // mode register
{
- /* Write to the FMR register */
- pMC->MC_FMR = mode;
+ // Write to the FMR register
+ pMC->MC_FMR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_GetModeReg */
-/** \brief Return MC EFC Mode Regsiter */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+ AT91PS_MC pMC) // pointer to a MC controller
{
- return pMC->MC_FMR;
+ return pMC->MC_FMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_ComputeFMCN */
-/** \brief Return MC EFC Mode Regsiter */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+ int master_clock) // master clock in Hz
{
- return( master_clock / 1000000 + 2 );
+ return (master_clock/1000000 +2);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_PerformCmd */
-/** \brief Perform EFC Command */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_EFC_PerformCmd( AT91PS_MC pMC, /* pointer to a MC controller */
- unsigned int transfer_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+ AT91PS_MC pMC, // pointer to a MC controller
+ unsigned int transfer_cmd)
{
- pMC->MC_FCR = transfer_cmd;
+ pMC->MC_FCR = transfer_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_GetStatus */
-/** \brief Return MC EFC Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_GetStatus( AT91PS_MC pMC ) /* pointer to a MC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+ AT91PS_MC pMC) // pointer to a MC controller
{
- return pMC->MC_FSR;
+ return pMC->MC_FSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_IsInterruptMasked */
-/** \brief Test if EFC MC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( AT91PS_MC pMC, /* \arg pointer to a MC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+ AT91PS_MC pMC, // \arg pointer to a MC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_MC_EFC_GetModeReg( pMC ) & flag );
+ return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_IsInterruptSet */
-/** \brief Test if EFC MC Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, /* \arg pointer to a MC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+ AT91PS_MC pMC, // \arg pointer to a MC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_MC_EFC_GetStatus( pMC ) & flag );
+ return (AT91F_MC_EFC_GetStatus(pMC) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR PDC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetNextRx */
-/** \brief Set the next receive transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be received */
- unsigned int bytes ) /* \arg number of bytes to be received */
+ SOFTWARE API FOR PDC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
{
- pPDC->PDC_RNPR = ( unsigned int ) address;
- pPDC->PDC_RNCR = bytes;
+ pPDC->PDC_RNPR = (unsigned int) address;
+ pPDC->PDC_RNCR = bytes;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetNextTx */
-/** \brief Set the next transmit transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be transmitted */
- unsigned int bytes ) /* \arg number of bytes to be transmitted */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
{
- pPDC->PDC_TNPR = ( unsigned int ) address;
- pPDC->PDC_TNCR = bytes;
+ pPDC->PDC_TNPR = (unsigned int) address;
+ pPDC->PDC_TNCR = bytes;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetRx */
-/** \brief Set the receive transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be received */
- unsigned int bytes ) /* \arg number of bytes to be received */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
{
- pPDC->PDC_RPR = ( unsigned int ) address;
- pPDC->PDC_RCR = bytes;
+ pPDC->PDC_RPR = (unsigned int) address;
+ pPDC->PDC_RCR = bytes;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetTx */
-/** \brief Set the transmit transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be transmitted */
- unsigned int bytes ) /* \arg number of bytes to be transmitted */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
{
- pPDC->PDC_TPR = ( unsigned int ) address;
- pPDC->PDC_TCR = bytes;
+ pPDC->PDC_TPR = (unsigned int) address;
+ pPDC->PDC_TCR = bytes;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_EnableTx */
-/** \brief Enable transmit */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
- pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_EnableRx */
-/** \brief Enable receive */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
- pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_DisableTx */
-/** \brief Disable transmit */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
- pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_DisableRx */
-/** \brief Disable receive */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
- pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsTxEmpty */
-/** \brief Test if the current transfer descriptor has been sent */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
- return !( pPDC->PDC_TCR );
+ return !(pPDC->PDC_TCR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsNextTxEmpty */
-/** \brief Test if the next transfer descriptor has been moved to the current td */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
- return !( pPDC->PDC_TNCR );
+ return !(pPDC->PDC_TNCR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsRxEmpty */
-/** \brief Test if the current transfer descriptor has been filled */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
- return !( pPDC->PDC_RCR );
+ return !(pPDC->PDC_RCR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsNextRxEmpty */
-/** \brief Test if the next transfer descriptor has been moved to the current td */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
- return !( pPDC->PDC_RNCR );
+ return !(pPDC->PDC_RNCR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_Open */
-/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
{
- /** Disable the RX and TX PDC transfer requests */
- AT91F_PDC_DisableRx( pPDC );
- AT91F_PDC_DisableTx( pPDC );
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
- /** Reset all Counter register Next buffer first */
- AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
- /** Enable the RX and TX PDC transfer requests */
- AT91F_PDC_EnableRx( pPDC );
- AT91F_PDC_EnableTx( pPDC );
+ //* Enable the RX and TX PDC transfer requests
+ AT91F_PDC_EnableRx(pPDC);
+ AT91F_PDC_EnableTx(pPDC);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_Close */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
{
- /** Disable the RX and TX PDC transfer requests */
- AT91F_PDC_DisableRx( pPDC );
- AT91F_PDC_DisableTx( pPDC );
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
- /** Reset all Counter register Next buffer first */
- AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SendFrame */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- if( AT91F_PDC_IsTxEmpty( pPDC ) )
- {
- /** Buffer and next buffer can be initialized */
- AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer );
- AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer );
- return 2;
- }
- else if( AT91F_PDC_IsNextTxEmpty( pPDC ) )
- {
- /** Only one buffer can be initialized */
- AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer );
- return 1;
- }
- else
- {
- /** All buffer are in use... */
- return 0;
- }
+ if (AT91F_PDC_IsTxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_ReceiveFrame */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- if( AT91F_PDC_IsRxEmpty( pPDC ) )
- {
- /** Buffer and next buffer can be initialized */
- AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer );
- AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer );
- return 2;
- }
- else if( AT91F_PDC_IsNextRxEmpty( pPDC ) )
- {
- /** Only one buffer can be initialized */
- AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer );
- return 1;
- }
- else
- {
- /** All buffer are in use... */
- return 0;
- }
+ if (AT91F_PDC_IsRxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+/* *****************************************************************************
+ SOFTWARE API FOR DBGU
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be enabled
+{
+ pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be disabled
+{
+ pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+ AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller
+{
+ return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR DBGU
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_InterruptEnable */
-/** \brief Enable DBGU Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg dbgu interrupt to be enabled */
+ SOFTWARE API FOR SSC
+ ***************************************************************************** */
+//* Define the standard I2S mode configuration
+
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ AT91C_SSC_CKS_DIV +\
+ AT91C_SSC_CKO_CONTINOUS +\
+ AT91C_SSC_CKG_NONE +\
+ AT91C_SSC_START_FALL_RF +\
+ AT91C_SSC_STTOUT +\
+ ((1<<16) & AT91C_SSC_STTDLY) +\
+ ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ (nb_bit_by_slot-1) +\
+ AT91C_SSC_MSBF +\
+ (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
+ (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+ AT91C_SSC_FSOS_NEGATIVE)
+
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int speed) // \arg SSC baudrate
{
- pDbgu->DBGU_IER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_InterruptDisable */
-/** \brief Disable DBGU Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg dbgu interrupt to be disabled */
-{
- pDbgu->DBGU_IDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_GetInterruptMaskStatus */
-/** \brief Return DBGU Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */
- AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */
-{
- return pDbgu->DBGU_IMR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_IsInterruptMasked */
-/** \brief Test if DBGU Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag );
-}
-
-/* *****************************************************************************
-* SOFTWARE API FOR SSC
-***************************************************************************** */
-/** Define the standard I2S mode configuration */
-
-/** Configuration to set in the SSC Transmit Clock Mode Register */
-/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
-/** nb_slot_by_frame : number of channels */
-#define AT91C_I2S_ASY_MASTER_TX_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
- ( + \
- AT91C_SSC_CKS_DIV + \
- AT91C_SSC_CKO_CONTINOUS + \
- AT91C_SSC_CKG_NONE + \
- AT91C_SSC_START_FALL_RF + \
- AT91C_SSC_STTOUT + \
- ( ( 1 << 16 ) & AT91C_SSC_STTDLY ) + \
- ( ( ( ( nb_bit_by_slot * nb_slot_by_frame ) / 2 ) - 1 ) << 24 ) )
-
-
-/** Configuration to set in the SSC Transmit Frame Mode Register */
-/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
-/** nb_slot_by_frame : number of channels */
-#define AT91C_I2S_ASY_TX_FRAME_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
- ( + \
- ( nb_bit_by_slot - 1 ) + \
- AT91C_SSC_MSBF + \
- ( ( ( nb_slot_by_frame - 1 ) << 8 ) & AT91C_SSC_DATNB ) + \
- ( ( ( nb_bit_by_slot - 1 ) << 16 ) & AT91C_SSC_FSLEN ) + \
- AT91C_SSC_FSOS_NEGATIVE )
-
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_SetBaudrate */
-/** \brief Set the baudrate according to the CPU clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_SetBaudrate( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int speed ) /* \arg SSC baudrate */
-{
- unsigned int baud_value;
-
- /** Define the baud rate divisor register */
- if( speed == 0 )
- {
- baud_value = 0;
- }
- else
- {
- baud_value = ( unsigned int ) ( mainClock * 10 ) / ( 2 * speed );
-
- if( ( baud_value % 10 ) >= 5 )
- {
- baud_value = ( baud_value / 10 ) + 1;
- }
+ unsigned int baud_value;
+ //* Define the baud rate divisor register
+ if (speed == 0)
+ baud_value = 0;
else
{
- baud_value /= 10;
+ baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+ if ((baud_value % 10) >= 5)
+ baud_value = (baud_value / 10) + 1;
+ else
+ baud_value /= 10;
}
- }
- pSSC->SSC_CMR = baud_value;
+ pSSC->SSC_CMR = baud_value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_Configure */
-/** \brief Configure SSC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_Configure( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int syst_clock, /* \arg System Clock Frequency */
- unsigned int baud_rate, /* \arg Expected Baud Rate Frequency */
- unsigned int clock_rx, /* \arg Receiver Clock Parameters */
- unsigned int mode_rx, /* \arg mode Register to be programmed */
- unsigned int clock_tx, /* \arg Transmitter Clock Parameters */
- unsigned int mode_tx ) /* \arg mode Register to be programmed */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int syst_clock, // \arg System Clock Frequency
+ unsigned int baud_rate, // \arg Expected Baud Rate Frequency
+ unsigned int clock_rx, // \arg Receiver Clock Parameters
+ unsigned int mode_rx, // \arg mode Register to be programmed
+ unsigned int clock_tx, // \arg Transmitter Clock Parameters
+ unsigned int mode_tx) // \arg mode Register to be programmed
{
- /** Disable interrupts */
- pSSC->SSC_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pSSC->SSC_IDR = (unsigned int) -1;
- /** Reset receiver and transmitter */
- pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS;
+ //* Reset receiver and transmitter
+ pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
- /** Define the Clock Mode Register */
- AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate );
+ //* Define the Clock Mode Register
+ AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
- /** Write the Receive Clock Mode Register */
- pSSC->SSC_RCMR = clock_rx;
+ //* Write the Receive Clock Mode Register
+ pSSC->SSC_RCMR = clock_rx;
- /** Write the Transmit Clock Mode Register */
- pSSC->SSC_TCMR = clock_tx;
+ //* Write the Transmit Clock Mode Register
+ pSSC->SSC_TCMR = clock_tx;
- /** Write the Receive Frame Mode Register */
- pSSC->SSC_RFMR = mode_rx;
+ //* Write the Receive Frame Mode Register
+ pSSC->SSC_RFMR = mode_rx;
- /** Write the Transmit Frame Mode Register */
- pSSC->SSC_TFMR = mode_tx;
+ //* Write the Transmit Frame Mode Register
+ pSSC->SSC_TFMR = mode_tx;
- /** Clear Transmit and Receive Counters */
- AT91F_PDC_Open( ( AT91PS_PDC ) &( pSSC->SSC_RPR ) );
+ //* Clear Transmit and Receive Counters
+ AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableRx */
-/** \brief Enable receiving datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Enable receiver */
+ //* Enable receiver
pSSC->SSC_CR = AT91C_SSC_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableRx */
-/** \brief Disable receiving datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Disable receiver */
+ //* Disable receiver
pSSC->SSC_CR = AT91C_SSC_RXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableTx */
-/** \brief Enable sending datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Enable transmitter */
+ //* Enable transmitter
pSSC->SSC_CR = AT91C_SSC_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableTx */
-/** \brief Disable sending datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Disable transmitter */
+ //* Disable transmitter
pSSC->SSC_CR = AT91C_SSC_TXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableIt */
-/** \brief Enable SSC IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pSSC->SSC_IER = flag;
+ //* Write to the IER register
+ pSSC->SSC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableIt */
-/** \brief Disable SSC IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pSSC->SSC_IDR = flag;
+ //* Write to the IDR register
+ pSSC->SSC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_ReceiveFrame( AT91PS_SSC pSSC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+ AT91PS_SSC pSSC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pSSC->SSC_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_SendFrame( AT91PS_SSC pSSC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+ AT91PS_SSC pSSC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pSSC->SSC_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_GetInterruptMaskStatus */
-/** \brief Return SSC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( /* \return SSC Interrupt Mask Status */
- AT91PS_SSC pSsc ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+ AT91PS_SSC pSsc) // \arg pointer to a SSC controller
{
- return pSsc->SSC_IMR;
+ return pSsc->SSC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_IsInterruptMasked */
-/** \brief Test if SSC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+ AT91PS_SSC pSsc, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_SSC_GetInterruptMaskStatus( pSsc ) & flag );
+ return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR SPI
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Open */
-/** \brief Open a SPI Port */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_Open( const unsigned int null ) /* \arg */
+ SOFTWARE API FOR SPI
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+ const unsigned int null) // \arg
{
- /* NOT DEFINED AT THIS MOMENT */
- return( 0 );
+ /* NOT DEFINED AT THIS MOMENT */
+ return ( 0 );
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgCs */
-/** \brief Configure SPI chip select register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgCs( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- int cs, /* SPI cs number (0 to 3) */
- int val ) /* chip select register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ int cs, // SPI cs number (0 to 3)
+ int val) // chip select register
{
- /** Write to the CSR register */
- *( pSPI->SPI_CSR + cs ) = val;
+ //* Write to the CSR register
+ *(pSPI->SPI_CSR + cs) = val;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_EnableIt */
-/** \brief Enable SPI interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_EnableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pSPI->SPI_IER = flag;
+ //* Write to the IER register
+ pSPI->SPI_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_DisableIt */
-/** \brief Disable SPI interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_DisableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pSPI->SPI_IDR = flag;
+ //* Write to the IDR register
+ pSPI->SPI_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Reset */
-/** \brief Reset the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Reset( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
- pSPI->SPI_CR = AT91C_SPI_SWRST;
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Enable */
-/** \brief Enable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Enable( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
- pSPI->SPI_CR = AT91C_SPI_SPIEN;
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Disable */
-/** \brief Disable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Disable( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ int mode) // mode register
+{
+ //* Write to the MR register
+ pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ char PCS_Device) // PCS of the Device
+{
+ //* Write to the MR register
+ pSPI->SPI_MR &= 0xFFF0FFFF;
+ pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+ AT91PS_SPI pSPI,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pSPI->SPI_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+ AT91PS_SPI pSPI,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pSPI->SPI_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+ AT91PS_SPI pSPI) // \arg pointer to a SPI controller
+{
+ //* Reset all the Chip Select register
+ pSPI->SPI_CSR[0] = 0 ;
+ pSPI->SPI_CSR[1] = 0 ;
+ pSPI->SPI_CSR[2] = 0 ;
+ pSPI->SPI_CSR[3] = 0 ;
+
+ //* Reset the SPI mode
+ pSPI->SPI_MR = 0 ;
+
+ //* Disable all interrupts
+ pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+ //* Abort the Peripheral Data Transfers
+ AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+ //* Disable receiver and transmitter and stop any activity immediately
pSPI->SPI_CR = AT91C_SPI_SPIDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgMode */
-/** \brief Enable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgMode( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- int mode ) /* mode register */
-{
- /** Write to the MR register */
- pSPI->SPI_MR = mode;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgPCS */
-/** \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgPCS( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- char PCS_Device ) /* PCS of the Device */
-{
- /** Write to the MR register */
- pSPI->SPI_MR &= 0xFFF0FFFF;
- pSPI->SPI_MR |= ( ( PCS_Device << 16 ) & AT91C_SPI_PCS );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_ReceiveFrame( AT91PS_SPI pSPI,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Close */
-/** \brief Close SPI: disable IT disable transfert, close PDC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */
-{
- /** Reset all the Chip Select register */
- pSPI->SPI_CSR[ 0 ] = 0;
- pSPI->SPI_CSR[ 1 ] = 0;
- pSPI->SPI_CSR[ 2 ] = 0;
- pSPI->SPI_CSR[ 3 ] = 0;
-
- /** Reset the SPI mode */
- pSPI->SPI_MR = 0;
-
- /** Disable all interrupts */
- pSPI->SPI_IDR = 0xFFFFFFFF;
-
- /** Abort the Peripheral Data Transfers */
- AT91F_PDC_Close( ( AT91PS_PDC ) &( pSPI->SPI_RPR ) );
-
- /** Disable receiver and transmitter and stop any activity immediately */
- pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_PutChar */
-/** \brief Send a character,does not check if ready to send */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_PutChar( AT91PS_SPI pSPI,
- unsigned int character,
- unsigned int cs_number )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+ AT91PS_SPI pSPI,
+ unsigned int character,
+ unsigned int cs_number )
{
unsigned int value_for_cs;
-
- value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; /*Place a zero among a 4 ONEs number */
- pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 );
+ value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number
+ pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_GetChar */
-/** \brief Receive a character,does not check if a character is available */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SPI_GetChar( const AT91PS_SPI pSPI )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+ const AT91PS_SPI pSPI)
{
- return( ( pSPI->SPI_RDR ) & 0xFFFF );
+ return((pSPI->SPI_RDR) & 0xFFFF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_GetInterruptMaskStatus */
-/** \brief Return SPI Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( /* \return SPI Interrupt Mask Status */
- AT91PS_SPI pSpi ) /* \arg pointer to a SPI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+ AT91PS_SPI pSpi) // \arg pointer to a SPI controller
{
- return pSpi->SPI_IMR;
+ return pSpi->SPI_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_IsInterruptMasked */
-/** \brief Test if SPI Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi, /* \arg pointer to a SPI controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+ AT91PS_SPI pSpi, // \arg pointer to a SPI controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_SPI_GetInterruptMaskStatus( pSpi ) & flag );
+ return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR PWMC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_GetStatus */
-/** \brief Return PWM Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_GetStatus( /* \return PWM Interrupt Status */
- AT91PS_PWMC pPWM ) /* pointer to a PWM controller */
+ SOFTWARE API FOR PWMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+ AT91PS_PWMC pPWM) // pointer to a PWM controller
{
- return pPWM->PWMC_SR;
+ return pPWM->PWMC_SR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_InterruptEnable */
-/** \brief Enable PWM Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_InterruptEnable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg PWM interrupt to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg PWM interrupt to be enabled
{
- pPwm->PWMC_IER = flag;
+ pPwm->PWMC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_InterruptDisable */
-/** \brief Disable PWM Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_InterruptDisable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg PWM interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg PWM interrupt to be disabled
{
- pPwm->PWMC_IDR = flag;
+ pPwm->PWMC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_GetInterruptMaskStatus */
-/** \brief Return PWM Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( /* \return PWM Interrupt Mask Status */
- AT91PS_PWMC pPwm ) /* \arg pointer to a PWM controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+ AT91PS_PWMC pPwm) // \arg pointer to a PWM controller
{
- return pPwm->PWMC_IMR;
+ return pPwm->PWMC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_IsInterruptMasked */
-/** \brief Test if PWM Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_IsInterruptMasked( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PWMC_GetInterruptMaskStatus( pPWM ) & flag );
+ return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_IsStatusSet */
-/** \brief Test if PWM Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_IsStatusSet( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PWMC_GetStatus( pPWM ) & flag );
+ return (AT91F_PWMC_GetStatus(pPWM) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_CfgChannel */
-/** \brief Test if PWM Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int channelId, /* \arg PWM channel ID */
- unsigned int mode, /* \arg PWM mode */
- unsigned int period, /* \arg PWM period */
- unsigned int duty ) /* \arg PWM duty cycle */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int channelId, // \arg PWM channel ID
+ unsigned int mode, // \arg PWM mode
+ unsigned int period, // \arg PWM period
+ unsigned int duty) // \arg PWM duty cycle
{
- pPWM->PWMC_CH[ channelId ].PWMC_CMR = mode;
- pPWM->PWMC_CH[ channelId ].PWMC_CDTYR = duty;
- pPWM->PWMC_CH[ channelId ].PWMC_CPRDR = period;
+ pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+ pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+ pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_StartChannel */
-/** \brief Enable channel */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_ENA = flag;
+ pPWM->PWMC_ENA = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_StopChannel */
-/** \brief Disable channel */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_DIS = flag;
+ pPWM->PWMC_DIS = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_UpdateChannel */
-/** \brief Update Period or Duty Cycle */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int channelId, /* \arg PWM channel ID */
- unsigned int update ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int channelId, // \arg PWM channel ID
+ unsigned int update) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_CH[ channelId ].PWMC_CUPDR = update;
+ pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
}
/* *****************************************************************************
-* SOFTWARE API FOR TC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_InterruptEnable */
-/** \brief Enable TC Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC_InterruptEnable( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg TC interrupt to be enabled */
+ SOFTWARE API FOR TC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg TC interrupt to be enabled
{
- pTc->TC_IER = flag;
+ pTc->TC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_InterruptDisable */
-/** \brief Disable TC Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC_InterruptDisable( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg TC interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg TC interrupt to be disabled
{
- pTc->TC_IDR = flag;
+ pTc->TC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_GetInterruptMaskStatus */
-/** \brief Return TC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TC_GetInterruptMaskStatus( /* \return TC Interrupt Mask Status */
- AT91PS_TC pTc ) /* \arg pointer to a TC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+ AT91PS_TC pTc) // \arg pointer to a TC controller
{
- return pTc->TC_IMR;
+ return pTc->TC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_IsInterruptMasked */
-/** \brief Test if TC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_TC_IsInterruptMasked( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_TC_GetInterruptMaskStatus( pTc ) & flag );
+ return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR PMC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgSysClkEnableReg */
-/** \brief Configure the System Clock Enable Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
+ SOFTWARE API FOR PMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
{
- /** Write to the SCER register */
- pPMC->PMC_SCER = mode;
+ //* Write to the SCER register
+ pPMC->PMC_SCER = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgSysClkDisableReg */
-/** \brief Configure the System Clock Disable Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
{
- /** Write to the SCDR register */
- pPMC->PMC_SCDR = mode;
+ //* Write to the SCDR register
+ pPMC->PMC_SCDR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetSysClkStatusReg */
-/** \brief Return the System Clock Status Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+ AT91PS_PMC pPMC // pointer to a CAN controller
+ )
{
- return pPMC->PMC_SCSR;
+ return pPMC->PMC_SCSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnablePeriphClock */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
{
- pPMC->PMC_PCER = periphIds;
+ pPMC->PMC_PCER = periphIds;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisablePeriphClock */
-/** \brief Disable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
{
- pPMC->PMC_PCDR = periphIds;
+ pPMC->PMC_PCDR = periphIds;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetPeriphClock */
-/** \brief Get peripheral clock status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
{
- return pPMC->PMC_PCSR;
+ return pPMC->PMC_PCSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_CfgMainOscillatorReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int mode)
{
- pCKGR->CKGR_MOR = mode;
+ pCKGR->CKGR_MOR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainOscillatorReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
- return pCKGR->CKGR_MOR;
+ return pCKGR->CKGR_MOR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_EnableMainOscillator */
-/** \brief Enable the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
- pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+ pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_DisableMainOscillator */
-/** \brief Disable the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_CfgMainOscStartUpTime */
-/** \brief Cfg MOR Register according to the main osc startup time */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
- unsigned int slowClock ) /* \arg slowClock in Hz */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int startup_time, // \arg main osc startup time in microsecond (us)
+ unsigned int slowClock) // \arg slowClock in Hz
{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
- pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8;
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+ pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainClockFreqReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
- return pCKGR->CKGR_MCFR;
+ return pCKGR->CKGR_MCFR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainClock */
-/** \brief Return Main clock in Hz */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int slowClock ) /* \arg slowClock in Hz */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
{
- return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4;
+ return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgMCKReg */
-/** \brief Cfg Master Clock Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
{
- pPMC->PMC_MCKR = mode;
+ pPMC->PMC_MCKR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetMCKReg */
-/** \brief Return Master Clock Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
{
- return pPMC->PMC_MCKR;
+ return pPMC->PMC_MCKR;
}
-/**------------------------------------------------------------------------------ */
-/** \fn AT91F_PMC_GetMasterClock */
-/** \brief Return master clock in Hz which correponds to processor clock for ARM7 */
-/**------------------------------------------------------------------------------ */
-__inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int slowClock ) /* \arg slowClock in Hz */
+//*------------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
{
- unsigned int reg = pPMC->PMC_MCKR;
- unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) );
- unsigned int pllDivider, pllMultiplier;
+ unsigned int reg = pPMC->PMC_MCKR;
+ unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+ unsigned int pllDivider, pllMultiplier;
- switch( reg & AT91C_PMC_CSS )
- {
- case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */
- return slowClock / prescaler;
-
- case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */
- return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
-
- case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */
- reg = pCKGR->CKGR_PLLR;
- pllDivider = ( reg & AT91C_CKGR_DIV );
- pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
- return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
- }
-
- return 0;
+ switch (reg & AT91C_PMC_CSS) {
+ case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+ return slowClock / prescaler;
+ case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+ case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+ reg = pCKGR->CKGR_PLLR;
+ pllDivider = (reg & AT91C_CKGR_DIV);
+ pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+ }
+ return 0;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnablePCK */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck, // \arg Peripheral clock identifier 0 .. 7
+ unsigned int mode)
{
- pPMC->PMC_PCKR[ pck ] = mode;
- pPMC->PMC_SCER = ( 1 << pck ) << 8;
+ pPMC->PMC_PCKR[pck] = mode;
+ pPMC->PMC_SCER = (1 << pck) << 8;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisablePCK */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck) // \arg Peripheral clock identifier 0 .. 7
{
- pPMC->PMC_SCDR = ( 1 << pck ) << 8;
+ pPMC->PMC_SCDR = (1 << pck) << 8;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnableIt */
-/** \brief Enable PMC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pPMC->PMC_IER = flag;
+ //* Write to the IER register
+ pPMC->PMC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisableIt */
-/** \brief Disable PMC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pPMC->PMC_IDR = flag;
+ //* Write to the IDR register
+ pPMC->PMC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetStatus */
-/** \brief Return PMC Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */
- AT91PS_PMC pPMC ) /* pointer to a PMC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
{
- return pPMC->PMC_SR;
+ return pPMC->PMC_SR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetInterruptMaskStatus */
-/** \brief Return PMC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */
- AT91PS_PMC pPMC ) /* pointer to a PMC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
{
- return pPMC->PMC_IMR;
+ return pPMC->PMC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_IsInterruptMasked */
-/** \brief Test if PMC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag );
+ return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_IsStatusSet */
-/** \brief Test if PMC Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PMC_GetStatus( pPMC ) & flag );
-} /* *****************************************************************************
- * SOFTWARE API FOR ADC
- ***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_EnableIt */
-/** \brief Enable ADC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_EnableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int flag ) /* IT to be enabled */
+ return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+ SOFTWARE API FOR ADC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pADC->ADC_IER = flag;
+ //* Write to the IER register
+ pADC->ADC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_DisableIt */
-/** \brief Disable ADC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_DisableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pADC->ADC_IDR = flag;
+ //* Write to the IDR register
+ pADC->ADC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetStatus */
-/** \brief Return ADC Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetStatus( /* \return ADC Interrupt Status */
- AT91PS_ADC pADC ) /* pointer to a ADC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+ AT91PS_ADC pADC) // pointer to a ADC controller
{
- return pADC->ADC_SR;
+ return pADC->ADC_SR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetInterruptMaskStatus */
-/** \brief Return ADC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( /* \return ADC Interrupt Mask Status */
- AT91PS_ADC pADC ) /* pointer to a ADC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+ AT91PS_ADC pADC) // pointer to a ADC controller
{
- return pADC->ADC_IMR;
+ return pADC->ADC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_IsInterruptMasked */
-/** \brief Test if ADC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_IsInterruptMasked( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_ADC_GetInterruptMaskStatus( pADC ) & flag );
+ return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_IsStatusSet */
-/** \brief Test if ADC Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_IsStatusSet( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_ADC_GetStatus( pADC ) & flag );
+ return (AT91F_ADC_GetStatus(pADC) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgModeReg */
-/** \brief Configure the Mode Register of the ADC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgModeReg( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int mode) // mode register
{
- /** Write to the MR register */
- pADC->ADC_MR = mode;
+ //* Write to the MR register
+ pADC->ADC_MR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetModeReg */
-/** \brief Return the Mode Register of the ADC controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetModeReg( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_MR;
+ return pADC->ADC_MR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgTimings */
-/** \brief Configure the different necessary timings of the ADC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgTimings( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int mck_clock, /* in MHz */
- unsigned int adc_clock, /* in MHz */
- unsigned int startup_time, /* in us */
- unsigned int sample_and_hold_time ) /* in ns */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int mck_clock, // in MHz
+ unsigned int adc_clock, // in MHz
+ unsigned int startup_time, // in us
+ unsigned int sample_and_hold_time) // in ns
{
- unsigned int prescal, startup, shtim;
-
- prescal = mck_clock / ( 2 * adc_clock ) - 1;
- startup = adc_clock * startup_time / 8 - 1;
- shtim = adc_clock * sample_and_hold_time / 1000 - 1;
-
- /** Write to the MR register */
- pADC->ADC_MR = ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) & AT91C_ADC_SHTIM );
+ unsigned int prescal,startup,shtim;
+
+ prescal = mck_clock/(2*adc_clock) - 1;
+ startup = adc_clock*startup_time/8 - 1;
+ shtim = adc_clock*sample_and_hold_time/1000 - 1;
+
+ //* Write to the MR register
+ pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_EnableChannel */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_EnableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int channel ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int channel) // mode register
{
- /** Write to the CHER register */
- pADC->ADC_CHER = channel;
+ //* Write to the CHER register
+ pADC->ADC_CHER = channel;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_DisableChannel */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_DisableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int channel ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int channel) // mode register
{
- /** Write to the CHDR register */
- pADC->ADC_CHDR = channel;
+ //* Write to the CHDR register
+ pADC->ADC_CHDR = channel;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetChannelStatus */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetChannelStatus( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_CHSR;
+ return pADC->ADC_CHSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_StartConversion */
-/** \brief Software request for a analog to digital conversion */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_StartConversion( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- pADC->ADC_CR = AT91C_ADC_START;
+ pADC->ADC_CR = AT91C_ADC_START;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_SoftReset */
-/** \brief Software reset */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_SoftReset( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- pADC->ADC_CR = AT91C_ADC_SWRST;
+ pADC->ADC_CR = AT91C_ADC_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetLastConvertedData */
-/** \brief Return the Last Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetLastConvertedData( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_LCDR;
+ return pADC->ADC_LCDR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH0 */
-/** \brief Return the Channel 0 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH0( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_CDR0;
+ return pADC->ADC_CDR0;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH1 */
-/** \brief Return the Channel 1 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH1( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_CDR1;
+ return pADC->ADC_CDR1;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH2 */
-/** \brief Return the Channel 2 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH2( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_CDR2;
+ return pADC->ADC_CDR2;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH3 */
-/** \brief Return the Channel 3 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH3( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_CDR3;
+ return pADC->ADC_CDR3;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH4 */
-/** \brief Return the Channel 4 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH4( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_CDR4;
+ return pADC->ADC_CDR4;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH5 */
-/** \brief Return the Channel 5 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH5( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_CDR5;
+ return pADC->ADC_CDR5;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH6 */
-/** \brief Return the Channel 6 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH6( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_CDR6;
+ return pADC->ADC_CDR6;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH7 */
-/** \brief Return the Channel 7 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH7( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
{
- return pADC->ADC_CDR7;
+ return pADC->ADC_CDR7;
}
/* *****************************************************************************
-* SOFTWARE API FOR PIO
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgPeriph */
-/** \brief Enable pins to be drived by peripheral */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int periphAEnable, /* \arg PERIPH A to enable */
- unsigned int periphBEnable ) /* \arg PERIPH B to enable */
+ SOFTWARE API FOR PIO
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int periphAEnable, // \arg PERIPH A to enable
+ unsigned int periphBEnable) // \arg PERIPH B to enable
{
- pPio->PIO_ASR = periphAEnable;
- pPio->PIO_BSR = periphBEnable;
- pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */
+ pPio->PIO_ASR = periphAEnable;
+ pPio->PIO_BSR = periphBEnable;
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgOutput */
-/** \brief Enable PIO in output mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int pioEnable ) /* \arg PIO to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pioEnable) // \arg PIO to be enabled
{
- pPio->PIO_PER = pioEnable; /* Set in PIO mode */
- pPio->PIO_OER = pioEnable; /* Configure in Output */
+ pPio->PIO_PER = pioEnable; // Set in PIO mode
+ pPio->PIO_OER = pioEnable; // Configure in Output
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgInput */
-/** \brief Enable PIO in input mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int inputEnable ) /* \arg PIO to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputEnable) // \arg PIO to be enabled
{
- /* Disable output */
- pPio->PIO_ODR = inputEnable;
- pPio->PIO_PER = inputEnable;
+ // Disable output
+ pPio->PIO_ODR = inputEnable;
+ pPio->PIO_PER = inputEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgOpendrain */
-/** \brief Configure PIO in open drain */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int multiDrvEnable) // \arg pio to be configured in open drain
{
- /* Configure the multi-drive option */
- pPio->PIO_MDDR = ~multiDrvEnable;
- pPio->PIO_MDER = multiDrvEnable;
+ // Configure the multi-drive option
+ pPio->PIO_MDDR = ~multiDrvEnable;
+ pPio->PIO_MDER = multiDrvEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgPullup */
-/** \brief Enable pullup on PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int pullupEnable ) /* \arg enable pullup on PIO */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pullupEnable) // \arg enable pullup on PIO
{
- /* Connect or not Pullup */
- pPio->PIO_PPUDR = ~pullupEnable;
- pPio->PIO_PPUER = pullupEnable;
+ // Connect or not Pullup
+ pPio->PIO_PPUDR = ~pullupEnable;
+ pPio->PIO_PPUER = pullupEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgDirectDrive */
-/** \brief Enable direct drive on PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int directDrive ) /* \arg PIO to be configured with direct drive */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int directDrive) // \arg PIO to be configured with direct drive
{
- /* Configure the Direct Drive */
- pPio->PIO_OWDR = ~directDrive;
- pPio->PIO_OWER = directDrive;
+ // Configure the Direct Drive
+ pPio->PIO_OWDR = ~directDrive;
+ pPio->PIO_OWER = directDrive;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgInputFilter */
-/** \brief Enable input filter on input PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int inputFilter ) /* \arg PIO to be configured with input filter */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputFilter) // \arg PIO to be configured with input filter
{
- /* Configure the Direct Drive */
- pPio->PIO_IFDR = ~inputFilter;
- pPio->PIO_IFER = inputFilter;
+ // Configure the Direct Drive
+ pPio->PIO_IFDR = ~inputFilter;
+ pPio->PIO_IFER = inputFilter;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInput */
-/** \brief Return PIO input value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_PDSR;
+ return pPio->PIO_PDSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInputSet */
-/** \brief Test if PIO is input flag is active */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PIO_GetInput( pPio ) & flag );
+ return (AT91F_PIO_GetInput(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_SetOutput */
-/** \brief Set to 1 output PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be set */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be set
{
- pPio->PIO_SODR = flag;
+ pPio->PIO_SODR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_ClearOutput */
-/** \brief Set to 0 output PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be cleared */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be cleared
{
- pPio->PIO_CODR = flag;
+ pPio->PIO_CODR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_ForceOutput */
-/** \brief Force output when Direct drive option is enabled */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be forced */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be forced
{
- pPio->PIO_ODSR = flag;
+ pPio->PIO_ODSR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Enable */
-/** \brief Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
{
- pPio->PIO_PER = flag;
+ pPio->PIO_PER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Disable */
-/** \brief Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
{
- pPio->PIO_PDR = flag;
+ pPio->PIO_PDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetStatus */
-/** \brief Return PIO Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_PSR;
+ return pPio->PIO_PSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsSet */
-/** \brief Test if PIO is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PIO_GetStatus( pPio ) & flag );
+ return (AT91F_PIO_GetStatus(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputEnable */
-/** \brief Output Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be enabled
{
- pPio->PIO_OER = flag;
+ pPio->PIO_OER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputDisable */
-/** \brief Output Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be disabled
{
- pPio->PIO_ODR = flag;
+ pPio->PIO_ODR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputStatus */
-/** \brief Return PIO Output Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_OSR;
+ return pPio->PIO_OSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOuputSet */
-/** \brief Test if PIO Output is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PIO_GetOutputStatus( pPio ) & flag );
+ return (AT91F_PIO_GetOutputStatus(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InputFilterEnable */
-/** \brief Input Filter Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio input filter to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be enabled
{
- pPio->PIO_IFER = flag;
+ pPio->PIO_IFER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InputFilterDisable */
-/** \brief Input Filter Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio input filter to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be disabled
{
- pPio->PIO_IFDR = flag;
+ pPio->PIO_IFDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInputFilterStatus */
-/** \brief Return PIO Input Filter Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_IFSR;
+ return pPio->PIO_IFSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInputFilterSet */
-/** \brief Test if PIO Input filter is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag );
+ return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputDataStatus */
-/** \brief Return PIO Output Data Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_ODSR;
+ return pPio->PIO_ODSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InterruptEnable */
-/** \brief Enable PIO Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio interrupt to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be enabled
{
- pPio->PIO_IER = flag;
+ pPio->PIO_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InterruptDisable */
-/** \brief Disable PIO Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be disabled
{
- pPio->PIO_IDR = flag;
+ pPio->PIO_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInterruptMaskStatus */
-/** \brief Return PIO Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_IMR;
+ return pPio->PIO_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInterruptStatus */
-/** \brief Return PIO Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_ISR;
+ return pPio->PIO_ISR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInterruptMasked */
-/** \brief Test if PIO Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag );
+ return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInterruptSet */
-/** \brief Test if PIO Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PIO_GetInterruptStatus( pPio ) & flag );
+ return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_MultiDriverEnable */
-/** \brief Multi Driver Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
{
- pPio->PIO_MDER = flag;
+ pPio->PIO_MDER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_MultiDriverDisable */
-/** \brief Multi Driver Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
{
- pPio->PIO_MDDR = flag;
+ pPio->PIO_MDDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetMultiDriverStatus */
-/** \brief Return PIO Multi Driver Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_MDSR;
+ return pPio->PIO_MDSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsMultiDriverSet */
-/** \brief Test if PIO MultiDriver is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag );
+ return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_A_RegisterSelection */
-/** \brief PIO A Register Selection */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio A register selection */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio A register selection
{
- pPio->PIO_ASR = flag;
+ pPio->PIO_ASR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_B_RegisterSelection */
-/** \brief PIO B Register Selection */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio B register selection */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio B register selection
{
- pPio->PIO_BSR = flag;
+ pPio->PIO_BSR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Get_AB_RegisterStatus */
-/** \brief Return PIO Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_ABSR;
+ return pPio->PIO_ABSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsAB_RegisterSet */
-/** \brief Test if PIO AB Register is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag );
+ return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputWriteEnable */
-/** \brief Output Write Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output write to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be enabled
{
- pPio->PIO_OWER = flag;
+ pPio->PIO_OWER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputWriteDisable */
-/** \brief Output Write Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output write to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be disabled
{
- pPio->PIO_OWDR = flag;
+ pPio->PIO_OWDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputWriteStatus */
-/** \brief Return PIO Output Write Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_OWSR;
+ return pPio->PIO_OWSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOutputWriteSet */
-/** \brief Test if PIO OutputWrite is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag );
+ return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetCfgPullup */
-/** \brief Return PIO Configuration Pullup */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- return pPio->PIO_PPUSR;
+ return pPio->PIO_PPUSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOutputDataStatusSet */
-/** \brief Test if PIO Output Data Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag );
+ return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsCfgPullupStatusSet */
-/** \brief Test if PIO Configuration Pullup Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag );
+ return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR TWI
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_EnableIt */
-/** \brief Enable TWI IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_EnableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg IT to be enabled */
+ SOFTWARE API FOR TWI
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pTWI->TWI_IER = flag;
+ //* Write to the IER register
+ pTWI->TWI_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_DisableIt */
-/** \brief Disable TWI IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_DisableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pTWI->TWI_IDR = flag;
+ //* Write to the IDR register
+ pTWI->TWI_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_Configure */
-/** \brief Configure TWI in master mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_Configure( AT91PS_TWI pTWI ) /* \arg pointer to a TWI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller
{
- /** Disable interrupts */
- pTWI->TWI_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pTWI->TWI_IDR = (unsigned int) -1;
- /** Reset peripheral */
- pTWI->TWI_CR = AT91C_TWI_SWRST;
+ //* Reset peripheral
+ pTWI->TWI_CR = AT91C_TWI_SWRST;
- /** Set Master mode */
- pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
+ //* Set Master mode
+ pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_GetInterruptMaskStatus */
-/** \brief Return TWI Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( /* \return TWI Interrupt Mask Status */
- AT91PS_TWI pTwi ) /* \arg pointer to a TWI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+ AT91PS_TWI pTwi) // \arg pointer to a TWI controller
{
- return pTwi->TWI_IMR;
+ return pTwi->TWI_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_IsInterruptMasked */
-/** \brief Test if TWI Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+ AT91PS_TWI pTwi, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_TWI_GetInterruptMaskStatus( pTwi ) & flag );
+ return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR USART
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Baudrate */
-/** \brief Calculate the baudrate */
-/** Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_ASYNC_MODE \
- ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+ SOFTWARE API FOR USART
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/** Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_ASYNC_SCK_MODE \
- ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_EXT )
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_EXT )
-/** Standard Synchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_SYNC_MODE \
- ( AT91C_US_SYNC + \
- AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+ AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/** SCK used Label */
-#define AT91C_US_SCK_USED ( AT91C_US_CKLO | AT91C_US_CLKS_EXT )
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-/** Standard ISO T=0 Mode : 8 bits , 1 stop , parity */
-#define AT91C_US_ISO_READER_MODE \
- ( AT91C_US_USMODE_ISO7816_0 + \
- AT91C_US_CLKS_CLOCK + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_EVEN + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CKLO + \
- AT91C_US_OVER )
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+ AT91C_US_CLKS_CLOCK +\
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_EVEN + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CKLO +\
+ AT91C_US_OVER)
-/** Standard IRDA mode */
-#define AT91C_US_ASYNC_IRDA_MODE \
- ( AT91C_US_USMODE_IRDA + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Baudrate */
-/** \brief Caluculate baud_value according to the main clock and the baud rate */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_Baudrate( const unsigned int main_clock, /* \arg peripheral clock */
- const unsigned int baud_rate ) /* \arg UART baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+ const unsigned int main_clock, // \arg peripheral clock
+ const unsigned int baud_rate) // \arg UART baudrate
{
- unsigned int baud_value = ( ( main_clock * 10 ) / ( baud_rate * 16 ) );
-
- if( ( baud_value % 10 ) >= 5 )
- {
- baud_value = ( baud_value / 10 ) + 1;
- }
- else
- {
- baud_value /= 10;
- }
-
- return baud_value;
+ unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+ if ((baud_value % 10) >= 5)
+ baud_value = (baud_value / 10) + 1;
+ else
+ baud_value /= 10;
+ return baud_value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetBaudrate */
-/** \brief Set the baudrate according to the CPU clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetBaudrate( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int speed ) /* \arg UART baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int speed) // \arg UART baudrate
{
- /** Define the baud rate divisor register */
- pUSART->US_BRGR = AT91F_US_Baudrate( mainClock, speed );
+ //* Define the baud rate divisor register
+ pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetTimeguard */
-/** \brief Set USART timeguard */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetTimeguard( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int timeguard ) /* \arg timeguard value */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int timeguard) // \arg timeguard value
{
- /** Write the Timeguard Register */
- pUSART->US_TTGR = timeguard;
+ //* Write the Timeguard Register
+ pUSART->US_TTGR = timeguard ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableIt */
-/** \brief Enable USART IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int flag ) /* \arg IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pUSART->US_IER = flag;
+ //* Write to the IER register
+ pUSART->US_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableIt */
-/** \brief Disable USART IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IER register */
- pUSART->US_IDR = flag;
+ //* Write to the IER register
+ pUSART->US_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Configure */
-/** \brief Configure USART */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_Configure( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int mode, /* \arg mode Register to be programmed */
- unsigned int baudRate, /* \arg baudrate to be programmed */
- unsigned int timeguard ) /* \arg timeguard to be programmed */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int mode , // \arg mode Register to be programmed
+ unsigned int baudRate , // \arg baudrate to be programmed
+ unsigned int timeguard ) // \arg timeguard to be programmed
{
- /** Disable interrupts */
- pUSART->US_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pUSART->US_IDR = (unsigned int) -1;
- /** Reset receiver and transmitter */
- pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
+ //* Reset receiver and transmitter
+ pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
- /** Define the baud rate divisor register */
- AT91F_US_SetBaudrate( pUSART, mainClock, baudRate );
+ //* Define the baud rate divisor register
+ AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
- /** Write the Timeguard Register */
- AT91F_US_SetTimeguard( pUSART, timeguard );
+ //* Write the Timeguard Register
+ AT91F_US_SetTimeguard(pUSART, timeguard);
- /** Clear Transmit and Receive Counters */
- AT91F_PDC_Open( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
+ //* Clear Transmit and Receive Counters
+ AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
- /** Define the USART mode */
- pUSART->US_MR = mode;
+ //* Define the USART mode
+ pUSART->US_MR = mode ;
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableRx */
-/** \brief Enable receiving characters */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Enable receiver */
+ //* Enable receiver
pUSART->US_CR = AT91C_US_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableTx */
-/** \brief Enable sending characters */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Enable transmitter */
+ //* Enable transmitter
pUSART->US_CR = AT91C_US_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ResetRx */
-/** \brief Reset Receiver and re-enable it */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_ResetRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset receiver */
- pUSART->US_CR = AT91C_US_RSTRX;
- /** Re-Enable receiver */
+ //* Reset receiver
+ pUSART->US_CR = AT91C_US_RSTRX;
+ //* Re-Enable receiver
pUSART->US_CR = AT91C_US_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ResetTx */
-/** \brief Reset Transmitter and re-enable it */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_ResetTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset transmitter */
- pUSART->US_CR = AT91C_US_RSTTX;
- /** Enable transmitter */
+ //* Reset transmitter
+ pUSART->US_CR = AT91C_US_RSTTX;
+ //* Enable transmitter
pUSART->US_CR = AT91C_US_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableRx */
-/** \brief Disable Receiver */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Disable receiver */
+ //* Disable receiver
pUSART->US_CR = AT91C_US_RXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableTx */
-/** \brief Disable Transmitter */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Disable transmitter */
+ //* Disable transmitter
pUSART->US_CR = AT91C_US_TXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Close */
-/** \brief Close USART: disable IT disable receiver and transmitter, close PDC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_Close( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset the baud rate divisor register */
- pUSART->US_BRGR = 0;
+ //* Reset the baud rate divisor register
+ pUSART->US_BRGR = 0 ;
- /** Reset the USART mode */
- pUSART->US_MR = 0;
+ //* Reset the USART mode
+ pUSART->US_MR = 0 ;
- /** Reset the Timeguard Register */
+ //* Reset the Timeguard Register
pUSART->US_TTGR = 0;
- /** Disable all interrupts */
- pUSART->US_IDR = 0xFFFFFFFF;
+ //* Disable all interrupts
+ pUSART->US_IDR = 0xFFFFFFFF ;
- /** Abort the Peripheral Data Transfers */
- AT91F_PDC_Close( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
+ //* Abort the Peripheral Data Transfers
+ AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
- /** Disable receiver and transmitter and stop any activity immediately */
- pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
+ //* Disable receiver and transmitter and stop any activity immediately
+ pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_TxReady */
-/** \brief Return 1 if a character can be written in US_THR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_TxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR & AT91C_US_TXRDY );
+ return (pUSART->US_CSR & AT91C_US_TXRDY);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_RxReady */
-/** \brief Return 1 if a character can be read in US_RHR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_RxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR & AT91C_US_RXRDY );
+ return (pUSART->US_CSR & AT91C_US_RXRDY);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Error */
-/** \brief Return the error flag */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_Error( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR &
- ( AT91C_US_OVRE | /* Overrun error */
- AT91C_US_FRAME | /* Framing error */
- AT91C_US_PARE ) ); /* Parity error */
+ return (pUSART->US_CSR &
+ (AT91C_US_OVRE | // Overrun error
+ AT91C_US_FRAME | // Framing error
+ AT91C_US_PARE)); // Parity error
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_PutChar */
-/** \brief Send a character,does not check if ready to send */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_PutChar( AT91PS_USART pUSART,
- int character )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+ AT91PS_USART pUSART,
+ int character )
{
- pUSART->US_THR = ( character & 0x1FF );
+ pUSART->US_THR = (character & 0x1FF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_GetChar */
-/** \brief Receive a character,does not check if a character is available */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_US_GetChar( const AT91PS_USART pUSART )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+ const AT91PS_USART pUSART)
{
- return( ( pUSART->US_RHR ) & 0x1FF );
+ return((pUSART->US_RHR) & 0x1FF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_SendFrame( AT91PS_USART pUSART,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+ AT91PS_USART pUSART,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pUSART->US_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pUSART->US_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_ReceiveFrame( AT91PS_USART pUSART,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+ AT91PS_USART pUSART,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pUSART->US_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pUSART->US_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetIrdaFilter */
-/** \brief Set the value of IrDa filter tregister */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetIrdaFilter( AT91PS_USART pUSART,
- unsigned char value )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+ AT91PS_USART pUSART,
+ unsigned char value
+)
{
- pUSART->US_IF = value;
+ pUSART->US_IF = value;
}
/* *****************************************************************************
-* SOFTWARE API FOR UDP
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EnableIt */
-/** \brief Enable UDP IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EnableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg IT to be enabled */
+ SOFTWARE API FOR UDP
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pUDP->UDP_IER = flag;
+ //* Write to the IER register
+ pUDP->UDP_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_DisableIt */
-/** \brief Disable UDP IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_DisableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pUDP->UDP_IDR = flag;
+ //* Write to the IDR register
+ pUDP->UDP_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_SetAddress */
-/** \brief Set UDP functional address */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_SetAddress( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char address ) /* \arg new UDP address */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char address) // \arg new UDP address
{
- pUDP->UDP_FADDR = ( AT91C_UDP_FEN | address );
+ pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EnableEp */
-/** \brief Enable Endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EnableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg endpoints to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg endpoints to be enabled
{
- pUDP->UDP_GLBSTATE |= flag;
+ pUDP->UDP_GLBSTATE |= flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_DisableEp */
-/** \brief Enable Endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_DisableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg endpoints to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg endpoints to be enabled
{
- pUDP->UDP_GLBSTATE &= ~( flag );
+ pUDP->UDP_GLBSTATE &= ~(flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_SetState */
-/** \brief Set UDP Device state */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_SetState( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg new UDP address */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg new UDP address
{
- pUDP->UDP_GLBSTATE &= ~( AT91C_UDP_FADDEN | AT91C_UDP_CONFG );
- pUDP->UDP_GLBSTATE |= flag;
+ pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+ pUDP->UDP_GLBSTATE |= flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_GetState */
-/** \brief return UDP Device state */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_GetState( /* \return the UDP device state */
- AT91PS_UDP pUDP ) /* \arg pointer to a UDP controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+ AT91PS_UDP pUDP) // \arg pointer to a UDP controller
{
- return( pUDP->UDP_GLBSTATE & ( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ) );
+ return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_ResetEp */
-/** \brief Reset UDP endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_ResetEp( /* \return the UDP device state */
- AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg Endpoints to be reset */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg Endpoints to be reset
{
- pUDP->UDP_RSTEP = flag;
+ pUDP->UDP_RSTEP = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpStall */
-/** \brief Endpoint will STALL requests */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpStall( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_FORCESTALL;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpWrite */
-/** \brief Write value in the DPR */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpWrite( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned char value ) /* \arg value to be written in the DPR */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned char value) // \arg value to be written in the DPR
{
- pUDP->UDP_FDR[ endpoint ] = value;
+ pUDP->UDP_FDR[endpoint] = value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpRead */
-/** \brief Return value from the DPR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_EpRead( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- return pUDP->UDP_FDR[ endpoint ];
+ return pUDP->UDP_FDR[endpoint];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpEndOfWr */
-/** \brief Notify the UDP that values in DPR are ready to be sent */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpEndOfWr( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_TXPKTRDY;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpClear */
-/** \brief Clear flag in the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpClear( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned int flag ) /* \arg flag to be cleared */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned int flag) // \arg flag to be cleared
{
- pUDP->UDP_CSR[ endpoint ] &= ~( flag );
+ pUDP->UDP_CSR[endpoint] &= ~(flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpSet */
-/** \brief Set flag in the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpSet( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned int flag ) /* \arg flag to be cleared */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned int flag) // \arg flag to be cleared
{
- pUDP->UDP_CSR[ endpoint ] |= flag;
+ pUDP->UDP_CSR[endpoint] |= flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpStatus */
-/** \brief Return the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_EpStatus( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- return pUDP->UDP_CSR[ endpoint ];
+ return pUDP->UDP_CSR[endpoint];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_GetInterruptMaskStatus */
-/** \brief Return UDP Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( /* \return UDP Interrupt Mask Status */
- AT91PS_UDP pUdp ) /* \arg pointer to a UDP controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+ AT91PS_UDP pUdp) // \arg pointer to a UDP controller
{
- return pUdp->UDP_IMR;
+ return pUdp->UDP_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_IsInterruptMasked */
-/** \brief Test if UDP Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+ AT91PS_UDP pUdp, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_UDP_GetInterruptMaskStatus( pUdp ) & flag );
+ return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR AIC
-***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */
+ SOFTWARE API FOR AIC
+ ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_ConfigureIt */
-/** \brief Interrupt Handler Initialization */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id, /* \arg interrupt number to initialize */
- unsigned int priority, /* \arg priority to give to the interrupt */
- unsigned int src_type, /* \arg activation and sense of activation */
- void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id, // \arg interrupt number to initialize
+ unsigned int priority, // \arg priority to give to the interrupt
+ unsigned int src_type, // \arg activation and sense of activation
+ void (*newHandler) (void) ) // \arg address of the interrupt handler
{
- unsigned int oldHandler;
- unsigned int mask;
+ unsigned int oldHandler;
+ unsigned int mask ;
- oldHandler = pAic->AIC_SVR[ irq_id ];
+ oldHandler = pAic->AIC_SVR[irq_id];
- mask = 0x1 << irq_id;
- /** Disable the interrupt on the interrupt controller */
- pAic->AIC_IDCR = mask;
- /** Save the interrupt handler routine pointer and the interrupt priority */
- pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;
- /** Store the Source Mode Register */
- pAic->AIC_SMR[ irq_id ] = src_type | priority;
- /** Clear the interrupt on the interrupt controller */
- pAic->AIC_ICCR = mask;
+ mask = 0x1 << irq_id ;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Save the interrupt handler routine pointer and the interrupt priority
+ pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+ //* Store the Source Mode Register
+ pAic->AIC_SMR[irq_id] = src_type | priority ;
+ //* Clear the interrupt on the interrupt controller
+ pAic->AIC_ICCR = mask ;
- return oldHandler;
+ return oldHandler;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_EnableIt */
-/** \brief Enable corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
{
- /** Enable the interrupt on the interrupt controller */
- pAic->AIC_IECR = 0x1 << irq_id;
+ //* Enable the interrupt on the interrupt controller
+ pAic->AIC_IECR = 0x1 << irq_id ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_DisableIt */
-/** \brief Disable corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
{
unsigned int mask = 0x1 << irq_id;
-
- /** Disable the interrupt on the interrupt controller */
- pAic->AIC_IDCR = mask;
- /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
- pAic->AIC_ICCR = mask;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = mask ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_ClearIt */
-/** \brief Clear corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number to initialize
{
- /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
- pAic->AIC_ICCR = ( 0x1 << irq_id );
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = (0x1 << irq_id);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_AcknowledgeIt */
-/** \brief Acknowledge corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+ AT91PS_AIC pAic) // \arg pointer to the AIC registers
{
pAic->AIC_EOICR = pAic->AIC_EOICR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_SetExceptionVector */
-/** \brief Configure vector handler */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */
- void ( * Handler )() ) /* \arg Interrupt Handler */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_SetExceptionVector (
+ unsigned int *pVector, // \arg pointer to the AIC registers
+ void (*Handler) () ) // \arg Interrupt Handler
{
- unsigned int oldVector = *pVector;
+ unsigned int oldVector = *pVector;
- if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE )
- {
- *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE;
- }
- else
- {
- *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000;
- }
+ if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+ *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+ else
+ *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
- return oldVector;
+ return oldVector;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_Trig */
-/** \brief Trig an IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Trig (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number
{
- pAic->AIC_ISCR = ( 0x1 << irq_id );
+ pAic->AIC_ISCR = (0x1 << irq_id) ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_IsActive */
-/** \brief Test if an IT is active */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg Interrupt Number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsActive (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
{
- return( pAic->AIC_ISR & ( 0x1 << irq_id ) );
+ return (pAic->AIC_ISR & (0x1 << irq_id));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_IsPending */
-/** \brief Test if an IT is pending */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg Interrupt Number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsPending (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
{
- return( pAic->AIC_IPR & ( 0x1 << irq_id ) );
+ return (pAic->AIC_IPR & (0x1 << irq_id));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_Open */
-/** \brief Set exception vectors and AIC registers to default values */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- void ( * IrqHandler )(), /* \arg Default IRQ vector exception */
- void ( * FiqHandler )(), /* \arg Default FIQ vector exception */
- void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */
- void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */
- unsigned int protectMode ) /* \arg Debug Control Register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ void (*IrqHandler) (), // \arg Default IRQ vector exception
+ void (*FiqHandler) (), // \arg Default FIQ vector exception
+ void (*DefaultHandler) (), // \arg Default Handler set in ISR
+ void (*SpuriousHandler) (), // \arg Default Spurious Handler
+ unsigned int protectMode) // \arg Debug Control Register
{
- int i;
+ int i;
- /* Disable all interrupts and set IVR to the default handler */
- for( i = 0; i < 32; ++i )
- {
- AT91F_AIC_DisableIt( pAic, i );
- AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler );
- }
+ // Disable all interrupts and set IVR to the default handler
+ for (i = 0; i < 32; ++i) {
+ AT91F_AIC_DisableIt(pAic, i);
+ AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);
+ }
- /* Set the IRQ exception vector */
- AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler );
- /* Set the Fast Interrupt exception vector */
- AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler );
+ // Set the IRQ exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+ // Set the Fast Interrupt exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
- pAic->AIC_SPU = ( unsigned int ) SpuriousHandler;
- pAic->AIC_DCR = protectMode;
+ pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+ pAic->AIC_DCR = protectMode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for MC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for DBGU */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_CfgPIO */
-/** \brief Configure PIO controllers to drive DBGU signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA10_DTXD ) |
- ( ( unsigned int ) AT91C_PA9_DRXD ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA10_DTXD ) |
+ ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH3_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH3 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH3_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA14_PWM3 ) |
- ( ( unsigned int ) AT91C_PA7_PWM3 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA14_PWM3 ) |
+ ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH2_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH2 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH2_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA2_PWM2 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA25_PWM2 ) |
- ( ( unsigned int ) AT91C_PA13_PWM2 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A
+ ((unsigned int) AT91C_PA25_PWM2 ) |
+ ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH1_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH1_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA1_PWM1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA24_PWM1 ) |
- ( ( unsigned int ) AT91C_PA12_PWM1 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A
+ ((unsigned int) AT91C_PA24_PWM1 ) |
+ ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH0_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH0_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA0_PWM0 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA23_PWM0 ) |
- ( ( unsigned int ) AT91C_PA11_PWM0 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A
+ ((unsigned int) AT91C_PA23_PWM0 ) |
+ ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SSC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SSC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SSC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_CfgPIO */
-/** \brief Configure PIO controllers to drive SSC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA17_TD ) |
- ( ( unsigned int ) AT91C_PA15_TF ) |
- ( ( unsigned int ) AT91C_PA19_RK ) |
- ( ( unsigned int ) AT91C_PA18_RD ) |
- ( ( unsigned int ) AT91C_PA20_RF ) |
- ( ( unsigned int ) AT91C_PA16_TK ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA17_TD ) |
+ ((unsigned int) AT91C_PA15_TF ) |
+ ((unsigned int) AT91C_PA19_RK ) |
+ ((unsigned int) AT91C_PA18_RD ) |
+ ((unsigned int) AT91C_PA20_RF ) |
+ ((unsigned int) AT91C_PA16_TK ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SPI */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SPI
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SPI ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SPI));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgPIO */
-/** \brief Configure PIO controllers to drive SPI signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgPIO
+//* \brief Configure PIO controllers to drive SPI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA11_NPCS0 ) |
- ( ( unsigned int ) AT91C_PA13_MOSI ) |
- ( ( unsigned int ) AT91C_PA31_NPCS1 ) |
- ( ( unsigned int ) AT91C_PA12_MISO ) |
- ( ( unsigned int ) AT91C_PA14_SPCK ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA9_NPCS1 ) |
- ( ( unsigned int ) AT91C_PA30_NPCS2 ) |
- ( ( unsigned int ) AT91C_PA10_NPCS2 ) |
- ( ( unsigned int ) AT91C_PA22_NPCS3 ) |
- ( ( unsigned int ) AT91C_PA3_NPCS3 ) |
- ( ( unsigned int ) AT91C_PA5_NPCS3 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA11_NPCS0 ) |
+ ((unsigned int) AT91C_PA13_MOSI ) |
+ ((unsigned int) AT91C_PA31_NPCS1 ) |
+ ((unsigned int) AT91C_PA12_MISO ) |
+ ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A
+ ((unsigned int) AT91C_PA9_NPCS1 ) |
+ ((unsigned int) AT91C_PA30_NPCS2 ) |
+ ((unsigned int) AT91C_PA10_NPCS2 ) |
+ ((unsigned int) AT91C_PA22_NPCS3 ) |
+ ((unsigned int) AT91C_PA3_NPCS3 ) |
+ ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PWMC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PWMC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PWMC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC2_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC2 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC2_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC2 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC2));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC2_CfgPIO */
-/** \brief Configure PIO controllers to drive TC2 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC2_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA26_TIOA2 ) |
- ( ( unsigned int ) AT91C_PA27_TIOB2 ) |
- ( ( unsigned int ) AT91C_PA29_TCLK2 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA26_TIOA2 ) |
+ ((unsigned int) AT91C_PA27_TIOB2 ) |
+ ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC1_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC1 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC1_CfgPIO */
-/** \brief Configure PIO controllers to drive TC1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC1_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA15_TIOA1 ) |
- ( ( unsigned int ) AT91C_PA16_TIOB1 ) |
- ( ( unsigned int ) AT91C_PA28_TCLK1 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA15_TIOA1 ) |
+ ((unsigned int) AT91C_PA16_TIOB1 ) |
+ ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC0_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC0 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC0_CfgPIO */
-/** \brief Configure PIO controllers to drive TC0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC0_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA0_TIOA0 ) |
- ( ( unsigned int ) AT91C_PA1_TIOB0 ) |
- ( ( unsigned int ) AT91C_PA4_TCLK0 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA0_TIOA0 ) |
+ ((unsigned int) AT91C_PA1_TIOB0 ) |
+ ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PMC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgPIO */
-/** \brief Configure PIO controllers to drive PMC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA17_PCK1 ) |
- ( ( unsigned int ) AT91C_PA21_PCK1 ) |
- ( ( unsigned int ) AT91C_PA31_PCK2 ) |
- ( ( unsigned int ) AT91C_PA18_PCK2 ) |
- ( ( unsigned int ) AT91C_PA6_PCK0 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA17_PCK1 ) |
+ ((unsigned int) AT91C_PA21_PCK1 ) |
+ ((unsigned int) AT91C_PA31_PCK2 ) |
+ ((unsigned int) AT91C_PA18_PCK2 ) |
+ ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for ADC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_ADC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_ADC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgPIO */
-/** \brief Configure PIO controllers to drive ADC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA8_ADTRG ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIOA_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PIOA */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIOA_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PIOA ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PIOA));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TWI */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TWI ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TWI));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_CfgPIO */
-/** \brief Configure PIO controllers to drive TWI signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA3_TWD ) |
- ( ( unsigned int ) AT91C_PA4_TWCK ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA3_TWD ) |
+ ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for US1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US1_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_US1 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_US1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US1_CfgPIO */
-/** \brief Configure PIO controllers to drive US1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US1_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA21_RXD1 ) |
- ( ( unsigned int ) AT91C_PA27_DTR1 ) |
- ( ( unsigned int ) AT91C_PA26_DCD1 ) |
- ( ( unsigned int ) AT91C_PA22_TXD1 ) |
- ( ( unsigned int ) AT91C_PA24_RTS1 ) |
- ( ( unsigned int ) AT91C_PA23_SCK1 ) |
- ( ( unsigned int ) AT91C_PA28_DSR1 ) |
- ( ( unsigned int ) AT91C_PA29_RI1 ) |
- ( ( unsigned int ) AT91C_PA25_CTS1 ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA21_RXD1 ) |
+ ((unsigned int) AT91C_PA27_DTR1 ) |
+ ((unsigned int) AT91C_PA26_DCD1 ) |
+ ((unsigned int) AT91C_PA22_TXD1 ) |
+ ((unsigned int) AT91C_PA24_RTS1 ) |
+ ((unsigned int) AT91C_PA23_SCK1 ) |
+ ((unsigned int) AT91C_PA28_DSR1 ) |
+ ((unsigned int) AT91C_PA29_RI1 ) |
+ ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for US0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US0_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_US0 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_US0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US0_CfgPIO */
-/** \brief Configure PIO controllers to drive US0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US0_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA5_RXD0 ) |
- ( ( unsigned int ) AT91C_PA6_TXD0 ) |
- ( ( unsigned int ) AT91C_PA7_RTS0 ) |
- ( ( unsigned int ) AT91C_PA8_CTS0 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA2_SCK0 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA5_RXD0 ) |
+ ((unsigned int) AT91C_PA6_TXD0 ) |
+ ((unsigned int) AT91C_PA7_RTS0 ) |
+ ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A
+ ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for UDP */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_UDP ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_UDP));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for AIC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_IRQ0 ) |
- ( ( unsigned int ) 1 << AT91C_ID_FIQ ) |
- ( ( unsigned int ) 1 << AT91C_ID_IRQ1 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_IRQ0) |
+ ((unsigned int) 1 << AT91C_ID_FIQ) |
+ ((unsigned int) 1 << AT91C_ID_IRQ1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_CfgPIO */
-/** \brief Configure PIO controllers to drive AIC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA30_IRQ1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA20_IRQ0 ) |
- ( ( unsigned int ) AT91C_PA19_FIQ ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A
+ ((unsigned int) AT91C_PA20_IRQ0 ) |
+ ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B
}
#endif // lib_AT91SAM7S64_H
diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
index 3b2bdf0..805a2bc 100644
--- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
+++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
@@ -1,4332 +1,4558 @@
-/** ---------------------------------------------------------------------------- */
-/** ATMEL Microcontroller Software Support - ROUSSET - */
-/** ---------------------------------------------------------------------------- */
-/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/** ---------------------------------------------------------------------------- */
-/** File Name : lib_AT91SAM7X128.h */
-/** Object : AT91SAM7X128 inlined functions */
-/** Generated : AT91 SW Application Group 05/20/2005 (16:22:23) */
-/** */
-/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
-/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */
-/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */
-/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */
-/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
-/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */
-/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
-/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */
-/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */
-/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */
-/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */
-/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */
-/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */
-/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */
-/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */
-/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */
-/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
-/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */
-/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
-/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */
-/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
-/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */
-/** ---------------------------------------------------------------------------- */
+//* ----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name : lib_AT91SAM7X128.h
+//* Object : AT91SAM7X128 inlined functions
+//* Generated : AT91 SW Application Group 05/20/2005 (16:22:23)
+//*
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
+//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
#ifndef lib_AT91SAM7X128_H
#define lib_AT91SAM7X128_H
/* *****************************************************************************
-* SOFTWARE API FOR AIC
-***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */
+ SOFTWARE API FOR AIC
+ ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_ConfigureIt */
-/** \brief Interrupt Handler Initialization */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id, /* \arg interrupt number to initialize */
- unsigned int priority, /* \arg priority to give to the interrupt */
- unsigned int src_type, /* \arg activation and sense of activation */
- void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id, // \arg interrupt number to initialize
+ unsigned int priority, // \arg priority to give to the interrupt
+ unsigned int src_type, // \arg activation and sense of activation
+ void (*newHandler) (void) ) // \arg address of the interrupt handler
{
- unsigned int oldHandler;
- unsigned int mask;
+ unsigned int oldHandler;
+ unsigned int mask ;
- oldHandler = pAic->AIC_SVR[ irq_id ];
+ oldHandler = pAic->AIC_SVR[irq_id];
- mask = 0x1 << irq_id;
- /** Disable the interrupt on the interrupt controller */
- pAic->AIC_IDCR = mask;
- /** Save the interrupt handler routine pointer and the interrupt priority */
- pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;
- /** Store the Source Mode Register */
- pAic->AIC_SMR[ irq_id ] = src_type | priority;
- /** Clear the interrupt on the interrupt controller */
- pAic->AIC_ICCR = mask;
+ mask = 0x1 << irq_id ;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Save the interrupt handler routine pointer and the interrupt priority
+ pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+ //* Store the Source Mode Register
+ pAic->AIC_SMR[irq_id] = src_type | priority ;
+ //* Clear the interrupt on the interrupt controller
+ pAic->AIC_ICCR = mask ;
- return oldHandler;
+ return oldHandler;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_EnableIt */
-/** \brief Enable corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
{
- /** Enable the interrupt on the interrupt controller */
- pAic->AIC_IECR = 0x1 << irq_id;
+ //* Enable the interrupt on the interrupt controller
+ pAic->AIC_IECR = 0x1 << irq_id ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_DisableIt */
-/** \brief Disable corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
{
unsigned int mask = 0x1 << irq_id;
-
- /** Disable the interrupt on the interrupt controller */
- pAic->AIC_IDCR = mask;
- /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
- pAic->AIC_ICCR = mask;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = mask ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_ClearIt */
-/** \brief Clear corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number to initialize
{
- /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
- pAic->AIC_ICCR = ( 0x1 << irq_id );
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = (0x1 << irq_id);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_AcknowledgeIt */
-/** \brief Acknowledge corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+ AT91PS_AIC pAic) // \arg pointer to the AIC registers
{
pAic->AIC_EOICR = pAic->AIC_EOICR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_SetExceptionVector */
-/** \brief Configure vector handler */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */
- void ( * Handler )() ) /* \arg Interrupt Handler */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_SetExceptionVector (
+ unsigned int *pVector, // \arg pointer to the AIC registers
+ void (*Handler) () ) // \arg Interrupt Handler
{
- unsigned int oldVector = *pVector;
+ unsigned int oldVector = *pVector;
- if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE )
- {
- *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE;
- }
- else
- {
- *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000;
- }
+ if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+ *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+ else
+ *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
- return oldVector;
+ return oldVector;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_Trig */
-/** \brief Trig an IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Trig (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number
{
- pAic->AIC_ISCR = ( 0x1 << irq_id );
+ pAic->AIC_ISCR = (0x1 << irq_id) ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_IsActive */
-/** \brief Test if an IT is active */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg Interrupt Number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsActive (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
{
- return( pAic->AIC_ISR & ( 0x1 << irq_id ) );
+ return (pAic->AIC_ISR & (0x1 << irq_id));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_IsPending */
-/** \brief Test if an IT is pending */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg Interrupt Number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsPending (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
{
- return( pAic->AIC_IPR & ( 0x1 << irq_id ) );
+ return (pAic->AIC_IPR & (0x1 << irq_id));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_Open */
-/** \brief Set exception vectors and AIC registers to default values */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- void ( * IrqHandler )(), /* \arg Default IRQ vector exception */
- void ( * FiqHandler )(), /* \arg Default FIQ vector exception */
- void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */
- void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */
- unsigned int protectMode ) /* \arg Debug Control Register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ void (*IrqHandler) (), // \arg Default IRQ vector exception
+ void (*FiqHandler) (), // \arg Default FIQ vector exception
+ void (*DefaultHandler) (), // \arg Default Handler set in ISR
+ void (*SpuriousHandler) (), // \arg Default Spurious Handler
+ unsigned int protectMode) // \arg Debug Control Register
{
- int i;
+ int i;
- /* Disable all interrupts and set IVR to the default handler */
- for( i = 0; i < 32; ++i )
- {
- AT91F_AIC_DisableIt( pAic, i );
- AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler );
- }
+ // Disable all interrupts and set IVR to the default handler
+ for (i = 0; i < 32; ++i) {
+ AT91F_AIC_DisableIt(pAic, i);
+ AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
+ }
- /* Set the IRQ exception vector */
- AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler );
- /* Set the Fast Interrupt exception vector */
- AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler );
+ // Set the IRQ exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+ // Set the Fast Interrupt exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
- pAic->AIC_SPU = ( unsigned int ) SpuriousHandler;
- pAic->AIC_DCR = protectMode;
+ pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+ pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+ SOFTWARE API FOR PDC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RNPR = (unsigned int) address;
+ pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TNPR = (unsigned int) address;
+ pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RPR = (unsigned int) address;
+ pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TPR = (unsigned int) address;
+ pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+ //* Enable the RX and TX PDC transfer requests
+ AT91F_PDC_EnableRx(pPDC);
+ AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ if (AT91F_PDC_IsTxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ if (AT91F_PDC_IsRxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+/* *****************************************************************************
+ SOFTWARE API FOR DBGU
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be enabled
+{
+ pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be disabled
+{
+ pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+ AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller
+{
+ return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR PDC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetNextRx */
-/** \brief Set the next receive transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be received */
- unsigned int bytes ) /* \arg number of bytes to be received */
+ SOFTWARE API FOR PIO
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int periphAEnable, // \arg PERIPH A to enable
+ unsigned int periphBEnable) // \arg PERIPH B to enable
+
{
- pPDC->PDC_RNPR = ( unsigned int ) address;
- pPDC->PDC_RNCR = bytes;
+ pPio->PIO_ASR = periphAEnable;
+ pPio->PIO_BSR = periphBEnable;
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetNextTx */
-/** \brief Set the next transmit transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be transmitted */
- unsigned int bytes ) /* \arg number of bytes to be transmitted */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pioEnable) // \arg PIO to be enabled
{
- pPDC->PDC_TNPR = ( unsigned int ) address;
- pPDC->PDC_TNCR = bytes;
+ pPio->PIO_PER = pioEnable; // Set in PIO mode
+ pPio->PIO_OER = pioEnable; // Configure in Output
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetRx */
-/** \brief Set the receive transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be received */
- unsigned int bytes ) /* \arg number of bytes to be received */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputEnable) // \arg PIO to be enabled
{
- pPDC->PDC_RPR = ( unsigned int ) address;
- pPDC->PDC_RCR = bytes;
+ // Disable output
+ pPio->PIO_ODR = inputEnable;
+ pPio->PIO_PER = inputEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetTx */
-/** \brief Set the transmit transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be transmitted */
- unsigned int bytes ) /* \arg number of bytes to be transmitted */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int multiDrvEnable) // \arg pio to be configured in open drain
{
- pPDC->PDC_TPR = ( unsigned int ) address;
- pPDC->PDC_TCR = bytes;
+ // Configure the multi-drive option
+ pPio->PIO_MDDR = ~multiDrvEnable;
+ pPio->PIO_MDER = multiDrvEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_EnableTx */
-/** \brief Enable transmit */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pullupEnable) // \arg enable pullup on PIO
{
- pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+ // Connect or not Pullup
+ pPio->PIO_PPUDR = ~pullupEnable;
+ pPio->PIO_PPUER = pullupEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_EnableRx */
-/** \brief Enable receive */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int directDrive) // \arg PIO to be configured with direct drive
+
{
- pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+ // Configure the Direct Drive
+ pPio->PIO_OWDR = ~directDrive;
+ pPio->PIO_OWER = directDrive;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_DisableTx */
-/** \brief Disable transmit */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputFilter) // \arg PIO to be configured with input filter
+
{
- pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+ // Configure the Direct Drive
+ pPio->PIO_IFDR = ~inputFilter;
+ pPio->PIO_IFER = inputFilter;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_DisableRx */
-/** \brief Disable receive */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+ return pPio->PIO_PDSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsTxEmpty */
-/** \brief Test if the current transfer descriptor has been sent */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return !( pPDC->PDC_TCR );
+ return (AT91F_PIO_GetInput(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsNextTxEmpty */
-/** \brief Test if the next transfer descriptor has been moved to the current td */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be set
{
- return !( pPDC->PDC_TNCR );
+ pPio->PIO_SODR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsRxEmpty */
-/** \brief Test if the current transfer descriptor has been filled */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be cleared
{
- return !( pPDC->PDC_RCR );
+ pPio->PIO_CODR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsNextRxEmpty */
-/** \brief Test if the next transfer descriptor has been moved to the current td */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be forced
{
- return !( pPDC->PDC_RNCR );
+ pPio->PIO_ODSR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_Open */
-/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
{
- /** Disable the RX and TX PDC transfer requests */
- AT91F_PDC_DisableRx( pPDC );
- AT91F_PDC_DisableTx( pPDC );
-
- /** Reset all Counter register Next buffer first */
- AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
-
- /** Enable the RX and TX PDC transfer requests */
- AT91F_PDC_EnableRx( pPDC );
- AT91F_PDC_EnableTx( pPDC );
+ pPio->PIO_PER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_Close */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
{
- /** Disable the RX and TX PDC transfer requests */
- AT91F_PDC_DisableRx( pPDC );
- AT91F_PDC_DisableTx( pPDC );
-
- /** Reset all Counter register Next buffer first */
- AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+ pPio->PIO_PDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SendFrame */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- if( AT91F_PDC_IsTxEmpty( pPDC ) )
- {
- /** Buffer and next buffer can be initialized */
- AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer );
- AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer );
- return 2;
- }
- else if( AT91F_PDC_IsNextTxEmpty( pPDC ) )
- {
- /** Only one buffer can be initialized */
- AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer );
- return 1;
- }
- else
- {
- /** All buffer are in use... */
- return 0;
- }
+ return pPio->PIO_PSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_ReceiveFrame */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- if( AT91F_PDC_IsRxEmpty( pPDC ) )
- {
- /** Buffer and next buffer can be initialized */
- AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer );
- AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer );
- return 2;
- }
- else if( AT91F_PDC_IsNextRxEmpty( pPDC ) )
- {
- /** Only one buffer can be initialized */
- AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer );
- return 1;
- }
- else
- {
- /** All buffer are in use... */
- return 0;
- }
+ return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be enabled
+{
+ pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be disabled
+{
+ pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be enabled
+{
+ pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be disabled
+{
+ pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be enabled
+{
+ pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be disabled
+{
+ pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
+{
+ pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
+{
+ pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio A register selection
+{
+ pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio B register selection
+{
+ pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be enabled
+{
+ pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be disabled
+{
+ pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR DBGU
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_InterruptEnable */
-/** \brief Enable DBGU Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg dbgu interrupt to be enabled */
+ SOFTWARE API FOR PMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
{
- pDbgu->DBGU_IER = flag;
+ //* Write to the SCER register
+ pPMC->PMC_SCER = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_InterruptDisable */
-/** \brief Disable DBGU Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg dbgu interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
{
- pDbgu->DBGU_IDR = flag;
+ //* Write to the SCDR register
+ pPMC->PMC_SCDR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_GetInterruptMaskStatus */
-/** \brief Return DBGU Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */
- AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+ AT91PS_PMC pPMC // pointer to a CAN controller
+ )
{
- return pDbgu->DBGU_IMR;
+ return pPMC->PMC_SCSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_IsInterruptMasked */
-/** \brief Test if DBGU Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
{
- return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag );
+ pPMC->PMC_PCER = periphIds;
}
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
+{
+ pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+ return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int mode)
+{
+ pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int startup_time, // \arg main osc startup time in microsecond (us)
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+ pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
+{
+ pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+ return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ unsigned int reg = pPMC->PMC_MCKR;
+ unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+ unsigned int pllDivider, pllMultiplier;
+
+ switch (reg & AT91C_PMC_CSS) {
+ case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+ return slowClock / prescaler;
+ case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+ case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+ reg = pCKGR->CKGR_PLLR;
+ pllDivider = (reg & AT91C_CKGR_DIV);
+ pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+ }
+ return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck, // \arg Peripheral clock identifier 0 .. 7
+ unsigned int mode)
+{
+ pPMC->PMC_PCKR[pck] = mode;
+ pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck) // \arg Peripheral clock identifier 0 .. 7
+{
+ pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be enabled
+{
+ //* Write to the IER register
+ pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be disabled
+{
+ //* Write to the IDR register
+ pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+ return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+ return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+ SOFTWARE API FOR RSTC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+ AT91PS_RSTC pRSTC,
+ unsigned int reset)
+{
+ pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+ AT91PS_RSTC pRSTC,
+ unsigned int mode)
+{
+ pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+ AT91PS_RSTC pRSTC)
+{
+ return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+ AT91PS_RSTC pRSTC)
+{
+ return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+ AT91PS_RSTC pRSTC)
+{
+ return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
/* *****************************************************************************
-* SOFTWARE API FOR PIO
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgPeriph */
-/** \brief Enable pins to be drived by peripheral */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int periphAEnable, /* \arg PERIPH A to enable */
- unsigned int periphBEnable ) /* \arg PERIPH B to enable */
-
+ SOFTWARE API FOR RTTC
+ ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_SetRTT_TimeBase()
+//* \brief Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+ AT91PS_RTTC pRTTC,
+ unsigned int ms)
{
- pPio->PIO_ASR = periphAEnable;
- pPio->PIO_BSR = periphBEnable;
- pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */
+ if (ms > 2000)
+ return 1; // AT91C_TIME_OUT_OF_RANGE
+ pRTTC->RTTC_RTMR &= ~0xFFFF;
+ pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
+ return 0;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgOutput */
-/** \brief Enable PIO in output mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int pioEnable ) /* \arg PIO to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTSetPrescaler()
+//* \brief Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+ AT91PS_RTTC pRTTC,
+ unsigned int rtpres)
{
- pPio->PIO_PER = pioEnable; /* Set in PIO mode */
- pPio->PIO_OER = pioEnable; /* Configure in Output */
+ pRTTC->RTTC_RTMR &= ~0xFFFF;
+ pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
+ return (pRTTC->RTTC_RTMR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgInput */
-/** \brief Enable PIO in input mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int inputEnable ) /* \arg PIO to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTRestart()
+//* \brief Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+ AT91PS_RTTC pRTTC)
{
- /* Disable output */
- pPio->PIO_ODR = inputEnable;
- pPio->PIO_PER = inputEnable;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgOpendrain */
-/** \brief Configure PIO in open drain */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */
-{
- /* Configure the multi-drive option */
- pPio->PIO_MDDR = ~multiDrvEnable;
- pPio->PIO_MDER = multiDrvEnable;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgPullup */
-/** \brief Enable pullup on PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int pullupEnable ) /* \arg enable pullup on PIO */
-{
- /* Connect or not Pullup */
- pPio->PIO_PPUDR = ~pullupEnable;
- pPio->PIO_PPUER = pullupEnable;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgDirectDrive */
-/** \brief Enable direct drive on PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int directDrive ) /* \arg PIO to be configured with direct drive */
-
-{
- /* Configure the Direct Drive */
- pPio->PIO_OWDR = ~directDrive;
- pPio->PIO_OWER = directDrive;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgInputFilter */
-/** \brief Enable input filter on input PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int inputFilter ) /* \arg PIO to be configured with input filter */
-
-{
- /* Configure the Direct Drive */
- pPio->PIO_IFDR = ~inputFilter;
- pPio->PIO_IFER = inputFilter;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInput */
-/** \brief Return PIO input value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_PDSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInputSet */
-/** \brief Test if PIO is input flag is active */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInput( pPio ) & flag );
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_SetOutput */
-/** \brief Set to 1 output PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be set */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetAlarmINT()
+//* \brief Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_SODR = flag;
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_ClearOutput */
-/** \brief Set to 0 output PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be cleared */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ClearAlarmINT()
+//* \brief Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_CODR = flag;
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_ForceOutput */
-/** \brief Force output when Direct drive option is enabled */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be forced */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetRttIncINT()
+//* \brief Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_ODSR = flag;
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Enable */
-/** \brief Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ClearRttIncINT()
+//* \brief Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_PER = flag;
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Disable */
-/** \brief Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be disabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetAlarmValue()
+//* \brief Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+ AT91PS_RTTC pRTTC, unsigned int alarm)
{
- pPio->PIO_PDR = flag;
+ pRTTC->RTTC_RTAR = alarm;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetStatus */
-/** \brief Return PIO Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_GetAlarmValue()
+//* \brief Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+ AT91PS_RTTC pRTTC)
{
- return pPio->PIO_PSR;
+ return(pRTTC->RTTC_RTAR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsSet */
-/** \brief Test if PIO is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTGetStatus()
+//* \brief Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+ AT91PS_RTTC pRTTC)
{
- return( AT91F_PIO_GetStatus( pPio ) & flag );
+ return(pRTTC->RTTC_RTSR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputEnable */
-/** \brief Output Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ReadValue()
+//* \brief Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_OER = flag;
+ register volatile unsigned int val1,val2;
+ do
+ {
+ val1 = pRTTC->RTTC_RTVR;
+ val2 = pRTTC->RTTC_RTVR;
+ }
+ while(val1 != val2);
+ return(val1);
}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputDisable */
-/** \brief Output Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output to be disabled */
-{
- pPio->PIO_ODR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputStatus */
-/** \brief Return PIO Output Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_OSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOuputSet */
-/** \brief Test if PIO Output is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetOutputStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InputFilterEnable */
-/** \brief Input Filter Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio input filter to be enabled */
-{
- pPio->PIO_IFER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InputFilterDisable */
-/** \brief Input Filter Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio input filter to be disabled */
-{
- pPio->PIO_IFDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInputFilterStatus */
-/** \brief Return PIO Input Filter Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_IFSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInputFilterSet */
-/** \brief Test if PIO Input filter is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputDataStatus */
-/** \brief Return PIO Output Data Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_ODSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InterruptEnable */
-/** \brief Enable PIO Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio interrupt to be enabled */
-{
- pPio->PIO_IER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InterruptDisable */
-/** \brief Disable PIO Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio interrupt to be disabled */
-{
- pPio->PIO_IDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInterruptMaskStatus */
-/** \brief Return PIO Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_IMR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInterruptStatus */
-/** \brief Return PIO Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_ISR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInterruptMasked */
-/** \brief Test if PIO Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInterruptSet */
-/** \brief Test if PIO Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInterruptStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_MultiDriverEnable */
-/** \brief Multi Driver Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be enabled */
-{
- pPio->PIO_MDER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_MultiDriverDisable */
-/** \brief Multi Driver Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be disabled */
-{
- pPio->PIO_MDDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetMultiDriverStatus */
-/** \brief Return PIO Multi Driver Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_MDSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsMultiDriverSet */
-/** \brief Test if PIO MultiDriver is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_A_RegisterSelection */
-/** \brief PIO A Register Selection */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio A register selection */
-{
- pPio->PIO_ASR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_B_RegisterSelection */
-/** \brief PIO B Register Selection */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio B register selection */
-{
- pPio->PIO_BSR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Get_AB_RegisterStatus */
-/** \brief Return PIO Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_ABSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsAB_RegisterSet */
-/** \brief Test if PIO AB Register is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputWriteEnable */
-/** \brief Output Write Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output write to be enabled */
-{
- pPio->PIO_OWER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputWriteDisable */
-/** \brief Output Write Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output write to be disabled */
-{
- pPio->PIO_OWDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputWriteStatus */
-/** \brief Return PIO Output Write Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_OWSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOutputWriteSet */
-/** \brief Test if PIO OutputWrite is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetCfgPullup */
-/** \brief Return PIO Configuration Pullup */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_PPUSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOutputDataStatusSet */
-/** \brief Test if PIO Output Data Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsCfgPullupStatusSet */
-/** \brief Test if PIO Configuration Pullup Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag );
-}
-
/* *****************************************************************************
-* SOFTWARE API FOR PMC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgSysClkEnableReg */
-/** \brief Configure the System Clock Enable Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
+ SOFTWARE API FOR PITC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITInit
+//* \brief System timer init : period in µsecond, system clock freq in MHz
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITInit(
+ AT91PS_PITC pPITC,
+ unsigned int period,
+ unsigned int pit_frequency)
{
- /** Write to the SCER register */
- pPMC->PMC_SCER = mode;
+ pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+ pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgSysClkDisableReg */
-/** \brief Configure the System Clock Disable Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITSetPIV
+//* \brief Set the PIT Periodic Interval Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITSetPIV(
+ AT91PS_PITC pPITC,
+ unsigned int piv)
{
- /** Write to the SCDR register */
- pPMC->PMC_SCDR = mode;
+ pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetSysClkStatusReg */
-/** \brief Return the System Clock Status Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITEnableInt
+//* \brief Enable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITEnableInt(
+ AT91PS_PITC pPITC)
{
- return pPMC->PMC_SCSR;
+ pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnablePeriphClock */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITDisableInt
+//* \brief Disable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITDisableInt(
+ AT91PS_PITC pPITC)
{
- pPMC->PMC_PCER = periphIds;
+ pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisablePeriphClock */
-/** \brief Disable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetMode
+//* \brief Read PIT mode register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetMode(
+ AT91PS_PITC pPITC)
{
- pPMC->PMC_PCDR = periphIds;
+ return(pPITC->PITC_PIMR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetPeriphClock */
-/** \brief Get peripheral clock status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetStatus
+//* \brief Read PIT status register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetStatus(
+ AT91PS_PITC pPITC)
{
- return pPMC->PMC_PCSR;
+ return(pPITC->PITC_PISR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_CfgMainOscillatorReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetPIIR
+//* \brief Read PIT CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIIR(
+ AT91PS_PITC pPITC)
{
- pCKGR->CKGR_MOR = mode;
+ return(pPITC->PITC_PIIR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainOscillatorReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetPIVR
+//* \brief Read System timer CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIVR(
+ AT91PS_PITC pPITC)
{
- return pCKGR->CKGR_MOR;
+ return(pPITC->PITC_PIVR);
}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_EnableMainOscillator */
-/** \brief Enable the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
-{
- pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_DisableMainOscillator */
-/** \brief Disable the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
-{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_CfgMainOscStartUpTime */
-/** \brief Cfg MOR Register according to the main osc startup time */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
- unsigned int slowClock ) /* \arg slowClock in Hz */
-{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
- pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainClockFreqReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
-{
- return pCKGR->CKGR_MCFR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainClock */
-/** \brief Return Main clock in Hz */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int slowClock ) /* \arg slowClock in Hz */
-{
- return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgMCKReg */
-/** \brief Cfg Master Clock Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
-{
- pPMC->PMC_MCKR = mode;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetMCKReg */
-/** \brief Return Master Clock Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
-{
- return pPMC->PMC_MCKR;
-}
-
-/**------------------------------------------------------------------------------ */
-/** \fn AT91F_PMC_GetMasterClock */
-/** \brief Return master clock in Hz which correponds to processor clock for ARM7 */
-/**------------------------------------------------------------------------------ */
-__inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int slowClock ) /* \arg slowClock in Hz */
-{
- unsigned int reg = pPMC->PMC_MCKR;
- unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) );
- unsigned int pllDivider, pllMultiplier;
-
- switch( reg & AT91C_PMC_CSS )
- {
- case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */
- return slowClock / prescaler;
-
- case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */
- return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
-
- case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */
- reg = pCKGR->CKGR_PLLR;
- pllDivider = ( reg & AT91C_CKGR_DIV );
- pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
- return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
- }
-
- return 0;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnablePCK */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */
- unsigned int mode )
-{
- pPMC->PMC_PCKR[ pck ] = mode;
- pPMC->PMC_SCER = ( 1 << pck ) << 8;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisablePCK */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */
-{
- pPMC->PMC_SCDR = ( 1 << pck ) << 8;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnableIt */
-/** \brief Enable PMC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */
- unsigned int flag ) /* IT to be enabled */
-{
- /** Write to the IER register */
- pPMC->PMC_IER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisableIt */
-/** \brief Disable PMC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */
- unsigned int flag ) /* IT to be disabled */
-{
- /** Write to the IDR register */
- pPMC->PMC_IDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetStatus */
-/** \brief Return PMC Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */
- AT91PS_PMC pPMC ) /* pointer to a PMC controller */
-{
- return pPMC->PMC_SR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetInterruptMaskStatus */
-/** \brief Return PMC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */
- AT91PS_PMC pPMC ) /* pointer to a PMC controller */
-{
- return pPMC->PMC_IMR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_IsInterruptMasked */
-/** \brief Test if PMC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_IsStatusSet */
-/** \brief Test if PMC Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PMC_GetStatus( pPMC ) & flag );
-} /* *****************************************************************************
- * SOFTWARE API FOR RSTC
- ***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTSoftReset */
-/** \brief Start Software Reset */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC,
- unsigned int reset )
-{
- pRSTC->RSTC_RCR = ( 0xA5000000 | reset );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTSetMode */
-/** \brief Set Reset Mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC,
- unsigned int mode )
-{
- pRSTC->RSTC_RMR = ( 0xA5000000 | mode );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTGetMode */
-/** \brief Get Reset Mode */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC )
-{
- return( pRSTC->RSTC_RMR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTGetStatus */
-/** \brief Get Reset Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC )
-{
- return( pRSTC->RSTC_RSR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTIsSoftRstActive */
-/** \brief Return !=0 if software reset is still not completed */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC )
-{
- return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP );
-}
-
/* *****************************************************************************
-* SOFTWARE API FOR RTTC
-***************************************************************************** */
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_SetRTT_TimeBase() */
-/** \brief Set the RTT prescaler according to the TimeBase in ms */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC,
- unsigned int ms )
+ SOFTWARE API FOR WDTC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTSetMode
+//* \brief Set Watchdog Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTSetMode(
+ AT91PS_WDTC pWDTC,
+ unsigned int Mode)
{
- if( ms > 2000 )
- {
- return 1; /* AT91C_TIME_OUT_OF_RANGE */
- }
-
- pRTTC->RTTC_RTMR &= ~0xFFFF;
- pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF );
- return 0;
+ pWDTC->WDTC_WDMR = Mode;
}
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTTSetPrescaler() */
-/** \brief Set the new prescaler value */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC,
- unsigned int rtpres )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTRestart
+//* \brief Restart Watchdog
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTRestart(
+ AT91PS_WDTC pWDTC)
{
- pRTTC->RTTC_RTMR &= ~0xFFFF;
- pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF );
- return( pRTTC->RTTC_RTMR );
+ pWDTC->WDTC_WDCR = 0xA5000001;
}
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTTRestart() */
-/** \brief Restart the RTT prescaler */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTSGettatus
+//* \brief Get Watchdog Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTSGettatus(
+ AT91PS_WDTC pWDTC)
{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
+ return(pWDTC->WDTC_WDSR & 0x3);
}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_SetAlarmINT() */
-/** \brief Enable RTT Alarm Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTGetPeriod
+//* \brief Translate ms into Watchdog Compatible value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+ if ((ms < 4) || (ms > 16000))
+ return 0;
+ return((ms << 8) / 1000);
}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_ClearAlarmINT() */
-/** \brief Disable RTT Alarm Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_SetRttIncINT() */
-/** \brief Enable RTT INC Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_ClearRttIncINT() */
-/** \brief Disable RTT INC Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_SetAlarmValue() */
-/** \brief Set RTT Alarm Value */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC,
- unsigned int alarm )
-{
- pRTTC->RTTC_RTAR = alarm;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_GetAlarmValue() */
-/** \brief Get RTT Alarm Value */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC )
-{
- return( pRTTC->RTTC_RTAR );
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTTGetStatus() */
-/** \brief Read the RTT status */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC )
-{
- return( pRTTC->RTTC_RTSR );
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_ReadValue() */
-/** \brief Read the RTT value */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC )
-{
- register volatile unsigned int val1, val2;
-
- do
- {
- val1 = pRTTC->RTTC_RTVR;
- val2 = pRTTC->RTTC_RTVR;
- }
- while( val1 != val2 );
-
- return( val1 );
-}
-
/* *****************************************************************************
-* SOFTWARE API FOR PITC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITInit */
-/** \brief System timer init : period in µsecond, system clock freq in MHz */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITInit( AT91PS_PITC pPITC,
- unsigned int period,
- unsigned int pit_frequency )
+ SOFTWARE API FOR VREG
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_Enable_LowPowerMode
+//* \brief Enable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Enable_LowPowerMode(
+ AT91PS_VREG pVREG)
{
- pPITC->PITC_PIMR = period ? ( period * pit_frequency + 8 ) >> 4 : 0; /* +8 to avoid %10 and /10 */
- pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
+ pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITSetPIV */
-/** \brief Set the PIT Periodic Interval Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITSetPIV( AT91PS_PITC pPITC,
- unsigned int piv )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_Disable_LowPowerMode
+//* \brief Disable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Disable_LowPowerMode(
+ AT91PS_VREG pVREG)
{
- pPITC->PITC_PIMR = piv | ( pPITC->PITC_PIMR & ( AT91C_PITC_PITEN | AT91C_PITC_PITIEN ) );
-}
+ pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
+}/* *****************************************************************************
+ SOFTWARE API FOR MC
+ ***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITEnableInt */
-/** \brief Enable PIT periodic interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITEnableInt( AT91PS_PITC pPITC )
+#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void) //
{
- pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITDisableInt */
-/** \brief Disable PIT periodic interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITDisableInt( AT91PS_PITC pPITC )
-{
- pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetMode */
-/** \brief Read PIT mode register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetMode( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PIMR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetStatus */
-/** \brief Read PIT status register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetStatus( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PISR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetPIIR */
-/** \brief Read PIT CPIV and PICNT without ressetting the counters */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetPIIR( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PIIR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetPIVR */
-/** \brief Read System timer CPIV and PICNT without ressetting the counters */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetPIVR( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PIVR );
-}
-
-/* *****************************************************************************
-* SOFTWARE API FOR WDTC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTSetMode */
-/** \brief Set Watchdog Mode Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_WDTSetMode( AT91PS_WDTC pWDTC,
- unsigned int Mode )
-{
- pWDTC->WDTC_WDMR = Mode;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTRestart */
-/** \brief Restart Watchdog */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_WDTRestart( AT91PS_WDTC pWDTC )
-{
- pWDTC->WDTC_WDCR = 0xA5000001;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTSGettatus */
-/** \brief Get Watchdog Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_WDTSGettatus( AT91PS_WDTC pWDTC )
-{
- return( pWDTC->WDTC_WDSR & 0x3 );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTGetPeriod */
-/** \brief Translate ms into Watchdog Compatible value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_WDTGetPeriod( unsigned int ms )
-{
- if( ( ms < 4 ) || ( ms > 16000 ) )
- {
- return 0;
- }
-
- return( ( ms << 8 ) / 1000 );
-}
-
-/* *****************************************************************************
-* SOFTWARE API FOR VREG
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_VREG_Enable_LowPowerMode */
-/** \brief Enable VREG Low Power Mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_VREG_Enable_LowPowerMode( AT91PS_VREG pVREG )
-{
- pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_VREG_Disable_LowPowerMode */
-/** \brief Disable VREG Low Power Mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_VREG_Disable_LowPowerMode( AT91PS_VREG pVREG )
-{
- pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
-} /* *****************************************************************************
- * SOFTWARE API FOR MC
- ***************************************************************************** */
-
-#define AT91C_MC_CORRECT_KEY ( ( unsigned int ) 0x5A << 24 ) /* (MC) Correct Protect Key */
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_Remap */
-/** \brief Make Remap */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_Remap( void ) /* */
-{
- AT91PS_MC pMC = ( AT91PS_MC ) AT91C_BASE_MC;
-
+ AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+
pMC->MC_RCR = AT91C_MC_RCB;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_CfgModeReg */
-/** \brief Configure the EFC Mode Register of the MC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, /* pointer to a MC controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+ AT91PS_MC pMC, // pointer to a MC controller
+ unsigned int mode) // mode register
{
- /* Write to the FMR register */
- pMC->MC_FMR = mode;
+ // Write to the FMR register
+ pMC->MC_FMR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_GetModeReg */
-/** \brief Return MC EFC Mode Regsiter */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+ AT91PS_MC pMC) // pointer to a MC controller
{
- return pMC->MC_FMR;
+ return pMC->MC_FMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_ComputeFMCN */
-/** \brief Return MC EFC Mode Regsiter */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+ int master_clock) // master clock in Hz
{
- return( master_clock / 1000000 + 2 );
+ return (master_clock/1000000 +2);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_PerformCmd */
-/** \brief Perform EFC Command */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_EFC_PerformCmd( AT91PS_MC pMC, /* pointer to a MC controller */
- unsigned int transfer_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+ AT91PS_MC pMC, // pointer to a MC controller
+ unsigned int transfer_cmd)
{
- pMC->MC_FCR = transfer_cmd;
+ pMC->MC_FCR = transfer_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_GetStatus */
-/** \brief Return MC EFC Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_GetStatus( AT91PS_MC pMC ) /* pointer to a MC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+ AT91PS_MC pMC) // pointer to a MC controller
{
- return pMC->MC_FSR;
+ return pMC->MC_FSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_IsInterruptMasked */
-/** \brief Test if EFC MC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( AT91PS_MC pMC, /* \arg pointer to a MC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+ AT91PS_MC pMC, // \arg pointer to a MC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_MC_EFC_GetModeReg( pMC ) & flag );
+ return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_IsInterruptSet */
-/** \brief Test if EFC MC Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, /* \arg pointer to a MC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+ AT91PS_MC pMC, // \arg pointer to a MC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_MC_EFC_GetStatus( pMC ) & flag );
+ return (AT91F_MC_EFC_GetStatus(pMC) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR SPI
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Open */
-/** \brief Open a SPI Port */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_Open( const unsigned int null ) /* \arg */
+ SOFTWARE API FOR SPI
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+ const unsigned int null) // \arg
{
- /* NOT DEFINED AT THIS MOMENT */
- return( 0 );
+ /* NOT DEFINED AT THIS MOMENT */
+ return ( 0 );
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgCs */
-/** \brief Configure SPI chip select register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgCs( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- int cs, /* SPI cs number (0 to 3) */
- int val ) /* chip select register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ int cs, // SPI cs number (0 to 3)
+ int val) // chip select register
{
- /** Write to the CSR register */
- *( pSPI->SPI_CSR + cs ) = val;
+ //* Write to the CSR register
+ *(pSPI->SPI_CSR + cs) = val;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_EnableIt */
-/** \brief Enable SPI interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_EnableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pSPI->SPI_IER = flag;
+ //* Write to the IER register
+ pSPI->SPI_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_DisableIt */
-/** \brief Disable SPI interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_DisableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pSPI->SPI_IDR = flag;
+ //* Write to the IDR register
+ pSPI->SPI_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Reset */
-/** \brief Reset the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Reset( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
- pSPI->SPI_CR = AT91C_SPI_SWRST;
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Enable */
-/** \brief Enable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Enable( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
- pSPI->SPI_CR = AT91C_SPI_SPIEN;
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Disable */
-/** \brief Disable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Disable( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ int mode) // mode register
+{
+ //* Write to the MR register
+ pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ char PCS_Device) // PCS of the Device
+{
+ //* Write to the MR register
+ pSPI->SPI_MR &= 0xFFF0FFFF;
+ pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+ AT91PS_SPI pSPI,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pSPI->SPI_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+ AT91PS_SPI pSPI,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pSPI->SPI_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+ AT91PS_SPI pSPI) // \arg pointer to a SPI controller
+{
+ //* Reset all the Chip Select register
+ pSPI->SPI_CSR[0] = 0 ;
+ pSPI->SPI_CSR[1] = 0 ;
+ pSPI->SPI_CSR[2] = 0 ;
+ pSPI->SPI_CSR[3] = 0 ;
+
+ //* Reset the SPI mode
+ pSPI->SPI_MR = 0 ;
+
+ //* Disable all interrupts
+ pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+ //* Abort the Peripheral Data Transfers
+ AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+ //* Disable receiver and transmitter and stop any activity immediately
pSPI->SPI_CR = AT91C_SPI_SPIDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgMode */
-/** \brief Enable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgMode( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- int mode ) /* mode register */
-{
- /** Write to the MR register */
- pSPI->SPI_MR = mode;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgPCS */
-/** \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgPCS( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- char PCS_Device ) /* PCS of the Device */
-{
- /** Write to the MR register */
- pSPI->SPI_MR &= 0xFFF0FFFF;
- pSPI->SPI_MR |= ( ( PCS_Device << 16 ) & AT91C_SPI_PCS );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_ReceiveFrame( AT91PS_SPI pSPI,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Close */
-/** \brief Close SPI: disable IT disable transfert, close PDC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */
-{
- /** Reset all the Chip Select register */
- pSPI->SPI_CSR[ 0 ] = 0;
- pSPI->SPI_CSR[ 1 ] = 0;
- pSPI->SPI_CSR[ 2 ] = 0;
- pSPI->SPI_CSR[ 3 ] = 0;
-
- /** Reset the SPI mode */
- pSPI->SPI_MR = 0;
-
- /** Disable all interrupts */
- pSPI->SPI_IDR = 0xFFFFFFFF;
-
- /** Abort the Peripheral Data Transfers */
- AT91F_PDC_Close( ( AT91PS_PDC ) &( pSPI->SPI_RPR ) );
-
- /** Disable receiver and transmitter and stop any activity immediately */
- pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_PutChar */
-/** \brief Send a character,does not check if ready to send */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_PutChar( AT91PS_SPI pSPI,
- unsigned int character,
- unsigned int cs_number )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+ AT91PS_SPI pSPI,
+ unsigned int character,
+ unsigned int cs_number )
{
unsigned int value_for_cs;
-
- value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; /*Place a zero among a 4 ONEs number */
- pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 );
+ value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number
+ pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_GetChar */
-/** \brief Receive a character,does not check if a character is available */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SPI_GetChar( const AT91PS_SPI pSPI )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+ const AT91PS_SPI pSPI)
{
- return( ( pSPI->SPI_RDR ) & 0xFFFF );
+ return((pSPI->SPI_RDR) & 0xFFFF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_GetInterruptMaskStatus */
-/** \brief Return SPI Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( /* \return SPI Interrupt Mask Status */
- AT91PS_SPI pSpi ) /* \arg pointer to a SPI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+ AT91PS_SPI pSpi) // \arg pointer to a SPI controller
{
- return pSpi->SPI_IMR;
+ return pSpi->SPI_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_IsInterruptMasked */
-/** \brief Test if SPI Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi, /* \arg pointer to a SPI controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+ AT91PS_SPI pSpi, // \arg pointer to a SPI controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_SPI_GetInterruptMaskStatus( pSpi ) & flag );
+ return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR USART
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Baudrate */
-/** \brief Calculate the baudrate */
-/** Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_ASYNC_MODE \
- ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+ SOFTWARE API FOR USART
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/** Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_ASYNC_SCK_MODE \
- ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_EXT )
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_EXT )
-/** Standard Synchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_SYNC_MODE \
- ( AT91C_US_SYNC + \
- AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+ AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/** SCK used Label */
-#define AT91C_US_SCK_USED ( AT91C_US_CKLO | AT91C_US_CLKS_EXT )
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-/** Standard ISO T=0 Mode : 8 bits , 1 stop , parity */
-#define AT91C_US_ISO_READER_MODE \
- ( AT91C_US_USMODE_ISO7816_0 + \
- AT91C_US_CLKS_CLOCK + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_EVEN + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CKLO + \
- AT91C_US_OVER )
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+ AT91C_US_CLKS_CLOCK +\
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_EVEN + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CKLO +\
+ AT91C_US_OVER)
-/** Standard IRDA mode */
-#define AT91C_US_ASYNC_IRDA_MODE \
- ( AT91C_US_USMODE_IRDA + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Baudrate */
-/** \brief Caluculate baud_value according to the main clock and the baud rate */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_Baudrate( const unsigned int main_clock, /* \arg peripheral clock */
- const unsigned int baud_rate ) /* \arg UART baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+ const unsigned int main_clock, // \arg peripheral clock
+ const unsigned int baud_rate) // \arg UART baudrate
{
- unsigned int baud_value = ( ( main_clock * 10 ) / ( baud_rate * 16 ) );
-
- if( ( baud_value % 10 ) >= 5 )
- {
- baud_value = ( baud_value / 10 ) + 1;
- }
- else
- {
- baud_value /= 10;
- }
-
- return baud_value;
+ unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+ if ((baud_value % 10) >= 5)
+ baud_value = (baud_value / 10) + 1;
+ else
+ baud_value /= 10;
+ return baud_value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetBaudrate */
-/** \brief Set the baudrate according to the CPU clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetBaudrate( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int speed ) /* \arg UART baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int speed) // \arg UART baudrate
{
- /** Define the baud rate divisor register */
- pUSART->US_BRGR = AT91F_US_Baudrate( mainClock, speed );
+ //* Define the baud rate divisor register
+ pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetTimeguard */
-/** \brief Set USART timeguard */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetTimeguard( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int timeguard ) /* \arg timeguard value */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int timeguard) // \arg timeguard value
{
- /** Write the Timeguard Register */
- pUSART->US_TTGR = timeguard;
+ //* Write the Timeguard Register
+ pUSART->US_TTGR = timeguard ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableIt */
-/** \brief Enable USART IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int flag ) /* \arg IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pUSART->US_IER = flag;
+ //* Write to the IER register
+ pUSART->US_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableIt */
-/** \brief Disable USART IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IER register */
- pUSART->US_IDR = flag;
+ //* Write to the IER register
+ pUSART->US_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Configure */
-/** \brief Configure USART */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_Configure( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int mode, /* \arg mode Register to be programmed */
- unsigned int baudRate, /* \arg baudrate to be programmed */
- unsigned int timeguard ) /* \arg timeguard to be programmed */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int mode , // \arg mode Register to be programmed
+ unsigned int baudRate , // \arg baudrate to be programmed
+ unsigned int timeguard ) // \arg timeguard to be programmed
{
- /** Disable interrupts */
- pUSART->US_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pUSART->US_IDR = (unsigned int) -1;
- /** Reset receiver and transmitter */
- pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
+ //* Reset receiver and transmitter
+ pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
- /** Define the baud rate divisor register */
- AT91F_US_SetBaudrate( pUSART, mainClock, baudRate );
+ //* Define the baud rate divisor register
+ AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
- /** Write the Timeguard Register */
- AT91F_US_SetTimeguard( pUSART, timeguard );
+ //* Write the Timeguard Register
+ AT91F_US_SetTimeguard(pUSART, timeguard);
- /** Clear Transmit and Receive Counters */
- AT91F_PDC_Open( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
+ //* Clear Transmit and Receive Counters
+ AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
- /** Define the USART mode */
- pUSART->US_MR = mode;
+ //* Define the USART mode
+ pUSART->US_MR = mode ;
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableRx */
-/** \brief Enable receiving characters */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Enable receiver */
+ //* Enable receiver
pUSART->US_CR = AT91C_US_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableTx */
-/** \brief Enable sending characters */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Enable transmitter */
+ //* Enable transmitter
pUSART->US_CR = AT91C_US_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ResetRx */
-/** \brief Reset Receiver and re-enable it */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_ResetRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset receiver */
- pUSART->US_CR = AT91C_US_RSTRX;
- /** Re-Enable receiver */
+ //* Reset receiver
+ pUSART->US_CR = AT91C_US_RSTRX;
+ //* Re-Enable receiver
pUSART->US_CR = AT91C_US_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ResetTx */
-/** \brief Reset Transmitter and re-enable it */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_ResetTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset transmitter */
- pUSART->US_CR = AT91C_US_RSTTX;
- /** Enable transmitter */
+ //* Reset transmitter
+ pUSART->US_CR = AT91C_US_RSTTX;
+ //* Enable transmitter
pUSART->US_CR = AT91C_US_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableRx */
-/** \brief Disable Receiver */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Disable receiver */
+ //* Disable receiver
pUSART->US_CR = AT91C_US_RXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableTx */
-/** \brief Disable Transmitter */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Disable transmitter */
+ //* Disable transmitter
pUSART->US_CR = AT91C_US_TXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Close */
-/** \brief Close USART: disable IT disable receiver and transmitter, close PDC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_Close( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset the baud rate divisor register */
- pUSART->US_BRGR = 0;
+ //* Reset the baud rate divisor register
+ pUSART->US_BRGR = 0 ;
- /** Reset the USART mode */
- pUSART->US_MR = 0;
+ //* Reset the USART mode
+ pUSART->US_MR = 0 ;
- /** Reset the Timeguard Register */
+ //* Reset the Timeguard Register
pUSART->US_TTGR = 0;
- /** Disable all interrupts */
- pUSART->US_IDR = 0xFFFFFFFF;
+ //* Disable all interrupts
+ pUSART->US_IDR = 0xFFFFFFFF ;
- /** Abort the Peripheral Data Transfers */
- AT91F_PDC_Close( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
+ //* Abort the Peripheral Data Transfers
+ AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
- /** Disable receiver and transmitter and stop any activity immediately */
- pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
+ //* Disable receiver and transmitter and stop any activity immediately
+ pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_TxReady */
-/** \brief Return 1 if a character can be written in US_THR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_TxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR & AT91C_US_TXRDY );
+ return (pUSART->US_CSR & AT91C_US_TXRDY);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_RxReady */
-/** \brief Return 1 if a character can be read in US_RHR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_RxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR & AT91C_US_RXRDY );
+ return (pUSART->US_CSR & AT91C_US_RXRDY);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Error */
-/** \brief Return the error flag */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_Error( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR &
- ( AT91C_US_OVRE | /* Overrun error */
- AT91C_US_FRAME | /* Framing error */
- AT91C_US_PARE ) ); /* Parity error */
+ return (pUSART->US_CSR &
+ (AT91C_US_OVRE | // Overrun error
+ AT91C_US_FRAME | // Framing error
+ AT91C_US_PARE)); // Parity error
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_PutChar */
-/** \brief Send a character,does not check if ready to send */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_PutChar( AT91PS_USART pUSART,
- int character )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+ AT91PS_USART pUSART,
+ int character )
{
- pUSART->US_THR = ( character & 0x1FF );
+ pUSART->US_THR = (character & 0x1FF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_GetChar */
-/** \brief Receive a character,does not check if a character is available */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_US_GetChar( const AT91PS_USART pUSART )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+ const AT91PS_USART pUSART)
{
- return( ( pUSART->US_RHR ) & 0x1FF );
+ return((pUSART->US_RHR) & 0x1FF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_SendFrame( AT91PS_USART pUSART,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+ AT91PS_USART pUSART,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pUSART->US_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pUSART->US_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_ReceiveFrame( AT91PS_USART pUSART,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+ AT91PS_USART pUSART,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pUSART->US_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pUSART->US_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetIrdaFilter */
-/** \brief Set the value of IrDa filter tregister */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetIrdaFilter( AT91PS_USART pUSART,
- unsigned char value )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+ AT91PS_USART pUSART,
+ unsigned char value
+)
{
- pUSART->US_IF = value;
+ pUSART->US_IF = value;
}
/* *****************************************************************************
-* SOFTWARE API FOR SSC
-***************************************************************************** */
-/** Define the standard I2S mode configuration */
+ SOFTWARE API FOR SSC
+ ***************************************************************************** */
+//* Define the standard I2S mode configuration
-/** Configuration to set in the SSC Transmit Clock Mode Register */
-/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
-/** nb_slot_by_frame : number of channels */
-#define AT91C_I2S_ASY_MASTER_TX_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
- ( + \
- AT91C_SSC_CKS_DIV + \
- AT91C_SSC_CKO_CONTINOUS + \
- AT91C_SSC_CKG_NONE + \
- AT91C_SSC_START_FALL_RF + \
- AT91C_SSC_STTOUT + \
- ( ( 1 << 16 ) & AT91C_SSC_STTDLY ) + \
- ( ( ( ( nb_bit_by_slot * nb_slot_by_frame ) / 2 ) - 1 ) << 24 ) )
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ AT91C_SSC_CKS_DIV +\
+ AT91C_SSC_CKO_CONTINOUS +\
+ AT91C_SSC_CKG_NONE +\
+ AT91C_SSC_START_FALL_RF +\
+ AT91C_SSC_STTOUT +\
+ ((1<<16) & AT91C_SSC_STTDLY) +\
+ ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
-/** Configuration to set in the SSC Transmit Frame Mode Register */
-/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
-/** nb_slot_by_frame : number of channels */
-#define AT91C_I2S_ASY_TX_FRAME_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
- ( + \
- ( nb_bit_by_slot - 1 ) + \
- AT91C_SSC_MSBF + \
- ( ( ( nb_slot_by_frame - 1 ) << 8 ) & AT91C_SSC_DATNB ) + \
- ( ( ( nb_bit_by_slot - 1 ) << 16 ) & AT91C_SSC_FSLEN ) + \
- AT91C_SSC_FSOS_NEGATIVE )
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ (nb_bit_by_slot-1) +\
+ AT91C_SSC_MSBF +\
+ (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
+ (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+ AT91C_SSC_FSOS_NEGATIVE)
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_SetBaudrate */
-/** \brief Set the baudrate according to the CPU clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_SetBaudrate( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int speed ) /* \arg SSC baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int speed) // \arg SSC baudrate
{
- unsigned int baud_value;
-
- /** Define the baud rate divisor register */
- if( speed == 0 )
- {
- baud_value = 0;
- }
- else
- {
- baud_value = ( unsigned int ) ( mainClock * 10 ) / ( 2 * speed );
-
- if( ( baud_value % 10 ) >= 5 )
- {
- baud_value = ( baud_value / 10 ) + 1;
- }
+ unsigned int baud_value;
+ //* Define the baud rate divisor register
+ if (speed == 0)
+ baud_value = 0;
else
{
- baud_value /= 10;
+ baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+ if ((baud_value % 10) >= 5)
+ baud_value = (baud_value / 10) + 1;
+ else
+ baud_value /= 10;
}
- }
- pSSC->SSC_CMR = baud_value;
+ pSSC->SSC_CMR = baud_value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_Configure */
-/** \brief Configure SSC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_Configure( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int syst_clock, /* \arg System Clock Frequency */
- unsigned int baud_rate, /* \arg Expected Baud Rate Frequency */
- unsigned int clock_rx, /* \arg Receiver Clock Parameters */
- unsigned int mode_rx, /* \arg mode Register to be programmed */
- unsigned int clock_tx, /* \arg Transmitter Clock Parameters */
- unsigned int mode_tx ) /* \arg mode Register to be programmed */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int syst_clock, // \arg System Clock Frequency
+ unsigned int baud_rate, // \arg Expected Baud Rate Frequency
+ unsigned int clock_rx, // \arg Receiver Clock Parameters
+ unsigned int mode_rx, // \arg mode Register to be programmed
+ unsigned int clock_tx, // \arg Transmitter Clock Parameters
+ unsigned int mode_tx) // \arg mode Register to be programmed
{
- /** Disable interrupts */
- pSSC->SSC_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pSSC->SSC_IDR = (unsigned int) -1;
- /** Reset receiver and transmitter */
- pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS;
+ //* Reset receiver and transmitter
+ pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
- /** Define the Clock Mode Register */
- AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate );
+ //* Define the Clock Mode Register
+ AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
- /** Write the Receive Clock Mode Register */
- pSSC->SSC_RCMR = clock_rx;
+ //* Write the Receive Clock Mode Register
+ pSSC->SSC_RCMR = clock_rx;
- /** Write the Transmit Clock Mode Register */
- pSSC->SSC_TCMR = clock_tx;
+ //* Write the Transmit Clock Mode Register
+ pSSC->SSC_TCMR = clock_tx;
- /** Write the Receive Frame Mode Register */
- pSSC->SSC_RFMR = mode_rx;
+ //* Write the Receive Frame Mode Register
+ pSSC->SSC_RFMR = mode_rx;
- /** Write the Transmit Frame Mode Register */
- pSSC->SSC_TFMR = mode_tx;
+ //* Write the Transmit Frame Mode Register
+ pSSC->SSC_TFMR = mode_tx;
- /** Clear Transmit and Receive Counters */
- AT91F_PDC_Open( ( AT91PS_PDC ) &( pSSC->SSC_RPR ) );
+ //* Clear Transmit and Receive Counters
+ AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableRx */
-/** \brief Enable receiving datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Enable receiver */
+ //* Enable receiver
pSSC->SSC_CR = AT91C_SSC_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableRx */
-/** \brief Disable receiving datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Disable receiver */
+ //* Disable receiver
pSSC->SSC_CR = AT91C_SSC_RXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableTx */
-/** \brief Enable sending datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Enable transmitter */
+ //* Enable transmitter
pSSC->SSC_CR = AT91C_SSC_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableTx */
-/** \brief Disable sending datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Disable transmitter */
+ //* Disable transmitter
pSSC->SSC_CR = AT91C_SSC_TXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableIt */
-/** \brief Enable SSC IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pSSC->SSC_IER = flag;
+ //* Write to the IER register
+ pSSC->SSC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableIt */
-/** \brief Disable SSC IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pSSC->SSC_IDR = flag;
+ //* Write to the IDR register
+ pSSC->SSC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_ReceiveFrame( AT91PS_SSC pSSC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+ AT91PS_SSC pSSC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pSSC->SSC_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_SendFrame( AT91PS_SSC pSSC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+ AT91PS_SSC pSSC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pSSC->SSC_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_GetInterruptMaskStatus */
-/** \brief Return SSC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( /* \return SSC Interrupt Mask Status */
- AT91PS_SSC pSsc ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+ AT91PS_SSC pSsc) // \arg pointer to a SSC controller
{
- return pSsc->SSC_IMR;
+ return pSsc->SSC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_IsInterruptMasked */
-/** \brief Test if SSC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+ AT91PS_SSC pSsc, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_SSC_GetInterruptMaskStatus( pSsc ) & flag );
+ return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR TWI
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_EnableIt */
-/** \brief Enable TWI IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_EnableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg IT to be enabled */
+ SOFTWARE API FOR TWI
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pTWI->TWI_IER = flag;
+ //* Write to the IER register
+ pTWI->TWI_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_DisableIt */
-/** \brief Disable TWI IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_DisableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pTWI->TWI_IDR = flag;
+ //* Write to the IDR register
+ pTWI->TWI_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_Configure */
-/** \brief Configure TWI in master mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_Configure( AT91PS_TWI pTWI ) /* \arg pointer to a TWI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller
{
- /** Disable interrupts */
- pTWI->TWI_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pTWI->TWI_IDR = (unsigned int) -1;
- /** Reset peripheral */
- pTWI->TWI_CR = AT91C_TWI_SWRST;
+ //* Reset peripheral
+ pTWI->TWI_CR = AT91C_TWI_SWRST;
- /** Set Master mode */
- pTWI->TWI_CR = AT91C_TWI_MSEN;
+ //* Set Master mode
+ pTWI->TWI_CR = AT91C_TWI_MSEN;
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_GetInterruptMaskStatus */
-/** \brief Return TWI Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( /* \return TWI Interrupt Mask Status */
- AT91PS_TWI pTwi ) /* \arg pointer to a TWI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+ AT91PS_TWI pTwi) // \arg pointer to a TWI controller
{
- return pTwi->TWI_IMR;
+ return pTwi->TWI_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_IsInterruptMasked */
-/** \brief Test if TWI Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+ AT91PS_TWI pTwi, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_TWI_GetInterruptMaskStatus( pTwi ) & flag );
+ return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR PWMC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_GetStatus */
-/** \brief Return PWM Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_GetStatus( /* \return PWM Interrupt Status */
- AT91PS_PWMC pPWM ) /* pointer to a PWM controller */
+ SOFTWARE API FOR PWMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+ AT91PS_PWMC pPWM) // pointer to a PWM controller
{
- return pPWM->PWMC_SR;
+ return pPWM->PWMC_SR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_InterruptEnable */
-/** \brief Enable PWM Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_InterruptEnable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg PWM interrupt to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg PWM interrupt to be enabled
{
- pPwm->PWMC_IER = flag;
+ pPwm->PWMC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_InterruptDisable */
-/** \brief Disable PWM Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_InterruptDisable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg PWM interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg PWM interrupt to be disabled
{
- pPwm->PWMC_IDR = flag;
+ pPwm->PWMC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_GetInterruptMaskStatus */
-/** \brief Return PWM Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( /* \return PWM Interrupt Mask Status */
- AT91PS_PWMC pPwm ) /* \arg pointer to a PWM controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+ AT91PS_PWMC pPwm) // \arg pointer to a PWM controller
{
- return pPwm->PWMC_IMR;
+ return pPwm->PWMC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_IsInterruptMasked */
-/** \brief Test if PWM Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_IsInterruptMasked( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PWMC_GetInterruptMaskStatus( pPWM ) & flag );
+ return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_IsStatusSet */
-/** \brief Test if PWM Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_IsStatusSet( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PWMC_GetStatus( pPWM ) & flag );
+ return (AT91F_PWMC_GetStatus(pPWM) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_CfgChannel */
-/** \brief Test if PWM Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int channelId, /* \arg PWM channel ID */
- unsigned int mode, /* \arg PWM mode */
- unsigned int period, /* \arg PWM period */
- unsigned int duty ) /* \arg PWM duty cycle */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int channelId, // \arg PWM channel ID
+ unsigned int mode, // \arg PWM mode
+ unsigned int period, // \arg PWM period
+ unsigned int duty) // \arg PWM duty cycle
{
- pPWM->PWMC_CH[ channelId ].PWMC_CMR = mode;
- pPWM->PWMC_CH[ channelId ].PWMC_CDTYR = duty;
- pPWM->PWMC_CH[ channelId ].PWMC_CPRDR = period;
+ pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+ pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+ pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_StartChannel */
-/** \brief Enable channel */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_ENA = flag;
+ pPWM->PWMC_ENA = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_StopChannel */
-/** \brief Disable channel */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_DIS = flag;
+ pPWM->PWMC_DIS = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_UpdateChannel */
-/** \brief Update Period or Duty Cycle */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int channelId, /* \arg PWM channel ID */
- unsigned int update ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int channelId, // \arg PWM channel ID
+ unsigned int update) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_CH[ channelId ].PWMC_CUPDR = update;
+ pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
}
/* *****************************************************************************
-* SOFTWARE API FOR UDP
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EnableIt */
-/** \brief Enable UDP IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EnableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg IT to be enabled */
+ SOFTWARE API FOR UDP
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pUDP->UDP_IER = flag;
+ //* Write to the IER register
+ pUDP->UDP_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_DisableIt */
-/** \brief Disable UDP IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_DisableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pUDP->UDP_IDR = flag;
+ //* Write to the IDR register
+ pUDP->UDP_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_SetAddress */
-/** \brief Set UDP functional address */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_SetAddress( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char address ) /* \arg new UDP address */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char address) // \arg new UDP address
{
- pUDP->UDP_FADDR = ( AT91C_UDP_FEN | address );
+ pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EnableEp */
-/** \brief Enable Endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EnableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_EPEDS;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_DisableEp */
-/** \brief Enable Endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_DisableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] &= ~AT91C_UDP_EPEDS;
+ pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_SetState */
-/** \brief Set UDP Device state */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_SetState( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg new UDP address */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg new UDP address
{
- pUDP->UDP_GLBSTATE &= ~( AT91C_UDP_FADDEN | AT91C_UDP_CONFG );
- pUDP->UDP_GLBSTATE |= flag;
+ pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+ pUDP->UDP_GLBSTATE |= flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_GetState */
-/** \brief return UDP Device state */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_GetState( /* \return the UDP device state */
- AT91PS_UDP pUDP ) /* \arg pointer to a UDP controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+ AT91PS_UDP pUDP) // \arg pointer to a UDP controller
{
- return( pUDP->UDP_GLBSTATE & ( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ) );
+ return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_ResetEp */
-/** \brief Reset UDP endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_ResetEp( /* \return the UDP device state */
- AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg Endpoints to be reset */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg Endpoints to be reset
{
- pUDP->UDP_RSTEP = flag;
- pUDP->UDP_RSTEP = 0;
+ pUDP->UDP_RSTEP = flag;
+ pUDP->UDP_RSTEP = 0;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpStall */
-/** \brief Endpoint will STALL requests */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpStall( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_FORCESTALL;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpWrite */
-/** \brief Write value in the DPR */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpWrite( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned char value ) /* \arg value to be written in the DPR */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned char value) // \arg value to be written in the DPR
{
- pUDP->UDP_FDR[ endpoint ] = value;
+ pUDP->UDP_FDR[endpoint] = value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpRead */
-/** \brief Return value from the DPR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_EpRead( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- return pUDP->UDP_FDR[ endpoint ];
+ return pUDP->UDP_FDR[endpoint];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpEndOfWr */
-/** \brief Notify the UDP that values in DPR are ready to be sent */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpEndOfWr( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_TXPKTRDY;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpClear */
-/** \brief Clear flag in the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpClear( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned int flag ) /* \arg flag to be cleared */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned int flag) // \arg flag to be cleared
{
- pUDP->UDP_CSR[ endpoint ] &= ~( flag );
+ pUDP->UDP_CSR[endpoint] &= ~(flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpSet */
-/** \brief Set flag in the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpSet( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned int flag ) /* \arg flag to be cleared */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned int flag) // \arg flag to be cleared
{
- pUDP->UDP_CSR[ endpoint ] |= flag;
+ pUDP->UDP_CSR[endpoint] |= flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpStatus */
-/** \brief Return the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_EpStatus( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- return pUDP->UDP_CSR[ endpoint ];
+ return pUDP->UDP_CSR[endpoint];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_GetInterruptMaskStatus */
-/** \brief Return UDP Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( /* \return UDP Interrupt Mask Status */
- AT91PS_UDP pUdp ) /* \arg pointer to a UDP controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+ AT91PS_UDP pUdp) // \arg pointer to a UDP controller
{
- return pUdp->UDP_IMR;
+ return pUdp->UDP_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_IsInterruptMasked */
-/** \brief Test if UDP Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+ AT91PS_UDP pUdp, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_UDP_GetInterruptMaskStatus( pUdp ) & flag );
+ return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR TC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_InterruptEnable */
-/** \brief Enable TC Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC_InterruptEnable( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg TC interrupt to be enabled */
+ SOFTWARE API FOR TC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg TC interrupt to be enabled
{
- pTc->TC_IER = flag;
+ pTc->TC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_InterruptDisable */
-/** \brief Disable TC Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC_InterruptDisable( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg TC interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg TC interrupt to be disabled
{
- pTc->TC_IDR = flag;
+ pTc->TC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_GetInterruptMaskStatus */
-/** \brief Return TC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TC_GetInterruptMaskStatus( /* \return TC Interrupt Mask Status */
- AT91PS_TC pTc ) /* \arg pointer to a TC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+ AT91PS_TC pTc) // \arg pointer to a TC controller
{
- return pTc->TC_IMR;
+ return pTc->TC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_IsInterruptMasked */
-/** \brief Test if TC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_TC_IsInterruptMasked( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_TC_GetInterruptMaskStatus( pTc ) & flag );
+ return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR CAN
-***************************************************************************** */
-#define STANDARD_FORMAT 0
-#define EXTENDED_FORMAT 1
+ SOFTWARE API FOR CAN
+ ***************************************************************************** */
+#define STANDARD_FORMAT 0
+#define EXTENDED_FORMAT 1
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_InitMailboxRegisters() */
-/** \brief Configure the corresponding mailbox */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_InitMailboxRegisters( AT91PS_CAN_MB CAN_Mailbox,
- int mode_reg,
- int acceptance_mask_reg,
- int id_reg,
- int data_low_reg,
- int data_high_reg,
- int control_reg )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_InitMailboxRegisters()
+//* \brief Configure the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox,
+ int mode_reg,
+ int acceptance_mask_reg,
+ int id_reg,
+ int data_low_reg,
+ int data_high_reg,
+ int control_reg)
{
- CAN_Mailbox->CAN_MB_MCR = 0x0;
- CAN_Mailbox->CAN_MB_MMR = mode_reg;
- CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;
- CAN_Mailbox->CAN_MB_MID = id_reg;
- CAN_Mailbox->CAN_MB_MDL = data_low_reg;
- CAN_Mailbox->CAN_MB_MDH = data_high_reg;
- CAN_Mailbox->CAN_MB_MCR = control_reg;
+ CAN_Mailbox->CAN_MB_MCR = 0x0;
+ CAN_Mailbox->CAN_MB_MMR = mode_reg;
+ CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;
+ CAN_Mailbox->CAN_MB_MID = id_reg;
+ CAN_Mailbox->CAN_MB_MDL = data_low_reg;
+ CAN_Mailbox->CAN_MB_MDH = data_high_reg;
+ CAN_Mailbox->CAN_MB_MCR = control_reg;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_EnableCAN() */
-/** \brief */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_EnableCAN( AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_EnableCAN()
+//* \brief
+//*----------------------------------------------------------------------------
+__inline void AT91F_EnableCAN(
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- pCAN->CAN_MR |= AT91C_CAN_CANEN;
+ pCAN->CAN_MR |= AT91C_CAN_CANEN;
- /* Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver */
- while( ( pCAN->CAN_SR & AT91C_CAN_WAKEUP ) != AT91C_CAN_WAKEUP )
- {
- }
+ // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
+ while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DisableCAN() */
-/** \brief */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DisableCAN( AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DisableCAN()
+//* \brief
+//*----------------------------------------------------------------------------
+__inline void AT91F_DisableCAN(
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
+ pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_EnableIt */
-/** \brief Enable CAN interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_EnableIt( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_EnableIt
+//* \brief Enable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_EnableIt (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pCAN->CAN_IER = flag;
+ //* Write to the IER register
+ pCAN->CAN_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_DisableIt */
-/** \brief Disable CAN interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_DisableIt( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_DisableIt
+//* \brief Disable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_DisableIt (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pCAN->CAN_IDR = flag;
+ //* Write to the IDR register
+ pCAN->CAN_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetStatus */
-/** \brief Return CAN Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetStatus( /* \return CAN Interrupt Status */
- AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetStatus
+//* \brief Return CAN Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- return pCAN->CAN_SR;
+ return pCAN->CAN_SR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetInterruptMaskStatus */
-/** \brief Return CAN Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( /* \return CAN Interrupt Mask Status */
- AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetInterruptMaskStatus
+//* \brief Return CAN Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- return pCAN->CAN_IMR;
+ return pCAN->CAN_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_IsInterruptMasked */
-/** \brief Test if CAN Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_IsInterruptMasked( AT91PS_CAN pCAN, /* \arg pointer to a CAN controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_IsInterruptMasked
+//* \brief Test if CAN Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsInterruptMasked(
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_CAN_GetInterruptMaskStatus( pCAN ) & flag );
+ return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_IsStatusSet */
-/** \brief Test if CAN Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_IsStatusSet( AT91PS_CAN pCAN, /* \arg pointer to a CAN controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_IsStatusSet
+//* \brief Test if CAN Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsStatusSet(
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_CAN_GetStatus( pCAN ) & flag );
+ return (AT91F_CAN_GetStatus(pCAN) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgModeReg */
-/** \brief Configure the Mode Register of the CAN controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgModeReg( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgModeReg
+//* \brief Configure the Mode Register of the CAN controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgModeReg (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int mode) // mode register
{
- /** Write to the MR register */
- pCAN->CAN_MR = mode;
+ //* Write to the MR register
+ pCAN->CAN_MR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetModeReg */
-/** \brief Return the Mode Register of the CAN controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetModeReg( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetModeReg
+//* \brief Return the Mode Register of the CAN controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetModeReg (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_MR;
+ return pCAN->CAN_MR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgBaudrateReg */
-/** \brief Configure the Baudrate of the CAN controller for the network */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgBaudrateReg( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int baudrate_cfg )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgBaudrateReg
+//* \brief Configure the Baudrate of the CAN controller for the network
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgBaudrateReg (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int baudrate_cfg)
{
- /** Write to the BR register */
- pCAN->CAN_BR = baudrate_cfg;
+ //* Write to the BR register
+ pCAN->CAN_BR = baudrate_cfg;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetBaudrate */
-/** \brief Return the Baudrate of the CAN controller for the network value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetBaudrate( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetBaudrate
+//* \brief Return the Baudrate of the CAN controller for the network value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetBaudrate (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_BR;
+ return pCAN->CAN_BR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetInternalCounter */
-/** \brief Return CAN Timer Regsiter Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetInternalCounter( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetInternalCounter
+//* \brief Return CAN Timer Regsiter Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInternalCounter (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_TIM;
+ return pCAN->CAN_TIM;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetTimestamp */
-/** \brief Return CAN Timestamp Register Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetTimestamp( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetTimestamp
+//* \brief Return CAN Timestamp Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetTimestamp (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_TIMESTP;
+ return pCAN->CAN_TIMESTP;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetErrorCounter */
-/** \brief Return CAN Error Counter Register Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetErrorCounter( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetErrorCounter
+//* \brief Return CAN Error Counter Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetErrorCounter (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_ECR;
+ return pCAN->CAN_ECR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_InitTransferRequest */
-/** \brief Request for a transfer on the corresponding mailboxes */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_InitTransferRequest( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int transfer_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_InitTransferRequest
+//* \brief Request for a transfer on the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitTransferRequest (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int transfer_cmd)
{
- pCAN->CAN_TCR = transfer_cmd;
+ pCAN->CAN_TCR = transfer_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_InitAbortRequest */
-/** \brief Abort the corresponding mailboxes */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_InitAbortRequest( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int abort_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_InitAbortRequest
+//* \brief Abort the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitAbortRequest (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int abort_cmd)
{
- pCAN->CAN_ACR = abort_cmd;
+ pCAN->CAN_ACR = abort_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageModeReg */
-/** \brief Program the Message Mode Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageModeReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageModeReg
+//* \brief Program the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageModeReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int mode)
{
- CAN_Mailbox->CAN_MB_MMR = mode;
+ CAN_Mailbox->CAN_MB_MMR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageModeReg */
-/** \brief Return the Message Mode Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageModeReg( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageModeReg
+//* \brief Return the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageModeReg (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MMR;
+ return CAN_Mailbox->CAN_MB_MMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageIDReg */
-/** \brief Program the Message ID Register */
-/** \brief Version == 0 for Standard messsage, Version == 1 for Extended */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageIDReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int id,
- unsigned char version )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageIDReg
+//* \brief Program the Message ID Register
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageIDReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int id,
+ unsigned char version)
{
- if( version == 0 ) /* IDvA Standard Format */
- {
- CAN_Mailbox->CAN_MB_MID = id << 18;
- }
- else /* IDvB Extended Format */
- {
- CAN_Mailbox->CAN_MB_MID = id | ( 1 << 29 ); /* set MIDE bit */
- }
+ if(version==0) // IDvA Standard Format
+ CAN_Mailbox->CAN_MB_MID = id<<18;
+ else // IDvB Extended Format
+ CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageIDReg */
-/** \brief Return the Message ID Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageIDReg( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageIDReg
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageIDReg (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MID;
+ return CAN_Mailbox->CAN_MB_MID;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageAcceptanceMaskReg */
-/** \brief Program the Message Acceptance Mask Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int mask )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg
+//* \brief Program the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int mask)
{
- CAN_Mailbox->CAN_MB_MAM = mask;
+ CAN_Mailbox->CAN_MB_MAM = mask;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageAcceptanceMaskReg */
-/** \brief Return the Message Acceptance Mask Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg
+//* \brief Return the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MAM;
+ return CAN_Mailbox->CAN_MB_MAM;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetFamilyID */
-/** \brief Return the Message ID Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetFamilyID( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetFamilyID
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetFamilyID (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MFID;
+ return CAN_Mailbox->CAN_MB_MFID;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageCtrl */
-/** \brief Request and config for a transfer on the corresponding mailbox */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageCtrlReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int message_ctrl_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageCtrl
+//* \brief Request and config for a transfer on the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageCtrlReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int message_ctrl_cmd)
{
- CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;
+ CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageStatus */
-/** \brief Return CAN Mailbox Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageStatus( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageStatus
+//* \brief Return CAN Mailbox Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageStatus (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MSR;
+ return CAN_Mailbox->CAN_MB_MSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageDataLow */
-/** \brief Program data low value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageDataLow( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int data )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageDataLow
+//* \brief Program data low value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataLow (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int data)
{
- CAN_Mailbox->CAN_MB_MDL = data;
+ CAN_Mailbox->CAN_MB_MDL = data;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageDataLow */
-/** \brief Return data low value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageDataLow( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageDataLow
+//* \brief Return data low value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataLow (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MDL;
+ return CAN_Mailbox->CAN_MB_MDL;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageDataHigh */
-/** \brief Program data high value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageDataHigh( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int data )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageDataHigh
+//* \brief Program data high value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataHigh (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int data)
{
- CAN_Mailbox->CAN_MB_MDH = data;
+ CAN_Mailbox->CAN_MB_MDH = data;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageDataHigh */
-/** \brief Return data high value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageDataHigh( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageDataHigh
+//* \brief Return data high value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MDH;
+ return CAN_Mailbox->CAN_MB_MDH;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_Open */
-/** \brief Open a CAN Port */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_Open( const unsigned int null ) /* \arg */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_Open
+//* \brief Open a CAN Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_Open (
+ const unsigned int null) // \arg
{
- /* NOT DEFINED AT THIS MOMENT */
- return( 0 );
+ /* NOT DEFINED AT THIS MOMENT */
+ return ( 0 );
+}
+/* *****************************************************************************
+ SOFTWARE API FOR ADC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int flag) // IT to be enabled
+{
+ //* Write to the IER register
+ pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int flag) // IT to be disabled
+{
+ //* Write to the IDR register
+ pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+ AT91PS_ADC pADC) // pointer to a ADC controller
+{
+ return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+ AT91PS_ADC pADC) // pointer to a ADC controller
+{
+ return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int mode) // mode register
+{
+ //* Write to the MR register
+ pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_MR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int mck_clock, // in MHz
+ unsigned int adc_clock, // in MHz
+ unsigned int startup_time, // in us
+ unsigned int sample_and_hold_time) // in ns
+{
+ unsigned int prescal,startup,shtim;
+
+ prescal = mck_clock/(2*adc_clock) - 1;
+ startup = adc_clock*startup_time/8 - 1;
+ shtim = adc_clock*sample_and_hold_time/1000 - 1;
+
+ //* Write to the MR register
+ pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int channel) // mode register
+{
+ //* Write to the CHER register
+ pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int channel) // mode register
+{
+ //* Write to the CHDR register
+ pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CHSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ pADC->ADC_CR = AT91C_ADC_START;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ pADC->ADC_CR = AT91C_ADC_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_LCDR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR1;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR2;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR3;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR5;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR6;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR7;
}
/* *****************************************************************************
-* SOFTWARE API FOR ADC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_EnableIt */
-/** \brief Enable ADC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_EnableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int flag ) /* IT to be enabled */
+ SOFTWARE API FOR AES
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_EnableIt
+//* \brief Enable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_EnableIt (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pADC->ADC_IER = flag;
+ //* Write to the IER register
+ pAES->AES_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_DisableIt */
-/** \brief Disable ADC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_DisableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_DisableIt
+//* \brief Disable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_DisableIt (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pADC->ADC_IDR = flag;
+ //* Write to the IDR register
+ pAES->AES_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetStatus */
-/** \brief Return ADC Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetStatus( /* \return ADC Interrupt Status */
- AT91PS_ADC pADC ) /* pointer to a ADC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetStatus
+//* \brief Return AES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
+ AT91PS_AES pAES) // pointer to a AES controller
{
- return pADC->ADC_SR;
+ return pAES->AES_ISR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetInterruptMaskStatus */
-/** \brief Return ADC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( /* \return ADC Interrupt Mask Status */
- AT91PS_ADC pADC ) /* pointer to a ADC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetInterruptMaskStatus
+//* \brief Return AES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
+ AT91PS_AES pAES) // pointer to a AES controller
{
- return pADC->ADC_IMR;
+ return pAES->AES_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_IsInterruptMasked */
-/** \brief Test if ADC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_IsInterruptMasked( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_IsInterruptMasked
+//* \brief Test if AES Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsInterruptMasked(
+ AT91PS_AES pAES, // \arg pointer to a AES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_ADC_GetInterruptMaskStatus( pADC ) & flag );
+ return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_IsStatusSet */
-/** \brief Test if ADC Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_IsStatusSet( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_IsStatusSet
+//* \brief Test if AES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsStatusSet(
+ AT91PS_AES pAES, // \arg pointer to a AES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_ADC_GetStatus( pADC ) & flag );
+ return (AT91F_AES_GetStatus(pAES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgModeReg */
-/** \brief Configure the Mode Register of the ADC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgModeReg( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_CfgModeReg
+//* \brief Configure the Mode Register of the AES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgModeReg (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned int mode) // mode register
{
- /** Write to the MR register */
- pADC->ADC_MR = mode;
+ //* Write to the MR register
+ pAES->AES_MR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetModeReg */
-/** \brief Return the Mode Register of the ADC controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetModeReg( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetModeReg
+//* \brief Return the Mode Register of the AES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetModeReg (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- return pADC->ADC_MR;
+ return pAES->AES_MR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgTimings */
-/** \brief Configure the different necessary timings of the ADC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgTimings( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int mck_clock, /* in MHz */
- unsigned int adc_clock, /* in MHz */
- unsigned int startup_time, /* in us */
- unsigned int sample_and_hold_time ) /* in ns */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_StartProcessing (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- unsigned int prescal, startup, shtim;
-
- prescal = mck_clock / ( 2 * adc_clock ) - 1;
- startup = adc_clock * startup_time / 8 - 1;
- shtim = adc_clock * sample_and_hold_time / 1000 - 1;
-
- /** Write to the MR register */
- pADC->ADC_MR = ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) & AT91C_ADC_SHTIM );
+ pAES->AES_CR = AT91C_AES_START;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_EnableChannel */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_EnableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int channel ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_SoftReset
+//* \brief Reset AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SoftReset (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- /** Write to the CHER register */
- pADC->ADC_CHER = channel;
+ pAES->AES_CR = AT91C_AES_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_DisableChannel */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_DisableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int channel ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_LoadNewSeed
+//* \brief Load New Seed in the random number generator
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_LoadNewSeed (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- /** Write to the CHDR register */
- pADC->ADC_CHDR = channel;
+ pAES->AES_CR = AT91C_AES_LOADSEED;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetChannelStatus */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetChannelStatus( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_SetCryptoKey
+//* \brief Set Cryptographic Key x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetCryptoKey (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- return pADC->ADC_CHSR;
+ pAES->AES_KEYWxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_StartConversion */
-/** \brief Software request for a analog to digital conversion */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_StartConversion( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_InputData (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index,
+ unsigned int indata
+ )
{
- pADC->ADC_CR = AT91C_ADC_START;
+ pAES->AES_IDATAxR[index] = indata;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_SoftReset */
-/** \brief Software reset */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_SoftReset( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetOutputData (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index
+ )
{
- pADC->ADC_CR = AT91C_ADC_SWRST;
+ return pAES->AES_ODATAxR[index];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetLastConvertedData */
-/** \brief Return the Last Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetLastConvertedData( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_SetInitializationVector
+//* \brief Set Initialization Vector (or Counter) x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetInitializationVector (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index,
+ unsigned int initvector
+ )
{
- return pADC->ADC_LCDR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH0 */
-/** \brief Return the Channel 0 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH0( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR0;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH1 */
-/** \brief Return the Channel 1 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH1( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR1;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH2 */
-/** \brief Return the Channel 2 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH2( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR2;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH3 */
-/** \brief Return the Channel 3 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH3( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR3;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH4 */
-/** \brief Return the Channel 4 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH4( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR4;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH5 */
-/** \brief Return the Channel 5 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH5( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR5;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH6 */
-/** \brief Return the Channel 6 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH6( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR6;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH7 */
-/** \brief Return the Channel 7 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH7( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR7;
+ pAES->AES_IVxR[index] = initvector;
}
/* *****************************************************************************
-* SOFTWARE API FOR AES
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_EnableIt */
-/** \brief Enable AES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_EnableIt( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned int flag ) /* IT to be enabled */
+ SOFTWARE API FOR TDES
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_EnableIt
+//* \brief Enable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_EnableIt (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pAES->AES_IER = flag;
+ //* Write to the IER register
+ pTDES->TDES_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_DisableIt */
-/** \brief Disable AES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_DisableIt( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_DisableIt
+//* \brief Disable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_DisableIt (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pAES->AES_IDR = flag;
+ //* Write to the IDR register
+ pTDES->TDES_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetStatus */
-/** \brief Return AES Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetStatus( /* \return AES Interrupt Status */
- AT91PS_AES pAES ) /* pointer to a AES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetStatus
+//* \brief Return TDES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
+ AT91PS_TDES pTDES) // pointer to a TDES controller
{
- return pAES->AES_ISR;
+ return pTDES->TDES_ISR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetInterruptMaskStatus */
-/** \brief Return AES Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetInterruptMaskStatus( /* \return AES Interrupt Mask Status */
- AT91PS_AES pAES ) /* pointer to a AES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetInterruptMaskStatus
+//* \brief Return TDES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
+ AT91PS_TDES pTDES) // pointer to a TDES controller
{
- return pAES->AES_IMR;
+ return pTDES->TDES_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_IsInterruptMasked */
-/** \brief Test if AES Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_IsInterruptMasked( AT91PS_AES pAES, /* \arg pointer to a AES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_IsInterruptMasked
+//* \brief Test if TDES Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsInterruptMasked(
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_AES_GetInterruptMaskStatus( pAES ) & flag );
+ return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_IsStatusSet */
-/** \brief Test if AES Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_IsStatusSet( AT91PS_AES pAES, /* \arg pointer to a AES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_IsStatusSet
+//* \brief Test if TDES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsStatusSet(
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_AES_GetStatus( pAES ) & flag );
+ return (AT91F_TDES_GetStatus(pTDES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_CfgModeReg */
-/** \brief Configure the Mode Register of the AES controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_CfgModeReg( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_CfgModeReg
+//* \brief Configure the Mode Register of the TDES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgModeReg (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned int mode) // mode register
{
- /** Write to the MR register */
- pAES->AES_MR = mode;
+ //* Write to the MR register
+ pTDES->TDES_MR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetModeReg */
-/** \brief Return the Mode Register of the AES controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetModeReg( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetModeReg
+//* \brief Return the Mode Register of the TDES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetModeReg (
+ AT91PS_TDES pTDES // pointer to a TDES controller
+ )
{
- return pAES->AES_MR;
+ return pTDES->TDES_MR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_StartProcessing */
-/** \brief Start Encryption or Decryption */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_StartProcessing( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_StartProcessing (
+ AT91PS_TDES pTDES // pointer to a TDES controller
+ )
{
- pAES->AES_CR = AT91C_AES_START;
+ pTDES->TDES_CR = AT91C_TDES_START;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_SoftReset */
-/** \brief Reset AES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_SoftReset( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SoftReset
+//* \brief Reset TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SoftReset (
+ AT91PS_TDES pTDES // pointer to a TDES controller
+ )
{
- pAES->AES_CR = AT91C_AES_SWRST;
+ pTDES->TDES_CR = AT91C_TDES_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_LoadNewSeed */
-/** \brief Load New Seed in the random number generator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_LoadNewSeed( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetCryptoKey1
+//* \brief Set Cryptographic Key 1 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey1 (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- pAES->AES_CR = AT91C_AES_LOADSEED;
+ pTDES->TDES_KEY1WxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_SetCryptoKey */
-/** \brief Set Cryptographic Key x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_SetCryptoKey( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetCryptoKey2
+//* \brief Set Cryptographic Key 2 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey2 (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- pAES->AES_KEYWxR[ index ] = keyword;
+ pTDES->TDES_KEY2WxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_InputData */
-/** \brief Set Input Data x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_InputData( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index,
- unsigned int indata )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetCryptoKey3
+//* \brief Set Cryptographic Key 3 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey3 (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- pAES->AES_IDATAxR[ index ] = indata;
+ pTDES->TDES_KEY3WxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetOutputData */
-/** \brief Get Output Data x */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetOutputData( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_InputData (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int indata
+ )
{
- return pAES->AES_ODATAxR[ index ];
+ pTDES->TDES_IDATAxR[index] = indata;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_SetInitializationVector */
-/** \brief Set Initialization Vector (or Counter) x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_SetInitializationVector( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index,
- unsigned int initvector )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetOutputData (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index
+ )
{
- pAES->AES_IVxR[ index ] = initvector;
+ return pTDES->TDES_ODATAxR[index];
}
-/* *****************************************************************************
-* SOFTWARE API FOR TDES
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_EnableIt */
-/** \brief Enable TDES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_EnableIt( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetInitializationVector
+//* \brief Set Initialization Vector x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetInitializationVector (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int initvector
+ )
{
- /** Write to the IER register */
- pTDES->TDES_IER = flag;
+ pTDES->TDES_IVxR[index] = initvector;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_DisableIt */
-/** \brief Disable TDES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_DisableIt( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
{
- /** Write to the IDR register */
- pTDES->TDES_IDR = flag;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetStatus */
-/** \brief Return TDES Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetStatus( /* \return TDES Interrupt Status */
- AT91PS_TDES pTDES ) /* pointer to a TDES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
{
- return pTDES->TDES_ISR;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA27_DRXD ) |
+ ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetInterruptMaskStatus */
-/** \brief Return TDES Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( /* \return TDES Interrupt Mask Status */
- AT91PS_TDES pTDES ) /* pointer to a TDES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
{
- return pTDES->TDES_IMR;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_IsInterruptMasked */
-/** \brief Test if TDES Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_IsInterruptMasked( AT91PS_TDES pTDES, /* \arg pointer to a TDES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
{
- return( AT91F_TDES_GetInterruptMaskStatus( pTDES ) & flag );
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB30_PCK2 ) |
+ ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A
+ ((unsigned int) AT91C_PB20_PCK0 ) |
+ ((unsigned int) AT91C_PB0_PCK0 ) |
+ ((unsigned int) AT91C_PB22_PCK2 ) |
+ ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA30_PCK2 ) |
+ ((unsigned int) AT91C_PA13_PCK1 ) |
+ ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_IsStatusSet */
-/** \brief Test if TDES Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_IsStatusSet( AT91PS_TDES pTDES, /* \arg pointer to a TDES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_CfgPMC
+//* \brief Enable Peripheral clock in PMC for VREG
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_CfgPMC (void)
{
- return( AT91F_TDES_GetStatus( pTDES ) & flag );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_CfgModeReg */
-/** \brief Configure the Mode Register of the TDES controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_CfgModeReg( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for RSTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTC_CfgPMC (void)
{
- /** Write to the MR register */
- pTDES->TDES_MR = mode;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetModeReg */
-/** \brief Return the Mode Register of the TDES controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetModeReg( AT91PS_TDES pTDES /* pointer to a TDES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
{
- return pTDES->TDES_MR;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SSC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_StartProcessing */
-/** \brief Start Encryption or Decryption */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_StartProcessing( AT91PS_TDES pTDES /* pointer to a TDES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
{
- pTDES->TDES_CR = AT91C_TDES_START;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA25_RK ) |
+ ((unsigned int) AT91C_PA22_TK ) |
+ ((unsigned int) AT91C_PA21_TF ) |
+ ((unsigned int) AT91C_PA24_RD ) |
+ ((unsigned int) AT91C_PA26_RF ) |
+ ((unsigned int) AT91C_PA23_TD ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SoftReset */
-/** \brief Reset TDES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SoftReset( AT91PS_TDES pTDES /* pointer to a TDES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for WDTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTC_CfgPMC (void)
{
- pTDES->TDES_CR = AT91C_TDES_SWRST;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetCryptoKey1 */
-/** \brief Set Cryptographic Key 1 Word x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetCryptoKey1( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
{
- pTDES->TDES_KEY1WxR[ index ] = keyword;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_US1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetCryptoKey2 */
-/** \brief Set Cryptographic Key 2 Word x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetCryptoKey2( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
{
- pTDES->TDES_KEY2WxR[ index ] = keyword;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB26_RI1 ) |
+ ((unsigned int) AT91C_PB24_DSR1 ) |
+ ((unsigned int) AT91C_PB23_DCD1 ) |
+ ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA7_SCK1 ) |
+ ((unsigned int) AT91C_PA8_RTS1 ) |
+ ((unsigned int) AT91C_PA6_TXD1 ) |
+ ((unsigned int) AT91C_PA5_RXD1 ) |
+ ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetCryptoKey3 */
-/** \brief Set Cryptographic Key 3 Word x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetCryptoKey3( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
{
- pTDES->TDES_KEY3WxR[ index ] = keyword;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_US0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_InputData */
-/** \brief Set Input Data x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_InputData( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int indata )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
{
- pTDES->TDES_IDATAxR[ index ] = indata;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA0_RXD0 ) |
+ ((unsigned int) AT91C_PA4_CTS0 ) |
+ ((unsigned int) AT91C_PA3_RTS0 ) |
+ ((unsigned int) AT91C_PA2_SCK0 ) |
+ ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetOutputData */
-/** \brief Get Output Data x */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetOutputData( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SPI1
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPMC (void)
{
- return pTDES->TDES_ODATAxR[ index ];
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SPI1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetInitializationVector */
-/** \brief Set Initialization Vector x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetInitializationVector( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int initvector )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI1_CfgPIO
+//* \brief Configure PIO controllers to drive SPI1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPIO (void)
{
- pTDES->TDES_IVxR[ index ] = initvector;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB16_NPCS13 ) |
+ ((unsigned int) AT91C_PB10_NPCS11 ) |
+ ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA4_NPCS13 ) |
+ ((unsigned int) AT91C_PA29_NPCS13 ) |
+ ((unsigned int) AT91C_PA21_NPCS10 ) |
+ ((unsigned int) AT91C_PA22_SPCK1 ) |
+ ((unsigned int) AT91C_PA25_NPCS11 ) |
+ ((unsigned int) AT91C_PA2_NPCS11 ) |
+ ((unsigned int) AT91C_PA24_MISO1 ) |
+ ((unsigned int) AT91C_PA3_NPCS12 ) |
+ ((unsigned int) AT91C_PA26_NPCS12 ) |
+ ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for DBGU */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SPI0
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SPI0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_CfgPIO */
-/** \brief Configure PIO controllers to drive DBGU signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI0_CfgPIO
+//* \brief Configure PIO controllers to drive SPI0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA27_DRXD ) |
- ( ( unsigned int ) AT91C_PA28_DTXD ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB13_NPCS01 ) |
+ ((unsigned int) AT91C_PB17_NPCS03 ) |
+ ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA16_MISO0 ) |
+ ((unsigned int) AT91C_PA13_NPCS01 ) |
+ ((unsigned int) AT91C_PA15_NPCS03 ) |
+ ((unsigned int) AT91C_PA17_MOSI0 ) |
+ ((unsigned int) AT91C_PA18_SPCK0 ) |
+ ((unsigned int) AT91C_PA14_NPCS02 ) |
+ ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A
+ ((unsigned int) AT91C_PA7_NPCS01 ) |
+ ((unsigned int) AT91C_PA9_NPCS03 ) |
+ ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PMC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PITC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgPIO */
-/** \brief Configure PIO controllers to drive PMC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB30_PCK2 ) |
- ( ( unsigned int ) AT91C_PB29_PCK1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB20_PCK0 ) |
- ( ( unsigned int ) AT91C_PB0_PCK0 ) |
- ( ( unsigned int ) AT91C_PB22_PCK2 ) |
- ( ( unsigned int ) AT91C_PB21_PCK1 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA30_PCK2 ) |
- ( ( unsigned int ) AT91C_PA13_PCK1 ) |
- ( ( unsigned int ) AT91C_PA27_PCK3 ) ); /* Peripheral B */
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_FIQ) |
+ ((unsigned int) 1 << AT91C_ID_IRQ0) |
+ ((unsigned int) 1 << AT91C_ID_IRQ1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_VREG_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for VREG */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_VREG_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA30_IRQ0 ) |
+ ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A
+ ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for RSTC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RSTC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_AES));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SSC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SSC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TWI));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_CfgPIO */
-/** \brief Configure PIO controllers to drive SSC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA25_RK ) |
- ( ( unsigned int ) AT91C_PA22_TK ) |
- ( ( unsigned int ) AT91C_PA21_TF ) |
- ( ( unsigned int ) AT91C_PA24_RD ) |
- ( ( unsigned int ) AT91C_PA26_RF ) |
- ( ( unsigned int ) AT91C_PA23_TD ), /* Peripheral A */
- 0 ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for WDTC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_WDTC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for US1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US1_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_US1 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US1_CfgPIO */
-/** \brief Configure PIO controllers to drive US1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US1_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB26_RI1 ) |
- ( ( unsigned int ) AT91C_PB24_DSR1 ) |
- ( ( unsigned int ) AT91C_PB23_DCD1 ) |
- ( ( unsigned int ) AT91C_PB25_DTR1 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA7_SCK1 ) |
- ( ( unsigned int ) AT91C_PA8_RTS1 ) |
- ( ( unsigned int ) AT91C_PA6_TXD1 ) |
- ( ( unsigned int ) AT91C_PA5_RXD1 ) |
- ( ( unsigned int ) AT91C_PA9_CTS1 ), /* Peripheral A */
- 0 ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for US0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US0_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_US0 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US0_CfgPIO */
-/** \brief Configure PIO controllers to drive US0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US0_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA0_RXD0 ) |
- ( ( unsigned int ) AT91C_PA4_CTS0 ) |
- ( ( unsigned int ) AT91C_PA3_RTS0 ) |
- ( ( unsigned int ) AT91C_PA2_SCK0 ) |
- ( ( unsigned int ) AT91C_PA1_TXD0 ), /* Peripheral A */
- 0 ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SPI1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI1_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SPI1 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI1_CfgPIO */
-/** \brief Configure PIO controllers to drive SPI1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI1_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB16_NPCS13 ) |
- ( ( unsigned int ) AT91C_PB10_NPCS11 ) |
- ( ( unsigned int ) AT91C_PB11_NPCS12 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA4_NPCS13 ) |
- ( ( unsigned int ) AT91C_PA29_NPCS13 ) |
- ( ( unsigned int ) AT91C_PA21_NPCS10 ) |
- ( ( unsigned int ) AT91C_PA22_SPCK1 ) |
- ( ( unsigned int ) AT91C_PA25_NPCS11 ) |
- ( ( unsigned int ) AT91C_PA2_NPCS11 ) |
- ( ( unsigned int ) AT91C_PA24_MISO1 ) |
- ( ( unsigned int ) AT91C_PA3_NPCS12 ) |
- ( ( unsigned int ) AT91C_PA26_NPCS12 ) |
- ( ( unsigned int ) AT91C_PA23_MOSI1 ) ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SPI0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI0_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SPI0 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI0_CfgPIO */
-/** \brief Configure PIO controllers to drive SPI0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI0_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB13_NPCS01 ) |
- ( ( unsigned int ) AT91C_PB17_NPCS03 ) |
- ( ( unsigned int ) AT91C_PB14_NPCS02 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA16_MISO0 ) |
- ( ( unsigned int ) AT91C_PA13_NPCS01 ) |
- ( ( unsigned int ) AT91C_PA15_NPCS03 ) |
- ( ( unsigned int ) AT91C_PA17_MOSI0 ) |
- ( ( unsigned int ) AT91C_PA18_SPCK0 ) |
- ( ( unsigned int ) AT91C_PA14_NPCS02 ) |
- ( ( unsigned int ) AT91C_PA12_NPCS00 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA7_NPCS01 ) |
- ( ( unsigned int ) AT91C_PA9_NPCS03 ) |
- ( ( unsigned int ) AT91C_PA8_NPCS02 ) ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PITC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for AIC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_FIQ ) |
- ( ( unsigned int ) 1 << AT91C_ID_IRQ0 ) |
- ( ( unsigned int ) 1 << AT91C_ID_IRQ1 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_CfgPIO */
-/** \brief Configure PIO controllers to drive AIC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA30_IRQ0 ) |
- ( ( unsigned int ) AT91C_PA29_FIQ ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA14_IRQ1 ) ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for AES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_AES ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TWI */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TWI ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_CfgPIO */
-/** \brief Configure PIO controllers to drive TWI signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA11_TWCK ) |
- ( ( unsigned int ) AT91C_PA10_TWD ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA11_TWCK ) |
+ ((unsigned int) AT91C_PA10_TWD ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for ADC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_ADC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_ADC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgPIO */
-/** \brief Configure PIO controllers to drive ADC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB18_ADTRG ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH3_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH3 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH3_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB22_PWM3 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB30_PWM3 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A
+ ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH2_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH2 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH2_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB21_PWM2 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB29_PWM2 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A
+ ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH1_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH1_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB20_PWM1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB28_PWM1 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A
+ ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH0_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH0_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB19_PWM0 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB27_PWM0 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A
+ ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RTTC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for RTTC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RTTC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RTTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for RTTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RTTC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for UDP */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_UDP ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_UDP));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TDES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TDES ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TDES));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_EMAC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for EMAC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_EMAC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_EMAC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for EMAC
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_EMAC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_EMAC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_EMAC_CfgPIO */
-/** \brief Configure PIO controllers to drive EMAC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_EMAC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_EMAC_CfgPIO
+//* \brief Configure PIO controllers to drive EMAC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB2_ETX0 ) |
- ( ( unsigned int ) AT91C_PB12_ETXER ) |
- ( ( unsigned int ) AT91C_PB16_ECOL ) |
- ( ( unsigned int ) AT91C_PB11_ETX3 ) |
- ( ( unsigned int ) AT91C_PB6_ERX1 ) |
- ( ( unsigned int ) AT91C_PB15_ERXDV ) |
- ( ( unsigned int ) AT91C_PB13_ERX2 ) |
- ( ( unsigned int ) AT91C_PB3_ETX1 ) |
- ( ( unsigned int ) AT91C_PB8_EMDC ) |
- ( ( unsigned int ) AT91C_PB5_ERX0 ) |
- /*((unsigned int) AT91C_PB18_EF100 ) | */
- ( ( unsigned int ) AT91C_PB14_ERX3 ) |
- ( ( unsigned int ) AT91C_PB4_ECRS_ECRSDV ) |
- ( ( unsigned int ) AT91C_PB1_ETXEN ) |
- ( ( unsigned int ) AT91C_PB10_ETX2 ) |
- ( ( unsigned int ) AT91C_PB0_ETXCK_EREFCK ) |
- ( ( unsigned int ) AT91C_PB9_EMDIO ) |
- ( ( unsigned int ) AT91C_PB7_ERXER ) |
- ( ( unsigned int ) AT91C_PB17_ERXCK ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB2_ETX0 ) |
+ ((unsigned int) AT91C_PB12_ETXER ) |
+ ((unsigned int) AT91C_PB16_ECOL ) |
+ ((unsigned int) AT91C_PB11_ETX3 ) |
+ ((unsigned int) AT91C_PB6_ERX1 ) |
+ ((unsigned int) AT91C_PB15_ERXDV ) |
+ ((unsigned int) AT91C_PB13_ERX2 ) |
+ ((unsigned int) AT91C_PB3_ETX1 ) |
+ ((unsigned int) AT91C_PB8_EMDC ) |
+ ((unsigned int) AT91C_PB5_ERX0 ) |
+ //((unsigned int) AT91C_PB18_EF100 ) |
+ ((unsigned int) AT91C_PB14_ERX3 ) |
+ ((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
+ ((unsigned int) AT91C_PB1_ETXEN ) |
+ ((unsigned int) AT91C_PB10_ETX2 ) |
+ ((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
+ ((unsigned int) AT91C_PB9_EMDIO ) |
+ ((unsigned int) AT91C_PB7_ERXER ) |
+ ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC0_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC0 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC0_CfgPIO */
-/** \brief Configure PIO controllers to drive TC0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC0_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB23_TIOA0 ) |
- ( ( unsigned int ) AT91C_PB24_TIOB0 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB12_TCLK0 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB23_TIOA0 ) |
+ ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A
+ ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC1_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC1 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC1_CfgPIO */
-/** \brief Configure PIO controllers to drive TC1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC1_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB25_TIOA1 ) |
- ( ( unsigned int ) AT91C_PB26_TIOB1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB19_TCLK1 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB25_TIOA1 ) |
+ ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A
+ ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC2_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC2 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC2_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC2 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC2));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC2_CfgPIO */
-/** \brief Configure PIO controllers to drive TC2 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC2_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB28_TIOB2 ) |
- ( ( unsigned int ) AT91C_PB27_TIOA2 ), /* Peripheral A */
- 0 ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA15_TCLK2 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB28_TIOB2 ) |
+ ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A
+ 0); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for MC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIOA_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PIOA */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIOA_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PIOA ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PIOA));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIOB_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PIOB */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIOB_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIOB_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PIOB
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOB_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PIOB ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PIOB));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for CAN */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgPMC
+//* \brief Enable Peripheral clock in PMC for CAN
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_CAN ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_CAN));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgPIO */
-/** \brief Configure PIO controllers to drive CAN signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgPIO
+//* \brief Configure PIO controllers to drive CAN signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA20_CANTX ) |
- ( ( unsigned int ) AT91C_PA19_CANRX ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA20_CANTX ) |
+ ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PWMC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PWMC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PWMC));
}
#endif // lib_AT91SAM7X128_H
diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
index 3c4fd7d..02ee900 100644
--- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
+++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
@@ -1,4332 +1,4558 @@
-/** ---------------------------------------------------------------------------- */
-/** ATMEL Microcontroller Software Support - ROUSSET - */
-/** ---------------------------------------------------------------------------- */
-/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/** ---------------------------------------------------------------------------- */
-/** File Name : lib_AT91SAM7X256.h */
-/** Object : AT91SAM7X256 inlined functions */
-/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */
-/** */
-/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
-/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */
-/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */
-/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */
-/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
-/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */
-/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
-/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */
-/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */
-/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */
-/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */
-/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */
-/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */
-/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */
-/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */
-/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */
-/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
-/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */
-/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
-/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */
-/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
-/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */
-/** ---------------------------------------------------------------------------- */
+//* ----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name : lib_AT91SAM7X256.h
+//* Object : AT91SAM7X256 inlined functions
+//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+//*
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
+//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
#ifndef lib_AT91SAM7X256_H
#define lib_AT91SAM7X256_H
/* *****************************************************************************
-* SOFTWARE API FOR AIC
-***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */
+ SOFTWARE API FOR AIC
+ ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_ConfigureIt */
-/** \brief Interrupt Handler Initialization */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id, /* \arg interrupt number to initialize */
- unsigned int priority, /* \arg priority to give to the interrupt */
- unsigned int src_type, /* \arg activation and sense of activation */
- void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id, // \arg interrupt number to initialize
+ unsigned int priority, // \arg priority to give to the interrupt
+ unsigned int src_type, // \arg activation and sense of activation
+ void (*newHandler) (void) ) // \arg address of the interrupt handler
{
- unsigned int oldHandler;
- unsigned int mask;
+ unsigned int oldHandler;
+ unsigned int mask ;
- oldHandler = pAic->AIC_SVR[ irq_id ];
+ oldHandler = pAic->AIC_SVR[irq_id];
- mask = 0x1 << irq_id;
- /** Disable the interrupt on the interrupt controller */
- pAic->AIC_IDCR = mask;
- /** Save the interrupt handler routine pointer and the interrupt priority */
- pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;
- /** Store the Source Mode Register */
- pAic->AIC_SMR[ irq_id ] = src_type | priority;
- /** Clear the interrupt on the interrupt controller */
- pAic->AIC_ICCR = mask;
+ mask = 0x1 << irq_id ;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Save the interrupt handler routine pointer and the interrupt priority
+ pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+ //* Store the Source Mode Register
+ pAic->AIC_SMR[irq_id] = src_type | priority ;
+ //* Clear the interrupt on the interrupt controller
+ pAic->AIC_ICCR = mask ;
- return oldHandler;
+ return oldHandler;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_EnableIt */
-/** \brief Enable corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
{
- /** Enable the interrupt on the interrupt controller */
- pAic->AIC_IECR = 0x1 << irq_id;
+ //* Enable the interrupt on the interrupt controller
+ pAic->AIC_IECR = 0x1 << irq_id ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_DisableIt */
-/** \brief Disable corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
{
unsigned int mask = 0x1 << irq_id;
-
- /** Disable the interrupt on the interrupt controller */
- pAic->AIC_IDCR = mask;
- /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
- pAic->AIC_ICCR = mask;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = mask ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_ClearIt */
-/** \brief Clear corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number to initialize */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number to initialize
{
- /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
- pAic->AIC_ICCR = ( 0x1 << irq_id );
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = (0x1 << irq_id);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_AcknowledgeIt */
-/** \brief Acknowledge corresponding IT number */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+ AT91PS_AIC pAic) // \arg pointer to the AIC registers
{
pAic->AIC_EOICR = pAic->AIC_EOICR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_SetExceptionVector */
-/** \brief Configure vector handler */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */
- void ( * Handler )() ) /* \arg Interrupt Handler */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_SetExceptionVector (
+ unsigned int *pVector, // \arg pointer to the AIC registers
+ void (*Handler) () ) // \arg Interrupt Handler
{
- unsigned int oldVector = *pVector;
+ unsigned int oldVector = *pVector;
- if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE )
- {
- *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE;
- }
- else
- {
- *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000;
- }
+ if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+ *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+ else
+ *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
- return oldVector;
+ return oldVector;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_Trig */
-/** \brief Trig an IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg interrupt number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Trig (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number
{
- pAic->AIC_ISCR = ( 0x1 << irq_id );
+ pAic->AIC_ISCR = (0x1 << irq_id) ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_IsActive */
-/** \brief Test if an IT is active */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg Interrupt Number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsActive (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
{
- return( pAic->AIC_ISR & ( 0x1 << irq_id ) );
+ return (pAic->AIC_ISR & (0x1 << irq_id));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_IsPending */
-/** \brief Test if an IT is pending */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- unsigned int irq_id ) /* \arg Interrupt Number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsPending (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
{
- return( pAic->AIC_IPR & ( 0x1 << irq_id ) );
+ return (pAic->AIC_IPR & (0x1 << irq_id));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_Open */
-/** \brief Set exception vectors and AIC registers to default values */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
- void ( * IrqHandler )(), /* \arg Default IRQ vector exception */
- void ( * FiqHandler )(), /* \arg Default FIQ vector exception */
- void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */
- void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */
- unsigned int protectMode ) /* \arg Debug Control Register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ void (*IrqHandler) (), // \arg Default IRQ vector exception
+ void (*FiqHandler) (), // \arg Default FIQ vector exception
+ void (*DefaultHandler) (), // \arg Default Handler set in ISR
+ void (*SpuriousHandler) (), // \arg Default Spurious Handler
+ unsigned int protectMode) // \arg Debug Control Register
{
- int i;
+ int i;
- /* Disable all interrupts and set IVR to the default handler */
- for( i = 0; i < 32; ++i )
- {
- AT91F_AIC_DisableIt( pAic, i );
- AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler );
- }
+ // Disable all interrupts and set IVR to the default handler
+ for (i = 0; i < 32; ++i) {
+ AT91F_AIC_DisableIt(pAic, i);
+ AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
+ }
- /* Set the IRQ exception vector */
- AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler );
- /* Set the Fast Interrupt exception vector */
- AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler );
+ // Set the IRQ exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+ // Set the Fast Interrupt exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
- pAic->AIC_SPU = ( unsigned int ) SpuriousHandler;
- pAic->AIC_DCR = protectMode;
+ pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+ pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+ SOFTWARE API FOR PDC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RNPR = (unsigned int) address;
+ pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TNPR = (unsigned int) address;
+ pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RPR = (unsigned int) address;
+ pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TPR = (unsigned int) address;
+ pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+ //* Enable the RX and TX PDC transfer requests
+ AT91F_PDC_EnableRx(pPDC);
+ AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ if (AT91F_PDC_IsTxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ if (AT91F_PDC_IsRxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+/* *****************************************************************************
+ SOFTWARE API FOR DBGU
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be enabled
+{
+ pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be disabled
+{
+ pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+ AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller
+{
+ return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR PDC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetNextRx */
-/** \brief Set the next receive transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be received */
- unsigned int bytes ) /* \arg number of bytes to be received */
+ SOFTWARE API FOR PIO
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int periphAEnable, // \arg PERIPH A to enable
+ unsigned int periphBEnable) // \arg PERIPH B to enable
+
{
- pPDC->PDC_RNPR = ( unsigned int ) address;
- pPDC->PDC_RNCR = bytes;
+ pPio->PIO_ASR = periphAEnable;
+ pPio->PIO_BSR = periphBEnable;
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetNextTx */
-/** \brief Set the next transmit transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be transmitted */
- unsigned int bytes ) /* \arg number of bytes to be transmitted */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pioEnable) // \arg PIO to be enabled
{
- pPDC->PDC_TNPR = ( unsigned int ) address;
- pPDC->PDC_TNCR = bytes;
+ pPio->PIO_PER = pioEnable; // Set in PIO mode
+ pPio->PIO_OER = pioEnable; // Configure in Output
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetRx */
-/** \brief Set the receive transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be received */
- unsigned int bytes ) /* \arg number of bytes to be received */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputEnable) // \arg PIO to be enabled
{
- pPDC->PDC_RPR = ( unsigned int ) address;
- pPDC->PDC_RCR = bytes;
+ // Disable output
+ pPio->PIO_ODR = inputEnable;
+ pPio->PIO_PER = inputEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SetTx */
-/** \brief Set the transmit transfer descriptor */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
- char * address, /* \arg address to the next bloc to be transmitted */
- unsigned int bytes ) /* \arg number of bytes to be transmitted */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int multiDrvEnable) // \arg pio to be configured in open drain
{
- pPDC->PDC_TPR = ( unsigned int ) address;
- pPDC->PDC_TCR = bytes;
+ // Configure the multi-drive option
+ pPio->PIO_MDDR = ~multiDrvEnable;
+ pPio->PIO_MDER = multiDrvEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_EnableTx */
-/** \brief Enable transmit */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pullupEnable) // \arg enable pullup on PIO
{
- pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+ // Connect or not Pullup
+ pPio->PIO_PPUDR = ~pullupEnable;
+ pPio->PIO_PPUER = pullupEnable;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_EnableRx */
-/** \brief Enable receive */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int directDrive) // \arg PIO to be configured with direct drive
+
{
- pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+ // Configure the Direct Drive
+ pPio->PIO_OWDR = ~directDrive;
+ pPio->PIO_OWER = directDrive;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_DisableTx */
-/** \brief Disable transmit */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputFilter) // \arg PIO to be configured with input filter
+
{
- pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+ // Configure the Direct Drive
+ pPio->PIO_IFDR = ~inputFilter;
+ pPio->PIO_IFER = inputFilter;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_DisableRx */
-/** \brief Disable receive */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+ return pPio->PIO_PDSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsTxEmpty */
-/** \brief Test if the current transfer descriptor has been sent */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- return !( pPDC->PDC_TCR );
+ return (AT91F_PIO_GetInput(pPio) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsNextTxEmpty */
-/** \brief Test if the next transfer descriptor has been moved to the current td */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be set
{
- return !( pPDC->PDC_TNCR );
+ pPio->PIO_SODR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsRxEmpty */
-/** \brief Test if the current transfer descriptor has been filled */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be cleared
{
- return !( pPDC->PDC_RCR );
+ pPio->PIO_CODR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_IsNextRxEmpty */
-/** \brief Test if the next transfer descriptor has been moved to the current td */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */
- AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be forced
{
- return !( pPDC->PDC_RNCR );
+ pPio->PIO_ODSR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_Open */
-/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
{
- /** Disable the RX and TX PDC transfer requests */
- AT91F_PDC_DisableRx( pPDC );
- AT91F_PDC_DisableTx( pPDC );
-
- /** Reset all Counter register Next buffer first */
- AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
-
- /** Enable the RX and TX PDC transfer requests */
- AT91F_PDC_EnableRx( pPDC );
- AT91F_PDC_EnableTx( pPDC );
+ pPio->PIO_PER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_Close */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
{
- /** Disable the RX and TX PDC transfer requests */
- AT91F_PDC_DisableRx( pPDC );
- AT91F_PDC_DisableTx( pPDC );
-
- /** Reset all Counter register Next buffer first */
- AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
- AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+ pPio->PIO_PDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_SendFrame */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
- if( AT91F_PDC_IsTxEmpty( pPDC ) )
- {
- /** Buffer and next buffer can be initialized */
- AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer );
- AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer );
- return 2;
- }
- else if( AT91F_PDC_IsNextTxEmpty( pPDC ) )
- {
- /** Only one buffer can be initialized */
- AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer );
- return 1;
- }
- else
- {
- /** All buffer are in use... */
- return 0;
- }
+ return pPio->PIO_PSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PDC_ReceiveFrame */
-/** \brief Close PDC: disable TX and RX reset transfer descriptors */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
{
- if( AT91F_PDC_IsRxEmpty( pPDC ) )
- {
- /** Buffer and next buffer can be initialized */
- AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer );
- AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer );
- return 2;
- }
- else if( AT91F_PDC_IsNextRxEmpty( pPDC ) )
- {
- /** Only one buffer can be initialized */
- AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer );
- return 1;
- }
- else
- {
- /** All buffer are in use... */
- return 0;
- }
+ return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be enabled
+{
+ pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be disabled
+{
+ pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be enabled
+{
+ pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be disabled
+{
+ pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be enabled
+{
+ pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be disabled
+{
+ pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
+{
+ pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
+{
+ pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio A register selection
+{
+ pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio B register selection
+{
+ pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be enabled
+{
+ pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be disabled
+{
+ pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR DBGU
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_InterruptEnable */
-/** \brief Enable DBGU Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg dbgu interrupt to be enabled */
+ SOFTWARE API FOR PMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
{
- pDbgu->DBGU_IER = flag;
+ //* Write to the SCER register
+ pPMC->PMC_SCER = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_InterruptDisable */
-/** \brief Disable DBGU Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg dbgu interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
{
- pDbgu->DBGU_IDR = flag;
+ //* Write to the SCDR register
+ pPMC->PMC_SCDR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_GetInterruptMaskStatus */
-/** \brief Return DBGU Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */
- AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+ AT91PS_PMC pPMC // pointer to a CAN controller
+ )
{
- return pDbgu->DBGU_IMR;
+ return pPMC->PMC_SCSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_IsInterruptMasked */
-/** \brief Test if DBGU Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
{
- return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag );
+ pPMC->PMC_PCER = periphIds;
}
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
+{
+ pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+ return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int mode)
+{
+ pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int startup_time, // \arg main osc startup time in microsecond (us)
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+ pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
+{
+ pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+ return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ unsigned int reg = pPMC->PMC_MCKR;
+ unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+ unsigned int pllDivider, pllMultiplier;
+
+ switch (reg & AT91C_PMC_CSS) {
+ case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+ return slowClock / prescaler;
+ case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+ case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+ reg = pCKGR->CKGR_PLLR;
+ pllDivider = (reg & AT91C_CKGR_DIV);
+ pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+ }
+ return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck, // \arg Peripheral clock identifier 0 .. 7
+ unsigned int mode)
+{
+ pPMC->PMC_PCKR[pck] = mode;
+ pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck) // \arg Peripheral clock identifier 0 .. 7
+{
+ pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be enabled
+{
+ //* Write to the IER register
+ pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be disabled
+{
+ //* Write to the IDR register
+ pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+ return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+ return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+ SOFTWARE API FOR RSTC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+ AT91PS_RSTC pRSTC,
+ unsigned int reset)
+{
+ pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+ AT91PS_RSTC pRSTC,
+ unsigned int mode)
+{
+ pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+ AT91PS_RSTC pRSTC)
+{
+ return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+ AT91PS_RSTC pRSTC)
+{
+ return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+ AT91PS_RSTC pRSTC)
+{
+ return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
/* *****************************************************************************
-* SOFTWARE API FOR PIO
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgPeriph */
-/** \brief Enable pins to be drived by peripheral */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int periphAEnable, /* \arg PERIPH A to enable */
- unsigned int periphBEnable ) /* \arg PERIPH B to enable */
-
+ SOFTWARE API FOR RTTC
+ ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_SetRTT_TimeBase()
+//* \brief Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+ AT91PS_RTTC pRTTC,
+ unsigned int ms)
{
- pPio->PIO_ASR = periphAEnable;
- pPio->PIO_BSR = periphBEnable;
- pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */
+ if (ms > 2000)
+ return 1; // AT91C_TIME_OUT_OF_RANGE
+ pRTTC->RTTC_RTMR &= ~0xFFFF;
+ pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
+ return 0;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgOutput */
-/** \brief Enable PIO in output mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int pioEnable ) /* \arg PIO to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTSetPrescaler()
+//* \brief Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+ AT91PS_RTTC pRTTC,
+ unsigned int rtpres)
{
- pPio->PIO_PER = pioEnable; /* Set in PIO mode */
- pPio->PIO_OER = pioEnable; /* Configure in Output */
+ pRTTC->RTTC_RTMR &= ~0xFFFF;
+ pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
+ return (pRTTC->RTTC_RTMR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgInput */
-/** \brief Enable PIO in input mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int inputEnable ) /* \arg PIO to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTRestart()
+//* \brief Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+ AT91PS_RTTC pRTTC)
{
- /* Disable output */
- pPio->PIO_ODR = inputEnable;
- pPio->PIO_PER = inputEnable;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgOpendrain */
-/** \brief Configure PIO in open drain */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */
-{
- /* Configure the multi-drive option */
- pPio->PIO_MDDR = ~multiDrvEnable;
- pPio->PIO_MDER = multiDrvEnable;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgPullup */
-/** \brief Enable pullup on PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int pullupEnable ) /* \arg enable pullup on PIO */
-{
- /* Connect or not Pullup */
- pPio->PIO_PPUDR = ~pullupEnable;
- pPio->PIO_PPUER = pullupEnable;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgDirectDrive */
-/** \brief Enable direct drive on PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int directDrive ) /* \arg PIO to be configured with direct drive */
-
-{
- /* Configure the Direct Drive */
- pPio->PIO_OWDR = ~directDrive;
- pPio->PIO_OWER = directDrive;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_CfgInputFilter */
-/** \brief Enable input filter on input PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int inputFilter ) /* \arg PIO to be configured with input filter */
-
-{
- /* Configure the Direct Drive */
- pPio->PIO_IFDR = ~inputFilter;
- pPio->PIO_IFER = inputFilter;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInput */
-/** \brief Return PIO input value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_PDSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInputSet */
-/** \brief Test if PIO is input flag is active */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInput( pPio ) & flag );
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_SetOutput */
-/** \brief Set to 1 output PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be set */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetAlarmINT()
+//* \brief Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_SODR = flag;
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_ClearOutput */
-/** \brief Set to 0 output PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be cleared */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ClearAlarmINT()
+//* \brief Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_CODR = flag;
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_ForceOutput */
-/** \brief Force output when Direct drive option is enabled */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg output to be forced */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetRttIncINT()
+//* \brief Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_ODSR = flag;
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Enable */
-/** \brief Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ClearRttIncINT()
+//* \brief Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_PER = flag;
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Disable */
-/** \brief Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be disabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetAlarmValue()
+//* \brief Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+ AT91PS_RTTC pRTTC, unsigned int alarm)
{
- pPio->PIO_PDR = flag;
+ pRTTC->RTTC_RTAR = alarm;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetStatus */
-/** \brief Return PIO Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_GetAlarmValue()
+//* \brief Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+ AT91PS_RTTC pRTTC)
{
- return pPio->PIO_PSR;
+ return(pRTTC->RTTC_RTAR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsSet */
-/** \brief Test if PIO is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTGetStatus()
+//* \brief Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+ AT91PS_RTTC pRTTC)
{
- return( AT91F_PIO_GetStatus( pPio ) & flag );
+ return(pRTTC->RTTC_RTSR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputEnable */
-/** \brief Output Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output to be enabled */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ReadValue()
+//* \brief Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+ AT91PS_RTTC pRTTC)
{
- pPio->PIO_OER = flag;
+ register volatile unsigned int val1,val2;
+ do
+ {
+ val1 = pRTTC->RTTC_RTVR;
+ val2 = pRTTC->RTTC_RTVR;
+ }
+ while(val1 != val2);
+ return(val1);
}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputDisable */
-/** \brief Output Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output to be disabled */
-{
- pPio->PIO_ODR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputStatus */
-/** \brief Return PIO Output Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_OSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOuputSet */
-/** \brief Test if PIO Output is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetOutputStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InputFilterEnable */
-/** \brief Input Filter Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio input filter to be enabled */
-{
- pPio->PIO_IFER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InputFilterDisable */
-/** \brief Input Filter Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio input filter to be disabled */
-{
- pPio->PIO_IFDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInputFilterStatus */
-/** \brief Return PIO Input Filter Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_IFSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInputFilterSet */
-/** \brief Test if PIO Input filter is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputDataStatus */
-/** \brief Return PIO Output Data Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_ODSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InterruptEnable */
-/** \brief Enable PIO Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio interrupt to be enabled */
-{
- pPio->PIO_IER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_InterruptDisable */
-/** \brief Disable PIO Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio interrupt to be disabled */
-{
- pPio->PIO_IDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInterruptMaskStatus */
-/** \brief Return PIO Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_IMR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetInterruptStatus */
-/** \brief Return PIO Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_ISR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInterruptMasked */
-/** \brief Test if PIO Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsInterruptSet */
-/** \brief Test if PIO Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetInterruptStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_MultiDriverEnable */
-/** \brief Multi Driver Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be enabled */
-{
- pPio->PIO_MDER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_MultiDriverDisable */
-/** \brief Multi Driver Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio to be disabled */
-{
- pPio->PIO_MDDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetMultiDriverStatus */
-/** \brief Return PIO Multi Driver Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_MDSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsMultiDriverSet */
-/** \brief Test if PIO MultiDriver is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_A_RegisterSelection */
-/** \brief PIO A Register Selection */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio A register selection */
-{
- pPio->PIO_ASR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_B_RegisterSelection */
-/** \brief PIO B Register Selection */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio B register selection */
-{
- pPio->PIO_BSR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_Get_AB_RegisterStatus */
-/** \brief Return PIO Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_ABSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsAB_RegisterSet */
-/** \brief Test if PIO AB Register is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputWriteEnable */
-/** \brief Output Write Enable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output write to be enabled */
-{
- pPio->PIO_OWER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_OutputWriteDisable */
-/** \brief Output Write Disable PIO */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg pio output write to be disabled */
-{
- pPio->PIO_OWDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetOutputWriteStatus */
-/** \brief Return PIO Output Write Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_OWSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOutputWriteSet */
-/** \brief Test if PIO OutputWrite is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_GetCfgPullup */
-/** \brief Return PIO Configuration Pullup */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */
- AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
-{
- return pPio->PIO_PPUSR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsOutputDataStatusSet */
-/** \brief Test if PIO Output Data Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIO_IsCfgPullupStatusSet */
-/** \brief Test if PIO Configuration Pullup Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag );
-}
-
/* *****************************************************************************
-* SOFTWARE API FOR PMC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgSysClkEnableReg */
-/** \brief Configure the System Clock Enable Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
+ SOFTWARE API FOR PITC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITInit
+//* \brief System timer init : period in µsecond, system clock freq in MHz
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITInit(
+ AT91PS_PITC pPITC,
+ unsigned int period,
+ unsigned int pit_frequency)
{
- /** Write to the SCER register */
- pPMC->PMC_SCER = mode;
+ pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+ pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgSysClkDisableReg */
-/** \brief Configure the System Clock Disable Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITSetPIV
+//* \brief Set the PIT Periodic Interval Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITSetPIV(
+ AT91PS_PITC pPITC,
+ unsigned int piv)
{
- /** Write to the SCDR register */
- pPMC->PMC_SCDR = mode;
+ pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetSysClkStatusReg */
-/** \brief Return the System Clock Status Register of the PMC controller */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITEnableInt
+//* \brief Enable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITEnableInt(
+ AT91PS_PITC pPITC)
{
- return pPMC->PMC_SCSR;
+ pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnablePeriphClock */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITDisableInt
+//* \brief Disable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITDisableInt(
+ AT91PS_PITC pPITC)
{
- pPMC->PMC_PCER = periphIds;
+ pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisablePeriphClock */
-/** \brief Disable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetMode
+//* \brief Read PIT mode register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetMode(
+ AT91PS_PITC pPITC)
{
- pPMC->PMC_PCDR = periphIds;
+ return(pPITC->PITC_PIMR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetPeriphClock */
-/** \brief Get peripheral clock status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetStatus
+//* \brief Read PIT status register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetStatus(
+ AT91PS_PITC pPITC)
{
- return pPMC->PMC_PCSR;
+ return(pPITC->PITC_PISR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_CfgMainOscillatorReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetPIIR
+//* \brief Read PIT CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIIR(
+ AT91PS_PITC pPITC)
{
- pCKGR->CKGR_MOR = mode;
+ return(pPITC->PITC_PIIR);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainOscillatorReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetPIVR
+//* \brief Read System timer CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIVR(
+ AT91PS_PITC pPITC)
{
- return pCKGR->CKGR_MOR;
+ return(pPITC->PITC_PIVR);
}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_EnableMainOscillator */
-/** \brief Enable the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
-{
- pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_DisableMainOscillator */
-/** \brief Disable the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
-{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_CfgMainOscStartUpTime */
-/** \brief Cfg MOR Register according to the main osc startup time */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
- unsigned int slowClock ) /* \arg slowClock in Hz */
-{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
- pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainClockFreqReg */
-/** \brief Cfg the main oscillator */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
-{
- return pCKGR->CKGR_MCFR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CKGR_GetMainClock */
-/** \brief Return Main clock in Hz */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int slowClock ) /* \arg slowClock in Hz */
-{
- return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgMCKReg */
-/** \brief Cfg Master Clock Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int mode )
-{
- pPMC->PMC_MCKR = mode;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetMCKReg */
-/** \brief Return Master Clock Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
-{
- return pPMC->PMC_MCKR;
-}
-
-/**------------------------------------------------------------------------------ */
-/** \fn AT91F_PMC_GetMasterClock */
-/** \brief Return master clock in Hz which correponds to processor clock for ARM7 */
-/**------------------------------------------------------------------------------ */
-__inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
- unsigned int slowClock ) /* \arg slowClock in Hz */
-{
- unsigned int reg = pPMC->PMC_MCKR;
- unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) );
- unsigned int pllDivider, pllMultiplier;
-
- switch( reg & AT91C_PMC_CSS )
- {
- case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */
- return slowClock / prescaler;
-
- case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */
- return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
-
- case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */
- reg = pCKGR->CKGR_PLLR;
- pllDivider = ( reg & AT91C_CKGR_DIV );
- pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
- return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
- }
-
- return 0;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnablePCK */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */
- unsigned int mode )
-{
- pPMC->PMC_PCKR[ pck ] = mode;
- pPMC->PMC_SCER = ( 1 << pck ) << 8;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisablePCK */
-/** \brief Enable peripheral clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
- unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */
-{
- pPMC->PMC_SCDR = ( 1 << pck ) << 8;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_EnableIt */
-/** \brief Enable PMC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */
- unsigned int flag ) /* IT to be enabled */
-{
- /** Write to the IER register */
- pPMC->PMC_IER = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_DisableIt */
-/** \brief Disable PMC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */
- unsigned int flag ) /* IT to be disabled */
-{
- /** Write to the IDR register */
- pPMC->PMC_IDR = flag;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetStatus */
-/** \brief Return PMC Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */
- AT91PS_PMC pPMC ) /* pointer to a PMC controller */
-{
- return pPMC->PMC_SR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_GetInterruptMaskStatus */
-/** \brief Return PMC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */
- AT91PS_PMC pPMC ) /* pointer to a PMC controller */
-{
- return pPMC->PMC_IMR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_IsInterruptMasked */
-/** \brief Test if PMC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_IsStatusSet */
-/** \brief Test if PMC Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */
- unsigned int flag ) /* \arg flag to be tested */
-{
- return( AT91F_PMC_GetStatus( pPMC ) & flag );
-} /* *****************************************************************************
- * SOFTWARE API FOR RSTC
- ***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTSoftReset */
-/** \brief Start Software Reset */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC,
- unsigned int reset )
-{
- pRSTC->RSTC_RCR = ( 0xA5000000 | reset );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTSetMode */
-/** \brief Set Reset Mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC,
- unsigned int mode )
-{
- pRSTC->RSTC_RMR = ( 0xA5000000 | mode );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTGetMode */
-/** \brief Get Reset Mode */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC )
-{
- return( pRSTC->RSTC_RMR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTGetStatus */
-/** \brief Get Reset Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC )
-{
- return( pRSTC->RSTC_RSR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTIsSoftRstActive */
-/** \brief Return !=0 if software reset is still not completed */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC )
-{
- return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP );
-}
-
/* *****************************************************************************
-* SOFTWARE API FOR RTTC
-***************************************************************************** */
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_SetRTT_TimeBase() */
-/** \brief Set the RTT prescaler according to the TimeBase in ms */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC,
- unsigned int ms )
+ SOFTWARE API FOR WDTC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTSetMode
+//* \brief Set Watchdog Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTSetMode(
+ AT91PS_WDTC pWDTC,
+ unsigned int Mode)
{
- if( ms > 2000 )
- {
- return 1; /* AT91C_TIME_OUT_OF_RANGE */
- }
-
- pRTTC->RTTC_RTMR &= ~0xFFFF;
- pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF );
- return 0;
+ pWDTC->WDTC_WDMR = Mode;
}
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTTSetPrescaler() */
-/** \brief Set the new prescaler value */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC,
- unsigned int rtpres )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTRestart
+//* \brief Restart Watchdog
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTRestart(
+ AT91PS_WDTC pWDTC)
{
- pRTTC->RTTC_RTMR &= ~0xFFFF;
- pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF );
- return( pRTTC->RTTC_RTMR );
+ pWDTC->WDTC_WDCR = 0xA5000001;
}
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTTRestart() */
-/** \brief Restart the RTT prescaler */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTSGettatus
+//* \brief Get Watchdog Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTSGettatus(
+ AT91PS_WDTC pWDTC)
{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
+ return(pWDTC->WDTC_WDSR & 0x3);
}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_SetAlarmINT() */
-/** \brief Enable RTT Alarm Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTGetPeriod
+//* \brief Translate ms into Watchdog Compatible value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+ if ((ms < 4) || (ms > 16000))
+ return 0;
+ return((ms << 8) / 1000);
}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_ClearAlarmINT() */
-/** \brief Disable RTT Alarm Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_SetRttIncINT() */
-/** \brief Enable RTT INC Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_ClearRttIncINT() */
-/** \brief Disable RTT INC Interrupt */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_SetAlarmValue() */
-/** \brief Set RTT Alarm Value */
-/**-------------------------------------------------------------------------------------- */
-__inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC,
- unsigned int alarm )
-{
- pRTTC->RTTC_RTAR = alarm;
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_GetAlarmValue() */
-/** \brief Get RTT Alarm Value */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC )
-{
- return( pRTTC->RTTC_RTAR );
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTTGetStatus() */
-/** \brief Read the RTT status */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC )
-{
- return( pRTTC->RTTC_RTSR );
-}
-
-/**-------------------------------------------------------------------------------------- */
-/** \fn AT91F_RTT_ReadValue() */
-/** \brief Read the RTT value */
-/**-------------------------------------------------------------------------------------- */
-__inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC )
-{
- register volatile unsigned int val1, val2;
-
- do
- {
- val1 = pRTTC->RTTC_RTVR;
- val2 = pRTTC->RTTC_RTVR;
- }
- while( val1 != val2 );
-
- return( val1 );
-}
-
/* *****************************************************************************
-* SOFTWARE API FOR PITC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITInit */
-/** \brief System timer init : period in µsecond, system clock freq in MHz */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITInit( AT91PS_PITC pPITC,
- unsigned int period,
- unsigned int pit_frequency )
+ SOFTWARE API FOR VREG
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_Enable_LowPowerMode
+//* \brief Enable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Enable_LowPowerMode(
+ AT91PS_VREG pVREG)
{
- pPITC->PITC_PIMR = period ? ( period * pit_frequency + 8 ) >> 4 : 0; /* +8 to avoid %10 and /10 */
- pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
+ pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITSetPIV */
-/** \brief Set the PIT Periodic Interval Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITSetPIV( AT91PS_PITC pPITC,
- unsigned int piv )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_Disable_LowPowerMode
+//* \brief Disable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Disable_LowPowerMode(
+ AT91PS_VREG pVREG)
{
- pPITC->PITC_PIMR = piv | ( pPITC->PITC_PIMR & ( AT91C_PITC_PITEN | AT91C_PITC_PITIEN ) );
-}
+ pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
+}/* *****************************************************************************
+ SOFTWARE API FOR MC
+ ***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITEnableInt */
-/** \brief Enable PIT periodic interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITEnableInt( AT91PS_PITC pPITC )
+#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void) //
{
- pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITDisableInt */
-/** \brief Disable PIT periodic interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITDisableInt( AT91PS_PITC pPITC )
-{
- pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetMode */
-/** \brief Read PIT mode register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetMode( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PIMR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetStatus */
-/** \brief Read PIT status register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetStatus( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PISR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetPIIR */
-/** \brief Read PIT CPIV and PICNT without ressetting the counters */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetPIIR( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PIIR );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITGetPIVR */
-/** \brief Read System timer CPIV and PICNT without ressetting the counters */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PITGetPIVR( AT91PS_PITC pPITC )
-{
- return( pPITC->PITC_PIVR );
-}
-
-/* *****************************************************************************
-* SOFTWARE API FOR WDTC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTSetMode */
-/** \brief Set Watchdog Mode Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_WDTSetMode( AT91PS_WDTC pWDTC,
- unsigned int Mode )
-{
- pWDTC->WDTC_WDMR = Mode;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTRestart */
-/** \brief Restart Watchdog */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_WDTRestart( AT91PS_WDTC pWDTC )
-{
- pWDTC->WDTC_WDCR = 0xA5000001;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTSGettatus */
-/** \brief Get Watchdog Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_WDTSGettatus( AT91PS_WDTC pWDTC )
-{
- return( pWDTC->WDTC_WDSR & 0x3 );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTGetPeriod */
-/** \brief Translate ms into Watchdog Compatible value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_WDTGetPeriod( unsigned int ms )
-{
- if( ( ms < 4 ) || ( ms > 16000 ) )
- {
- return 0;
- }
-
- return( ( ms << 8 ) / 1000 );
-}
-
-/* *****************************************************************************
-* SOFTWARE API FOR VREG
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_VREG_Enable_LowPowerMode */
-/** \brief Enable VREG Low Power Mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_VREG_Enable_LowPowerMode( AT91PS_VREG pVREG )
-{
- pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_VREG_Disable_LowPowerMode */
-/** \brief Disable VREG Low Power Mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_VREG_Disable_LowPowerMode( AT91PS_VREG pVREG )
-{
- pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
-} /* *****************************************************************************
- * SOFTWARE API FOR MC
- ***************************************************************************** */
-
-#define AT91C_MC_CORRECT_KEY ( ( unsigned int ) 0x5A << 24 ) /* (MC) Correct Protect Key */
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_Remap */
-/** \brief Make Remap */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_Remap( void ) /* */
-{
- AT91PS_MC pMC = ( AT91PS_MC ) AT91C_BASE_MC;
+ AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
pMC->MC_RCR = AT91C_MC_RCB;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_CfgModeReg */
-/** \brief Configure the EFC Mode Register of the MC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, /* pointer to a MC controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+ AT91PS_MC pMC, // pointer to a MC controller
+ unsigned int mode) // mode register
{
- /* Write to the FMR register */
- pMC->MC_FMR = mode;
+ // Write to the FMR register
+ pMC->MC_FMR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_GetModeReg */
-/** \brief Return MC EFC Mode Regsiter */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+ AT91PS_MC pMC) // pointer to a MC controller
{
- return pMC->MC_FMR;
+ return pMC->MC_FMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_ComputeFMCN */
-/** \brief Return MC EFC Mode Regsiter */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+ int master_clock) // master clock in Hz
{
- return( master_clock / 1000000 + 2 );
+ return (master_clock/1000000 +2);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_PerformCmd */
-/** \brief Perform EFC Command */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_EFC_PerformCmd( AT91PS_MC pMC, /* pointer to a MC controller */
- unsigned int transfer_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+ AT91PS_MC pMC, // pointer to a MC controller
+ unsigned int transfer_cmd)
{
- pMC->MC_FCR = transfer_cmd;
+ pMC->MC_FCR = transfer_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_GetStatus */
-/** \brief Return MC EFC Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_GetStatus( AT91PS_MC pMC ) /* pointer to a MC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+ AT91PS_MC pMC) // pointer to a MC controller
{
- return pMC->MC_FSR;
+ return pMC->MC_FSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_IsInterruptMasked */
-/** \brief Test if EFC MC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( AT91PS_MC pMC, /* \arg pointer to a MC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+ AT91PS_MC pMC, // \arg pointer to a MC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_MC_EFC_GetModeReg( pMC ) & flag );
+ return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_EFC_IsInterruptSet */
-/** \brief Test if EFC MC Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, /* \arg pointer to a MC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+ AT91PS_MC pMC, // \arg pointer to a MC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_MC_EFC_GetStatus( pMC ) & flag );
+ return (AT91F_MC_EFC_GetStatus(pMC) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR SPI
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Open */
-/** \brief Open a SPI Port */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_Open( const unsigned int null ) /* \arg */
+ SOFTWARE API FOR SPI
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+ const unsigned int null) // \arg
{
- /* NOT DEFINED AT THIS MOMENT */
- return( 0 );
+ /* NOT DEFINED AT THIS MOMENT */
+ return ( 0 );
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgCs */
-/** \brief Configure SPI chip select register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgCs( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- int cs, /* SPI cs number (0 to 3) */
- int val ) /* chip select register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ int cs, // SPI cs number (0 to 3)
+ int val) // chip select register
{
- /** Write to the CSR register */
- *( pSPI->SPI_CSR + cs ) = val;
+ //* Write to the CSR register
+ *(pSPI->SPI_CSR + cs) = val;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_EnableIt */
-/** \brief Enable SPI interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_EnableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pSPI->SPI_IER = flag;
+ //* Write to the IER register
+ pSPI->SPI_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_DisableIt */
-/** \brief Disable SPI interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_DisableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pSPI->SPI_IDR = flag;
+ //* Write to the IDR register
+ pSPI->SPI_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Reset */
-/** \brief Reset the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Reset( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
- pSPI->SPI_CR = AT91C_SPI_SWRST;
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Enable */
-/** \brief Enable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Enable( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
- pSPI->SPI_CR = AT91C_SPI_SPIEN;
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Disable */
-/** \brief Disable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Disable( AT91PS_SPI pSPI /* pointer to a SPI controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
{
- /** Write to the CR register */
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ int mode) // mode register
+{
+ //* Write to the MR register
+ pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ char PCS_Device) // PCS of the Device
+{
+ //* Write to the MR register
+ pSPI->SPI_MR &= 0xFFF0FFFF;
+ pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+ AT91PS_SPI pSPI,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pSPI->SPI_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+ AT91PS_SPI pSPI,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pSPI->SPI_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+ AT91PS_SPI pSPI) // \arg pointer to a SPI controller
+{
+ //* Reset all the Chip Select register
+ pSPI->SPI_CSR[0] = 0 ;
+ pSPI->SPI_CSR[1] = 0 ;
+ pSPI->SPI_CSR[2] = 0 ;
+ pSPI->SPI_CSR[3] = 0 ;
+
+ //* Reset the SPI mode
+ pSPI->SPI_MR = 0 ;
+
+ //* Disable all interrupts
+ pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+ //* Abort the Peripheral Data Transfers
+ AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+ //* Disable receiver and transmitter and stop any activity immediately
pSPI->SPI_CR = AT91C_SPI_SPIDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgMode */
-/** \brief Enable the SPI controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgMode( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- int mode ) /* mode register */
-{
- /** Write to the MR register */
- pSPI->SPI_MR = mode;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_CfgPCS */
-/** \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_CfgPCS( AT91PS_SPI pSPI, /* pointer to a SPI controller */
- char PCS_Device ) /* PCS of the Device */
-{
- /** Write to the MR register */
- pSPI->SPI_MR &= 0xFFF0FFFF;
- pSPI->SPI_MR |= ( ( PCS_Device << 16 ) & AT91C_SPI_PCS );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_ReceiveFrame( AT91PS_SPI pSPI,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_Close */
-/** \brief Close SPI: disable IT disable transfert, close PDC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */
-{
- /** Reset all the Chip Select register */
- pSPI->SPI_CSR[ 0 ] = 0;
- pSPI->SPI_CSR[ 1 ] = 0;
- pSPI->SPI_CSR[ 2 ] = 0;
- pSPI->SPI_CSR[ 3 ] = 0;
-
- /** Reset the SPI mode */
- pSPI->SPI_MR = 0;
-
- /** Disable all interrupts */
- pSPI->SPI_IDR = 0xFFFFFFFF;
-
- /** Abort the Peripheral Data Transfers */
- AT91F_PDC_Close( ( AT91PS_PDC ) &( pSPI->SPI_RPR ) );
-
- /** Disable receiver and transmitter and stop any activity immediately */
- pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_PutChar */
-/** \brief Send a character,does not check if ready to send */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI_PutChar( AT91PS_SPI pSPI,
- unsigned int character,
- unsigned int cs_number )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+ AT91PS_SPI pSPI,
+ unsigned int character,
+ unsigned int cs_number )
{
unsigned int value_for_cs;
-
- value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; /*Place a zero among a 4 ONEs number */
- pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 );
+ value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number
+ pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_GetChar */
-/** \brief Receive a character,does not check if a character is available */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SPI_GetChar( const AT91PS_SPI pSPI )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+ const AT91PS_SPI pSPI)
{
- return( ( pSPI->SPI_RDR ) & 0xFFFF );
+ return((pSPI->SPI_RDR) & 0xFFFF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_GetInterruptMaskStatus */
-/** \brief Return SPI Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( /* \return SPI Interrupt Mask Status */
- AT91PS_SPI pSpi ) /* \arg pointer to a SPI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+ AT91PS_SPI pSpi) // \arg pointer to a SPI controller
{
- return pSpi->SPI_IMR;
+ return pSpi->SPI_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI_IsInterruptMasked */
-/** \brief Test if SPI Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi, /* \arg pointer to a SPI controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+ AT91PS_SPI pSpi, // \arg pointer to a SPI controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_SPI_GetInterruptMaskStatus( pSpi ) & flag );
+ return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR USART
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Baudrate */
-/** \brief Calculate the baudrate */
-/** Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_ASYNC_MODE \
- ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+ SOFTWARE API FOR USART
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/** Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_ASYNC_SCK_MODE \
- ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_EXT )
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_EXT )
-/** Standard Synchronous Mode : 8 bits , 1 stop , no parity */
-#define AT91C_US_SYNC_MODE \
- ( AT91C_US_SYNC + \
- AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+ AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/** SCK used Label */
-#define AT91C_US_SCK_USED ( AT91C_US_CKLO | AT91C_US_CLKS_EXT )
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-/** Standard ISO T=0 Mode : 8 bits , 1 stop , parity */
-#define AT91C_US_ISO_READER_MODE \
- ( AT91C_US_USMODE_ISO7816_0 + \
- AT91C_US_CLKS_CLOCK + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_EVEN + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CKLO + \
- AT91C_US_OVER )
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+ AT91C_US_CLKS_CLOCK +\
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_EVEN + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CKLO +\
+ AT91C_US_OVER)
-/** Standard IRDA mode */
-#define AT91C_US_ASYNC_IRDA_MODE \
- ( AT91C_US_USMODE_IRDA + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Baudrate */
-/** \brief Caluculate baud_value according to the main clock and the baud rate */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_Baudrate( const unsigned int main_clock, /* \arg peripheral clock */
- const unsigned int baud_rate ) /* \arg UART baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+ const unsigned int main_clock, // \arg peripheral clock
+ const unsigned int baud_rate) // \arg UART baudrate
{
- unsigned int baud_value = ( ( main_clock * 10 ) / ( baud_rate * 16 ) );
-
- if( ( baud_value % 10 ) >= 5 )
- {
- baud_value = ( baud_value / 10 ) + 1;
- }
- else
- {
- baud_value /= 10;
- }
-
- return baud_value;
+ unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+ if ((baud_value % 10) >= 5)
+ baud_value = (baud_value / 10) + 1;
+ else
+ baud_value /= 10;
+ return baud_value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetBaudrate */
-/** \brief Set the baudrate according to the CPU clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetBaudrate( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int speed ) /* \arg UART baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int speed) // \arg UART baudrate
{
- /** Define the baud rate divisor register */
- pUSART->US_BRGR = AT91F_US_Baudrate( mainClock, speed );
+ //* Define the baud rate divisor register
+ pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetTimeguard */
-/** \brief Set USART timeguard */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetTimeguard( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int timeguard ) /* \arg timeguard value */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int timeguard) // \arg timeguard value
{
- /** Write the Timeguard Register */
- pUSART->US_TTGR = timeguard;
+ //* Write the Timeguard Register
+ pUSART->US_TTGR = timeguard ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableIt */
-/** \brief Enable USART IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int flag ) /* \arg IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pUSART->US_IER = flag;
+ //* Write to the IER register
+ pUSART->US_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableIt */
-/** \brief Disable USART IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IER register */
- pUSART->US_IDR = flag;
+ //* Write to the IER register
+ pUSART->US_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Configure */
-/** \brief Configure USART */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_Configure( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int mode, /* \arg mode Register to be programmed */
- unsigned int baudRate, /* \arg baudrate to be programmed */
- unsigned int timeguard ) /* \arg timeguard to be programmed */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int mode , // \arg mode Register to be programmed
+ unsigned int baudRate , // \arg baudrate to be programmed
+ unsigned int timeguard ) // \arg timeguard to be programmed
{
- /** Disable interrupts */
- pUSART->US_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pUSART->US_IDR = (unsigned int) -1;
- /** Reset receiver and transmitter */
- pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
+ //* Reset receiver and transmitter
+ pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
- /** Define the baud rate divisor register */
- AT91F_US_SetBaudrate( pUSART, mainClock, baudRate );
+ //* Define the baud rate divisor register
+ AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
- /** Write the Timeguard Register */
- AT91F_US_SetTimeguard( pUSART, timeguard );
+ //* Write the Timeguard Register
+ AT91F_US_SetTimeguard(pUSART, timeguard);
- /** Clear Transmit and Receive Counters */
- AT91F_PDC_Open( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
+ //* Clear Transmit and Receive Counters
+ AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
- /** Define the USART mode */
- pUSART->US_MR = mode;
+ //* Define the USART mode
+ pUSART->US_MR = mode ;
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableRx */
-/** \brief Enable receiving characters */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Enable receiver */
+ //* Enable receiver
pUSART->US_CR = AT91C_US_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_EnableTx */
-/** \brief Enable sending characters */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_EnableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Enable transmitter */
+ //* Enable transmitter
pUSART->US_CR = AT91C_US_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ResetRx */
-/** \brief Reset Receiver and re-enable it */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_ResetRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset receiver */
- pUSART->US_CR = AT91C_US_RSTRX;
- /** Re-Enable receiver */
+ //* Reset receiver
+ pUSART->US_CR = AT91C_US_RSTRX;
+ //* Re-Enable receiver
pUSART->US_CR = AT91C_US_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ResetTx */
-/** \brief Reset Transmitter and re-enable it */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_ResetTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset transmitter */
- pUSART->US_CR = AT91C_US_RSTTX;
- /** Enable transmitter */
+ //* Reset transmitter
+ pUSART->US_CR = AT91C_US_RSTTX;
+ //* Enable transmitter
pUSART->US_CR = AT91C_US_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableRx */
-/** \brief Disable Receiver */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Disable receiver */
+ //* Disable receiver
pUSART->US_CR = AT91C_US_RXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_DisableTx */
-/** \brief Disable Transmitter */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_DisableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Disable transmitter */
+ //* Disable transmitter
pUSART->US_CR = AT91C_US_TXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Close */
-/** \brief Close USART: disable IT disable receiver and transmitter, close PDC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_Close( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
{
- /** Reset the baud rate divisor register */
- pUSART->US_BRGR = 0;
+ //* Reset the baud rate divisor register
+ pUSART->US_BRGR = 0 ;
- /** Reset the USART mode */
- pUSART->US_MR = 0;
+ //* Reset the USART mode
+ pUSART->US_MR = 0 ;
- /** Reset the Timeguard Register */
+ //* Reset the Timeguard Register
pUSART->US_TTGR = 0;
- /** Disable all interrupts */
- pUSART->US_IDR = 0xFFFFFFFF;
+ //* Disable all interrupts
+ pUSART->US_IDR = 0xFFFFFFFF ;
- /** Abort the Peripheral Data Transfers */
- AT91F_PDC_Close( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
+ //* Abort the Peripheral Data Transfers
+ AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
- /** Disable receiver and transmitter and stop any activity immediately */
- pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
+ //* Disable receiver and transmitter and stop any activity immediately
+ pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_TxReady */
-/** \brief Return 1 if a character can be written in US_THR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_TxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR & AT91C_US_TXRDY );
+ return (pUSART->US_CSR & AT91C_US_TXRDY);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_RxReady */
-/** \brief Return 1 if a character can be read in US_RHR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_RxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR & AT91C_US_RXRDY );
+ return (pUSART->US_CSR & AT91C_US_RXRDY);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_Error */
-/** \brief Return the error flag */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_Error( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
- return( pUSART->US_CSR &
- ( AT91C_US_OVRE | /* Overrun error */
- AT91C_US_FRAME | /* Framing error */
- AT91C_US_PARE ) ); /* Parity error */
+ return (pUSART->US_CSR &
+ (AT91C_US_OVRE | // Overrun error
+ AT91C_US_FRAME | // Framing error
+ AT91C_US_PARE)); // Parity error
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_PutChar */
-/** \brief Send a character,does not check if ready to send */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_PutChar( AT91PS_USART pUSART,
- int character )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+ AT91PS_USART pUSART,
+ int character )
{
- pUSART->US_THR = ( character & 0x1FF );
+ pUSART->US_THR = (character & 0x1FF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_GetChar */
-/** \brief Receive a character,does not check if a character is available */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_US_GetChar( const AT91PS_USART pUSART )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+ const AT91PS_USART pUSART)
{
- return( ( pUSART->US_RHR ) & 0x1FF );
+ return((pUSART->US_RHR) & 0x1FF);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_SendFrame( AT91PS_USART pUSART,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+ AT91PS_USART pUSART,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pUSART->US_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pUSART->US_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_US_ReceiveFrame( AT91PS_USART pUSART,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+ AT91PS_USART pUSART,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pUSART->US_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pUSART->US_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US_SetIrdaFilter */
-/** \brief Set the value of IrDa filter tregister */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US_SetIrdaFilter( AT91PS_USART pUSART,
- unsigned char value )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+ AT91PS_USART pUSART,
+ unsigned char value
+)
{
- pUSART->US_IF = value;
+ pUSART->US_IF = value;
}
/* *****************************************************************************
-* SOFTWARE API FOR SSC
-***************************************************************************** */
-/** Define the standard I2S mode configuration */
+ SOFTWARE API FOR SSC
+ ***************************************************************************** */
+//* Define the standard I2S mode configuration
-/** Configuration to set in the SSC Transmit Clock Mode Register */
-/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
-/** nb_slot_by_frame : number of channels */
-#define AT91C_I2S_ASY_MASTER_TX_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
- ( + \
- AT91C_SSC_CKS_DIV + \
- AT91C_SSC_CKO_CONTINOUS + \
- AT91C_SSC_CKG_NONE + \
- AT91C_SSC_START_FALL_RF + \
- AT91C_SSC_STTOUT + \
- ( ( 1 << 16 ) & AT91C_SSC_STTDLY ) + \
- ( ( ( ( nb_bit_by_slot * nb_slot_by_frame ) / 2 ) - 1 ) << 24 ) )
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ AT91C_SSC_CKS_DIV +\
+ AT91C_SSC_CKO_CONTINOUS +\
+ AT91C_SSC_CKG_NONE +\
+ AT91C_SSC_START_FALL_RF +\
+ AT91C_SSC_STTOUT +\
+ ((1<<16) & AT91C_SSC_STTDLY) +\
+ ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
-/** Configuration to set in the SSC Transmit Frame Mode Register */
-/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
-/** nb_slot_by_frame : number of channels */
-#define AT91C_I2S_ASY_TX_FRAME_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
- ( + \
- ( nb_bit_by_slot - 1 ) + \
- AT91C_SSC_MSBF + \
- ( ( ( nb_slot_by_frame - 1 ) << 8 ) & AT91C_SSC_DATNB ) + \
- ( ( ( nb_bit_by_slot - 1 ) << 16 ) & AT91C_SSC_FSLEN ) + \
- AT91C_SSC_FSOS_NEGATIVE )
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ (nb_bit_by_slot-1) +\
+ AT91C_SSC_MSBF +\
+ (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
+ (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+ AT91C_SSC_FSOS_NEGATIVE)
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_SetBaudrate */
-/** \brief Set the baudrate according to the CPU clock */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_SetBaudrate( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int mainClock, /* \arg peripheral clock */
- unsigned int speed ) /* \arg SSC baudrate */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int speed) // \arg SSC baudrate
{
- unsigned int baud_value;
-
- /** Define the baud rate divisor register */
- if( speed == 0 )
- {
- baud_value = 0;
- }
- else
- {
- baud_value = ( unsigned int ) ( mainClock * 10 ) / ( 2 * speed );
-
- if( ( baud_value % 10 ) >= 5 )
- {
- baud_value = ( baud_value / 10 ) + 1;
- }
+ unsigned int baud_value;
+ //* Define the baud rate divisor register
+ if (speed == 0)
+ baud_value = 0;
else
{
- baud_value /= 10;
+ baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+ if ((baud_value % 10) >= 5)
+ baud_value = (baud_value / 10) + 1;
+ else
+ baud_value /= 10;
}
- }
- pSSC->SSC_CMR = baud_value;
+ pSSC->SSC_CMR = baud_value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_Configure */
-/** \brief Configure SSC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_Configure( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int syst_clock, /* \arg System Clock Frequency */
- unsigned int baud_rate, /* \arg Expected Baud Rate Frequency */
- unsigned int clock_rx, /* \arg Receiver Clock Parameters */
- unsigned int mode_rx, /* \arg mode Register to be programmed */
- unsigned int clock_tx, /* \arg Transmitter Clock Parameters */
- unsigned int mode_tx ) /* \arg mode Register to be programmed */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int syst_clock, // \arg System Clock Frequency
+ unsigned int baud_rate, // \arg Expected Baud Rate Frequency
+ unsigned int clock_rx, // \arg Receiver Clock Parameters
+ unsigned int mode_rx, // \arg mode Register to be programmed
+ unsigned int clock_tx, // \arg Transmitter Clock Parameters
+ unsigned int mode_tx) // \arg mode Register to be programmed
{
- /** Disable interrupts */
- pSSC->SSC_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pSSC->SSC_IDR = (unsigned int) -1;
- /** Reset receiver and transmitter */
- pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS;
+ //* Reset receiver and transmitter
+ pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
- /** Define the Clock Mode Register */
- AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate );
+ //* Define the Clock Mode Register
+ AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
- /** Write the Receive Clock Mode Register */
- pSSC->SSC_RCMR = clock_rx;
+ //* Write the Receive Clock Mode Register
+ pSSC->SSC_RCMR = clock_rx;
- /** Write the Transmit Clock Mode Register */
- pSSC->SSC_TCMR = clock_tx;
+ //* Write the Transmit Clock Mode Register
+ pSSC->SSC_TCMR = clock_tx;
- /** Write the Receive Frame Mode Register */
- pSSC->SSC_RFMR = mode_rx;
+ //* Write the Receive Frame Mode Register
+ pSSC->SSC_RFMR = mode_rx;
- /** Write the Transmit Frame Mode Register */
- pSSC->SSC_TFMR = mode_tx;
+ //* Write the Transmit Frame Mode Register
+ pSSC->SSC_TFMR = mode_tx;
- /** Clear Transmit and Receive Counters */
- AT91F_PDC_Open( ( AT91PS_PDC ) &( pSSC->SSC_RPR ) );
+ //* Clear Transmit and Receive Counters
+ AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableRx */
-/** \brief Enable receiving datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Enable receiver */
+ //* Enable receiver
pSSC->SSC_CR = AT91C_SSC_RXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableRx */
-/** \brief Disable receiving datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Disable receiver */
+ //* Disable receiver
pSSC->SSC_CR = AT91C_SSC_RXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableTx */
-/** \brief Enable sending datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Enable transmitter */
+ //* Enable transmitter
pSSC->SSC_CR = AT91C_SSC_TXEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableTx */
-/** \brief Disable sending datas */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
- /** Disable transmitter */
+ //* Disable transmitter
pSSC->SSC_CR = AT91C_SSC_TXDIS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_EnableIt */
-/** \brief Enable SSC IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_EnableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pSSC->SSC_IER = flag;
+ //* Write to the IER register
+ pSSC->SSC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_DisableIt */
-/** \brief Disable SSC IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_DisableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pSSC->SSC_IDR = flag;
+ //* Write to the IDR register
+ pSSC->SSC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_ReceiveFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_ReceiveFrame( AT91PS_SSC pSSC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+ AT91PS_SSC pSSC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_ReceiveFrame(
- ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pSSC->SSC_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_SendFrame */
-/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_SendFrame( AT91PS_SSC pSSC,
- char * pBuffer,
- unsigned int szBuffer,
- char * pNextBuffer,
- unsigned int szNextBuffer )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+ AT91PS_SSC pSSC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
{
- return AT91F_PDC_SendFrame(
- ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer );
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pSSC->SSC_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_GetInterruptMaskStatus */
-/** \brief Return SSC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( /* \return SSC Interrupt Mask Status */
- AT91PS_SSC pSsc ) /* \arg pointer to a SSC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+ AT91PS_SSC pSsc) // \arg pointer to a SSC controller
{
- return pSsc->SSC_IMR;
+ return pSsc->SSC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_IsInterruptMasked */
-/** \brief Test if SSC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc, /* \arg pointer to a SSC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+ AT91PS_SSC pSsc, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_SSC_GetInterruptMaskStatus( pSsc ) & flag );
+ return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR TWI
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_EnableIt */
-/** \brief Enable TWI IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_EnableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg IT to be enabled */
+ SOFTWARE API FOR TWI
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pTWI->TWI_IER = flag;
+ //* Write to the IER register
+ pTWI->TWI_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_DisableIt */
-/** \brief Disable TWI IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_DisableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pTWI->TWI_IDR = flag;
+ //* Write to the IDR register
+ pTWI->TWI_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_Configure */
-/** \brief Configure TWI in master mode */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_Configure( AT91PS_TWI pTWI ) /* \arg pointer to a TWI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller
{
- /** Disable interrupts */
- pTWI->TWI_IDR = ( unsigned int ) -1;
+ //* Disable interrupts
+ pTWI->TWI_IDR = (unsigned int) -1;
- /** Reset peripheral */
- pTWI->TWI_CR = AT91C_TWI_SWRST;
+ //* Reset peripheral
+ pTWI->TWI_CR = AT91C_TWI_SWRST;
- /** Set Master mode */
- pTWI->TWI_CR = AT91C_TWI_MSEN;
+ //* Set Master mode
+ pTWI->TWI_CR = AT91C_TWI_MSEN;
+
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_GetInterruptMaskStatus */
-/** \brief Return TWI Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( /* \return TWI Interrupt Mask Status */
- AT91PS_TWI pTwi ) /* \arg pointer to a TWI controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+ AT91PS_TWI pTwi) // \arg pointer to a TWI controller
{
- return pTwi->TWI_IMR;
+ return pTwi->TWI_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_IsInterruptMasked */
-/** \brief Test if TWI Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi, /* \arg pointer to a TWI controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+ AT91PS_TWI pTwi, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_TWI_GetInterruptMaskStatus( pTwi ) & flag );
+ return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR PWMC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_GetStatus */
-/** \brief Return PWM Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_GetStatus( /* \return PWM Interrupt Status */
- AT91PS_PWMC pPWM ) /* pointer to a PWM controller */
+ SOFTWARE API FOR PWMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+ AT91PS_PWMC pPWM) // pointer to a PWM controller
{
- return pPWM->PWMC_SR;
+ return pPWM->PWMC_SR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_InterruptEnable */
-/** \brief Enable PWM Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_InterruptEnable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg PWM interrupt to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg PWM interrupt to be enabled
{
- pPwm->PWMC_IER = flag;
+ pPwm->PWMC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_InterruptDisable */
-/** \brief Disable PWM Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_InterruptDisable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg PWM interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg PWM interrupt to be disabled
{
- pPwm->PWMC_IDR = flag;
+ pPwm->PWMC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_GetInterruptMaskStatus */
-/** \brief Return PWM Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( /* \return PWM Interrupt Mask Status */
- AT91PS_PWMC pPwm ) /* \arg pointer to a PWM controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+ AT91PS_PWMC pPwm) // \arg pointer to a PWM controller
{
- return pPwm->PWMC_IMR;
+ return pPwm->PWMC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_IsInterruptMasked */
-/** \brief Test if PWM Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_IsInterruptMasked( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PWMC_GetInterruptMaskStatus( pPWM ) & flag );
+ return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_IsStatusSet */
-/** \brief Test if PWM Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_PWMC_IsStatusSet( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_PWMC_GetStatus( pPWM ) & flag );
+ return (AT91F_PWMC_GetStatus(pPWM) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_CfgChannel */
-/** \brief Test if PWM Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int channelId, /* \arg PWM channel ID */
- unsigned int mode, /* \arg PWM mode */
- unsigned int period, /* \arg PWM period */
- unsigned int duty ) /* \arg PWM duty cycle */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int channelId, // \arg PWM channel ID
+ unsigned int mode, // \arg PWM mode
+ unsigned int period, // \arg PWM period
+ unsigned int duty) // \arg PWM duty cycle
{
- pPWM->PWMC_CH[ channelId ].PWMC_CMR = mode;
- pPWM->PWMC_CH[ channelId ].PWMC_CDTYR = duty;
- pPWM->PWMC_CH[ channelId ].PWMC_CPRDR = period;
+ pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+ pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+ pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_StartChannel */
-/** \brief Enable channel */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_ENA = flag;
+ pPWM->PWMC_ENA = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_StopChannel */
-/** \brief Disable channel */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int flag ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_DIS = flag;
+ pPWM->PWMC_DIS = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWM_UpdateChannel */
-/** \brief Update Period or Duty Cycle */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
- unsigned int channelId, /* \arg PWM channel ID */
- unsigned int update ) /* \arg Channels IDs to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int channelId, // \arg PWM channel ID
+ unsigned int update) // \arg Channels IDs to be enabled
{
- pPWM->PWMC_CH[ channelId ].PWMC_CUPDR = update;
+ pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
}
/* *****************************************************************************
-* SOFTWARE API FOR UDP
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EnableIt */
-/** \brief Enable UDP IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EnableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg IT to be enabled */
+ SOFTWARE API FOR UDP
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg IT to be enabled
{
- /** Write to the IER register */
- pUDP->UDP_IER = flag;
+ //* Write to the IER register
+ pUDP->UDP_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_DisableIt */
-/** \brief Disable UDP IT */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_DisableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg IT to be disabled
{
- /** Write to the IDR register */
- pUDP->UDP_IDR = flag;
+ //* Write to the IDR register
+ pUDP->UDP_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_SetAddress */
-/** \brief Set UDP functional address */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_SetAddress( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char address ) /* \arg new UDP address */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char address) // \arg new UDP address
{
- pUDP->UDP_FADDR = ( AT91C_UDP_FEN | address );
+ pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EnableEp */
-/** \brief Enable Endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EnableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_EPEDS;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_DisableEp */
-/** \brief Enable Endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_DisableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] &= ~AT91C_UDP_EPEDS;
+ pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_SetState */
-/** \brief Set UDP Device state */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_SetState( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg new UDP address */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg new UDP address
{
- pUDP->UDP_GLBSTATE &= ~( AT91C_UDP_FADDEN | AT91C_UDP_CONFG );
- pUDP->UDP_GLBSTATE |= flag;
+ pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+ pUDP->UDP_GLBSTATE |= flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_GetState */
-/** \brief return UDP Device state */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_GetState( /* \return the UDP device state */
- AT91PS_UDP pUDP ) /* \arg pointer to a UDP controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+ AT91PS_UDP pUDP) // \arg pointer to a UDP controller
{
- return( pUDP->UDP_GLBSTATE & ( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ) );
+ return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_ResetEp */
-/** \brief Reset UDP endpoint */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_ResetEp( /* \return the UDP device state */
- AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg Endpoints to be reset */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg Endpoints to be reset
{
- pUDP->UDP_RSTEP = flag;
- pUDP->UDP_RSTEP = 0;
+ pUDP->UDP_RSTEP = flag;
+ pUDP->UDP_RSTEP = 0;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpStall */
-/** \brief Endpoint will STALL requests */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpStall( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_FORCESTALL;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpWrite */
-/** \brief Write value in the DPR */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpWrite( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned char value ) /* \arg value to be written in the DPR */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned char value) // \arg value to be written in the DPR
{
- pUDP->UDP_FDR[ endpoint ] = value;
+ pUDP->UDP_FDR[endpoint] = value;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpRead */
-/** \brief Return value from the DPR */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_EpRead( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- return pUDP->UDP_FDR[ endpoint ];
+ return pUDP->UDP_FDR[endpoint];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpEndOfWr */
-/** \brief Notify the UDP that values in DPR are ready to be sent */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpEndOfWr( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_TXPKTRDY;
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpClear */
-/** \brief Clear flag in the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpClear( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned int flag ) /* \arg flag to be cleared */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned int flag) // \arg flag to be cleared
{
- pUDP->UDP_CSR[ endpoint ] &= ~( flag );
+ pUDP->UDP_CSR[endpoint] &= ~(flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpSet */
-/** \brief Set flag in the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_EpSet( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint, /* \arg endpoint number */
- unsigned int flag ) /* \arg flag to be cleared */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned int flag) // \arg flag to be cleared
{
- pUDP->UDP_CSR[ endpoint ] |= flag;
+ pUDP->UDP_CSR[endpoint] |= flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_EpStatus */
-/** \brief Return the endpoint CSR register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_EpStatus( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
- unsigned char endpoint ) /* \arg endpoint number */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
{
- return pUDP->UDP_CSR[ endpoint ];
+ return pUDP->UDP_CSR[endpoint];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_GetInterruptMaskStatus */
-/** \brief Return UDP Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( /* \return UDP Interrupt Mask Status */
- AT91PS_UDP pUdp ) /* \arg pointer to a UDP controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+ AT91PS_UDP pUdp) // \arg pointer to a UDP controller
{
- return pUdp->UDP_IMR;
+ return pUdp->UDP_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_IsInterruptMasked */
-/** \brief Test if UDP Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp, /* \arg pointer to a UDP controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+ AT91PS_UDP pUdp, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_UDP_GetInterruptMaskStatus( pUdp ) & flag );
+ return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR TC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_InterruptEnable */
-/** \brief Enable TC Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC_InterruptEnable( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg TC interrupt to be enabled */
+ SOFTWARE API FOR TC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg TC interrupt to be enabled
{
- pTc->TC_IER = flag;
+ pTc->TC_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_InterruptDisable */
-/** \brief Disable TC Interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC_InterruptDisable( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg TC interrupt to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg TC interrupt to be disabled
{
- pTc->TC_IDR = flag;
+ pTc->TC_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_GetInterruptMaskStatus */
-/** \brief Return TC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TC_GetInterruptMaskStatus( /* \return TC Interrupt Mask Status */
- AT91PS_TC pTc ) /* \arg pointer to a TC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+ AT91PS_TC pTc) // \arg pointer to a TC controller
{
- return pTc->TC_IMR;
+ return pTc->TC_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC_IsInterruptMasked */
-/** \brief Test if TC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline int AT91F_TC_IsInterruptMasked( AT91PS_TC pTc, /* \arg pointer to a TC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_TC_GetInterruptMaskStatus( pTc ) & flag );
+ return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
}
/* *****************************************************************************
-* SOFTWARE API FOR CAN
-***************************************************************************** */
-#define STANDARD_FORMAT 0
-#define EXTENDED_FORMAT 1
+ SOFTWARE API FOR CAN
+ ***************************************************************************** */
+#define STANDARD_FORMAT 0
+#define EXTENDED_FORMAT 1
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_InitMailboxRegisters() */
-/** \brief Configure the corresponding mailbox */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_InitMailboxRegisters( AT91PS_CAN_MB CAN_Mailbox,
- int mode_reg,
- int acceptance_mask_reg,
- int id_reg,
- int data_low_reg,
- int data_high_reg,
- int control_reg )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_InitMailboxRegisters()
+//* \brief Configure the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox,
+ int mode_reg,
+ int acceptance_mask_reg,
+ int id_reg,
+ int data_low_reg,
+ int data_high_reg,
+ int control_reg)
{
- CAN_Mailbox->CAN_MB_MCR = 0x0;
- CAN_Mailbox->CAN_MB_MMR = mode_reg;
- CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;
- CAN_Mailbox->CAN_MB_MID = id_reg;
- CAN_Mailbox->CAN_MB_MDL = data_low_reg;
- CAN_Mailbox->CAN_MB_MDH = data_high_reg;
- CAN_Mailbox->CAN_MB_MCR = control_reg;
+ CAN_Mailbox->CAN_MB_MCR = 0x0;
+ CAN_Mailbox->CAN_MB_MMR = mode_reg;
+ CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;
+ CAN_Mailbox->CAN_MB_MID = id_reg;
+ CAN_Mailbox->CAN_MB_MDL = data_low_reg;
+ CAN_Mailbox->CAN_MB_MDH = data_high_reg;
+ CAN_Mailbox->CAN_MB_MCR = control_reg;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_EnableCAN() */
-/** \brief */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_EnableCAN( AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_EnableCAN()
+//* \brief
+//*----------------------------------------------------------------------------
+__inline void AT91F_EnableCAN(
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- pCAN->CAN_MR |= AT91C_CAN_CANEN;
+ pCAN->CAN_MR |= AT91C_CAN_CANEN;
- /* Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver */
- while( ( pCAN->CAN_SR & AT91C_CAN_WAKEUP ) != AT91C_CAN_WAKEUP )
- {
- }
+ // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
+ while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DisableCAN() */
-/** \brief */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DisableCAN( AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DisableCAN()
+//* \brief
+//*----------------------------------------------------------------------------
+__inline void AT91F_DisableCAN(
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
+ pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_EnableIt */
-/** \brief Enable CAN interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_EnableIt( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_EnableIt
+//* \brief Enable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_EnableIt (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pCAN->CAN_IER = flag;
+ //* Write to the IER register
+ pCAN->CAN_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_DisableIt */
-/** \brief Disable CAN interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_DisableIt( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_DisableIt
+//* \brief Disable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_DisableIt (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pCAN->CAN_IDR = flag;
+ //* Write to the IDR register
+ pCAN->CAN_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetStatus */
-/** \brief Return CAN Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetStatus( /* \return CAN Interrupt Status */
- AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetStatus
+//* \brief Return CAN Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- return pCAN->CAN_SR;
+ return pCAN->CAN_SR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetInterruptMaskStatus */
-/** \brief Return CAN Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( /* \return CAN Interrupt Mask Status */
- AT91PS_CAN pCAN ) /* pointer to a CAN controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetInterruptMaskStatus
+//* \brief Return CAN Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
+ AT91PS_CAN pCAN) // pointer to a CAN controller
{
- return pCAN->CAN_IMR;
+ return pCAN->CAN_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_IsInterruptMasked */
-/** \brief Test if CAN Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_IsInterruptMasked( AT91PS_CAN pCAN, /* \arg pointer to a CAN controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_IsInterruptMasked
+//* \brief Test if CAN Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsInterruptMasked(
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_CAN_GetInterruptMaskStatus( pCAN ) & flag );
+ return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_IsStatusSet */
-/** \brief Test if CAN Interrupt is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_IsStatusSet( AT91PS_CAN pCAN, /* \arg pointer to a CAN controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_IsStatusSet
+//* \brief Test if CAN Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsStatusSet(
+ AT91PS_CAN pCAN, // \arg pointer to a CAN controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_CAN_GetStatus( pCAN ) & flag );
+ return (AT91F_CAN_GetStatus(pCAN) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgModeReg */
-/** \brief Configure the Mode Register of the CAN controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgModeReg( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgModeReg
+//* \brief Configure the Mode Register of the CAN controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgModeReg (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int mode) // mode register
{
- /** Write to the MR register */
- pCAN->CAN_MR = mode;
+ //* Write to the MR register
+ pCAN->CAN_MR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetModeReg */
-/** \brief Return the Mode Register of the CAN controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetModeReg( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetModeReg
+//* \brief Return the Mode Register of the CAN controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetModeReg (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_MR;
+ return pCAN->CAN_MR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgBaudrateReg */
-/** \brief Configure the Baudrate of the CAN controller for the network */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgBaudrateReg( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int baudrate_cfg )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgBaudrateReg
+//* \brief Configure the Baudrate of the CAN controller for the network
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgBaudrateReg (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int baudrate_cfg)
{
- /** Write to the BR register */
- pCAN->CAN_BR = baudrate_cfg;
+ //* Write to the BR register
+ pCAN->CAN_BR = baudrate_cfg;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetBaudrate */
-/** \brief Return the Baudrate of the CAN controller for the network value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetBaudrate( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetBaudrate
+//* \brief Return the Baudrate of the CAN controller for the network value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetBaudrate (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_BR;
+ return pCAN->CAN_BR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetInternalCounter */
-/** \brief Return CAN Timer Regsiter Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetInternalCounter( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetInternalCounter
+//* \brief Return CAN Timer Regsiter Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInternalCounter (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_TIM;
+ return pCAN->CAN_TIM;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetTimestamp */
-/** \brief Return CAN Timestamp Register Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetTimestamp( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetTimestamp
+//* \brief Return CAN Timestamp Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetTimestamp (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_TIMESTP;
+ return pCAN->CAN_TIMESTP;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetErrorCounter */
-/** \brief Return CAN Error Counter Register Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetErrorCounter( AT91PS_CAN pCAN /* pointer to a CAN controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetErrorCounter
+//* \brief Return CAN Error Counter Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetErrorCounter (
+ AT91PS_CAN pCAN // pointer to a CAN controller
+ )
{
- return pCAN->CAN_ECR;
+ return pCAN->CAN_ECR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_InitTransferRequest */
-/** \brief Request for a transfer on the corresponding mailboxes */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_InitTransferRequest( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int transfer_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_InitTransferRequest
+//* \brief Request for a transfer on the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitTransferRequest (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int transfer_cmd)
{
- pCAN->CAN_TCR = transfer_cmd;
+ pCAN->CAN_TCR = transfer_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_InitAbortRequest */
-/** \brief Abort the corresponding mailboxes */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_InitAbortRequest( AT91PS_CAN pCAN, /* pointer to a CAN controller */
- unsigned int abort_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_InitAbortRequest
+//* \brief Abort the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitAbortRequest (
+ AT91PS_CAN pCAN, // pointer to a CAN controller
+ unsigned int abort_cmd)
{
- pCAN->CAN_ACR = abort_cmd;
+ pCAN->CAN_ACR = abort_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageModeReg */
-/** \brief Program the Message Mode Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageModeReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int mode )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageModeReg
+//* \brief Program the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageModeReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int mode)
{
- CAN_Mailbox->CAN_MB_MMR = mode;
+ CAN_Mailbox->CAN_MB_MMR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageModeReg */
-/** \brief Return the Message Mode Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageModeReg( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageModeReg
+//* \brief Return the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageModeReg (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MMR;
+ return CAN_Mailbox->CAN_MB_MMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageIDReg */
-/** \brief Program the Message ID Register */
-/** \brief Version == 0 for Standard messsage, Version == 1 for Extended */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageIDReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int id,
- unsigned char version )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageIDReg
+//* \brief Program the Message ID Register
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageIDReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int id,
+ unsigned char version)
{
- if( version == 0 ) /* IDvA Standard Format */
- {
- CAN_Mailbox->CAN_MB_MID = id << 18;
- }
- else /* IDvB Extended Format */
- {
- CAN_Mailbox->CAN_MB_MID = id | ( 1 << 29 ); /* set MIDE bit */
- }
+ if(version==0) // IDvA Standard Format
+ CAN_Mailbox->CAN_MB_MID = id<<18;
+ else // IDvB Extended Format
+ CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageIDReg */
-/** \brief Return the Message ID Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageIDReg( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageIDReg
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageIDReg (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MID;
+ return CAN_Mailbox->CAN_MB_MID;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageAcceptanceMaskReg */
-/** \brief Program the Message Acceptance Mask Register */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int mask )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg
+//* \brief Program the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int mask)
{
- CAN_Mailbox->CAN_MB_MAM = mask;
+ CAN_Mailbox->CAN_MB_MAM = mask;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageAcceptanceMaskReg */
-/** \brief Return the Message Acceptance Mask Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg
+//* \brief Return the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MAM;
+ return CAN_Mailbox->CAN_MB_MAM;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetFamilyID */
-/** \brief Return the Message ID Register */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetFamilyID( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetFamilyID
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetFamilyID (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MFID;
+ return CAN_Mailbox->CAN_MB_MFID;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageCtrl */
-/** \brief Request and config for a transfer on the corresponding mailbox */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageCtrlReg( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int message_ctrl_cmd )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageCtrl
+//* \brief Request and config for a transfer on the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageCtrlReg (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int message_ctrl_cmd)
{
- CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;
+ CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageStatus */
-/** \brief Return CAN Mailbox Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageStatus( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageStatus
+//* \brief Return CAN Mailbox Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageStatus (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MSR;
+ return CAN_Mailbox->CAN_MB_MSR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageDataLow */
-/** \brief Program data low value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageDataLow( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int data )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageDataLow
+//* \brief Program data low value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataLow (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int data)
{
- CAN_Mailbox->CAN_MB_MDL = data;
+ CAN_Mailbox->CAN_MB_MDL = data;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageDataLow */
-/** \brief Return data low value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageDataLow( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageDataLow
+//* \brief Return data low value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataLow (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MDL;
+ return CAN_Mailbox->CAN_MB_MDL;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgMessageDataHigh */
-/** \brief Program data high value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgMessageDataHigh( AT91PS_CAN_MB CAN_Mailbox, /* pointer to a CAN Mailbox */
- unsigned int data )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgMessageDataHigh
+//* \brief Program data high value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataHigh (
+ AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
+ unsigned int data)
{
- CAN_Mailbox->CAN_MB_MDH = data;
+ CAN_Mailbox->CAN_MB_MDH = data;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_GetMessageDataHigh */
-/** \brief Return data high value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_GetMessageDataHigh( AT91PS_CAN_MB CAN_Mailbox ) /* pointer to a CAN Mailbox */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_GetMessageDataHigh
+//* \brief Return data high value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (
+ AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
{
- return CAN_Mailbox->CAN_MB_MDH;
+ return CAN_Mailbox->CAN_MB_MDH;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_Open */
-/** \brief Open a CAN Port */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_CAN_Open( const unsigned int null ) /* \arg */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_Open
+//* \brief Open a CAN Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_Open (
+ const unsigned int null) // \arg
{
- /* NOT DEFINED AT THIS MOMENT */
- return( 0 );
+ /* NOT DEFINED AT THIS MOMENT */
+ return ( 0 );
+}
+/* *****************************************************************************
+ SOFTWARE API FOR ADC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int flag) // IT to be enabled
+{
+ //* Write to the IER register
+ pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int flag) // IT to be disabled
+{
+ //* Write to the IDR register
+ pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+ AT91PS_ADC pADC) // pointer to a ADC controller
+{
+ return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+ AT91PS_ADC pADC) // pointer to a ADC controller
+{
+ return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int mode) // mode register
+{
+ //* Write to the MR register
+ pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_MR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int mck_clock, // in MHz
+ unsigned int adc_clock, // in MHz
+ unsigned int startup_time, // in us
+ unsigned int sample_and_hold_time) // in ns
+{
+ unsigned int prescal,startup,shtim;
+
+ prescal = mck_clock/(2*adc_clock) - 1;
+ startup = adc_clock*startup_time/8 - 1;
+ shtim = adc_clock*sample_and_hold_time/1000 - 1;
+
+ //* Write to the MR register
+ pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int channel) // mode register
+{
+ //* Write to the CHER register
+ pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int channel) // mode register
+{
+ //* Write to the CHDR register
+ pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CHSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ pADC->ADC_CR = AT91C_ADC_START;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ pADC->ADC_CR = AT91C_ADC_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_LCDR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR1;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR2;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR3;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR5;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR6;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR7;
}
/* *****************************************************************************
-* SOFTWARE API FOR ADC
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_EnableIt */
-/** \brief Enable ADC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_EnableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int flag ) /* IT to be enabled */
+ SOFTWARE API FOR AES
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_EnableIt
+//* \brief Enable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_EnableIt (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pADC->ADC_IER = flag;
+ //* Write to the IER register
+ pAES->AES_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_DisableIt */
-/** \brief Disable ADC interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_DisableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_DisableIt
+//* \brief Disable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_DisableIt (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pADC->ADC_IDR = flag;
+ //* Write to the IDR register
+ pAES->AES_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetStatus */
-/** \brief Return ADC Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetStatus( /* \return ADC Interrupt Status */
- AT91PS_ADC pADC ) /* pointer to a ADC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetStatus
+//* \brief Return AES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
+ AT91PS_AES pAES) // pointer to a AES controller
{
- return pADC->ADC_SR;
+ return pAES->AES_ISR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetInterruptMaskStatus */
-/** \brief Return ADC Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( /* \return ADC Interrupt Mask Status */
- AT91PS_ADC pADC ) /* pointer to a ADC controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetInterruptMaskStatus
+//* \brief Return AES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
+ AT91PS_AES pAES) // pointer to a AES controller
{
- return pADC->ADC_IMR;
+ return pAES->AES_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_IsInterruptMasked */
-/** \brief Test if ADC Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_IsInterruptMasked( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_IsInterruptMasked
+//* \brief Test if AES Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsInterruptMasked(
+ AT91PS_AES pAES, // \arg pointer to a AES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_ADC_GetInterruptMaskStatus( pADC ) & flag );
+ return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_IsStatusSet */
-/** \brief Test if ADC Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_IsStatusSet( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_IsStatusSet
+//* \brief Test if AES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsStatusSet(
+ AT91PS_AES pAES, // \arg pointer to a AES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_ADC_GetStatus( pADC ) & flag );
+ return (AT91F_AES_GetStatus(pAES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgModeReg */
-/** \brief Configure the Mode Register of the ADC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgModeReg( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_CfgModeReg
+//* \brief Configure the Mode Register of the AES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgModeReg (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned int mode) // mode register
{
- /** Write to the MR register */
- pADC->ADC_MR = mode;
+ //* Write to the MR register
+ pAES->AES_MR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetModeReg */
-/** \brief Return the Mode Register of the ADC controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetModeReg( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetModeReg
+//* \brief Return the Mode Register of the AES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetModeReg (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- return pADC->ADC_MR;
+ return pAES->AES_MR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgTimings */
-/** \brief Configure the different necessary timings of the ADC controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgTimings( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int mck_clock, /* in MHz */
- unsigned int adc_clock, /* in MHz */
- unsigned int startup_time, /* in us */
- unsigned int sample_and_hold_time ) /* in ns */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_StartProcessing (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- unsigned int prescal, startup, shtim;
-
- prescal = mck_clock / ( 2 * adc_clock ) - 1;
- startup = adc_clock * startup_time / 8 - 1;
- shtim = adc_clock * sample_and_hold_time / 1000 - 1;
-
- /** Write to the MR register */
- pADC->ADC_MR = ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) & AT91C_ADC_SHTIM );
+ pAES->AES_CR = AT91C_AES_START;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_EnableChannel */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_EnableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int channel ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_SoftReset
+//* \brief Reset AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SoftReset (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- /** Write to the CHER register */
- pADC->ADC_CHER = channel;
+ pAES->AES_CR = AT91C_AES_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_DisableChannel */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_DisableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */
- unsigned int channel ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_LoadNewSeed
+//* \brief Load New Seed in the random number generator
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_LoadNewSeed (
+ AT91PS_AES pAES // pointer to a AES controller
+ )
{
- /** Write to the CHDR register */
- pADC->ADC_CHDR = channel;
+ pAES->AES_CR = AT91C_AES_LOADSEED;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetChannelStatus */
-/** \brief Return ADC Timer Register Value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetChannelStatus( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_SetCryptoKey
+//* \brief Set Cryptographic Key x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetCryptoKey (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- return pADC->ADC_CHSR;
+ pAES->AES_KEYWxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_StartConversion */
-/** \brief Software request for a analog to digital conversion */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_StartConversion( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_InputData (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index,
+ unsigned int indata
+ )
{
- pADC->ADC_CR = AT91C_ADC_START;
+ pAES->AES_IDATAxR[index] = indata;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_SoftReset */
-/** \brief Software reset */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_SoftReset( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetOutputData (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index
+ )
{
- pADC->ADC_CR = AT91C_ADC_SWRST;
+ return pAES->AES_ODATAxR[index];
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetLastConvertedData */
-/** \brief Return the Last Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetLastConvertedData( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_SetInitializationVector
+//* \brief Set Initialization Vector (or Counter) x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetInitializationVector (
+ AT91PS_AES pAES, // pointer to a AES controller
+ unsigned char index,
+ unsigned int initvector
+ )
{
- return pADC->ADC_LCDR;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH0 */
-/** \brief Return the Channel 0 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH0( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR0;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH1 */
-/** \brief Return the Channel 1 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH1( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR1;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH2 */
-/** \brief Return the Channel 2 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH2( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR2;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH3 */
-/** \brief Return the Channel 3 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH3( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR3;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH4 */
-/** \brief Return the Channel 4 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH4( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR4;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH5 */
-/** \brief Return the Channel 5 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH5( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR5;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH6 */
-/** \brief Return the Channel 6 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH6( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR6;
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_GetConvertedDataCH7 */
-/** \brief Return the Channel 7 Converted Data */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_ADC_GetConvertedDataCH7( AT91PS_ADC pADC /* pointer to a ADC controller */
- )
-{
- return pADC->ADC_CDR7;
+ pAES->AES_IVxR[index] = initvector;
}
/* *****************************************************************************
-* SOFTWARE API FOR AES
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_EnableIt */
-/** \brief Enable AES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_EnableIt( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned int flag ) /* IT to be enabled */
+ SOFTWARE API FOR TDES
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_EnableIt
+//* \brief Enable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_EnableIt (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned int flag) // IT to be enabled
{
- /** Write to the IER register */
- pAES->AES_IER = flag;
+ //* Write to the IER register
+ pTDES->TDES_IER = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_DisableIt */
-/** \brief Disable AES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_DisableIt( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_DisableIt
+//* \brief Disable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_DisableIt (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned int flag) // IT to be disabled
{
- /** Write to the IDR register */
- pAES->AES_IDR = flag;
+ //* Write to the IDR register
+ pTDES->TDES_IDR = flag;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetStatus */
-/** \brief Return AES Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetStatus( /* \return AES Interrupt Status */
- AT91PS_AES pAES ) /* pointer to a AES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetStatus
+//* \brief Return TDES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
+ AT91PS_TDES pTDES) // pointer to a TDES controller
{
- return pAES->AES_ISR;
+ return pTDES->TDES_ISR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetInterruptMaskStatus */
-/** \brief Return AES Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetInterruptMaskStatus( /* \return AES Interrupt Mask Status */
- AT91PS_AES pAES ) /* pointer to a AES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetInterruptMaskStatus
+//* \brief Return TDES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
+ AT91PS_TDES pTDES) // pointer to a TDES controller
{
- return pAES->AES_IMR;
+ return pTDES->TDES_IMR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_IsInterruptMasked */
-/** \brief Test if AES Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_IsInterruptMasked( AT91PS_AES pAES, /* \arg pointer to a AES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_IsInterruptMasked
+//* \brief Test if TDES Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsInterruptMasked(
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_AES_GetInterruptMaskStatus( pAES ) & flag );
+ return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_IsStatusSet */
-/** \brief Test if AES Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_IsStatusSet( AT91PS_AES pAES, /* \arg pointer to a AES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_IsStatusSet
+//* \brief Test if TDES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsStatusSet(
+ AT91PS_TDES pTDES, // \arg pointer to a TDES controller
+ unsigned int flag) // \arg flag to be tested
{
- return( AT91F_AES_GetStatus( pAES ) & flag );
+ return (AT91F_TDES_GetStatus(pTDES) & flag);
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_CfgModeReg */
-/** \brief Configure the Mode Register of the AES controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_CfgModeReg( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_CfgModeReg
+//* \brief Configure the Mode Register of the TDES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgModeReg (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned int mode) // mode register
{
- /** Write to the MR register */
- pAES->AES_MR = mode;
+ //* Write to the MR register
+ pTDES->TDES_MR = mode;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetModeReg */
-/** \brief Return the Mode Register of the AES controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetModeReg( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetModeReg
+//* \brief Return the Mode Register of the TDES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetModeReg (
+ AT91PS_TDES pTDES // pointer to a TDES controller
+ )
{
- return pAES->AES_MR;
+ return pTDES->TDES_MR;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_StartProcessing */
-/** \brief Start Encryption or Decryption */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_StartProcessing( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_StartProcessing (
+ AT91PS_TDES pTDES // pointer to a TDES controller
+ )
{
- pAES->AES_CR = AT91C_AES_START;
+ pTDES->TDES_CR = AT91C_TDES_START;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_SoftReset */
-/** \brief Reset AES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_SoftReset( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SoftReset
+//* \brief Reset TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SoftReset (
+ AT91PS_TDES pTDES // pointer to a TDES controller
+ )
{
- pAES->AES_CR = AT91C_AES_SWRST;
+ pTDES->TDES_CR = AT91C_TDES_SWRST;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_LoadNewSeed */
-/** \brief Load New Seed in the random number generator */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_LoadNewSeed( AT91PS_AES pAES /* pointer to a AES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetCryptoKey1
+//* \brief Set Cryptographic Key 1 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey1 (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- pAES->AES_CR = AT91C_AES_LOADSEED;
+ pTDES->TDES_KEY1WxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_SetCryptoKey */
-/** \brief Set Cryptographic Key x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_SetCryptoKey( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetCryptoKey2
+//* \brief Set Cryptographic Key 2 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey2 (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- pAES->AES_KEYWxR[ index ] = keyword;
+ pTDES->TDES_KEY2WxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_InputData */
-/** \brief Set Input Data x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_InputData( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index,
- unsigned int indata )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetCryptoKey3
+//* \brief Set Cryptographic Key 3 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey3 (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int keyword
+ )
{
- pAES->AES_IDATAxR[ index ] = indata;
+ pTDES->TDES_KEY3WxR[index] = keyword;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_GetOutputData */
-/** \brief Get Output Data x */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_AES_GetOutputData( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_InputData (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int indata
+ )
{
- return pAES->AES_ODATAxR[ index ];
+ pTDES->TDES_IDATAxR[index] = indata;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_SetInitializationVector */
-/** \brief Set Initialization Vector (or Counter) x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_SetInitializationVector( AT91PS_AES pAES, /* pointer to a AES controller */
- unsigned char index,
- unsigned int initvector )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetOutputData (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index
+ )
{
- pAES->AES_IVxR[ index ] = initvector;
+ return pTDES->TDES_ODATAxR[index];
}
-/* *****************************************************************************
-* SOFTWARE API FOR TDES
-***************************************************************************** */
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_EnableIt */
-/** \brief Enable TDES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_EnableIt( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned int flag ) /* IT to be enabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_SetInitializationVector
+//* \brief Set Initialization Vector x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetInitializationVector (
+ AT91PS_TDES pTDES, // pointer to a TDES controller
+ unsigned char index,
+ unsigned int initvector
+ )
{
- /** Write to the IER register */
- pTDES->TDES_IER = flag;
+ pTDES->TDES_IVxR[index] = initvector;
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_DisableIt */
-/** \brief Disable TDES interrupt */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_DisableIt( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned int flag ) /* IT to be disabled */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
{
- /** Write to the IDR register */
- pTDES->TDES_IDR = flag;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetStatus */
-/** \brief Return TDES Interrupt Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetStatus( /* \return TDES Interrupt Status */
- AT91PS_TDES pTDES ) /* pointer to a TDES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
{
- return pTDES->TDES_ISR;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA27_DRXD ) |
+ ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetInterruptMaskStatus */
-/** \brief Return TDES Interrupt Mask Status */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( /* \return TDES Interrupt Mask Status */
- AT91PS_TDES pTDES ) /* pointer to a TDES controller */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
{
- return pTDES->TDES_IMR;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_IsInterruptMasked */
-/** \brief Test if TDES Interrupt is Masked */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_IsInterruptMasked( AT91PS_TDES pTDES, /* \arg pointer to a TDES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
{
- return( AT91F_TDES_GetInterruptMaskStatus( pTDES ) & flag );
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB30_PCK2 ) |
+ ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A
+ ((unsigned int) AT91C_PB20_PCK0 ) |
+ ((unsigned int) AT91C_PB0_PCK0 ) |
+ ((unsigned int) AT91C_PB22_PCK2 ) |
+ ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA30_PCK2 ) |
+ ((unsigned int) AT91C_PA13_PCK1 ) |
+ ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_IsStatusSet */
-/** \brief Test if TDES Status is Set */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_IsStatusSet( AT91PS_TDES pTDES, /* \arg pointer to a TDES controller */
- unsigned int flag ) /* \arg flag to be tested */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_CfgPMC
+//* \brief Enable Peripheral clock in PMC for VREG
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_CfgPMC (void)
{
- return( AT91F_TDES_GetStatus( pTDES ) & flag );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_CfgModeReg */
-/** \brief Configure the Mode Register of the TDES controller */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_CfgModeReg( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned int mode ) /* mode register */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for RSTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTC_CfgPMC (void)
{
- /** Write to the MR register */
- pTDES->TDES_MR = mode;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetModeReg */
-/** \brief Return the Mode Register of the TDES controller value */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetModeReg( AT91PS_TDES pTDES /* pointer to a TDES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
{
- return pTDES->TDES_MR;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SSC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_StartProcessing */
-/** \brief Start Encryption or Decryption */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_StartProcessing( AT91PS_TDES pTDES /* pointer to a TDES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
{
- pTDES->TDES_CR = AT91C_TDES_START;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA25_RK ) |
+ ((unsigned int) AT91C_PA22_TK ) |
+ ((unsigned int) AT91C_PA21_TF ) |
+ ((unsigned int) AT91C_PA24_RD ) |
+ ((unsigned int) AT91C_PA26_RF ) |
+ ((unsigned int) AT91C_PA23_TD ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SoftReset */
-/** \brief Reset TDES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SoftReset( AT91PS_TDES pTDES /* pointer to a TDES controller */
- )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for WDTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTC_CfgPMC (void)
{
- pTDES->TDES_CR = AT91C_TDES_SWRST;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetCryptoKey1 */
-/** \brief Set Cryptographic Key 1 Word x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetCryptoKey1( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
{
- pTDES->TDES_KEY1WxR[ index ] = keyword;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_US1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetCryptoKey2 */
-/** \brief Set Cryptographic Key 2 Word x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetCryptoKey2( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
{
- pTDES->TDES_KEY2WxR[ index ] = keyword;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB26_RI1 ) |
+ ((unsigned int) AT91C_PB24_DSR1 ) |
+ ((unsigned int) AT91C_PB23_DCD1 ) |
+ ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA7_SCK1 ) |
+ ((unsigned int) AT91C_PA8_RTS1 ) |
+ ((unsigned int) AT91C_PA6_TXD1 ) |
+ ((unsigned int) AT91C_PA5_RXD1 ) |
+ ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetCryptoKey3 */
-/** \brief Set Cryptographic Key 3 Word x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetCryptoKey3( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int keyword )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
{
- pTDES->TDES_KEY3WxR[ index ] = keyword;
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_US0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_InputData */
-/** \brief Set Input Data x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_InputData( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int indata )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
{
- pTDES->TDES_IDATAxR[ index ] = indata;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA0_RXD0 ) |
+ ((unsigned int) AT91C_PA4_CTS0 ) |
+ ((unsigned int) AT91C_PA3_RTS0 ) |
+ ((unsigned int) AT91C_PA2_SCK0 ) |
+ ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_GetOutputData */
-/** \brief Get Output Data x */
-/**---------------------------------------------------------------------------- */
-__inline unsigned int AT91F_TDES_GetOutputData( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SPI1
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPMC (void)
{
- return pTDES->TDES_ODATAxR[ index ];
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SPI1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_SetInitializationVector */
-/** \brief Set Initialization Vector x */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_SetInitializationVector( AT91PS_TDES pTDES, /* pointer to a TDES controller */
- unsigned char index,
- unsigned int initvector )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI1_CfgPIO
+//* \brief Configure PIO controllers to drive SPI1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPIO (void)
{
- pTDES->TDES_IVxR[ index ] = initvector;
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB16_NPCS13 ) |
+ ((unsigned int) AT91C_PB10_NPCS11 ) |
+ ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA4_NPCS13 ) |
+ ((unsigned int) AT91C_PA29_NPCS13 ) |
+ ((unsigned int) AT91C_PA21_NPCS10 ) |
+ ((unsigned int) AT91C_PA22_SPCK1 ) |
+ ((unsigned int) AT91C_PA25_NPCS11 ) |
+ ((unsigned int) AT91C_PA2_NPCS11 ) |
+ ((unsigned int) AT91C_PA24_MISO1 ) |
+ ((unsigned int) AT91C_PA3_NPCS12 ) |
+ ((unsigned int) AT91C_PA26_NPCS12 ) |
+ ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for DBGU */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SPI0
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SPI0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_DBGU_CfgPIO */
-/** \brief Configure PIO controllers to drive DBGU signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_DBGU_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI0_CfgPIO
+//* \brief Configure PIO controllers to drive SPI0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA27_DRXD ) |
- ( ( unsigned int ) AT91C_PA28_DTXD ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB13_NPCS01 ) |
+ ((unsigned int) AT91C_PB17_NPCS03 ) |
+ ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA16_MISO0 ) |
+ ((unsigned int) AT91C_PA13_NPCS01 ) |
+ ((unsigned int) AT91C_PA15_NPCS03 ) |
+ ((unsigned int) AT91C_PA17_MOSI0 ) |
+ ((unsigned int) AT91C_PA18_SPCK0 ) |
+ ((unsigned int) AT91C_PA14_NPCS02 ) |
+ ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A
+ ((unsigned int) AT91C_PA7_NPCS01 ) |
+ ((unsigned int) AT91C_PA9_NPCS03 ) |
+ ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PMC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PITC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PMC_CfgPIO */
-/** \brief Configure PIO controllers to drive PMC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PMC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB30_PCK2 ) |
- ( ( unsigned int ) AT91C_PB29_PCK1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB20_PCK0 ) |
- ( ( unsigned int ) AT91C_PB0_PCK0 ) |
- ( ( unsigned int ) AT91C_PB22_PCK2 ) |
- ( ( unsigned int ) AT91C_PB21_PCK1 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA30_PCK2 ) |
- ( ( unsigned int ) AT91C_PA13_PCK1 ) |
- ( ( unsigned int ) AT91C_PA27_PCK3 ) ); /* Peripheral B */
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_FIQ) |
+ ((unsigned int) 1 << AT91C_ID_IRQ0) |
+ ((unsigned int) 1 << AT91C_ID_IRQ1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_VREG_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for VREG */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_VREG_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA30_IRQ0 ) |
+ ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A
+ ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RSTC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for RSTC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RSTC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_AES));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SSC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SSC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TWI));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SSC_CfgPIO */
-/** \brief Configure PIO controllers to drive SSC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SSC_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA25_RK ) |
- ( ( unsigned int ) AT91C_PA22_TK ) |
- ( ( unsigned int ) AT91C_PA21_TF ) |
- ( ( unsigned int ) AT91C_PA24_RD ) |
- ( ( unsigned int ) AT91C_PA26_RF ) |
- ( ( unsigned int ) AT91C_PA23_TD ), /* Peripheral A */
- 0 ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_WDTC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for WDTC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_WDTC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for US1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US1_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_US1 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US1_CfgPIO */
-/** \brief Configure PIO controllers to drive US1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US1_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB26_RI1 ) |
- ( ( unsigned int ) AT91C_PB24_DSR1 ) |
- ( ( unsigned int ) AT91C_PB23_DCD1 ) |
- ( ( unsigned int ) AT91C_PB25_DTR1 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA7_SCK1 ) |
- ( ( unsigned int ) AT91C_PA8_RTS1 ) |
- ( ( unsigned int ) AT91C_PA6_TXD1 ) |
- ( ( unsigned int ) AT91C_PA5_RXD1 ) |
- ( ( unsigned int ) AT91C_PA9_CTS1 ), /* Peripheral A */
- 0 ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for US0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US0_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_US0 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_US0_CfgPIO */
-/** \brief Configure PIO controllers to drive US0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_US0_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA0_RXD0 ) |
- ( ( unsigned int ) AT91C_PA4_CTS0 ) |
- ( ( unsigned int ) AT91C_PA3_RTS0 ) |
- ( ( unsigned int ) AT91C_PA2_SCK0 ) |
- ( ( unsigned int ) AT91C_PA1_TXD0 ), /* Peripheral A */
- 0 ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SPI1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI1_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SPI1 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI1_CfgPIO */
-/** \brief Configure PIO controllers to drive SPI1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI1_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB16_NPCS13 ) |
- ( ( unsigned int ) AT91C_PB10_NPCS11 ) |
- ( ( unsigned int ) AT91C_PB11_NPCS12 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA4_NPCS13 ) |
- ( ( unsigned int ) AT91C_PA29_NPCS13 ) |
- ( ( unsigned int ) AT91C_PA21_NPCS10 ) |
- ( ( unsigned int ) AT91C_PA22_SPCK1 ) |
- ( ( unsigned int ) AT91C_PA25_NPCS11 ) |
- ( ( unsigned int ) AT91C_PA2_NPCS11 ) |
- ( ( unsigned int ) AT91C_PA24_MISO1 ) |
- ( ( unsigned int ) AT91C_PA3_NPCS12 ) |
- ( ( unsigned int ) AT91C_PA26_NPCS12 ) |
- ( ( unsigned int ) AT91C_PA23_MOSI1 ) ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for SPI0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI0_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SPI0 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_SPI0_CfgPIO */
-/** \brief Configure PIO controllers to drive SPI0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_SPI0_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB13_NPCS01 ) |
- ( ( unsigned int ) AT91C_PB17_NPCS03 ) |
- ( ( unsigned int ) AT91C_PB14_NPCS02 ) ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA16_MISO0 ) |
- ( ( unsigned int ) AT91C_PA13_NPCS01 ) |
- ( ( unsigned int ) AT91C_PA15_NPCS03 ) |
- ( ( unsigned int ) AT91C_PA17_MOSI0 ) |
- ( ( unsigned int ) AT91C_PA18_SPCK0 ) |
- ( ( unsigned int ) AT91C_PA14_NPCS02 ) |
- ( ( unsigned int ) AT91C_PA12_NPCS00 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA7_NPCS01 ) |
- ( ( unsigned int ) AT91C_PA9_NPCS03 ) |
- ( ( unsigned int ) AT91C_PA8_NPCS02 ) ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PITC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PITC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PITC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for AIC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_FIQ ) |
- ( ( unsigned int ) 1 << AT91C_ID_IRQ0 ) |
- ( ( unsigned int ) 1 << AT91C_ID_IRQ1 ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AIC_CfgPIO */
-/** \brief Configure PIO controllers to drive AIC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AIC_CfgPIO( void )
-{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA30_IRQ0 ) |
- ( ( unsigned int ) AT91C_PA29_FIQ ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PA14_IRQ1 ) ); /* Peripheral B */
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_AES_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for AES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_AES_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_AES ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TWI */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TWI ) );
-}
-
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TWI_CfgPIO */
-/** \brief Configure PIO controllers to drive TWI signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TWI_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA11_TWCK ) |
- ( ( unsigned int ) AT91C_PA10_TWD ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA11_TWCK ) |
+ ((unsigned int) AT91C_PA10_TWD ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for ADC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_ADC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_ADC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_ADC_CfgPIO */
-/** \brief Configure PIO controllers to drive ADC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_ADC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PB18_ADTRG ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH3_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH3 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH3_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB22_PWM3 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB30_PWM3 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A
+ ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH2_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH2 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH2_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB21_PWM2 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB29_PWM2 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A
+ ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH1_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH1_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB20_PWM1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB28_PWM1 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A
+ ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CH0_CfgPIO */
-/** \brief Configure PIO controllers to drive PWMC_CH0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CH0_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB19_PWM0 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB27_PWM0 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A
+ ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_RTTC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for RTTC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_RTTC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RTTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for RTTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RTTC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_UDP_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for UDP */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_UDP_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_UDP ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_UDP));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TDES_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TDES */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TDES_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TDES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TDES ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TDES));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_EMAC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for EMAC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_EMAC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_EMAC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for EMAC
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_EMAC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_EMAC));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_EMAC_CfgPIO */
-/** \brief Configure PIO controllers to drive EMAC signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_EMAC_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_EMAC_CfgPIO
+//* \brief Configure PIO controllers to drive EMAC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB2_ETX0 ) |
- ( ( unsigned int ) AT91C_PB12_ETXER ) |
- ( ( unsigned int ) AT91C_PB16_ECOL ) |
- ( ( unsigned int ) AT91C_PB11_ETX3 ) |
- ( ( unsigned int ) AT91C_PB6_ERX1 ) |
- ( ( unsigned int ) AT91C_PB15_ERXDV ) |
- ( ( unsigned int ) AT91C_PB13_ERX2 ) |
- ( ( unsigned int ) AT91C_PB3_ETX1 ) |
- ( ( unsigned int ) AT91C_PB8_EMDC ) |
- ( ( unsigned int ) AT91C_PB5_ERX0 ) |
- /*((unsigned int) AT91C_PB18_EF100 ) | */
- ( ( unsigned int ) AT91C_PB14_ERX3 ) |
- ( ( unsigned int ) AT91C_PB4_ECRS_ECRSDV ) |
- ( ( unsigned int ) AT91C_PB1_ETXEN ) |
- ( ( unsigned int ) AT91C_PB10_ETX2 ) |
- ( ( unsigned int ) AT91C_PB0_ETXCK_EREFCK ) |
- ( ( unsigned int ) AT91C_PB9_EMDIO ) |
- ( ( unsigned int ) AT91C_PB7_ERXER ) |
- ( ( unsigned int ) AT91C_PB17_ERXCK ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB2_ETX0 ) |
+ ((unsigned int) AT91C_PB12_ETXER ) |
+ ((unsigned int) AT91C_PB16_ECOL ) |
+ ((unsigned int) AT91C_PB11_ETX3 ) |
+ ((unsigned int) AT91C_PB6_ERX1 ) |
+ ((unsigned int) AT91C_PB15_ERXDV ) |
+ ((unsigned int) AT91C_PB13_ERX2 ) |
+ ((unsigned int) AT91C_PB3_ETX1 ) |
+ ((unsigned int) AT91C_PB8_EMDC ) |
+ ((unsigned int) AT91C_PB5_ERX0 ) |
+ //((unsigned int) AT91C_PB18_EF100 ) |
+ ((unsigned int) AT91C_PB14_ERX3 ) |
+ ((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
+ ((unsigned int) AT91C_PB1_ETXEN ) |
+ ((unsigned int) AT91C_PB10_ETX2 ) |
+ ((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
+ ((unsigned int) AT91C_PB9_EMDIO ) |
+ ((unsigned int) AT91C_PB7_ERXER ) |
+ ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC0_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC0 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC0_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC0 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC0));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC0_CfgPIO */
-/** \brief Configure PIO controllers to drive TC0 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC0_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB23_TIOA0 ) |
- ( ( unsigned int ) AT91C_PB24_TIOB0 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB12_TCLK0 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB23_TIOA0 ) |
+ ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A
+ ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC1_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC1 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC1_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC1 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC1));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC1_CfgPIO */
-/** \brief Configure PIO controllers to drive TC1 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC1_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB25_TIOA1 ) |
- ( ( unsigned int ) AT91C_PB26_TIOB1 ), /* Peripheral A */
- ( ( unsigned int ) AT91C_PB19_TCLK1 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB25_TIOA1 ) |
+ ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A
+ ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC2_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for TC2 */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC2_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_TC2 ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC2));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_TC2_CfgPIO */
-/** \brief Configure PIO controllers to drive TC2 signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_TC2_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PB28_TIOB2 ) |
- ( ( unsigned int ) AT91C_PB27_TIOA2 ), /* Peripheral A */
- 0 ); /* Peripheral B */
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- 0, /* Peripheral A */
- ( ( unsigned int ) AT91C_PA15_TCLK2 ) ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ ((unsigned int) AT91C_PB28_TIOB2 ) |
+ ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A
+ 0); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_MC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for MC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_MC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIOA_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PIOA */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIOA_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PIOA ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PIOA));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PIOB_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PIOB */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PIOB_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIOB_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PIOB
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOB_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PIOB ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PIOB));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for CAN */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgPMC
+//* \brief Enable Peripheral clock in PMC for CAN
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_CAN ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_CAN));
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_CAN_CfgPIO */
-/** \brief Configure PIO controllers to drive CAN signals */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_CAN_CfgPIO( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CAN_CfgPIO
+//* \brief Configure PIO controllers to drive CAN signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPIO (void)
{
- /* Configure PIO controllers to periph mode */
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, /* PIO controller base address */
- ( ( unsigned int ) AT91C_PA20_CANTX ) |
- ( ( unsigned int ) AT91C_PA19_CANRX ), /* Peripheral A */
- 0 ); /* Peripheral B */
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA20_CANTX ) |
+ ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A
+ 0); // Peripheral B
}
-/**---------------------------------------------------------------------------- */
-/** \fn AT91F_PWMC_CfgPMC */
-/** \brief Enable Peripheral clock in PMC for PWMC */
-/**---------------------------------------------------------------------------- */
-__inline void AT91F_PWMC_CfgPMC( void )
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, /* PIO controller base address */
- ( ( unsigned int ) 1 << AT91C_ID_PWMC ) );
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PWMC));
}
#endif // lib_AT91SAM7X256_H
diff --git a/portable/IAR/AtmelSAM7S64/port.c b/portable/IAR/AtmelSAM7S64/port.c
index 0ad6ba7..1dbf34c 100644
--- a/portable/IAR/AtmelSAM7S64/port.c
+++ b/portable/IAR/AtmelSAM7S64/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Atmel ARM7 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Atmel ARM7 port.
+ *----------------------------------------------------------*/
/* Standard includes. */
@@ -38,29 +38,29 @@
#include "task.h"
/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
/* Constants required to setup the PIT. */
-#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )
-#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-#define portINT_LEVEL_SENSITIVE 0
-#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
+#define portINT_LEVEL_SENSITIVE 0
+#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
/*-----------------------------------------------------------*/
/* Setup the PIT to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
- * cannot be initialised to 0 as this will cause interrupts to be enabled
- * during the kernel initialisation process. */
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
uint32_t ulCriticalNesting = ( uint32_t ) 9999;
/*-----------------------------------------------------------*/
@@ -71,181 +71,189 @@
*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The status register is set for system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* The status register is set for system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+
+ pxTopOfStack--;
- if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ /* Interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
-
- /* Interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortStartFirstTask();
+ /* Start the first task. */
+ vPortStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 0
-/* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick. */
- static __arm __irq void vPortNonPreemptiveTick( void );
- static __arm __irq void vPortNonPreemptiveTick( void )
- {
- uint32_t ulDummy;
+ /* The cooperative scheduler requires a normal IRQ service routine to
+ simply increment the system tick. */
+ static __arm __irq void vPortNonPreemptiveTick( void );
+ static __arm __irq void vPortNonPreemptiveTick( void )
+ {
+ uint32_t ulDummy;
+
+ /* Increment the tick count - which may wake some tasks but as the
+ preemptive scheduler is not being used any woken task is not given
+ processor time no matter what its priority. */
+ xTaskIncrementTick();
+
+ /* Clear the PIT interrupt. */
+ ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+
+ /* End the interrupt in the AIC. */
+ AT91C_BASE_AIC->AIC_EOICR = ulDummy;
+ }
- /* Increment the tick count - which may wake some tasks but as the
- * preemptive scheduler is not being used any woken task is not given
- * processor time no matter what its priority. */
- xTaskIncrementTick();
+#else
- /* Clear the PIT interrupt. */
- ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+ /* Currently the IAR port requires the preemptive tick function to be
+ defined in an asm file. */
- /* End the interrupt in the AIC. */
- AT91C_BASE_AIC->AIC_EOICR = ulDummy;
- }
-
-#else /* if configUSE_PREEMPTION == 0 */
-
-/* Currently the IAR port requires the preemptive tick function to be
- * defined in an asm file. */
-
-#endif /* if configUSE_PREEMPTION == 0 */
+#endif
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- AT91PS_PITC pxPIT = AT91C_BASE_PITC;
+AT91PS_PITC pxPIT = AT91C_BASE_PITC;
- /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
- * on whether the preemptive or cooperative scheduler is being used. */
- #if configUSE_PREEMPTION == 0
- AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPortNonPreemptiveTick );
- #else
- extern void( vPortPreemptiveTick )( void );
- AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPortPreemptiveTick );
- #endif
+ /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
+ on whether the preemptive or cooperative scheduler is being used. */
+ #if configUSE_PREEMPTION == 0
- /* Configure the PIT period. */
- pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
+ AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick );
- /* Enable the interrupt. Global interrupts are disables at this point so
- * this is safe. */
- AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
+ #else
+
+ extern void ( vPortPreemptiveTick )( void );
+ AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick );
+
+ #endif
+
+ /* Configure the PIT period. */
+ pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
+
+ /* Enable the interrupt. Global interrupts are disables at this point so
+ this is safe. */
+ AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- /* Disable interrupts first! */
- __disable_interrupt();
+ /* Disable interrupts first! */
+ __disable_interrupt();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- __enable_interrupt();
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ __enable_interrupt();
+ }
+ }
}
/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/portable/IAR/AtmelSAM7S64/portmacro.h b/portable/IAR/AtmelSAM7S64/portmacro.h
index f40f457..86cb211 100644
--- a/portable/IAR/AtmelSAM7S64/portmacro.h
+++ b/portable/IAR/AtmelSAM7S64/portmacro.h
@@ -27,11 +27,11 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,66 +44,68 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portYIELD() asm ( "SWI 0" )
- #define portNOP() asm ( "NOP" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portYIELD() asm ( "SWI 0" )
+#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
- __arm __interwork void vPortDisableInterruptsFromThumb( void );
- __arm __interwork void vPortEnableInterruptsFromThumb( void );
- __arm __interwork void vPortEnterCritical( void );
- __arm __interwork void vPortExitCritical( void );
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() __disable_interrupt()
- #define portENABLE_INTERRUPTS() __enable_interrupt()
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() __disable_interrupt()
+#define portENABLE_INTERRUPTS() __enable_interrupt()
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern void vTaskSwitchContext( void ); \
- \
- if( xSwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+{ \
+extern void vTaskSwitchContext( void ); \
+ \
+ if( xSwitchRequired ) \
+ { \
+ vTaskSwitchContext(); \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
+
diff --git a/portable/IAR/AtmelSAM9XE/ISR_Support.h b/portable/IAR/AtmelSAM9XE/ISR_Support.h
index 338d052..4a32f39 100644
--- a/portable/IAR/AtmelSAM9XE/ISR_Support.h
+++ b/portable/IAR/AtmelSAM9XE/ISR_Support.h
@@ -1,96 +1,78 @@
-EXTERN pxCurrentTCB
-EXTERN ulCriticalNesting
+ EXTERN pxCurrentTCB
+ EXTERN ulCriticalNesting
-;
-Context save and restore macro definitions
-;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
-;
-Push R0 as we are going to use the register.
- STMDB SP !, { R0 }
+ ; Push R0 as we are going to use the register.
+ STMDB SP!, {R0}
-;
-Set R0 to point to the task stack pointer.
- STMDB SP, { SP } ^
-NOP
-SUB SP, SP, # 4
-LDMIA SP !, { R0 }
+ ; Set R0 to point to the task stack pointer.
+ STMDB SP, {SP}^
+ NOP
+ SUB SP, SP, #4
+ LDMIA SP!, {R0}
-;
-Push the return address onto the stack.
- STMDB R0 !, { LR }
+ ; Push the return address onto the stack.
+ STMDB R0!, {LR}
-;
+ ; Now we have saved LR we can use it instead of R0.
+ MOV LR, R0
-Now we have saved LR we can use it instead of R0.
- MOV LR, R0
+ ; Pop R0 so we can save it onto the system mode stack.
+ LDMIA SP!, {R0}
-;
-Pop R0 so we can save it onto the system mode stack.
- LDMIA SP !, { R0 }
+ ; Push all the system mode registers onto the task stack.
+ STMDB LR, {R0-LR}^
+ NOP
+ SUB LR, LR, #60
-;
-Push all the system mode registers onto the task stack.
- STMDB LR, { R0 - LR } ^
-NOP
-SUB LR, LR, # 60
+ ; Push the SPSR onto the task stack.
+ MRS R0, SPSR
+ STMDB LR!, {R0}
-;
-Push the SPSR onto the task stack.
- MRS R0, SPSR
-STMDB LR !, { R0 }
+ LDR R0, =ulCriticalNesting
+ LDR R0, [R0]
+ STMDB LR!, {R0}
-LDR R0, = ulCriticalNesting
- LDR R0, [ R0 ]
-STMDB LR !, { R0 }
+ ; Store the new top of stack for the task.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ STR LR, [R0]
-;
-Store the new top of stack for the task.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-STR LR, [ R0 ]
-
-ENDM
+ ENDM
portRESTORE_CONTEXT MACRO
-;
-Set the LR to the task stack.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-LDR LR, [ R0 ]
+ ; Set the LR to the task stack.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ LDR LR, [R0]
-;
-The critical nesting depth is the first item on the stack.
- ;
-Load it into the ulCriticalNesting variable.
- LDR R0, = ulCriticalNesting
- LDMFD LR !, { R1 }
-STR R1, [ R0 ]
+ ; The critical nesting depth is the first item on the stack.
+ ; Load it into the ulCriticalNesting variable.
+ LDR R0, =ulCriticalNesting
+ LDMFD LR!, {R1}
+ STR R1, [R0]
-;
-Get the SPSR from the stack.
- LDMFD LR !, { R0 }
-MSR SPSR_cxsf, R0
+ ; Get the SPSR from the stack.
+ LDMFD LR!, {R0}
+ MSR SPSR_cxsf, R0
-;
-Restore all system mode registers for the task.
- LDMFD LR, { R0 - R14 } ^
-NOP
+ ; Restore all system mode registers for the task.
+ LDMFD LR, {R0-R14}^
+ NOP
-;
-Restore the return address.
- LDR LR, [ LR, # + 60 ]
+ ; Restore the return address.
+ LDR LR, [LR, #+60]
-;
+ ; And return - correcting the offset in the LR to obtain the
+ ; correct address.
+ SUBS PC, LR, #4
-And return -correcting the offset in the LR to obtain the
-;
+ ENDM
-correct address.
- SUBS PC, LR, # 4
-
-ENDM
diff --git a/portable/IAR/AtmelSAM9XE/port.c b/portable/IAR/AtmelSAM9XE/port.c
index f96e576..b65a07c 100644
--- a/portable/IAR/AtmelSAM9XE/port.c
+++ b/portable/IAR/AtmelSAM9XE/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Atmel ARM7 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Atmel ARM7 port.
+ *----------------------------------------------------------*/
/* Standard includes. */
@@ -50,21 +50,21 @@
/*-----------------------------------------------------------*/
/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
/* Constants required to setup the PIT. */
-#define port1MHz_IN_Hz ( 1000000ul )
-#define port1SECOND_IN_uS ( 1000000.0 )
+#define port1MHz_IN_Hz ( 1000000ul )
+#define port1SECOND_IN_uS ( 1000000.0 )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-#define portINT_LEVEL_SENSITIVE 0
-#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
+#define portINT_LEVEL_SENSITIVE 0
+#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
/*-----------------------------------------------------------*/
/* Setup the PIT to generate the tick interrupts. */
@@ -74,8 +74,8 @@
static void vPortTickISR( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
- * cannot be initialised to 0 as this will cause interrupts to be enabled
- * during the kernel initialisation process. */
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
uint32_t ulCriticalNesting = ( uint32_t ) 9999;
/*-----------------------------------------------------------*/
@@ -86,167 +86,171 @@
*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The status register is set for system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* The status register is set for system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ #ifdef THUMB_INTERWORK
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+ #endif
+
+ pxTopOfStack--;
- #ifdef THUMB_INTERWORK
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
- #endif
+ /* Interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
-
- /* Interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortStartFirstTask();
+ /* Start the first task. */
+ vPortStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
static __arm void vPortTickISR( void )
{
- volatile uint32_t ulDummy;
-
- /* Increment the tick count - which may wake some tasks but as the
- * preemptive scheduler is not being used any woken task is not given
- * processor time no matter what its priority. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Clear the PIT interrupt. */
- ulDummy = AT91C_BASE_PITC->PITC_PIVR;
-
- /* To remove compiler warning. */
- ( void ) ulDummy;
-
- /* The AIC is cleared in the asm wrapper, outside of this function. */
+volatile uint32_t ulDummy;
+
+ /* Increment the tick count - which may wake some tasks but as the
+ preemptive scheduler is not being used any woken task is not given
+ processor time no matter what its priority. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ /* Clear the PIT interrupt. */
+ ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+
+ /* To remove compiler warning. */
+ ( void ) ulDummy;
+
+ /* The AIC is cleared in the asm wrapper, outside of this function. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS;
+const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS;
- /* Setup the PIT for the required frequency. */
- PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz );
-
- /* Setup the PIT interrupt. */
- AIC_DisableIT( AT91C_ID_SYS );
- AIC_ConfigureIT( AT91C_ID_SYS, AT91C_AIC_PRIOR_LOWEST, vPortTickISR );
- AIC_EnableIT( AT91C_ID_SYS );
- PIT_EnableIT();
+ /* Setup the PIT for the required frequency. */
+ PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz );
+
+ /* Setup the PIT interrupt. */
+ AIC_DisableIT( AT91C_ID_SYS );
+ AIC_ConfigureIT( AT91C_ID_SYS, AT91C_AIC_PRIOR_LOWEST, vPortTickISR );
+ AIC_EnableIT( AT91C_ID_SYS );
+ PIT_EnableIT();
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- /* Disable interrupts first! */
- __disable_irq();
+ /* Disable interrupts first! */
+ __disable_irq();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- __enable_irq();
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ __enable_irq();
+ }
+ }
}
/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/portable/IAR/AtmelSAM9XE/portmacro.h b/portable/IAR/AtmelSAM9XE/portmacro.h
index c659756..a721c9f 100644
--- a/portable/IAR/AtmelSAM9XE/portmacro.h
+++ b/portable/IAR/AtmelSAM9XE/portmacro.h
@@ -27,13 +27,13 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include <intrinsics.h>
+#include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -46,67 +46,69 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portYIELD() asm ( "SWI 0" )
- #define portNOP() asm ( "NOP" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portYIELD() asm ( "SWI 0" )
+#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
- __arm __interwork void vPortDisableInterruptsFromThumb( void );
- __arm __interwork void vPortEnableInterruptsFromThumb( void );
- __arm __interwork void vPortEnterCritical( void );
- __arm __interwork void vPortExitCritical( void );
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() __disable_irq()
- #define portENABLE_INTERRUPTS() __enable_irq()
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() __disable_irq()
+#define portENABLE_INTERRUPTS() __enable_irq()
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern void vTaskSwitchContext( void ); \
- \
- if( xSwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+{ \
+extern void vTaskSwitchContext( void ); \
+ \
+ if( xSwitchRequired ) \
+ { \
+ vTaskSwitchContext(); \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
+
diff --git a/portable/IAR/LPC2000/ISR_Support.h b/portable/IAR/LPC2000/ISR_Support.h
index 72f4b15..360fff6 100644
--- a/portable/IAR/LPC2000/ISR_Support.h
+++ b/portable/IAR/LPC2000/ISR_Support.h
@@ -1,123 +1,105 @@
-; /*
- * ; * FreeRTOS Kernel V10.3.1
- * ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * ; *
- * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * ; * this software and associated documentation files (the "Software"), to deal in
- * ; * the Software without restriction, including without limitation the rights to
- * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * ; * the Software, and to permit persons to whom the Software is furnished to do so,
- * ; * subject to the following conditions:
- * ; *
- * ; * The above copyright notice and this permission notice shall be included in all
- * ; * copies or substantial portions of the Software.
- * ; *
- * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * ; *
- * ; * http://www.FreeRTOS.org
- * ; * http://aws.amazon.com/freertos
- * ; *
- * ; * 1 tab == 4 spaces!
- * ; */
+;/*
+; * FreeRTOS Kernel V10.3.1
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
-EXTERN pxCurrentTCB
-EXTERN ulCriticalNesting
+ EXTERN pxCurrentTCB
+ EXTERN ulCriticalNesting
-;
-Context save and restore macro definitions
-;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
-;
-Push R0 as we are going to use the register.
- STMDB SP !, { R0 }
+ ; Push R0 as we are going to use the register.
+ STMDB SP!, {R0}
-;
-Set R0 to point to the task stack pointer.
- STMDB SP, { SP } ^
-NOP
-SUB SP, SP, # 4
-LDMIA SP !, { R0 }
+ ; Set R0 to point to the task stack pointer.
+ STMDB SP, {SP}^
+ NOP
+ SUB SP, SP, #4
+ LDMIA SP!, {R0}
-;
-Push the return address onto the stack.
- STMDB R0 !, { LR }
+ ; Push the return address onto the stack.
+ STMDB R0!, {LR}
-;
+ ; Now we have saved LR we can use it instead of R0.
+ MOV LR, R0
-Now we have saved LR we can use it instead of R0.
- MOV LR, R0
+ ; Pop R0 so we can save it onto the system mode stack.
+ LDMIA SP!, {R0}
-;
-Pop R0 so we can save it onto the system mode stack.
- LDMIA SP !, { R0 }
+ ; Push all the system mode registers onto the task stack.
+ STMDB LR, {R0-LR}^
+ NOP
+ SUB LR, LR, #60
-;
-Push all the system mode registers onto the task stack.
- STMDB LR, { R0 - LR } ^
-NOP
-SUB LR, LR, # 60
+ ; Push the SPSR onto the task stack.
+ MRS R0, SPSR
+ STMDB LR!, {R0}
-;
-Push the SPSR onto the task stack.
- MRS R0, SPSR
-STMDB LR !, { R0 }
+ LDR R0, =ulCriticalNesting
+ LDR R0, [R0]
+ STMDB LR!, {R0}
-LDR R0, = ulCriticalNesting
- LDR R0, [ R0 ]
-STMDB LR !, { R0 }
+ ; Store the new top of stack for the task.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ STR LR, [R0]
-;
-Store the new top of stack for the task.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-STR LR, [ R0 ]
-
-ENDM
+ ENDM
portRESTORE_CONTEXT MACRO
-;
-Set the LR to the task stack.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-LDR LR, [ R0 ]
+ ; Set the LR to the task stack.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ LDR LR, [R0]
-;
-The critical nesting depth is the first item on the stack.
- ;
-Load it into the ulCriticalNesting variable.
- LDR R0, = ulCriticalNesting
- LDMFD LR !, { R1 }
-STR R1, [ R0 ]
+ ; The critical nesting depth is the first item on the stack.
+ ; Load it into the ulCriticalNesting variable.
+ LDR R0, =ulCriticalNesting
+ LDMFD LR!, {R1}
+ STR R1, [R0]
-;
-Get the SPSR from the stack.
- LDMFD LR !, { R0 }
-MSR SPSR_cxsf, R0
+ ; Get the SPSR from the stack.
+ LDMFD LR!, {R0}
+ MSR SPSR_cxsf, R0
-;
-Restore all system mode registers for the task.
- LDMFD LR, { R0 - R14 } ^
-NOP
+ ; Restore all system mode registers for the task.
+ LDMFD LR, {R0-R14}^
+ NOP
-;
-Restore the return address.
- LDR LR, [ LR, # + 60 ]
+ ; Restore the return address.
+ LDR LR, [LR, #+60]
-;
+ ; And return - correcting the offset in the LR to obtain the
+ ; correct address.
+ SUBS PC, LR, #4
-And return -correcting the offset in the LR to obtain the
-;
+ ENDM
-correct address.
- SUBS PC, LR, # 4
-
-ENDM
diff --git a/portable/IAR/LPC2000/port.c b/portable/IAR/LPC2000/port.c
index 7682626..1385ec0 100644
--- a/portable/IAR/LPC2000/port.c
+++ b/portable/IAR/LPC2000/port.c
@@ -26,16 +26,16 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Philips ARM7 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Philips ARM7 port.
+ *----------------------------------------------------------*/
/*
- * Changes from V3.2.2
- *
- + Bug fix - The prescale value for the timer setup is now written to T0PR
- + instead of T0PC. This bug would have had no effect unless a prescale
- + value was actually used.
- */
+ Changes from V3.2.2
+
+ + Bug fix - The prescale value for the timer setup is now written to T0PR
+ instead of T0PC. This bug would have had no effect unless a prescale
+ value was actually used.
+*/
/* Standard includes. */
#include <stdlib.h>
@@ -46,36 +46,36 @@
#include "task.h"
/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE 0x00
-#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
+#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE 0x00
+#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
/* Constants required to setup the PIT. */
-#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )
-#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-#define portINT_LEVEL_SENSITIVE 0
-#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
+#define portINT_LEVEL_SENSITIVE 0
+#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
/* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
+#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
/*-----------------------------------------------------------*/
@@ -83,8 +83,8 @@
static void prvSetupTimerInterrupt( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
- * cannot be initialised to 0 as this will cause interrupts to be enabled
- * during the kernel initialisation process. */
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
uint32_t ulCriticalNesting = ( uint32_t ) 9999;
/*-----------------------------------------------------------*/
@@ -95,219 +95,223 @@
*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The status register is set for system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* The status register is set for system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+
+ pxTopOfStack--;
- if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ /* Interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
-
- /* Interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortStartFirstTask();
+ /* Start the first task. */
+ vPortStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 0
-/* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick. */
- static __arm __irq void vPortNonPreemptiveTick( void );
- static __arm __irq void vPortNonPreemptiveTick( void )
- {
- /* Increment the tick count - which may wake some tasks but as the
- * preemptive scheduler is not being used any woken task is not given
- * processor time no matter what its priority. */
- xTaskIncrementTick();
+ /* The cooperative scheduler requires a normal IRQ service routine to
+ simply increment the system tick. */
+ static __arm __irq void vPortNonPreemptiveTick( void );
+ static __arm __irq void vPortNonPreemptiveTick( void )
+ {
+ /* Increment the tick count - which may wake some tasks but as the
+ preemptive scheduler is not being used any woken task is not given
+ processor time no matter what its priority. */
+ xTaskIncrementTick();
+
+ /* Ready for the next interrupt. */
+ T0IR = portTIMER_MATCH_ISR_BIT;
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;
+ }
- /* Ready for the next interrupt. */
- T0IR = portTIMER_MATCH_ISR_BIT;
- VICVectAddr = portCLEAR_VIC_INTERRUPT;
- }
+#else
-#else /* if configUSE_PREEMPTION == 0 */
+ /* This function is called from an asm wrapper, so does not require the __irq
+ keyword. */
+ void vPortPreemptiveTick( void );
+ void vPortPreemptiveTick( void )
+ {
+ /* Increment the tick counter. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* The new tick value might unblock a task. Ensure the highest task that
+ is ready to execute is the task that will execute when the tick ISR
+ exits. */
+ vTaskSwitchContext();
+ }
+
+ /* Ready for the next interrupt. */
+ T0IR = portTIMER_MATCH_ISR_BIT;
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;
+ }
-/* This function is called from an asm wrapper, so does not require the __irq
- * keyword. */
- void vPortPreemptiveTick( void );
- void vPortPreemptiveTick( void )
- {
- /* Increment the tick counter. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* The new tick value might unblock a task. Ensure the highest task that
- * is ready to execute is the task that will execute when the tick ISR
- * exits. */
- vTaskSwitchContext();
- }
-
- /* Ready for the next interrupt. */
- T0IR = portTIMER_MATCH_ISR_BIT;
- VICVectAddr = portCLEAR_VIC_INTERRUPT;
- }
-
-#endif /* if configUSE_PREEMPTION == 0 */
+#endif
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- uint32_t ulCompareMatch;
+uint32_t ulCompareMatch;
- /* A 1ms tick does not require the use of the timer prescale. This is
- * defaulted to zero but can be used if necessary. */
- T0PR = portPRESCALE_VALUE;
+ /* A 1ms tick does not require the use of the timer prescale. This is
+ defaulted to zero but can be used if necessary. */
+ T0PR = portPRESCALE_VALUE;
- /* Calculate the match value required for our wanted tick rate. */
- ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+ /* Calculate the match value required for our wanted tick rate. */
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
- /* Protect against divide by zero. Using an if() statement still results
- * in a warning - hence the #if. */
- #if portPRESCALE_VALUE != 0
- {
- ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
- }
- #endif
+ /* Protect against divide by zero. Using an if() statement still results
+ in a warning - hence the #if. */
+ #if portPRESCALE_VALUE != 0
+ {
+ ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+ }
+ #endif
- T0MR0 = ulCompareMatch;
+ T0MR0 = ulCompareMatch;
- /* Generate tick with timer 0 compare match. */
- T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+ /* Generate tick with timer 0 compare match. */
+ T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
- /* Setup the VIC for the timer. */
- VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
- VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+ /* Setup the VIC for the timer. */
+ VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+ VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+
+ /* The ISR installed depends on whether the preemptive or cooperative
+ scheduler is being used. */
+ #if configUSE_PREEMPTION == 1
+ {
+ extern void ( vPortPreemptiveTickEntry )( void );
- /* The ISR installed depends on whether the preemptive or cooperative
- * scheduler is being used. */
- #if configUSE_PREEMPTION == 1
- {
- extern void( vPortPreemptiveTickEntry )( void );
+ VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry;
+ }
+ #else
+ {
+ extern void ( vNonPreemptiveTick )( void );
- VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry;
- }
- #else
- {
- extern void( vNonPreemptiveTick )( void );
+ VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick;
+ }
+ #endif
- VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick;
- }
- #endif /* if configUSE_PREEMPTION == 1 */
+ VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
- VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
-
- /* Start the timer - interrupts are disabled when this function is called
- * so it is okay to do this here. */
- T0TCR = portENABLE_TIMER;
+ /* Start the timer - interrupts are disabled when this function is called
+ so it is okay to do this here. */
+ T0TCR = portENABLE_TIMER;
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- /* Disable interrupts first! */
- __disable_interrupt();
+ /* Disable interrupts first! */
+ __disable_interrupt();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- __enable_interrupt();
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ __enable_interrupt();
+ }
+ }
}
/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/portable/IAR/LPC2000/portmacro.h b/portable/IAR/LPC2000/portmacro.h
index 3133d8d..cb275c7 100644
--- a/portable/IAR/LPC2000/portmacro.h
+++ b/portable/IAR/LPC2000/portmacro.h
@@ -27,13 +27,13 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include <intrinsics.h>
+#include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -46,66 +46,68 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portYIELD() asm ( "SWI 0" )
- #define portNOP() asm ( "NOP" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portYIELD() asm ( "SWI 0" )
+#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
- __arm __interwork void vPortDisableInterruptsFromThumb( void );
- __arm __interwork void vPortEnableInterruptsFromThumb( void );
- __arm __interwork void vPortEnterCritical( void );
- __arm __interwork void vPortExitCritical( void );
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() __disable_interrupt()
- #define portENABLE_INTERRUPTS() __enable_interrupt()
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() __disable_interrupt()
+#define portENABLE_INTERRUPTS() __enable_interrupt()
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern void vTaskSwitchContext( void ); \
- \
- if( xSwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+{ \
+extern void vTaskSwitchContext( void ); \
+ \
+ if( xSwitchRequired ) \
+ { \
+ vTaskSwitchContext(); \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
+
diff --git a/portable/IAR/MSP430/port.c b/portable/IAR/MSP430/port.c
index 229cf06..1a03448 100644
--- a/portable/IAR/MSP430/port.c
+++ b/portable/IAR/MSP430/port.c
@@ -30,28 +30,28 @@
#include "task.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the MSP430 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
/* Constants required for hardware setup. The tick ISR runs off the ACLK,
- * not the MCLK. */
-#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/* Each task maintains a count of the critical section nesting depth. Each
- * time a critical section is entered the count is incremented. Each time a
- * critical section is exited the count is decremented - with interrupts only
- * being re-enabled if the count is zero.
- *
- * usCriticalNesting will get set to zero when the scheduler starts, but must
- * not be initialised to zero as this will cause problems during the startup
- * sequence. */
+time a critical section is entered the count is incremented. Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@@ -69,76 +69,74 @@
*
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /*
- * Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging and can be included if required.
- *
- * pxTopOfStack = ( StackType_t ) 0x1111;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x2222;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x3333;
- * pxTopOfStack--;
- */
+ /*
+ Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging and can be included if required.
- /* The msp430 automatically pushes the PC then SR onto the stack before
- * executing an ISR. We want the stack to look just as if this has happened
- * so place a pointer to the start of the task on the stack first - followed
- * by the flags we want the task to use when it starts up. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
- *pxTopOfStack = portFLAGS_INT_ENABLED;
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x3333;
+ pxTopOfStack--;
+ */
- /* Next the general purpose registers. */
- *pxTopOfStack = ( StackType_t ) 0x4444;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x5555;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x6666;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x7777;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x8888;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x9999;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaa;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xbbbb;
- pxTopOfStack--;
+ /* The msp430 automatically pushes the PC then SR onto the stack before
+ executing an ISR. We want the stack to look just as if this has happened
+ so place a pointer to the start of the task on the stack first - followed
+ by the flags we want the task to use when it starts up. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+ *pxTopOfStack = portFLAGS_INT_ENABLED;
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R15. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
+ /* Next the general purpose registers. */
+ *pxTopOfStack = ( StackType_t ) 0x4444;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x5555;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x6666;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x7777;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x8888;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x9999;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xbbbb;
+ pxTopOfStack--;
+
+ /* When the task starts is will expect to find the function parameter in
+ R15. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0xdddd;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xffff;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xdddd;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xeeee;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xffff;
- pxTopOfStack--;
+ /* A variable is used to keep track of the critical section nesting.
+ This variable has to be stored as part of the task context and is
+ initially set to zero. */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
- /* A variable is used to keep track of the critical section nesting.
- * This variable has to be stored as part of the task context and is
- * initially set to zero. */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
-
- /* Return a pointer to the top of the stack we have generated so this can
- * be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* Return a pointer to the top of the stack we have generated so this can
+ be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the MSP430 port will get stopped. If required simply
- * disable the tick interrupt here. */
+ /* It is unlikely that the MSP430 port will get stopped. If required simply
+ disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@@ -148,25 +146,28 @@
*/
void vPortSetupTimerInterrupt( void )
{
- /* Ensure the timer is stopped. */
- TACTL = 0;
+ /* Ensure the timer is stopped. */
+ TACTL = 0;
- /* Run the timer of the ACLK. */
- TACTL = TASSEL_1;
+ /* Run the timer of the ACLK. */
+ TACTL = TASSEL_1;
- /* Clear everything to start with. */
- TACTL |= TACLR;
+ /* Clear everything to start with. */
+ TACTL |= TACLR;
- /* Set the compare match value according to the tick rate we want. */
- TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+ /* Set the compare match value according to the tick rate we want. */
+ TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
- /* Enable the interrupts. */
- TACCTL0 = CCIE;
+ /* Enable the interrupts. */
+ TACCTL0 = CCIE;
- /* Start up clean. */
- TACTL |= TACLR;
+ /* Start up clean. */
+ TACTL |= TACLR;
- /* Up mode. */
- TACTL |= MC_1;
+ /* Up mode. */
+ TACTL |= MC_1;
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/IAR/MSP430/portasm.h b/portable/IAR/MSP430/portasm.h
index 0873b6a..d95e0ae 100644
--- a/portable/IAR/MSP430/portasm.h
+++ b/portable/IAR/MSP430/portasm.h
@@ -30,54 +30,55 @@
portSAVE_CONTEXT macro
-IMPORT pxCurrentTCB
-IMPORT usCriticalNesting
+ IMPORT pxCurrentTCB
+ IMPORT usCriticalNesting
-/* Save the remaining registers. */
-push r4
-push r5
-push r6
-push r7
-push r8
-push r9
-push r10
-push r11
-push r12
-push r13
-push r14
-push r15
-mov.w &usCriticalNesting, r14
-push r14
- mov.w &pxCurrentTCB, r12
- mov.w r1, 0 ( r12 )
-endm
+ /* Save the remaining registers. */
+ push r4
+ push r5
+ push r6
+ push r7
+ push r8
+ push r9
+ push r10
+ push r11
+ push r12
+ push r13
+ push r14
+ push r15
+ mov.w &usCriticalNesting, r14
+ push r14
+ mov.w &pxCurrentTCB, r12
+ mov.w r1, 0(r12)
+ endm
/*-----------------------------------------------------------*/
-
+
portRESTORE_CONTEXT macro
-mov.w & pxCurrentTCB, r12
-mov.w @r12, r1
-pop r15
-mov.w r15, &usCriticalNesting
-pop r15
-pop r14
-pop r13
-pop r12
-pop r11
-pop r10
-pop r9
-pop r8
-pop r7
-pop r6
-pop r5
-pop r4
+ mov.w &pxCurrentTCB, r12
+ mov.w @r12, r1
+ pop r15
+ mov.w r15, &usCriticalNesting
+ pop r15
+ pop r14
+ pop r13
+ pop r12
+ pop r11
+ pop r10
+ pop r9
+ pop r8
+ pop r7
+ pop r6
+ pop r5
+ pop r4
-/* The last thing on the stack will be the status register.
- * Ensure the power down bits are clear ready for the next
- * time this power down register is popped from the stack. */
-bic.w # 0xf0, 0 ( SP )
+ /* The last thing on the stack will be the status register.
+ Ensure the power down bits are clear ready for the next
+ time this power down register is popped from the stack. */
+ bic.w #0xf0,0(SP)
-reti
-endm
+ reti
+ endm
/*-----------------------------------------------------------*/
-#endif /* ifndef PORTASM_H */
+#endif
+
diff --git a/portable/IAR/MSP430/portmacro.h b/portable/IAR/MSP430/portmacro.h
index 9e957f8..c3a50aa 100644
--- a/portable/IAR/MSP430/portmacro.h
+++ b/portable/IAR/MSP430/portmacro.h
@@ -39,66 +39,66 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint16_t
-#define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() _DINT(); _NOP()
-#define portENABLE_INTERRUPTS() _EINT(); _NOP()
+#define portDISABLE_INTERRUPTS() _DINT(); _NOP()
+#define portENABLE_INTERRUPTS() _EINT(); _NOP()
/*-----------------------------------------------------------*/
/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
-#define portENTER_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled usCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled usCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
-#define portEXIT_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
@@ -107,26 +107,27 @@
* Manual context switch called by portYIELD or taskYIELD.
*/
extern void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD() vPortYield()
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 2
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portNOP()
-#define portPOINTER_SIZE_TYPE uint16_t
+#define portPOINTER_SIZE_TYPE uint16_t
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#if configINTERRUPT_EXAMPLE_METHOD == 2
- extern void vTaskSwitchContext( void );
- #define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/MSP430X/data_model.h b/portable/IAR/MSP430X/data_model.h
index 875cc3f..36935cb 100644
--- a/portable/IAR/MSP430X/data_model.h
+++ b/portable/IAR/MSP430X/data_model.h
@@ -29,34 +29,35 @@
#define DATA_MODEL_H
#if __DATA_MODEL__ == __DATA_MODEL_SMALL__
- #define pushm_x pushm.w
- #define popm_x popm.w
- #define push_x push.w
- #define pop_x pop.w
- #define mov_x mov.w
- #define cmp_x cmp.w
+ #define pushm_x pushm.w
+ #define popm_x popm.w
+ #define push_x push.w
+ #define pop_x pop.w
+ #define mov_x mov.w
+ #define cmp_x cmp.w
#endif
#if __DATA_MODEL__ == __DATA_MODEL_MEDIUM__
- #define pushm_x pushm.a
- #define popm_x popm.a
- #define push_x pushx.a
- #define pop_x popx.a
- #define mov_x mov.w
- #define cmp_x cmp.w
+ #define pushm_x pushm.a
+ #define popm_x popm.a
+ #define push_x pushx.a
+ #define pop_x popx.a
+ #define mov_x mov.w
+ #define cmp_x cmp.w
#endif
#if __DATA_MODEL__ == __DATA_MODEL_LARGE__
- #define pushm_x pushm.a
- #define popm_x popm.a
- #define push_x pushx.a
- #define pop_x popx.a
- #define mov_x movx.a
- #define cmp_x cmpx.a
+ #define pushm_x pushm.a
+ #define popm_x popm.a
+ #define push_x pushx.a
+ #define pop_x popx.a
+ #define mov_x movx.a
+ #define cmp_x cmpx.a
#endif
#ifndef pushm_x
- #error The assembler options must define one of the following symbols: __DATA_MODEL_SMALL__, __DATA_MODEL_MEDIUM__, or __DATA_MODEL_LARGE__
+ #error The assembler options must define one of the following symbols: __DATA_MODEL_SMALL__, __DATA_MODEL_MEDIUM__, or __DATA_MODEL_LARGE__
#endif
#endif /* DATA_MODEL_H */
+
diff --git a/portable/IAR/MSP430X/port.c b/portable/IAR/MSP430X/port.c
index 873ac71..fb460d0 100644
--- a/portable/IAR/MSP430X/port.c
+++ b/portable/IAR/MSP430X/port.c
@@ -30,28 +30,28 @@
#include "task.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the MSP430X port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the MSP430X port.
+ *----------------------------------------------------------*/
/* Constants required for hardware setup. The tick ISR runs off the ACLK,
- * not the MCLK. */
-#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/* Each task maintains a count of the critical section nesting depth. Each
- * time a critical section is entered the count is incremented. Each time a
- * critical section is exited the count is decremented - with interrupts only
- * being re-enabled if the count is zero.
- *
- * usCriticalNesting will get set to zero when the scheduler starts, but must
- * not be initialised to zero as this will cause problems during the startup
- * sequence. */
+time a critical section is entered the count is incremented. Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@@ -69,98 +69,95 @@
*
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint16_t * pusTopOfStack;
- uint32_t * pulTopOfStack;
+uint16_t *pusTopOfStack;
+uint32_t *pulTopOfStack;
- /*
- * Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging and can be included if required.
- *
- * pxTopOfStack = ( StackType_t ) 0x1111;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x2222;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x3333;
- */
+ /*
+ Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging and can be included if required.
+
+ *pxTopOfStack = ( StackType_t ) 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x3333;
+ */
- /* StackType_t is either 16 bits or 32 bits depending on the data model.
- * Some stacked items do not change size depending on the data model so have
- * to be explicitly cast to the correct size so this function will work
- * whichever data model is being used. */
- if( sizeof( StackType_t ) == sizeof( uint16_t ) )
- {
- /* Make room for a 20 bit value stored as a 32 bit value. */
- pusTopOfStack = ( uint16_t * ) pxTopOfStack;
- pusTopOfStack--;
- pulTopOfStack = ( uint32_t * ) pusTopOfStack;
- }
- else
- {
- pulTopOfStack = ( uint32_t * ) pxTopOfStack;
- }
+ /* StackType_t is either 16 bits or 32 bits depending on the data model.
+ Some stacked items do not change size depending on the data model so have
+ to be explicitly cast to the correct size so this function will work
+ whichever data model is being used. */
+ if( sizeof( StackType_t ) == sizeof( uint16_t ) )
+ {
+ /* Make room for a 20 bit value stored as a 32 bit value. */
+ pusTopOfStack = ( uint16_t * ) pxTopOfStack;
+ pusTopOfStack--;
+ pulTopOfStack = ( uint32_t * ) pusTopOfStack;
+ }
+ else
+ {
+ pulTopOfStack = ( uint32_t * ) pxTopOfStack;
+ }
+ *pulTopOfStack = ( uint32_t ) pxCode;
+
+ pusTopOfStack = ( uint16_t * ) pulTopOfStack;
+ pusTopOfStack--;
+ *pusTopOfStack = portFLAGS_INT_ENABLED;
+ pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
+
+ /* From here on the size of stacked items depends on the memory model. */
+ pxTopOfStack = ( StackType_t * ) pusTopOfStack;
- *pulTopOfStack = ( uint32_t ) pxCode;
-
- pusTopOfStack = ( uint16_t * ) pulTopOfStack;
- pusTopOfStack--;
- *pusTopOfStack = portFLAGS_INT_ENABLED;
- pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
-
- /* From here on the size of stacked items depends on the memory model. */
- pxTopOfStack = ( StackType_t * ) pusTopOfStack;
-
- /* Next the general purpose registers. */
- #ifdef PRELOAD_REGISTER_VALUES
- *pxTopOfStack = ( StackType_t ) 0xffff;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xeeee;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xdddd;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xbbbb;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaa;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x9999;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x8888;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x5555;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x6666;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x5555;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x4444;
- pxTopOfStack--;
- #else /* ifdef PRELOAD_REGISTER_VALUES */
- pxTopOfStack -= 3;
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack -= 9;
- #endif /* ifdef PRELOAD_REGISTER_VALUES */
+ /* Next the general purpose registers. */
+ #ifdef PRELOAD_REGISTER_VALUES
+ *pxTopOfStack = ( StackType_t ) 0xffff;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xdddd;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x9999;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x8888;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x5555;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x6666;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x5555;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x4444;
+ pxTopOfStack--;
+ #else
+ pxTopOfStack -= 3;
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack -= 9;
+ #endif
- /* A variable is used to keep track of the critical section nesting.
- * This variable has to be stored as part of the task context and is
- * initially set to zero. */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+ /* A variable is used to keep track of the critical section nesting.
+ This variable has to be stored as part of the task context and is
+ initially set to zero. */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
- /* Return a pointer to the top of the stack we have generated so this can
- * be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* Return a pointer to the top of the stack we have generated so this can
+ be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the MSP430 port will get stopped. If required simply
- * disable the tick interrupt here. */
+ /* It is unlikely that the MSP430 port will get stopped. If required simply
+ disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@@ -169,15 +166,17 @@
*/
void vPortSetupTimerInterrupt( void )
{
- vApplicationSetupTimerInterrupt();
+ vApplicationSetupTimerInterrupt();
}
/*-----------------------------------------------------------*/
#pragma vector=configTICK_VECTOR
__interrupt __raw void vTickISREntry( void )
{
- extern void vPortTickISR( void );
+extern void vPortTickISR( void );
- __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
- vPortTickISR();
+ __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
+ vPortTickISR();
}
+
+
diff --git a/portable/IAR/MSP430X/portmacro.h b/portable/IAR/MSP430X/portmacro.h
index 708601c..cf0aace 100644
--- a/portable/IAR/MSP430X/portmacro.h
+++ b/portable/IAR/MSP430X/portmacro.h
@@ -42,72 +42,72 @@
#include "msp430.h"
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portBASE_TYPE short
/* The stack type changes depending on the data model. */
-#if ( __DATA_MODEL__ == __DATA_MODEL_SMALL__ )
- #define portSTACK_TYPE uint16_t
- #define portPOINTER_SIZE_TYPE uint16_t
+#if( __DATA_MODEL__ == __DATA_MODEL_SMALL__ )
+ #define portSTACK_TYPE uint16_t
+ #define portPOINTER_SIZE_TYPE uint16_t
#else
- #define portSTACK_TYPE uint32_t
+ #define portSTACK_TYPE uint32_t
#endif
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() _DINT(); _NOP()
-#define portENABLE_INTERRUPTS() _EINT(); _NOP()
+#define portDISABLE_INTERRUPTS() _DINT(); _NOP()
+#define portENABLE_INTERRUPTS() _EINT(); _NOP()
/*-----------------------------------------------------------*/
/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
-#define portENTER_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled usCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled usCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
-#define portEXIT_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
@@ -116,26 +116,27 @@
* Manual context switch called by portYIELD or taskYIELD.
*/
extern void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD() vPortYield()
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 2
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() __no_operation()
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __no_operation()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
+#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
void vApplicationSetupTimerInterrupt( void );
/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
- * run time stats information is to be displayed. */
+run time stats information is to be displayed. */
#define portLU_PRINTF_SPECIFIER_REQUIRED
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
index 1877057..2296be8 100644
--- a/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -53,16 +53,16 @@
#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
#define __FREERTOS_RISC_V_EXTENSIONS_H__
-#define portasmHAS_SIFIVE_CLINT 1
-#define portasmHAS_MTIME 1
-#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+#define portasmHAS_SIFIVE_CLINT 1
+#define portasmHAS_MTIME 1
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
portasmSAVE_ADDITIONAL_REGISTERS MACRO
-/* No additional registers to save, so this macro does nothing. */
-ENDM
+ /* No additional registers to save, so this macro does nothing. */
+ ENDM
portasmRESTORE_ADDITIONAL_REGISTERS MACRO
-/* No additional registers to restore, so this macro does nothing. */
- ENDM
+ /* No additional registers to restore, so this macro does nothing. */
+ ENDM
#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/portable/IAR/RISC-V/port.c b/portable/IAR/RISC-V/port.c
index 3d73271..bf8eca0 100644
--- a/portable/IAR/RISC-V/port.c
+++ b/portable/IAR/RISC-V/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RISC-V RV32 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RISC-V RV32 port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -38,44 +38,44 @@
#include "string.h"
#ifdef configCLINT_BASE_ADDRESS
- #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
+ #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef configMTIME_BASE_ADDRESS
- #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
+ #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef configMTIMECMP_BASE_ADDRESS
- #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
+ #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
- * to use a statically allocated array as the interrupt stack. Alternative leave
- * configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
- * linker variable names __freertos_irq_stack_top has the same value as the top
- * of the stack used by main. Using the linker script method will repurpose the
- * stack that was used by main before the scheduler was started for use as the
- * interrupt stack after the scheduler has started. */
+to use a statically allocated array as the interrupt stack. Alternative leave
+configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
+linker variable names __freertos_irq_stack_top has the same value as the top
+of the stack used by main. Using the linker script method will repurpose the
+stack that was used by main before the scheduler was started for use as the
+interrupt stack after the scheduler has started. */
#ifdef configISR_STACK_SIZE_WORDS
- static __attribute__( ( aligned( 16 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
- const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
+ static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
+ const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
-/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
- * the task stacks, and so will legitimately appear in many positions within
- * the ISR stack. */
- #define portISR_STACK_FILL_BYTE 0xee
+ /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+ the task stacks, and so will legitimately appear in many positions within
+ the ISR stack. */
+ #define portISR_STACK_FILL_BYTE 0xee
#else
- extern const uint32_t __freertos_irq_stack_top[];
- const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
+ extern const uint32_t __freertos_irq_stack_top[];
+ const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
#endif
/*
@@ -83,130 +83,130 @@
* file is weak to allow application writers to change the timer used to
* generate the tick interrupt.
*/
-void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
+void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
/*-----------------------------------------------------------*/
/* Used to program the machine timer compare register. */
uint64_t ullNextTime = 0ULL;
-const uint64_t * pullNextTime = &ullNextTime;
+const uint64_t *pullNextTime = &ullNextTime;
const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
volatile uint64_t * pullMachineTimerCompareRegister = NULL;
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
- * stack checking. A problem in the ISR stack will trigger an assert, not call the
- * stack overflow hook function (because the stack overflow hook is specific to a
- * task stack, not the ISR stack). */
+stack checking. A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
- #warning This path not tested, or even compiled yet.
+ #warning This path not tested, or even compiled yet.
- static const uint8_t ucExpectedStackBytes[] =
- {
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
- }; \
+ static const uint8_t ucExpectedStackBytes[] = {
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
- #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
- /* Define the function away. */
- #define portCHECK_ISR_STACK()
+ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+ /* Define the function away. */
+ #define portCHECK_ISR_STACK()
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
/*-----------------------------------------------------------*/
-#if ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
+#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
- void vPortSetupTimerInterrupt( void )
- {
- uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
- volatile uint32_t * const pulTimeHigh = ( uint32_t * ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */
- volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configMTIME_BASE_ADDRESS );
- volatile uint32_t ulHartId;
+ void vPortSetupTimerInterrupt( void )
+ {
+ uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+ volatile uint32_t * const pulTimeHigh = ( uint32_t * ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */
+ volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configMTIME_BASE_ADDRESS );
+ volatile uint32_t ulHartId;
- __asm volatile ( "csrr %0, 0xf14" : "=r" ( ulHartId ) ); /* 0xf14 is hartid. */
+ __asm volatile( "csrr %0, 0xf14" : "=r"( ulHartId ) ); /* 0xf14 is hartid. */
+ pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
- pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
+ do
+ {
+ ulCurrentTimeHigh = *pulTimeHigh;
+ ulCurrentTimeLow = *pulTimeLow;
+ } while( ulCurrentTimeHigh != *pulTimeHigh );
- do
- {
- ulCurrentTimeHigh = *pulTimeHigh;
- ulCurrentTimeLow = *pulTimeLow;
- } while( ulCurrentTimeHigh != *pulTimeHigh );
+ ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
+ ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
+ ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+ *pullMachineTimerCompareRegister = ullNextTime;
- ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
- ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
- ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
- ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
- *pullMachineTimerCompareRegister = ullNextTime;
-
- /* Prepare the time to use after the next tick interrupt. */
- ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
- }
+ /* Prepare the time to use after the next tick interrupt. */
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+ }
#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void xPortStartFirstTask( void );
+extern void xPortStartFirstTask( void );
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t mtvec = 0;
+ #if( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t mtvec = 0;
- /* Check the least significant two bits of mtvec are 00 - indicating
- * single vector mode. */
- __asm volatile ( "csrr %0, 0x305" : "=r" ( mtvec ) ); /* 0x305 is mtvec. */
- configASSERT( ( mtvec & 0x03UL ) == 0 );
+ /* Check the least significant two bits of mtvec are 00 - indicating
+ single vector mode. */
+ __asm volatile( "csrr %0, 0x305" : "=r"( mtvec ) ); /* 0x305 is mtvec. */
+ configASSERT( ( mtvec & 0x03UL ) == 0 );
- /* Check alignment of the interrupt stack - which is the same as the
- * stack that was being used by main() prior to the scheduler being
- * started. */
- configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
+ /* Check alignment of the interrupt stack - which is the same as the
+ stack that was being used by main() prior to the scheduler being
+ started. */
+ configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
- #ifdef configISR_STACK_SIZE_WORDS
- {
- memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
- }
- #endif /* configISR_STACK_SIZE_WORDS */
- }
- #endif /* configASSERT_DEFINED */
+ #ifdef configISR_STACK_SIZE_WORDS
+ {
+ memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+ }
+ #endif /* configISR_STACK_SIZE_WORDS */
+ }
+ #endif /* configASSERT_DEFINED */
- /* If there is a CLINT then it is ok to use the default implementation
- * in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
- * configure whichever clock is to be used to generate the tick interrupt. */
- vPortSetupTimerInterrupt();
+ /* If there is a CLINT then it is ok to use the default implementation
+ in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
+ configure whichever clock is to be used to generate the tick interrupt. */
+ vPortSetupTimerInterrupt();
- #if ( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
- {
- /* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
- * for external interrupt. _RB_ What happens here when mtime is not present as
- * with pulpino? */
- __asm volatile ( "csrs 0x304, %0" ::"r" ( 0x880 ) ); /* 0x304 is mie. */
- }
- #else
- {
- /* Enable external interrupts. */
- __asm volatile ( "csrs 0x304, %0" ::"r" ( 0x800 ) ); /* 304 is mie. */
- }
- #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
+ #if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
+ {
+ /* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
+ for external interrupt. _RB_ What happens here when mtime is not present as
+ with pulpino? */
+ __asm volatile( "csrs 0x304, %0" :: "r"(0x880) ); /* 0x304 is mie. */
+ }
+ #else
+ {
+ /* Enable external interrupts. */
+ __asm volatile( "csrs 0x304, %0" :: "r"(0x800) ); /* 304 is mie. */
+ }
+ #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
- xPortStartFirstTask();
+ xPortStartFirstTask();
- /* Should not get here as after calling xPortStartFirstTask() only tasks
- * should be executing. */
- return pdFAIL;
+ /* Should not get here as after calling xPortStartFirstTask() only tasks
+ should be executing. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented. */
- for( ; ; )
- {
- }
+ /* Not implemented. */
+ for( ;; );
}
+
+
+
+
+
diff --git a/portable/IAR/RISC-V/portmacro.h b/portable/IAR/RISC-V/portmacro.h
index e43fbad..4d31f4f 100644
--- a/portable/IAR/RISC-V/portmacro.h
+++ b/portable/IAR/RISC-V/portmacro.h
@@ -27,13 +27,13 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include "intrinsics.h"
+#include "intrinsics.h"
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -46,133 +46,132 @@
*/
/* Type definitions. */
- #if __riscv_xlen == 64
- #define portSTACK_TYPE uint64_t
- #define portBASE_TYPE int64_t
- #define portUBASE_TYPE uint64_t
- #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
- #define portPOINTER_SIZE_TYPE uint64_t
- #elif __riscv_xlen == 32
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE int32_t
- #define portUBASE_TYPE uint32_t
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #else /* if __riscv_xlen == 64 */
- #error Assembler did not define __riscv_xlen
- #endif /* if __riscv_xlen == 64 */
+#if __riscv_xlen == 64
+ #define portSTACK_TYPE uint64_t
+ #define portBASE_TYPE int64_t
+ #define portUBASE_TYPE uint64_t
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
+ #define portPOINTER_SIZE_TYPE uint64_t
+#elif __riscv_xlen == 32
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE int32_t
+ #define portUBASE_TYPE uint32_t
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#else
+ #error Assembler did not define __riscv_xlen
+#endif
- typedef portSTACK_TYPE StackType_t;
- typedef portBASE_TYPE BaseType_t;
- typedef portUBASE_TYPE UBaseType_t;
- typedef portUBASE_TYPE TickType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef portUBASE_TYPE UBaseType_t;
+typedef portUBASE_TYPE TickType_t;
/* Legacy type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #ifdef __riscv64
- #error This is the RV32 port that has not yet been adapted for 64.
- #define portBYTE_ALIGNMENT 16
- #else
- #define portBYTE_ALIGNMENT 16
- #endif
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#ifdef __riscv64
+ #error This is the RV32 port that has not yet been adapted for 64.
+ #define portBYTE_ALIGNMENT 16
+#else
+ #define portBYTE_ALIGNMENT 16
+#endif
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- extern void vTaskSwitchContext( void );
- #define portYIELD() __asm volatile ( "ecall" );
- #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+extern void vTaskSwitchContext( void );
+#define portYIELD() __asm volatile( "ecall" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- #define portCRITICAL_NESTING_IN_TCB 1
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB 1
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() 0
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
- #define portDISABLE_INTERRUPTS() __disable_interrupt()
- #define portENABLE_INTERRUPTS() __enable_interrupt()
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#define portDISABLE_INTERRUPTS() __disable_interrupt()
+#define portENABLE_INTERRUPTS() __enable_interrupt()
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated.
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated.
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo files
- * (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+not necessary for to use this port. They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
- #define portNOP() __asm volatile ( " nop " )
+#define portNOP() __asm volatile ( " nop " )
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
- * the source code because to do so would cause other compilers to generate
- * warnings. */
- #pragma diag_suppress=Pa082
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pa082
/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
- * configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
- * backward compatibility derive the newer definitions from the old if the old
- * definition is found. */
- #if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
-
-/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
- * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
- * addresses to 0. */
- #define configMTIME_BASE_ADDRESS ( 0 )
- #define configMTIMECMP_BASE_ADDRESS ( 0 )
- #elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
-
-/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
- * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
- * from the CLINT address. */
- #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
- #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
- #elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
- #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https: /*www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
- #endif /* if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) */
+configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
+backward compatibility derive the newer definitions from the old if the old
+definition is found. */
+#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
+ /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
+ there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
+ addresses to 0. */
+ #define configMTIME_BASE_ADDRESS ( 0 )
+ #define configMTIMECMP_BASE_ADDRESS ( 0 )
+#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
+ /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
+ the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
+ from the CLINT address. */
+ #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
+ #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
+#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
+ #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
+#endif
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/RL78/ISR_Support.h b/portable/IAR/RL78/ISR_Support.h
index e48401b..1be2a7b 100644
--- a/portable/IAR/RL78/ISR_Support.h
+++ b/portable/IAR/RL78/ISR_Support.h
@@ -1,112 +1,83 @@
-; /*
- * ; * FreeRTOS Kernel V10.3.1
- * ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * ; *
- * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * ; * this software and associated documentation files (the "Software"), to deal in
- * ; * the Software without restriction, including without limitation the rights to
- * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * ; * the Software, and to permit persons to whom the Software is furnished to do so,
- * ; * subject to the following conditions:
- * ; *
- * ; * The above copyright notice and this permission notice shall be included in all
- * ; * copies or substantial portions of the Software.
- * ; *
- * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * ; *
- * ; * http://www.FreeRTOS.org
- * ; * http://aws.amazon.com/freertos
- * ; *
- * ; * 1 tab == 4 spaces!
- * ; */
+;/*
+; * FreeRTOS Kernel V10.3.1
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
#include "FreeRTOSConfig.h"
-;
-Variables used by scheduler
-;
-------------------------------------------------------------------------------
-EXTERN pxCurrentTCB
-EXTERN usCriticalNesting
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+ EXTERN pxCurrentTCB
+ EXTERN usCriticalNesting
-;
-------------------------------------------------------------------------------
-;
-portSAVE_CONTEXT MACRO
-;
-Saves the context of the general purpose registers, CS and ES( only in far
- ;
- memory mode ) registers the usCriticalNesting Value and the Stack Pointer
-;
-of the active Task onto the task stack
-;
-------------------------------------------------------------------------------
+;------------------------------------------------------------------------------
+; portSAVE_CONTEXT MACRO
+; Saves the context of the general purpose registers, CS and ES (only in far
+; memory mode) registers the usCriticalNesting Value and the Stack Pointer
+; of the active Task onto the task stack
+;------------------------------------------------------------------------------
portSAVE_CONTEXT MACRO
-PUSH AX;
-Save AX Register to stack.
- PUSH HL
-MOV A, CS;
-Save CS register.
- XCH A, X
-MOV A, ES;
-Save ES register.
- PUSH AX
-PUSH DE;
-Save the remaining general purpose registers.
- PUSH BC
-MOVW AX, usCriticalNesting;
-Save the usCriticalNesting value.
- PUSH AX
-MOVW AX, pxCurrentTCB;
-Save the Stack pointer.
- MOVW HL, AX
-MOVW AX, SP
- MOVW[ HL ], AX
- ENDM
-;
-------------------------------------------------------------------------------
+ PUSH AX ; Save AX Register to stack.
+ PUSH HL
+ MOV A, CS ; Save CS register.
+ XCH A, X
+ MOV A, ES ; Save ES register.
+ PUSH AX
+ PUSH DE ; Save the remaining general purpose registers.
+ PUSH BC
+ MOVW AX, usCriticalNesting ; Save the usCriticalNesting value.
+ PUSH AX
+ MOVW AX, pxCurrentTCB ; Save the Stack pointer.
+ MOVW HL, AX
+ MOVW AX, SP
+ MOVW [HL], AX
+ ENDM
+;------------------------------------------------------------------------------
-;
-------------------------------------------------------------------------------
-;
+;------------------------------------------------------------------------------
+; portRESTORE_CONTEXT MACRO
+; Restores the task Stack Pointer then use this to restore usCriticalNesting,
+; general purpose registers and the CS and ES (only in far memory mode)
+; of the selected task from the task stack
+;------------------------------------------------------------------------------
portRESTORE_CONTEXT MACRO
-;
-Restores the task Stack Pointer then use this to restore usCriticalNesting,
-;
-general purpose registers and the CS and ES( only in far memory mode )
-;
-of the selected task from the task stack
-;
-------------------------------------------------------------------------------
-portRESTORE_CONTEXT MACRO
-MOVW AX, pxCurrentTCB;
-Restore the Stack pointer.
- MOVW HL, AX
-MOVW AX, [ HL ]
-MOVW SP, AX
-POP AX;
-Restore usCriticalNesting value.
- MOVW usCriticalNesting, AX
-POP BC;
-Restore the necessary general purpose registers.
- POP DE
-POP AX;
-Restore the ES register.
- MOV ES, A
-XCH A, X;
-Restore the CS register.
- MOV CS, A
-POP HL;
-Restore general purpose register HL.
- POP AX;
-Restore AX.
- ENDM
-;
-------------------------------------------------------------------------------
+ MOVW AX, pxCurrentTCB ; Restore the Stack pointer.
+ MOVW HL, AX
+ MOVW AX, [HL]
+ MOVW SP, AX
+ POP AX ; Restore usCriticalNesting value.
+ MOVW usCriticalNesting, AX
+ POP BC ; Restore the necessary general purpose registers.
+ POP DE
+ POP AX ; Restore the ES register.
+ MOV ES, A
+ XCH A, X ; Restore the CS register.
+ MOV CS, A
+ POP HL ; Restore general purpose register HL.
+ POP AX ; Restore AX.
+ ENDM
+;------------------------------------------------------------------------------
diff --git a/portable/IAR/RL78/port.c b/portable/IAR/RL78/port.c
index 3af6152..3dbe43e 100644
--- a/portable/IAR/RL78/port.c
+++ b/portable/IAR/RL78/port.c
@@ -30,8 +30,8 @@
#include "task.h"
/* The critical nesting value is initialised to a non zero value to ensure
- * interrupts don't accidentally become enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
+interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
/* Initial PSW value allocated to a newly created task.
* 1100011000000000
@@ -44,21 +44,21 @@
* |--------------------- Zero Flag set
* ---------------------- Global Interrupt Flag set (enabled)
*/
-#define portPSW ( 0xc6UL )
+#define portPSW ( 0xc6UL )
/* The address of the pxCurrentTCB variable, but don't know or need to know its
- * type. */
+type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/* Each task maintains a count of the critical section nesting depth. Each time
- * a critical section is entered the count is incremented. Each time a critical
- * section is exited the count is decremented - with interrupts only being
- * re-enabled if the count is zero.
- *
- * usCriticalNesting will get set to zero when the scheduler starts, but must
- * not be initialised to zero as that could cause problems during the startup
- * sequence. */
+a critical section is entered the count is incremented. Each time a critical
+section is exited the count is decremented - with interrupts only being
+re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as that could cause problems during the startup
+sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@@ -71,10 +71,9 @@
*/
static void prvSetupTimerInterrupt( void );
#ifndef configSETUP_TICK_INTERRUPT
-
-/* The user has not provided their own tick interrupt configuration so use
- * the definition in this file (which uses the interval timer). */
- #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+ /* The user has not provided their own tick interrupt configuration so use
+ the definition in this file (which uses the interval timer). */
+ #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
#endif /* configSETUP_TICK_INTERRUPT */
/*
@@ -96,190 +95,186 @@
*
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint32_t * pulLocal;
+uint32_t *pulLocal;
- /* With large code and large data sizeof( StackType_t ) == 2, and
- * sizeof( StackType_t * ) == 4. With small code and small data
- * sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */
+ /* With large code and large data sizeof( StackType_t ) == 2, and
+ sizeof( StackType_t * ) == 4. With small code and small data
+ sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */
- #if __DATA_MODEL__ == __DATA_MODEL_FAR__
- {
- /* Parameters are passed in on the stack, and written using a 32-bit value
- * hence a space is left for the second two bytes. */
- pxTopOfStack--;
+ #if __DATA_MODEL__ == __DATA_MODEL_FAR__
+ {
+ /* Parameters are passed in on the stack, and written using a 32-bit value
+ hence a space is left for the second two bytes. */
+ pxTopOfStack--;
- /* Write in the parameter value. */
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( uint32_t ) pvParameters;
- pxTopOfStack--;
+ /* Write in the parameter value. */
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( uint32_t ) pvParameters;
+ pxTopOfStack--;
- /* The return address, leaving space for the first two bytes of the
- * 32-bit value. See the comments above the prvTaskExitError() prototype
- * at the top of this file. */
- pxTopOfStack--;
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( uint32_t ) prvTaskExitError;
- pxTopOfStack--;
+ /* The return address, leaving space for the first two bytes of the
+ 32-bit value. See the comments above the prvTaskExitError() prototype
+ at the top of this file. */
+ pxTopOfStack--;
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( uint32_t ) prvTaskExitError;
+ pxTopOfStack--;
- /* The start address / PSW value is also written in as a 32-bit value,
- * so leave a space for the second two bytes. */
- pxTopOfStack--;
+ /* The start address / PSW value is also written in as a 32-bit value,
+ so leave a space for the second two bytes. */
+ pxTopOfStack--;
- /* Task function start address combined with the PSW. */
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
- pxTopOfStack--;
+ /* Task function start address combined with the PSW. */
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+ pxTopOfStack--;
- /* An initial value for the AX register. */
- *pxTopOfStack = ( StackType_t ) 0x1111;
- pxTopOfStack--;
- }
- #else /* if __DATA_MODEL__ == __DATA_MODEL_FAR__ */
- {
- /* The return address, leaving space for the first two bytes of the
- * 32-bit value. See the comments above the prvTaskExitError() prototype
- * at the top of this file. */
- pxTopOfStack--;
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( uint32_t ) prvTaskExitError;
- pxTopOfStack--;
+ /* An initial value for the AX register. */
+ *pxTopOfStack = ( StackType_t ) 0x1111;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ /* The return address, leaving space for the first two bytes of the
+ 32-bit value. See the comments above the prvTaskExitError() prototype
+ at the top of this file. */
+ pxTopOfStack--;
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( uint32_t ) prvTaskExitError;
+ pxTopOfStack--;
- /* Task function. Again as it is written as a 32-bit value a space is
- * left on the stack for the second two bytes. */
- pxTopOfStack--;
+ /* Task function. Again as it is written as a 32-bit value a space is
+ left on the stack for the second two bytes. */
+ pxTopOfStack--;
- /* Task function start address combined with the PSW. */
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
- pxTopOfStack--;
+ /* Task function start address combined with the PSW. */
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+ pxTopOfStack--;
- /* The parameter is passed in AX. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
- }
- #endif /* if __DATA_MODEL__ == __DATA_MODEL_FAR__ */
+ /* The parameter is passed in AX. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+ }
+ #endif
- /* An initial value for the HL register. */
- *pxTopOfStack = ( StackType_t ) 0x2222;
- pxTopOfStack--;
+ /* An initial value for the HL register. */
+ *pxTopOfStack = ( StackType_t ) 0x2222;
+ pxTopOfStack--;
- /* CS and ES registers. */
- *pxTopOfStack = ( StackType_t ) 0x0F00;
- pxTopOfStack--;
+ /* CS and ES registers. */
+ *pxTopOfStack = ( StackType_t ) 0x0F00;
+ pxTopOfStack--;
- /* The remaining general purpose registers DE and BC */
- *pxTopOfStack = ( StackType_t ) 0xDEDE;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xBCBC;
- pxTopOfStack--;
+ /* The remaining general purpose registers DE and BC */
+ *pxTopOfStack = ( StackType_t ) 0xDEDE;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xBCBC;
+ pxTopOfStack--;
- /* Finally the critical section nesting count is set to zero when the task
- * first starts. */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+ /* Finally the critical section nesting count is set to zero when the task
+ first starts. */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
- /* Return a pointer to the top of the stack that has been generated so it
- * can be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* Return a pointer to the top of the stack that has been generated so it
+ can be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( usCriticalNesting == ~0U );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( usCriticalNesting == ~0U );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- * this function is called. */
- configSETUP_TICK_INTERRUPT();
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called. */
+ configSETUP_TICK_INTERRUPT();
- /* Restore the context of the first task that is going to run. */
- vPortStartFirstTask();
+ /* Restore the context of the first task that is going to run. */
+ vPortStartFirstTask();
- /* Execution should not reach here as the tasks are now running!
- * prvSetupTimerInterrupt() is called here to prevent the compiler outputting
- * a warning about a statically declared function not being referenced in the
- * case that the application writer has provided their own tick interrupt
- * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
- * their own routine will be called in place of prvSetupTimerInterrupt()). */
- prvSetupTimerInterrupt();
- return pdTRUE;
+ /* Execution should not reach here as the tasks are now running!
+ prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+ a warning about a statically declared function not being referenced in the
+ case that the application writer has provided their own tick interrupt
+ configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+ their own routine will be called in place of prvSetupTimerInterrupt()). */
+ prvSetupTimerInterrupt();
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the RL78 port will get stopped. */
+ /* It is unlikely that the RL78 port will get stopped. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- const uint16_t usClockHz = 15000UL; /* Internal clock. */
- const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
+const uint16_t usClockHz = 15000UL; /* Internal clock. */
+const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
- /* Use the internal 15K clock. */
- OSMC = ( uint8_t ) 0x16;
+ /* Use the internal 15K clock. */
+ OSMC = ( uint8_t ) 0x16;
- #ifdef RTCEN
- {
- /* Supply the interval timer clock. */
- RTCEN = ( uint8_t ) 1U;
+ #ifdef RTCEN
+ {
+ /* Supply the interval timer clock. */
+ RTCEN = ( uint8_t ) 1U;
- /* Disable INTIT interrupt. */
- ITMK = ( uint8_t ) 1;
+ /* Disable INTIT interrupt. */
+ ITMK = ( uint8_t ) 1;
- /* Disable ITMC operation. */
- ITMC = ( uint8_t ) 0x0000;
+ /* Disable ITMC operation. */
+ ITMC = ( uint8_t ) 0x0000;
- /* Clear INIT interrupt. */
- ITIF = ( uint8_t ) 0;
+ /* Clear INIT interrupt. */
+ ITIF = ( uint8_t ) 0;
- /* Set interval and enable interrupt operation. */
- ITMC = usCompareMatch | 0x8000U;
+ /* Set interval and enable interrupt operation. */
+ ITMC = usCompareMatch | 0x8000U;
- /* Enable INTIT interrupt. */
- ITMK = ( uint8_t ) 0;
- }
- #endif /* ifdef RTCEN */
+ /* Enable INTIT interrupt. */
+ ITMK = ( uint8_t ) 0;
+ }
+ #endif
- #ifdef TMKAEN
- {
- /* Supply the interval timer clock. */
- TMKAEN = ( uint8_t ) 1U;
+ #ifdef TMKAEN
+ {
+ /* Supply the interval timer clock. */
+ TMKAEN = ( uint8_t ) 1U;
- /* Disable INTIT interrupt. */
- TMKAMK = ( uint8_t ) 1;
+ /* Disable INTIT interrupt. */
+ TMKAMK = ( uint8_t ) 1;
- /* Disable ITMC operation. */
- ITMC = ( uint8_t ) 0x0000;
+ /* Disable ITMC operation. */
+ ITMC = ( uint8_t ) 0x0000;
- /* Clear INIT interrupt. */
- TMKAIF = ( uint8_t ) 0;
+ /* Clear INIT interrupt. */
+ TMKAIF = ( uint8_t ) 0;
- /* Set interval and enable interrupt operation. */
- ITMC = usCompareMatch | 0x8000U;
+ /* Set interval and enable interrupt operation. */
+ ITMC = usCompareMatch | 0x8000U;
- /* Enable INTIT interrupt. */
- TMKAMK = ( uint8_t ) 0;
- }
- #endif /* ifdef TMKAEN */
+ /* Enable INTIT interrupt. */
+ TMKAMK = ( uint8_t ) 0;
+ }
+ #endif
}
/*-----------------------------------------------------------*/
+
diff --git a/portable/IAR/RL78/portmacro.h b/portable/IAR/RL78/portmacro.h
index d667dae..c6aa995 100644
--- a/portable/IAR/RL78/portmacro.h
+++ b/portable/IAR/RL78/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -42,102 +42,103 @@
*-----------------------------------------------------------
*/
- #if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__
- #warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model.
- #endif
+#if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__
+ #warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model.
+#endif
- #if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__
- #warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model.
- #endif
+#if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__
+ #warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model.
+#endif
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint16_t
- #define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
- typedef portSTACK_TYPE StackType_t;
- typedef short BaseType_t;
- typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
- #if __DATA_MODEL__ == __DATA_MODEL_FAR__
- #define portPOINTER_SIZE_TYPE uint32_t
- #else
- #define portPOINTER_SIZE_TYPE uint16_t
- #endif
+#if __DATA_MODEL__ == __DATA_MODEL_FAR__
+ #define portPOINTER_SIZE_TYPE uint32_t
+#else
+ #define portPOINTER_SIZE_TYPE uint16_t
+#endif
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef unsigned int TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if ( configUSE_16_BIT_TICKS == 1 )
+ typedef unsigned int TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
- #define portDISABLE_INTERRUPTS() __asm( "DI" )
- #define portENABLE_INTERRUPTS() __asm( "EI" )
+#define portDISABLE_INTERRUPTS() __asm ( "DI" )
+#define portENABLE_INTERRUPTS() __asm ( "EI" )
/*-----------------------------------------------------------*/
/* Critical section control macros. */
- #define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
- #define portENTER_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
- #define portEXIT_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portYIELD() __asm( "BRK" )
- #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
- #define portNOP() __asm( "NOP" )
+#define portYIELD() __asm( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+#define portNOP() __asm( "NOP" )
/*-----------------------------------------------------------*/
/* Hardwware specifics. */
- #define portBYTE_ALIGNMENT 2
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/RX100/port.c b/portable/IAR/RX100/port.c
index 65acbf4..083e740 100644
--- a/portable/IAR/RX100/port.c
+++ b/portable/IAR/RX100/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the SH2A port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
/* Standard C includes. */
#include "limits.h"
@@ -45,29 +45,29 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
/* The peripheral clock is divided by this value before being supplying the
- * CMT. */
+CMT. */
#if ( configUSE_TICKLESS_IDLE == 0 )
- /* If tickless idle is not used then the divisor can be fixed. */
- #define portCLOCK_DIVISOR 8UL
+ /* If tickless idle is not used then the divisor can be fixed. */
+ #define portCLOCK_DIVISOR 8UL
#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
- #define portCLOCK_DIVISOR 512UL
+ #define portCLOCK_DIVISOR 512UL
#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
- #define portCLOCK_DIVISOR 128UL
+ #define portCLOCK_DIVISOR 128UL
#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
- #define portCLOCK_DIVISOR 32UL
+ #define portCLOCK_DIVISOR 32UL
#else
- #define portCLOCK_DIVISOR 8UL
+ #define portCLOCK_DIVISOR 8UL
#endif
/* Keys required to lock and unlock access to certain system registers
- * respectively. */
-#define portUNLOCK_KEY 0xA50B
-#define portLOCK_KEY 0xA500
+respectively. */
+#define portUNLOCK_KEY 0xA50B
+#define portLOCK_KEY 0xA500
/*-----------------------------------------------------------*/
@@ -91,10 +91,9 @@
*/
static void prvSetupTimerInterrupt( void );
#ifndef configSETUP_TICK_INTERRUPT
-
-/* The user has not provided their own tick interrupt configuration so use
- * the definition in this file (which uses the interval timer). */
- #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+ /* The user has not provided their own tick interrupt configuration so use
+ the definition in this file (which uses the interval timer). */
+ #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
#endif /* configSETUP_TICK_INTERRUPT */
/*
@@ -103,12 +102,12 @@
* instruction.
*/
#if configUSE_TICKLESS_IDLE == 1
- static void prvSleep( TickType_t xExpectedIdleTime );
+ static void prvSleep( TickType_t xExpectedIdleTime );
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
-extern void * pxCurrentTCB;
+extern void *pxCurrentTCB;
/*-----------------------------------------------------------*/
@@ -117,406 +116,401 @@
#if configUSE_TICKLESS_IDLE == 1
-/* Holds the maximum number of ticks that can be suppressed - which is
- * basically how far into the future an interrupt can be generated. Set
- * during initialisation. This is the maximum possible value that the
- * compare match register can hold divided by ulMatchValueForOneTick. */
- static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+ /* Holds the maximum number of ticks that can be suppressed - which is
+ basically how far into the future an interrupt can be generated. Set
+ during initialisation. This is the maximum possible value that the
+ compare match register can hold divided by ulMatchValueForOneTick. */
+ static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-/* Flag set from the tick interrupt to allow the sleep processing to know if
- * sleep mode was exited because of a tick interrupt, or an interrupt
- * generated by something else. */
- static volatile uint32_t ulTickFlag = pdFALSE;
+ /* Flag set from the tick interrupt to allow the sleep processing to know if
+ sleep mode was exited because of a tick interrupt, or an interrupt
+ generated by something else. */
+ static volatile uint32_t ulTickFlag = pdFALSE;
-/* The CMT counter is stopped temporarily each time it is re-programmed.
- * The following constant offsets the CMT counter match value by the number of
- * CMT counts that would typically be missed while the counter was stopped to
- * compensate for the lost time. The large difference between the divided CMT
- * clock and the CPU clock means it is likely ulStoppedTimerCompensation will
- * equal zero - and be optimised away. */
- static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
+ /* The CMT counter is stopped temporarily each time it is re-programmed.
+ The following constant offsets the CMT counter match value by the number of
+ CMT counts that would typically be missed while the counter was stopped to
+ compensate for the lost time. The large difference between the divided CMT
+ clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+ equal zero - and be optimised away. */
+ static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
-#endif /* if configUSE_TICKLESS_IDLE == 1 */
+#endif
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Offset to end up on 8 byte boundary. */
- pxTopOfStack--;
+ /* Offset to end up on 8 byte boundary. */
+ pxTopOfStack--;
- /* R0 is not included as it is the stack pointer. */
+ /* R0 is not included as it is the stack pointer. */
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
*pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
- /* When debugging it can be useful if every register is set to a known
- * value. Otherwise code space can be saved by just setting the registers
- * that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaabbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
- {
- /* Leave space for the registers that will get popped from the stack
- * when the task first starts executing. */
- pxTopOfStack -= 15;
- }
- #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaabbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ /* Leave space for the registers that will get popped from the stack
+ when the task first starts executing. */
+ pxTopOfStack -= 15;
+ }
+ #endif
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* Accumulator. */
- pxTopOfStack--;
- *pxTopOfStack = 0x87654321; /* Accumulator. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* Accumulator. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x87654321; /* Accumulator. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate
- * the tick interrupt. This way the application can decide which
- * peripheral to use. If tickless mode is used then the default
- * implementation defined in this file (which uses CMT0) should not be
- * overridden. */
- configSETUP_TICK_INTERRUPT();
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate
+ the tick interrupt. This way the application can decide which
+ peripheral to use. If tickless mode is used then the default
+ implementation defined in this file (which uses CMT0) should not be
+ overridden. */
+ configSETUP_TICK_INTERRUPT();
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the first task. */
- prvStartFirstTask();
- }
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
- /* Execution should not reach here as the tasks are now running!
- * prvSetupTimerInterrupt() is called here to prevent the compiler outputting
- * a warning about a statically declared function not being referenced in the
- * case that the application writer has provided their own tick interrupt
- * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
- * their own routine will be called in place of prvSetupTimerInterrupt()). */
- prvSetupTimerInterrupt();
+ /* Execution should not reach here as the tasks are now running!
+ prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+ a warning about a statically declared function not being referenced in the
+ case that the application writer has provided their own tick interrupt
+ configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+ their own routine will be called in place of prvSetupTimerInterrupt()). */
+ prvSetupTimerInterrupt();
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
#pragma vector = configTICK_VECTOR
__interrupt static void prvTickISR( void )
{
- /* Re-enable interrupts. */
- __enable_interrupt();
+ /* Re-enable interrupts. */
+ __enable_interrupt();
- /* Increment the tick, and perform any processing the new tick value
- * necessitates. */
- __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. */
+ __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
- #if configUSE_TICKLESS_IDLE == 1
- {
- /* The CPU woke because of a tick. */
- ulTickFlag = pdTRUE;
+ #if configUSE_TICKLESS_IDLE == 1
+ {
+ /* The CPU woke because of a tick. */
+ ulTickFlag = pdTRUE;
- /* If this is the first tick since exiting tickless mode then the CMT
- * compare match value needs resetting. */
- CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
- }
- #endif
+ /* If this is the first tick since exiting tickless mode then the CMT
+ compare match value needs resetting. */
+ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+ }
+ #endif
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- /* Unlock. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+ /* Unlock. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
- /* Enable CMT0. */
- MSTP( CMT0 ) = 0;
+ /* Enable CMT0. */
+ MSTP( CMT0 ) = 0;
- /* Lock again. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
+ /* Lock again. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
- /* Interrupt on compare match. */
- CMT0.CMCR.BIT.CMIE = 1;
+ /* Interrupt on compare match. */
+ CMT0.CMCR.BIT.CMIE = 1;
- /* Set the compare match value. */
- CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+ /* Set the compare match value. */
+ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
- /* Divide the PCLK. */
- #if portCLOCK_DIVISOR == 512
- {
- CMT0.CMCR.BIT.CKS = 3;
- }
- #elif portCLOCK_DIVISOR == 128
- {
- CMT0.CMCR.BIT.CKS = 2;
- }
- #elif portCLOCK_DIVISOR == 32
- {
- CMT0.CMCR.BIT.CKS = 1;
- }
- #elif portCLOCK_DIVISOR == 8
- {
- CMT0.CMCR.BIT.CKS = 0;
- }
- #else /* if portCLOCK_DIVISOR == 512 */
- {
- #error Invalid portCLOCK_DIVISOR setting
- }
- #endif /* if portCLOCK_DIVISOR == 512 */
+ /* Divide the PCLK. */
+ #if portCLOCK_DIVISOR == 512
+ {
+ CMT0.CMCR.BIT.CKS = 3;
+ }
+ #elif portCLOCK_DIVISOR == 128
+ {
+ CMT0.CMCR.BIT.CKS = 2;
+ }
+ #elif portCLOCK_DIVISOR == 32
+ {
+ CMT0.CMCR.BIT.CKS = 1;
+ }
+ #elif portCLOCK_DIVISOR == 8
+ {
+ CMT0.CMCR.BIT.CKS = 0;
+ }
+ #else
+ {
+ #error Invalid portCLOCK_DIVISOR setting
+ }
+ #endif
- /* Enable the interrupt... */
- _IEN( _CMT0_CMI0 ) = 1;
+ /* Enable the interrupt... */
+ _IEN( _CMT0_CMI0 ) = 1;
- /* ...and set its priority to the application defined kernel priority. */
- _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* ...and set its priority to the application defined kernel priority. */
+ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the timer. */
- CMT.CMSTR0.BIT.STR0 = 1;
+ /* Start the timer. */
+ CMT.CMSTR0.BIT.STR0 = 1;
}
/*-----------------------------------------------------------*/
#if configUSE_TICKLESS_IDLE == 1
- static void prvSleep( TickType_t xExpectedIdleTime )
- {
- /* Allow the application to define some pre-sleep processing. */
- configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
+ static void prvSleep( TickType_t xExpectedIdleTime )
+ {
+ /* Allow the application to define some pre-sleep processing. */
+ configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
- /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
- * means the application defined code has already executed the WAIT
- * instruction. */
- if( xExpectedIdleTime > 0 )
- {
- __wait_for_interrupt();
- }
+ /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
+ means the application defined code has already executed the WAIT
+ instruction. */
+ if( xExpectedIdleTime > 0 )
+ {
+ __wait_for_interrupt();
+ }
- /* Allow the application to define some post sleep processing. */
- configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
- }
+ /* Allow the application to define some post sleep processing. */
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
#if configUSE_TICKLESS_IDLE == 1
- void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
- {
- uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
- eSleepModeStatus eSleepAction;
+ void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+ eSleepModeStatus eSleepAction;
- /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
+ /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
- /* Make sure the CMT reload value does not overflow the counter. */
- if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
- {
- xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
- }
+ /* Make sure the CMT reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
- /* Calculate the reload value required to wait xExpectedIdleTime tick
- * periods. */
- ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+ /* Calculate the reload value required to wait xExpectedIdleTime tick
+ periods. */
+ ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+ if( ulMatchValue > ulStoppedTimerCompensation )
+ {
+ /* Compensate for the fact that the CMT is going to be stopped
+ momentarily. */
+ ulMatchValue -= ulStoppedTimerCompensation;
+ }
- if( ulMatchValue > ulStoppedTimerCompensation )
- {
- /* Compensate for the fact that the CMT is going to be stopped
- * momentarily. */
- ulMatchValue -= ulStoppedTimerCompensation;
- }
+ /* Stop the CMT momentarily. The time the CMT is stopped for is
+ accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ CMT.CMSTR0.BIT.STR0 = 0;
+ while( CMT.CMSTR0.BIT.STR0 == 1 )
+ {
+ /* Nothing to do here. */
+ }
- /* Stop the CMT momentarily. The time the CMT is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- CMT.CMSTR0.BIT.STR0 = 0;
+ /* Critical section using the global interrupt bit as the i bit is
+ automatically reset by the WAIT instruction. */
+ __disable_interrupt();
- while( CMT.CMSTR0.BIT.STR0 == 1 )
- {
- /* Nothing to do here. */
- }
+ /* The tick flag is set to false before sleeping. If it is true when
+ sleep mode is exited then sleep mode was probably exited because the
+ tick was suppressed for the entire xExpectedIdleTime period. */
+ ulTickFlag = pdFALSE;
- /* Critical section using the global interrupt bit as the i bit is
- * automatically reset by the WAIT instruction. */
- __disable_interrupt();
+ /* If a context switch is pending then abandon the low power entry as
+ the context switch might have been pended by an external interrupt that
+ requires processing. */
+ eSleepAction = eTaskConfirmSleepModeStatus();
+ if( eSleepAction == eAbortSleep )
+ {
+ /* Restart tick. */
+ CMT.CMSTR0.BIT.STR0 = 1;
+ __enable_interrupt();
+ }
+ else if( eSleepAction == eNoTasksWaitingTimeout )
+ {
+ /* Protection off. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
- /* The tick flag is set to false before sleeping. If it is true when
- * sleep mode is exited then sleep mode was probably exited because the
- * tick was suppressed for the entire xExpectedIdleTime period. */
- ulTickFlag = pdFALSE;
+ /* Ready for software standby with all clocks stopped. */
+ SYSTEM.SBYCR.BIT.SSBY = 1;
- /* If a context switch is pending then abandon the low power entry as
- * the context switch might have been pended by an external interrupt that
- * requires processing. */
- eSleepAction = eTaskConfirmSleepModeStatus();
+ /* Protection on. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
- if( eSleepAction == eAbortSleep )
- {
- /* Restart tick. */
- CMT.CMSTR0.BIT.STR0 = 1;
- __enable_interrupt();
- }
- else if( eSleepAction == eNoTasksWaitingTimeout )
- {
- /* Protection off. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+ /* Sleep until something happens. Calling prvSleep() will
+ automatically reset the i bit in the PSW. */
+ prvSleep( xExpectedIdleTime );
- /* Ready for software standby with all clocks stopped. */
- SYSTEM.SBYCR.BIT.SSBY = 1;
+ /* Restart the CMT. */
+ CMT.CMSTR0.BIT.STR0 = 1;
+ }
+ else
+ {
+ /* Protection off. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
- /* Protection on. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
+ /* Ready for deep sleep mode. */
+ SYSTEM.MSTPCRC.BIT.DSLPE = 1;
+ SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
+ SYSTEM.SBYCR.BIT.SSBY = 0;
- /* Sleep until something happens. Calling prvSleep() will
- * automatically reset the i bit in the PSW. */
- prvSleep( xExpectedIdleTime );
+ /* Protection on. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
- /* Restart the CMT. */
- CMT.CMSTR0.BIT.STR0 = 1;
- }
- else
- {
- /* Protection off. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+ /* Adjust the match value to take into account that the current
+ time slice is already partially complete. */
+ ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
- /* Ready for deep sleep mode. */
- SYSTEM.MSTPCRC.BIT.DSLPE = 1;
- SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
- SYSTEM.SBYCR.BIT.SSBY = 0;
+ /* Restart the CMT to count up to the new match value. */
+ CMT0.CMCNT = 0;
+ CMT.CMSTR0.BIT.STR0 = 1;
- /* Protection on. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
+ /* Sleep until something happens. Calling prvSleep() will
+ automatically reset the i bit in the PSW. */
+ prvSleep( xExpectedIdleTime );
- /* Adjust the match value to take into account that the current
- * time slice is already partially complete. */
- ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+ /* Stop CMT. Again, the time the SysTick is stopped for is
+ accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ CMT.CMSTR0.BIT.STR0 = 0;
+ while( CMT.CMSTR0.BIT.STR0 == 1 )
+ {
+ /* Nothing to do here. */
+ }
- /* Restart the CMT to count up to the new match value. */
- CMT0.CMCNT = 0;
- CMT.CMSTR0.BIT.STR0 = 1;
+ ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
- /* Sleep until something happens. Calling prvSleep() will
- * automatically reset the i bit in the PSW. */
- prvSleep( xExpectedIdleTime );
+ if( ulTickFlag != pdFALSE )
+ {
+ /* The tick interrupt has already executed, although because
+ this function is called with the scheduler suspended the actual
+ tick processing will not occur until after this function has
+ exited. Reset the match value with whatever remains of this
+ tick period. */
+ ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
- /* Stop CMT. Again, the time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- CMT.CMSTR0.BIT.STR0 = 0;
+ /* The tick interrupt handler will already have pended the tick
+ processing in the kernel. As the pending tick will be
+ processed as soon as this function exits, the tick value
+ maintained by the tick is stepped forward by one less than the
+ time spent sleeping. The actual stepping of the tick appears
+ later in this function. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep.
+ How many complete tick periods passed while the processor was
+ sleeping? */
+ ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
- while( CMT.CMSTR0.BIT.STR0 == 1 )
- {
- /* Nothing to do here. */
- }
+ /* The match value is set to whatever fraction of a single tick
+ period remains. */
+ ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+ }
- ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
+ /* Restart the CMT so it runs up to the match value. The match value
+ will get set to the value required to generate exactly one tick period
+ the next time the CMT interrupt executes. */
+ CMT0.CMCNT = 0;
+ CMT.CMSTR0.BIT.STR0 = 1;
- if( ulTickFlag != pdFALSE )
- {
- /* The tick interrupt has already executed, although because
- * this function is called with the scheduler suspended the actual
- * tick processing will not occur until after this function has
- * exited. Reset the match value with whatever remains of this
- * tick period. */
- ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
- /* The tick interrupt handler will already have pended the tick
- * processing in the kernel. As the pending tick will be
- * processed as soon as this function exits, the tick value
- * maintained by the tick is stepped forward by one less than the
- * time spent sleeping. The actual stepping of the tick appears
- * later in this function. */
- ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
- }
- else
- {
- /* Something other than the tick interrupt ended the sleep.
- * How many complete tick periods passed while the processor was
- * sleeping? */
- ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
-
- /* The match value is set to whatever fraction of a single tick
- * period remains. */
- ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
- }
-
- /* Restart the CMT so it runs up to the match value. The match value
- * will get set to the value required to generate exactly one tick period
- * the next time the CMT interrupt executes. */
- CMT0.CMCNT = 0;
- CMT.CMSTR0.BIT.STR0 = 1;
-
- /* Wind the tick forward by the number of tick periods that the CPU
- * remained in a low power state. */
- vTaskStepTick( ulCompleteTickPeriods );
- }
- }
+ /* Wind the tick forward by the number of tick periods that the CPU
+ remained in a low power state. */
+ vTaskStepTick( ulCompleteTickPeriods );
+ }
+ }
#endif /* configUSE_TICKLESS_IDLE */
+
diff --git a/portable/IAR/RX100/portmacro.h b/portable/IAR/RX100/portmacro.h
index 99da589..8e288e8 100644
--- a/portable/IAR/RX100/portmacro.h
+++ b/portable/IAR/RX100/portmacro.h
@@ -27,16 +27,16 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include <intrinsics.h>
+#include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Hardware specifics. */
- #include "machine.h"
+#include "machine.h"
/*-----------------------------------------------------------
* Port specific definitions.
@@ -49,101 +49,102 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() __no_operation()
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __no_operation()
- #define portYIELD() \
- __asm volatile \
- ( \
- "MOV.L #0x872E0, R15 \n"\
- "MOV.B #1, [R15] \n"\
- "MOV.L [R15], R15 \n"\
- ::: "R15" \
- )
+#define portYIELD() \
+ __asm volatile \
+ ( \
+ "MOV.L #0x872E0, R15 \n" \
+ "MOV.B #1, [R15] \n" \
+ "MOV.L [R15], R15 \n" \
+ ::: "R15" \
+ )
- #define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) { portYIELD(); }
+#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) { portYIELD(); }
/* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
- * functions are those that end in FromISR. FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
- #define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 )
- #ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #else
- #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #endif
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+ #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
- #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
/* Tickless idle/low power functionality. */
- #if configUSE_TICKLESS_IDLE == 1
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
- #endif
+#if configUSE_TICKLESS_IDLE == 1
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+#endif
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Prevent warnings of undefined behaviour: the order of volatile accesses is
- * undefined - all warnings have been manually checked and are not an issue, and
- * the warnings cannot be prevent by code changes without undesirable effects. */
- #pragma diag_suppress=Pa082
+undefined - all warnings have been manually checked and are not an issue, and
+the warnings cannot be prevent by code changes without undesirable effects. */
+#pragma diag_suppress=Pa082
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/RX600/port.c b/portable/IAR/RX600/port.c
index a413d01..45a7174 100644
--- a/portable/IAR/RX600/port.c
+++ b/portable/IAR/RX600/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the SH2A port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -42,9 +42,9 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
/*-----------------------------------------------------------*/
@@ -62,131 +62,132 @@
/*-----------------------------------------------------------*/
-extern void * pxCurrentTCB;
+extern void *pxCurrentTCB;
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* R0 is not included as it is the stack pointer. */
+ /* R0 is not included as it is the stack pointer. */
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
- /* When debugging it can be useful if every register is set to a known
- * value. Otherwise code space can be saved by just setting the registers
- * that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0xffffffff; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xeeeeeeee;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
- {
- pxTopOfStack -= 15;
- }
- #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0xffffffff; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xeeeeeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= 15;
+ }
+ #endif
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_FPSW;
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* Accumulator. */
- pxTopOfStack--;
- *pxTopOfStack = 0x87654321; /* Accumulator. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_FPSW;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* Accumulator. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x87654321; /* Accumulator. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate the
- * tick interrupt. This way the application can decide which peripheral to
- * use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the first task. */
- prvStartFirstTask();
- }
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
#pragma vector = configTICK_VECTOR
__interrupt void vTickISR( void )
{
- /* Re-enable interrupts. */
- __enable_interrupt();
+ /* Re-enable interrupts. */
+ __enable_interrupt();
- /* Increment the tick, and perform any processing the new tick value
- * necessitates. */
- __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. */
+ __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/IAR/RX600/portmacro.h b/portable/IAR/RX600/portmacro.h
index 3d30185..66963c9 100644
--- a/portable/IAR/RX600/portmacro.h
+++ b/portable/IAR/RX600/portmacro.h
@@ -27,13 +27,13 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include <intrinsics.h>
+#include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -46,93 +46,94 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() __no_operation()
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __no_operation()
/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
- * where portITU_SWINTR is the location of the software interrupt register
- * (0x000872E0). Don't rely on the assembler to select a register, so instead
- * save and restore clobbered registers manually. */
- #define portYIELD() \
- __asm volatile \
- ( \
- "PUSH.L R10 \n"\
- "MOV.L #0x872E0, R10 \n"\
- "MOV.B #0x1, [R10] \n"\
- "MOV.L [R10], R10 \n"\
- "POP R10 \n"\
- )
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0). Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD() \
+ __asm volatile \
+ ( \
+ "PUSH.L R10 \n" \
+ "MOV.L #0x872E0, R10 \n" \
+ "MOV.B #0x1, [R10] \n" \
+ "MOV.L [R10], R10 \n" \
+ "POP R10 \n" \
+ )
- #define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
- * functions are those that end in FromISR. FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
- #define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 )
- #ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #else
- #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #endif
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+ #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
- #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/RXv2/port.c b/portable/IAR/RXv2/port.c
index 267ef18..4024645 100644
--- a/portable/IAR/RXv2/port.c
+++ b/portable/IAR/RXv2/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the SH2A port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -42,9 +42,9 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
/*-----------------------------------------------------------*/
@@ -62,139 +62,140 @@
/*-----------------------------------------------------------*/
-extern void * pxCurrentTCB;
+extern void *pxCurrentTCB;
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* R0 is not included as it is the stack pointer. */
+ /* R0 is not included as it is the stack pointer. */
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
- /* When debugging it can be useful if every register is set to a known
- * value. Otherwise code space can be saved by just setting the registers
- * that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0xffffffff; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xeeeeeeee;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
- {
- pxTopOfStack -= 15;
- }
- #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0xffffffff; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xeeeeeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= 15;
+ }
+ #endif
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_FPSW;
- pxTopOfStack--;
- *pxTopOfStack = 0x11111111; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444; /* Accumulator 1. */
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555; /* Accumulator 1. */
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666; /* Accumulator 1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_FPSW;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11111111; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444; /* Accumulator 1. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555; /* Accumulator 1. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666; /* Accumulator 1. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate the
- * tick interrupt. This way the application can decide which peripheral to
- * use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the first task. */
- prvStartFirstTask();
- }
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
#pragma vector = configTICK_VECTOR
__interrupt void vTickISR( void )
{
- /* Re-enable interrupts. */
- __enable_interrupt();
+ /* Re-enable interrupts. */
+ __enable_interrupt();
- /* Increment the tick, and perform any processing the new tick value
- * necessitates. */
- __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. */
+ __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/IAR/RXv2/portmacro.h b/portable/IAR/RXv2/portmacro.h
index 354c1a9..dd9763b 100644
--- a/portable/IAR/RXv2/portmacro.h
+++ b/portable/IAR/RXv2/portmacro.h
@@ -27,13 +27,13 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include <intrinsics.h>
+#include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -46,98 +46,99 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() __no_operation()
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __no_operation()
/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
- * where portITU_SWINTR is the location of the software interrupt register
- * (0x000872E0). Don't rely on the assembler to select a register, so instead
- * save and restore clobbered registers manually. */
- #define portYIELD() \
- __asm volatile \
- ( \
- "PUSH.L R10 \n"\
- "MOV.L #0x872E0, R10 \n"\
- "MOV.B #0x1, [R10] \n"\
- "MOV.L [R10], R10 \n"\
- "POP R10 \n"\
- )
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0). Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD() \
+ __asm volatile \
+ ( \
+ "PUSH.L R10 \n" \
+ "MOV.L #0x872E0, R10 \n" \
+ "MOV.B #0x1, [R10] \n" \
+ "MOV.L [R10], R10 \n" \
+ "POP R10 \n" \
+ )
- #define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
- * functions are those that end in FromISR. FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
- #define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 )
- #ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #else
- #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #endif
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+ #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
- #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Prevent warnings of undefined behaviour: the order of volatile accesses is
- * undefined - all warnings have been manually checked and are not an issue, and
- * the warnings cannot be prevent by code changes without undesirable effects. */
- #pragma diag_suppress=Pa082
+undefined - all warnings have been manually checked and are not an issue, and
+the warnings cannot be prevent by code changes without undesirable effects. */
+#pragma diag_suppress=Pa082
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/IAR/STR71x/ISR_Support.h b/portable/IAR/STR71x/ISR_Support.h
index 72f4b15..360fff6 100644
--- a/portable/IAR/STR71x/ISR_Support.h
+++ b/portable/IAR/STR71x/ISR_Support.h
@@ -1,123 +1,105 @@
-; /*
- * ; * FreeRTOS Kernel V10.3.1
- * ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * ; *
- * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * ; * this software and associated documentation files (the "Software"), to deal in
- * ; * the Software without restriction, including without limitation the rights to
- * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * ; * the Software, and to permit persons to whom the Software is furnished to do so,
- * ; * subject to the following conditions:
- * ; *
- * ; * The above copyright notice and this permission notice shall be included in all
- * ; * copies or substantial portions of the Software.
- * ; *
- * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * ; *
- * ; * http://www.FreeRTOS.org
- * ; * http://aws.amazon.com/freertos
- * ; *
- * ; * 1 tab == 4 spaces!
- * ; */
+;/*
+; * FreeRTOS Kernel V10.3.1
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
-EXTERN pxCurrentTCB
-EXTERN ulCriticalNesting
+ EXTERN pxCurrentTCB
+ EXTERN ulCriticalNesting
-;
-Context save and restore macro definitions
-;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
-;
-Push R0 as we are going to use the register.
- STMDB SP !, { R0 }
+ ; Push R0 as we are going to use the register.
+ STMDB SP!, {R0}
-;
-Set R0 to point to the task stack pointer.
- STMDB SP, { SP } ^
-NOP
-SUB SP, SP, # 4
-LDMIA SP !, { R0 }
+ ; Set R0 to point to the task stack pointer.
+ STMDB SP, {SP}^
+ NOP
+ SUB SP, SP, #4
+ LDMIA SP!, {R0}
-;
-Push the return address onto the stack.
- STMDB R0 !, { LR }
+ ; Push the return address onto the stack.
+ STMDB R0!, {LR}
-;
+ ; Now we have saved LR we can use it instead of R0.
+ MOV LR, R0
-Now we have saved LR we can use it instead of R0.
- MOV LR, R0
+ ; Pop R0 so we can save it onto the system mode stack.
+ LDMIA SP!, {R0}
-;
-Pop R0 so we can save it onto the system mode stack.
- LDMIA SP !, { R0 }
+ ; Push all the system mode registers onto the task stack.
+ STMDB LR, {R0-LR}^
+ NOP
+ SUB LR, LR, #60
-;
-Push all the system mode registers onto the task stack.
- STMDB LR, { R0 - LR } ^
-NOP
-SUB LR, LR, # 60
+ ; Push the SPSR onto the task stack.
+ MRS R0, SPSR
+ STMDB LR!, {R0}
-;
-Push the SPSR onto the task stack.
- MRS R0, SPSR
-STMDB LR !, { R0 }
+ LDR R0, =ulCriticalNesting
+ LDR R0, [R0]
+ STMDB LR!, {R0}
-LDR R0, = ulCriticalNesting
- LDR R0, [ R0 ]
-STMDB LR !, { R0 }
+ ; Store the new top of stack for the task.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ STR LR, [R0]
-;
-Store the new top of stack for the task.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-STR LR, [ R0 ]
-
-ENDM
+ ENDM
portRESTORE_CONTEXT MACRO
-;
-Set the LR to the task stack.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-LDR LR, [ R0 ]
+ ; Set the LR to the task stack.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ LDR LR, [R0]
-;
-The critical nesting depth is the first item on the stack.
- ;
-Load it into the ulCriticalNesting variable.
- LDR R0, = ulCriticalNesting
- LDMFD LR !, { R1 }
-STR R1, [ R0 ]
+ ; The critical nesting depth is the first item on the stack.
+ ; Load it into the ulCriticalNesting variable.
+ LDR R0, =ulCriticalNesting
+ LDMFD LR!, {R1}
+ STR R1, [R0]
-;
-Get the SPSR from the stack.
- LDMFD LR !, { R0 }
-MSR SPSR_cxsf, R0
+ ; Get the SPSR from the stack.
+ LDMFD LR!, {R0}
+ MSR SPSR_cxsf, R0
-;
-Restore all system mode registers for the task.
- LDMFD LR, { R0 - R14 } ^
-NOP
+ ; Restore all system mode registers for the task.
+ LDMFD LR, {R0-R14}^
+ NOP
-;
-Restore the return address.
- LDR LR, [ LR, # + 60 ]
+ ; Restore the return address.
+ LDR LR, [LR, #+60]
-;
+ ; And return - correcting the offset in the LR to obtain the
+ ; correct address.
+ SUBS PC, LR, #4
-And return -correcting the offset in the LR to obtain the
-;
+ ENDM
-correct address.
- SUBS PC, LR, # 4
-
-ENDM
diff --git a/portable/IAR/STR71x/port.c b/portable/IAR/STR71x/port.c
index 96570d7..a285643 100644
--- a/portable/IAR/STR71x/port.c
+++ b/portable/IAR/STR71x/port.c
@@ -26,9 +26,9 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ST STR71x ARM7
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the ST STR71x ARM7
+ * port.
+ *----------------------------------------------------------*/
/* Library includes. */
#include "wdg.h"
@@ -42,14 +42,14 @@
#include "task.h"
/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-#define portMICROS_PER_SECOND 1000000
+#define portMICROS_PER_SECOND 1000000
/*-----------------------------------------------------------*/
@@ -57,13 +57,13 @@
static void prvSetupTimerInterrupt( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
- * cannot be initialised to 0 as this will cause interrupts to be enabled
- * during the kernel initialisation process. */
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
uint32_t ulCriticalNesting = ( uint32_t ) 9999;
/* Tick interrupt routines for cooperative and preemptive operation
- * respectively. The preemptive version is not defined as __irq as it is called
- * from an asm wrapper function. */
+respectively. The preemptive version is not defined as __irq as it is called
+from an asm wrapper function. */
__arm __irq void vPortNonPreemptiveTick( void );
void vPortPreemptiveTick( void );
@@ -75,180 +75,184 @@
*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The status register is set for system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* The status register is set for system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+
+ pxTopOfStack--;
- if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ /* Interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
-
- /* Interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortStartFirstTask();
+ /* Start the first task. */
+ vPortStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
/* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick. */
+simply increment the system tick. */
__arm __irq void vPortNonPreemptiveTick( void )
{
- /* Increment the tick count - which may wake some tasks but as the
- * preemptive scheduler is not being used any woken task is not given
- * processor time no matter what its priority. */
- xTaskIncrementTick();
+ /* Increment the tick count - which may wake some tasks but as the
+ preemptive scheduler is not being used any woken task is not given
+ processor time no matter what its priority. */
+ xTaskIncrementTick();
- /* Clear the interrupt in the watchdog and EIC. */
- WDG->SR = 0x0000;
- portCLEAR_EIC();
+ /* Clear the interrupt in the watchdog and EIC. */
+ WDG->SR = 0x0000;
+ portCLEAR_EIC();
}
/*-----------------------------------------------------------*/
/* This function is called from an asm wrapper, so does not require the __irq
- * keyword. */
+keyword. */
void vPortPreemptiveTick( void )
{
- /* Increment the tick counter. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Select a new task to execute. */
- vTaskSwitchContext();
- }
+ /* Increment the tick counter. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Select a new task to execute. */
+ vTaskSwitchContext();
+ }
- /* Clear the interrupt in the watchdog and EIC. */
- WDG->SR = 0x0000;
- portCLEAR_EIC();
+ /* Clear the interrupt in the watchdog and EIC. */
+ WDG->SR = 0x0000;
+ portCLEAR_EIC();
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- /* Set the watchdog up to generate a periodic tick. */
- WDG_ECITConfig( DISABLE );
- WDG_CntOnOffConfig( DISABLE );
- WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ );
+ /* Set the watchdog up to generate a periodic tick. */
+ WDG_ECITConfig( DISABLE );
+ WDG_CntOnOffConfig( DISABLE );
+ WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ );
- /* Setup the tick interrupt in the EIC. */
- EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 );
- EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE );
- EIC_IRQConfig( ENABLE );
- WDG_ECITConfig( ENABLE );
+ /* Setup the tick interrupt in the EIC. */
+ EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 );
+ EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE );
+ EIC_IRQConfig( ENABLE );
+ WDG_ECITConfig( ENABLE );
- /* Start the timer - interrupts are actually disabled at this point so
- * it is safe to do this here. */
- WDG_CntOnOffConfig( ENABLE );
+ /* Start the timer - interrupts are actually disabled at this point so
+ it is safe to do this here. */
+ WDG_CntOnOffConfig( ENABLE );
}
/*-----------------------------------------------------------*/
__arm __interwork void vPortEnterCritical( void )
{
- /* Disable interrupts first! */
- __disable_interrupt();
+ /* Disable interrupts first! */
+ __disable_interrupt();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
__arm __interwork void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- __enable_interrupt();
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ __enable_interrupt();
+ }
+ }
}
/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/portable/IAR/STR71x/portmacro.h b/portable/IAR/STR71x/portmacro.h
index 59b3526..ca2e3ba 100644
--- a/portable/IAR/STR71x/portmacro.h
+++ b/portable/IAR/STR71x/portmacro.h
@@ -27,7 +27,7 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
@@ -39,81 +39,83 @@
*-----------------------------------------------------------
*/
- #include <intrinsics.h>
+#include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portYIELD() asm ( "SWI 0" )
- #define portNOP() asm ( "NOP" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portYIELD() asm ( "SWI 0" )
+#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
- __arm __interwork void vPortDisableInterruptsFromThumb( void );
- __arm __interwork void vPortEnableInterruptsFromThumb( void );
- __arm __interwork void vPortEnterCritical( void );
- __arm __interwork void vPortExitCritical( void );
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() __disable_interrupt()
- #define portENABLE_INTERRUPTS() __enable_interrupt()
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() __disable_interrupt()
+#define portENABLE_INTERRUPTS() __enable_interrupt()
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern void vTaskSwitchContext( void ); \
- \
- if( xSwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+{ \
+extern void vTaskSwitchContext( void ); \
+ \
+ if( xSwitchRequired ) \
+ { \
+ vTaskSwitchContext(); \
+ } \
+}
/*-----------------------------------------------------------*/
/* EIC utilities. */
- #define portEIC_CICR_ADDR *( ( uint32_t * ) 0xFFFFF804 )
- #define portEIC_IPR_ADDR *( ( uint32_t * ) 0xFFFFF840 )
- #define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR
+#define portEIC_CICR_ADDR *( ( uint32_t * ) 0xFFFFF804 )
+#define portEIC_IPR_ADDR *( ( uint32_t * ) 0xFFFFF840 )
+#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
+
diff --git a/portable/IAR/STR75x/ISR_Support.h b/portable/IAR/STR75x/ISR_Support.h
index 72f4b15..360fff6 100644
--- a/portable/IAR/STR75x/ISR_Support.h
+++ b/portable/IAR/STR75x/ISR_Support.h
@@ -1,123 +1,105 @@
-; /*
- * ; * FreeRTOS Kernel V10.3.1
- * ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * ; *
- * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * ; * this software and associated documentation files (the "Software"), to deal in
- * ; * the Software without restriction, including without limitation the rights to
- * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * ; * the Software, and to permit persons to whom the Software is furnished to do so,
- * ; * subject to the following conditions:
- * ; *
- * ; * The above copyright notice and this permission notice shall be included in all
- * ; * copies or substantial portions of the Software.
- * ; *
- * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * ; *
- * ; * http://www.FreeRTOS.org
- * ; * http://aws.amazon.com/freertos
- * ; *
- * ; * 1 tab == 4 spaces!
- * ; */
+;/*
+; * FreeRTOS Kernel V10.3.1
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
-EXTERN pxCurrentTCB
-EXTERN ulCriticalNesting
+ EXTERN pxCurrentTCB
+ EXTERN ulCriticalNesting
-;
-Context save and restore macro definitions
-;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
-;
-Push R0 as we are going to use the register.
- STMDB SP !, { R0 }
+ ; Push R0 as we are going to use the register.
+ STMDB SP!, {R0}
-;
-Set R0 to point to the task stack pointer.
- STMDB SP, { SP } ^
-NOP
-SUB SP, SP, # 4
-LDMIA SP !, { R0 }
+ ; Set R0 to point to the task stack pointer.
+ STMDB SP, {SP}^
+ NOP
+ SUB SP, SP, #4
+ LDMIA SP!, {R0}
-;
-Push the return address onto the stack.
- STMDB R0 !, { LR }
+ ; Push the return address onto the stack.
+ STMDB R0!, {LR}
-;
+ ; Now we have saved LR we can use it instead of R0.
+ MOV LR, R0
-Now we have saved LR we can use it instead of R0.
- MOV LR, R0
+ ; Pop R0 so we can save it onto the system mode stack.
+ LDMIA SP!, {R0}
-;
-Pop R0 so we can save it onto the system mode stack.
- LDMIA SP !, { R0 }
+ ; Push all the system mode registers onto the task stack.
+ STMDB LR, {R0-LR}^
+ NOP
+ SUB LR, LR, #60
-;
-Push all the system mode registers onto the task stack.
- STMDB LR, { R0 - LR } ^
-NOP
-SUB LR, LR, # 60
+ ; Push the SPSR onto the task stack.
+ MRS R0, SPSR
+ STMDB LR!, {R0}
-;
-Push the SPSR onto the task stack.
- MRS R0, SPSR
-STMDB LR !, { R0 }
+ LDR R0, =ulCriticalNesting
+ LDR R0, [R0]
+ STMDB LR!, {R0}
-LDR R0, = ulCriticalNesting
- LDR R0, [ R0 ]
-STMDB LR !, { R0 }
+ ; Store the new top of stack for the task.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ STR LR, [R0]
-;
-Store the new top of stack for the task.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-STR LR, [ R0 ]
-
-ENDM
+ ENDM
portRESTORE_CONTEXT MACRO
-;
-Set the LR to the task stack.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-LDR LR, [ R0 ]
+ ; Set the LR to the task stack.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ LDR LR, [R0]
-;
-The critical nesting depth is the first item on the stack.
- ;
-Load it into the ulCriticalNesting variable.
- LDR R0, = ulCriticalNesting
- LDMFD LR !, { R1 }
-STR R1, [ R0 ]
+ ; The critical nesting depth is the first item on the stack.
+ ; Load it into the ulCriticalNesting variable.
+ LDR R0, =ulCriticalNesting
+ LDMFD LR!, {R1}
+ STR R1, [R0]
-;
-Get the SPSR from the stack.
- LDMFD LR !, { R0 }
-MSR SPSR_cxsf, R0
+ ; Get the SPSR from the stack.
+ LDMFD LR!, {R0}
+ MSR SPSR_cxsf, R0
-;
-Restore all system mode registers for the task.
- LDMFD LR, { R0 - R14 } ^
-NOP
+ ; Restore all system mode registers for the task.
+ LDMFD LR, {R0-R14}^
+ NOP
-;
-Restore the return address.
- LDR LR, [ LR, # + 60 ]
+ ; Restore the return address.
+ LDR LR, [LR, #+60]
-;
+ ; And return - correcting the offset in the LR to obtain the
+ ; correct address.
+ SUBS PC, LR, #4
-And return -correcting the offset in the LR to obtain the
-;
+ ENDM
-correct address.
- SUBS PC, LR, # 4
-
-ENDM
diff --git a/portable/IAR/STR75x/port.c b/portable/IAR/STR75x/port.c
index fe0fbd2..20b4a35 100644
--- a/portable/IAR/STR75x/port.c
+++ b/portable/IAR/STR75x/port.c
@@ -26,9 +26,9 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ST STR75x ARM7
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the ST STR75x ARM7
+ * port.
+ *----------------------------------------------------------*/
/* Library includes. */
#include "75x_tb.h"
@@ -39,14 +39,14 @@
#include "task.h"
/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* Prescale used on the timer clock when calculating the tick period. */
-#define portPRESCALE 20
+#define portPRESCALE 20
/*-----------------------------------------------------------*/
@@ -55,8 +55,8 @@
static void prvSetupTimerInterrupt( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
- * cannot be initialised to 0 as this will cause interrupts to be enabled
- * during the kernel initialisation process. */
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
uint32_t ulCriticalNesting = ( uint32_t ) 9999;
/* Tick interrupt routines for preemptive operation. */
@@ -70,164 +70,168 @@
*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The status register is set for system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- pxTopOfStack--;
+ /* The status register is set for system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ pxTopOfStack--;
- /* Interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
+ /* Interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortStartFirstTask();
+ /* Start the first task. */
+ vPortStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
__arm void vPortPreemptiveTick( void )
{
- /* Increment the tick counter. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Select a new task to execute. */
- vTaskSwitchContext();
- }
-
- TB_ClearITPendingBit( TB_IT_Update );
+ /* Increment the tick counter. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Select a new task to execute. */
+ vTaskSwitchContext();
+ }
+
+ TB_ClearITPendingBit( TB_IT_Update );
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- EIC_IRQInitTypeDef EIC_IRQInitStructure;
- TB_InitTypeDef TB_InitStructure;
+EIC_IRQInitTypeDef EIC_IRQInitStructure;
+TB_InitTypeDef TB_InitStructure;
- /* Setup the EIC for the TB. */
- EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
- EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
- EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
- EIC_IRQInit( &EIC_IRQInitStructure );
+ /* Setup the EIC for the TB. */
+ EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
+ EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
+ EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
+ EIC_IRQInit(&EIC_IRQInitStructure);
+
+ /* Setup the TB for the generation of the tick interrupt. */
+ TB_InitStructure.TB_Mode = TB_Mode_Timing;
+ TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
+ TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
+ TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
+ TB_Init(&TB_InitStructure);
+
+ /* Enable TB Update interrupt */
+ TB_ITConfig(TB_IT_Update, ENABLE);
- /* Setup the TB for the generation of the tick interrupt. */
- TB_InitStructure.TB_Mode = TB_Mode_Timing;
- TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
- TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
- TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
- TB_Init( &TB_InitStructure );
+ /* Clear TB Update interrupt pending bit */
+ TB_ClearITPendingBit(TB_IT_Update);
- /* Enable TB Update interrupt */
- TB_ITConfig( TB_IT_Update, ENABLE );
-
- /* Clear TB Update interrupt pending bit */
- TB_ClearITPendingBit( TB_IT_Update );
-
- /* Enable TB */
- TB_Cmd( ENABLE );
+ /* Enable TB */
+ TB_Cmd(ENABLE);
}
/*-----------------------------------------------------------*/
__arm __interwork void vPortEnterCritical( void )
{
- /* Disable interrupts first! */
- __disable_interrupt();
+ /* Disable interrupts first! */
+ __disable_interrupt();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
__arm __interwork void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- __enable_interrupt();
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ __enable_interrupt();
+ }
+ }
}
/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/portable/IAR/STR75x/portmacro.h b/portable/IAR/STR75x/portmacro.h
index 21f11ca..f9a8a1e 100644
--- a/portable/IAR/STR75x/portmacro.h
+++ b/portable/IAR/STR75x/portmacro.h
@@ -27,7 +27,7 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
@@ -39,72 +39,74 @@
*-----------------------------------------------------------
*/
- #include <intrinsics.h>
+#include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portYIELD() asm ( "SWI 0" )
- #define portNOP() asm ( "NOP" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portYIELD() asm ( "SWI 0" )
+#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
- __arm __interwork void vPortEnterCritical( void );
- __arm __interwork void vPortExitCritical( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() __disable_interrupt()
- #define portENABLE_INTERRUPTS() __enable_interrupt()
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() __disable_interrupt()
+#define portENABLE_INTERRUPTS() __enable_interrupt()
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern void vTaskSwitchContext( void ); \
- \
- if( xSwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+{ \
+extern void vTaskSwitchContext( void ); \
+ \
+ if( xSwitchRequired ) \
+ { \
+ vTaskSwitchContext(); \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
+
diff --git a/portable/IAR/STR91x/ISR_Support.h b/portable/IAR/STR91x/ISR_Support.h
index 3352160..c4a12a2 100644
--- a/portable/IAR/STR91x/ISR_Support.h
+++ b/portable/IAR/STR91x/ISR_Support.h
@@ -25,99 +25,81 @@
* 1 tab == 4 spaces!
*/
-EXTERN pxCurrentTCB
-EXTERN ulCriticalNesting
+ EXTERN pxCurrentTCB
+ EXTERN ulCriticalNesting
-;
-Context save and restore macro definitions
-;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
-;
-Push R0 as we are going to use the register.
- STMDB SP !, { R0 }
+ ; Push R0 as we are going to use the register.
+ STMDB SP!, {R0}
-;
-Set R0 to point to the task stack pointer.
- STMDB SP, { SP } ^
-NOP
-SUB SP, SP, # 4
-LDMIA SP !, { R0 }
+ ; Set R0 to point to the task stack pointer.
+ STMDB SP, {SP}^
+ NOP
+ SUB SP, SP, #4
+ LDMIA SP!, {R0}
-;
-Push the return address onto the stack.
- STMDB R0 !, { LR }
+ ; Push the return address onto the stack.
+ STMDB R0!, {LR}
-;
+ ; Now we have saved LR we can use it instead of R0.
+ MOV LR, R0
-Now we have saved LR we can use it instead of R0.
- MOV LR, R0
+ ; Pop R0 so we can save it onto the system mode stack.
+ LDMIA SP!, {R0}
-;
-Pop R0 so we can save it onto the system mode stack.
- LDMIA SP !, { R0 }
+ ; Push all the system mode registers onto the task stack.
+ STMDB LR, {R0-LR}^
+ NOP
+ SUB LR, LR, #60
-;
-Push all the system mode registers onto the task stack.
- STMDB LR, { R0 - LR } ^
-NOP
-SUB LR, LR, # 60
+ ; Push the SPSR onto the task stack.
+ MRS R0, SPSR
+ STMDB LR!, {R0}
-;
-Push the SPSR onto the task stack.
- MRS R0, SPSR
-STMDB LR !, { R0 }
+ LDR R0, =ulCriticalNesting
+ LDR R0, [R0]
+ STMDB LR!, {R0}
-LDR R0, = ulCriticalNesting
- LDR R0, [ R0 ]
-STMDB LR !, { R0 }
+ ; Store the new top of stack for the task.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ STR LR, [R0]
-;
-Store the new top of stack for the task.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-STR LR, [ R0 ]
-
-ENDM
+ ENDM
portRESTORE_CONTEXT MACRO
-;
-Set the LR to the task stack.
- LDR R1, = pxCurrentTCB
- LDR R0, [ R1 ]
-LDR LR, [ R0 ]
+ ; Set the LR to the task stack.
+ LDR R1, =pxCurrentTCB
+ LDR R0, [R1]
+ LDR LR, [R0]
-;
-The critical nesting depth is the first item on the stack.
- ;
-Load it into the ulCriticalNesting variable.
- LDR R0, = ulCriticalNesting
- LDMFD LR !, { R1 }
-STR R1, [ R0 ]
+ ; The critical nesting depth is the first item on the stack.
+ ; Load it into the ulCriticalNesting variable.
+ LDR R0, =ulCriticalNesting
+ LDMFD LR!, {R1}
+ STR R1, [R0]
-;
-Get the SPSR from the stack.
- LDMFD LR !, { R0 }
-MSR SPSR_cxsf, R0
+ ; Get the SPSR from the stack.
+ LDMFD LR!, {R0}
+ MSR SPSR_cxsf, R0
-;
-Restore all system mode registers for the task.
- LDMFD LR, { R0 - R14 } ^
-NOP
+ ; Restore all system mode registers for the task.
+ LDMFD LR, {R0-R14}^
+ NOP
-;
-Restore the return address.
- LDR LR, [ LR, # + 60 ]
+ ; Restore the return address.
+ LDR LR, [LR, #+60]
-;
+ ; And return - correcting the offset in the LR to obtain the
+ ; correct address.
+ SUBS PC, LR, #4
-And return -correcting the offset in the LR to obtain the
-;
+ ENDM
-correct address.
- SUBS PC, LR, # 4
-
-ENDM
diff --git a/portable/IAR/STR91x/port.c b/portable/IAR/STR91x/port.c
index 5e643e4..7d4ad1d 100644
--- a/portable/IAR/STR91x/port.c
+++ b/portable/IAR/STR91x/port.c
@@ -26,9 +26,9 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ST STR91x ARM9
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the ST STR91x ARM9
+ * port.
+ *----------------------------------------------------------*/
/* Library includes. */
#include "91x_lib.h"
@@ -42,23 +42,23 @@
#include "task.h"
#ifndef configUSE_WATCHDOG_TICK
- #error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively.
+ #error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively.
#endif
/* Constants required to setup the initial stack. */
#ifndef _RUN_TASK_IN_ARM_MODE_
- #define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
+ #define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
#else
- #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+ #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
#endif
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
#ifndef abs
- #define abs( x ) ( ( x ) > 0 ? ( x ) : -( x ) )
+ #define abs(x) ((x)>0 ? (x) : -(x))
#endif
/**
@@ -73,15 +73,15 @@
* }
*
*/
-#define TOGGLE_LED( port, pin ) \
- if( ( ( ( ( port )->DR[ ( pin ) << 2 ] ) ) & ( pin ) ) != Bit_RESET ) \
- { \
- ( port )->DR[ ( pin ) << 2 ] = 0x00; \
- } \
- else \
- { \
- ( port )->DR[ ( pin ) << 2 ] = ( pin ); \
- }
+#define TOGGLE_LED(port,pin) \
+ if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) \
+ { \
+ (port)->DR[(pin) <<2] = 0x00; \
+ } \
+ else \
+ { \
+ (port)->DR[(pin) <<2] = (pin); \
+ }
/*-----------------------------------------------------------*/
@@ -90,21 +90,21 @@
static void prvSetupTimerInterrupt( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
- * cannot be initialised to 0 as this will cause interrupts to be enabled
- * during the kernel initialisation process. */
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
uint32_t ulCriticalNesting = ( uint32_t ) 9999;
/* Tick interrupt routines for cooperative and preemptive operation
- * respectively. The preemptive version is not defined as __irq as it is called
- * from an asm wrapper function. */
+respectively. The preemptive version is not defined as __irq as it is called
+from an asm wrapper function. */
void WDG_IRQHandler( void );
/* VIC interrupt default handler. */
static void prvDefaultHandler( void );
#if configUSE_WATCHDOG_TICK == 0
- /* Used to update the OCR timer register */
- static u16 s_nPulseLength;
+ /* Used to update the OCR timer register */
+ static u16 s_nPulseLength;
#endif
/*-----------------------------------------------------------*/
@@ -115,286 +115,268 @@
*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+ StackType_t *pxOriginalTOS;
- pxOriginalTOS = pxTopOfStack;
+ pxOriginalTOS = pxTopOfStack;
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The status register is set for system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- pxTopOfStack--;
+ /* The status register is set for system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ pxTopOfStack--;
- /* Interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
+ /* Interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortStartFirstTask();
+ /* Start the first task. */
+ vPortStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
}
/*-----------------------------------------------------------*/
/* This function is called from an asm wrapper, so does not require the __irq
- * keyword. */
+keyword. */
#if configUSE_WATCHDOG_TICK == 1
- static void prvFindFactors( u32 n,
- u16 * a,
- u32 * b )
- {
- /* This function is copied from the ST STR7 library and is
- * copyright STMicroelectronics. Reproduced with permission. */
+ static void prvFindFactors(u32 n, u16 *a, u32 *b)
+ {
+ /* This function is copied from the ST STR7 library and is
+ copyright STMicroelectronics. Reproduced with permission. */
+
+ u32 b0;
+ u16 a0;
+ int32_t err, err_min=n;
+
+ *a = a0 = ((n-1)/65536ul) + 1;
+ *b = b0 = n / *a;
+
+ for (; *a <= 256; (*a)++)
+ {
+ *b = n / *a;
+ err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+ if (abs(err) > (*a / 2))
+ {
+ (*b)++;
+ err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+ }
+ if (abs(err) < abs(err_min))
+ {
+ err_min = err;
+ a0 = *a;
+ b0 = *b;
+ if (err == 0) break;
+ }
+ }
+
+ *a = a0;
+ *b = b0;
+ }
+ /*-----------------------------------------------------------*/
- u32 b0;
- u16 a0;
- int32_t err, err_min = n;
+ static void prvSetupTimerInterrupt( void )
+ {
+ WDG_InitTypeDef xWdg;
+ uint16_t a;
+ uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
+
+ /* Configure the watchdog as a free running timer that generates a
+ periodic interrupt. */
+
+ SCU_APBPeriphClockConfig( __WDG, ENABLE );
+ WDG_DeInit();
+ WDG_StructInit(&xWdg);
+ prvFindFactors( n, &a, &b );
+ xWdg.WDG_Prescaler = a - 1;
+ xWdg.WDG_Preload = b - 1;
+ WDG_Init( &xWdg );
+ WDG_ITConfig(ENABLE);
+
+ /* Configure the VIC for the WDG interrupt. */
+ VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
+ VIC_ITCmd( WDG_ITLine, ENABLE );
+
+ /* Install the default handlers for both VIC's. */
+ VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
+ VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
+
+ WDG_Cmd(ENABLE);
+ }
+ /*-----------------------------------------------------------*/
- *a = a0 = ( ( n - 1 ) / 65536ul ) + 1;
- *b = b0 = n / *a;
+ void WDG_IRQHandler( void )
+ {
+ {
+ /* Increment the tick counter. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Select a new task to execute. */
+ vTaskSwitchContext();
+ }
+
+ /* Clear the interrupt in the watchdog. */
+ WDG->SR &= ~0x0001;
+ }
+ }
- for( ; *a <= 256; ( *a )++ )
- {
- *b = n / *a;
- err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n;
+#else
- if( abs( err ) > ( *a / 2 ) )
- {
- ( *b )++;
- err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n;
- }
+ static void prvFindFactors(u32 n, u8 *a, u16 *b)
+ {
+ /* This function is copied from the ST STR7 library and is
+ copyright STMicroelectronics. Reproduced with permission. */
+
+ u16 b0;
+ u8 a0;
+ int32_t err, err_min=n;
+
+
+ *a = a0 = ((n-1)/256) + 1;
+ *b = b0 = n / *a;
+
+ for (; *a <= 256; (*a)++)
+ {
+ *b = n / *a;
+ err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+ if (abs(err) > (*a / 2))
+ {
+ (*b)++;
+ err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+ }
+ if (abs(err) < abs(err_min))
+ {
+ err_min = err;
+ a0 = *a;
+ b0 = *b;
+ if (err == 0) break;
+ }
+ }
+
+ *a = a0;
+ *b = b0;
+ }
+ /*-----------------------------------------------------------*/
- if( abs( err ) < abs( err_min ) )
- {
- err_min = err;
- a0 = *a;
- b0 = *b;
+ static void prvSetupTimerInterrupt( void )
+ {
+ uint8_t a;
+ uint16_t b;
+ uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
+
+ TIM_InitTypeDef timer;
+
+ SCU_APBPeriphClockConfig( __TIM23, ENABLE );
+ TIM_DeInit(TIM2);
+ TIM_StructInit(&timer);
+ prvFindFactors( n, &a, &b );
+
+ timer.TIM_Mode = TIM_OCM_CHANNEL_1;
+ timer.TIM_OC1_Modes = TIM_TIMING;
+ timer.TIM_Clock_Source = TIM_CLK_APB;
+ timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING;
+ timer.TIM_Prescaler = a-1;
+ timer.TIM_Pulse_Level_1 = TIM_HIGH;
+ timer.TIM_Pulse_Length_1 = s_nPulseLength = b-1;
+
+ TIM_Init (TIM2, &timer);
+ TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE);
+ /* Configure the VIC for the WDG interrupt. */
+ VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
+ VIC_ITCmd( TIM2_ITLine, ENABLE );
+
+ /* Install the default handlers for both VIC's. */
+ VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
+ VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
+
+ TIM_CounterCmd(TIM2, TIM_CLEAR);
+ TIM_CounterCmd(TIM2, TIM_START);
+ }
+ /*-----------------------------------------------------------*/
- if( err == 0 )
- {
- break;
- }
- }
- }
-
- *a = a0;
- *b = b0;
- }
- /*-----------------------------------------------------------*/
-
- static void prvSetupTimerInterrupt( void )
- {
- WDG_InitTypeDef xWdg;
- uint16_t a;
- uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
-
- /* Configure the watchdog as a free running timer that generates a
- * periodic interrupt. */
-
- SCU_APBPeriphClockConfig( __WDG, ENABLE );
- WDG_DeInit();
- WDG_StructInit( &xWdg );
- prvFindFactors( n, &a, &b );
- xWdg.WDG_Prescaler = a - 1;
- xWdg.WDG_Preload = b - 1;
- WDG_Init( &xWdg );
- WDG_ITConfig( ENABLE );
-
- /* Configure the VIC for the WDG interrupt. */
- VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
- VIC_ITCmd( WDG_ITLine, ENABLE );
-
- /* Install the default handlers for both VIC's. */
- VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
- VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
-
- WDG_Cmd( ENABLE );
- }
- /*-----------------------------------------------------------*/
-
- void WDG_IRQHandler( void )
- {
- {
- /* Increment the tick counter. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Select a new task to execute. */
- vTaskSwitchContext();
- }
-
- /* Clear the interrupt in the watchdog. */
- WDG->SR &= ~0x0001;
- }
- }
-
-#else /* if configUSE_WATCHDOG_TICK == 1 */
-
- static void prvFindFactors( u32 n,
- u8 * a,
- u16 * b )
- {
- /* This function is copied from the ST STR7 library and is
- * copyright STMicroelectronics. Reproduced with permission. */
-
- u16 b0;
- u8 a0;
- int32_t err, err_min = n;
-
-
- *a = a0 = ( ( n - 1 ) / 256 ) + 1;
- *b = b0 = n / *a;
-
- for( ; *a <= 256; ( *a )++ )
- {
- *b = n / *a;
- err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n;
-
- if( abs( err ) > ( *a / 2 ) )
- {
- ( *b )++;
- err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n;
- }
-
- if( abs( err ) < abs( err_min ) )
- {
- err_min = err;
- a0 = *a;
- b0 = *b;
-
- if( err == 0 )
- {
- break;
- }
- }
- }
-
- *a = a0;
- *b = b0;
- }
- /*-----------------------------------------------------------*/
-
- static void prvSetupTimerInterrupt( void )
- {
- uint8_t a;
- uint16_t b;
- uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
-
- TIM_InitTypeDef timer;
-
- SCU_APBPeriphClockConfig( __TIM23, ENABLE );
- TIM_DeInit( TIM2 );
- TIM_StructInit( &timer );
- prvFindFactors( n, &a, &b );
-
- timer.TIM_Mode = TIM_OCM_CHANNEL_1;
- timer.TIM_OC1_Modes = TIM_TIMING;
- timer.TIM_Clock_Source = TIM_CLK_APB;
- timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING;
- timer.TIM_Prescaler = a - 1;
- timer.TIM_Pulse_Level_1 = TIM_HIGH;
- timer.TIM_Pulse_Length_1 = s_nPulseLength = b - 1;
-
- TIM_Init( TIM2, &timer );
- TIM_ITConfig( TIM2, TIM_IT_OC1, ENABLE );
- /* Configure the VIC for the WDG interrupt. */
- VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
- VIC_ITCmd( TIM2_ITLine, ENABLE );
-
- /* Install the default handlers for both VIC's. */
- VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
- VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
-
- TIM_CounterCmd( TIM2, TIM_CLEAR );
- TIM_CounterCmd( TIM2, TIM_START );
- }
- /*-----------------------------------------------------------*/
-
- void TIM2_IRQHandler( void )
- {
- /* Reset the timer counter to avioid overflow. */
- TIM2->OC1R += s_nPulseLength;
-
- /* Increment the tick counter. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Select a new task to run. */
- vTaskSwitchContext();
- }
-
- /* Clear the interrupt in the watchdog. */
- TIM2->SR &= ~TIM_FLAG_OC1;
- }
+ void TIM2_IRQHandler( void )
+ {
+ /* Reset the timer counter to avioid overflow. */
+ TIM2->OC1R += s_nPulseLength;
+
+ /* Increment the tick counter. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Select a new task to run. */
+ vTaskSwitchContext();
+ }
+
+ /* Clear the interrupt in the watchdog. */
+ TIM2->SR &= ~TIM_FLAG_OC1;
+ }
#endif /* USE_WATCHDOG_TICK */
@@ -402,33 +384,38 @@
__arm __interwork void vPortEnterCritical( void )
{
- /* Disable interrupts first! */
- portDISABLE_INTERRUPTS();
+ /* Disable interrupts first! */
+ portDISABLE_INTERRUPTS();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
__arm __interwork void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- portENABLE_INTERRUPTS();
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ }
}
/*-----------------------------------------------------------*/
static void prvDefaultHandler( void )
{
}
+
+
+
+
+
diff --git a/portable/IAR/STR91x/portmacro.h b/portable/IAR/STR91x/portmacro.h
index 010d39e..3f800ba 100644
--- a/portable/IAR/STR91x/portmacro.h
+++ b/portable/IAR/STR91x/portmacro.h
@@ -27,7 +27,7 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
@@ -39,74 +39,76 @@
*-----------------------------------------------------------
*/
- #include <intrinsics.h>
+#include <intrinsics.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portYIELD() asm ( "SWI 0" )
- #define portNOP() asm ( "NOP" )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portYIELD() asm ( "SWI 0" )
+#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
- __arm __interwork void vPortEnterCritical( void );
- __arm __interwork void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
- #define portDISABLE_INTERRUPTS() __disable_interrupt()
- #define portENABLE_INTERRUPTS() __enable_interrupt()
+#define portDISABLE_INTERRUPTS() __disable_interrupt()
+#define portENABLE_INTERRUPTS() __enable_interrupt()
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern void vTaskSwitchContext( void ); \
- \
- if( xSwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+{ \
+extern void vTaskSwitchContext( void ); \
+ \
+ if( xSwitchRequired ) \
+ { \
+ vTaskSwitchContext(); \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
+
diff --git a/portable/IAR/V850ES/ISR_Support.h b/portable/IAR/V850ES/ISR_Support.h
index 7a1361e..d3822fb 100644
--- a/portable/IAR/V850ES/ISR_Support.h
+++ b/portable/IAR/V850ES/ISR_Support.h
@@ -25,142 +25,125 @@
* 1 tab == 4 spaces!
*/
-EXTERN pxCurrentTCB
-EXTERN usCriticalNesting
+ EXTERN pxCurrentTCB
+ EXTERN usCriticalNesting
#include "FreeRTOSConfig.h"
-;
-Context save and restore macro definitions
-;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
- add - 0x0C, sp;
-prepare stack to save necessary values
-st.w lp, 8[ sp ];
-store LP to stack
- stsr 0, r31
- st.w lp, 4[ sp ];
-store EIPC to stack
- stsr 1, lp
- st.w lp, 0[ sp ];
-store EIPSW to stack
-#if configDATA_MODE == 1; Using the Tiny data model
- prepare { r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30 }, 76, sp;
- save general purpose registers
- sst.w r19, 72[ ep ]
- sst.w r18, 68[ ep ]
- sst.w r17, 64[ ep ]
- sst.w r16, 60[ ep ]
- sst.w r15, 56[ ep ]
- sst.w r14, 52[ ep ]
- sst.w r13, 48[ ep ]
- sst.w r12, 44[ ep ]
- sst.w r11, 40[ ep ]
- sst.w r10, 36[ ep ]
- sst.w r9, 32[ ep ]
- sst.w r8, 28[ ep ]
- sst.w r7, 24[ ep ]
- sst.w r6, 20[ ep ]
- sst.w r5, 16[ ep ]
- sst.w r4, 12[ ep ]
-#else; Using the Small / Large data model
- prepare { r20, r21, r22, r23, r24, r26, r27, r28, r29, r30 }, 72, sp;
- save general purpose registers
- sst.w r19, 68[ ep ]
- sst.w r18, 64[ ep ]
- sst.w r17, 60[ ep ]
- sst.w r16, 56[ ep ]
- sst.w r15, 52[ ep ]
- sst.w r14, 48[ ep ]
- sst.w r13, 44[ ep ]
- sst.w r12, 40[ ep ]
- sst.w r11, 36[ ep ]
- sst.w r10, 32[ ep ]
- sst.w r9, 28[ ep ]
- sst.w r8, 24[ ep ]
- sst.w r7, 20[ ep ]
- sst.w r6, 16[ ep ]
- sst.w r5, 12[ ep ]
+ add -0x0C,sp ; prepare stack to save necessary values
+ st.w lp,8[sp] ; store LP to stack
+ stsr 0,r31
+ st.w lp,4[sp] ; store EIPC to stack
+ stsr 1,lp
+ st.w lp,0[sp] ; store EIPSW to stack
+#if configDATA_MODE == 1 ; Using the Tiny data model
+ prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
+ sst.w r19,72[ep]
+ sst.w r18,68[ep]
+ sst.w r17,64[ep]
+ sst.w r16,60[ep]
+ sst.w r15,56[ep]
+ sst.w r14,52[ep]
+ sst.w r13,48[ep]
+ sst.w r12,44[ep]
+ sst.w r11,40[ep]
+ sst.w r10,36[ep]
+ sst.w r9,32[ep]
+ sst.w r8,28[ep]
+ sst.w r7,24[ep]
+ sst.w r6,20[ep]
+ sst.w r5,16[ep]
+ sst.w r4,12[ep]
+#else ; Using the Small/Large data model
+ prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers
+ sst.w r19,68[ep]
+ sst.w r18,64[ep]
+ sst.w r17,60[ep]
+ sst.w r16,56[ep]
+ sst.w r15,52[ep]
+ sst.w r14,48[ep]
+ sst.w r13,44[ep]
+ sst.w r12,40[ep]
+ sst.w r11,36[ep]
+ sst.w r10,32[ep]
+ sst.w r9,28[ep]
+ sst.w r8,24[ep]
+ sst.w r7,20[ep]
+ sst.w r6,16[ep]
+ sst.w r5,12[ep]
#endif /* configDATA_MODE */
-sst.w r2, 8[ ep ]
-sst.w r1, 4[ ep ]
-MOVHI hi1( usCriticalNesting ), r0, r1;
-save usCriticalNesting value to stack
-ld.w lw1( usCriticalNesting )[ r1 ], r2
-sst.w r2, 0[ ep ]
-MOVHI hi1( pxCurrentTCB ), r0, r1;
-save SP to top of current TCB
-ld.w lw1( pxCurrentTCB )[ r1 ], r2
-st.w sp, 0[ r2 ]
-ENDM
+ sst.w r2,8[ep]
+ sst.w r1,4[ep]
+ MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack
+ ld.w lw1(usCriticalNesting)[r1],r2
+ sst.w r2,0[ep]
+ MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB
+ ld.w lw1(pxCurrentTCB)[r1],r2
+ st.w sp,0[r2]
+ ENDM
portRESTORE_CONTEXT MACRO
-MOVHI hi1( pxCurrentTCB ), r0, r1;
-get Stackpointer address
-ld.w lw1( pxCurrentTCB )[ r1 ], sp
-MOV sp, r1
-ld.w 0[ r1 ], sp;
-load stackpointer
-MOV sp, ep;
-set stack pointer to element pointer
-sld.w 0[ ep ], r1;
-load usCriticalNesting value from stack
-MOVHI hi1( usCriticalNesting ), r0, r2
-st.w r1, lw1( usCriticalNesting )[ r2 ]
-sld.w 4[ ep ], r1;
-restore general purpose registers
-sld.w 8[ ep ], r2
-#if configDATA_MODE == 1; Using Tiny data model
- sld.w 12[ ep ], r4
- sld.w 16[ ep ], r5
- sld.w 20[ ep ], r6
- sld.w 24[ ep ], r7
- sld.w 28[ ep ], r8
- sld.w 32[ ep ], r9
- sld.w 36[ ep ], r10
- sld.w 40[ ep ], r11
- sld.w 44[ ep ], r12
- sld.w 48[ ep ], r13
- sld.w 52[ ep ], r14
- sld.w 56[ ep ], r15
- sld.w 60[ ep ], r16
- sld.w 64[ ep ], r17
- sld.w 68[ ep ], r18
- sld.w 72[ ep ], r19
- dispose 76, { r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30 }
-#else; Using Small / Large data model
- sld.w 12[ ep ], r5
- sld.w 16[ ep ], r6
- sld.w 20[ ep ], r7
- sld.w 24[ ep ], r8
- sld.w 28[ ep ], r9
- sld.w 32[ ep ], r10
- sld.w 36[ ep ], r11
- sld.w 40[ ep ], r12
- sld.w 44[ ep ], r13
- sld.w 48[ ep ], r14
- sld.w 52[ ep ], r15
- sld.w 56[ ep ], r16
- sld.w 60[ ep ], r17
- sld.w 64[ ep ], r18
- sld.w 68[ ep ], r19
- dispose 72, { r20, r21, r22, r23, r24, r26, r27, r28, r29, r30 }
+ MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address
+ ld.w lw1(pxCurrentTCB)[r1],sp
+ MOV sp,r1
+ ld.w 0[r1],sp ; load stackpointer
+ MOV sp,ep ; set stack pointer to element pointer
+ sld.w 0[ep],r1 ; load usCriticalNesting value from stack
+ MOVHI hi1(usCriticalNesting),r0,r2
+ st.w r1,lw1(usCriticalNesting)[r2]
+ sld.w 4[ep],r1 ; restore general purpose registers
+ sld.w 8[ep],r2
+#if configDATA_MODE == 1 ; Using Tiny data model
+ sld.w 12[ep],r4
+ sld.w 16[ep],r5
+ sld.w 20[ep],r6
+ sld.w 24[ep],r7
+ sld.w 28[ep],r8
+ sld.w 32[ep],r9
+ sld.w 36[ep],r10
+ sld.w 40[ep],r11
+ sld.w 44[ep],r12
+ sld.w 48[ep],r13
+ sld.w 52[ep],r14
+ sld.w 56[ep],r15
+ sld.w 60[ep],r16
+ sld.w 64[ep],r17
+ sld.w 68[ep],r18
+ sld.w 72[ep],r19
+ dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
+#else ; Using Small/Large data model
+ sld.w 12[ep],r5
+ sld.w 16[ep],r6
+ sld.w 20[ep],r7
+ sld.w 24[ep],r8
+ sld.w 28[ep],r9
+ sld.w 32[ep],r10
+ sld.w 36[ep],r11
+ sld.w 40[ep],r12
+ sld.w 44[ep],r13
+ sld.w 48[ep],r14
+ sld.w 52[ep],r15
+ sld.w 56[ep],r16
+ sld.w 60[ep],r17
+ sld.w 64[ep],r18
+ sld.w 68[ep],r19
+ dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
#endif /* configDATA_MODE */
-ld.w 0[ sp ], lp;
-restore EIPSW from stack
-ldsr lp, 1
-ld.w 4[ sp ], lp;
-restore EIPC from stack
-ldsr lp, 0
-ld.w 8[ sp ], lp;
-restore LP from stack
- add 0x0C, sp;
-set SP to right position
+ ld.w 0[sp],lp ; restore EIPSW from stack
+ ldsr lp,1
+ ld.w 4[sp],lp ; restore EIPC from stack
+ ldsr lp,0
+ ld.w 8[sp],lp ; restore LP from stack
+ add 0x0C,sp ; set SP to right position
-RETI
+ RETI
-ENDM
+ ENDM
diff --git a/portable/IAR/V850ES/port.c b/portable/IAR/V850ES/port.c
index 0b2c2d5..82a36fd 100644
--- a/portable/IAR/V850ES/port.c
+++ b/portable/IAR/V850ES/port.c
@@ -33,14 +33,14 @@
#include "task.h"
/* Critical nesting should be initialised to a non zero value so interrupts don't
- * accidentally get enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING ( ( StackType_t ) 10 )
+accidentally get enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING (( StackType_t ) 10)
/* The PSW value assigned to tasks when they start to run for the first time. */
-#define portPSW ( ( StackType_t ) 0x00000000 )
+#define portPSW (( StackType_t ) 0x00000000)
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
@@ -52,106 +52,104 @@
static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */
- pxTopOfStack--;
- *pxTopOfStack = portPSW; /* Initial PSW value */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x20202020; /* Initial Value of R20 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x21212121; /* Initial Value of R21 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R22 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x23232323; /* Initial Value of R23 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 */
- pxTopOfStack--;
- #if ( __DATA_MODEL__ == 0 ) || ( __DATA_MODEL__ == 1 )
- *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */
- pxTopOfStack--;
- #endif /* configDATA_MODE */
- *pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x27272727; /* Initial Value of R27 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x28282828; /* Initial Value of R28 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x29292929; /* Initial Value of R29 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x30303030; /* Initial Value of R30 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19191919; /* Initial Value of R19 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18181818; /* Initial Value of R18 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x17171717; /* Initial Value of R17 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x16161616; /* Initial Value of R16 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15151515; /* Initial Value of R15 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14141414; /* Initial Value of R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x13131313; /* Initial Value of R13 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* Initial Value of R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* Initial Value of R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* Initial Value of R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x99999999; /* Initial Value of R09 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x88888888; /* Initial Value of R08 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x77777777; /* Initial Value of R07 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x66666666; /* Initial Value of R06 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x55555555; /* Initial Value of R05 */
- pxTopOfStack--;
- #if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1
- *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */
- pxTopOfStack--;
- #endif /* configDATA_MODE */
- *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R02 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 is expected to hold the function parameter*/
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */
+ pxTopOfStack--;
+ *pxTopOfStack = portPSW; /* Initial PSW value */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x20202020; /* Initial Value of R20 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x21212121; /* Initial Value of R21 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R22 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x23232323; /* Initial Value of R23 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 */
+ pxTopOfStack--;
+#if (__DATA_MODEL__ == 0) || (__DATA_MODEL__ == 1)
+ *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */
+ pxTopOfStack--;
+#endif /* configDATA_MODE */
+ *pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x27272727; /* Initial Value of R27 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x28282828; /* Initial Value of R28 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x29292929; /* Initial Value of R29 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x30303030; /* Initial Value of R30 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x19191919; /* Initial Value of R19 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x18181818; /* Initial Value of R18 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x17171717; /* Initial Value of R17 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x16161616; /* Initial Value of R16 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x15151515; /* Initial Value of R15 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x14141414; /* Initial Value of R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x13131313; /* Initial Value of R13 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* Initial Value of R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* Initial Value of R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* Initial Value of R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x99999999; /* Initial Value of R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x88888888; /* Initial Value of R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x77777777; /* Initial Value of R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x66666666; /* Initial Value of R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x55555555; /* Initial Value of R05 */
+ pxTopOfStack--;
+#if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1
+ *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */
+ pxTopOfStack--;
+#endif /* configDATA_MODE */
+ *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R02 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 is expected to hold the function parameter*/
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
- /*
- * Return a pointer to the top of the stack we have generated so this can
- * be stored in the task control block for the task.
- */
- return pxTopOfStack;
+ /*
+ * Return a pointer to the top of the stack we have generated so this can
+ * be stored in the task control block for the task.
+ */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- * this function is called. */
- prvSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called. */
+ prvSetupTimerInterrupt();
- /* Restore the context of the first task that is going to run. */
- vPortStart();
+ /* Restore the context of the first task that is going to run. */
+ vPortStart();
- /* Should not get here as the tasks are now running! */
- return pdTRUE;
+ /* Should not get here as the tasks are now running! */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the V850ES/Fx3 port will get stopped. If required simply
- * disable the tick interrupt here. */
+ /* It is unlikely that the V850ES/Fx3 port will get stopped. If required simply
+ disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
@@ -160,24 +158,26 @@
*/
static void prvSetupTimerInterrupt( void )
{
- TM0CE = 0; /* TMM0 operation disable */
- TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */
- TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
+ TM0CE = 0; /* TMM0 operation disable */
+ TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */
+ TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
- #ifdef __IAR_V850ES_Fx3__
- {
- TM0CMP0 = ( ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / 2 ) - 1 ); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
- }
- #else
- {
- TM0CMP0 = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
- }
- #endif
+ #ifdef __IAR_V850ES_Fx3__
+ {
+ TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
+ }
+ #else
+ {
+ TM0CMP0 = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
+ }
+ #endif
- TM0EQIC0 &= 0xF8;
- TM0CTL0 = 0x00;
- TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
- TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */
- TM0CE = 1; /* TMM0 operation enable */
+ TM0EQIC0 &= 0xF8;
+ TM0CTL0 = 0x00;
+ TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
+ TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */
+ TM0CE = 1; /* TMM0 operation enable */
}
/*-----------------------------------------------------------*/
+
+
diff --git a/portable/IAR/V850ES/portmacro.h b/portable/IAR/V850ES/portmacro.h
index f0a5871..0b661e8 100644
--- a/portable/IAR/V850ES/portmacro.h
+++ b/portable/IAR/V850ES/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,92 +43,93 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE unsigned int
- #define portBASE_TYPE int
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE unsigned int
+#define portBASE_TYPE int
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if (configUSE_16_BIT_TICKS==1)
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
- #define portDISABLE_INTERRUPTS() __asm( "DI" )
- #define portENABLE_INTERRUPTS() __asm( "EI" )
+#define portDISABLE_INTERRUPTS() __asm ( "DI" )
+#define portENABLE_INTERRUPTS() __asm ( "EI" )
/*-----------------------------------------------------------*/
/* Critical section control macros. */
- #define portNO_CRITICAL_SECTION_NESTING ( ( UBaseType_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( UBaseType_t ) 0 )
- #define portENTER_CRITICAL() \
- { \
- extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
- #define portEXIT_CRITICAL() \
- { \
- extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
- extern void vPortYield( void );
- extern void vPortStart( void );
- extern void portSAVE_CONTEXT( void );
- extern void portRESTORE_CONTEXT( void );
- #define portYIELD() __asm( "trap 0" )
- #define portNOP() __asm( "NOP" )
- extern void vTaskSwitchContext( void );
- #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+extern void vPortYield( void );
+extern void vPortStart( void );
+extern void portSAVE_CONTEXT( void );
+extern void portRESTORE_CONTEXT( void );
+#define portYIELD() __asm ( "trap 0" )
+#define portNOP() __asm ( "NOP" )
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
/*-----------------------------------------------------------*/
/* Hardwware specifics. */
- #define portBYTE_ALIGNMENT 4
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/MPLAB/PIC18F/port.c b/portable/MPLAB/PIC18F/port.c
index f85f5b7..6f76d46 100644
--- a/portable/MPLAB/PIC18F/port.c
+++ b/portable/MPLAB/PIC18F/port.c
@@ -25,34 +25,34 @@
* 1 tab == 4 spaces!
*/
-/*
- * Changes between V1.2.4 and V1.2.5
- *
- + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
- + interrupt flag setting. Using the two bits defined within
- + portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
- + before the test was performed.
- +
- + Changes from V1.2.5
- +
- + Set the interrupt vector address to 0x08. Previously it was at the
- + incorrect address for compatibility mode of 0x18.
- +
- + Changes from V2.1.1
- +
- + PCLATU and PCLATH are now saved as part of the context. This allows
- + function pointers to be used within tasks. Thanks to Javier Espeche
- + for the enhancement.
- +
- + Changes from V2.3.1
- +
- + TABLAT is now saved as part of the task context.
- +
- + Changes from V3.2.0
- +
- + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
- + value and does not write to the register.
- */
+/*
+Changes between V1.2.4 and V1.2.5
+
+ + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
+ interrupt flag setting. Using the two bits defined within
+ portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
+ before the test was performed.
+
+Changes from V1.2.5
+
+ + Set the interrupt vector address to 0x08. Previously it was at the
+ incorrect address for compatibility mode of 0x18.
+
+Changes from V2.1.1
+
+ + PCLATU and PCLATH are now saved as part of the context. This allows
+ function pointers to be used within tasks. Thanks to Javier Espeche
+ for the enhancement.
+
+Changes from V2.3.1
+
+ + TABLAT is now saved as part of the task context.
+
+Changes from V3.2.0
+
+ + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
+ value and does not write to the register.
+*/
/* Scheduler include files. */
#include "FreeRTOS.h"
@@ -62,37 +62,37 @@
#include "timers.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PIC port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PIC port.
+ *----------------------------------------------------------*/
/* Hardware setup for tick. */
-#define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
+#define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
/* Initial interrupt enable state for newly created tasks. This value is
- * copied into INTCON when a task switches in for the first time. */
-#define portINITAL_INTERRUPT_STATE 0xc0
+copied into INTCON when a task switches in for the first time. */
+#define portINITAL_INTERRUPT_STATE 0xc0
/* Just the bit within INTCON for the global interrupt flag. */
-#define portGLOBAL_INTERRUPT_FLAG 0x80
+#define portGLOBAL_INTERRUPT_FLAG 0x80
-/* Constant used for context switch macro when we require the interrupt
- * enable state to be unchanged when the interrupted task is switched back in. */
-#define portINTERRUPTS_UNCHANGED 0x00
+/* Constant used for context switch macro when we require the interrupt
+enable state to be unchanged when the interrupted task is switched back in. */
+#define portINTERRUPTS_UNCHANGED 0x00
/* Some memory areas get saved as part of the task context. These memory
- * area's get used by the compiler for temporary storage, especially when
- * performing mathematical operations, or when using 32bit data types. This
- * constant defines the size of memory area which must be saved. */
-#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
+area's get used by the compiler for temporary storage, especially when
+performing mathematical operations, or when using 32bit data types. This
+constant defines the size of memory area which must be saved. */
+#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/* IO port constants. */
-#define portBIT_SET ( ( uint8_t ) 1 )
-#define portBIT_CLEAR ( ( uint8_t ) 0 )
+#define portBIT_SET ( ( uint8_t ) 1 )
+#define portBIT_CLEAR ( ( uint8_t ) 0 )
/*
* The serial port ISR's are defined in serial.c, but are called from portable
@@ -106,7 +106,7 @@
*/
static void prvSetupTimerInterrupt( void );
-/*
+/*
* ISR to maintain the tick, and perform tick context switches if the
* preemptive scheduler is being used.
*/
@@ -118,13 +118,13 @@
*/
static void prvLowInterrupt( void );
-/*
+/*
* Macro that pushes all the registers that make up the context of a task onto
* the stack, then saves the new top of stack into the TCB.
- *
- * If this is called from an ISR then the interrupt enable bits must have been
+ *
+ * If this is called from an ISR then the interrupt enable bits must have been
* set for the ISR to ever get called. Therefore we want to save the INTCON
- * register with the enable bits forced to be set - and ucForcedInterruptFlags
+ * register with the enable bits forced to be set - and ucForcedInterruptFlags
* must contain these bit settings. This means the interrupts will again be
* enabled when the interrupted task is switched back in.
*
@@ -137,362 +137,360 @@
* storage during math and other computations. This is especially true if
* 32bit data types are utilised (as they are by the scheduler). The .tmpdata
* and MATH_DATA sections have to be stored in there entirety as part of a task
- * context. This macro stores from data address 0x00 to
- * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
- * applications but you should check the map file for your project to ensure
- * this is sufficient for your needs. It is not clear whether this size is
+ * context. This macro stores from data address 0x00 to
+ * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
+ * applications but you should check the map file for your project to ensure
+ * this is sufficient for your needs. It is not clear whether this size is
* fixed for all compilations or has the potential to be program specific.
*/
-#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
- { \
- _asm \
- /* Save the status and WREG registers first, as these will get modified \
- * by the operations below. */ \
- MOVFF WREG, PREINC1 \
- MOVFF STATUS, PREINC1 \
- /* Save the INTCON register with the appropriate bits forced if \
- * necessary - as described above. */ \
- MOVFF INTCON, WREG \
- IORLW ucForcedInterruptFlags \
- MOVFF WREG, PREINC1 \
- _endasm \
- \
- portDISABLE_INTERRUPTS(); \
- \
- _asm \
- /* Store the necessary registers to the stack. */ \
- MOVFF BSR, PREINC1 \
- MOVFF FSR2L, PREINC1 \
- MOVFF FSR2H, PREINC1 \
- MOVFF FSR0L, PREINC1 \
- MOVFF FSR0H, PREINC1 \
- MOVFF TABLAT, PREINC1 \
- MOVFF TBLPTRU, PREINC1 \
- MOVFF TBLPTRH, PREINC1 \
- MOVFF TBLPTRL, PREINC1 \
- MOVFF PRODH, PREINC1 \
- MOVFF PRODL, PREINC1 \
- MOVFF PCLATU, PREINC1 \
- MOVFF PCLATH, PREINC1 \
- /* Store the .tempdata and MATH_DATA areas as described above. */ \
- CLRF FSR0L, 0 \
- CLRF FSR0H, 0 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF POSTINC0, PREINC1 \
- MOVFF INDF0, PREINC1 \
- MOVFF FSR0L, PREINC1 \
- MOVFF FSR0H, PREINC1 \
- /* Store the hardware stack pointer in a temp register before we \
- * modify it. */ \
- MOVFF STKPTR, FSR0L \
- _endasm \
- \
- /* Store each address from the hardware stack. */ \
- while( STKPTR > ( uint8_t ) 0 ) \
- { \
- _asm \
- MOVFF TOSL, PREINC1 \
- MOVFF TOSH, PREINC1 \
- MOVFF TOSU, PREINC1 \
- POP \
- _endasm \
- } \
- \
- _asm \
- /* Store the number of addresses on the hardware stack (from the \
- * temporary register). */ \
- MOVFF FSR0L, PREINC1 \
- MOVF PREINC1, 1, 0 \
- _endasm \
- \
- /* Save the new top of the software stack in the TCB. */ \
- _asm \
- MOVFF pxCurrentTCB, FSR0L \
- MOVFF pxCurrentTCB + 1, FSR0H \
- MOVFF FSR1L, POSTINC0 \
- MOVFF FSR1H, POSTINC0 \
- _endasm \
- }
+#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
+{ \
+ _asm \
+ /* Save the status and WREG registers first, as these will get modified \
+ by the operations below. */ \
+ MOVFF WREG, PREINC1 \
+ MOVFF STATUS, PREINC1 \
+ /* Save the INTCON register with the appropriate bits forced if \
+ necessary - as described above. */ \
+ MOVFF INTCON, WREG \
+ IORLW ucForcedInterruptFlags \
+ MOVFF WREG, PREINC1 \
+ _endasm \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ _asm \
+ /* Store the necessary registers to the stack. */ \
+ MOVFF BSR, PREINC1 \
+ MOVFF FSR2L, PREINC1 \
+ MOVFF FSR2H, PREINC1 \
+ MOVFF FSR0L, PREINC1 \
+ MOVFF FSR0H, PREINC1 \
+ MOVFF TABLAT, PREINC1 \
+ MOVFF TBLPTRU, PREINC1 \
+ MOVFF TBLPTRH, PREINC1 \
+ MOVFF TBLPTRL, PREINC1 \
+ MOVFF PRODH, PREINC1 \
+ MOVFF PRODL, PREINC1 \
+ MOVFF PCLATU, PREINC1 \
+ MOVFF PCLATH, PREINC1 \
+ /* Store the .tempdata and MATH_DATA areas as described above. */ \
+ CLRF FSR0L, 0 \
+ CLRF FSR0H, 0 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF POSTINC0, PREINC1 \
+ MOVFF INDF0, PREINC1 \
+ MOVFF FSR0L, PREINC1 \
+ MOVFF FSR0H, PREINC1 \
+ /* Store the hardware stack pointer in a temp register before we \
+ modify it. */ \
+ MOVFF STKPTR, FSR0L \
+ _endasm \
+ \
+ /* Store each address from the hardware stack. */ \
+ while( STKPTR > ( uint8_t ) 0 ) \
+ { \
+ _asm \
+ MOVFF TOSL, PREINC1 \
+ MOVFF TOSH, PREINC1 \
+ MOVFF TOSU, PREINC1 \
+ POP \
+ _endasm \
+ } \
+ \
+ _asm \
+ /* Store the number of addresses on the hardware stack (from the \
+ temporary register). */ \
+ MOVFF FSR0L, PREINC1 \
+ MOVF PREINC1, 1, 0 \
+ _endasm \
+ \
+ /* Save the new top of the software stack in the TCB. */ \
+ _asm \
+ MOVFF pxCurrentTCB, FSR0L \
+ MOVFF pxCurrentTCB + 1, FSR0H \
+ MOVFF FSR1L, POSTINC0 \
+ MOVFF FSR1H, POSTINC0 \
+ _endasm \
+}
/*-----------------------------------------------------------*/
/*
* This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
* details.
*/
-#define portRESTORE_CONTEXT() \
- { \
- _asm \
- /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
- MOVFF pxCurrentTCB, FSR0L \
- MOVFF pxCurrentTCB + 1, FSR0H \
- \
- /* De-reference FSR0 to set the address it holds into FSR1. \
- * (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
- MOVFF POSTINC0, FSR1L \
- MOVFF POSTINC0, FSR1H \
- \
- /* How many return addresses are there on the hardware stack? Discard \
- * the first byte as we are pointing to the next free space. */ \
- MOVFF POSTDEC1, FSR0L \
- MOVFF POSTDEC1, FSR0L \
- _endasm \
- \
- /* Fill the hardware stack from our software stack. */ \
- STKPTR = 0; \
- \
- while( STKPTR < FSR0L ) \
- { \
- _asm \
- PUSH \
- MOVF POSTDEC1, 0, 0 \
- MOVWF TOSU, 0 \
- MOVF POSTDEC1, 0, 0 \
- MOVWF TOSH, 0 \
- MOVF POSTDEC1, 0, 0 \
- MOVWF TOSL, 0 \
- _endasm \
- } \
- \
- _asm \
- /* Restore the .tmpdata and MATH_DATA memory. */ \
- MOVFF POSTDEC1, FSR0H \
- MOVFF POSTDEC1, FSR0L \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, POSTDEC0 \
- MOVFF POSTDEC1, INDF0 \
- /* Restore the other registers forming the tasks context. */ \
- MOVFF POSTDEC1, PCLATH \
- MOVFF POSTDEC1, PCLATU \
- MOVFF POSTDEC1, PRODL \
- MOVFF POSTDEC1, PRODH \
- MOVFF POSTDEC1, TBLPTRL \
- MOVFF POSTDEC1, TBLPTRH \
- MOVFF POSTDEC1, TBLPTRU \
- MOVFF POSTDEC1, TABLAT \
- MOVFF POSTDEC1, FSR0H \
- MOVFF POSTDEC1, FSR0L \
- MOVFF POSTDEC1, FSR2H \
- MOVFF POSTDEC1, FSR2L \
- MOVFF POSTDEC1, BSR \
- /* The next byte is the INTCON register. Read this into WREG as some \
- * manipulation is required. */ \
- MOVFF POSTDEC1, WREG \
- _endasm \
- \
- /* From the INTCON register, only the interrupt enable bits form part \
- * of the tasks context. It is perfectly legitimate for another task to \
- * have modified any other bits. We therefore only restore the top two bits. \
- */ \
- if( WREG &portGLOBAL_INTERRUPT_FLAG ) \
- { \
- _asm \
- MOVFF POSTDEC1, STATUS \
- MOVFF POSTDEC1, WREG \
- /* Return enabling interrupts. */ \
- RETFIE 0 \
- _endasm \
- } \
- else \
- { \
- _asm \
- MOVFF POSTDEC1, STATUS \
- MOVFF POSTDEC1, WREG \
- /* Return without effecting interrupts. The context may have \
- * been saved from a critical region. */ \
- RETURN 0 \
- _endasm \
- } \
- }
+#define portRESTORE_CONTEXT() \
+{ \
+ _asm \
+ /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
+ MOVFF pxCurrentTCB, FSR0L \
+ MOVFF pxCurrentTCB + 1, FSR0H \
+ \
+ /* De-reference FSR0 to set the address it holds into FSR1. \
+ (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
+ MOVFF POSTINC0, FSR1L \
+ MOVFF POSTINC0, FSR1H \
+ \
+ /* How many return addresses are there on the hardware stack? Discard \
+ the first byte as we are pointing to the next free space. */ \
+ MOVFF POSTDEC1, FSR0L \
+ MOVFF POSTDEC1, FSR0L \
+ _endasm \
+ \
+ /* Fill the hardware stack from our software stack. */ \
+ STKPTR = 0; \
+ \
+ while( STKPTR < FSR0L ) \
+ { \
+ _asm \
+ PUSH \
+ MOVF POSTDEC1, 0, 0 \
+ MOVWF TOSU, 0 \
+ MOVF POSTDEC1, 0, 0 \
+ MOVWF TOSH, 0 \
+ MOVF POSTDEC1, 0, 0 \
+ MOVWF TOSL, 0 \
+ _endasm \
+ } \
+ \
+ _asm \
+ /* Restore the .tmpdata and MATH_DATA memory. */ \
+ MOVFF POSTDEC1, FSR0H \
+ MOVFF POSTDEC1, FSR0L \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, POSTDEC0 \
+ MOVFF POSTDEC1, INDF0 \
+ /* Restore the other registers forming the tasks context. */ \
+ MOVFF POSTDEC1, PCLATH \
+ MOVFF POSTDEC1, PCLATU \
+ MOVFF POSTDEC1, PRODL \
+ MOVFF POSTDEC1, PRODH \
+ MOVFF POSTDEC1, TBLPTRL \
+ MOVFF POSTDEC1, TBLPTRH \
+ MOVFF POSTDEC1, TBLPTRU \
+ MOVFF POSTDEC1, TABLAT \
+ MOVFF POSTDEC1, FSR0H \
+ MOVFF POSTDEC1, FSR0L \
+ MOVFF POSTDEC1, FSR2H \
+ MOVFF POSTDEC1, FSR2L \
+ MOVFF POSTDEC1, BSR \
+ /* The next byte is the INTCON register. Read this into WREG as some \
+ manipulation is required. */ \
+ MOVFF POSTDEC1, WREG \
+ _endasm \
+ \
+ /* From the INTCON register, only the interrupt enable bits form part \
+ of the tasks context. It is perfectly legitimate for another task to \
+ have modified any other bits. We therefore only restore the top two bits. \
+ */ \
+ if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
+ { \
+ _asm \
+ MOVFF POSTDEC1, STATUS \
+ MOVFF POSTDEC1, WREG \
+ /* Return enabling interrupts. */ \
+ RETFIE 0 \
+ _endasm \
+ } \
+ else \
+ { \
+ _asm \
+ MOVFF POSTDEC1, STATUS \
+ MOVFF POSTDEC1, WREG \
+ /* Return without effecting interrupts. The context may have \
+ been saved from a critical region. */ \
+ RETURN 0 \
+ _endasm \
+ } \
+}
/*-----------------------------------------------------------*/
-/*
- * See header file for description.
+/*
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint32_t ulAddress;
- uint8_t ucBlock;
+uint32_t ulAddress;
+uint8_t ucBlock;
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging. */
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
- *pxTopOfStack = 0x11;
- pxTopOfStack++;
- *pxTopOfStack = 0x22;
- pxTopOfStack++;
- *pxTopOfStack = 0x33;
- pxTopOfStack++;
+ *pxTopOfStack = 0x11;
+ pxTopOfStack++;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack++;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack++;
- /* Simulate how the stack would look after a call to vPortYield() generated
- * by the compiler.
- *
- * First store the function parameters. This is where the task will expect to
- * find them when it starts running. */
- ulAddress = ( uint32_t ) pvParameters;
- *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
- pxTopOfStack++;
+ /* Simulate how the stack would look after a call to vPortYield() generated
+ by the compiler.
- ulAddress >>= 8;
- *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
- pxTopOfStack++;
+ First store the function parameters. This is where the task will expect to
+ find them when it starts running. */
+ ulAddress = ( uint32_t ) pvParameters;
+ *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+ pxTopOfStack++;
- /* Next we just leave a space. When a context is saved the stack pointer
- * is incremented before it is used so as not to corrupt whatever the stack
- * pointer is actually pointing to. This is especially necessary during
- * function epilogue code generated by the compiler. */
- *pxTopOfStack = 0x44;
- pxTopOfStack++;
+ ulAddress >>= 8;
+ *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+ pxTopOfStack++;
- /* Next are all the registers that form part of the task context. */
+ /* Next we just leave a space. When a context is saved the stack pointer
+ is incremented before it is used so as not to corrupt whatever the stack
+ pointer is actually pointing to. This is especially necessary during
+ function epilogue code generated by the compiler. */
+ *pxTopOfStack = 0x44;
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
- pxTopOfStack++;
+ /* Next are all the registers that form part of the task context. */
+
+ *pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
+ pxTopOfStack++;
- /* INTCON is saved with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
- pxTopOfStack++;
+ /* INTCON is saved with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
+ pxTopOfStack++;
- /* Next the .tmpdata and MATH_DATA sections. */
- for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
- {
- *pxTopOfStack = ( StackType_t ) ucBlock;
- *pxTopOfStack++;
- }
+ /* Next the .tmpdata and MATH_DATA sections. */
+ for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
+ {
+ *pxTopOfStack = ( StackType_t ) ucBlock;
+ *pxTopOfStack++;
+ }
- /* Store the top of the global data section. */
- *pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
- pxTopOfStack++;
+ /* Store the top of the global data section. */
+ *pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
+ pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) 0x00; /* High. */
- pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* High. */
+ pxTopOfStack++;
- /* The only function return address so far is the address of the
- * task. */
- ulAddress = ( uint32_t ) pxCode;
+ /* The only function return address so far is the address of the
+ task. */
+ ulAddress = ( uint32_t ) pxCode;
- /* TOS low. */
- *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
- pxTopOfStack++;
- ulAddress >>= 8;
+ /* TOS low. */
+ *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+ pxTopOfStack++;
+ ulAddress >>= 8;
- /* TOS high. */
- *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
- pxTopOfStack++;
- ulAddress >>= 8;
+ /* TOS high. */
+ *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+ pxTopOfStack++;
+ ulAddress >>= 8;
- /* TOS even higher. */
- *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
- pxTopOfStack++;
+ /* TOS even higher. */
+ *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+ pxTopOfStack++;
- /* Store the number of return addresses on the hardware stack - so far only
- * the address of the task entry point. */
- *pxTopOfStack = ( StackType_t ) 1;
- pxTopOfStack++;
+ /* Store the number of return addresses on the hardware stack - so far only
+ the address of the task entry point. */
+ *pxTopOfStack = ( StackType_t ) 1;
+ pxTopOfStack++;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup a timer for the tick ISR is using the preemptive scheduler. */
- prvSetupTimerInterrupt();
+ /* Setup a timer for the tick ISR is using the preemptive scheduler. */
+ prvSetupTimerInterrupt();
- /* Restore the context of the first task to run. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the first task to run. */
+ portRESTORE_CONTEXT();
- /* Should not get here. Use the function name to stop compiler warnings. */
- ( void ) prvLowInterrupt;
- ( void ) prvTickISR;
+ /* Should not get here. Use the function name to stop compiler warnings. */
+ ( void ) prvLowInterrupt;
+ ( void ) prvTickISR;
- return pdTRUE;
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the scheduler for the PIC port will get stopped
- * once running. If required disable the tick interrupt here, then return
- * to xPortStartScheduler(). */
+ /* It is unlikely that the scheduler for the PIC port will get stopped
+ once running. If required disable the tick interrupt here, then return
+ to xPortStartScheduler(). */
}
/*-----------------------------------------------------------*/
@@ -503,15 +501,15 @@
*/
void vPortYield( void )
{
- /* This can get called with interrupts either enabled or disabled. We
- * will save the INTCON register with the interrupt enable bits unmodified. */
- portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
+ /* This can get called with interrupts either enabled or disabled. We
+ will save the INTCON register with the interrupt enable bits unmodified. */
+ portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
- /* Switch to the highest priority task that is ready to run. */
- vTaskSwitchContext();
+ /* Switch to the highest priority task that is ready to run. */
+ vTaskSwitchContext();
- /* Start executing the task we have just switched to. */
- portRESTORE_CONTEXT();
+ /* Start executing the task we have just switched to. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@@ -521,32 +519,32 @@
#pragma code high_vector=0x08
static void prvLowInterrupt( void )
{
- /* Was the interrupt the tick? */
- if( PIR1bits.CCP1IF )
- {
- _asm
- goto prvTickISR
- _endasm
- }
+ /* Was the interrupt the tick? */
+ if( PIR1bits.CCP1IF )
+ {
+ _asm
+ goto prvTickISR
+ _endasm
+ }
- /* Was the interrupt a byte being received? */
- if( PIR1bits.RCIF )
- {
- _asm
- goto vSerialRxISR
- _endasm
- }
+ /* Was the interrupt a byte being received? */
+ if( PIR1bits.RCIF )
+ {
+ _asm
+ goto vSerialRxISR
+ _endasm
+ }
- /* Was the interrupt the Tx register becoming empty? */
- if( PIR1bits.TXIF )
- {
- if( PIE1bits.TXIE )
- {
- _asm
- goto vSerialTxISR
- _endasm
- }
- }
+ /* Was the interrupt the Tx register becoming empty? */
+ if( PIR1bits.TXIF )
+ {
+ if( PIE1bits.TXIE )
+ {
+ _asm
+ goto vSerialTxISR
+ _endasm
+ }
+ }
}
#pragma code
@@ -554,25 +552,25 @@
/*
* ISR for the tick.
- * This increments the tick count and, if using the preemptive scheduler,
- * performs a context switch. This must be identical to the manual
- * context switch in how it stores the context of a task.
+ * This increments the tick count and, if using the preemptive scheduler,
+ * performs a context switch. This must be identical to the manual
+ * context switch in how it stores the context of a task.
*/
static void prvTickISR( void )
{
- /* Interrupts must have been enabled for the ISR to fire, so we have to
- * save the context with interrupts enabled. */
- portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
- PIR1bits.CCP1IF = 0;
+ /* Interrupts must have been enabled for the ISR to fire, so we have to
+ save the context with interrupts enabled. */
+ portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
+ PIR1bits.CCP1IF = 0;
- /* Maintain the tick count. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Switch to the highest priority task that is ready to run. */
- vTaskSwitchContext();
- }
+ /* Maintain the tick count. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Switch to the highest priority task that is ready to run. */
+ vTaskSwitchContext();
+ }
- portRESTORE_CONTEXT();
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
@@ -581,36 +579,37 @@
*/
static void prvSetupTimerInterrupt( void )
{
- const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
- uint32_t ulCompareValue;
- uint8_t ucByte;
+const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
+uint32_t ulCompareValue;
+uint8_t ucByte;
- /* Interrupts are disabled when this function is called.
- *
- * Setup CCP1 to provide the tick interrupt using a compare match on timer
- * 1.
- *
- * Clear the time count then setup timer. */
- TMR1H = ( uint8_t ) 0x00;
- TMR1L = ( uint8_t ) 0x00;
+ /* Interrupts are disabled when this function is called.
- /* Set the compare match value. */
- ulCompareValue = ulConstCompareValue;
- CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
- ulCompareValue >>= ( uint32_t ) 8;
- CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
+ Setup CCP1 to provide the tick interrupt using a compare match on timer
+ 1.
- CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
- CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
- CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
- CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
- PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
+ Clear the time count then setup timer. */
+ TMR1H = ( uint8_t ) 0x00;
+ TMR1L = ( uint8_t ) 0x00;
- /* We are only going to use the global interrupt bit, so set the peripheral
- * bit to true. */
- INTCONbits.GIEL = portBIT_SET;
+ /* Set the compare match value. */
+ ulCompareValue = ulConstCompareValue;
+ CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
+ ulCompareValue >>= ( uint32_t ) 8;
+ CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
- /* Provided library function for setting up the timer that will produce the
- * tick. */
- OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
+ CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
+ CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
+ CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
+ CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
+ PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
+
+ /* We are only going to use the global interrupt bit, so set the peripheral
+ bit to true. */
+ INTCONbits.GIEL = portBIT_SET;
+
+ /* Provided library function for setting up the timer that will produce the
+ tick. */
+ OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
}
+
diff --git a/portable/MPLAB/PIC18F/portmacro.h b/portable/MPLAB/PIC18F/portmacro.h
index fa3f747..0b42126 100644
--- a/portable/MPLAB/PIC18F/portmacro.h
+++ b/portable/MPLAB/PIC18F/portmacro.h
@@ -39,76 +39,74 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint8_t
-#define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 1
-#define portGLOBAL_INT_ENABLE_BIT 0x80
-#define portSTACK_GROWTH 1
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 1
+#define portGLOBAL_INT_ENABLE_BIT 0x80
+#define portSTACK_GROWTH 1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Critical section management. */
-#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0;
-#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1;
+#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0;
+#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1;
/* Push the INTCON register onto the stack, then disable interrupts. */
-#define portENTER_CRITICAL() \
- POSTINC1 = INTCON; \
- INTCONbits.GIEH = 0;
+#define portENTER_CRITICAL() POSTINC1 = INTCON; \
+ INTCONbits.GIEH = 0;
/* Retrieve the INTCON register from the stack, and enable interrupts
- * if they were saved as being enabled. Don't modify any other bits
- * within the INTCON register as these may have lagitimately have been
- * modified within the critical region. */
-#define portEXIT_CRITICAL() \
- _asm \
- MOVF POSTDEC1, 1, 0 \
- _endasm \
- if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \
- { \
- portENABLE_INTERRUPTS(); \
- }
+if they were saved as being enabled. Don't modify any other bits
+within the INTCON register as these may have lagitimately have been
+modified within the critical region. */
+#define portEXIT_CRITICAL() _asm \
+ MOVF POSTDEC1, 1, 0 \
+ _endasm \
+ if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ }
/*-----------------------------------------------------------*/
/* Task utilities. */
extern void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD() vPortYield()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
/* Required by the kernel aware debugger. */
#ifdef __DEBUG
- #define portREMOVE_STATIC_QUALIFIER
+ #define portREMOVE_STATIC_QUALIFIER
#endif
-#define portNOP() \
- _asm \
- NOP \
- _endasm
+#define portNOP() _asm \
+ NOP \
+ _endasm
#endif /* PORTMACRO_H */
+
diff --git a/portable/MPLAB/PIC24_dsPIC/port.c b/portable/MPLAB/PIC24_dsPIC/port.c
index 46d1843..62f621c 100644
--- a/portable/MPLAB/PIC24_dsPIC/port.c
+++ b/portable/MPLAB/PIC24_dsPIC/port.c
@@ -26,129 +26,129 @@
*/
/*
- * Changes from V4.2.1
- *
- + Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
- */
+ Changes from V4.2.1
+
+ + Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
+*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PIC24 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PIC24 port.
+ *----------------------------------------------------------*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Hardware specifics. */
-#define portBIT_SET 1
-#define portTIMER_PRESCALE 8
-#define portINITIAL_SR 0
+#define portBIT_SET 1
+#define portTIMER_PRESCALE 8
+#define portINITIAL_SR 0
/* Defined for backward compatability with project created prior to
- * FreeRTOS.org V4.3.0. */
+FreeRTOS.org V4.3.0. */
#ifndef configKERNEL_INTERRUPT_PRIORITY
- #define configKERNEL_INTERRUPT_PRIORITY 1
+ #define configKERNEL_INTERRUPT_PRIORITY 1
#endif
/* Use _T1Interrupt as the interrupt handler name if the application writer has
- * not provided their own. */
+not provided their own. */
#ifndef configTICK_INTERRUPT_HANDLER
- #define configTICK_INTERRUPT_HANDLER _T1Interrupt
+ #define configTICK_INTERRUPT_HANDLER _T1Interrupt
#endif /* configTICK_INTERRUPT_HANDLER */
/* The program counter is only 23 bits. */
-#define portUNUSED_PR_BITS 0x7f
+#define portUNUSED_PR_BITS 0x7f
/* Records the nesting depth of calls to portENTER_CRITICAL(). */
UBaseType_t uxCriticalNesting = 0xef;
#if configKERNEL_INTERRUPT_PRIORITY != 1
- #error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )
+ #error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )
#endif
-#if defined( __PIC24E__ ) || defined( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
+#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
#ifdef __HAS_EDS__
- #define portRESTORE_CONTEXT() \
- asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
- "MOV [W0], W15 \n" \
- "POP W0 \n"/* Restore the critical nesting counter for the task. */\
- "MOV W0, _uxCriticalNesting \n" \
- "POP DSWPAG \n" \
- "POP DSRPAG \n" \
- "POP CORCON \n" \
- "POP TBLPAG \n" \
- "POP RCOUNT \n"/* Restore the registers from the stack. */ \
- "POP W14 \n" \
- "POP.D W12 \n" \
- "POP.D W10 \n" \
- "POP.D W8 \n" \
- "POP.D W6 \n" \
- "POP.D W4 \n" \
- "POP.D W2 \n" \
- "POP.D W0 \n" \
- "POP SR ");
- #else /* __HAS_EDS__ */
- #define portRESTORE_CONTEXT() \
- asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
- "MOV [W0], W15 \n" \
- "POP W0 \n"/* Restore the critical nesting counter for the task. */\
- "MOV W0, _uxCriticalNesting \n" \
- "POP PSVPAG \n" \
- "POP CORCON \n" \
- "POP TBLPAG \n" \
- "POP RCOUNT \n"/* Restore the registers from the stack. */ \
- "POP W14 \n" \
- "POP.D W12 \n" \
- "POP.D W10 \n" \
- "POP.D W8 \n" \
- "POP.D W6 \n" \
- "POP.D W4 \n" \
- "POP.D W2 \n" \
- "POP.D W0 \n" \
- "POP SR ");
- #endif /* __HAS_EDS__ */
+ #define portRESTORE_CONTEXT() \
+ asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
+ "MOV [W0], W15 \n" \
+ "POP W0 \n" /* Restore the critical nesting counter for the task. */ \
+ "MOV W0, _uxCriticalNesting \n" \
+ "POP DSWPAG \n" \
+ "POP DSRPAG \n" \
+ "POP CORCON \n" \
+ "POP TBLPAG \n" \
+ "POP RCOUNT \n" /* Restore the registers from the stack. */ \
+ "POP W14 \n" \
+ "POP.D W12 \n" \
+ "POP.D W10 \n" \
+ "POP.D W8 \n" \
+ "POP.D W6 \n" \
+ "POP.D W4 \n" \
+ "POP.D W2 \n" \
+ "POP.D W0 \n" \
+ "POP SR " );
+ #else /* __HAS_EDS__ */
+ #define portRESTORE_CONTEXT() \
+ asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
+ "MOV [W0], W15 \n" \
+ "POP W0 \n" /* Restore the critical nesting counter for the task. */ \
+ "MOV W0, _uxCriticalNesting \n" \
+ "POP PSVPAG \n" \
+ "POP CORCON \n" \
+ "POP TBLPAG \n" \
+ "POP RCOUNT \n" /* Restore the registers from the stack. */ \
+ "POP W14 \n" \
+ "POP.D W12 \n" \
+ "POP.D W10 \n" \
+ "POP.D W8 \n" \
+ "POP.D W6 \n" \
+ "POP.D W4 \n" \
+ "POP.D W2 \n" \
+ "POP.D W0 \n" \
+ "POP SR " );
+ #endif /* __HAS_EDS__ */
#endif /* MPLAB_PIC24_PORT */
#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
- #define portRESTORE_CONTEXT() \
- asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
- "MOV [W0], W15 \n" \
- "POP W0 \n"/* Restore the critical nesting counter for the task. */\
- "MOV W0, _uxCriticalNesting \n" \
- "POP PSVPAG \n" \
- "POP CORCON \n" \
- "POP DOENDH \n" \
- "POP DOENDL \n" \
- "POP DOSTARTH \n" \
- "POP DOSTARTL \n" \
- "POP DCOUNT \n" \
- "POP ACCBU \n" \
- "POP ACCBH \n" \
- "POP ACCBL \n" \
- "POP ACCAU \n" \
- "POP ACCAH \n" \
- "POP ACCAL \n" \
- "POP TBLPAG \n" \
- "POP RCOUNT \n"/* Restore the registers from the stack. */ \
- "POP W14 \n" \
- "POP.D W12 \n" \
- "POP.D W10 \n" \
- "POP.D W8 \n" \
- "POP.D W6 \n" \
- "POP.D W4 \n" \
- "POP.D W2 \n" \
- "POP.D W0 \n" \
- "POP SR ");
+ #define portRESTORE_CONTEXT() \
+ asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
+ "MOV [W0], W15 \n" \
+ "POP W0 \n" /* Restore the critical nesting counter for the task. */ \
+ "MOV W0, _uxCriticalNesting \n" \
+ "POP PSVPAG \n" \
+ "POP CORCON \n" \
+ "POP DOENDH \n" \
+ "POP DOENDL \n" \
+ "POP DOSTARTH \n" \
+ "POP DOSTARTL \n" \
+ "POP DCOUNT \n" \
+ "POP ACCBU \n" \
+ "POP ACCBH \n" \
+ "POP ACCBL \n" \
+ "POP ACCAU \n" \
+ "POP ACCAH \n" \
+ "POP ACCAL \n" \
+ "POP TBLPAG \n" \
+ "POP RCOUNT \n" /* Restore the registers from the stack. */ \
+ "POP W14 \n" \
+ "POP.D W12 \n" \
+ "POP.D W10 \n" \
+ "POP.D W8 \n" \
+ "POP.D W6 \n" \
+ "POP.D W4 \n" \
+ "POP.D W2 \n" \
+ "POP.D W0 \n" \
+ "POP SR " );
#endif /* MPLAB_DSPIC_PORT */
#ifndef portRESTORE_CONTEXT
- #error Unrecognised device selected
+ #error Unrecognised device selected
-/* Note: dsPIC parts with EDS are not supported as there is no easy way to
- * recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
+ /* Note: dsPIC parts with EDS are not supported as there is no easy way to
+ recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
#endif
/*
@@ -159,177 +159,175 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint16_t usCode;
- UBaseType_t i;
+uint16_t usCode;
+UBaseType_t i;
- const StackType_t xInitialStack[] =
- {
- 0x1111, /* W1 */
- 0x2222, /* W2 */
- 0x3333, /* W3 */
- 0x4444, /* W4 */
- 0x5555, /* W5 */
- 0x6666, /* W6 */
- 0x7777, /* W7 */
- 0x8888, /* W8 */
- 0x9999, /* W9 */
- 0xaaaa, /* W10 */
- 0xbbbb, /* W11 */
- 0xcccc, /* W12 */
- 0xdddd, /* W13 */
- 0xeeee, /* W14 */
- 0xcdce, /* RCOUNT */
- 0xabac, /* TBLPAG */
+const StackType_t xInitialStack[] =
+{
+ 0x1111, /* W1 */
+ 0x2222, /* W2 */
+ 0x3333, /* W3 */
+ 0x4444, /* W4 */
+ 0x5555, /* W5 */
+ 0x6666, /* W6 */
+ 0x7777, /* W7 */
+ 0x8888, /* W8 */
+ 0x9999, /* W9 */
+ 0xaaaa, /* W10 */
+ 0xbbbb, /* W11 */
+ 0xcccc, /* W12 */
+ 0xdddd, /* W13 */
+ 0xeeee, /* W14 */
+ 0xcdce, /* RCOUNT */
+ 0xabac, /* TBLPAG */
- /* dsPIC specific registers. */
- #ifdef MPLAB_DSPIC_PORT
- 0x0202, /* ACCAL */
- 0x0303, /* ACCAH */
- 0x0404, /* ACCAU */
- 0x0505, /* ACCBL */
- 0x0606, /* ACCBH */
- 0x0707, /* ACCBU */
- 0x0808, /* DCOUNT */
- 0x090a, /* DOSTARTL */
- 0x1010, /* DOSTARTH */
- 0x1110, /* DOENDL */
- 0x1212, /* DOENDH */
- #endif /* ifdef MPLAB_DSPIC_PORT */
- };
+ /* dsPIC specific registers. */
+ #ifdef MPLAB_DSPIC_PORT
+ 0x0202, /* ACCAL */
+ 0x0303, /* ACCAH */
+ 0x0404, /* ACCAU */
+ 0x0505, /* ACCBL */
+ 0x0606, /* ACCBH */
+ 0x0707, /* ACCBU */
+ 0x0808, /* DCOUNT */
+ 0x090a, /* DOSTARTL */
+ 0x1010, /* DOSTARTH */
+ 0x1110, /* DOENDL */
+ 0x1212, /* DOENDH */
+ #endif
+};
- /* Setup the stack as if a yield had occurred.
- *
- * Save the low bytes of the program counter. */
- usCode = ( uint16_t ) pxCode;
- *pxTopOfStack = ( StackType_t ) usCode;
- pxTopOfStack++;
+ /* Setup the stack as if a yield had occurred.
- /* Save the high byte of the program counter. This will always be zero
- * here as it is passed in a 16bit pointer. If the address is greater than
- * 16 bits then the pointer will point to a jump table. */
- *pxTopOfStack = ( StackType_t ) 0;
- pxTopOfStack++;
+ Save the low bytes of the program counter. */
+ usCode = ( uint16_t ) pxCode;
+ *pxTopOfStack = ( StackType_t ) usCode;
+ pxTopOfStack++;
- /* Status register with interrupts enabled. */
- *pxTopOfStack = portINITIAL_SR;
- pxTopOfStack++;
+ /* Save the high byte of the program counter. This will always be zero
+ here as it is passed in a 16bit pointer. If the address is greater than
+ 16 bits then the pointer will point to a jump table. */
+ *pxTopOfStack = ( StackType_t ) 0;
+ pxTopOfStack++;
- /* Parameters are passed in W0. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack++;
+ /* Status register with interrupts enabled. */
+ *pxTopOfStack = portINITIAL_SR;
+ pxTopOfStack++;
- for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( StackType_t ) ); i++ )
- {
- *pxTopOfStack = xInitialStack[ i ];
- pxTopOfStack++;
- }
+ /* Parameters are passed in W0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack++;
- *pxTopOfStack = CORCON;
- pxTopOfStack++;
+ for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( StackType_t ) ); i++ )
+ {
+ *pxTopOfStack = xInitialStack[ i ];
+ pxTopOfStack++;
+ }
- #if defined( __HAS_EDS__ )
- *pxTopOfStack = DSRPAG;
- pxTopOfStack++;
- *pxTopOfStack = DSWPAG;
- pxTopOfStack++;
- #else /* __HAS_EDS__ */
- *pxTopOfStack = PSVPAG;
- pxTopOfStack++;
- #endif /* __HAS_EDS__ */
+ *pxTopOfStack = CORCON;
+ pxTopOfStack++;
- /* Finally the critical nesting depth. */
- *pxTopOfStack = 0x00;
- pxTopOfStack++;
+ #if defined(__HAS_EDS__)
+ *pxTopOfStack = DSRPAG;
+ pxTopOfStack++;
+ *pxTopOfStack = DSWPAG;
+ pxTopOfStack++;
+ #else /* __HAS_EDS__ */
+ *pxTopOfStack = PSVPAG;
+ pxTopOfStack++;
+ #endif /* __HAS_EDS__ */
- return pxTopOfStack;
+ /* Finally the critical nesting depth. */
+ *pxTopOfStack = 0x00;
+ pxTopOfStack++;
+
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup a timer for the tick ISR. */
- vApplicationSetupTickTimerInterrupt();
+ /* Setup a timer for the tick ISR. */
+ vApplicationSetupTickTimerInterrupt();
- /* Restore the context of the first task to run. */
- portRESTORE_CONTEXT();
+ /* Restore the context of the first task to run. */
+ portRESTORE_CONTEXT();
- /* Simulate the end of the yield function. */
- asm volatile ( "return" );
+ /* Simulate the end of the yield function. */
+ asm volatile ( "return" );
- /* Should not reach here. */
- return pdTRUE;
+ /* Should not reach here. */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
/*
* Setup a timer for a regular tick.
*/
-__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
{
- const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
+const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
- /* Prescale of 8. */
- T1CON = 0;
- TMR1 = 0;
+ /* Prescale of 8. */
+ T1CON = 0;
+ TMR1 = 0;
- PR1 = ( uint16_t ) ulCompareMatch;
+ PR1 = ( uint16_t ) ulCompareMatch;
- /* Setup timer 1 interrupt priority. */
- IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
+ /* Setup timer 1 interrupt priority. */
+ IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
- /* Clear the interrupt as a starting condition. */
- IFS0bits.T1IF = 0;
+ /* Clear the interrupt as a starting condition. */
+ IFS0bits.T1IF = 0;
- /* Enable the interrupt. */
- IEC0bits.T1IE = 1;
+ /* Enable the interrupt. */
+ IEC0bits.T1IE = 1;
- /* Setup the prescale value. */
- T1CONbits.TCKPS0 = 1;
- T1CONbits.TCKPS1 = 0;
+ /* Setup the prescale value. */
+ T1CONbits.TCKPS0 = 1;
+ T1CONbits.TCKPS1 = 0;
- /* Start the timer. */
- T1CONbits.TON = 1;
+ /* Start the timer. */
+ T1CONbits.TON = 1;
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
}
/*-----------------------------------------------------------*/
-void __attribute__( ( __interrupt__, auto_psv ) ) configTICK_INTERRUPT_HANDLER( void )
+void __attribute__((__interrupt__, auto_psv)) configTICK_INTERRUPT_HANDLER( void )
{
- /* Clear the timer interrupt. */
- IFS0bits.T1IF = 0;
+ /* Clear the timer interrupt. */
+ IFS0bits.T1IF = 0;
- if( xTaskIncrementTick() != pdFALSE )
- {
- portYIELD();
- }
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ portYIELD();
+ }
}
+
diff --git a/portable/MPLAB/PIC24_dsPIC/portmacro.h b/portable/MPLAB/PIC24_dsPIC/portmacro.h
index a1ab91f..ece9cd9 100644
--- a/portable/MPLAB/PIC24_dsPIC/portmacro.h
+++ b/portable/MPLAB/PIC24_dsPIC/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,66 +43,66 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint16_t
- #define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
- typedef portSTACK_TYPE StackType_t;
- typedef short BaseType_t;
- typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 2
- #define portSTACK_GROWTH 1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH 1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Critical section management. */
- #define portDISABLE_INTERRUPTS() SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" )
- #define portENABLE_INTERRUPTS() SET_CPU_IPL( 0 )
+#define portDISABLE_INTERRUPTS() SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" )
+#define portENABLE_INTERRUPTS() SET_CPU_IPL( 0 )
/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter
- * what their value was prior to entering the critical section. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+what their value was prior to entering the critical section. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
- extern void vPortYield( void );
- #define portYIELD() \
- asm volatile ( "CALL _vPortYield \n"\
- "NOP ");
+extern void vPortYield( void );
+#define portYIELD() asm volatile ( "CALL _vPortYield \n" \
+ "NOP " );
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
/* Required by the kernel aware debugger. */
- #ifdef __DEBUG
- #define portREMOVE_STATIC_QUALIFIER
- #endif
+#ifdef __DEBUG
+ #define portREMOVE_STATIC_QUALIFIER
+#endif
- #define portNOP() asm volatile ( "NOP" )
+#define portNOP() asm volatile ( "NOP" )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
index fadf12d..41170d3 100644
--- a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
+++ b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
@@ -27,187 +27,188 @@
#include "FreeRTOSConfig.h"
-#define portCONTEXT_SIZE 132
-#define portEPC_STACK_LOCATION 124
-#define portSTATUS_STACK_LOCATION 128
+#define portCONTEXT_SIZE 132
+#define portEPC_STACK_LOCATION 124
+#define portSTATUS_STACK_LOCATION 128
#ifdef __LANGUAGE_ASSEMBLY__
/******************************************************************/
- .macro portSAVE_CONTEXT
+.macro portSAVE_CONTEXT
-/* Make room for the context. First save the current status so it can be
- * manipulated, and the cause and EPC registers so their original values are
- * captured. */
- mfc0 k0, _CP0_CAUSE
- addiu sp, sp, -portCONTEXT_SIZE
- mfc0 k1, _CP0_STATUS
+ /* Make room for the context. First save the current status so it can be
+ manipulated, and the cause and EPC registers so their original values are
+ captured. */
+ mfc0 k0, _CP0_CAUSE
+ addiu sp, sp, -portCONTEXT_SIZE
+ mfc0 k1, _CP0_STATUS
-/* Also save s6 and s5 so they can be used. Any nesting interrupts should
- * maintain the values of these registers across the ISR. */
- sw s6, 44 ( sp )
- sw s5, 40 ( sp )
- sw k1, portSTATUS_STACK_LOCATION( sp )
+ /* Also save s6 and s5 so they can be used. Any nesting interrupts should
+ maintain the values of these registers across the ISR. */
+ sw s6, 44(sp)
+ sw s5, 40(sp)
+ sw k1, portSTATUS_STACK_LOCATION(sp)
-/* Prepare to enable interrupts above the current priority.
- * k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
- srl k0, k0, 0xa
+ /* Prepare to enable interrupts above the current priority.
+ k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
+ srl k0, k0, 0xa
-/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
- ins k1, k0, 10, 7
+ /* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
+ ins k1, k0, 10, 7
-/* Sets CP0.Status.IPL = CP0.Cause.RIPL
- * Copy the MSB of the IPL, but it would be an error if it was set anyway. */
- srl k0, k0, 0x7
+ /* Sets CP0.Status.IPL = CP0.Cause.RIPL
+ Copy the MSB of the IPL, but it would be an error if it was set anyway. */
+ srl k0, k0, 0x7
-/* MSB of IPL is bit[18] of CP0.Status */
- ins k1, k0, 18, 1
+ /* MSB of IPL is bit[18] of CP0.Status */
+ ins k1, k0, 18, 1
-/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
- * b[3]=Rsvd, b[2]=ERL, b[1]=EXL
- * Setting EXL=0 allows higher priority interrupts
- * to preempt this handler */
- ins k1, zero, 1, 4
+ /* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
+ b[3]=Rsvd, b[2]=ERL, b[1]=EXL
+ Setting EXL=0 allows higher priority interrupts
+ to preempt this handler */
+ ins k1, zero, 1, 4
-/* s5 is used as the frame pointer. */
- add s5, zero, sp
+ /* s5 is used as the frame pointer. */
+ add s5, zero, sp
-/* Check the nesting count value. */
- la k0, uxInterruptNesting
- lw s6, ( k0 )
+ /* Check the nesting count value. */
+ la k0, uxInterruptNesting
+ lw s6, (k0)
-/* If the nesting count is 0 then swap to the the system stack, otherwise
- * the system stack is already being used. */
- bne s6, zero, 1f
- nop
+ /* If the nesting count is 0 then swap to the the system stack, otherwise
+ the system stack is already being used. */
+ bne s6, zero, 1f
+ nop
-/* Swap to the system stack. */
- la sp, xISRStackTop
- lw sp, ( sp )
+ /* Swap to the system stack. */
+ la sp, xISRStackTop
+ lw sp, (sp)
-/* Increment and save the nesting count. */
- 1 : addiu s6, s6, 1
- sw s6, 0 ( k0 )
+ /* Increment and save the nesting count. */
+1: addiu s6, s6, 1
+ sw s6, 0(k0)
-/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
- mfc0 s6, _CP0_EPC
+ /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+ mfc0 s6, _CP0_EPC
-/* Re-enable interrupts. */
- mtc0 k1, _CP0_STATUS
+ /* Re-enable interrupts. */
+ mtc0 k1, _CP0_STATUS
-/* Save the context into the space just created. s6 is saved again
- * here as it now contains the EPC value. No other s registers need be
- * saved. */
- sw ra, 120 ( s5 ) /* Return address (RA=R31) */
- sw s8, 116 ( s5 ) /* Frame Pointer (FP=R30) */
- sw t9, 112 ( s5 )
- sw t8, 108 ( s5 )
- sw t7, 104 ( s5 )
- sw t6, 100 ( s5 )
- sw t5, 96 ( s5 )
- sw t4, 92 ( s5 )
- sw t3, 88 ( s5 )
- sw t2, 84 ( s5 )
- sw t1, 80 ( s5 )
- sw t0, 76 ( s5 )
- sw a3, 72 ( s5 )
- sw a2, 68 ( s5 )
- sw a1, 64 ( s5 )
- sw a0, 60 ( s5 )
- sw v1, 56 ( s5 )
- sw v0, 52 ( s5 )
- sw s6, portEPC_STACK_LOCATION( s5 )
- sw $1, 16 ( s5 )
+ /* Save the context into the space just created. s6 is saved again
+ here as it now contains the EPC value. No other s registers need be
+ saved. */
+ sw ra, 120(s5) /* Return address (RA=R31) */
+ sw s8, 116(s5) /* Frame Pointer (FP=R30) */
+ sw t9, 112(s5)
+ sw t8, 108(s5)
+ sw t7, 104(s5)
+ sw t6, 100(s5)
+ sw t5, 96(s5)
+ sw t4, 92(s5)
+ sw t3, 88(s5)
+ sw t2, 84(s5)
+ sw t1, 80(s5)
+ sw t0, 76(s5)
+ sw a3, 72(s5)
+ sw a2, 68(s5)
+ sw a1, 64(s5)
+ sw a0, 60(s5)
+ sw v1, 56(s5)
+ sw v0, 52(s5)
+ sw s6, portEPC_STACK_LOCATION(s5)
+ sw $1, 16(s5)
-/* MEC14xx does not have DSP, removed 7 words */
- mfhi s6
- sw s6, 12 ( s5 )
- mflo s6
- sw s6, 8 ( s5 )
+ /* MEC14xx does not have DSP, removed 7 words */
+ mfhi s6
+ sw s6, 12(s5)
+ mflo s6
+ sw s6, 8(s5)
-/* Update the task stack pointer value if nesting is zero. */
- la s6, uxInterruptNesting
- lw s6, ( s6 )
- addiu s6, s6, -1
- bne s6, zero, 1f
- nop
+ /* Update the task stack pointer value if nesting is zero. */
+ la s6, uxInterruptNesting
+ lw s6, (s6)
+ addiu s6, s6, -1
+ bne s6, zero, 1f
+ nop
-/* Save the stack pointer. */
- la s6, uxSavedTaskStackPointer
- sw s5, ( s6 )
- 1 :
- .endm
+ /* Save the stack pointer. */
+ la s6, uxSavedTaskStackPointer
+ sw s5, (s6)
+1:
+ .endm
/******************************************************************/
- .macro portRESTORE_CONTEXT
+.macro portRESTORE_CONTEXT
-/* Restore the stack pointer from the TCB. This is only done if the
- * nesting count is 1. */
- la s6, uxInterruptNesting
- lw s6, ( s6 )
- addiu s6, s6, -1
- bne s6, zero, 1f
- nop
- la s6, uxSavedTaskStackPointer
- lw s5, ( s6 )
+ /* Restore the stack pointer from the TCB. This is only done if the
+ nesting count is 1. */
+ la s6, uxInterruptNesting
+ lw s6, (s6)
+ addiu s6, s6, -1
+ bne s6, zero, 1f
+ nop
+ la s6, uxSavedTaskStackPointer
+ lw s5, (s6)
-/* Restore the context.
- * MCHP MEC14xx does not include DSP */
- 1 :
- lw s6, 8 ( s5 )
- mtlo s6
- lw s6, 12 ( s5 )
- mthi s6
- lw $1, 16 ( s5 )
+ /* Restore the context.
+ MCHP MEC14xx does not include DSP */
+1:
+ lw s6, 8(s5)
+ mtlo s6
+ lw s6, 12(s5)
+ mthi s6
+ lw $1, 16(s5)
-/* s6 is loaded as it was used as a scratch register and therefore saved
- * as part of the interrupt context. */
- lw s6, 44 ( s5 )
- lw v0, 52 ( s5 )
- lw v1, 56 ( s5 )
- lw a0, 60 ( s5 )
- lw a1, 64 ( s5 )
- lw a2, 68 ( s5 )
- lw a3, 72 ( s5 )
- lw t0, 76 ( s5 )
- lw t1, 80 ( s5 )
- lw t2, 84 ( s5 )
- lw t3, 88 ( s5 )
- lw t4, 92 ( s5 )
- lw t5, 96 ( s5 )
- lw t6, 100 ( s5 )
- lw t7, 104 ( s5 )
- lw t8, 108 ( s5 )
- lw t9, 112 ( s5 )
- lw s8, 116 ( s5 )
- lw ra, 120 ( s5 )
+ /* s6 is loaded as it was used as a scratch register and therefore saved
+ as part of the interrupt context. */
+ lw s6, 44(s5)
+ lw v0, 52(s5)
+ lw v1, 56(s5)
+ lw a0, 60(s5)
+ lw a1, 64(s5)
+ lw a2, 68(s5)
+ lw a3, 72(s5)
+ lw t0, 76(s5)
+ lw t1, 80(s5)
+ lw t2, 84(s5)
+ lw t3, 88(s5)
+ lw t4, 92(s5)
+ lw t5, 96(s5)
+ lw t6, 100(s5)
+ lw t7, 104(s5)
+ lw t8, 108(s5)
+ lw t9, 112(s5)
+ lw s8, 116(s5)
+ lw ra, 120(s5)
-/* Protect access to the k registers, and others. */
- di
- ehb
+ /* Protect access to the k registers, and others. */
+ di
+ ehb
-/* Decrement the nesting count. */
- la k0, uxInterruptNesting
- lw k1, ( k0 )
- addiu k1, k1, -1
- sw k1, 0 ( k0 )
+ /* Decrement the nesting count. */
+ la k0, uxInterruptNesting
+ lw k1, (k0)
+ addiu k1, k1, -1
+ sw k1, 0(k0)
- lw k0, portSTATUS_STACK_LOCATION( s5 )
- lw k1, portEPC_STACK_LOCATION( s5 )
+ lw k0, portSTATUS_STACK_LOCATION(s5)
+ lw k1, portEPC_STACK_LOCATION(s5)
-/* Leave the stack in its original state. First load sp from s5, then
- * restore s5 from the stack. */
- add sp, zero, s5
- lw s5, 40 ( sp )
- addiu sp, sp, portCONTEXT_SIZE
+ /* Leave the stack in its original state. First load sp from s5, then
+ restore s5 from the stack. */
+ add sp, zero, s5
+ lw s5, 40(sp)
+ addiu sp, sp, portCONTEXT_SIZE
- mtc0 k0, _CP0_STATUS
- mtc0 k1, _CP0_EPC
- ehb
- eret
- nop
+ mtc0 k0, _CP0_STATUS
+ mtc0 k1, _CP0_EPC
+ ehb
+ eret
+ nop
- .endm
+ .endm
#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */
+
diff --git a/portable/MPLAB/PIC32MEC14xx/port.c b/portable/MPLAB/PIC32MEC14xx/port.c
index eaf189b..c2d837f 100644
--- a/portable/MPLAB/PIC32MEC14xx/port.c
+++ b/portable/MPLAB/PIC32MEC14xx/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PIC32MEC14xx port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PIC32MEC14xx port.
+ *----------------------------------------------------------*/
/* Scheduler include files. */
#include "FreeRTOS.h"
@@ -37,96 +37,94 @@
#include <xc.h>
#include <cp0defs.h>
-#if !defined( __MEC__ )
- #error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings.
+#if !defined(__MEC__)
+ #error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings.
#endif
-#if ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
- #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
+#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
+ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
#endif
/* Bits within various registers. */
-#define portIE_BIT ( 0x00000001 )
-#define portEXL_BIT ( 0x00000002 )
+#define portIE_BIT ( 0x00000001 )
+#define portEXL_BIT ( 0x00000002 )
/* The EXL bit is set to ensure interrupts do not occur while the context of
- * the first task is being restored. MEC14xx does not have DSP HW. */
-#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
+the first task is being restored. MEC14xx does not have DSP HW. */
+#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
/* MEC14xx RTOS Timer MMCR's. */
-#define portMMCR_RTMR_PRELOAD *( ( volatile uint32_t * ) ( 0xA0007404ul ) )
-#define portMMCR_RTMR_CONTROL *( ( volatile uint32_t * ) ( 0xA0007408ul ) )
+#define portMMCR_RTMR_PRELOAD *((volatile uint32_t *)(0xA0007404ul))
+#define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul))
/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
- * peripheral space. */
-#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 )
-#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
-#define portMMCR_JTVIC_GIRQ23_SRC *( ( volatile uint32_t * ) ( 0xBFFFC0F0ul ) )
-#define portMMCR_JTVIC_GIRQ23_SETEN *( ( volatile uint32_t * ) ( 0xBFFFC0F4ul ) )
-#define portMMCR_JTVIC_GIRQ23_PRIA *( ( volatile uint32_t * ) ( 0xBFFFC3F0ul ) )
+peripheral space. */
+#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 )
+#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
+#define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul))
+#define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul))
+#define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul))
/* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
-#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
-#define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
-#define portMMCR_JTVIC_GIRQ24_SRC *( ( volatile uint32_t * ) ( 0xBFFFC100ul ) )
-#define portMMCR_JTVIC_GIRQ24_SETEN *( ( volatile uint32_t * ) ( 0xBFFFC104ul ) )
-#define portMMCR_JTVIC_GIRQ24_PRIA *( ( volatile uint32_t * ) ( 0xBFFFC400ul ) )
+#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
+#define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
+#define portMMCR_JTVIC_GIRQ24_SRC *((volatile uint32_t *)(0xBFFFC100ul))
+#define portMMCR_JTVIC_GIRQ24_SETEN *((volatile uint32_t *)(0xBFFFC104ul))
+#define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul))
/*
- * By default port.c generates its tick interrupt from the RTOS timer. The user
- * can override this behaviour by:
- * 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
- * which is the function that configures the timer. The function is defined
- * as a weak symbol in this file so if the same function name is used in the
- * application code then the version in the application code will be linked
- * into the application in preference to the version defined in this file.
- * 2: Provide a vector implementation in port_asm.S that overrides the default
- * behaviour for the specified interrupt vector.
- * 3: Specify the correct bit to clear the interrupt during the timer interrupt
- * handler.
- */
+By default port.c generates its tick interrupt from the RTOS timer. The user
+can override this behaviour by:
+ 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+ which is the function that configures the timer. The function is defined
+ as a weak symbol in this file so if the same function name is used in the
+ application code then the version in the application code will be linked
+ into the application in preference to the version defined in this file.
+ 2: Provide a vector implementation in port_asm.S that overrides the default
+ behaviour for the specified interrupt vector.
+ 3: Specify the correct bit to clear the interrupt during the timer interrupt
+ handler.
+*/
#ifndef configTICK_INTERRUPT_VECTOR
- #define configTICK_INTERRUPT_VECTOR girq23_b4
- #define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
+ #define configTICK_INTERRUPT_VECTOR girq23_b4
+ #define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
#else
- #ifndef configCLEAR_TICK_TIMER_INTERRUPT
- #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
- #endif
+ #ifndef configCLEAR_TICK_TIMER_INTERRUPT
+ #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
+ #endif
#endif
/* Let the user override the pre-loading of the initial RA with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
- * in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
+in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
- * stack checking. A problem in the ISR stack will trigger an assert, not call the
- * stack overflow hook function (because the stack overflow hook is specific to a
- * task stack, not the ISR stack). */
-#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+stack checking. A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
-/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
- * the task stacks, and so will legitimately appear in many positions within
- * the ISR stack. */
- #define portISR_STACK_FILL_BYTE 0xee
+ /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
+ the task stacks, and so will legitimately appear in many positions within
+ the ISR stack. */
+ #define portISR_STACK_FILL_BYTE 0xee
- static const uint8_t ucExpectedStackBytes[] =
- {
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
- }; \
+ static const uint8_t ucExpectedStackBytes[] = {
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
- #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
- /* Define the function away. */
- #define portCHECK_ISR_STACK()
+ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+ /* Define the function away. */
+ #define portCHECK_ISR_STACK()
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
@@ -140,7 +138,7 @@
/*-----------------------------------------------------------*/
/* Records the interrupt nesting depth. This is initialised to one as it is
- * decremented to 0 when the first task starts. */
+decremented to 0 when the first task starts. */
volatile UBaseType_t uxInterruptNesting = 0x01;
/* Stores the task stack pointer when a switch is made to use the system stack. */
@@ -150,7 +148,7 @@
StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
/* The top of stack value ensures there is enough space to store 6 registers on
- * the callers stack, as some functions seem to want to do this. */
+the callers stack, as some functions seem to want to do this. */
const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
/*-----------------------------------------------------------*/
@@ -158,62 +156,56 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Ensure byte alignment is maintained when leaving this function. */
- pxTopOfStack--;
+ /* Ensure byte alignment is maintained when leaving this function. */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ulPortGetCP0Cause();
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
- pxTopOfStack -= 15;
+ *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
+ pxTopOfStack -= 15;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
- pxTopOfStack -= 15;
+ *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+ pxTopOfStack -= 15;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static __inline uint32_t prvDisableInterrupt( void )
{
- uint32_t prev_state;
+uint32_t prev_state;
- __asm volatile ( "di %0; ehb" : "=r" ( prev_state )::"memory" );
-
- return prev_state;
+ __asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
+ return prev_state;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( uxSavedTaskStackPointer == 0UL );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( uxSavedTaskStackPointer == 0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
@@ -225,124 +217,129 @@
* ensure the RTOS provided tick interrupt handler is installed on the correct
* vector number.
*/
-__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
{
/* MEC14xx RTOS Timer whose input clock is 32KHz. */
- const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
+const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
- configASSERT( ulPreload != 0UL );
+ configASSERT( ulPreload != 0UL );
- /* Configure the RTOS timer. */
- portMMCR_RTMR_CONTROL = 0ul;
- portMMCR_RTMR_PRELOAD = ulPreload;
+ /* Configure the RTOS timer. */
+ portMMCR_RTMR_CONTROL = 0ul;
+ portMMCR_RTMR_PRELOAD = ulPreload;
- /* Configure interrupts from the RTOS timer. */
- portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
- portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
- portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 );
- portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
+ /* Configure interrupts from the RTOS timer. */
+ portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
+ portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
+ portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 );
+ portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
- /* Enable the RTOS timer. */
- portMMCR_RTMR_CONTROL = 0x0Fu;
+ /* Enable the RTOS timer. */
+ portMMCR_RTMR_CONTROL = 0x0Fu;
}
/*-----------------------------------------------------------*/
-void vPortEndScheduler( void )
+void vPortEndScheduler(void)
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxInterruptNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( uxInterruptNesting == 1000UL );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
- extern void * pxCurrentTCB;
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
- #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
- {
- /* Fill the ISR stack to make it easy to asses how much is being used. */
- memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
- }
- #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+ #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+ {
+ /* Fill the ISR stack to make it easy to asses how much is being used. */
+ memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+ }
+ #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
- /* Clear the software interrupt flag. */
- portMMCR_JTVIC_GIRQ24_SRC = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
+ /* Clear the software interrupt flag. */
+ portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
- /* Set software timer priority. Each GIRQn has one nibble containing its
- * priority */
- portMMCR_JTVIC_GIRQ24_PRIA &= ~( 0xF0ul );
- portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
+ /* Set software timer priority. Each GIRQn has one nibble containing its
+ priority */
+ portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
+ portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
- /* Enable software interrupt. */
- portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
+ /* Enable software interrupt. */
+ portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
- /* Setup the timer to generate the tick. Interrupts will have been disabled
- * by the time we get here. */
- vApplicationSetupTickTimerInterrupt();
+ /* Setup the timer to generate the tick. Interrupts will have been disabled
+ by the time we get here. */
+ vApplicationSetupTickTimerInterrupt();
- /* Start the highest priority task that has been created so far. Its stack
- * location is loaded into uxSavedTaskStackPointer. */
- uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
- vPortStartFirstTask();
+ /* Start the highest priority task that has been created so far. Its stack
+ location is loaded into uxSavedTaskStackPointer. */
+ uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
+ vPortStartFirstTask();
- /* Should never get here as the tasks will now be executing! Call the task
- * exit error function to prevent compiler warnings about a static function
- * not being called in the case that the application writer overrides this
- * functionality by defining configTASK_RETURN_ADDRESS. */
- prvTaskExitError();
+ /* Should never get here as the tasks will now be executing! Call the task
+ exit error function to prevent compiler warnings about a static function
+ not being called in the case that the application writer overrides this
+ functionality by defining configTASK_RETURN_ADDRESS. */
+ prvTaskExitError();
- return pdFALSE;
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortIncrementTick( void )
{
- UBaseType_t uxSavedStatus;
- uint32_t ulCause;
+UBaseType_t uxSavedStatus;
+uint32_t ulCause;
- uxSavedStatus = uxPortSetInterruptMaskFromISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Pend a context switch. */
- ulCause = ulPortGetCP0Cause();
- ulCause |= ( 1ul << 8UL );
- vPortSetCP0Cause( ulCause );
- }
- }
- vPortClearInterruptMaskFromISR( uxSavedStatus );
+ uxSavedStatus = uxPortSetInterruptMaskFromISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ ulCause = ulPortGetCP0Cause();
+ ulCause |= ( 1ul << 8UL );
+ vPortSetCP0Cause( ulCause );
+ }
+ }
+ vPortClearInterruptMaskFromISR( uxSavedStatus );
- /* Look for the ISR stack getting near or past its limit. */
- portCHECK_ISR_STACK();
+ /* Look for the ISR stack getting near or past its limit. */
+ portCHECK_ISR_STACK();
- /* Clear timer interrupt. */
- configCLEAR_TICK_TIMER_INTERRUPT();
+ /* Clear timer interrupt. */
+ configCLEAR_TICK_TIMER_INTERRUPT();
}
/*-----------------------------------------------------------*/
UBaseType_t uxPortSetInterruptMaskFromISR( void )
{
- UBaseType_t uxSavedStatusRegister;
+UBaseType_t uxSavedStatusRegister;
- prvDisableInterrupt();
- uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
+ prvDisableInterrupt();
+ uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
- /* This clears the IPL bits, then sets them to
- * configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
- * from an interrupt that has a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
- * can only result in the IPL being unchanged or raised, and therefore never
- * lowered. */
- vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
+ /* This clears the IPL bits, then sets them to
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
+ from an interrupt that has a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+ can only result in the IPL being unchanged or raised, and therefore never
+ lowered. */
+ vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
- return uxSavedStatusRegister;
+ return uxSavedStatusRegister;
}
/*-----------------------------------------------------------*/
void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
{
- vPortSetCP0Status( uxSavedStatusRegister );
+ vPortSetCP0Status( uxSavedStatusRegister );
}
/*-----------------------------------------------------------*/
+
+
+
+
+
diff --git a/portable/MPLAB/PIC32MEC14xx/portmacro.h b/portable/MPLAB/PIC32MEC14xx/portmacro.h
index ba05ed7..f4a30b0 100644
--- a/portable/MPLAB/PIC32MEC14xx/portmacro.h
+++ b/portable/MPLAB/PIC32MEC14xx/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,211 +43,210 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Critical section management. */
- #define portIPL_SHIFT ( 10UL )
-
+#define portIPL_SHIFT ( 10UL )
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
- * never have higher IPL bits set anyway. */
- #define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
- #define portSW0_BIT ( 0x01 << 8 )
+never have higher IPL bits set anyway. */
+#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
+#define portSW0_BIT ( 0x01 << 8 )
/* Interrupt priority conversion */
- #define portIPL_TO_CODE( iplNumber ) ( ( iplNumber >> 1 ) & 0x03ul )
- #define portCODE_TO_IPL( iplCode ) ( ( iplCode << 1 ) | 0x01ul )
+#define portIPL_TO_CODE( iplNumber ) ( ( iplNumber >> 1 ) & 0x03ul )
+#define portCODE_TO_IPL( iplCode ) ( ( iplCode << 1 ) | 0x01ul )
/*-----------------------------------------------------------*/
- static inline uint32_t ulPortGetCP0Status( void )
- {
- uint32_t rv;
+static inline uint32_t ulPortGetCP0Status( void )
+{
+uint32_t rv;
- __asm volatile (
- "\n\t"
- "mfc0 %0,$12,0 \n\t"
- : "=r" ( rv )::);
+ __asm volatile(
+ "\n\t"
+ "mfc0 %0,$12,0 \n\t"
+ : "=r" ( rv ) :: );
- return rv;
- }
+ return rv;
+}
/*-----------------------------------------------------------*/
- static inline void vPortSetCP0Status( uint32_t new_status )
- {
- ( void ) new_status;
+static inline void vPortSetCP0Status( uint32_t new_status)
+{
+ ( void ) new_status;
- __asm__ __volatile__ (
- "\n\t"
- "mtc0 %0,$12,0 \n\t"
- "ehb \n\t"
- :
- : "r" ( new_status ) : );
- }
+ __asm__ __volatile__(
+ "\n\t"
+ "mtc0 %0,$12,0 \n\t"
+ "ehb \n\t"
+ :
+ :"r" ( new_status ) : );
+}
/*-----------------------------------------------------------*/
- static inline uint32_t ulPortGetCP0Cause( void )
- {
- uint32_t rv;
+static inline uint32_t ulPortGetCP0Cause( void )
+{
+uint32_t rv;
- __asm volatile (
- "\n\t"
- "mfc0 %0,$13,0 \n\t"
- : "=r" ( rv )::);
+ __asm volatile(
+ "\n\t"
+ "mfc0 %0,$13,0 \n\t"
+ : "=r" ( rv ) :: );
- return rv;
- }
+ return rv;
+}
/*-----------------------------------------------------------*/
- static inline void vPortSetCP0Cause( uint32_t new_cause )
- {
- ( void ) new_cause;
+static inline void vPortSetCP0Cause( uint32_t new_cause )
+{
+ ( void ) new_cause;
- __asm__ __volatile__ (
- "\n\t"
- "mtc0 %0,$13,0 \n\t"
- "ehb \n\t"
- :
- : "r" ( new_cause ) : );
- }
+ __asm__ __volatile__(
+ "\n\t"
+ "mtc0 %0,$13,0 \n\t"
+ "ehb \n\t"
+ :
+ :"r" ( new_cause ) : );
+}
/*-----------------------------------------------------------*/
/* This clears the IPL bits, then sets them to
- * configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
- * configASSERT() is defined to ensure an assertion handler does not inadvertently
- * attempt to lower the IPL when the call to assert was triggered because the IPL
- * value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
- * safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
- * those that end in FromISR. FreeRTOS maintains a separate interrupt API to
- * ensure API function and interrupt entry is as fast and as simple as possible. */
- #ifdef configASSERT
- #define portDISABLE_INTERRUPTS() \
- { \
- uint32_t ulStatus; \
- /* Mask interrupts at and below the kernel interrupt priority. */ \
- ulStatus = ulPortGetCP0Status(); \
- /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
- if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
- { \
- ulStatus &= ~portALL_IPL_BITS; \
- vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
- } \
+configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
+those that end in FromISR. FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
+#ifdef configASSERT
+ #define portDISABLE_INTERRUPTS() \
+ { \
+ uint32_t ulStatus; \
+ /* Mask interrupts at and below the kernel interrupt priority. */ \
+ ulStatus = ulPortGetCP0Status(); \
+ /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
+ if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
+ { \
+ ulStatus &= ~portALL_IPL_BITS; \
+ vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+ } \
}
- #else /* configASSERT */
- #define portDISABLE_INTERRUPTS() \
- { \
- uint32_t ulStatus; \
- /* Mask interrupts at and below the kernel interrupt priority. */ \
- ulStatus = ulPortGetCP0Status(); \
- ulStatus &= ~portALL_IPL_BITS; \
- vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
- }
- #endif /* configASSERT */
+#else /* configASSERT */
+ #define portDISABLE_INTERRUPTS() \
+ { \
+ uint32_t ulStatus; \
+ /* Mask interrupts at and below the kernel interrupt priority. */ \
+ ulStatus = ulPortGetCP0Status(); \
+ ulStatus &= ~portALL_IPL_BITS; \
+ vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+ }
+#endif /* configASSERT */
- #define portENABLE_INTERRUPTS() \
- { \
- uint32_t ulStatus; \
- /* Unmask all interrupts. */ \
- ulStatus = ulPortGetCP0Status(); \
- ulStatus &= ~portALL_IPL_BITS; \
- vPortSetCP0Status( ulStatus ); \
- }
+#define portENABLE_INTERRUPTS() \
+{ \
+uint32_t ulStatus; \
+ /* Unmask all interrupts. */ \
+ ulStatus = ulPortGetCP0Status(); \
+ ulStatus &= ~portALL_IPL_BITS; \
+ vPortSetCP0Status( ulStatus ); \
+}
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portCRITICAL_NESTING_IN_TCB 1
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB 1
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
- extern UBaseType_t uxPortSetInterruptMaskFromISR();
- extern void vPortClearInterruptMaskFromISR( UBaseType_t );
- #define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+extern UBaseType_t uxPortSetInterruptMaskFromISR();
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
- #endif /* taskRECORD_READY_PRIORITY */
+#endif /* taskRECORD_READY_PRIORITY */
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portYIELD() \
- { \
- uint32_t ulCause; \
- /* Trigger software interrupt. */ \
- ulCause = ulPortGetCP0Cause(); \
- ulCause |= portSW0_BIT; \
- vPortSetCP0Cause( ulCause ); \
- }
+#define portYIELD() \
+{ \
+uint32_t ulCause; \
+ /* Trigger software interrupt. */ \
+ ulCause = ulPortGetCP0Cause(); \
+ ulCause |= portSW0_BIT; \
+ vPortSetCP0Cause( ulCause ); \
+}
- extern volatile UBaseType_t uxInterruptNesting;
- #define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+extern volatile UBaseType_t uxInterruptNesting;
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
- #define portNOP() __asm volatile ( "nop" )
+#define portNOP() __asm volatile ( "nop" )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- if( xSwitchRequired ) \
- { \
- portYIELD(); \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
+ { \
+ portYIELD(); \
+ }
/* Required by the kernel aware debugger. */
- #ifdef __DEBUG
- #define portREMOVE_STATIC_QUALIFIER
- #endif
+#ifdef __DEBUG
+ #define portREMOVE_STATIC_QUALIFIER
+#endif
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/MPLAB/PIC32MX/ISR_Support.h b/portable/MPLAB/PIC32MX/ISR_Support.h
index c826faf..1dab513 100644
--- a/portable/MPLAB/PIC32MX/ISR_Support.h
+++ b/portable/MPLAB/PIC32MX/ISR_Support.h
@@ -27,165 +27,165 @@
#include "FreeRTOSConfig.h"
-#define portCONTEXT_SIZE 132
-#define portEPC_STACK_LOCATION 124
-#define portSTATUS_STACK_LOCATION 128
+#define portCONTEXT_SIZE 132
+#define portEPC_STACK_LOCATION 124
+#define portSTATUS_STACK_LOCATION 128
/******************************************************************/
-.macro portSAVE_CONTEXT
+.macro portSAVE_CONTEXT
-/* Make room for the context. First save the current status so it can be
- * manipulated, and the cause and EPC registers so their original values are
- * captured. */
-mfc0 k0, _CP0_CAUSE
-addiu sp, sp, -portCONTEXT_SIZE
-mfc0 k1, _CP0_STATUS
+ /* Make room for the context. First save the current status so it can be
+ manipulated, and the cause and EPC registers so their original values are
+ captured. */
+ mfc0 k0, _CP0_CAUSE
+ addiu sp, sp, -portCONTEXT_SIZE
+ mfc0 k1, _CP0_STATUS
-/* Also save s6 and s5 so they can be used. Any nesting interrupts should
- * maintain the values of these registers across the ISR. */
-sw s6, 44 ( sp )
-sw s5, 40 ( sp )
-sw k1, portSTATUS_STACK_LOCATION( sp )
+ /* Also save s6 and s5 so they can be used. Any nesting interrupts should
+ maintain the values of these registers across the ISR. */
+ sw s6, 44(sp)
+ sw s5, 40(sp)
+ sw k1, portSTATUS_STACK_LOCATION(sp)
-/* Prepare to enable interrupts above the current priority. */
-srl k0, k0, 0xa
-ins k1, k0, 10, 6
-ins k1, zero, 1, 4
+ /* Prepare to enable interrupts above the current priority. */
+ srl k0, k0, 0xa
+ ins k1, k0, 10, 6
+ ins k1, zero, 1, 4
-/* s5 is used as the frame pointer. */
-add s5, zero, sp
+ /* s5 is used as the frame pointer. */
+ add s5, zero, sp
-/* Check the nesting count value. */
-la k0, uxInterruptNesting
-lw s6, ( k0 )
+ /* Check the nesting count value. */
+ la k0, uxInterruptNesting
+ lw s6, (k0)
-/* If the nesting count is 0 then swap to the the system stack, otherwise
- * the system stack is already being used. */
-bne s6, zero, 1f
-nop
+ /* If the nesting count is 0 then swap to the the system stack, otherwise
+ the system stack is already being used. */
+ bne s6, zero, 1f
+ nop
-/* Swap to the system stack. */
-la sp, xISRStackTop
-lw sp, ( sp )
+ /* Swap to the system stack. */
+ la sp, xISRStackTop
+ lw sp, (sp)
-/* Increment and save the nesting count. */
-1 : addiu s6, s6, 1
-sw s6, 0 ( k0 )
+ /* Increment and save the nesting count. */
+1: addiu s6, s6, 1
+ sw s6, 0(k0)
-/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-mfc0 s6, _CP0_EPC
+ /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+ mfc0 s6, _CP0_EPC
-/* Re-enable interrupts. */
-mtc0 k1, _CP0_STATUS
+ /* Re-enable interrupts. */
+ mtc0 k1, _CP0_STATUS
-/* Save the context into the space just created. s6 is saved again
- * here as it now contains the EPC value. No other s registers need be
- * saved. */
-sw ra, 120 ( s5 )
-sw s8, 116 ( s5 )
-sw t9, 112 ( s5 )
-sw t8, 108 ( s5 )
-sw t7, 104 ( s5 )
-sw t6, 100 ( s5 )
-sw t5, 96 ( s5 )
-sw t4, 92 ( s5 )
-sw t3, 88 ( s5 )
-sw t2, 84 ( s5 )
-sw t1, 80 ( s5 )
-sw t0, 76 ( s5 )
-sw a3, 72 ( s5 )
-sw a2, 68 ( s5 )
-sw a1, 64 ( s5 )
-sw a0, 60 ( s5 )
-sw v1, 56 ( s5 )
-sw v0, 52 ( s5 )
-sw s6, portEPC_STACK_LOCATION( s5 )
-sw $1, 16 ( s5 )
+ /* Save the context into the space just created. s6 is saved again
+ here as it now contains the EPC value. No other s registers need be
+ saved. */
+ sw ra, 120(s5)
+ sw s8, 116(s5)
+ sw t9, 112(s5)
+ sw t8, 108(s5)
+ sw t7, 104(s5)
+ sw t6, 100(s5)
+ sw t5, 96(s5)
+ sw t4, 92(s5)
+ sw t3, 88(s5)
+ sw t2, 84(s5)
+ sw t1, 80(s5)
+ sw t0, 76(s5)
+ sw a3, 72(s5)
+ sw a2, 68(s5)
+ sw a1, 64(s5)
+ sw a0, 60(s5)
+ sw v1, 56(s5)
+ sw v0, 52(s5)
+ sw s6, portEPC_STACK_LOCATION(s5)
+ sw $1, 16(s5)
-/* s6 is used as a scratch register. */
-mfhi s6
-sw s6, 12 ( s5 )
-mflo s6
-sw s6, 8 ( s5 )
+ /* s6 is used as a scratch register. */
+ mfhi s6
+ sw s6, 12(s5)
+ mflo s6
+ sw s6, 8(s5)
-/* Update the task stack pointer value if nesting is zero. */
-la s6, uxInterruptNesting
-lw s6, ( s6 )
-addiu s6, s6, -1
-bne s6, zero, 1f
-nop
+ /* Update the task stack pointer value if nesting is zero. */
+ la s6, uxInterruptNesting
+ lw s6, (s6)
+ addiu s6, s6, -1
+ bne s6, zero, 1f
+ nop
-/* Save the stack pointer. */
-la s6, uxSavedTaskStackPointer
-sw s5, ( s6 )
-1 :
-.endm
+ /* Save the stack pointer. */
+ la s6, uxSavedTaskStackPointer
+ sw s5, (s6)
+1:
+ .endm
/******************************************************************/
- .macro portRESTORE_CONTEXT
+.macro portRESTORE_CONTEXT
-/* Restore the stack pointer from the TCB. This is only done if the
- * nesting count is 1. */
-la s6, uxInterruptNesting
-lw s6, ( s6 )
-addiu s6, s6, -1
-bne s6, zero, 1f
-nop
-la s6, uxSavedTaskStackPointer
-lw s5, ( s6 )
+ /* Restore the stack pointer from the TCB. This is only done if the
+ nesting count is 1. */
+ la s6, uxInterruptNesting
+ lw s6, (s6)
+ addiu s6, s6, -1
+ bne s6, zero, 1f
+ nop
+ la s6, uxSavedTaskStackPointer
+ lw s5, (s6)
-/* Restore the context. */
-1 : lw s6, 8 ( s5 )
-mtlo s6
-lw s6, 12 ( s5 )
-mthi s6
-lw $1, 16 ( s5 )
+ /* Restore the context. */
+1: lw s6, 8(s5)
+ mtlo s6
+ lw s6, 12(s5)
+ mthi s6
+ lw $1, 16(s5)
+ /* s6 is loaded as it was used as a scratch register and therefore saved
+ as part of the interrupt context. */
+ lw s6, 44(s5)
+ lw v0, 52(s5)
+ lw v1, 56(s5)
+ lw a0, 60(s5)
+ lw a1, 64(s5)
+ lw a2, 68(s5)
+ lw a3, 72(s5)
+ lw t0, 76(s5)
+ lw t1, 80(s5)
+ lw t2, 84(s5)
+ lw t3, 88(s5)
+ lw t4, 92(s5)
+ lw t5, 96(s5)
+ lw t6, 100(s5)
+ lw t7, 104(s5)
+ lw t8, 108(s5)
+ lw t9, 112(s5)
+ lw s8, 116(s5)
+ lw ra, 120(s5)
-/* s6 is loaded as it was used as a scratch register and therefore saved
- * as part of the interrupt context. */
-lw s6, 44 ( s5 )
-lw v0, 52 ( s5 )
-lw v1, 56 ( s5 )
-lw a0, 60 ( s5 )
-lw a1, 64 ( s5 )
-lw a2, 68 ( s5 )
-lw a3, 72 ( s5 )
-lw t0, 76 ( s5 )
-lw t1, 80 ( s5 )
-lw t2, 84 ( s5 )
-lw t3, 88 ( s5 )
-lw t4, 92 ( s5 )
-lw t5, 96 ( s5 )
-lw t6, 100 ( s5 )
-lw t7, 104 ( s5 )
-lw t8, 108 ( s5 )
-lw t9, 112 ( s5 )
-lw s8, 116 ( s5 )
-lw ra, 120 ( s5 )
+ /* Protect access to the k registers, and others. */
+ di
+ ehb
-/* Protect access to the k registers, and others. */
-di
-ehb
+ /* Decrement the nesting count. */
+ la k0, uxInterruptNesting
+ lw k1, (k0)
+ addiu k1, k1, -1
+ sw k1, 0(k0)
-/* Decrement the nesting count. */
-la k0, uxInterruptNesting
-lw k1, ( k0 )
-addiu k1, k1, -1
-sw k1, 0 ( k0 )
+ lw k0, portSTATUS_STACK_LOCATION(s5)
+ lw k1, portEPC_STACK_LOCATION(s5)
-lw k0, portSTATUS_STACK_LOCATION( s5 )
-lw k1, portEPC_STACK_LOCATION( s5 )
+ /* Leave the stack in its original state. First load sp from s5, then
+ restore s5 from the stack. */
+ add sp, zero, s5
+ lw s5, 40(sp)
+ addiu sp, sp, portCONTEXT_SIZE
-/* Leave the stack in its original state. First load sp from s5, then
- * restore s5 from the stack. */
-add sp, zero, s5
-lw s5, 40 ( sp )
-addiu sp, sp, portCONTEXT_SIZE
+ mtc0 k0, _CP0_STATUS
+ mtc0 k1, _CP0_EPC
+ ehb
+ eret
+ nop
-mtc0 k0, _CP0_STATUS
-mtc0 k1, _CP0_EPC
-ehb
-eret
-nop
+ .endm
- .endm
diff --git a/portable/MPLAB/PIC32MX/port.c b/portable/MPLAB/PIC32MX/port.c
index 38ac85a..8ed86eb 100644
--- a/portable/MPLAB/PIC32MX/port.c
+++ b/portable/MPLAB/PIC32MX/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PIC32MX port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PIC32MX port.
+ *----------------------------------------------------------*/
#ifndef __XC
#error This port is designed to work with XC32. Please update your C compiler version.
@@ -38,80 +38,78 @@
#include "task.h"
/* Hardware specifics. */
-#define portTIMER_PRESCALE 8
-#define portPRESCALE_BITS 1
+#define portTIMER_PRESCALE 8
+#define portPRESCALE_BITS 1
/* Bits within various registers. */
-#define portIE_BIT ( 0x00000001 )
-#define portEXL_BIT ( 0x00000002 )
+#define portIE_BIT ( 0x00000001 )
+#define portEXL_BIT ( 0x00000002 )
/* Bits within the CAUSE register. */
-#define portCORE_SW_0 ( 0x00000100 )
-#define portCORE_SW_1 ( 0x00000200 )
+#define portCORE_SW_0 ( 0x00000100 )
+#define portCORE_SW_1 ( 0x00000200 )
/* The EXL bit is set to ensure interrupts do not occur while the context of
- * the first task is being restored. */
-#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
+the first task is being restored. */
+#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
/*
- * By default port.c generates its tick interrupt from TIMER1. The user can
- * override this behaviour by:
- * 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
- * which is the function that configures the timer. The function is defined
- * as a weak symbol in this file so if the same function name is used in the
- * application code then the version in the application code will be linked
- * into the application in preference to the version defined in this file.
- * 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
- * to generate the tick interrupt. For example, when timer 1 is used then
- * configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
- * configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
- * 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
- * timer used to generate the tick interrupt. For example, when timer 1 is
- * used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
- * IFS0CLR = _IFS0_T1IF_MASK.
- */
+By default port.c generates its tick interrupt from TIMER1. The user can
+override this behaviour by:
+ 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+ which is the function that configures the timer. The function is defined
+ as a weak symbol in this file so if the same function name is used in the
+ application code then the version in the application code will be linked
+ into the application in preference to the version defined in this file.
+ 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
+ to generate the tick interrupt. For example, when timer 1 is used then
+ configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
+ configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
+ 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
+ timer used to generate the tick interrupt. For example, when timer 1 is
+ used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
+ IFS0CLR = _IFS0_T1IF_MASK.
+*/
#ifndef configTICK_INTERRUPT_VECTOR
- #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
- #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
+ #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
+ #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
#else
- #ifndef configCLEAR_TICK_TIMER_INTERRUPT
- #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
- #endif
+ #ifndef configCLEAR_TICK_TIMER_INTERRUPT
+ #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
+ #endif
#endif
/* Let the user override the pre-loading of the initial RA with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
- * stack checking. A problem in the ISR stack will trigger an assert, not call the
- * stack overflow hook function (because the stack overflow hook is specific to a
- * task stack, not the ISR stack). */
-#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+stack checking. A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
-/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
- * the task stacks, and so will legitimately appear in many positions within
- * the ISR stack. */
- #define portISR_STACK_FILL_BYTE 0xee
+ /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+ the task stacks, and so will legitimately appear in many positions within
+ the ISR stack. */
+ #define portISR_STACK_FILL_BYTE 0xee
- static const uint8_t ucExpectedStackBytes[] =
- {
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
- }; \
+ static const uint8_t ucExpectedStackBytes[] = {
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
- #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
- /* Define the function away. */
- #define portCHECK_ISR_STACK()
+ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+ /* Define the function away. */
+ #define portCHECK_ISR_STACK()
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
/*-----------------------------------------------------------*/
@@ -123,7 +121,7 @@
* following line of code has no effect. The interrupt priority is set by the
* call to ConfigIntTimer1() in vApplicationSetupTickTimerInterrupt().
*/
-extern void __attribute__( ( interrupt( IPL1AUTO ), vector( configTICK_INTERRUPT_VECTOR ) ) ) vPortTickInterruptHandler( void );
+extern void __attribute__( (interrupt(IPL1AUTO), vector( configTICK_INTERRUPT_VECTOR ))) vPortTickInterruptHandler( void );
/*
* The software interrupt handler that performs the yield. Note that, because
@@ -131,7 +129,7 @@
* code has no effect. The interrupt priority is set by the call to
* mConfigIntCoreSW0() in xPortStartScheduler().
*/
-void __attribute__( ( interrupt( IPL1AUTO ), vector( _CORE_SOFTWARE_0_VECTOR ) ) ) vPortYieldISR( void );
+void __attribute__( (interrupt(IPL1AUTO), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void );
/*
* Used to catch tasks that attempt to return from their implementing function.
@@ -141,17 +139,17 @@
/*-----------------------------------------------------------*/
/* Records the interrupt nesting depth. This is initialised to one as it is
- * decremented to 0 when the first task starts. */
+decremented to 0 when the first task starts. */
volatile UBaseType_t uxInterruptNesting = 0x01;
/* Stores the task stack pointer when a switch is made to use the system stack. */
UBaseType_t uxSavedTaskStackPointer = 0;
/* The stack used by interrupt service routines that cause a context switch. */
-__attribute__( ( aligned( 8 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
/* The top of stack value ensures there is enough space to store 6 registers on
- * the callers stack, as some functions seem to want to do this. */
+the callers stack, as some functions seem to want to do this. */
const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
/*-----------------------------------------------------------*/
@@ -159,52 +157,47 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Ensure byte alignment is maintained when leaving this function. */
- pxTopOfStack--;
+ /* Ensure byte alignment is maintained when leaving this function. */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) _CP0_GET_CAUSE();
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
- pxTopOfStack -= 15;
+ *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
+ pxTopOfStack -= 15;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
- pxTopOfStack -= 15;
+ *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+ pxTopOfStack -= 15;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( uxSavedTaskStackPointer == 0UL );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( uxSavedTaskStackPointer == 0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
@@ -217,119 +210,123 @@
* vector number. When Timer 1 is used the vector number is defined as
* _TIMER_1_VECTOR.
*/
-__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
{
- const uint32_t ulCompareMatch = ( ( configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
+const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1;
- T1CON = 0x0000;
- T1CONbits.TCKPS = portPRESCALE_BITS;
- PR1 = ulCompareMatch;
- IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
+ T1CON = 0x0000;
+ T1CONbits.TCKPS = portPRESCALE_BITS;
+ PR1 = ulCompareMatch;
+ IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
- /* Clear the interrupt as a starting condition. */
- IFS0bits.T1IF = 0;
+ /* Clear the interrupt as a starting condition. */
+ IFS0bits.T1IF = 0;
- /* Enable the interrupt. */
- IEC0bits.T1IE = 1;
+ /* Enable the interrupt. */
+ IEC0bits.T1IE = 1;
- /* Start the timer. */
- T1CONbits.TON = 1;
+ /* Start the timer. */
+ T1CONbits.TON = 1;
}
/*-----------------------------------------------------------*/
-void vPortEndScheduler( void )
+void vPortEndScheduler(void)
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxInterruptNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( uxInterruptNesting == 1000UL );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
- extern void * pxCurrentTCB;
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
- #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
- {
- /* Fill the ISR stack to make it easy to asses how much is being used. */
- memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
- }
- #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+ #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+ {
+ /* Fill the ISR stack to make it easy to asses how much is being used. */
+ memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+ }
+ #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
- /* Clear the software interrupt flag. */
- IFS0CLR = _IFS0_CS0IF_MASK;
+ /* Clear the software interrupt flag. */
+ IFS0CLR = _IFS0_CS0IF_MASK;
- /* Set software timer priority. */
- IPC0CLR = _IPC0_CS0IP_MASK;
- IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
+ /* Set software timer priority. */
+ IPC0CLR = _IPC0_CS0IP_MASK;
+ IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
- /* Enable software interrupt. */
- IEC0CLR = _IEC0_CS0IE_MASK;
- IEC0SET = 1 << _IEC0_CS0IE_POSITION;
+ /* Enable software interrupt. */
+ IEC0CLR = _IEC0_CS0IE_MASK;
+ IEC0SET = 1 << _IEC0_CS0IE_POSITION;
- /* Setup the timer to generate the tick. Interrupts will have been
- * disabled by the time we get here. */
- vApplicationSetupTickTimerInterrupt();
+ /* Setup the timer to generate the tick. Interrupts will have been
+ disabled by the time we get here. */
+ vApplicationSetupTickTimerInterrupt();
- /* Kick off the highest priority task that has been created so far.
- * Its stack location is loaded into uxSavedTaskStackPointer. */
- uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
- vPortStartFirstTask();
+ /* Kick off the highest priority task that has been created so far.
+ Its stack location is loaded into uxSavedTaskStackPointer. */
+ uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
+ vPortStartFirstTask();
- /* Should never get here as the tasks will now be executing! Call the task
- * exit error function to prevent compiler warnings about a static function
- * not being called in the case that the application writer overrides this
- * functionality by defining configTASK_RETURN_ADDRESS. */
- prvTaskExitError();
+ /* Should never get here as the tasks will now be executing! Call the task
+ exit error function to prevent compiler warnings about a static function
+ not being called in the case that the application writer overrides this
+ functionality by defining configTASK_RETURN_ADDRESS. */
+ prvTaskExitError();
- return pdFALSE;
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortIncrementTick( void )
{
- UBaseType_t uxSavedStatus;
+UBaseType_t uxSavedStatus;
- uxSavedStatus = uxPortSetInterruptMaskFromISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Pend a context switch. */
- _CP0_BIS_CAUSE( portCORE_SW_0 );
- }
- }
- vPortClearInterruptMaskFromISR( uxSavedStatus );
+ uxSavedStatus = uxPortSetInterruptMaskFromISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ _CP0_BIS_CAUSE( portCORE_SW_0 );
+ }
+ }
+ vPortClearInterruptMaskFromISR( uxSavedStatus );
- /* Look for the ISR stack getting near or past its limit. */
- portCHECK_ISR_STACK();
+ /* Look for the ISR stack getting near or past its limit. */
+ portCHECK_ISR_STACK();
- /* Clear timer interrupt. */
- configCLEAR_TICK_TIMER_INTERRUPT();
+ /* Clear timer interrupt. */
+ configCLEAR_TICK_TIMER_INTERRUPT();
}
/*-----------------------------------------------------------*/
UBaseType_t uxPortSetInterruptMaskFromISR( void )
{
- UBaseType_t uxSavedStatusRegister;
+UBaseType_t uxSavedStatusRegister;
- __builtin_disable_interrupts();
- uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
+ __builtin_disable_interrupts();
+ uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
+ /* This clears the IPL bits, then sets them to
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
+ from an interrupt that has a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+ can only result in the IPL being unchanged or raised, and therefore never
+ lowered. */
+ _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
- /* This clears the IPL bits, then sets them to
- * configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
- * from an interrupt that has a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
- * can only result in the IPL being unchanged or raised, and therefore never
- * lowered. */
- _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
-
- return uxSavedStatusRegister;
+ return uxSavedStatusRegister;
}
/*-----------------------------------------------------------*/
void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
{
- _CP0_SET_STATUS( uxSavedStatusRegister );
+ _CP0_SET_STATUS( uxSavedStatusRegister );
}
/*-----------------------------------------------------------*/
+
+
+
+
+
diff --git a/portable/MPLAB/PIC32MX/portmacro.h b/portable/MPLAB/PIC32MX/portmacro.h
index 8b683fd..a578e58 100644
--- a/portable/MPLAB/PIC32MX/portmacro.h
+++ b/portable/MPLAB/PIC32MX/portmacro.h
@@ -26,14 +26,14 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/* System include files */
- #include <xc.h>
+#include <xc.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -46,159 +46,159 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Critical section management. */
- #define portIPL_SHIFT ( 10UL )
- #define portALL_IPL_BITS ( 0x3fUL << portIPL_SHIFT )
- #define portSW0_BIT ( 0x01 << 8 )
+#define portIPL_SHIFT ( 10UL )
+#define portALL_IPL_BITS ( 0x3fUL << portIPL_SHIFT )
+#define portSW0_BIT ( 0x01 << 8 )
/* This clears the IPL bits, then sets them to
- * configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
- * configASSERT() is defined to ensure an assertion handler does not inadvertently
- * attempt to lower the IPL when the call to assert was triggered because the IPL
- * value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
- * safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
- * those that end in FromISR. FreeRTOS maintains a separate interrupt API to
- * ensure API function and interrupt entry is as fast and as simple as possible. */
- #ifdef configASSERT
- #define portDISABLE_INTERRUPTS() \
- { \
- uint32_t ulStatus; \
- \
- /* Mask interrupts at and below the kernel interrupt priority. */ \
- ulStatus = _CP0_GET_STATUS(); \
- \
- /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
- if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
- { \
- ulStatus &= ~portALL_IPL_BITS; \
- _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
- } \
- }
- #else /* configASSERT */
- #define portDISABLE_INTERRUPTS() \
- { \
- uint32_t ulStatus; \
- \
- /* Mask interrupts at and below the kernel interrupt priority. */ \
- ulStatus = _CP0_GET_STATUS(); \
- ulStatus &= ~portALL_IPL_BITS; \
- _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
- }
- #endif /* configASSERT */
+configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
+those that end in FromISR. FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
+#ifdef configASSERT
+ #define portDISABLE_INTERRUPTS() \
+ { \
+ uint32_t ulStatus; \
+ \
+ /* Mask interrupts at and below the kernel interrupt priority. */ \
+ ulStatus = _CP0_GET_STATUS(); \
+ \
+ /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
+ if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
+ { \
+ ulStatus &= ~portALL_IPL_BITS; \
+ _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+ } \
+ }
+#else /* configASSERT */
+ #define portDISABLE_INTERRUPTS() \
+ { \
+ uint32_t ulStatus; \
+ \
+ /* Mask interrupts at and below the kernel interrupt priority. */ \
+ ulStatus = _CP0_GET_STATUS(); \
+ ulStatus &= ~portALL_IPL_BITS; \
+ _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+ }
+#endif /* configASSERT */
- #define portENABLE_INTERRUPTS() \
- { \
- uint32_t ulStatus; \
- \
- /* Unmask all interrupts. */ \
- ulStatus = _CP0_GET_STATUS(); \
- ulStatus &= ~portALL_IPL_BITS; \
- _CP0_SET_STATUS( ulStatus ); \
- }
+#define portENABLE_INTERRUPTS() \
+{ \
+uint32_t ulStatus; \
+ \
+ /* Unmask all interrupts. */ \
+ ulStatus = _CP0_GET_STATUS(); \
+ ulStatus &= ~portALL_IPL_BITS; \
+ _CP0_SET_STATUS( ulStatus ); \
+}
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portCRITICAL_NESTING_IN_TCB 1
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB 1
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
- extern UBaseType_t uxPortSetInterruptMaskFromISR();
- extern void vPortClearInterruptMaskFromISR( UBaseType_t );
- #define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+extern UBaseType_t uxPortSetInterruptMaskFromISR();
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
- #endif /* taskRECORD_READY_PRIORITY */
+#endif /* taskRECORD_READY_PRIORITY */
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portYIELD() \
- { \
- uint32_t ulCause; \
- \
- /* Trigger software interrupt. */ \
- ulCause = _CP0_GET_CAUSE(); \
- ulCause |= portSW0_BIT; \
- _CP0_SET_CAUSE( ulCause ); \
- }
+#define portYIELD() \
+{ \
+uint32_t ulCause; \
+ \
+ /* Trigger software interrupt. */ \
+ ulCause = _CP0_GET_CAUSE(); \
+ ulCause |= portSW0_BIT; \
+ _CP0_SET_CAUSE( ulCause ); \
+}
- extern volatile UBaseType_t uxInterruptNesting;
- #define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+extern volatile UBaseType_t uxInterruptNesting;
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
- #define portNOP() __asm volatile ( "nop" )
+#define portNOP() __asm volatile ( "nop" )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- if( xSwitchRequired ) \
- { \
- portYIELD(); \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
+ { \
+ portYIELD(); \
+ }
/* Required by the kernel aware debugger. */
- #ifdef __DEBUG
- #define portREMOVE_STATIC_QUALIFIER
- #endif
+#ifdef __DEBUG
+ #define portREMOVE_STATIC_QUALIFIER
+#endif
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/MPLAB/PIC32MZ/ISR_Support.h b/portable/MPLAB/PIC32MZ/ISR_Support.h
index 8cf035d..f0c2688 100644
--- a/portable/MPLAB/PIC32MZ/ISR_Support.h
+++ b/portable/MPLAB/PIC32MZ/ISR_Support.h
@@ -27,406 +27,406 @@
#include "FreeRTOSConfig.h"
-#define portCONTEXT_SIZE 160
-#define portEPC_STACK_LOCATION 152
-#define portSTATUS_STACK_LOCATION 156
-#define portFPCSR_STACK_LOCATION 0
-#define portTASK_HAS_FPU_STACK_LOCATION 0
-#define portFPU_CONTEXT_SIZE 264
+#define portCONTEXT_SIZE 160
+#define portEPC_STACK_LOCATION 152
+#define portSTATUS_STACK_LOCATION 156
+#define portFPCSR_STACK_LOCATION 0
+#define portTASK_HAS_FPU_STACK_LOCATION 0
+#define portFPU_CONTEXT_SIZE 264
/******************************************************************/
-.macro portSAVE_FPU_REGS offset, base
+.macro portSAVE_FPU_REGS offset, base
+ /* Macro to assist with saving just the FPU registers to the
+ * specified address and base offset,
+ * offset is a constant, base is the base pointer register */
-/* Macro to assist with saving just the FPU registers to the
- * specified address and base offset,
- * offset is a constant, base is the base pointer register */
+ sdc1 $f31, \offset + 248(\base)
+ sdc1 $f30, \offset + 240(\base)
+ sdc1 $f29, \offset + 232(\base)
+ sdc1 $f28, \offset + 224(\base)
+ sdc1 $f27, \offset + 216(\base)
+ sdc1 $f26, \offset + 208(\base)
+ sdc1 $f25, \offset + 200(\base)
+ sdc1 $f24, \offset + 192(\base)
+ sdc1 $f23, \offset + 184(\base)
+ sdc1 $f22, \offset + 176(\base)
+ sdc1 $f21, \offset + 168(\base)
+ sdc1 $f20, \offset + 160(\base)
+ sdc1 $f19, \offset + 152(\base)
+ sdc1 $f18, \offset + 144(\base)
+ sdc1 $f17, \offset + 136(\base)
+ sdc1 $f16, \offset + 128(\base)
+ sdc1 $f15, \offset + 120(\base)
+ sdc1 $f14, \offset + 112(\base)
+ sdc1 $f13, \offset + 104(\base)
+ sdc1 $f12, \offset + 96(\base)
+ sdc1 $f11, \offset + 88(\base)
+ sdc1 $f10, \offset + 80(\base)
+ sdc1 $f9, \offset + 72(\base)
+ sdc1 $f8, \offset + 64(\base)
+ sdc1 $f7, \offset + 56(\base)
+ sdc1 $f6, \offset + 48(\base)
+ sdc1 $f5, \offset + 40(\base)
+ sdc1 $f4, \offset + 32(\base)
+ sdc1 $f3, \offset + 24(\base)
+ sdc1 $f2, \offset + 16(\base)
+ sdc1 $f1, \offset + 8(\base)
+ sdc1 $f0, \offset + 0(\base)
-sdc1 $f31, \ offset + 248 ( \ base )
-sdc1 $f30, \ offset + 240 ( \ base )
-sdc1 $f29, \ offset + 232 ( \ base )
-sdc1 $f28, \ offset + 224 ( \ base )
-sdc1 $f27, \ offset + 216 ( \ base )
-sdc1 $f26, \ offset + 208 ( \ base )
-sdc1 $f25, \ offset + 200 ( \ base )
-sdc1 $f24, \ offset + 192 ( \ base )
-sdc1 $f23, \ offset + 184 ( \ base )
-sdc1 $f22, \ offset + 176 ( \ base )
-sdc1 $f21, \ offset + 168 ( \ base )
-sdc1 $f20, \ offset + 160 ( \ base )
-sdc1 $f19, \ offset + 152 ( \ base )
-sdc1 $f18, \ offset + 144 ( \ base )
-sdc1 $f17, \ offset + 136 ( \ base )
-sdc1 $f16, \ offset + 128 ( \ base )
-sdc1 $f15, \ offset + 120 ( \ base )
-sdc1 $f14, \ offset + 112 ( \ base )
-sdc1 $f13, \ offset + 104 ( \ base )
-sdc1 $f12, \ offset + 96 ( \ base )
-sdc1 $f11, \ offset + 88 ( \ base )
-sdc1 $f10, \ offset + 80 ( \ base )
-sdc1 $f9, \ offset + 72 ( \ base )
-sdc1 $f8, \ offset + 64 ( \ base )
-sdc1 $f7, \ offset + 56 ( \ base )
-sdc1 $f6, \ offset + 48 ( \ base )
-sdc1 $f5, \ offset + 40 ( \ base )
-sdc1 $f4, \ offset + 32 ( \ base )
-sdc1 $f3, \ offset + 24 ( \ base )
-sdc1 $f2, \ offset + 16 ( \ base )
-sdc1 $f1, \ offset + 8 ( \ base )
-sdc1 $f0, \ offset + 0 ( \ base )
-
- .endm
+ .endm
/******************************************************************/
- .macro portLOAD_FPU_REGS offset, base
+.macro portLOAD_FPU_REGS offset, base
+ /* Macro to assist with loading just the FPU registers from the
+ * specified address and base offset, offset is a constant,
+ * base is the base pointer register */
-/* Macro to assist with loading just the FPU registers from the
- * specified address and base offset, offset is a constant,
- * base is the base pointer register */
+ ldc1 $f0, \offset + 0(\base)
+ ldc1 $f1, \offset + 8(\base)
+ ldc1 $f2, \offset + 16(\base)
+ ldc1 $f3, \offset + 24(\base)
+ ldc1 $f4, \offset + 32(\base)
+ ldc1 $f5, \offset + 40(\base)
+ ldc1 $f6, \offset + 48(\base)
+ ldc1 $f7, \offset + 56(\base)
+ ldc1 $f8, \offset + 64(\base)
+ ldc1 $f9, \offset + 72(\base)
+ ldc1 $f10, \offset + 80(\base)
+ ldc1 $f11, \offset + 88(\base)
+ ldc1 $f12, \offset + 96(\base)
+ ldc1 $f13, \offset + 104(\base)
+ ldc1 $f14, \offset + 112(\base)
+ ldc1 $f15, \offset + 120(\base)
+ ldc1 $f16, \offset + 128(\base)
+ ldc1 $f17, \offset + 136(\base)
+ ldc1 $f18, \offset + 144(\base)
+ ldc1 $f19, \offset + 152(\base)
+ ldc1 $f20, \offset + 160(\base)
+ ldc1 $f21, \offset + 168(\base)
+ ldc1 $f22, \offset + 176(\base)
+ ldc1 $f23, \offset + 184(\base)
+ ldc1 $f24, \offset + 192(\base)
+ ldc1 $f25, \offset + 200(\base)
+ ldc1 $f26, \offset + 208(\base)
+ ldc1 $f27, \offset + 216(\base)
+ ldc1 $f28, \offset + 224(\base)
+ ldc1 $f29, \offset + 232(\base)
+ ldc1 $f30, \offset + 240(\base)
+ ldc1 $f31, \offset + 248(\base)
-ldc1 $f0, \ offset + 0 ( \ base )
-ldc1 $f1, \ offset + 8 ( \ base )
-ldc1 $f2, \ offset + 16 ( \ base )
-ldc1 $f3, \ offset + 24 ( \ base )
-ldc1 $f4, \ offset + 32 ( \ base )
-ldc1 $f5, \ offset + 40 ( \ base )
-ldc1 $f6, \ offset + 48 ( \ base )
-ldc1 $f7, \ offset + 56 ( \ base )
-ldc1 $f8, \ offset + 64 ( \ base )
-ldc1 $f9, \ offset + 72 ( \ base )
-ldc1 $f10, \ offset + 80 ( \ base )
-ldc1 $f11, \ offset + 88 ( \ base )
-ldc1 $f12, \ offset + 96 ( \ base )
-ldc1 $f13, \ offset + 104 ( \ base )
-ldc1 $f14, \ offset + 112 ( \ base )
-ldc1 $f15, \ offset + 120 ( \ base )
-ldc1 $f16, \ offset + 128 ( \ base )
-ldc1 $f17, \ offset + 136 ( \ base )
-ldc1 $f18, \ offset + 144 ( \ base )
-ldc1 $f19, \ offset + 152 ( \ base )
-ldc1 $f20, \ offset + 160 ( \ base )
-ldc1 $f21, \ offset + 168 ( \ base )
-ldc1 $f22, \ offset + 176 ( \ base )
-ldc1 $f23, \ offset + 184 ( \ base )
-ldc1 $f24, \ offset + 192 ( \ base )
-ldc1 $f25, \ offset + 200 ( \ base )
-ldc1 $f26, \ offset + 208 ( \ base )
-ldc1 $f27, \ offset + 216 ( \ base )
-ldc1 $f28, \ offset + 224 ( \ base )
-ldc1 $f29, \ offset + 232 ( \ base )
-ldc1 $f30, \ offset + 240 ( \ base )
-ldc1 $f31, \ offset + 248 ( \ base )
-
- .endm
+ .endm
/******************************************************************/
- .macro portSAVE_CONTEXT
+.macro portSAVE_CONTEXT
-/* Make room for the context. First save the current status so it can be
- * manipulated, and the cause and EPC registers so their original values are
- * captured. */
-mfc0 k0, _CP0_CAUSE
-addiu sp, sp, -portCONTEXT_SIZE
+ /* Make room for the context. First save the current status so it can be
+ manipulated, and the cause and EPC registers so their original values are
+ captured. */
+ mfc0 k0, _CP0_CAUSE
+ addiu sp, sp, -portCONTEXT_SIZE
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ /* Test if we are already using the system stack. Only tasks may use the
+ FPU so if we are already in a nested interrupt then the FPU context does
+ not require saving. */
+ la k1, uxInterruptNesting
+ lw k1, 0(k1)
+ bne k1, zero, 2f
+ nop
-/* Test if we are already using the system stack. Only tasks may use the
- * FPU so if we are already in a nested interrupt then the FPU context does
- * not require saving. */
- la k1, uxInterruptNesting
- lw k1, 0 ( k1 )
- bne k1, zero, 2f
- nop
+ /* Test if the current task needs the FPU context saving. */
+ la k1, ulTaskHasFPUContext
+ lw k1, 0(k1)
+ beq k1, zero, 1f
+ nop
-/* Test if the current task needs the FPU context saving. */
- la k1, ulTaskHasFPUContext
- lw k1, 0 ( k1 )
- beq k1, zero, 1f
- nop
+ /* Adjust the stack to account for the additional FPU context.*/
+ addiu sp, sp, -portFPU_CONTEXT_SIZE
-/* Adjust the stack to account for the additional FPU context.*/
- addiu sp, sp, -portFPU_CONTEXT_SIZE
+ 1:
+ /* Save the ulTaskHasFPUContext flag. */
+ sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
- 1 :
- /* Save the ulTaskHasFPUContext flag. */
- sw k1, portTASK_HAS_FPU_STACK_LOCATION( sp )
+ 2:
+ #endif
- 2 :
-#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+ mfc0 k1, _CP0_STATUS
-mfc0 k1, _CP0_STATUS
+ /* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
+ should maintain the values of these registers across the ISR. */
+ sw s7, 48(sp)
+ sw s6, 44(sp)
+ sw s5, 40(sp)
+ sw k1, portSTATUS_STACK_LOCATION(sp)
-/* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
- * should maintain the values of these registers across the ISR. */
-sw s7, 48 ( sp )
-sw s6, 44 ( sp )
-sw s5, 40 ( sp )
-sw k1, portSTATUS_STACK_LOCATION( sp )
+ /* Prepare to enable interrupts above the current priority. */
+ srl k0, k0, 0xa
+ ins k1, k0, 10, 7
+ srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
+ ins k1, k0, 18, 1
+ ins k1, zero, 1, 4
-/* Prepare to enable interrupts above the current priority. */
-srl k0, k0, 0xa
-ins k1, k0, 10, 7
-srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
-ins k1, k0, 18, 1
-ins k1, zero, 1, 4
+ /* s5 is used as the frame pointer. */
+ add s5, zero, sp
-/* s5 is used as the frame pointer. */
-add s5, zero, sp
+ /* Check the nesting count value. */
+ la k0, uxInterruptNesting
+ lw s6, (k0)
-/* Check the nesting count value. */
-la k0, uxInterruptNesting
-lw s6, ( k0 )
+ /* If the nesting count is 0 then swap to the the system stack, otherwise
+ the system stack is already being used. */
+ bne s6, zero, 1f
+ nop
-/* If the nesting count is 0 then swap to the the system stack, otherwise
- * the system stack is already being used. */
-bne s6, zero, 1f
-nop
+ /* Swap to the system stack. */
+ la sp, xISRStackTop
+ lw sp, (sp)
-/* Swap to the system stack. */
-la sp, xISRStackTop
-lw sp, ( sp )
+ /* Increment and save the nesting count. */
+1: addiu s6, s6, 1
+ sw s6, 0(k0)
-/* Increment and save the nesting count. */
-1 : addiu s6, s6, 1
-sw s6, 0 ( k0 )
+ /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+ mfc0 s6, _CP0_EPC
-/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-mfc0 s6, _CP0_EPC
+ /* Re-enable interrupts. */
+ mtc0 k1, _CP0_STATUS
-/* Re-enable interrupts. */
-mtc0 k1, _CP0_STATUS
+ /* Save the context into the space just created. s6 is saved again
+ here as it now contains the EPC value. No other s registers need be
+ saved. */
+ sw ra, 120(s5)
+ sw s8, 116(s5)
+ sw t9, 112(s5)
+ sw t8, 108(s5)
+ sw t7, 104(s5)
+ sw t6, 100(s5)
+ sw t5, 96(s5)
+ sw t4, 92(s5)
+ sw t3, 88(s5)
+ sw t2, 84(s5)
+ sw t1, 80(s5)
+ sw t0, 76(s5)
+ sw a3, 72(s5)
+ sw a2, 68(s5)
+ sw a1, 64(s5)
+ sw a0, 60(s5)
+ sw v1, 56(s5)
+ sw v0, 52(s5)
+ sw s6, portEPC_STACK_LOCATION(s5)
+ sw $1, 16(s5)
-/* Save the context into the space just created. s6 is saved again
- * here as it now contains the EPC value. No other s registers need be
- * saved. */
-sw ra, 120 ( s5 )
-sw s8, 116 ( s5 )
-sw t9, 112 ( s5 )
-sw t8, 108 ( s5 )
-sw t7, 104 ( s5 )
-sw t6, 100 ( s5 )
-sw t5, 96 ( s5 )
-sw t4, 92 ( s5 )
-sw t3, 88 ( s5 )
-sw t2, 84 ( s5 )
-sw t1, 80 ( s5 )
-sw t0, 76 ( s5 )
-sw a3, 72 ( s5 )
-sw a2, 68 ( s5 )
-sw a1, 64 ( s5 )
-sw a0, 60 ( s5 )
-sw v1, 56 ( s5 )
-sw v0, 52 ( s5 )
-sw s6, portEPC_STACK_LOCATION( s5 )
-sw $1, 16 ( s5 )
+ /* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a
+ scratch register. */
+ mfhi s6, $ac1
+ sw s6, 128(s5)
+ mflo s6, $ac1
+ sw s6, 124(s5)
-/* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a
- * scratch register. */
-mfhi s6, $ac1
-sw s6, 128 ( s5 )
-mflo s6, $ac1
-sw s6, 124 ( s5 )
+ mfhi s6, $ac2
+ sw s6, 136(s5)
+ mflo s6, $ac2
+ sw s6, 132(s5)
-mfhi s6, $ac2
-sw s6, 136 ( s5 )
-mflo s6, $ac2
-sw s6, 132 ( s5 )
+ mfhi s6, $ac3
+ sw s6, 144(s5)
+ mflo s6, $ac3
+ sw s6, 140(s5)
-mfhi s6, $ac3
-sw s6, 144 ( s5 )
-mflo s6, $ac3
-sw s6, 140 ( s5 )
+ /* Save the DSP Control register */
+ rddsp s6
+ sw s6, 148(s5)
-/* Save the DSP Control register */
-rddsp s6
-sw s6, 148 ( s5 )
+ /* ac0 is done separately to match the MX port. */
+ mfhi s6, $ac0
+ sw s6, 12(s5)
+ mflo s6, $ac0
+ sw s6, 8(s5)
-/* ac0 is done separately to match the MX port. */
-mfhi s6, $ac0
-sw s6, 12 ( s5 )
-mflo s6, $ac0
-sw s6, 8 ( s5 )
+ /* Save the FPU context if the nesting count was zero. */
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ la s6, uxInterruptNesting
+ lw s6, 0(s6)
+ addiu s6, s6, -1
+ bne s6, zero, 1f
+ nop
-/* Save the FPU context if the nesting count was zero. */
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
- la s6, uxInterruptNesting
- lw s6, 0 ( s6 )
- addiu s6, s6, -1
- bne s6, zero, 1f
- nop
+ /* Test if the current task needs the FPU context saving. */
+ lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
+ beq s6, zero, 1f
+ nop
-/* Test if the current task needs the FPU context saving. */
- lw s6, portTASK_HAS_FPU_STACK_LOCATION( s5 )
- beq s6, zero, 1f
- nop
- /* Save the FPU registers. */
- portSAVE_FPU_REGS( portCONTEXT_SIZE + 8 ), s5
+ /* Save the FPU registers. */
+ portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
-/* Save the FPU status register */
- cfc1 s6, $f31
- sw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )( s5 )
+ /* Save the FPU status register */
+ cfc1 s6, $f31
+ sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
- 1 :
-#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+ 1:
+ #endif
-/* Update the task stack pointer value if nesting is zero. */
-la s6, uxInterruptNesting
-lw s6, ( s6 )
-addiu s6, s6, -1
-bne s6, zero, 1f
-nop
+ /* Update the task stack pointer value if nesting is zero. */
+ la s6, uxInterruptNesting
+ lw s6, (s6)
+ addiu s6, s6, -1
+ bne s6, zero, 1f
+ nop
-/* Save the stack pointer. */
-la s6, uxSavedTaskStackPointer
-sw s5, ( s6 )
-1 :
-.endm
+ /* Save the stack pointer. */
+ la s6, uxSavedTaskStackPointer
+ sw s5, (s6)
+1:
+ .endm
/******************************************************************/
- .macro portRESTORE_CONTEXT
+.macro portRESTORE_CONTEXT
-/* Restore the stack pointer from the TCB. This is only done if the
- * nesting count is 1. */
-la s6, uxInterruptNesting
-lw s6, ( s6 )
-addiu s6, s6, -1
-bne s6, zero, 1f
-nop
-la s6, uxSavedTaskStackPointer
-lw s5, ( s6 )
+ /* Restore the stack pointer from the TCB. This is only done if the
+ nesting count is 1. */
+ la s6, uxInterruptNesting
+ lw s6, (s6)
+ addiu s6, s6, -1
+ bne s6, zero, 1f
+ nop
+ la s6, uxSavedTaskStackPointer
+ lw s5, (s6)
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
- /* Restore the FPU context if required. */
- lw s6, portTASK_HAS_FPU_STACK_LOCATION( s5 )
- beq s6, zero, 1f
- nop
- /* Restore the FPU registers. */
- portLOAD_FPU_REGS( portCONTEXT_SIZE + 8 ), s5
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ /* Restore the FPU context if required. */
+ lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
+ beq s6, zero, 1f
+ nop
-/* Restore the FPU status register. */
- lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )( s5 )
- ctc1 s6, $f31
-#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+ /* Restore the FPU registers. */
+ portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
-1 :
+ /* Restore the FPU status register. */
+ lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
+ ctc1 s6, $f31
+ #endif
-/* Restore the context. */
-lw s6, 128 ( s5 )
-mthi s6, $ac1
-lw s6, 124 ( s5 )
-mtlo s6, $ac1
+1:
-lw s6, 136 ( s5 )
-mthi s6, $ac2
-lw s6, 132 ( s5 )
-mtlo s6, $ac2
+ /* Restore the context. */
+ lw s6, 128(s5)
+ mthi s6, $ac1
+ lw s6, 124(s5)
+ mtlo s6, $ac1
-lw s6, 144 ( s5 )
-mthi s6, $ac3
-lw s6, 140 ( s5 )
-mtlo s6, $ac3
+ lw s6, 136(s5)
+ mthi s6, $ac2
+ lw s6, 132(s5)
+ mtlo s6, $ac2
-/* Restore DSPControl. */
-lw s6, 148 ( s5 )
-wrdsp s6
+ lw s6, 144(s5)
+ mthi s6, $ac3
+ lw s6, 140(s5)
+ mtlo s6, $ac3
-lw s6, 8 ( s5 )
-mtlo s6, $ac0
-lw s6, 12 ( s5 )
-mthi s6, $ac0
-lw $1, 16 ( s5 )
+ /* Restore DSPControl. */
+ lw s6, 148(s5)
+ wrdsp s6
-/* s6 is loaded as it was used as a scratch register and therefore saved
- * as part of the interrupt context. */
-lw s7, 48 ( s5 )
-lw s6, 44 ( s5 )
-lw v0, 52 ( s5 )
-lw v1, 56 ( s5 )
-lw a0, 60 ( s5 )
-lw a1, 64 ( s5 )
-lw a2, 68 ( s5 )
-lw a3, 72 ( s5 )
-lw t0, 76 ( s5 )
-lw t1, 80 ( s5 )
-lw t2, 84 ( s5 )
-lw t3, 88 ( s5 )
-lw t4, 92 ( s5 )
-lw t5, 96 ( s5 )
-lw t6, 100 ( s5 )
-lw t7, 104 ( s5 )
-lw t8, 108 ( s5 )
-lw t9, 112 ( s5 )
-lw s8, 116 ( s5 )
-lw ra, 120 ( s5 )
+ lw s6, 8(s5)
+ mtlo s6, $ac0
+ lw s6, 12(s5)
+ mthi s6, $ac0
+ lw $1, 16(s5)
-/* Protect access to the k registers, and others. */
-di
-ehb
+ /* s6 is loaded as it was used as a scratch register and therefore saved
+ as part of the interrupt context. */
+ lw s7, 48(s5)
+ lw s6, 44(s5)
+ lw v0, 52(s5)
+ lw v1, 56(s5)
+ lw a0, 60(s5)
+ lw a1, 64(s5)
+ lw a2, 68(s5)
+ lw a3, 72(s5)
+ lw t0, 76(s5)
+ lw t1, 80(s5)
+ lw t2, 84(s5)
+ lw t3, 88(s5)
+ lw t4, 92(s5)
+ lw t5, 96(s5)
+ lw t6, 100(s5)
+ lw t7, 104(s5)
+ lw t8, 108(s5)
+ lw t9, 112(s5)
+ lw s8, 116(s5)
+ lw ra, 120(s5)
-/* Decrement the nesting count. */
-la k0, uxInterruptNesting
-lw k1, ( k0 )
-addiu k1, k1, -1
-sw k1, 0 ( k0 )
+ /* Protect access to the k registers, and others. */
+ di
+ ehb
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
- /* If the nesting count is now zero then the FPU context may be restored. */
- bne k1, zero, 1f
- nop
+ /* Decrement the nesting count. */
+ la k0, uxInterruptNesting
+ lw k1, (k0)
+ addiu k1, k1, -1
+ sw k1, 0(k0)
-/* Restore the value of ulTaskHasFPUContext */
- la k0, ulTaskHasFPUContext
- lw k1, 0 ( s5 )
- sw k1, 0 ( k0 )
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ /* If the nesting count is now zero then the FPU context may be restored. */
+ bne k1, zero, 1f
+ nop
-/* If the task does not have an FPU context then adjust the stack normally. */
- beq k1, zero, 1f
- nop
+ /* Restore the value of ulTaskHasFPUContext */
+ la k0, ulTaskHasFPUContext
+ lw k1, 0(s5)
+ sw k1, 0(k0)
-/* Restore the STATUS and EPC registers */
- lw k0, portSTATUS_STACK_LOCATION( s5 )
- lw k1, portEPC_STACK_LOCATION( s5 )
+ /* If the task does not have an FPU context then adjust the stack normally. */
+ beq k1, zero, 1f
+ nop
-/* Leave the stack in its original state. First load sp from s5, then
- * restore s5 from the stack. */
- add sp, zero, s5
- lw s5, 40 ( sp )
+ /* Restore the STATUS and EPC registers */
+ lw k0, portSTATUS_STACK_LOCATION(s5)
+ lw k1, portEPC_STACK_LOCATION(s5)
-/* Adjust the stack pointer to remove the FPU context */
- addiu sp, sp, portFPU_CONTEXT_SIZE
- beq zero, zero, 2f
- nop
+ /* Leave the stack in its original state. First load sp from s5, then
+ restore s5 from the stack. */
+ add sp, zero, s5
+ lw s5, 40(sp)
- 1 : /* Restore the STATUS and EPC registers */
- lw k0, portSTATUS_STACK_LOCATION( s5 )
- lw k1, portEPC_STACK_LOCATION( s5 )
+ /* Adjust the stack pointer to remove the FPU context */
+ addiu sp, sp, portFPU_CONTEXT_SIZE
+ beq zero, zero, 2f
+ nop
-/* Leave the stack in its original state. First load sp from s5, then
- * restore s5 from the stack. */
- add sp, zero, s5
- lw s5, 40 ( sp )
+ 1: /* Restore the STATUS and EPC registers */
+ lw k0, portSTATUS_STACK_LOCATION(s5)
+ lw k1, portEPC_STACK_LOCATION(s5)
- 2 : /* Adjust the stack pointer */
- addiu sp, sp, portCONTEXT_SIZE
+ /* Leave the stack in its original state. First load sp from s5, then
+ restore s5 from the stack. */
+ add sp, zero, s5
+ lw s5, 40(sp)
-#else /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+ 2: /* Adjust the stack pointer */
+ addiu sp, sp, portCONTEXT_SIZE
-/* Restore the frame when there is no hardware FP support. */
- lw k0, portSTATUS_STACK_LOCATION( s5 )
- lw k1, portEPC_STACK_LOCATION( s5 )
+ #else
-/* Leave the stack in its original state. First load sp from s5, then
- * restore s5 from the stack. */
- add sp, zero, s5
- lw s5, 40 ( sp )
+ /* Restore the frame when there is no hardware FP support. */
+ lw k0, portSTATUS_STACK_LOCATION(s5)
+ lw k1, portEPC_STACK_LOCATION(s5)
- addiu sp, sp, portCONTEXT_SIZE
+ /* Leave the stack in its original state. First load sp from s5, then
+ restore s5 from the stack. */
+ add sp, zero, s5
+ lw s5, 40(sp)
-#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ addiu sp, sp, portCONTEXT_SIZE
-mtc0 k0, _CP0_STATUS
-mtc0 k1, _CP0_EPC
-ehb
-eret
-nop
+ #endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
- .endm
+ mtc0 k0, _CP0_STATUS
+ mtc0 k1, _CP0_EPC
+ ehb
+ eret
+ nop
+
+ .endm
+
diff --git a/portable/MPLAB/PIC32MZ/port.c b/portable/MPLAB/PIC32MZ/port.c
index 444aaec..028d35b 100644
--- a/portable/MPLAB/PIC32MZ/port.c
+++ b/portable/MPLAB/PIC32MZ/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PIC32MZ port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PIC32MZ port.
+ *----------------------------------------------------------*/
/* Microchip specific headers. */
#include <xc.h>
@@ -39,101 +39,99 @@
#include "FreeRTOS.h"
#include "task.h"
-#if !defined( __PIC32MZ__ )
+#if !defined(__PIC32MZ__)
#error This port is designed to work with XC32 on PIC32MZ MCUs. Please update your C compiler version or settings.
#endif
-#if ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
- #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
+#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
+ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
#endif
/* Hardware specifics. */
-#define portTIMER_PRESCALE 8
-#define portPRESCALE_BITS 1
+#define portTIMER_PRESCALE 8
+#define portPRESCALE_BITS 1
/* Bits within various registers. */
-#define portIE_BIT ( 0x00000001 )
-#define portEXL_BIT ( 0x00000002 )
-#define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */
-#define portCU1_BIT ( 0x20000000 ) /* enable CP1 for parts with hardware. */
-#define portFR_BIT ( 0x04000000 ) /* Enable 64 bit floating point registers. */
+#define portIE_BIT ( 0x00000001 )
+#define portEXL_BIT ( 0x00000002 )
+#define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */
+#define portCU1_BIT ( 0x20000000 ) /* enable CP1 for parts with hardware. */
+#define portFR_BIT ( 0x04000000 ) /* Enable 64 bit floating point registers. */
/* Bits within the CAUSE register. */
-#define portCORE_SW_0 ( 0x00000100 )
-#define portCORE_SW_1 ( 0x00000200 )
+#define portCORE_SW_0 ( 0x00000100 )
+#define portCORE_SW_1 ( 0x00000200 )
/* The EXL bit is set to ensure interrupts do not occur while the context of
- * the first task is being restored. */
+the first task is being restored. */
#if ( __mips_hard_float == 1 )
- #define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
+ #define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
#else
- #define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT )
+ #define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT )
#endif
/* The initial value to store into the FPU status and control register. This is
- * only used on parts that support a hardware FPU. */
-#define portINITIAL_FPSCR ( 0x1000000 ) /* High perf on denormal ops */
+ only used on parts that support a hardware FPU. */
+#define portINITIAL_FPSCR (0x1000000) /* High perf on denormal ops */
/*
- * By default port.c generates its tick interrupt from TIMER1. The user can
- * override this behaviour by:
- * 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
- * which is the function that configures the timer. The function is defined
- * as a weak symbol in this file so if the same function name is used in the
- * application code then the version in the application code will be linked
- * into the application in preference to the version defined in this file.
- * 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
- * to generate the tick interrupt. For example, when timer 1 is used then
- * configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
- * configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
- * 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
- * timer used to generate the tick interrupt. For example, when timer 1 is
- * used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
- * IFS0CLR = _IFS0_T1IF_MASK.
- */
+By default port.c generates its tick interrupt from TIMER1. The user can
+override this behaviour by:
+ 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+ which is the function that configures the timer. The function is defined
+ as a weak symbol in this file so if the same function name is used in the
+ application code then the version in the application code will be linked
+ into the application in preference to the version defined in this file.
+ 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
+ to generate the tick interrupt. For example, when timer 1 is used then
+ configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
+ configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
+ 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
+ timer used to generate the tick interrupt. For example, when timer 1 is
+ used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
+ IFS0CLR = _IFS0_T1IF_MASK.
+*/
#ifndef configTICK_INTERRUPT_VECTOR
- #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
- #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
+ #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
+ #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
#else
- #ifndef configCLEAR_TICK_TIMER_INTERRUPT
- #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
- #endif
+ #ifndef configCLEAR_TICK_TIMER_INTERRUPT
+ #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
+ #endif
#endif
/* Let the user override the pre-loading of the initial RA with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
- * stack checking. A problem in the ISR stack will trigger an assert, not call the
- * stack overflow hook function (because the stack overflow hook is specific to a
- * task stack, not the ISR stack). */
-#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+stack checking. A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
-/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
- * the task stacks, and so will legitimately appear in many positions within
- * the ISR stack. */
- #define portISR_STACK_FILL_BYTE 0xee
+ /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+ the task stacks, and so will legitimately appear in many positions within
+ the ISR stack. */
+ #define portISR_STACK_FILL_BYTE 0xee
- static const uint8_t ucExpectedStackBytes[] =
- {
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
- }; \
+ static const uint8_t ucExpectedStackBytes[] = {
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
- #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
- /* Define the function away. */
- #define portCHECK_ISR_STACK()
+ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+ /* Define the function away. */
+ #define portCHECK_ISR_STACK()
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
/*-----------------------------------------------------------*/
@@ -146,25 +144,25 @@
/*-----------------------------------------------------------*/
/* Records the interrupt nesting depth. This is initialised to one as it is
- * decremented to 0 when the first task starts. */
+decremented to 0 when the first task starts. */
volatile UBaseType_t uxInterruptNesting = 0x01;
/* Stores the task stack pointer when a switch is made to use the system stack. */
UBaseType_t uxSavedTaskStackPointer = 0;
/* The stack used by interrupt service routines that cause a context switch. */
-__attribute__( ( aligned( 8 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
/* The top of stack value ensures there is enough space to store 6 registers on
- * the callers stack, as some functions seem to want to do this. 8 byte alignment
- * is required to allow double word floating point stack pushes generated by the
- * compiler. */
+the callers stack, as some functions seem to want to do this. 8 byte alignment
+is required to allow double word floating point stack pushes generated by the
+compiler. */
const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
/* Saved as part of the task context. Set to pdFALSE if the task does not
- * require an FPU context. */
+ require an FPU context. */
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
- uint32_t ulTaskHasFPUContext = 0;
+ uint32_t ulTaskHasFPUContext = 0;
#endif
/*-----------------------------------------------------------*/
@@ -172,58 +170,53 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Ensure 8 byte alignment is maintained when leaving this function. */
- pxTopOfStack--;
- pxTopOfStack--;
+ /* Ensure 8 byte alignment is maintained when leaving this function. */
+ pxTopOfStack--;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) _CP0_GET_CAUSE();
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
- pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000; /* DSPControl */
- pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */
+ *pxTopOfStack = (StackType_t) 0x00000000; /* DSPControl */
+ pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
- pxTopOfStack -= 15;
+ *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
+ pxTopOfStack -= 15;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
- pxTopOfStack -= 15;
+ *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+ pxTopOfStack -= 15;
- *pxTopOfStack = ( StackType_t ) pdFALSE; /*by default disable FPU context save on parts with FPU */
+ *pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( uxSavedTaskStackPointer == 0UL );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( uxSavedTaskStackPointer == 0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
@@ -236,141 +229,144 @@
* vector number. When Timer 1 is used the vector number is defined as
* _TIMER_1_VECTOR.
*/
-__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
{
- const uint32_t ulCompareMatch = ( ( configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1UL;
+const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL;
- T1CON = 0x0000;
- T1CONbits.TCKPS = portPRESCALE_BITS;
- PR1 = ulCompareMatch;
- IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
+ T1CON = 0x0000;
+ T1CONbits.TCKPS = portPRESCALE_BITS;
+ PR1 = ulCompareMatch;
+ IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
- /* Clear the interrupt as a starting condition. */
- IFS0bits.T1IF = 0;
+ /* Clear the interrupt as a starting condition. */
+ IFS0bits.T1IF = 0;
- /* Enable the interrupt. */
- IEC0bits.T1IE = 1;
+ /* Enable the interrupt. */
+ IEC0bits.T1IE = 1;
- /* Start the timer. */
- T1CONbits.TON = 1;
+ /* Start the timer. */
+ T1CONbits.TON = 1;
}
/*-----------------------------------------------------------*/
-void vPortEndScheduler( void )
+void vPortEndScheduler(void)
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxInterruptNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( uxInterruptNesting == 1000UL );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vPortStartFirstTask( void );
- extern void * pxCurrentTCB;
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
- #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
- {
- /* Fill the ISR stack to make it easy to asses how much is being used. */
- memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
- }
- #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+ #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+ {
+ /* Fill the ISR stack to make it easy to asses how much is being used. */
+ memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+ }
+ #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
- /* Clear the software interrupt flag. */
- IFS0CLR = _IFS0_CS0IF_MASK;
+ /* Clear the software interrupt flag. */
+ IFS0CLR = _IFS0_CS0IF_MASK;
- /* Set software timer priority. */
- IPC0CLR = _IPC0_CS0IP_MASK;
- IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
+ /* Set software timer priority. */
+ IPC0CLR = _IPC0_CS0IP_MASK;
+ IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
- /* Enable software interrupt. */
- IEC0CLR = _IEC0_CS0IE_MASK;
- IEC0SET = 1 << _IEC0_CS0IE_POSITION;
+ /* Enable software interrupt. */
+ IEC0CLR = _IEC0_CS0IE_MASK;
+ IEC0SET = 1 << _IEC0_CS0IE_POSITION;
- /* Setup the timer to generate the tick. Interrupts will have been
- * disabled by the time we get here. */
- vApplicationSetupTickTimerInterrupt();
+ /* Setup the timer to generate the tick. Interrupts will have been
+ disabled by the time we get here. */
+ vApplicationSetupTickTimerInterrupt();
- /* Kick off the highest priority task that has been created so far.
- * Its stack location is loaded into uxSavedTaskStackPointer. */
- uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
- vPortStartFirstTask();
+ /* Kick off the highest priority task that has been created so far.
+ Its stack location is loaded into uxSavedTaskStackPointer. */
+ uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
+ vPortStartFirstTask();
- /* Should never get here as the tasks will now be executing! Call the task
- * exit error function to prevent compiler warnings about a static function
- * not being called in the case that the application writer overrides this
- * functionality by defining configTASK_RETURN_ADDRESS. */
- prvTaskExitError();
+ /* Should never get here as the tasks will now be executing! Call the task
+ exit error function to prevent compiler warnings about a static function
+ not being called in the case that the application writer overrides this
+ functionality by defining configTASK_RETURN_ADDRESS. */
+ prvTaskExitError();
- return pdFALSE;
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortIncrementTick( void )
{
- UBaseType_t uxSavedStatus;
+UBaseType_t uxSavedStatus;
- uxSavedStatus = uxPortSetInterruptMaskFromISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Pend a context switch. */
- _CP0_BIS_CAUSE( portCORE_SW_0 );
- }
- }
- vPortClearInterruptMaskFromISR( uxSavedStatus );
+ uxSavedStatus = uxPortSetInterruptMaskFromISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ _CP0_BIS_CAUSE( portCORE_SW_0 );
+ }
+ }
+ vPortClearInterruptMaskFromISR( uxSavedStatus );
- /* Look for the ISR stack getting near or past its limit. */
- portCHECK_ISR_STACK();
+ /* Look for the ISR stack getting near or past its limit. */
+ portCHECK_ISR_STACK();
- /* Clear timer interrupt. */
- configCLEAR_TICK_TIMER_INTERRUPT();
+ /* Clear timer interrupt. */
+ configCLEAR_TICK_TIMER_INTERRUPT();
}
/*-----------------------------------------------------------*/
UBaseType_t uxPortSetInterruptMaskFromISR( void )
{
- UBaseType_t uxSavedStatusRegister;
+UBaseType_t uxSavedStatusRegister;
- __builtin_disable_interrupts();
- uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
+ __builtin_disable_interrupts();
+ uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
+ /* This clears the IPL bits, then sets them to
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
+ from an interrupt that has a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+ can only result in the IPL being unchanged or raised, and therefore never
+ lowered. */
+ _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
- /* This clears the IPL bits, then sets them to
- * configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
- * from an interrupt that has a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
- * can only result in the IPL being unchanged or raised, and therefore never
- * lowered. */
- _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
-
- return uxSavedStatusRegister;
+ return uxSavedStatusRegister;
}
/*-----------------------------------------------------------*/
void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
{
- _CP0_SET_STATUS( uxSavedStatusRegister );
+ _CP0_SET_STATUS( uxSavedStatusRegister );
}
/*-----------------------------------------------------------*/
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
- void vPortTaskUsesFPU( void )
- {
- extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
+ void vPortTaskUsesFPU(void)
+ {
+ extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
- portENTER_CRITICAL();
+ portENTER_CRITICAL();
- /* Initialise the floating point status register. */
- vPortInitialiseFPSCR( portINITIAL_FPSCR );
+ /* Initialise the floating point status register. */
+ vPortInitialiseFPSCR(portINITIAL_FPSCR);
- /* A task is registering the fact that it needs a FPU context. Set the
- * FPU flag (saved as part of the task context). */
- ulTaskHasFPUContext = pdTRUE;
+ /* A task is registering the fact that it needs a FPU context. Set the
+ FPU flag (saved as part of the task context). */
+ ulTaskHasFPUContext = pdTRUE;
- portEXIT_CRITICAL();
- }
+ portEXIT_CRITICAL();
+ }
#endif /* __mips_hard_float == 1 */
/*-----------------------------------------------------------*/
+
+
+
+
diff --git a/portable/MPLAB/PIC32MZ/portmacro.h b/portable/MPLAB/PIC32MZ/portmacro.h
index d788440..65843cf 100644
--- a/portable/MPLAB/PIC32MZ/portmacro.h
+++ b/portable/MPLAB/PIC32MZ/portmacro.h
@@ -26,14 +26,14 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/* System include files */
- #include <xc.h>
+#include <xc.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -46,171 +46,170 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Critical section management. */
- #define portIPL_SHIFT ( 10UL )
-
+#define portIPL_SHIFT ( 10UL )
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
- * never have higher IPL bits set anyway. */
- #define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
- #define portSW0_BIT ( 0x01 << 8 )
+never have higher IPL bits set anyway. */
+#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
+#define portSW0_BIT ( 0x01 << 8 )
/* This clears the IPL bits, then sets them to
- * configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
- * configASSERT() is defined to ensure an assertion handler does not inadvertently
- * attempt to lower the IPL when the call to assert was triggered because the IPL
- * value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
- * safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
- * those that end in FromISR. FreeRTOS maintains a separate interrupt API to
- * ensure API function and interrupt entry is as fast and as simple as possible. */
- #ifdef configASSERT
- #define portDISABLE_INTERRUPTS() \
- { \
- uint32_t ulStatus; \
- \
- /* Mask interrupts at and below the kernel interrupt priority. */ \
- ulStatus = _CP0_GET_STATUS(); \
- \
- /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
- if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
- { \
- ulStatus &= ~portALL_IPL_BITS; \
- _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
- } \
- }
- #else /* configASSERT */
- #define portDISABLE_INTERRUPTS() \
- { \
- uint32_t ulStatus; \
- \
- /* Mask interrupts at and below the kernel interrupt priority. */ \
- ulStatus = _CP0_GET_STATUS(); \
- ulStatus &= ~portALL_IPL_BITS; \
- _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
- }
- #endif /* configASSERT */
+configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
+those that end in FromISR. FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
+#ifdef configASSERT
+ #define portDISABLE_INTERRUPTS() \
+ { \
+ uint32_t ulStatus; \
+ \
+ /* Mask interrupts at and below the kernel interrupt priority. */ \
+ ulStatus = _CP0_GET_STATUS(); \
+ \
+ /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
+ if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
+ { \
+ ulStatus &= ~portALL_IPL_BITS; \
+ _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+ } \
+ }
+#else /* configASSERT */
+ #define portDISABLE_INTERRUPTS() \
+ { \
+ uint32_t ulStatus; \
+ \
+ /* Mask interrupts at and below the kernel interrupt priority. */ \
+ ulStatus = _CP0_GET_STATUS(); \
+ ulStatus &= ~portALL_IPL_BITS; \
+ _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+ }
+#endif /* configASSERT */
- #define portENABLE_INTERRUPTS() \
- { \
- uint32_t ulStatus; \
- \
- /* Unmask all interrupts. */ \
- ulStatus = _CP0_GET_STATUS(); \
- ulStatus &= ~portALL_IPL_BITS; \
- _CP0_SET_STATUS( ulStatus ); \
- }
+#define portENABLE_INTERRUPTS() \
+{ \
+uint32_t ulStatus; \
+ \
+ /* Unmask all interrupts. */ \
+ ulStatus = _CP0_GET_STATUS(); \
+ ulStatus &= ~portALL_IPL_BITS; \
+ _CP0_SET_STATUS( ulStatus ); \
+}
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portCRITICAL_NESTING_IN_TCB 1
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB 1
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
- extern UBaseType_t uxPortSetInterruptMaskFromISR();
- extern void vPortClearInterruptMaskFromISR( UBaseType_t );
- #define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+extern UBaseType_t uxPortSetInterruptMaskFromISR();
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
- #if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
- #error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
- #endif
+#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ #error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
+#endif
- #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
- void vPortTaskUsesFPU( void );
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
- #endif
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ void vPortTaskUsesFPU( void );
+ #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#endif
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
- #endif /* taskRECORD_READY_PRIORITY */
+#endif /* taskRECORD_READY_PRIORITY */
/*-----------------------------------------------------------*/
/* Task utilities. */
- #define portYIELD() \
- { \
- uint32_t ulCause; \
- \
- /* Trigger software interrupt. */ \
- ulCause = _CP0_GET_CAUSE(); \
- ulCause |= portSW0_BIT; \
- _CP0_SET_CAUSE( ulCause ); \
- }
+#define portYIELD() \
+{ \
+uint32_t ulCause; \
+ \
+ /* Trigger software interrupt. */ \
+ ulCause = _CP0_GET_CAUSE(); \
+ ulCause |= portSW0_BIT; \
+ _CP0_SET_CAUSE( ulCause ); \
+}
- extern volatile UBaseType_t uxInterruptNesting;
- #define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+extern volatile UBaseType_t uxInterruptNesting;
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
- #define portNOP() __asm volatile ( "nop" )
+#define portNOP() __asm volatile ( "nop" )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- if( xSwitchRequired ) \
- { \
- portYIELD(); \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
+ { \
+ portYIELD(); \
+ }
/* Required by the kernel aware debugger. */
- #ifdef __DEBUG
- #define portREMOVE_STATIC_QUALIFIER
- #endif
+#ifdef __DEBUG
+ #define portREMOVE_STATIC_QUALIFIER
+#endif
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index 79cca49..982ef0d 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -33,19 +33,19 @@
#include "task.h"
#ifdef __GNUC__
- #include "mmsystem.h"
+ #include "mmsystem.h"
#else
- #pragma comment(lib, "winmm.lib")
+ #pragma comment(lib, "winmm.lib")
#endif
-#define portMAX_INTERRUPTS ( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portMAX_INTERRUPTS ( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* The priorities at which the various components of the simulation execute. */
-#define portDELETE_SELF_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */
-#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL
-#define portSIMULATED_TIMER_THREAD_PRIORITY THREAD_PRIORITY_HIGHEST
-#define portTASK_THREAD_PRIORITY THREAD_PRIORITY_ABOVE_NORMAL
+#define portDELETE_SELF_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */
+#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL
+#define portSIMULATED_TIMER_THREAD_PRIORITY THREAD_PRIORITY_HIGHEST
+#define portTASK_THREAD_PRIORITY THREAD_PRIORITY_ABOVE_NORMAL
/*
* Created as a high priority thread, this function uses a timer to simulate
@@ -86,47 +86,47 @@
/*-----------------------------------------------------------*/
/* The WIN32 simulator runs each task in a thread. The context switching is
- * managed by the threads, so the task stack does not have to be managed directly,
- * although the task stack is still used to hold an xThreadState structure this is
- * the only thing it will ever hold. The structure indirectly maps the task handle
- * to a thread handle. */
+managed by the threads, so the task stack does not have to be managed directly,
+although the task stack is still used to hold an xThreadState structure this is
+the only thing it will ever hold. The structure indirectly maps the task handle
+to a thread handle. */
typedef struct
{
- /* Handle of the thread that executes the task. */
- void * pvThread;
+ /* Handle of the thread that executes the task. */
+ void *pvThread;
- /* Event used to make sure the thread does not execute past a yield point
- * between the call to SuspendThread() to suspend the thread and the
- * asynchronous SuspendThread() operation actually being performed. */
- void * pvYieldEvent;
+ /* Event used to make sure the thread does not execute past a yield point
+ between the call to SuspendThread() to suspend the thread and the
+ asynchronous SuspendThread() operation actually being performed. */
+ void *pvYieldEvent;
} ThreadState_t;
/* Simulated interrupts waiting to be processed. This is a bit mask where each
- * bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */
+bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */
static volatile uint32_t ulPendingInterrupts = 0UL;
/* An event used to inform the simulated interrupt processing thread (a high
- * priority thread that simulated interrupt processing) that an interrupt is
- * pending. */
-static void * pvInterruptEvent = NULL;
+priority thread that simulated interrupt processing) that an interrupt is
+pending. */
+static void *pvInterruptEvent = NULL;
/* Mutex used to protect all the simulated interrupt variables that are accessed
- * by multiple threads. */
-static void * pvInterruptEventMutex = NULL;
+by multiple threads. */
+static void *pvInterruptEventMutex = NULL;
/* The critical nesting count for the currently executing task. This is
- * initialised to a non-zero value so interrupts do not become enabled during
- * the initialisation phase. As each task has its own critical nesting value
- * ulCriticalNesting will get set to zero when the first task runs. This
- * initialisation is probably not critical in this simulated environment as the
- * simulated interrupt handlers do not get created until the FreeRTOS scheduler is
- * started anyway. */
+initialised to a non-zero value so interrupts do not become enabled during
+the initialisation phase. As each task has its own critical nesting value
+ulCriticalNesting will get set to zero when the first task runs. This
+initialisation is probably not critical in this simulated environment as the
+simulated interrupt handlers do not get created until the FreeRTOS scheduler is
+started anyway. */
static volatile uint32_t ulCriticalNesting = 9999UL;
/* Handlers for all the simulated software interrupts. The first two positions
- * are used for the Yield and Tick interrupts so are handled slightly differently,
- * all the other interrupts can be user defined. */
-static uint32_t (* ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 };
+are used for the Yield and Tick interrupts so are handled slightly differently,
+all the other interrupts can be user defined. */
+static uint32_t (*ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 };
/* Pointer to the TCB of the currently executing task. */
extern void * volatile pxCurrentTCB;
@@ -138,572 +138,562 @@
static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter )
{
- TickType_t xMinimumWindowsBlockTime;
- TIMECAPS xTimeCaps;
+TickType_t xMinimumWindowsBlockTime;
+TIMECAPS xTimeCaps;
- /* Set the timer resolution to the maximum possible. */
- if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
- {
- xMinimumWindowsBlockTime = ( TickType_t ) xTimeCaps.wPeriodMin;
- timeBeginPeriod( xTimeCaps.wPeriodMin );
+ /* Set the timer resolution to the maximum possible. */
+ if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
+ {
+ xMinimumWindowsBlockTime = ( TickType_t ) xTimeCaps.wPeriodMin;
+ timeBeginPeriod( xTimeCaps.wPeriodMin );
- /* Register an exit handler so the timeBeginPeriod() function can be
- * matched with a timeEndPeriod() when the application exits. */
- SetConsoleCtrlHandler( prvEndProcess, TRUE );
- }
- else
- {
- xMinimumWindowsBlockTime = ( TickType_t ) 20;
- }
+ /* Register an exit handler so the timeBeginPeriod() function can be
+ matched with a timeEndPeriod() when the application exits. */
+ SetConsoleCtrlHandler( prvEndProcess, TRUE );
+ }
+ else
+ {
+ xMinimumWindowsBlockTime = ( TickType_t ) 20;
+ }
- /* Just to prevent compiler warnings. */
- ( void ) lpParameter;
+ /* Just to prevent compiler warnings. */
+ ( void ) lpParameter;
- for( ; ; )
- {
- /* Wait until the timer expires and we can access the simulated interrupt
- * variables. *NOTE* this is not a 'real time' way of generating tick
- * events as the next wake time should be relative to the previous wake
- * time, not the time that Sleep() is called. It is done this way to
- * prevent overruns in this very non real time simulated/emulated
- * environment. */
- if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime )
- {
- Sleep( xMinimumWindowsBlockTime );
- }
- else
- {
- Sleep( portTICK_PERIOD_MS );
- }
+ for( ;; )
+ {
+ /* Wait until the timer expires and we can access the simulated interrupt
+ variables. *NOTE* this is not a 'real time' way of generating tick
+ events as the next wake time should be relative to the previous wake
+ time, not the time that Sleep() is called. It is done this way to
+ prevent overruns in this very non real time simulated/emulated
+ environment. */
+ if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime )
+ {
+ Sleep( xMinimumWindowsBlockTime );
+ }
+ else
+ {
+ Sleep( portTICK_PERIOD_MS );
+ }
- configASSERT( xPortRunning );
+ configASSERT( xPortRunning );
- /* Can't proceed if in a critical section as pvInterruptEventMutex won't
- * be available. */
- WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+ /* Can't proceed if in a critical section as pvInterruptEventMutex won't
+ be available. */
+ WaitForSingleObject( pvInterruptEventMutex, INFINITE );
- /* The timer has expired, generate the simulated tick event. */
- ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
+ /* The timer has expired, generate the simulated tick event. */
+ ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
- /* The interrupt is now pending - notify the simulated interrupt
- * handler thread. Must be outside of a critical section to get here so
- * the handler thread can execute immediately pvInterruptEventMutex is
- * released. */
- configASSERT( ulCriticalNesting == 0UL );
- SetEvent( pvInterruptEvent );
+ /* The interrupt is now pending - notify the simulated interrupt
+ handler thread. Must be outside of a critical section to get here so
+ the handler thread can execute immediately pvInterruptEventMutex is
+ released. */
+ configASSERT( ulCriticalNesting == 0UL );
+ SetEvent( pvInterruptEvent );
- /* Give back the mutex so the simulated interrupt handler unblocks
- * and can access the interrupt handler variables. */
- ReleaseMutex( pvInterruptEventMutex );
- }
+ /* Give back the mutex so the simulated interrupt handler unblocks
+ and can access the interrupt handler variables. */
+ ReleaseMutex( pvInterruptEventMutex );
+ }
- #ifdef __GNUC__
-
- /* Should never reach here - MingW complains if you leave this line out,
- * MSVC complains if you put it in. */
- return 0;
- #endif
+ #ifdef __GNUC__
+ /* Should never reach here - MingW complains if you leave this line out,
+ MSVC complains if you put it in. */
+ return 0;
+ #endif
}
/*-----------------------------------------------------------*/
static BOOL WINAPI prvEndProcess( DWORD dwCtrlType )
{
- TIMECAPS xTimeCaps;
+TIMECAPS xTimeCaps;
- ( void ) dwCtrlType;
+ ( void ) dwCtrlType;
- if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
- {
- /* Match the call to timeBeginPeriod( xTimeCaps.wPeriodMin ) made when
- * the process started with a timeEndPeriod() as the process exits. */
- timeEndPeriod( xTimeCaps.wPeriodMin );
- }
+ if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
+ {
+ /* Match the call to timeBeginPeriod( xTimeCaps.wPeriodMin ) made when
+ the process started with a timeEndPeriod() as the process exits. */
+ timeEndPeriod( xTimeCaps.wPeriodMin );
+ }
- return pdFALSE;
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- ThreadState_t * pxThreadState = NULL;
- int8_t * pcTopOfStack = ( int8_t * ) pxTopOfStack;
- const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */
+ThreadState_t *pxThreadState = NULL;
+int8_t *pcTopOfStack = ( int8_t * ) pxTopOfStack;
+const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */
- /* In this simulated case a stack is not initialised, but instead a thread
- * is created that will execute the task being created. The thread handles
- * the context switching itself. The ThreadState_t object is placed onto
- * the stack that was created for the task - so the stack buffer is still
- * used, just not in the conventional way. It will not be used for anything
- * other than holding this structure. */
- pxThreadState = ( ThreadState_t * ) ( pcTopOfStack - sizeof( ThreadState_t ) );
+ /* In this simulated case a stack is not initialised, but instead a thread
+ is created that will execute the task being created. The thread handles
+ the context switching itself. The ThreadState_t object is placed onto
+ the stack that was created for the task - so the stack buffer is still
+ used, just not in the conventional way. It will not be used for anything
+ other than holding this structure. */
+ pxThreadState = ( ThreadState_t * ) ( pcTopOfStack - sizeof( ThreadState_t ) );
- /* Create the event used to prevent the thread from executing past its yield
- * point if the SuspendThread() call that suspends the thread does not take
- * effect immediately (it is an asynchronous call). */
- pxThreadState->pvYieldEvent = CreateEvent( NULL, /* Default security attributes. */
- FALSE, /* Auto reset. */
- FALSE, /* Start not signalled. */
- NULL ); /* No name. */
+ /* Create the event used to prevent the thread from executing past its yield
+ point if the SuspendThread() call that suspends the thread does not take
+ effect immediately (it is an asynchronous call). */
+ pxThreadState->pvYieldEvent = CreateEvent( NULL, /* Default security attributes. */
+ FALSE, /* Auto reset. */
+ FALSE, /* Start not signalled. */
+ NULL );/* No name. */
- /* Create the thread itself. */
- pxThreadState->pvThread = CreateThread( NULL, xStackSize, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED | STACK_SIZE_PARAM_IS_A_RESERVATION, NULL );
- configASSERT( pxThreadState->pvThread ); /* See comment where TerminateThread() is called. */
- SetThreadAffinityMask( pxThreadState->pvThread, 0x01 );
- SetThreadPriorityBoost( pxThreadState->pvThread, TRUE );
- SetThreadPriority( pxThreadState->pvThread, portTASK_THREAD_PRIORITY );
+ /* Create the thread itself. */
+ pxThreadState->pvThread = CreateThread( NULL, xStackSize, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED | STACK_SIZE_PARAM_IS_A_RESERVATION, NULL );
+ configASSERT( pxThreadState->pvThread ); /* See comment where TerminateThread() is called. */
+ SetThreadAffinityMask( pxThreadState->pvThread, 0x01 );
+ SetThreadPriorityBoost( pxThreadState->pvThread, TRUE );
+ SetThreadPriority( pxThreadState->pvThread, portTASK_THREAD_PRIORITY );
- return ( StackType_t * ) pxThreadState;
+ return ( StackType_t * ) pxThreadState;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- void * pvHandle = NULL;
- int32_t lSuccess;
- ThreadState_t * pxThreadState = NULL;
- SYSTEM_INFO xSystemInfo;
+void *pvHandle = NULL;
+int32_t lSuccess;
+ThreadState_t *pxThreadState = NULL;
+SYSTEM_INFO xSystemInfo;
- /* This port runs windows threads with extremely high priority. All the
- * threads execute on the same core - to prevent locking up the host only start
- * if the host has multiple cores. */
- GetSystemInfo( &xSystemInfo );
+ /* This port runs windows threads with extremely high priority. All the
+ threads execute on the same core - to prevent locking up the host only start
+ if the host has multiple cores. */
+ GetSystemInfo( &xSystemInfo );
+ if( xSystemInfo.dwNumberOfProcessors <= 1 )
+ {
+ printf( "This version of the FreeRTOS Windows port can only be used on multi-core hosts.\r\n" );
+ lSuccess = pdFAIL;
+ }
+ else
+ {
+ lSuccess = pdPASS;
- if( xSystemInfo.dwNumberOfProcessors <= 1 )
- {
- printf( "This version of the FreeRTOS Windows port can only be used on multi-core hosts.\r\n" );
- lSuccess = pdFAIL;
- }
- else
- {
- lSuccess = pdPASS;
+ /* The highest priority class is used to [try to] prevent other Windows
+ activity interfering with FreeRTOS timing too much. */
+ if( SetPriorityClass( GetCurrentProcess(), REALTIME_PRIORITY_CLASS ) == 0 )
+ {
+ printf( "SetPriorityClass() failed\r\n" );
+ }
- /* The highest priority class is used to [try to] prevent other Windows
- * activity interfering with FreeRTOS timing too much. */
- if( SetPriorityClass( GetCurrentProcess(), REALTIME_PRIORITY_CLASS ) == 0 )
- {
- printf( "SetPriorityClass() failed\r\n" );
- }
+ /* Install the interrupt handlers used by the scheduler itself. */
+ vPortSetInterruptHandler( portINTERRUPT_YIELD, prvProcessYieldInterrupt );
+ vPortSetInterruptHandler( portINTERRUPT_TICK, prvProcessTickInterrupt );
- /* Install the interrupt handlers used by the scheduler itself. */
- vPortSetInterruptHandler( portINTERRUPT_YIELD, prvProcessYieldInterrupt );
- vPortSetInterruptHandler( portINTERRUPT_TICK, prvProcessTickInterrupt );
+ /* Create the events and mutexes that are used to synchronise all the
+ threads. */
+ pvInterruptEventMutex = CreateMutex( NULL, FALSE, NULL );
+ pvInterruptEvent = CreateEvent( NULL, FALSE, FALSE, NULL );
- /* Create the events and mutexes that are used to synchronise all the
- * threads. */
- pvInterruptEventMutex = CreateMutex( NULL, FALSE, NULL );
- pvInterruptEvent = CreateEvent( NULL, FALSE, FALSE, NULL );
+ if( ( pvInterruptEventMutex == NULL ) || ( pvInterruptEvent == NULL ) )
+ {
+ lSuccess = pdFAIL;
+ }
- if( ( pvInterruptEventMutex == NULL ) || ( pvInterruptEvent == NULL ) )
- {
- lSuccess = pdFAIL;
- }
+ /* Set the priority of this thread such that it is above the priority of
+ the threads that run tasks. This higher priority is required to ensure
+ simulated interrupts take priority over tasks. */
+ pvHandle = GetCurrentThread();
+ if( pvHandle == NULL )
+ {
+ lSuccess = pdFAIL;
+ }
+ }
- /* Set the priority of this thread such that it is above the priority of
- * the threads that run tasks. This higher priority is required to ensure
- * simulated interrupts take priority over tasks. */
- pvHandle = GetCurrentThread();
+ if( lSuccess == pdPASS )
+ {
+ if( SetThreadPriority( pvHandle, portSIMULATED_INTERRUPTS_THREAD_PRIORITY ) == 0 )
+ {
+ lSuccess = pdFAIL;
+ }
+ SetThreadPriorityBoost( pvHandle, TRUE );
+ SetThreadAffinityMask( pvHandle, 0x01 );
+ }
- if( pvHandle == NULL )
- {
- lSuccess = pdFAIL;
- }
- }
+ if( lSuccess == pdPASS )
+ {
+ /* Start the thread that simulates the timer peripheral to generate
+ tick interrupts. The priority is set below that of the simulated
+ interrupt handler so the interrupt event mutex is used for the
+ handshake / overrun protection. */
+ pvHandle = CreateThread( NULL, 0, prvSimulatedPeripheralTimer, NULL, CREATE_SUSPENDED, NULL );
+ if( pvHandle != NULL )
+ {
+ SetThreadPriority( pvHandle, portSIMULATED_TIMER_THREAD_PRIORITY );
+ SetThreadPriorityBoost( pvHandle, TRUE );
+ SetThreadAffinityMask( pvHandle, 0x01 );
+ ResumeThread( pvHandle );
+ }
- if( lSuccess == pdPASS )
- {
- if( SetThreadPriority( pvHandle, portSIMULATED_INTERRUPTS_THREAD_PRIORITY ) == 0 )
- {
- lSuccess = pdFAIL;
- }
+ /* Start the highest priority task by obtaining its associated thread
+ state structure, in which is stored the thread handle. */
+ pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB );
+ ulCriticalNesting = portNO_CRITICAL_NESTING;
- SetThreadPriorityBoost( pvHandle, TRUE );
- SetThreadAffinityMask( pvHandle, 0x01 );
- }
+ /* Start the first task. */
+ ResumeThread( pxThreadState->pvThread );
- if( lSuccess == pdPASS )
- {
- /* Start the thread that simulates the timer peripheral to generate
- * tick interrupts. The priority is set below that of the simulated
- * interrupt handler so the interrupt event mutex is used for the
- * handshake / overrun protection. */
- pvHandle = CreateThread( NULL, 0, prvSimulatedPeripheralTimer, NULL, CREATE_SUSPENDED, NULL );
+ /* Handle all simulated interrupts - including yield requests and
+ simulated ticks. */
+ prvProcessSimulatedInterrupts();
+ }
- if( pvHandle != NULL )
- {
- SetThreadPriority( pvHandle, portSIMULATED_TIMER_THREAD_PRIORITY );
- SetThreadPriorityBoost( pvHandle, TRUE );
- SetThreadAffinityMask( pvHandle, 0x01 );
- ResumeThread( pvHandle );
- }
-
- /* Start the highest priority task by obtaining its associated thread
- * state structure, in which is stored the thread handle. */
- pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB );
- ulCriticalNesting = portNO_CRITICAL_NESTING;
-
- /* Start the first task. */
- ResumeThread( pxThreadState->pvThread );
-
- /* Handle all simulated interrupts - including yield requests and
- * simulated ticks. */
- prvProcessSimulatedInterrupts();
- }
-
- /* Would not expect to return from prvProcessSimulatedInterrupts(), so should
- * not get here. */
- return 0;
+ /* Would not expect to return from prvProcessSimulatedInterrupts(), so should
+ not get here. */
+ return 0;
}
/*-----------------------------------------------------------*/
static uint32_t prvProcessYieldInterrupt( void )
{
- /* Always return true as this is a yield. */
- return pdTRUE;
+ /* Always return true as this is a yield. */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
static uint32_t prvProcessTickInterrupt( void )
{
- uint32_t ulSwitchRequired;
+uint32_t ulSwitchRequired;
- /* Process the tick itself. */
- configASSERT( xPortRunning );
- ulSwitchRequired = ( uint32_t ) xTaskIncrementTick();
+ /* Process the tick itself. */
+ configASSERT( xPortRunning );
+ ulSwitchRequired = ( uint32_t ) xTaskIncrementTick();
- return ulSwitchRequired;
+ return ulSwitchRequired;
}
/*-----------------------------------------------------------*/
static void prvProcessSimulatedInterrupts( void )
{
- uint32_t ulSwitchRequired, i;
- ThreadState_t * pxThreadState;
- void * pvObjectList[ 2 ];
- CONTEXT xContext;
+uint32_t ulSwitchRequired, i;
+ThreadState_t *pxThreadState;
+void *pvObjectList[ 2 ];
+CONTEXT xContext;
- /* Going to block on the mutex that ensured exclusive access to the simulated
- * interrupt objects, and the event that signals that a simulated interrupt
- * should be processed. */
- pvObjectList[ 0 ] = pvInterruptEventMutex;
- pvObjectList[ 1 ] = pvInterruptEvent;
+ /* Going to block on the mutex that ensured exclusive access to the simulated
+ interrupt objects, and the event that signals that a simulated interrupt
+ should be processed. */
+ pvObjectList[ 0 ] = pvInterruptEventMutex;
+ pvObjectList[ 1 ] = pvInterruptEvent;
- /* Create a pending tick to ensure the first task is started as soon as
- * this thread pends. */
- ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
- SetEvent( pvInterruptEvent );
+ /* Create a pending tick to ensure the first task is started as soon as
+ this thread pends. */
+ ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
+ SetEvent( pvInterruptEvent );
- xPortRunning = pdTRUE;
+ xPortRunning = pdTRUE;
- for( ; ; )
- {
- xInsideInterrupt = pdFALSE;
- WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, INFINITE );
+ for(;;)
+ {
+ xInsideInterrupt = pdFALSE;
+ WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, INFINITE );
- /* Cannot be in a critical section to get here. Tasks that exit a
- * critical section will block on a yield mutex to wait for an interrupt to
- * process if an interrupt was set pending while the task was inside the
- * critical section. xInsideInterrupt prevents interrupts that contain
- * critical sections from doing the same. */
- xInsideInterrupt = pdTRUE;
+ /* Cannot be in a critical section to get here. Tasks that exit a
+ critical section will block on a yield mutex to wait for an interrupt to
+ process if an interrupt was set pending while the task was inside the
+ critical section. xInsideInterrupt prevents interrupts that contain
+ critical sections from doing the same. */
+ xInsideInterrupt = pdTRUE;
- /* Used to indicate whether the simulated interrupt processing has
- * necessitated a context switch to another task/thread. */
- ulSwitchRequired = pdFALSE;
+ /* Used to indicate whether the simulated interrupt processing has
+ necessitated a context switch to another task/thread. */
+ ulSwitchRequired = pdFALSE;
- /* For each interrupt we are interested in processing, each of which is
- * represented by a bit in the 32bit ulPendingInterrupts variable. */
- for( i = 0; i < portMAX_INTERRUPTS; i++ )
- {
- /* Is the simulated interrupt pending? */
- if( ( ulPendingInterrupts & ( 1UL << i ) ) != 0 )
- {
- /* Is a handler installed? */
- if( ulIsrHandler[ i ] != NULL )
- {
- /* Run the actual handler. Handlers return pdTRUE if they
- * necessitate a context switch. */
- if( ulIsrHandler[ i ]() != pdFALSE )
- {
- /* A bit mask is used purely to help debugging. */
- ulSwitchRequired |= ( 1 << i );
- }
- }
+ /* For each interrupt we are interested in processing, each of which is
+ represented by a bit in the 32bit ulPendingInterrupts variable. */
+ for( i = 0; i < portMAX_INTERRUPTS; i++ )
+ {
+ /* Is the simulated interrupt pending? */
+ if( ( ulPendingInterrupts & ( 1UL << i ) ) != 0 )
+ {
+ /* Is a handler installed? */
+ if( ulIsrHandler[ i ] != NULL )
+ {
+ /* Run the actual handler. Handlers return pdTRUE if they
+ necessitate a context switch. */
+ if( ulIsrHandler[ i ]() != pdFALSE )
+ {
+ /* A bit mask is used purely to help debugging. */
+ ulSwitchRequired |= ( 1 << i );
+ }
+ }
- /* Clear the interrupt pending bit. */
- ulPendingInterrupts &= ~( 1UL << i );
- }
- }
+ /* Clear the interrupt pending bit. */
+ ulPendingInterrupts &= ~( 1UL << i );
+ }
+ }
- if( ulSwitchRequired != pdFALSE )
- {
- void * pvOldCurrentTCB;
+ if( ulSwitchRequired != pdFALSE )
+ {
+ void *pvOldCurrentTCB;
- pvOldCurrentTCB = pxCurrentTCB;
+ pvOldCurrentTCB = pxCurrentTCB;
- /* Select the next task to run. */
- vTaskSwitchContext();
+ /* Select the next task to run. */
+ vTaskSwitchContext();
- /* If the task selected to enter the running state is not the task
- * that is already in the running state. */
- if( pvOldCurrentTCB != pxCurrentTCB )
- {
- /* Suspend the old thread. In the cases where the (simulated)
- * interrupt is asynchronous (tick event swapping a task out rather
- * than a task blocking or yielding) it doesn't matter if the
- * 'suspend' operation doesn't take effect immediately - if it
- * doesn't it would just be like the interrupt occurring slightly
- * later. In cases where the yield was caused by a task blocking
- * or yielding then the task will block on a yield event after the
- * yield operation in case the 'suspend' operation doesn't take
- * effect immediately. */
- pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pvOldCurrentTCB );
- SuspendThread( pxThreadState->pvThread );
+ /* If the task selected to enter the running state is not the task
+ that is already in the running state. */
+ if( pvOldCurrentTCB != pxCurrentTCB )
+ {
+ /* Suspend the old thread. In the cases where the (simulated)
+ interrupt is asynchronous (tick event swapping a task out rather
+ than a task blocking or yielding) it doesn't matter if the
+ 'suspend' operation doesn't take effect immediately - if it
+ doesn't it would just be like the interrupt occurring slightly
+ later. In cases where the yield was caused by a task blocking
+ or yielding then the task will block on a yield event after the
+ yield operation in case the 'suspend' operation doesn't take
+ effect immediately. */
+ pxThreadState = ( ThreadState_t *) *( ( size_t * ) pvOldCurrentTCB );
+ SuspendThread( pxThreadState->pvThread );
- /* Ensure the thread is actually suspended by performing a
- * synchronous operation that can only complete when the thread is
- * actually suspended. The below code asks for dummy register
- * data. Experimentation shows that these two lines don't appear
- * to do anything now, but according to
- * https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743
- * they do - so as they do not harm (slight run-time hit). */
- xContext.ContextFlags = CONTEXT_INTEGER;
- ( void ) GetThreadContext( pxThreadState->pvThread, &xContext );
+ /* Ensure the thread is actually suspended by performing a
+ synchronous operation that can only complete when the thread is
+ actually suspended. The below code asks for dummy register
+ data. Experimentation shows that these two lines don't appear
+ to do anything now, but according to
+ https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743
+ they do - so as they do not harm (slight run-time hit). */
+ xContext.ContextFlags = CONTEXT_INTEGER;
+ ( void ) GetThreadContext( pxThreadState->pvThread, &xContext );
- /* Obtain the state of the task now selected to enter the
- * Running state. */
- pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pxCurrentTCB );
+ /* Obtain the state of the task now selected to enter the
+ Running state. */
+ pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB );
- /* pxThreadState->pvThread can be NULL if the task deleted
- * itself - but a deleted task should never be resumed here. */
- configASSERT( pxThreadState->pvThread != NULL );
- ResumeThread( pxThreadState->pvThread );
- }
- }
+ /* pxThreadState->pvThread can be NULL if the task deleted
+ itself - but a deleted task should never be resumed here. */
+ configASSERT( pxThreadState->pvThread != NULL );
+ ResumeThread( pxThreadState->pvThread );
+ }
+ }
- /* If the thread that is about to be resumed stopped running
- * because it yielded then it will wait on an event when it resumed
- * (to ensure it does not continue running after the call to
- * SuspendThread() above as SuspendThread() is asynchronous).
- * Signal the event to ensure the thread can proceed now it is
- * valid for it to do so. Signaling the event is benign in the case that
- * the task was switched out asynchronously by an interrupt as the event
- * is reset before the task blocks on it. */
- pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pxCurrentTCB );
- SetEvent( pxThreadState->pvYieldEvent );
- ReleaseMutex( pvInterruptEventMutex );
- }
+ /* If the thread that is about to be resumed stopped running
+ because it yielded then it will wait on an event when it resumed
+ (to ensure it does not continue running after the call to
+ SuspendThread() above as SuspendThread() is asynchronous).
+ Signal the event to ensure the thread can proceed now it is
+ valid for it to do so. Signaling the event is benign in the case that
+ the task was switched out asynchronously by an interrupt as the event
+ is reset before the task blocks on it. */
+ pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB );
+ SetEvent( pxThreadState->pvYieldEvent );
+ ReleaseMutex( pvInterruptEventMutex );
+ }
}
/*-----------------------------------------------------------*/
-void vPortDeleteThread( void * pvTaskToDelete )
+void vPortDeleteThread( void *pvTaskToDelete )
{
- ThreadState_t * pxThreadState;
- uint32_t ulErrorCode;
+ThreadState_t *pxThreadState;
+uint32_t ulErrorCode;
- /* Remove compiler warnings if configASSERT() is not defined. */
- ( void ) ulErrorCode;
+ /* Remove compiler warnings if configASSERT() is not defined. */
+ ( void ) ulErrorCode;
- /* Find the handle of the thread being deleted. */
- pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pvTaskToDelete );
+ /* Find the handle of the thread being deleted. */
+ pxThreadState = ( ThreadState_t * ) ( *( size_t *) pvTaskToDelete );
- /* Check that the thread is still valid, it might have been closed by
- * vPortCloseRunningThread() - which will be the case if the task associated
- * with the thread originally deleted itself rather than being deleted by a
- * different task. */
- if( pxThreadState->pvThread != NULL )
- {
- WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+ /* Check that the thread is still valid, it might have been closed by
+ vPortCloseRunningThread() - which will be the case if the task associated
+ with the thread originally deleted itself rather than being deleted by a
+ different task. */
+ if( pxThreadState->pvThread != NULL )
+ {
+ WaitForSingleObject( pvInterruptEventMutex, INFINITE );
- /* !!! This is not a nice way to terminate a thread, and will eventually
- * result in resources being depleted if tasks frequently delete other
- * tasks (rather than deleting themselves) as the task stacks will not be
- * freed. */
- ulErrorCode = TerminateThread( pxThreadState->pvThread, 0 );
- configASSERT( ulErrorCode );
+ /* !!! This is not a nice way to terminate a thread, and will eventually
+ result in resources being depleted if tasks frequently delete other
+ tasks (rather than deleting themselves) as the task stacks will not be
+ freed. */
+ ulErrorCode = TerminateThread( pxThreadState->pvThread, 0 );
+ configASSERT( ulErrorCode );
- ulErrorCode = CloseHandle( pxThreadState->pvThread );
- configASSERT( ulErrorCode );
+ ulErrorCode = CloseHandle( pxThreadState->pvThread );
+ configASSERT( ulErrorCode );
- ReleaseMutex( pvInterruptEventMutex );
- }
+ ReleaseMutex( pvInterruptEventMutex );
+ }
}
/*-----------------------------------------------------------*/
-void vPortCloseRunningThread( void * pvTaskToDelete,
- volatile BaseType_t * pxPendYield )
+void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield )
{
- ThreadState_t * pxThreadState;
- void * pvThread;
- uint32_t ulErrorCode;
+ThreadState_t *pxThreadState;
+void *pvThread;
+uint32_t ulErrorCode;
- /* Remove compiler warnings if configASSERT() is not defined. */
- ( void ) ulErrorCode;
+ /* Remove compiler warnings if configASSERT() is not defined. */
+ ( void ) ulErrorCode;
- /* Find the handle of the thread being deleted. */
- pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pvTaskToDelete );
- pvThread = pxThreadState->pvThread;
+ /* Find the handle of the thread being deleted. */
+ pxThreadState = ( ThreadState_t * ) ( *( size_t *) pvTaskToDelete );
+ pvThread = pxThreadState->pvThread;
- /* Raise the Windows priority of the thread to ensure the FreeRTOS scheduler
- * does not run and swap it out before it is closed. If that were to happen
- * the thread would never run again and effectively be a thread handle and
- * memory leak. */
- SetThreadPriority( pvThread, portDELETE_SELF_THREAD_PRIORITY );
+ /* Raise the Windows priority of the thread to ensure the FreeRTOS scheduler
+ does not run and swap it out before it is closed. If that were to happen
+ the thread would never run again and effectively be a thread handle and
+ memory leak. */
+ SetThreadPriority( pvThread, portDELETE_SELF_THREAD_PRIORITY );
- /* This function will not return, therefore a yield is set as pending to
- * ensure a context switch occurs away from this thread on the next tick. */
- *pxPendYield = pdTRUE;
+ /* This function will not return, therefore a yield is set as pending to
+ ensure a context switch occurs away from this thread on the next tick. */
+ *pxPendYield = pdTRUE;
- /* Mark the thread associated with this task as invalid so
- * vPortDeleteThread() does not try to terminate it. */
- pxThreadState->pvThread = NULL;
+ /* Mark the thread associated with this task as invalid so
+ vPortDeleteThread() does not try to terminate it. */
+ pxThreadState->pvThread = NULL;
- /* Close the thread. */
- ulErrorCode = CloseHandle( pvThread );
- configASSERT( ulErrorCode );
+ /* Close the thread. */
+ ulErrorCode = CloseHandle( pvThread );
+ configASSERT( ulErrorCode );
- /* This is called from a critical section, which must be exited before the
- * thread stops. */
- taskEXIT_CRITICAL();
- CloseHandle( pxThreadState->pvYieldEvent );
- ExitThread( 0 );
+ /* This is called from a critical section, which must be exited before the
+ thread stops. */
+ taskEXIT_CRITICAL();
+ CloseHandle( pxThreadState->pvYieldEvent );
+ ExitThread( 0 );
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- exit( 0 );
+ exit( 0 );
}
/*-----------------------------------------------------------*/
void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber )
{
- ThreadState_t * pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB );
+ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB );
- configASSERT( xPortRunning );
+ configASSERT( xPortRunning );
- if( ( ulInterruptNumber < portMAX_INTERRUPTS ) && ( pvInterruptEventMutex != NULL ) )
- {
- WaitForSingleObject( pvInterruptEventMutex, INFINITE );
- ulPendingInterrupts |= ( 1 << ulInterruptNumber );
+ if( ( ulInterruptNumber < portMAX_INTERRUPTS ) && ( pvInterruptEventMutex != NULL ) )
+ {
+ WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+ ulPendingInterrupts |= ( 1 << ulInterruptNumber );
- /* The simulated interrupt is now held pending, but don't actually
- * process it yet if this call is within a critical section. It is
- * possible for this to be in a critical section as calls to wait for
- * mutexes are accumulative. If in a critical section then the event
- * will get set when the critical section nesting count is wound back
- * down to zero. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- SetEvent( pvInterruptEvent );
+ /* The simulated interrupt is now held pending, but don't actually
+ process it yet if this call is within a critical section. It is
+ possible for this to be in a critical section as calls to wait for
+ mutexes are accumulative. If in a critical section then the event
+ will get set when the critical section nesting count is wound back
+ down to zero. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ SetEvent( pvInterruptEvent );
- /* Going to wait for an event - make sure the event is not already
- * signaled. */
- ResetEvent( pxThreadState->pvYieldEvent );
- }
+ /* Going to wait for an event - make sure the event is not already
+ signaled. */
+ ResetEvent( pxThreadState->pvYieldEvent );
+ }
- ReleaseMutex( pvInterruptEventMutex );
-
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* An interrupt was pended so ensure to block to allow it to
- * execute. In most cases the (simulated) interrupt will have
- * executed before the next line is reached - so this is just to make
- * sure. */
- WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE );
- }
- }
+ ReleaseMutex( pvInterruptEventMutex );
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* An interrupt was pended so ensure to block to allow it to
+ execute. In most cases the (simulated) interrupt will have
+ executed before the next line is reached - so this is just to make
+ sure. */
+ WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE );
+ }
+ }
}
/*-----------------------------------------------------------*/
-void vPortSetInterruptHandler( uint32_t ulInterruptNumber,
- uint32_t ( * pvHandler )( void ) )
+void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) )
{
- if( ulInterruptNumber < portMAX_INTERRUPTS )
- {
- if( pvInterruptEventMutex != NULL )
- {
- WaitForSingleObject( pvInterruptEventMutex, INFINITE );
- ulIsrHandler[ ulInterruptNumber ] = pvHandler;
- ReleaseMutex( pvInterruptEventMutex );
- }
- else
- {
- ulIsrHandler[ ulInterruptNumber ] = pvHandler;
- }
- }
+ if( ulInterruptNumber < portMAX_INTERRUPTS )
+ {
+ if( pvInterruptEventMutex != NULL )
+ {
+ WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+ ulIsrHandler[ ulInterruptNumber ] = pvHandler;
+ ReleaseMutex( pvInterruptEventMutex );
+ }
+ else
+ {
+ ulIsrHandler[ ulInterruptNumber ] = pvHandler;
+ }
+ }
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- if( xPortRunning == pdTRUE )
- {
- /* The interrupt event mutex is held for the entire critical section,
- * effectively disabling (simulated) interrupts. */
- WaitForSingleObject( pvInterruptEventMutex, INFINITE );
- }
+ if( xPortRunning == pdTRUE )
+ {
+ /* The interrupt event mutex is held for the entire critical section,
+ effectively disabling (simulated) interrupts. */
+ WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+ }
- ulCriticalNesting++;
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- int32_t lMutexNeedsReleasing;
+int32_t lMutexNeedsReleasing;
- /* The interrupt event mutex should already be held by this thread as it was
- * obtained on entry to the critical section. */
- lMutexNeedsReleasing = pdTRUE;
+ /* The interrupt event mutex should already be held by this thread as it was
+ obtained on entry to the critical section. */
+ lMutexNeedsReleasing = pdTRUE;
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ ulCriticalNesting--;
- /* Don't need to wait for any pending interrupts to execute if the
- * critical section was exited from inside an interrupt. */
- if( ( ulCriticalNesting == portNO_CRITICAL_NESTING ) && ( xInsideInterrupt == pdFALSE ) )
- {
- /* Were any interrupts set to pending while interrupts were
- * (simulated) disabled? */
- if( ulPendingInterrupts != 0UL )
- {
- ThreadState_t * pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB );
+ /* Don't need to wait for any pending interrupts to execute if the
+ critical section was exited from inside an interrupt. */
+ if( ( ulCriticalNesting == portNO_CRITICAL_NESTING ) && ( xInsideInterrupt == pdFALSE ) )
+ {
+ /* Were any interrupts set to pending while interrupts were
+ (simulated) disabled? */
+ if( ulPendingInterrupts != 0UL )
+ {
+ ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB );
- configASSERT( xPortRunning );
+ configASSERT( xPortRunning );
- /* The interrupt won't actually executed until
- * pvInterruptEventMutex is released as it waits on both
- * pvInterruptEventMutex and pvInterruptEvent.
- * pvInterruptEvent is only set when the simulated
- * interrupt is pended if the interrupt is pended
- * from outside a critical section - hence it is set
- * here. */
- SetEvent( pvInterruptEvent );
+ /* The interrupt won't actually executed until
+ pvInterruptEventMutex is released as it waits on both
+ pvInterruptEventMutex and pvInterruptEvent.
+ pvInterruptEvent is only set when the simulated
+ interrupt is pended if the interrupt is pended
+ from outside a critical section - hence it is set
+ here. */
+ SetEvent( pvInterruptEvent );
+ /* The calling task is going to wait for an event to ensure the
+ interrupt that is pending executes immediately after the
+ critical section is exited - so make sure the event is not
+ already signaled. */
+ ResetEvent( pxThreadState->pvYieldEvent );
- /* The calling task is going to wait for an event to ensure the
- * interrupt that is pending executes immediately after the
- * critical section is exited - so make sure the event is not
- * already signaled. */
- ResetEvent( pxThreadState->pvYieldEvent );
+ /* Mutex will be released now so the (simulated) interrupt can
+ execute, so does not require releasing on function exit. */
+ lMutexNeedsReleasing = pdFALSE;
+ ReleaseMutex( pvInterruptEventMutex );
+ WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE );
+ }
+ }
+ }
- /* Mutex will be released now so the (simulated) interrupt can
- * execute, so does not require releasing on function exit. */
- lMutexNeedsReleasing = pdFALSE;
- ReleaseMutex( pvInterruptEventMutex );
- WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE );
- }
- }
- }
-
- if( pvInterruptEventMutex != NULL )
- {
- if( lMutexNeedsReleasing == pdTRUE )
- {
- configASSERT( xPortRunning );
- ReleaseMutex( pvInterruptEventMutex );
- }
- }
+ if( pvInterruptEventMutex != NULL )
+ {
+ if( lMutexNeedsReleasing == pdTRUE )
+ {
+ configASSERT( xPortRunning );
+ ReleaseMutex( pvInterruptEventMutex );
+ }
+ }
}
/*-----------------------------------------------------------*/
+
diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index c2a528e..91a8a0a 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -32,121 +32,119 @@
#include <WinBase.h>
/******************************************************************************
-* Defines
+ Defines
******************************************************************************/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE size_t
-#define portBASE_TYPE long
-#define portPOINTER_SIZE_TYPE size_t
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE size_t
+#define portBASE_TYPE long
+#define portPOINTER_SIZE_TYPE size_t
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick
- * count do not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+ /* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick
+ count do not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
#endif
/* Hardware specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portINLINE __inline
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portINLINE __inline
-#if defined( __x86_64__ ) || defined( _M_X64 )
- #define portBYTE_ALIGNMENT 8
+#if defined( __x86_64__) || defined( _M_X64 )
+ #define portBYTE_ALIGNMENT 8
#else
- #define portBYTE_ALIGNMENT 4
+ #define portBYTE_ALIGNMENT 4
#endif
-#define portYIELD() vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD )
+#define portYIELD() vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD )
extern volatile BaseType_t xInsideInterrupt;
-#define portSOFTWARE_BARRIER() while( xInsideInterrupt != pdFALSE )
+#define portSOFTWARE_BARRIER() while( xInsideInterrupt != pdFALSE )
/* Simulated interrupts return pdFALSE if no context switch should be performed,
- * or a non-zero number if a context switch should be performed. */
-#define portYIELD_FROM_ISR( x ) ( void ) x
-#define portEND_SWITCHING_ISR( x ) portYIELD_FROM_ISR( ( x ) )
+or a non-zero number if a context switch should be performed. */
+#define portYIELD_FROM_ISR( x ) ( void ) x
+#define portEND_SWITCHING_ISR( x ) portYIELD_FROM_ISR( ( x ) )
-void vPortCloseRunningThread( void * pvTaskToDelete,
- volatile BaseType_t * pxPendYield );
-void vPortDeleteThread( void * pvThreadToDelete );
-#define portCLEAN_UP_TCB( pxTCB ) vPortDeleteThread( pxTCB )
-#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) )
-#define portDISABLE_INTERRUPTS() vPortEnterCritical()
-#define portENABLE_INTERRUPTS() vPortExitCritical()
+void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield );
+void vPortDeleteThread( void *pvThreadToDelete );
+#define portCLEAN_UP_TCB( pxTCB ) vPortDeleteThread( pxTCB )
+#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) )
+#define portDISABLE_INTERRUPTS() vPortEnterCritical()
+#define portENABLE_INTERRUPTS() vPortExitCritical()
/* Critical section handling. */
void vPortEnterCritical( void );
void vPortExitCritical( void );
-#define portENTER_CRITICAL() vPortEnterCritical()
-#define portEXIT_CRITICAL() vPortExitCritical()
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #ifdef __GNUC__
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
- __asm volatile ( "bsr %1, %0\n\t" \
- : "=r" ( uxTopPriority ) : "rm" ( uxReadyPriorities ) : "cc" )
- #else
-
-/* BitScanReverse returns the bit position of the most significant '1'
- * in the word. */
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) )
- #endif /* __GNUC__ */
+ #ifdef __GNUC__
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
+ __asm volatile( "bsr %1, %0\n\t" \
+ :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
+ #else
+ /* BitScanReverse returns the bit position of the most significant '1'
+ in the word. */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) )
+ #endif /* __GNUC__ */
#endif /* taskRECORD_READY_PRIORITY */
#ifndef __GNUC__
- __pragma( warning( disable: 4211 ) ) /* Nonstandard extension used, as extern is only nonstandard to MSVC. */
+ __pragma( warning( disable:4211 ) ) /* Nonstandard extension used, as extern is only nonstandard to MSVC. */
#endif
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portINTERRUPT_YIELD ( 0UL )
-#define portINTERRUPT_TICK ( 1UL )
+#define portINTERRUPT_YIELD ( 0UL )
+#define portINTERRUPT_TICK ( 1UL )
/*
* Raise a simulated interrupt represented by the bit mask in ulInterruptMask.
* Each bit can be used to represent an individual interrupt - with the first
* two bits being used for the Yield and Tick interrupts respectively.
- */
+*/
void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber );
/*
@@ -158,7 +156,7 @@
* Interrupt handler functions must return a non-zero value if executing the
* handler resulted in a task switch being required.
*/
-void vPortSetInterruptHandler( uint32_t ulInterruptNumber,
- uint32_t ( * pvHandler )( void ) );
+void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) );
-#endif /* ifndef PORTMACRO_H */
+#endif
+
diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c
index 73b62c4..e61fc40 100644
--- a/portable/MikroC/ARM_CM4F/port.c
+++ b/portable/MikroC/ARM_CM4F/port.c
@@ -246,15 +246,17 @@
void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF
{
__asm {
- ldr r3, = _pxCurrentTCB /* Restore the context. */
- ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+/* *INDENT-OFF* */
+ ldr r3, =_pxCurrentTCB /* Restore the context. */
+ ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
ldm r0 !, ( r4 - r11, r14 ) /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
msr psp, r0 /* Restore the task stack pointer. */
isb
- mov r0, # 0
+ mov r0, #0
msr basepri, r0
bx r14
+/* *INDENT-ON* */
};
}
/*-----------------------------------------------------------*/
@@ -262,8 +264,9 @@
static void prvPortStartFirstTask( void )
{
__asm {
- ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */
- ldr r0, [ r0 ]
+/* *INDENT-OFF* */
+ ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
+ ldr r0, [ r0 ]
ldr r0, [ r0 ]
msr msp, r0 /* Set the msp back to the start of the stack. */
@@ -271,14 +274,15 @@
* before the scheduler was started - which would otherwise result in the
* unnecessary leaving of space in the SVC stack for lazy saving of FPU
* registers. */
- mov r0, # 0
+ mov r0, #0
msr control, r0
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
- svc # 0 /* System call to start first task. */
+ svc #0 /* System call to start first task. */
nop
+/* *INDENT-ON* */
};
}
/*-----------------------------------------------------------*/
@@ -432,18 +436,19 @@
{
__asm {
#ifdef HW_DEBUG
+/* *INDENT-OFF* */
/* The function is not truly naked, so add back the 4 bytes subtracted
- * from the stack pointer by the function prologue. */
+ * from the stack pointer by the function prologue. */
add sp, sp, # 4
#endif
mrs r0, psp
isb
- ldr r3, = _pxCurrentTCB /* Get the location of the current TCB. */
- ldr r2, [ r3 ]
+ ldr r3, =_pxCurrentTCB /* Get the location of the current TCB. */
+ ldr r2, [ r3 ]
- tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
+ tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
it eq
vstmdbeq r0 !, ( s16 - s31 )
@@ -453,12 +458,12 @@
stmdb sp !, ( r0, r3 )
ldr r0, = _ucMaxSyscallInterruptPriority
- ldr r1, [ r0 ]
+ ldr r1, [ r0 ]
msr basepri, r1
dsb
isb
bl _vTaskSwitchContext
- mov r0, # 0
+ mov r0, #0
msr basepri, r0
ldm sp !, ( r0, r3 )
@@ -467,13 +472,14 @@
ldm r0 !, ( r4 - r11, r14 ) /* Pop the core registers. */
- tst r14, # 0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
+ tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
it eq
vldmiaeq r0 !, ( s16 - s31 )
msr psp, r0
isb
bx r14
+/* *INDENT-ON* */
}
}
/*-----------------------------------------------------------*/
@@ -499,7 +505,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) )
+ #if ( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) )
void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
@@ -694,14 +700,14 @@
}
}
-#endif /* #if configUSE_TICKLESS_IDLE */
+ #endif /* #if configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
-#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+ #if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
void vPortSetupTimerInterrupt( void )
{
@@ -723,19 +729,21 @@
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
-#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+ #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vPortEnableVFP( void )
{
__asm {
- ldr r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */
- ldr r1, [ r0 ]
+/* *INDENT-OFF* */
+ ldr r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
+ ldr r1, [ r0 ]
- orr r1, r1, # 0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */
+ orr r1, r1, #0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */
str r1, [ r0 ]
bx r14
+/* *INDENT-ON* */
};
}
/*-----------------------------------------------------------*/
@@ -758,7 +766,7 @@
}
/*-----------------------------------------------------------*/
-#if ( configASSERT_DEFINED == 1 )
+ #if ( configASSERT_DEFINED == 1 )
/* Limitations in the MikroC inline asm means ulCurrentInterrupt has to be
* global - which makes vPortValidateInterruptPriority() non re-entrant.
@@ -772,11 +780,13 @@
{
/* Obtain the number of the currently executing interrupt. */
__asm {
+/* *INDENT-OFF* */
push( r0, r1 )
mrs r0, ipsr
- ldr r1, = _ulCurrentInterrupt
- str r0, [ r1 ]
+ ldr r1, =_ulCurrentInterrupt
+ str r0, [ r1 ]
pop( r0, r1 )
+/* *INDENT-ON* */
};
/* Is the interrupt number a user defined interrupt? */
@@ -827,4 +837,4 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* configASSERT_DEFINED */
+ #endif /* configASSERT_DEFINED */
diff --git a/portable/Paradigm/Tern_EE/large_untested/port.c b/portable/Paradigm/Tern_EE/large_untested/port.c
index a7c6d8b..fb727e0 100644
--- a/portable/Paradigm/Tern_EE/large_untested/port.c
+++ b/portable/Paradigm/Tern_EE/large_untested/port.c
@@ -27,9 +27,9 @@
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Tern EE 186
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Tern EE 186
+ * port.
+ *----------------------------------------------------------*/
/* Library includes. */
#include <embedded.h>
@@ -41,200 +41,199 @@
#include "portasm.h"
/* The timer increments every four clocks, hence the divide by 4. */
-#define portTIMER_COMPARE ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 )
+#define portTIMER_COMPARE ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 )
/* From the RDC data sheet. */
-#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe001
+#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe001
/* Interrupt control. */
-#define portEIO_REGISTER 0xff22
-#define portCLEAR_INTERRUPT 0x0008
+#define portEIO_REGISTER 0xff22
+#define portCLEAR_INTERRUPT 0x0008
/* Setup the hardware to generate the required tick frequency. */
static void prvSetupTimerInterrupt( void );
/* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
- static void __interrupt __far prvPreemptiveTick( void );
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+ /* Tick service routine used by the scheduler when preemptive scheduling is
+ being used. */
+ static void __interrupt __far prvPreemptiveTick( void );
#else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
- static void __interrupt __far prvNonPreemptiveTick( void );
+ /* Tick service routine used by the scheduler when cooperative scheduling is
+ being used. */
+ static void __interrupt __far prvNonPreemptiveTick( void );
#endif
/* Trap routine used by taskYIELD() to manually cause a context switch. */
static void __interrupt __far prvYieldProcessor( void );
/* The timer initialisation functions leave interrupts enabled,
- * which is not what we want. This ISR is installed temporarily in case
- * the timer fires before we get a change to disable interrupts again. */
+which is not what we want. This ISR is installed temporarily in case
+the timer fires before we get a change to disable interrupts again. */
static void __interrupt __far prvDummyISR( void );
/*-----------------------------------------------------------*/
/* See header file for description. */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t DS_Reg = 0;
+StackType_t DS_Reg = 0;
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging. */
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
- *pxTopOfStack = 0x1111;
- pxTopOfStack--;
- *pxTopOfStack = 0x2222;
- pxTopOfStack--;
- *pxTopOfStack = 0x3333;
- pxTopOfStack--;
+ *pxTopOfStack = 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x3333;
+ pxTopOfStack--;
- /* We are going to start the scheduler using a return from interrupt
- * instruction to load the program counter, so first there would be the
- * function call with parameters preamble. */
+ /* We are going to start the scheduler using a return from interrupt
+ instruction to load the program counter, so first there would be the
+ function call with parameters preamble. */
+
+ *pxTopOfStack = FP_SEG( pvParameters );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pvParameters );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_SEG( pxCode );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pxCode );
+ pxTopOfStack--;
- *pxTopOfStack = FP_SEG( pvParameters );
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pvParameters );
- pxTopOfStack--;
- *pxTopOfStack = FP_SEG( pxCode );
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pxCode );
- pxTopOfStack--;
+ /* Next the status register and interrupt return address. */
+ *pxTopOfStack = portINITIAL_SW;
+ pxTopOfStack--;
+ *pxTopOfStack = FP_SEG( pxCode );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pxCode );
+ pxTopOfStack--;
- /* Next the status register and interrupt return address. */
- *pxTopOfStack = portINITIAL_SW;
- pxTopOfStack--;
- *pxTopOfStack = FP_SEG( pxCode );
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pxCode );
- pxTopOfStack--;
+ /* The remaining registers would be pushed on the stack by our context
+ switch function. These are loaded with values simply to make debugging
+ easier. */
+ *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */
+ pxTopOfStack--;
- /* The remaining registers would be pushed on the stack by our context
- * switch function. These are loaded with values simply to make debugging
- * easier. */
- *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */
- pxTopOfStack--;
+ /* We need the true data segment. */
+ __asm{ MOV DS_Reg, DS };
- /* We need the true data segment. */
- __asm {
- MOV DS_Reg, DS
- };
+ *pxTopOfStack = DS_Reg; /* DS */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */
- *pxTopOfStack = DS_Reg; /* DS */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* This is called with interrupts already disabled. */
+ /* This is called with interrupts already disabled. */
- /* Put our manual switch (yield) function on a known
- * vector. */
- setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+ /* Put our manual switch (yield) function on a known
+ vector. */
+ setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
- /* Setup the tick interrupt. */
- prvSetupTimerInterrupt();
+ /* Setup the tick interrupt. */
+ prvSetupTimerInterrupt();
- /* Kick off the scheduler by setting up the context of the first task. */
- portFIRST_CONTEXT();
+ /* Kick off the scheduler by setting up the context of the first task. */
+ portFIRST_CONTEXT();
- /* Should not get here! */
- return pdFALSE;
+ /* Should not get here! */
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
static void __interrupt __far prvDummyISR( void )
{
- /* The timer initialisation functions leave interrupts enabled,
- * which is not what we want. This ISR is installed temporarily in case
- * the timer fires before we get a change to disable interrupts again. */
- outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+ /* The timer initialisation functions leave interrupts enabled,
+ which is not what we want. This ISR is installed temporarily in case
+ the timer fires before we get a change to disable interrupts again. */
+ outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
}
/*-----------------------------------------------------------*/
/* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
- static void __interrupt __far prvPreemptiveTick( void )
- {
- /* Get the scheduler to update the task states following the tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Switch in the context of the next task to be run. */
- portSWITCH_CONTEXT();
- }
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+ static void __interrupt __far prvPreemptiveTick( void )
+ {
+ /* Get the scheduler to update the task states following the tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Switch in the context of the next task to be run. */
+ portSWITCH_CONTEXT();
+ }
- /* Reset interrupt. */
- outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
- }
-#else /* if ( configUSE_PREEMPTION == 1 ) */
- static void __interrupt __far prvNonPreemptiveTick( void )
- {
- /* Same as preemptive tick, but the cooperative scheduler is being used
- * so we don't have to switch in the context of the next task. */
- xTaskIncrementTick();
-
- /* Reset interrupt. */
- outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
- }
-#endif /* if ( configUSE_PREEMPTION == 1 ) */
+ /* Reset interrupt. */
+ outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+ }
+#else
+ static void __interrupt __far prvNonPreemptiveTick( void )
+ {
+ /* Same as preemptive tick, but the cooperative scheduler is being used
+ so we don't have to switch in the context of the next task. */
+ xTaskIncrementTick();
+
+ /* Reset interrupt. */
+ outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+ }
+#endif
/*-----------------------------------------------------------*/
static void __interrupt __far prvYieldProcessor( void )
{
- /* Switch in the context of the next task to be run. */
- portSWITCH_CONTEXT();
+ /* Switch in the context of the next task to be run. */
+ portSWITCH_CONTEXT();
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented. */
+ /* Not implemented. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT;
- const uint16_t usT2_IRQ = 0x13;
+const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT;
+const uint16_t usT2_IRQ = 0x13;
- /* Configure the timer, the dummy handler is used here as the init
- * function leaves interrupts enabled. */
- t2_init( usTimerAMode, usTimerACompare, prvDummyISR );
+ /* Configure the timer, the dummy handler is used here as the init
+ function leaves interrupts enabled. */
+ t2_init( usTimerAMode, usTimerACompare, prvDummyISR );
- /* Disable interrupts again before installing the real handlers. */
- portDISABLE_INTERRUPTS();
+ /* Disable interrupts again before installing the real handlers. */
+ portDISABLE_INTERRUPTS();
- #if ( configUSE_PREEMPTION == 1 )
-
- /* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
- setvect( usT2_IRQ, prvPreemptiveTick );
- #else
-
- /* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
- setvect( usT2_IRQ, prvNonPreemptiveTick );
- #endif
+ #if( configUSE_PREEMPTION == 1 )
+ /* Tick service routine used by the scheduler when preemptive scheduling is
+ being used. */
+ setvect( usT2_IRQ, prvPreemptiveTick );
+ #else
+ /* Tick service routine used by the scheduler when cooperative scheduling is
+ being used. */
+ setvect( usT2_IRQ, prvNonPreemptiveTick );
+ #endif
}
+
+
+
+
+
+
+
diff --git a/portable/Paradigm/Tern_EE/large_untested/portasm.h b/portable/Paradigm/Tern_EE/large_untested/portasm.h
index c4266fd..9392f7b 100644
--- a/portable/Paradigm/Tern_EE/large_untested/portasm.h
+++ b/portable/Paradigm/Tern_EE/large_untested/portasm.h
@@ -43,32 +43,34 @@
*/
void portFIRST_CONTEXT( void );
-#define portSWITCH_CONTEXT() \
- asm { mov ax, seg pxCurrentTCB } \
- asm { mov ds, ax } \
- asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \
- asm { mov es : 0x2[ bx ], ss } \
- asm { mov es:[ bx ], sp } \
- asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \
- asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \
- asm { mov ds, ax } \
- asm { les bx, dword ptr pxCurrentTCB } \
- asm { mov ss, es:[ bx + 2 ] } \
- asm { mov sp, es:[ bx ] }
+#define portSWITCH_CONTEXT() \
+ asm { mov ax, seg pxCurrentTCB } \
+ asm { mov ds, ax } \
+ asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \
+ asm { mov es:0x2[ bx ], ss } \
+ asm { mov es:[ bx ], sp } \
+ asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \
+ asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \
+ asm { mov ds, ax } \
+ asm { les bx, dword ptr pxCurrentTCB } \
+ asm { mov ss, es:[ bx + 2 ] } \
+ asm { mov sp, es:[ bx ] }
-#define portFIRST_CONTEXT() \
- asm { mov ax, seg pxCurrentTCB } \
- asm { mov ds, ax } \
- asm { les bx, dword ptr pxCurrentTCB } \
- asm { mov ss, es:[ bx + 2 ] } \
- asm { mov sp, es:[ bx ] } \
- asm { pop bp } \
- asm { pop di } \
- asm { pop si } \
- asm { pop ds } \
- asm { pop es } \
- asm { pop dx } \
- asm { pop cx } \
- asm { pop bx } \
- asm { pop ax } \
- asm { iret }
+#define portFIRST_CONTEXT() \
+ asm { mov ax, seg pxCurrentTCB } \
+ asm { mov ds, ax } \
+ asm { les bx, dword ptr pxCurrentTCB } \
+ asm { mov ss, es:[ bx + 2 ] } \
+ asm { mov sp, es:[ bx ] } \
+ asm { pop bp } \
+ asm { pop di } \
+ asm { pop si } \
+ asm { pop ds } \
+ asm { pop es } \
+ asm { pop dx } \
+ asm { pop cx } \
+ asm { pop bx } \
+ asm { pop ax } \
+ asm { iret }
+
+
diff --git a/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/portable/Paradigm/Tern_EE/large_untested/portmacro.h
index 6f0824f..354b000 100644
--- a/portable/Paradigm/Tern_EE/large_untested/portmacro.h
+++ b/portable/Paradigm/Tern_EE/large_untested/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,64 +43,64 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE long
- #define portLONG long
- #define portSHORT int
- #define portSTACK_TYPE uint16_t
- #define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE long
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
- typedef portSTACK_TYPE StackType_t;
- typedef short BaseType_t;
- typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Critical section handling. */
- #define portENTER_CRITICAL() \
- __asm{ pushf } \
- __asm{ cli } \
+#define portENTER_CRITICAL() __asm{ pushf } \
+ __asm{ cli } \
- #define portEXIT_CRITICAL() __asm{ popf }
+#define portEXIT_CRITICAL() __asm{ popf }
- #define portDISABLE_INTERRUPTS() __asm{ cli }
+#define portDISABLE_INTERRUPTS() __asm{ cli }
- #define portENABLE_INTERRUPTS() __asm{ sti }
+#define portENABLE_INTERRUPTS() __asm{ sti }
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portNOP() __asm{ nop }
- #define portSTACK_GROWTH ( -1 )
- #define portSWITCH_INT_NUMBER 0x80
- #define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 2
- #define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
+#define portNOP() __asm{ nop }
+#define portSTACK_GROWTH ( -1 )
+#define portSWITCH_INT_NUMBER 0x80
+#define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
/*-----------------------------------------------------------*/
/* Compiler specifics. */
- #define portINPUT_BYTE( xAddr ) inp( xAddr )
- #define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
- #define portINPUT_WORD( xAddr ) inpw( xAddr )
- #define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr ) inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr ) inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void * pvParameters )
- #define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/Paradigm/Tern_EE/small/port.c b/portable/Paradigm/Tern_EE/small/port.c
index c1eae43..6fdb9b8 100644
--- a/portable/Paradigm/Tern_EE/small/port.c
+++ b/portable/Paradigm/Tern_EE/small/port.c
@@ -27,9 +27,9 @@
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Tern EE 186
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Tern EE 186
+ * port.
+ *----------------------------------------------------------*/
/* Library includes. */
#include <embedded.h>
@@ -41,32 +41,30 @@
#include "portasm.h"
/* The timer increments every four clocks, hence the divide by 4. */
-#define portPRESCALE_VALUE ( 16 )
-#define portTIMER_COMPARE ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 4UL ) )
+#define portPRESCALE_VALUE ( 16 )
+#define portTIMER_COMPARE ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 4UL ) )
/* From the RDC data sheet. */
-#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe00b
-#define portENABLE_TIMER ( uint16_t ) 0xC001
+#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe00b
+#define portENABLE_TIMER ( uint16_t ) 0xC001
/* Interrupt control. */
-#define portEIO_REGISTER 0xff22
-#define portCLEAR_INTERRUPT 0x0008
+#define portEIO_REGISTER 0xff22
+#define portCLEAR_INTERRUPT 0x0008
/* Setup the hardware to generate the required tick frequency. */
static void prvSetupTimerInterrupt( void );
/* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
- static void __interrupt __far prvPreemptiveTick( void );
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+ /* Tick service routine used by the scheduler when preemptive scheduling is
+ being used. */
+ static void __interrupt __far prvPreemptiveTick( void );
#else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
- static void __interrupt __far prvNonPreemptiveTick( void );
+ /* Tick service routine used by the scheduler when cooperative scheduling is
+ being used. */
+ static void __interrupt __far prvNonPreemptiveTick( void );
#endif
/* Trap routine used by taskYIELD() to manually cause a context switch. */
@@ -74,147 +72,148 @@
/*-----------------------------------------------------------*/
/* See header file for description. */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t DS_Reg = 0;
+StackType_t DS_Reg = 0;
- /* We need the true data segment. */
- __asm {
- MOV DS_Reg, DS
- };
+ /* We need the true data segment. */
+ __asm{ MOV DS_Reg, DS };
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging. */
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
- *pxTopOfStack = 0x1111;
- pxTopOfStack--;
- *pxTopOfStack = 0x2222;
- pxTopOfStack--;
- *pxTopOfStack = 0x3333;
- pxTopOfStack--;
+ *pxTopOfStack = 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x3333;
+ pxTopOfStack--;
- /* We are going to start the scheduler using a return from interrupt
- * instruction to load the program counter, so first there would be the
- * function call with parameters preamble. */
+ /* We are going to start the scheduler using a return from interrupt
+ instruction to load the program counter, so first there would be the
+ function call with parameters preamble. */
+
+ *pxTopOfStack = FP_OFF( pvParameters );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pxCode );
+ pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pvParameters );
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pxCode );
- pxTopOfStack--;
+ /* Next the status register and interrupt return address. */
+ *pxTopOfStack = portINITIAL_SW;
+ pxTopOfStack--;
+ *pxTopOfStack = FP_SEG( pxCode );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pxCode );
+ pxTopOfStack--;
- /* Next the status register and interrupt return address. */
- *pxTopOfStack = portINITIAL_SW;
- pxTopOfStack--;
- *pxTopOfStack = FP_SEG( pxCode );
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pxCode );
- pxTopOfStack--;
+ /* The remaining registers would be pushed on the stack by our context
+ switch function. These are loaded with values simply to make debugging
+ easier. */
+ *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */
+ pxTopOfStack--;
- /* The remaining registers would be pushed on the stack by our context
- * switch function. These are loaded with values simply to make debugging
- * easier. */
- *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */
- pxTopOfStack--;
+ *pxTopOfStack = DS_Reg; /* DS */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */
- *pxTopOfStack = DS_Reg; /* DS */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* This is called with interrupts already disabled. */
+ /* This is called with interrupts already disabled. */
- /* Put our manual switch (yield) function on a known
- * vector. */
- setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+ /* Put our manual switch (yield) function on a known
+ vector. */
+ setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
- /* Setup the tick interrupt. */
- prvSetupTimerInterrupt();
+ /* Setup the tick interrupt. */
+ prvSetupTimerInterrupt();
- /* Kick off the scheduler by setting up the context of the first task. */
- portFIRST_CONTEXT();
+ /* Kick off the scheduler by setting up the context of the first task. */
+ portFIRST_CONTEXT();
- /* Should not get here! */
- return pdFALSE;
+ /* Should not get here! */
+ return pdFALSE;
}
/*-----------------------------------------------------------*/
/* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
- static void __interrupt __far prvPreemptiveTick( void )
- {
- /* Get the scheduler to update the task states following the tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Switch in the context of the next task to be run. */
- portEND_SWITCHING_ISR();
- }
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+ static void __interrupt __far prvPreemptiveTick( void )
+ {
+ /* Get the scheduler to update the task states following the tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Switch in the context of the next task to be run. */
+ portEND_SWITCHING_ISR();
+ }
- /* Reset interrupt. */
- outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
- }
-#else /* if ( configUSE_PREEMPTION == 1 ) */
- static void __interrupt __far prvNonPreemptiveTick( void )
- {
- /* Same as preemptive tick, but the cooperative scheduler is being used
- * so we don't have to switch in the context of the next task. */
- xTaskIncrementTick();
-
- /* Reset interrupt. */
- outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
- }
-#endif /* if ( configUSE_PREEMPTION == 1 ) */
+ /* Reset interrupt. */
+ outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+ }
+#else
+ static void __interrupt __far prvNonPreemptiveTick( void )
+ {
+ /* Same as preemptive tick, but the cooperative scheduler is being used
+ so we don't have to switch in the context of the next task. */
+ xTaskIncrementTick();
+
+ /* Reset interrupt. */
+ outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+ }
+#endif
/*-----------------------------------------------------------*/
static void __interrupt __far prvYieldProcessor( void )
{
- /* Switch in the context of the next task to be run. */
- portEND_SWITCHING_ISR();
+ /* Switch in the context of the next task to be run. */
+ portEND_SWITCHING_ISR();
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented. */
+ /* Not implemented. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- const uint32_t ulCompareValue = portTIMER_COMPARE;
- uint16_t usTimerCompare;
+const uint32_t ulCompareValue = portTIMER_COMPARE;
+uint16_t usTimerCompare;
- usTimerCompare = ( uint16_t ) ( ulCompareValue >> 4 );
+ usTimerCompare = ( uint16_t ) ( ulCompareValue >> 4 );
t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL );
- #if ( configUSE_PREEMPTION == 1 )
-
- /* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
- t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick );
- #else
-
- /* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
- t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick );
- #endif
+ #if( configUSE_PREEMPTION == 1 )
+ /* Tick service routine used by the scheduler when preemptive scheduling is
+ being used. */
+ t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick );
+ #else
+ /* Tick service routine used by the scheduler when cooperative scheduling is
+ being used. */
+ t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick );
+ #endif
}
+
+
+
+
+
+
+
diff --git a/portable/Paradigm/Tern_EE/small/portasm.h b/portable/Paradigm/Tern_EE/small/portasm.h
index 055089a..e224062 100644
--- a/portable/Paradigm/Tern_EE/small/portasm.h
+++ b/portable/Paradigm/Tern_EE/small/portasm.h
@@ -46,26 +46,27 @@
*/
void portFIRST_CONTEXT( void );
-#define portEND_SWITCHING_ISR() \
- asm { mov bx, [ pxCurrentTCB ] } \
- asm { mov word ptr[ bx ], sp } \
- asm { call far ptr vTaskSwitchContext } \
- asm { mov bx, [ pxCurrentTCB ] } \
- asm { mov sp, [ bx ] }
+#define portEND_SWITCHING_ISR() \
+ asm { mov bx, [pxCurrentTCB] } \
+ asm { mov word ptr [bx], sp } \
+ asm { call far ptr vTaskSwitchContext } \
+ asm { mov bx, [pxCurrentTCB] } \
+ asm { mov sp, [bx] }
-#define portFIRST_CONTEXT() \
- asm { mov bx, [ pxCurrentTCB ] } \
- asm { mov sp, [ bx ] } \
- asm { pop bp } \
- asm { pop di } \
- asm { pop si } \
- asm { pop ds } \
- asm { pop es } \
- asm { pop dx } \
- asm { pop cx } \
- asm { pop bx } \
- asm { pop ax } \
- asm { iret }
+#define portFIRST_CONTEXT() \
+ asm { mov bx, [pxCurrentTCB] } \
+ asm { mov sp, [bx] } \
+ asm { pop bp } \
+ asm { pop di } \
+ asm { pop si } \
+ asm { pop ds } \
+ asm { pop es } \
+ asm { pop dx } \
+ asm { pop cx } \
+ asm { pop bx } \
+ asm { pop ax } \
+ asm { iret }
-#endif /* ifndef PORT_ASM_H */
+#endif
+
diff --git a/portable/Paradigm/Tern_EE/small/portmacro.h b/portable/Paradigm/Tern_EE/small/portmacro.h
index bebd154..fd3ca1d 100644
--- a/portable/Paradigm/Tern_EE/small/portmacro.h
+++ b/portable/Paradigm/Tern_EE/small/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,65 +43,65 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE long
- #define portLONG long
- #define portSHORT int
- #define portSTACK_TYPE uint16_t
- #define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE long
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
- typedef portSTACK_TYPE StackType_t;
- typedef short BaseType_t;
- typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
- typedef void ( __interrupt __far * pxISR )();
+typedef void ( __interrupt __far *pxISR )();
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Critical section handling. */
- #define portENTER_CRITICAL() \
- __asm{ pushf } \
- __asm{ cli } \
+#define portENTER_CRITICAL() __asm{ pushf } \
+ __asm{ cli } \
- #define portEXIT_CRITICAL() __asm{ popf }
+#define portEXIT_CRITICAL() __asm{ popf }
- #define portDISABLE_INTERRUPTS() __asm{ cli }
+#define portDISABLE_INTERRUPTS() __asm{ cli }
- #define portENABLE_INTERRUPTS() __asm{ sti }
+#define portENABLE_INTERRUPTS() __asm{ sti }
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portNOP() __asm{ nop }
- #define portSTACK_GROWTH ( -1 )
- #define portSWITCH_INT_NUMBER 0x80
- #define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 2
- #define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
+#define portNOP() __asm{ nop }
+#define portSTACK_GROWTH ( -1 )
+#define portSWITCH_INT_NUMBER 0x80
+#define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
/*-----------------------------------------------------------*/
/* Compiler specifics. */
- #define portINPUT_BYTE( xAddr ) inp( xAddr )
- #define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
- #define portINPUT_WORD( xAddr ) inpw( xAddr )
- #define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr ) inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr ) inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void * pvParameters )
- #define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/RVDS/ARM7_LPC21xx/port.c b/portable/RVDS/ARM7_LPC21xx/port.c
index 5b9c4c9..b111f13 100644
--- a/portable/RVDS/ARM7_LPC21xx/port.c
+++ b/portable/RVDS/ARM7_LPC21xx/port.c
@@ -34,35 +34,35 @@
#include "task.h"
/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE 0x00
-#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
+#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE 0x00
+#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
/* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
+#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
/*-----------------------------------------------------------*/
/* The code generated by the Keil compiler does not maintain separate
- * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
- * use the stack as per other ports. Instead a variable is used to keep
- * track of the critical section nesting. This variable has to be stored
- * as part of the task context and must be initialised to a non zero value. */
+stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+use the stack as per other ports. Instead a variable is used to keep
+track of the critical section nesting. This variable has to be stored
+as part of the task context and must be initialised to a non zero value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
volatile uint32_t ulCriticalNesting = 9999UL;
/*-----------------------------------------------------------*/
@@ -70,222 +70,222 @@
/* Setup the timer to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
-/*
- * The scheduler can only be started from ARM mode, so
- * vPortStartFirstSTask() is defined in portISR.c.
+/*
+ * The scheduler can only be started from ARM mode, so
+ * vPortStartFirstSTask() is defined in portISR.c.
*/
extern __asm void vPortStartFirstTask( void );
/*-----------------------------------------------------------*/
-/*
- * See header file for description.
+/*
+ * See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro.
- *
- * Remember where the top of the (simulated) stack is before we place
- * anything on it. */
- pxOriginalTOS = pxTopOfStack;
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro.
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- * is not really required. */
- pxTopOfStack--;
+ Remember where the top of the (simulated) stack is before we place
+ anything on it. */
+ pxOriginalTOS = pxTopOfStack;
+
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The last thing onto the stack is the status register, which is set for
- * system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* The last thing onto the stack is the status register, which is set for
+ system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
- pxTopOfStack--;
+ pxTopOfStack--;
- /* The code generated by the Keil compiler does not maintain separate
- * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
- * use the stack as per other ports. Instead a variable is used to keep
- * track of the critical section nesting. This variable has to be stored
- * as part of the task context and is initially set to zero. */
- *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+ /* The code generated by the Keil compiler does not maintain separate
+ stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+ use the stack as per other ports. Instead a variable is used to keep
+ track of the critical section nesting. This variable has to be stored
+ as part of the task context and is initially set to zero. */
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Start the timer that generates the tick ISR. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. */
+ prvSetupTimerInterrupt();
- /* Start the first task. This is done from portISR.c as ARM mode must be
- * used. */
- vPortStartFirstTask();
+ /* Start the first task. This is done from portISR.c as ARM mode must be
+ used. */
+ vPortStartFirstTask();
- /* Should not get here! */
- return 0;
+ /* Should not get here! */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the ARM port will require this function as there
- * is nothing to return to. If this is required - stop the tick ISR then
- * return back to main. */
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. If this is required - stop the tick ISR then
+ return back to main. */
}
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 0
-/*
- * The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick.
- */
- void vNonPreemptiveTick( void ) __irq;
- void vNonPreemptiveTick( void ) __irq
- {
- /* Increment the tick count - this may make a delaying task ready
- * to run - but a context switch is not performed. */
- xTaskIncrementTick();
+ /*
+ * The cooperative scheduler requires a normal IRQ service routine to
+ * simply increment the system tick.
+ */
+ void vNonPreemptiveTick( void ) __irq;
+ void vNonPreemptiveTick( void ) __irq
+ {
+ /* Increment the tick count - this may make a delaying task ready
+ to run - but a context switch is not performed. */
+ xTaskIncrementTick();
- T0IR = portTIMER_MATCH_ISR_BIT; /* Clear the timer event */
- VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */
- }
+ T0IR = portTIMER_MATCH_ISR_BIT; /* Clear the timer event */
+ VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */
+ }
-#else /* if configUSE_PREEMPTION == 0 */
+ #else
-/*
- **************************************************************************
- * The preemptive scheduler ISR is written in assembler and can be found
- * in the portASM.s file. This will only get used if portUSE_PREEMPTION
- * is set to 1 in portmacro.h
- **************************************************************************
- */
+ /*
+ **************************************************************************
+ * The preemptive scheduler ISR is written in assembler and can be found
+ * in the portASM.s file. This will only get used if portUSE_PREEMPTION
+ * is set to 1 in portmacro.h
+ **************************************************************************
+ */
- void vPreemptiveTick( void );
+ void vPreemptiveTick( void );
-#endif /* if configUSE_PREEMPTION == 0 */
+#endif
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- uint32_t ulCompareMatch;
+uint32_t ulCompareMatch;
- /* A 1ms tick does not require the use of the timer prescale. This is
- * defaulted to zero but can be used if necessary. */
- T0PR = portPRESCALE_VALUE;
+ /* A 1ms tick does not require the use of the timer prescale. This is
+ defaulted to zero but can be used if necessary. */
+ T0PR = portPRESCALE_VALUE;
- /* Calculate the match value required for our wanted tick rate. */
- ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+ /* Calculate the match value required for our wanted tick rate. */
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
- /* Protect against divide by zero. Using an if() statement still results
- * in a warning - hence the #if. */
- #if portPRESCALE_VALUE != 0
- {
- ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
- }
- #endif
+ /* Protect against divide by zero. Using an if() statement still results
+ in a warning - hence the #if. */
+ #if portPRESCALE_VALUE != 0
+ {
+ ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+ }
+ #endif
- T0MR0 = ulCompareMatch;
+ T0MR0 = ulCompareMatch;
- /* Generate tick with timer 0 compare match. */
- T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+ /* Generate tick with timer 0 compare match. */
+ T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
- /* Setup the VIC for the timer. */
- VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
- VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+ /* Setup the VIC for the timer. */
+ VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+ VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+
+ /* The ISR installed depends on whether the preemptive or cooperative
+ scheduler is being used. */
+ #if configUSE_PREEMPTION == 1
+ {
+ VICVectAddr0 = ( uint32_t ) vPreemptiveTick;
+ }
+ #else
+ {
+ VICVectAddr0 = ( uint32_t ) vNonPreemptiveTick;
+ }
+ #endif
- /* The ISR installed depends on whether the preemptive or cooperative
- * scheduler is being used. */
- #if configUSE_PREEMPTION == 1
- {
- VICVectAddr0 = ( uint32_t ) vPreemptiveTick;
- }
- #else
- {
- VICVectAddr0 = ( uint32_t ) vNonPreemptiveTick;
- }
- #endif
+ VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
- VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
-
- /* Start the timer - interrupts are disabled when this function is called
- * so it is okay to do this here. */
- T0TCR = portENABLE_TIMER;
+ /* Start the timer - interrupts are disabled when this function is called
+ so it is okay to do this here. */
+ T0TCR = portENABLE_TIMER;
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- __disable_irq();
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ __disable_irq();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then interrupts should be
- * re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- __enable_irq();
- }
- }
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ __enable_irq();
+ }
+ }
}
/*-----------------------------------------------------------*/
+
+
diff --git a/portable/RVDS/ARM7_LPC21xx/portmacro.h b/portable/RVDS/ARM7_LPC21xx/portmacro.h
index 3aed982..6f24ac7 100644
--- a/portable/RVDS/ARM7_LPC21xx/portmacro.h
+++ b/portable/RVDS/ARM7_LPC21xx/portmacro.h
@@ -27,11 +27,11 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,57 +44,57 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Task utilities. */
/*-----------------------------------------------------------
-* ISR entry and exit macros. These are only required if a task switch
-* is required from an ISR.
-*----------------------------------------------------------*/
+ * ISR entry and exit macros. These are only required if a task switch
+ * is required from an ISR.
+ *----------------------------------------------------------*/
/* If a switch is required then we just need to call */
/* vTaskSwitchContext() as the context has already been */
/* saved. */
- #define portEXIT_SWITCHING_ISR( SwitchRequired ) \
- { \
- extern void vTaskSwitchContext( void ); \
- \
- if( SwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
- } \
+#define portEXIT_SWITCHING_ISR(SwitchRequired) \
+{ \
+extern void vTaskSwitchContext(void); \
+ \
+ if(SwitchRequired) \
+ { \
+ vTaskSwitchContext(); \
+ } \
+} \
- extern void vPortYield( void );
- #define portYIELD() vPortYield()
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
/* Critical section management. */
@@ -107,39 +107,40 @@
* take care of that for us.
*******************************************************************
*/
- #define portDISABLE_INTERRUPTS() __disable_irq()
- #define portENABLE_INTERRUPTS() __enable_irq()
+#define portDISABLE_INTERRUPTS() __disable_irq()
+#define portENABLE_INTERRUPTS() __enable_irq()
/*-----------------------------------------------------------
-* Critical section control
-*
-* The code generated by the Keil compiler does not maintain separate
-* stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
-* use the stack as per other ports. Instead a variable is used to keep
-* track of the critical section nesting. This necessitates the use of a
-* function in place of the macro.
-*----------------------------------------------------------*/
+ * Critical section control
+ *
+ * The code generated by the Keil compiler does not maintain separate
+ * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+ * use the stack as per other ports. Instead a variable is used to keep
+ * track of the critical section nesting. This necessitates the use of a
+ * function in place of the macro.
+ *----------------------------------------------------------*/
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
/*-----------------------------------------------------------*/
/* Compiler specifics. */
- #define inline
- #define register
- #define portNOP() __asm{ NOP }
+#define inline
+#define register
+#define portNOP() __asm{ NOP }
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/RVDS/ARM_CA9/port.c b/portable/RVDS/ARM_CA9/port.c
index e7c418d..250f313 100644
--- a/portable/RVDS/ARM_CA9/port.c
+++ b/portable/RVDS/ARM_CA9/port.c
@@ -33,124 +33,124 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
- #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
- #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http: /*www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#endif
#ifndef configCLEAR_TICK_INTERRUPT
- #define configCLEAR_TICK_INTERRUPT()
+ #define configCLEAR_TICK_INTERRUPT()
#endif
/* The number of bits to shift for an interrupt priority is dependent on the
- * number of bits implemented by the interrupt controller. */
+number of bits implemented by the interrupt controller. */
#if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
-#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
- #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+#else
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
/* A critical section is exited when the critical section nesting count reaches
- * this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
- * (but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
- * floating point context after they have been created. A variable is stored as
- * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
- * does not have an FPU context, or any other value if the task does have an FPU
- * context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
- * point is zero. */
-#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
- * mode. */
-#define portAPSR_USER_MODE ( 0x10 )
+mode. */
+#define portAPSR_USER_MODE ( 0x10 )
/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK() \
- { \
- __disable_irq(); \
- portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
- __asm( "DSB \n" \
- "ISB \n"); \
- __enable_irq(); \
- }
+#define portCLEAR_INTERRUPT_MASK() \
+{ \
+ __disable_irq(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm( "DSB \n" \
+ "ISB \n" ); \
+ __enable_irq(); \
+}
/*-----------------------------------------------------------*/
@@ -168,29 +168,29 @@
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
- * variable has to be stored as part of the task context and must be initialised to
- * a non zero value to ensure interrupts don't inadvertently become unmasked before
- * the scheduler starts. As it is stored as part of the task context it will
- * automatically be set to 0 when the first task is started. */
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Used to pass constants into the ASM code. The address at which variables are
- * placed is the constant value so indirect loads in the asm code are not
- * required. */
+placed is the constant value so indirect loads in the asm code are not
+required. */
uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
- * a floating point context must be saved and restored for the task. */
+a floating point context must be saved and restored for the task. */
uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
- * if the nesting depth is 0. */
+if the nesting depth is 0. */
uint32_t ulPortInterruptNesting = 0UL;
/*-----------------------------------------------------------*/
@@ -198,286 +198,283 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro.
- *
- * The fist real value on the stack is the status register, which is set for
- * system mode, with interrupts enabled. A few NULLs are added first to ensure
- * GDB does not try decoding a non-existent return address. */
- *pxTopOfStack = NULL;
- pxTopOfStack--;
- *pxTopOfStack = NULL;
- pxTopOfStack--;
- *pxTopOfStack = NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro.
- if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
- {
- /* The task will start in THUMB mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
+ The fist real value on the stack is the status register, which is set for
+ system mode, with interrupts enabled. A few NULLs are added first to ensure
+ GDB does not try decoding a non-existent return address. */
+ *pxTopOfStack = NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
- pxTopOfStack--;
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+ {
+ /* The task will start in THUMB mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
- /* Next the return address, which in this case is the start of the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
+ pxTopOfStack--;
- /* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
+ /* Next the return address, which in this case is the start of the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
- /* The task will start with a critical nesting count of 0 as interrupts are
- * enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
+ /* Next all the registers other than the stack pointer. */
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
- /* The task will start without a floating point context. A task that uses
- * the floating point hardware must call vPortTaskUsesFPU() before executing
- * any floating point instructions. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
- return pxTopOfStack;
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( ulPortInterruptNesting == ~0UL );
- portDISABLE_INTERRUPTS();
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
- for( ; ; )
- {
- }
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulPortInterruptNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- uint32_t ulAPSR;
+uint32_t ulAPSR;
- /* Only continue if the CPU is not in User mode. The CPU must be in a
- * Privileged mode for the scheduler to start. */
- __asm( "MRS ulAPSR, APSR" );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
- configASSERT( ulAPSR != portAPSR_USER_MODE );
+ /* Only continue if the CPU is not in User mode. The CPU must be in a
+ Privileged mode for the scheduler to start. */
+ __asm( "MRS ulAPSR, APSR" );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+ configASSERT( ulAPSR != portAPSR_USER_MODE );
- if( ulAPSR != portAPSR_USER_MODE )
- {
- /* Only continue if the binary point value is set to its lowest possible
- * setting. See the comments in vPortValidateInterruptPriority() below for
- * more information. */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ if( ulAPSR != portAPSR_USER_MODE )
+ {
+ /* Only continue if the binary point value is set to its lowest possible
+ setting. See the comments in vPortValidateInterruptPriority() below for
+ more information. */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
- if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
- {
- /* Start the timer that generates the tick ISR. */
- configSETUP_TICK_INTERRUPT();
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+ {
+ /* Start the timer that generates the tick ISR. */
+ configSETUP_TICK_INTERRUPT();
- __enable_irq();
- vPortRestoreTaskContext();
- }
- }
+ __enable_irq();
+ vPortRestoreTaskContext();
+ }
+ }
- /* Will only get here if vTaskStartScheduler() was called with the CPU in
- * a non-privileged mode or the binary point register was not set to its lowest
- * possible value. */
- return 0;
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in
+ a non-privileged mode or the binary point register was not set to its lowest
+ possible value. */
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- ulPortSetInterruptMask();
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ ulPortSetInterruptMask();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( ulCriticalNesting == 1 )
- {
- configASSERT( ulPortInterruptNesting == 0 );
- }
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ulCriticalNesting == 1 )
+ {
+ configASSERT( ulPortInterruptNesting == 0 );
+ }
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- * exited. */
- ulCriticalNesting--;
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
- /* If the nesting level has reached zero then all interrupt
- * priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- * should be unmasked. */
- portCLEAR_INTERRUPT_MASK();
- }
- }
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portCLEAR_INTERRUPT_MASK();
+ }
+ }
}
/*-----------------------------------------------------------*/
void FreeRTOS_Tick_Handler( void )
{
- /* Set interrupt mask before altering scheduler structures. The tick
- * handler runs at the lowest priority, so interrupts cannot already be masked,
- * so there is no need to save and restore the current mask value. */
- __disable_irq();
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm( "DSB \n"
- "ISB \n");
- __enable_irq();
+ /* Set interrupt mask before altering scheduler structures. The tick
+ handler runs at the lowest priority, so interrupts cannot already be masked,
+ so there is no need to save and restore the current mask value. */
+ __disable_irq();
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm( "DSB \n"
+ "ISB \n" );
+ __enable_irq();
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ulPortYieldRequired = pdTRUE;
- }
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ulPortYieldRequired = pdTRUE;
+ }
- /* Ensure all interrupt priorities are active again. */
- portCLEAR_INTERRUPT_MASK();
- configCLEAR_TICK_INTERRUPT();
+ /* Ensure all interrupt priorities are active again. */
+ portCLEAR_INTERRUPT_MASK();
+ configCLEAR_TICK_INTERRUPT();
}
/*-----------------------------------------------------------*/
void vPortTaskUsesFPU( void )
{
- uint32_t ulInitialFPSCR = 0;
+uint32_t ulInitialFPSCR = 0;
- /* A task is registering the fact that it needs an FPU context. Set the
- * FPU flag (which is saved as part of the task context). */
- ulPortTaskHasFPUContext = pdTRUE;
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ulPortTaskHasFPUContext = pdTRUE;
- /* Initialise the floating point status register. */
- __asm( "FMXR FPSCR, ulInitialFPSCR");
+ /* Initialise the floating point status register. */
+ __asm( "FMXR FPSCR, ulInitialFPSCR" );
}
/*-----------------------------------------------------------*/
void vPortClearInterruptMask( uint32_t ulNewMaskValue )
{
- if( ulNewMaskValue == pdFALSE )
- {
- portCLEAR_INTERRUPT_MASK();
- }
+ if( ulNewMaskValue == pdFALSE )
+ {
+ portCLEAR_INTERRUPT_MASK();
+ }
}
/*-----------------------------------------------------------*/
uint32_t ulPortSetInterruptMask( void )
{
- uint32_t ulReturn;
+uint32_t ulReturn;
- __disable_irq();
+ __disable_irq();
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+ {
+ /* Interrupts were already masked. */
+ ulReturn = pdTRUE;
+ }
+ else
+ {
+ ulReturn = pdFALSE;
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm( "DSB \n"
+ "ISB \n" );
+ }
+ __enable_irq();
- if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
- {
- /* Interrupts were already masked. */
- ulReturn = pdTRUE;
- }
- else
- {
- ulReturn = pdFALSE;
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm( "DSB \n"
- "ISB \n");
- }
-
- __enable_irq();
-
- return ulReturn;
+ return ulReturn;
}
/*-----------------------------------------------------------*/
-#if ( configASSERT_DEFINED == 1 )
+#if( configASSERT_DEFINED == 1 )
- void vPortValidateInterruptPriority( void )
- {
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible.
- *
- * The following links provide detailed information:
- * http://www.freertos.org/RTOS-Cortex-M3-M4.html
- * http://www.freertos.org/FAQHelp.html */
- configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+ void vPortValidateInterruptPriority( void )
+ {
+ /* The following assertion will fail if a service routine (ISR) for
+ an interrupt that has been assigned a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ function. ISR safe FreeRTOS API functions must *only* be called
+ from interrupts that have been assigned a priority at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
- /* Priority grouping: The interrupt controller (GIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * The priority grouping is configured by the GIC's binary point register
- * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
- * possible value (which may be above 0). */
- configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
- }
+ Numerically low interrupt priority numbers represent logically high
+ interrupt priorities, therefore the priority of the interrupt must
+ be set to a value equal to or numerically *higher* than
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ FreeRTOS maintains separate thread and ISR API functions to ensure
+ interrupt entry is as fast and simple as possible.
+
+ The following links provide detailed information:
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html
+ http://www.freertos.org/FAQHelp.html */
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+ /* Priority grouping: The interrupt controller (GIC) allows the bits
+ that define each interrupt's priority to be split between bits that
+ define the interrupt's pre-emption priority bits and bits that define
+ the interrupt's sub-priority. For simplicity all bits must be defined
+ to be pre-emption priority bits. The following assertion will fail if
+ this is not the case (if some bits represent a sub-priority).
+
+ The priority grouping is configured by the GIC's binary point register
+ (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
+ possible value (which may be above 0). */
+ configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
+ }
#endif /* configASSERT_DEFINED */
+
+
+
+
diff --git a/portable/RVDS/ARM_CA9/portmacro.h b/portable/RVDS/ARM_CA9/portmacro.h
index f71deb1..02a7211 100644
--- a/portable/RVDS/ARM_CA9/portmacro.h
+++ b/portable/RVDS/ARM_CA9/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,120 +43,121 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Task utilities. */
/* Called at the end of an ISR that can cause a context switch. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
- }
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{ \
+extern uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+}
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
- #define portYIELD() __asm( "SWI 0" );
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm( "SWI 0" );
/*-----------------------------------------------------------
-* Critical section control
-*----------------------------------------------------------*/
+ * Critical section control
+ *----------------------------------------------------------*/
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern uint32_t ulPortSetInterruptMask( void );
- extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
/* These macros do not globally disable/enable interrupts. They do mask off
- * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
- #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
- #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not required for this port but included in case common demo code that uses these
- * macros is used. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
- * handler for whichever peripheral is used to generate the RTOS tick. */
- void FreeRTOS_Tick_Handler( void );
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- * before any floating point instructions are executed. */
- void vPortTaskUsesFPU( void );
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
- #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
- #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-/*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
- #define portNOP() __nop()
+#define portNOP() __nop()
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/RVDS/ARM_CM0/port.c b/portable/RVDS/ARM_CM0/port.c
index 88d0b12..d4e76ee 100644
--- a/portable/RVDS/ARM_CM0/port.c
+++ b/portable/RVDS/ARM_CM0/port.c
@@ -177,20 +177,21 @@
/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
* table offset register that can be used to locate the initial stack value.
* Not all M0 parts have the application vector table at address 0. */
+ /* *INDENT-OFF* */
ldr r3, = pxCurrentTCB /* Obtain location of pxCurrentTCB. */
- ldr r1, [ r3 ]
+ ldr r1, [ r3 ]
ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
adds r0, # 32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
movs r0, # 2 /* Switch to the psp stack. */
msr CONTROL, r0
isb
- pop {
+ pop {
r0 - r5
} /* Pop the registers that are saved automatically. */
mov lr, r5 /* lr is now in r5. */
- pop {
+ pop {
r3
} /* The return address is now in r3. */
pop {
@@ -199,7 +200,8 @@
cpsie i /* The first task has its context and interrupts can be enabled. */
bx r3 /* Finally, jump to the user defined task code. */
- ALIGN
+ ALIGN
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -289,12 +291,13 @@
extern vTaskSwitchContext
extern pxCurrentTCB
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, psp
ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */
- ldr r2, [ r3 ]
+ ldr r2, [ r3 ]
subs r0, # 32 /* Make space for the remaining low registers. */
str r0, [ r2 ] /* Save the new top of stack. */
@@ -315,7 +318,7 @@
cpsid i
bl vTaskSwitchContext
cpsie i
- pop {
+ pop {
r2, r3
} /* lr goes in r3. r2 now holds tcb pointer. */
@@ -338,7 +341,8 @@
} /* Pop low registers. */
bx r3
- ALIGN
+ ALIGN
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c
index 5ac9d2c..ead2869 100644
--- a/portable/RVDS/ARM_CM3/port.c
+++ b/portable/RVDS/ARM_CM3/port.c
@@ -213,10 +213,11 @@
__asm void vPortSVCHandler( void )
{
+/* *INDENT-OFF* */
PRESERVE8
ldr r3, = pxCurrentTCB /* Restore the context. */
- ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+ ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
ldmia r0 !, {
r4 - r11
@@ -227,16 +228,18 @@
msr basepri, r0
orr r14, # 0xd
bx r14
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
__asm void prvStartFirstTask( void )
{
+/* *INDENT-OFF* */
PRESERVE8
/* Use the NVIC offset register to locate the stack. */
ldr r0, = 0xE000ED08
- ldr r0, [ r0 ]
+ ldr r0, [ r0 ]
ldr r0, [ r0 ]
/* Set the msp back to the start of the stack. */
@@ -247,9 +250,10 @@
dsb
isb
/* Call SVC to start the first task. */
- svc 0
+ svc 0
nop
- nop
+ nop
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -388,13 +392,14 @@
extern pxCurrentTCB;
extern vTaskSwitchContext;
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, psp
isb
- ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */
- ldr r2, [ r3 ]
+ ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
+ ldr r2, [ r3 ]
stmdb r0 !, {
r4 - r11
@@ -404,12 +409,12 @@
stmdb sp !, {
r3, r14
}
- mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0
dsb
isb
bl vTaskSwitchContext
- mov r0, # 0
+ mov r0, #0
msr basepri, r0
ldmia sp !, {
r3, r14
@@ -423,7 +428,8 @@
msr psp, r0
isb
bx r14
- nop
+ nop
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -651,10 +657,12 @@
__asm uint32_t vPortGetIPSR( void )
{
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, ipsr
bx r14
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c
index 488e516..9bf92e6 100644
--- a/portable/RVDS/ARM_CM4F/port.c
+++ b/portable/RVDS/ARM_CM4F/port.c
@@ -240,6 +240,7 @@
__asm void vPortSVCHandler( void )
{
+/* *INDENT-OFF* */
PRESERVE8
/* Get the location of the current TCB. */
@@ -255,16 +256,18 @@
mov r0, # 0
msr basepri, r0
bx r14
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
__asm void prvStartFirstTask( void )
{
+/* *INDENT-OFF* */
PRESERVE8
/* Use the NVIC offset register to locate the stack. */
- ldr r0, = 0xE000ED08
- ldr r0, [ r0 ]
+ ldr r0, =0xE000ED08
+ ldr r0, [ r0 ]
ldr r0, [ r0 ]
/* Set the msp back to the start of the stack. */
msr msp, r0
@@ -273,7 +276,7 @@
* before the scheduler was started - which would otherwise result in the
* unnecessary leaving of space in the SVC stack for lazy saving of FPU
* registers. */
- mov r0, # 0
+ mov r0, #0
msr control, r0
/* Globally enable interrupts. */
cpsie i
@@ -281,25 +284,28 @@
dsb
isb
/* Call SVC to start the first task. */
- svc 0
+ svc 0
nop
- nop
+ nop
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
__asm void prvEnableVFP( void )
{
+/* *INDENT-OFF* */
PRESERVE8
/* The FPU enable bits are in the CPACR. */
- ldr.w r0, = 0xE000ED88
- ldr r1, [ r0 ]
+ ldr.w r0, =0xE000ED88
+ ldr r1, [ r0 ]
/* Enable CP10 and CP11 coprocessors, then save back. */
orr r1, r1, # ( 0xf << 20 )
str r1, [ r0 ]
bx r14
nop
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -453,16 +459,17 @@
extern pxCurrentTCB;
extern vTaskSwitchContext;
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, psp
isb
/* Get the location of the current TCB. */
- ldr r3, = pxCurrentTCB
- ldr r2, [ r3 ]
+ ldr r3, =pxCurrentTCB
+ ldr r2, [ r3 ]
/* Is the task using the FPU context? If so, push high vfp registers. */
- tst r14, # 0x10
+ tst r14, #0x10
it eq
vstmdbeq r0 !, {
s16 - s31
@@ -508,7 +515,7 @@
}
msr psp, r0
- isb
+ isb
#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
#if WORKAROUND_PMU_CM001 == 1
push {
@@ -522,6 +529,7 @@
#endif
bx r14
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -749,10 +757,12 @@
__asm uint32_t vPortGetIPSR( void )
{
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, ipsr
bx r14
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index 18228f4..005881a 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -310,7 +310,8 @@
{
extern prvSVCHandler
- PRESERVE8
+/* *INDENT-OFF* */
+ PRESERVE8
/* Assumes psp was in use. */
#ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
@@ -323,52 +324,69 @@
#endif
b prvSVCHandler
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
__asm void prvRestoreContextOfFirstTask( void )
{
+/* *INDENT-OFF* */
PRESERVE8
- ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */
+ ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [ r0 ]
ldr r0, [ r0 ]
- msr msp, r0 /* Set the msp back to the start of the stack. */
- ldr r3, = pxCurrentTCB /* Restore the context. */
+ msr msp, r0 /* Set the msp back to the start of the stack. */
+ ldr r3, =pxCurrentTCB /* Restore the context. */
ldr r1, [ r3 ]
- ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
- add r1, r1, # 4 /* Move onto the second item in the TCB... */
+ ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
+ add r1, r1, #4 /* Move onto the second item in the TCB... */
- dmb /* Complete outstanding transfers before disabling MPU. */
- ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
- bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- str r3, [ r2 ] /* Disable MPU. */
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r2, =0xe000ed94 /* MPU_CTRL register. */
+ ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
+ bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+ str r3, [ r2 ] /* Disable MPU. */
- ldr r2, = 0xe000ed9c /* Region Base Address register. */
- ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- stmia r2, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ ldr r2, =0xe000ed9c /* Region Base Address register. */
+ ldmia r1 !, {
+ r4 - r11
+ } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ stmia r2, {
+ r4 - r11
+ } /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
-#if ( portTOTAL_NUM_REGIONS == 16 )
- ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
-#endif /* portTOTAL_NUM_REGIONS == 16. */
+ #if ( portTOTAL_NUM_REGIONS == 16 )
+ ldmia r1 !, {
+ r4 - r11
+ } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+ stmia r2, {
+ r4 - r11
+ } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+ ldmia r1 !, {
+ r4 - r11
+ } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+ stmia r2, {
+ r4 - r11
+ } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+ #endif /* portTOTAL_NUM_REGIONS == 16. */
- ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
- orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- str r3, [ r2 ] /* Enable MPU. */
- dsb /* Force memory writes before continuing. */
+ ldr r2, =0xe000ed94 /* MPU_CTRL register. */
+ ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
+ orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+ str r3, [ r2 ] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
- ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
+ ldmia r0 !, {
+ r3 - r11, r14
+ } /* Pop the registers that are not automatically saved on exception entry. */
msr control, r3
- msr psp, r0 /* Restore the task stack pointer. */
- mov r0, # 0
+ msr psp, r0 /* Restore the task stack pointer. */
+ mov r0, #0
msr basepri, r0
bx r14
nop
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -476,10 +494,11 @@
__asm void prvStartFirstTask( void )
{
+/* *INDENT-OFF* */
PRESERVE8
/* Use the NVIC offset register to locate the stack. */
- ldr r0, = 0xE000ED08
+ ldr r0, =0xE000ED08
ldr r0, [ r0 ]
ldr r0, [ r0 ]
/* Set the msp back to the start of the stack. */
@@ -489,7 +508,7 @@
* before the scheduler was started - which would otherwise result in the
* unnecessary leaving of space in the SVC stack for lazy saving of FPU
* registers. */
- mov r0, # 0
+ mov r0, #0
msr control, r0
/* Globally enable interrupts. */
cpsie i
@@ -499,6 +518,7 @@
svc portSVC_START_SCHEDULER /* System call to start first task. */
nop
nop
+/* *INDENT-ON* */
}
void vPortEndScheduler( void )
@@ -542,68 +562,94 @@
extern pxCurrentTCB;
extern vTaskSwitchContext;
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, psp
- ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */
+ ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
ldr r2, [ r3 ]
- tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
+ tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
it eq
- vstmdbeq r0!, {s16-s31}
+ vstmdbeq r0 !, {
+ s16 - s31
+ }
mrs r1, control
- stmdb r0!, {r1, r4-r11, r14} /* Save the remaining registers. */
- str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
+ stmdb r0 !, {
+ r1, r4 - r11, r14
+ } /* Save the remaining registers. */
+ str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
- stmdb sp!, {r0, r3}
+ stmdb sp !, {
+ r0, r3
+ }
mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0
dsb
isb
bl vTaskSwitchContext
- mov r0, # 0
+ mov r0, #0
msr basepri, r0
- ldmia sp!, {r0, r3}
+ ldmia sp !, {
+ r0, r3
+ }
/* Restore the context. */
ldr r1, [ r3 ]
- ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
- add r1, r1, # 4 /* Move onto the second item in the TCB... */
+ ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
+ add r1, r1, #4 /* Move onto the second item in the TCB... */
- dmb /* Complete outstanding transfers before disabling MPU. */
- ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
- bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- str r3, [ r2 ] /* Disable MPU. */
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r2, =0xe000ed94 /* MPU_CTRL register. */
+ ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
+ bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+ str r3, [ r2 ] /* Disable MPU. */
- ldr r2, = 0xe000ed9c /* Region Base Address register. */
- ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- stmia r2, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ ldr r2, =0xe000ed9c /* Region Base Address register. */
+ ldmia r1 !, {
+ r4 - r11
+ } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ stmia r2, {
+ r4 - r11
+ } /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
-#if ( portTOTAL_NUM_REGIONS == 16 )
- ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
-#endif /* portTOTAL_NUM_REGIONS == 16. */
+ #if ( portTOTAL_NUM_REGIONS == 16 )
+ ldmia r1 !, {
+ r4 - r11
+ } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+ stmia r2, {
+ r4 - r11
+ } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+ ldmia r1 !, {
+ r4 - r11
+ } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+ stmia r2, {
+ r4 - r11
+ } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+ #endif /* portTOTAL_NUM_REGIONS == 16. */
- ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
- orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- str r3, [ r2 ] /* Enable MPU. */
- dsb /* Force memory writes before continuing. */
+ ldr r2, =0xe000ed94 /* MPU_CTRL register. */
+ ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
+ orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+ str r3, [ r2 ] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
- ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
+ ldmia r0 !, {
+ r3 - r11, r14
+ } /* Pop the registers that are not automatically saved on exception entry. */
msr control, r3
- tst r14, # 0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
+ tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
it eq
- vldmiaeq r0!, {s16-s31}
+ vldmiaeq r0 !, {
+ s16 - s31
+ }
msr psp, r0
bx r14
nop
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -642,27 +688,31 @@
__asm void vPortSwitchToUserMode( void )
{
+ /* *INDENT-OFF* */
PRESERVE8
mrs r0, control
- orr r0, # 1
+ orr r0, #1
msr control, r0
bx r14
+ /* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
__asm void vPortEnableVFP( void )
{
+/* *INDENT-OFF* */
PRESERVE8
- ldr.w r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */
+ ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
ldr r1, [ r0 ]
- orr r1, r1, # ( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
+ orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
str r1, [ r0 ]
bx r14
nop
nop
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -761,25 +811,29 @@
__asm BaseType_t xIsPrivileged( void )
{
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, control /* r0 = CONTROL. */
- tst r0, # 1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
- movne r0, # 0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- moveq r0, # 1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
bx lr /* Return. */
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
__asm void vResetPrivilege( void )
{
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, control /* r0 = CONTROL. */
- orrs r0, # 1 /* r0 = r0 | 1. */
+ orrs r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return. */
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -886,10 +940,12 @@
__asm uint32_t prvPortGetIPSR( void )
{
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, ipsr
bx r14
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index e5f5b12..589e4eb 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -27,11 +27,13 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,173 +46,174 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* MPU specific constants. */
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
+#define portUSING_MPU_WRAPPERS 1
+#define portPRIVILEGE_BIT ( 0x80000000UL )
- #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
- #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
- #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
- /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
- * Register (RASR). */
- #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
- #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
+#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
- /* MPU settings that can be overriden in FreeRTOSConfig.h. */
- #ifndef configTOTAL_MPU_REGIONS
- /* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
- #endif
+/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
+ * Register (RASR). */
+#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
+#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
- /*
- * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
- * memory type, and where necessary the cacheable and shareable properties
- * of the memory region.
- *
- * The TEX, C, and B bits together indicate the memory type of the region,
- * and:
- * - For Normal memory, the cacheable properties of the region.
- * - For Device memory, whether the region is shareable.
- *
- * For Normal memory regions, the S bit indicates whether the region is
- * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
- *
- * See the following two tables for setting TEX, S, C and B bits for
- * unprivileged flash, privileged flash and privileged RAM regions.
- *
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 1 | Device | Shared device | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 1 | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 011 | X | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
- | | | | | outer cacheability rules that must be exported on the | |
- | | | | | bus. See the table below for the cacheability policy | |
- | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
- +-----------------------------------------+----------------------------------------+
- | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
- +-----------------------------------------+----------------------------------------+
- | 00 | Non-cacheable |
- +-----------------------------------------+----------------------------------------+
- | 01 | Write-back, write and read allocate |
- +-----------------------------------------+----------------------------------------+
- | 10 | Write-through, no write allocate |
- +-----------------------------------------+----------------------------------------+
- | 11 | Write-back, no write allocate |
- +-----------------------------------------+----------------------------------------+
- */
+/*
+ * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
+ * memory type, and where necessary the cacheable and shareable properties
+ * of the memory region.
+ *
+ * The TEX, C, and B bits together indicate the memory type of the region,
+ * and:
+ * - For Normal memory, the cacheable properties of the region.
+ * - For Device memory, whether the region is shareable.
+ *
+ * For Normal memory regions, the S bit indicates whether the region is
+ * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
+ *
+ * See the following two tables for setting TEX, S, C and B bits for
+ * unprivileged flash, privileged flash and privileged RAM regions.
+ *
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 1 | Device | Shared device | Shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 1 | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 1 | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 1 | X | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 011 | X | X | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
+ | | | | | outer cacheability rules that must be exported on the | |
+ | | | | | bus. See the table below for the cacheability policy | |
+ | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ |
+ +-----------------------------------------+----------------------------------------+
+ | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
+ +-----------------------------------------+----------------------------------------+
+ | 00 | Non-cacheable |
+ +-----------------------------------------+----------------------------------------+
+ | 01 | Write-back, write and read allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 10 | Write-through, no write allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 11 | Write-back, no write allocate |
+ +-----------------------------------------+----------------------------------------+
+ */
- /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash
- * region. */
- #ifndef configTEX_S_C_B_FLASH
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_FLASH ( 0x07UL )
- #endif
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash
+ * region. */
+#ifndef configTEX_S_C_B_FLASH
+ /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+ #define configTEX_S_C_B_FLASH ( 0x07UL )
+#endif
- /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM
- * region. */
- #ifndef configTEX_S_C_B_SRAM
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_SRAM ( 0x07UL )
- #endif
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM
+ * region. */
+#ifndef configTEX_S_C_B_SRAM
+ /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+ #define configTEX_S_C_B_SRAM ( 0x07UL )
+#endif
- #define portUNPRIVILEGED_FLASH_REGION ( 0UL )
- #define portPRIVILEGED_FLASH_REGION ( 1UL )
- #define portPRIVILEGED_RAM_REGION ( 2UL )
- #define portGENERAL_PERIPHERALS_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
- #define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
- #define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
+#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
+#define portPRIVILEGED_FLASH_REGION ( 1UL )
+#define portPRIVILEGED_RAM_REGION ( 2UL )
+#define portGENERAL_PERIPHERALS_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
+#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
+#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
- void vPortSwitchToUserMode( void );
- #define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
+void vPortSwitchToUserMode( void );
+#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
- typedef struct MPU_REGION_REGISTERS
- {
- uint32_t ulRegionBaseAddress;
- uint32_t ulRegionAttribute;
- } xMPU_REGION_REGISTERS;
+typedef struct MPU_REGION_REGISTERS
+{
+ uint32_t ulRegionBaseAddress;
+ uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
/* Plus 1 to create space for the stack region. */
- typedef struct MPU_SETTINGS
- {
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/* Constants used with memory barrier intrinsics. */
- #define portSY_FULL_READ_WRITE ( 15 )
+#define portSY_FULL_READ_WRITE ( 15 )
/*-----------------------------------------------------------*/
/* SVC numbers for various services. */
- #define portSVC_START_SCHEDULER 0
- #define portSVC_YIELD 1
- #define portSVC_RAISE_PRIVILEGE 2
+#define portSVC_START_SCHEDULER 0
+#define portSVC_YIELD 1
+#define portSVC_RAISE_PRIVILEGE 2
/* Scheduler utilities. */
- #define portYIELD() __asm{ SVC portSVC_YIELD }
- #define portYIELD_WITHIN_API() \
+#define portYIELD() __asm{ SVC portSVC_YIELD }
+#define portYIELD_WITHIN_API() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -222,180 +225,190 @@
}
/*-----------------------------------------------------------*/
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE __forceinline
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE __forceinline
+#endif
/*-----------------------------------------------------------*/
- extern BaseType_t xIsPrivileged( void );
- extern void vResetPrivilege( void );
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+#define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
*/
- #define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE }
+#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE }
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
+#define portRESET_PRIVILEGE() vResetPrivilege()
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+ __asm
{
- __asm
- {
- /* Barrier instructions are not used as this function is only used to
- * lower the BASEPRI value. */
- msr basepri, ulBASEPRI
- }
+ /* Barrier instructions are not used as this function is only used to
+ * lower the BASEPRI value. */
+/* *INDENT-OFF* */
+ msr basepri, ulBASEPRI
+/* *INDENT-ON* */
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+ uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+ __asm
{
- uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
- __asm
- {
- /* Set BASEPRI to the max syscall priority to effect a critical
- * section. */
- msr basepri, ulNewBASEPRI
- dsb
- isb
- }
+ /* Set BASEPRI to the max syscall priority to effect a critical
+ * section. */
+/* *INDENT-OFF* */
+ msr basepri, ulNewBASEPRI
+ dsb
+ isb
+/* *INDENT-ON* */
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+ __asm
{
- __asm
- {
- /* Set BASEPRI to 0 so no interrupts are masked. This function is only
- * used to lower the mask in an interrupt, so memory barriers are not
- * used. */
- msr basepri, # 0
- }
+ /* Set BASEPRI to 0 so no interrupts are masked. This function is only
+ * used to lower the mask in an interrupt, so memory barriers are not
+ * used. */
+/* *INDENT-OFF* */
+ msr basepri, # 0
+/* *INDENT-ON* */
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+ uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+ __asm
{
- uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
- __asm
- {
- /* Set BASEPRI to the max syscall priority to effect a critical
- * section. */
- mrs ulReturn, basepri
- msr basepri, ulNewBASEPRI
- dsb
- isb
- }
-
- return ulReturn;
+ /* Set BASEPRI to the max syscall priority to effect a critical
+ * section. */
+/* *INDENT-OFF* */
+ mrs ulReturn, basepri
+ msr basepri, ulNewBASEPRI
+ dsb
+ isb
+/* *INDENT-ON* */
}
+
+ return ulReturn;
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm
{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm
- {
- mrs ulCurrentInterrupt, ipsr
- }
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
+ mrs ulCurrentInterrupt, ipsr
}
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
/*-----------------------------------------------------------*/
- #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */
- #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
- #endif
+#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+ #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */
+ #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
+#endif
/*-----------------------------------------------------------*/
- #ifdef __cplusplus
- }
- #endif
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
#endif /* PORTMACRO_H */
diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c
index d206964..0519cac 100644
--- a/portable/RVDS/ARM_CM7/r0p1/port.c
+++ b/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -236,9 +236,10 @@
{
PRESERVE8
+/* *INDENT-OFF* */
/* Get the location of the current TCB. */
- ldr r3, = pxCurrentTCB
- ldr r1, [ r3 ]
+ ldr r3, =pxCurrentTCB
+ ldr r1, [ r3 ]
ldr r0, [ r1 ]
/* Pop the core registers. */
ldmia r0 !, {
@@ -246,19 +247,21 @@
}
msr psp, r0
isb
- mov r0, # 0
+ mov r0, #0
msr basepri, r0
bx r14
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
__asm void prvStartFirstTask( void )
{
+/* *INDENT-OFF* */
PRESERVE8
/* Use the NVIC offset register to locate the stack. */
- ldr r0, = 0xE000ED08
- ldr r0, [ r0 ]
+ ldr r0, =0xE000ED08
+ ldr r0, [ r0 ]
ldr r0, [ r0 ]
/* Set the msp back to the start of the stack. */
msr msp, r0
@@ -267,7 +270,7 @@
* before the scheduler was started - which would otherwise result in the
* unnecessary leaving of space in the SVC stack for lazy saving of FPU
* registers. */
- mov r0, # 0
+ mov r0, #0
msr control, r0
/* Globally enable interrupts. */
cpsie i
@@ -277,23 +280,26 @@
/* Call SVC to start the first task. */
svc 0
nop
- nop
+ nop
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
__asm void prvEnableVFP( void )
{
+/* *INDENT-OFF* */
PRESERVE8
/* The FPU enable bits are in the CPACR. */
- ldr.w r0, = 0xE000ED88
- ldr r1, [ r0 ]
+ ldr.w r0, =0xE000ED88
+ ldr r1, [ r0 ]
/* Enable CP10 and CP11 coprocessors, then save back. */
- orr r1, r1, # ( 0xf << 20 )
+ orr r1, r1, #( 0xf << 20 )
str r1, [ r0 ]
bx r14
nop
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -438,16 +444,17 @@
extern pxCurrentTCB;
extern vTaskSwitchContext;
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, psp
isb
/* Get the location of the current TCB. */
- ldr r3, = pxCurrentTCB
- ldr r2, [ r3 ]
+ ldr r3, =pxCurrentTCB
+ ldr r2, [ r3 ]
/* Is the task using the FPU context? If so, push high vfp registers. */
- tst r14, # 0x10
+ tst r14, #0x10
it eq
vstmdbeq r0 !, {
s16 - s31
@@ -464,14 +471,14 @@
stmdb sp !, {
r0, r3
}
- mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
cpsid i
msr basepri, r0
dsb
isb
cpsie i
bl vTaskSwitchContext
- mov r0, # 0
+ mov r0, #0
msr basepri, r0
ldmia sp !, {
r0, r3
@@ -488,14 +495,14 @@
/* Is the task using the FPU context? If so, pop the high vfp registers
* too. */
- tst r14, # 0x10
+ tst r14, #0x10
it eq
vldmiaeq r0 !, {
s16 - s31
}
msr psp, r0
- isb
+ isb
#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
#if WORKAROUND_PMU_CM001 == 1
push {
@@ -509,6 +516,7 @@
#endif
bx r14
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -736,10 +744,12 @@
__asm uint32_t vPortGetIPSR( void )
{
+/* *INDENT-OFF* */
PRESERVE8
mrs r0, ipsr
bx r14
+/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
diff --git a/portable/Renesas/RX100/port.c b/portable/Renesas/RX100/port.c
index c3ff5df..d947e64 100644
--- a/portable/Renesas/RX100/port.c
+++ b/portable/Renesas/RX100/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RX100 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RX100 port.
+ *----------------------------------------------------------*/
/* Standard C includes. */
#include "limits.h"
@@ -45,35 +45,35 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
/* The peripheral clock is divided by this value before being supplying the
- * CMT. */
+CMT. */
#if ( configUSE_TICKLESS_IDLE == 0 )
- /* If tickless idle is not used then the divisor can be fixed. */
- #define portCLOCK_DIVISOR 8UL
+ /* If tickless idle is not used then the divisor can be fixed. */
+ #define portCLOCK_DIVISOR 8UL
#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
- #define portCLOCK_DIVISOR 512UL
+ #define portCLOCK_DIVISOR 512UL
#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
- #define portCLOCK_DIVISOR 128UL
+ #define portCLOCK_DIVISOR 128UL
#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
- #define portCLOCK_DIVISOR 32UL
+ #define portCLOCK_DIVISOR 32UL
#else
- #define portCLOCK_DIVISOR 8UL
+ #define portCLOCK_DIVISOR 8UL
#endif
/* Keys required to lock and unlock access to certain system registers
- * respectively. */
-#define portUNLOCK_KEY 0xA50B
-#define portLOCK_KEY 0xA500
+respectively. */
+#define portUNLOCK_KEY 0xA50B
+#define portLOCK_KEY 0xA500
/*-----------------------------------------------------------*/
/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- * and therefore installed in the vector table, when the FreeRTOS code is built
- * as a library. */
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
extern BaseType_t vSoftwareInterruptEntry;
const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
@@ -108,10 +108,9 @@
*/
static void prvSetupTimerInterrupt( void );
#ifndef configSETUP_TICK_INTERRUPT
-
-/* The user has not provided their own tick interrupt configuration so use
- * the definition in this file (which uses the interval timer). */
- #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+ /* The user has not provided their own tick interrupt configuration so use
+ the definition in this file (which uses the interval timer). */
+ #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
#endif /* configSETUP_TICK_INTERRUPT */
/*
@@ -120,13 +119,13 @@
* instruction.
*/
#if configUSE_TICKLESS_IDLE == 1
- static void prvSleep( TickType_t xExpectedIdleTime );
+ static void prvSleep( TickType_t xExpectedIdleTime );
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
/* These is accessed by the inline assembler functions. */
-extern void * pxCurrentTCB;
+extern void *pxCurrentTCB;
extern void vTaskSwitchContext( void );
/*-----------------------------------------------------------*/
@@ -136,524 +135,512 @@
#if configUSE_TICKLESS_IDLE == 1
-/* Holds the maximum number of ticks that can be suppressed - which is
- * basically how far into the future an interrupt can be generated. Set
- * during initialisation. This is the maximum possible value that the
- * compare match register can hold divided by ulMatchValueForOneTick. */
- static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+ /* Holds the maximum number of ticks that can be suppressed - which is
+ basically how far into the future an interrupt can be generated. Set
+ during initialisation. This is the maximum possible value that the
+ compare match register can hold divided by ulMatchValueForOneTick. */
+ static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-/* Flag set from the tick interrupt to allow the sleep processing to know if
- * sleep mode was exited because of a tick interrupt, or an interrupt
- * generated by something else. */
- static volatile uint32_t ulTickFlag = pdFALSE;
+ /* Flag set from the tick interrupt to allow the sleep processing to know if
+ sleep mode was exited because of a tick interrupt, or an interrupt
+ generated by something else. */
+ static volatile uint32_t ulTickFlag = pdFALSE;
-/* The CMT counter is stopped temporarily each time it is re-programmed.
- * The following constant offsets the CMT counter match value by the number of
- * CMT counts that would typically be missed while the counter was stopped to
- * compensate for the lost time. The large difference between the divided CMT
- * clock and the CPU clock means it is likely ulStoppedTimerCompensation will
- * equal zero - and be optimised away. */
- static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
+ /* The CMT counter is stopped temporarily each time it is re-programmed.
+ The following constant offsets the CMT counter match value by the number of
+ CMT counts that would typically be missed while the counter was stopped to
+ compensate for the lost time. The large difference between the divided CMT
+ clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+ equal zero - and be optimised away. */
+ static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
-#endif /* if configUSE_TICKLESS_IDLE == 1 */
+#endif
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Offset to end up on 8 byte boundary. */
- pxTopOfStack--;
+ /* Offset to end up on 8 byte boundary. */
+ pxTopOfStack--;
- /* R0 is not included as it is the stack pointer. */
+ /* R0 is not included as it is the stack pointer. */
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
*pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
- /* When debugging it can be useful if every register is set to a known
- * value. Otherwise code space can be saved by just setting the registers
- * that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaabbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
- {
- /* Leave space for the registers that will get popped from the stack
- * when the task first starts executing. */
- pxTopOfStack -= 15;
- }
- #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaabbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ /* Leave space for the registers that will get popped from the stack
+ when the task first starts executing. */
+ pxTopOfStack -= 15;
+ }
+ #endif
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* Accumulator. */
- pxTopOfStack--;
- *pxTopOfStack = 0x87654321; /* Accumulator. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* Accumulator. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x87654321; /* Accumulator. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate
- * the tick interrupt. This way the application can decide which
- * peripheral to use. If tickless mode is used then the default
- * implementation defined in this file (which uses CMT0) should not be
- * overridden. */
- configSETUP_TICK_INTERRUPT();
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate
+ the tick interrupt. This way the application can decide which
+ peripheral to use. If tickless mode is used then the default
+ implementation defined in this file (which uses CMT0) should not be
+ overridden. */
+ configSETUP_TICK_INTERRUPT();
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the first task. */
- prvStartFirstTask();
- }
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
- /* Execution should not reach here as the tasks are now running!
- * prvSetupTimerInterrupt() is called here to prevent the compiler outputting
- * a warning about a statically declared function not being referenced in the
- * case that the application writer has provided their own tick interrupt
- * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
- * their own routine will be called in place of prvSetupTimerInterrupt()). */
- prvSetupTimerInterrupt();
+ /* Execution should not reach here as the tasks are now running!
+ prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+ a warning about a statically declared function not being referenced in the
+ case that the application writer has provided their own tick interrupt
+ configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+ their own routine will be called in place of prvSetupTimerInterrupt()). */
+ prvSetupTimerInterrupt();
- /* Just to make sure the function is not optimised away. */
- ( void ) vSoftwareInterruptISR();
+ /* Just to make sure the function is not optimised away. */
+ ( void ) vSoftwareInterruptISR();
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
#pragma inline_asm prvStartFirstTask
static void prvStartFirstTask( void )
{
- /* When starting the scheduler there is nothing that needs moving to the
- * interrupt stack because the function is not called from an interrupt.
- * Just ensure the current stack is the user stack. */
- SETPSW U
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ SETPSW U
- /* Obtain the location of the stack associated with which ever task
- * pxCurrentTCB is currently pointing to. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L[ R15 ], R0
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ MOV.L #_pxCurrentTCB, R15
+ MOV.L [R15], R15
+ MOV.L [R15], R0
- /* Restore the registers from the stack of the task pointed to by
- * pxCurrentTCB. */
- POP R15
- MVTACLO R15 /* Accumulator low 32 bits. */
- POP R15
- MVTACHI R15 /* Accumulator high 32 bits. */
- POPM R1 - R15 /* R1 to R15 - R0 is not included as it is the SP. */
- RTE /* This pops the remaining registers. */
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ POP R15
+ MVTACLO R15 /* Accumulator low 32 bits. */
+ POP R15
+ MVTACHI R15 /* Accumulator high 32 bits. */
+ POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */
+ RTE /* This pops the remaining registers. */
NOP
- NOP
+ NOP
}
/*-----------------------------------------------------------*/
#pragma interrupt ( prvTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
void prvTickISR( void )
{
- /* Increment the tick, and perform any processing the new tick value
- * necessitates. */
- set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. */
+ set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ set_ipl( configKERNEL_INTERRUPT_PRIORITY );
- set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+ #if configUSE_TICKLESS_IDLE == 1
+ {
+ /* The CPU woke because of a tick. */
+ ulTickFlag = pdTRUE;
- #if configUSE_TICKLESS_IDLE == 1
- {
- /* The CPU woke because of a tick. */
- ulTickFlag = pdTRUE;
-
- /* If this is the first tick since exiting tickless mode then the CMT
- * compare match value needs resetting. */
- CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
- }
- #endif
+ /* If this is the first tick since exiting tickless mode then the CMT
+ compare match value needs resetting. */
+ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+ }
+ #endif
}
/*-----------------------------------------------------------*/
void vSoftwareInterruptISR( void )
{
- prvYieldHandler();
+ prvYieldHandler();
}
/*-----------------------------------------------------------*/
#pragma inline_asm prvYieldHandler
static void prvYieldHandler( void )
{
- /* Re-enable interrupts. */
- SETPSW I
+ /* Re-enable interrupts. */
+ SETPSW I
- /* Move the data that was automatically pushed onto the interrupt stack
- * when the interrupt occurred from the interrupt stack to the user stack.
- *
- * R15 is saved before it is clobbered. */
- PUSH.L R15
+ /* Move the data that was automatically pushed onto the interrupt stack
+ when the interrupt occurred from the interrupt stack to the user stack.
- /* Read the user stack pointer. */
- MVFC USP, R15
+ R15 is saved before it is clobbered. */
+ PUSH.L R15
- /* Move the address down to the data being moved. */
- SUB # 12, R15
- MVTC R15, USP
+ /* Read the user stack pointer. */
+ MVFC USP, R15
- /* Copy the data across. */
- MOV.L[ R0 ], [ R15 ];
- R15
+ /* Move the address down to the data being moved. */
+ SUB #12, R15
+ MVTC R15, USP
- MOV.L 4[ R0 ], 4[ R15 ];
- PC
- MOV.L 8[ R0 ], 8[ R15 ];
- PSW
+ /* Copy the data across. */
+ MOV.L [ R0 ], [ R15 ] ; R15
+ MOV.L 4[ R0 ], 4[ R15 ] ; PC
+ MOV.L 8[ R0 ], 8[ R15 ] ; PSW
- /* Move the interrupt stack pointer to its new correct position. */
- ADD # 12, R0
+ /* Move the interrupt stack pointer to its new correct position. */
+ ADD #12, R0
- /* All the rest of the registers are saved directly to the user stack. */
- SETPSW U
+ /* All the rest of the registers are saved directly to the user stack. */
+ SETPSW U
- /* Save the rest of the general registers (R15 has been saved already). */
- PUSHM R1 - R14
+ /* Save the rest of the general registers (R15 has been saved already). */
+ PUSHM R1-R14
- /* Save the accumulator. */
- MVFACHI R15
- PUSH.L R15
- MVFACMI R15;
- Middle order word.
- SHLL # 16, R15;
- Shifted left as it is restored to the low order word.
- PUSH.L R15
+ /* Save the accumulator. */
+ MVFACHI R15
+ PUSH.L R15
+ MVFACMI R15 ; Middle order word.
+ SHLL #16, R15 ; Shifted left as it is restored to the low order word.
+ PUSH.L R15
- /* Save the stack pointer to the TCB. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L R0, [ R15 ]
+ /* Save the stack pointer to the TCB. */
+ MOV.L #_pxCurrentTCB, R15
+ MOV.L [ R15 ], R15
+ MOV.L R0, [ R15 ]
- /* Ensure the interrupt mask is set to the syscall priority while the
- * kernel structures are being accessed. */
- MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY
+ /* Ensure the interrupt mask is set to the syscall priority while the
+ kernel structures are being accessed. */
+ MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
- /* Select the next task to run. */
- BSR.A _vTaskSwitchContext
+ /* Select the next task to run. */
+ BSR.A _vTaskSwitchContext
- /* Reset the interrupt mask as no more data structure access is
- * required. */
- MVTIPL # configKERNEL_INTERRUPT_PRIORITY
+ /* Reset the interrupt mask as no more data structure access is
+ required. */
+ MVTIPL #configKERNEL_INTERRUPT_PRIORITY
- /* Load the stack pointer of the task that is now selected as the Running
- * state task from its TCB. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L[ R15 ], R0
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ MOV.L #_pxCurrentTCB,R15
+ MOV.L [ R15 ], R15
+ MOV.L [ R15 ], R0
- /* Restore the context of the new task. The PSW (Program Status Word) and
- * PC will be popped by the RTE instruction. */
- POP R15
- MVTACLO R15
- POP R15
- MVTACHI R15
- POPM R1 - R15
- RTE
- NOP
- NOP
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ POP R15
+ MVTACLO R15
+ POP R15
+ MVTACHI R15
+ POPM R1-R15
+ RTE
+ NOP
+ NOP
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
- /* The following line is just to prevent the symbol getting optimised away. */
- ( void ) vTaskSwitchContext();
+ /* The following line is just to prevent the symbol getting optimised away. */
+ ( void ) vTaskSwitchContext();
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- /* Unlock. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+ /* Unlock. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
- /* Enable CMT0. */
- MSTP( CMT0 ) = 0;
+ /* Enable CMT0. */
+ MSTP( CMT0 ) = 0;
- /* Lock again. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
+ /* Lock again. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
- /* Interrupt on compare match. */
- CMT0.CMCR.BIT.CMIE = 1;
+ /* Interrupt on compare match. */
+ CMT0.CMCR.BIT.CMIE = 1;
- /* Set the compare match value. */
- CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+ /* Set the compare match value. */
+ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
- /* Divide the PCLK. */
- #if portCLOCK_DIVISOR == 512
- {
- CMT0.CMCR.BIT.CKS = 3;
- }
- #elif portCLOCK_DIVISOR == 128
- {
- CMT0.CMCR.BIT.CKS = 2;
- }
- #elif portCLOCK_DIVISOR == 32
- {
- CMT0.CMCR.BIT.CKS = 1;
- }
- #elif portCLOCK_DIVISOR == 8
- {
- CMT0.CMCR.BIT.CKS = 0;
- }
- #else /* if portCLOCK_DIVISOR == 512 */
- {
- #error Invalid portCLOCK_DIVISOR setting
- }
- #endif /* if portCLOCK_DIVISOR == 512 */
+ /* Divide the PCLK. */
+ #if portCLOCK_DIVISOR == 512
+ {
+ CMT0.CMCR.BIT.CKS = 3;
+ }
+ #elif portCLOCK_DIVISOR == 128
+ {
+ CMT0.CMCR.BIT.CKS = 2;
+ }
+ #elif portCLOCK_DIVISOR == 32
+ {
+ CMT0.CMCR.BIT.CKS = 1;
+ }
+ #elif portCLOCK_DIVISOR == 8
+ {
+ CMT0.CMCR.BIT.CKS = 0;
+ }
+ #else
+ {
+ #error Invalid portCLOCK_DIVISOR setting
+ }
+ #endif
- /* Enable the interrupt... */
- _IEN( _CMT0_CMI0 ) = 1;
+ /* Enable the interrupt... */
+ _IEN( _CMT0_CMI0 ) = 1;
- /* ...and set its priority to the application defined kernel priority. */
- _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* ...and set its priority to the application defined kernel priority. */
+ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the timer. */
- CMT.CMSTR0.BIT.STR0 = 1;
+ /* Start the timer. */
+ CMT.CMSTR0.BIT.STR0 = 1;
}
/*-----------------------------------------------------------*/
#if configUSE_TICKLESS_IDLE == 1
- static void prvSleep( TickType_t xExpectedIdleTime )
- {
- /* Allow the application to define some pre-sleep processing. */
- configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
+ static void prvSleep( TickType_t xExpectedIdleTime )
+ {
+ /* Allow the application to define some pre-sleep processing. */
+ configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
- /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
- * means the application defined code has already executed the WAIT
- * instruction. */
- if( xExpectedIdleTime > 0 )
- {
- wait();
- }
+ /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
+ means the application defined code has already executed the WAIT
+ instruction. */
+ if( xExpectedIdleTime > 0 )
+ {
+ wait();
+ }
- /* Allow the application to define some post sleep processing. */
- configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
- }
+ /* Allow the application to define some post sleep processing. */
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
#if configUSE_TICKLESS_IDLE == 1
- void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
- {
- uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
- eSleepModeStatus eSleepAction;
+ void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+ eSleepModeStatus eSleepAction;
- /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
+ /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
- /* Make sure the CMT reload value does not overflow the counter. */
- if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
- {
- xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
- }
+ /* Make sure the CMT reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
- /* Calculate the reload value required to wait xExpectedIdleTime tick
- * periods. */
- ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+ /* Calculate the reload value required to wait xExpectedIdleTime tick
+ periods. */
+ ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+ if( ulMatchValue > ulStoppedTimerCompensation )
+ {
+ /* Compensate for the fact that the CMT is going to be stopped
+ momentarily. */
+ ulMatchValue -= ulStoppedTimerCompensation;
+ }
- if( ulMatchValue > ulStoppedTimerCompensation )
- {
- /* Compensate for the fact that the CMT is going to be stopped
- * momentarily. */
- ulMatchValue -= ulStoppedTimerCompensation;
- }
+ /* Stop the CMT momentarily. The time the CMT is stopped for is
+ accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ CMT.CMSTR0.BIT.STR0 = 0;
+ while( CMT.CMSTR0.BIT.STR0 == 1 )
+ {
+ /* Nothing to do here. */
+ }
- /* Stop the CMT momentarily. The time the CMT is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- CMT.CMSTR0.BIT.STR0 = 0;
+ /* Critical section using the global interrupt bit as the i bit is
+ automatically reset by the WAIT instruction. */
+ clrpsw_i();
- while( CMT.CMSTR0.BIT.STR0 == 1 )
- {
- /* Nothing to do here. */
- }
+ /* The tick flag is set to false before sleeping. If it is true when
+ sleep mode is exited then sleep mode was probably exited because the
+ tick was suppressed for the entire xExpectedIdleTime period. */
+ ulTickFlag = pdFALSE;
- /* Critical section using the global interrupt bit as the i bit is
- * automatically reset by the WAIT instruction. */
- clrpsw_i();
+ /* If a context switch is pending then abandon the low power entry as
+ the context switch might have been pended by an external interrupt that
+ requires processing. */
+ eSleepAction = eTaskConfirmSleepModeStatus();
+ if( eSleepAction == eAbortSleep )
+ {
+ /* Restart tick. */
+ CMT.CMSTR0.BIT.STR0 = 1;
+ setpsw_i();
+ }
+ else if( eSleepAction == eNoTasksWaitingTimeout )
+ {
+ /* Protection off. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
- /* The tick flag is set to false before sleeping. If it is true when
- * sleep mode is exited then sleep mode was probably exited because the
- * tick was suppressed for the entire xExpectedIdleTime period. */
- ulTickFlag = pdFALSE;
+ /* Ready for software standby with all clocks stopped. */
+ SYSTEM.SBYCR.BIT.SSBY = 1;
- /* If a context switch is pending then abandon the low power entry as
- * the context switch might have been pended by an external interrupt that
- * requires processing. */
- eSleepAction = eTaskConfirmSleepModeStatus();
+ /* Protection on. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
- if( eSleepAction == eAbortSleep )
- {
- /* Restart tick. */
- CMT.CMSTR0.BIT.STR0 = 1;
- setpsw_i();
- }
- else if( eSleepAction == eNoTasksWaitingTimeout )
- {
- /* Protection off. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+ /* Sleep until something happens. Calling prvSleep() will
+ automatically reset the i bit in the PSW. */
+ prvSleep( xExpectedIdleTime );
- /* Ready for software standby with all clocks stopped. */
- SYSTEM.SBYCR.BIT.SSBY = 1;
+ /* Restart the CMT. */
+ CMT.CMSTR0.BIT.STR0 = 1;
+ }
+ else
+ {
+ /* Protection off. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
- /* Protection on. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
+ /* Ready for deep sleep mode. */
+ SYSTEM.MSTPCRC.BIT.DSLPE = 1;
+ SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
+ SYSTEM.SBYCR.BIT.SSBY = 0;
- /* Sleep until something happens. Calling prvSleep() will
- * automatically reset the i bit in the PSW. */
- prvSleep( xExpectedIdleTime );
+ /* Protection on. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
- /* Restart the CMT. */
- CMT.CMSTR0.BIT.STR0 = 1;
- }
- else
- {
- /* Protection off. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+ /* Adjust the match value to take into account that the current
+ time slice is already partially complete. */
+ ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
- /* Ready for deep sleep mode. */
- SYSTEM.MSTPCRC.BIT.DSLPE = 1;
- SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
- SYSTEM.SBYCR.BIT.SSBY = 0;
+ /* Restart the CMT to count up to the new match value. */
+ CMT0.CMCNT = 0;
+ CMT.CMSTR0.BIT.STR0 = 1;
- /* Protection on. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
+ /* Sleep until something happens. Calling prvSleep() will
+ automatically reset the i bit in the PSW. */
+ prvSleep( xExpectedIdleTime );
- /* Adjust the match value to take into account that the current
- * time slice is already partially complete. */
- ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+ /* Stop CMT. Again, the time the SysTick is stopped for is
+ accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ CMT.CMSTR0.BIT.STR0 = 0;
+ while( CMT.CMSTR0.BIT.STR0 == 1 )
+ {
+ /* Nothing to do here. */
+ }
- /* Restart the CMT to count up to the new match value. */
- CMT0.CMCNT = 0;
- CMT.CMSTR0.BIT.STR0 = 1;
+ ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
- /* Sleep until something happens. Calling prvSleep() will
- * automatically reset the i bit in the PSW. */
- prvSleep( xExpectedIdleTime );
+ if( ulTickFlag != pdFALSE )
+ {
+ /* The tick interrupt has already executed, although because
+ this function is called with the scheduler suspended the actual
+ tick processing will not occur until after this function has
+ exited. Reset the match value with whatever remains of this
+ tick period. */
+ ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
- /* Stop CMT. Again, the time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- CMT.CMSTR0.BIT.STR0 = 0;
+ /* The tick interrupt handler will already have pended the tick
+ processing in the kernel. As the pending tick will be
+ processed as soon as this function exits, the tick value
+ maintained by the tick is stepped forward by one less than the
+ time spent sleeping. The actual stepping of the tick appears
+ later in this function. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep.
+ How many complete tick periods passed while the processor was
+ sleeping? */
+ ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
- while( CMT.CMSTR0.BIT.STR0 == 1 )
- {
- /* Nothing to do here. */
- }
+ /* The match value is set to whatever fraction of a single tick
+ period remains. */
+ ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+ }
- ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
+ /* Restart the CMT so it runs up to the match value. The match value
+ will get set to the value required to generate exactly one tick period
+ the next time the CMT interrupt executes. */
+ CMT0.CMCNT = 0;
+ CMT.CMSTR0.BIT.STR0 = 1;
- if( ulTickFlag != pdFALSE )
- {
- /* The tick interrupt has already executed, although because
- * this function is called with the scheduler suspended the actual
- * tick processing will not occur until after this function has
- * exited. Reset the match value with whatever remains of this
- * tick period. */
- ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
- /* The tick interrupt handler will already have pended the tick
- * processing in the kernel. As the pending tick will be
- * processed as soon as this function exits, the tick value
- * maintained by the tick is stepped forward by one less than the
- * time spent sleeping. The actual stepping of the tick appears
- * later in this function. */
- ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
- }
- else
- {
- /* Something other than the tick interrupt ended the sleep.
- * How many complete tick periods passed while the processor was
- * sleeping? */
- ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
-
- /* The match value is set to whatever fraction of a single tick
- * period remains. */
- ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
- }
-
- /* Restart the CMT so it runs up to the match value. The match value
- * will get set to the value required to generate exactly one tick period
- * the next time the CMT interrupt executes. */
- CMT0.CMCNT = 0;
- CMT.CMSTR0.BIT.STR0 = 1;
-
- /* Wind the tick forward by the number of tick periods that the CPU
- * remained in a low power state. */
- vTaskStepTick( ulCompleteTickPeriods );
- }
- }
+ /* Wind the tick forward by the number of tick periods that the CPU
+ remained in a low power state. */
+ vTaskStepTick( ulCompleteTickPeriods );
+ }
+ }
#endif /* configUSE_TICKLESS_IDLE */
+
diff --git a/portable/Renesas/RX100/portmacro.h b/portable/Renesas/RX100/portmacro.h
index b9c029a..2f71e7e 100644
--- a/portable/Renesas/RX100/portmacro.h
+++ b/portable/Renesas/RX100/portmacro.h
@@ -27,14 +27,14 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Hardware specifics. */
- #include "machine.h"
+#include "machine.h"
/*-----------------------------------------------------------
* Port specific definitions.
@@ -47,104 +47,105 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other
- * than portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+than portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() nop()
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() nop()
- #pragma inline_asm vPortYield
- static void vPortYield( void )
- {
- /* Save clobbered register - may not actually be necessary if inline asm
- * functions are considered to use the same rules as function calls by the
- * compiler. */
- PUSH.L R5
- /* Set ITU SWINTR. */
- MOV.L # 872E0H, R5
- MOV.B # 1, [ R5 ]
- /* Read back to ensure the value is taken before proceeding. */
- MOV.L[ R5 ], R5
- /* Restore clobbered register to its previous value. */
- POP R5
- }
- #define portYIELD() vPortYield()
- #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) { portYIELD(); }
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+ /* Save clobbered register - may not actually be necessary if inline asm
+ functions are considered to use the same rules as function calls by the
+ compiler. */
+ PUSH.L R5
+ /* Set ITU SWINTR. */
+ MOV.L #872E0H, R5
+ MOV.B #1, [R5]
+ /* Read back to ensure the value is taken before proceeding. */
+ MOV.L [R5], R5
+ /* Restore clobbered register to its previous value. */
+ POP R5
+}
+#define portYIELD() vPortYield()
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) { portYIELD(); }
/* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
- * functions are those that end in FromISR. FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
- #define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 )
- #ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #else
- #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #endif
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+ #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
- #define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( signed long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( signed long ) uxSavedInterruptStatus )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
- #if configUSE_TICKLESS_IDLE == 1
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
- #endif
+#if configUSE_TICKLESS_IDLE == 1
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+#endif
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/Renesas/RX200/port.c b/portable/Renesas/RX200/port.c
index ee4e5b6..975722f 100644
--- a/portable/Renesas/RX200/port.c
+++ b/portable/Renesas/RX200/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RX200 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RX200 port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -42,14 +42,14 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
/*-----------------------------------------------------------*/
/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- * and therefore installed in the vector table, when the FreeRTOS code is built
- * as a library. */
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
extern BaseType_t vSoftwareInterruptEntry;
const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
@@ -79,8 +79,8 @@
/*-----------------------------------------------------------*/
/* This is accessed by the inline assembler functions so is file scope for
- * convenience. */
-extern void * pxCurrentTCB;
+convenience. */
+extern void *pxCurrentTCB;
extern void vTaskSwitchContext( void );
/*-----------------------------------------------------------*/
@@ -88,243 +88,237 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Offset to end up on 8 byte boundary. */
- pxTopOfStack--;
+ /* Offset to end up on 8 byte boundary. */
+ pxTopOfStack--;
- /* R0 is not included as it is the stack pointer. */
+ /* R0 is not included as it is the stack pointer. */
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
*pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
- /* When debugging it can be useful if every register is set to a known
- * value. Otherwise code space can be saved by just setting the registers
- * that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaabbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
- {
- pxTopOfStack -= 15;
- }
- #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaabbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= 15;
+ }
+ #endif
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* Accumulator. */
- pxTopOfStack--;
- *pxTopOfStack = 0x87654321; /* Accumulator. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* Accumulator. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x87654321; /* Accumulator. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate the
- * tick interrupt. This way the application can decide which peripheral to
- * use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the first task. */
- prvStartFirstTask();
- }
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
- /* Just to make sure the function is not optimised away. */
- ( void ) vSoftwareInterruptISR();
+ /* Just to make sure the function is not optimised away. */
+ ( void ) vSoftwareInterruptISR();
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
#pragma inline_asm prvStartFirstTask
static void prvStartFirstTask( void )
{
- /* When starting the scheduler there is nothing that needs moving to the
- * interrupt stack because the function is not called from an interrupt.
- * Just ensure the current stack is the user stack. */
- SETPSW U
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ SETPSW U
- /* Obtain the location of the stack associated with which ever task
- * pxCurrentTCB is currently pointing to. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L[ R15 ], R0
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ MOV.L #_pxCurrentTCB, R15
+ MOV.L [R15], R15
+ MOV.L [R15], R0
- /* Restore the registers from the stack of the task pointed to by
- * pxCurrentTCB. */
- POP R15
- MVTACLO R15 /* Accumulator low 32 bits. */
- POP R15
- MVTACHI R15 /* Accumulator high 32 bits. */
- POPM R1 - R15 /* R1 to R15 - R0 is not included as it is the SP. */
- RTE /* This pops the remaining registers. */
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ POP R15
+ MVTACLO R15 /* Accumulator low 32 bits. */
+ POP R15
+ MVTACHI R15 /* Accumulator high 32 bits. */
+ POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */
+ RTE /* This pops the remaining registers. */
NOP
- NOP
+ NOP
}
/*-----------------------------------------------------------*/
#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
void vTickISR( void )
{
- /* Increment the tick, and perform any processing the new tick value
- * necessitates. */
- set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
-
- set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. */
+ set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ set_ipl( configKERNEL_INTERRUPT_PRIORITY );
}
/*-----------------------------------------------------------*/
void vSoftwareInterruptISR( void )
{
- prvYieldHandler();
+ prvYieldHandler();
}
/*-----------------------------------------------------------*/
#pragma inline_asm prvYieldHandler
static void prvYieldHandler( void )
{
- /* Re-enable interrupts. */
- SETPSW I
+ /* Re-enable interrupts. */
+ SETPSW I
- /* Move the data that was automatically pushed onto the interrupt stack when
- * the interrupt occurred from the interrupt stack to the user stack.
- *
- * R15 is saved before it is clobbered. */
- PUSH.L R15
+ /* Move the data that was automatically pushed onto the interrupt stack when
+ the interrupt occurred from the interrupt stack to the user stack.
- /* Read the user stack pointer. */
- MVFC USP, R15
+ R15 is saved before it is clobbered. */
+ PUSH.L R15
- /* Move the address down to the data being moved. */
- SUB # 12, R15
- MVTC R15, USP
+ /* Read the user stack pointer. */
+ MVFC USP, R15
- /* Copy the data across. */
- MOV.L[ R0 ], [ R15 ];
- R15
+ /* Move the address down to the data being moved. */
+ SUB #12, R15
+ MVTC R15, USP
- MOV.L 4[ R0 ], 4[ R15 ];
- PC
- MOV.L 8[ R0 ], 8[ R15 ];
- PSW
+ /* Copy the data across. */
+ MOV.L [ R0 ], [ R15 ] ; R15
+ MOV.L 4[ R0 ], 4[ R15 ] ; PC
+ MOV.L 8[ R0 ], 8[ R15 ] ; PSW
- /* Move the interrupt stack pointer to its new correct position. */
- ADD # 12, R0
+ /* Move the interrupt stack pointer to its new correct position. */
+ ADD #12, R0
- /* All the rest of the registers are saved directly to the user stack. */
- SETPSW U
+ /* All the rest of the registers are saved directly to the user stack. */
+ SETPSW U
- /* Save the rest of the general registers (R15 has been saved already). */
- PUSHM R1 - R14
+ /* Save the rest of the general registers (R15 has been saved already). */
+ PUSHM R1-R14
- /* Save the accumulator. */
- MVFACHI R15
- PUSH.L R15
- MVFACMI R15;
- Middle order word.
- SHLL # 16, R15;
- Shifted left as it is restored to the low order word.
- PUSH.L R15
+ /* Save the accumulator. */
+ MVFACHI R15
+ PUSH.L R15
+ MVFACMI R15 ; Middle order word.
+ SHLL #16, R15 ; Shifted left as it is restored to the low order word.
+ PUSH.L R15
- /* Save the stack pointer to the TCB. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L R0, [ R15 ]
+ /* Save the stack pointer to the TCB. */
+ MOV.L #_pxCurrentTCB, R15
+ MOV.L [ R15 ], R15
+ MOV.L R0, [ R15 ]
- /* Ensure the interrupt mask is set to the syscall priority while the kernel
- * structures are being accessed. */
- MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel
+ structures are being accessed. */
+ MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
- /* Select the next task to run. */
- BSR.A _vTaskSwitchContext
+ /* Select the next task to run. */
+ BSR.A _vTaskSwitchContext
- /* Reset the interrupt mask as no more data structure access is required. */
- MVTIPL # configKERNEL_INTERRUPT_PRIORITY
+ /* Reset the interrupt mask as no more data structure access is required. */
+ MVTIPL #configKERNEL_INTERRUPT_PRIORITY
- /* Load the stack pointer of the task that is now selected as the Running
- * state task from its TCB. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L[ R15 ], R0
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ MOV.L #_pxCurrentTCB,R15
+ MOV.L [ R15 ], R15
+ MOV.L [ R15 ], R0
- /* Restore the context of the new task. The PSW (Program Status Word) and
- * PC will be popped by the RTE instruction. */
- POP R15
- MVTACLO R15
- POP R15
- MVTACHI R15
- POPM R1 - R15
- RTE
- NOP
- NOP
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ POP R15
+ MVTACLO R15
+ POP R15
+ MVTACHI R15
+ POPM R1-R15
+ RTE
+ NOP
+ NOP
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
- /* The following line is just to prevent the symbol getting optimised away. */
- ( void ) vTaskSwitchContext();
+ /* The following line is just to prevent the symbol getting optimised away. */
+ ( void ) vTaskSwitchContext();
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/Renesas/RX200/portmacro.h b/portable/Renesas/RX200/portmacro.h
index c1a58b5..4abab1c 100644
--- a/portable/Renesas/RX200/portmacro.h
+++ b/portable/Renesas/RX200/portmacro.h
@@ -27,14 +27,14 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Hardware specifics. */
- #include "machine.h"
+#include "machine.h"
/*-----------------------------------------------------------
* Port specific definitions.
@@ -47,94 +47,95 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() nop()
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() nop()
- #pragma inline_asm vPortYield
- static void vPortYield( void )
- {
- /* Save clobbered register - may not actually be necessary if inline asm
- * functions are considered to use the same rules as function calls by the
- * compiler. */
- PUSH.L R5
- /* Set ITU SWINTR. */
- MOV.L # 553696, R5
- MOV.B # 1, [ R5 ]
- /* Read back to ensure the value is taken before proceeding. */
- MOV.L[ R5 ], R5
- /* Restore clobbered register to its previous value. */
- POP R5
- }
- #define portYIELD() vPortYield()
- #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+ /* Save clobbered register - may not actually be necessary if inline asm
+ functions are considered to use the same rules as function calls by the
+ compiler. */
+ PUSH.L R5
+ /* Set ITU SWINTR. */
+ MOV.L #553696, R5
+ MOV.B #1, [R5]
+ /* Read back to ensure the value is taken before proceeding. */
+ MOV.L [R5], R5
+ /* Restore clobbered register to its previous value. */
+ POP R5
+}
+#define portYIELD() vPortYield()
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
- * functions are those that end in FromISR. FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
- #define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 )
- #ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #else
- #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #endif
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+ #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
- #define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/Renesas/RX600/port.c b/portable/Renesas/RX600/port.c
index 2d9db43..aa6010c 100644
--- a/portable/Renesas/RX600/port.c
+++ b/portable/Renesas/RX600/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RX600 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RX600 port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -42,15 +42,15 @@
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
+PSW is set with U and I set, and PM and IPL clear. */
#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
/*-----------------------------------------------------------*/
/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- * and therefore installed in the vector table, when the FreeRTOS code is built
- * as a library. */
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
extern BaseType_t vSoftwareInterruptEntry;
const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
@@ -80,8 +80,8 @@
/*-----------------------------------------------------------*/
/* This is accessed by the inline assembler functions so is file scope for
- * convenience. */
-extern void * pxCurrentTCB;
+convenience. */
+extern void *pxCurrentTCB;
extern void vTaskSwitchContext( void );
/*-----------------------------------------------------------*/
@@ -89,247 +89,241 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* R0 is not included as it is the stack pointer. */
+ /* R0 is not included as it is the stack pointer. */
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
- /* When debugging it can be useful if every register is set to a known
- * value. Otherwise code space can be saved by just setting the registers
- * that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0xffffffff; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xeeeeeeee;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
- {
- pxTopOfStack -= 15;
- }
- #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0xffffffff; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xeeeeeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= 15;
+ }
+ #endif
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_FPSW;
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* Accumulator. */
- pxTopOfStack--;
- *pxTopOfStack = 0x87654321; /* Accumulator. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_FPSW;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* Accumulator. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x87654321; /* Accumulator. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate the
- * tick interrupt. This way the application can decide which peripheral to
- * use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the first task. */
- prvStartFirstTask();
- }
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
- /* Just to make sure the function is not optimised away. */
- ( void ) vSoftwareInterruptISR();
+ /* Just to make sure the function is not optimised away. */
+ ( void ) vSoftwareInterruptISR();
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
#pragma inline_asm prvStartFirstTask
static void prvStartFirstTask( void )
{
- /* When starting the scheduler there is nothing that needs moving to the
- * interrupt stack because the function is not called from an interrupt.
- * Just ensure the current stack is the user stack. */
- SETPSW U
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ SETPSW U
- /* Obtain the location of the stack associated with which ever task
- * pxCurrentTCB is currently pointing to. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L[ R15 ], R0
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ MOV.L #_pxCurrentTCB, R15
+ MOV.L [R15], R15
+ MOV.L [R15], R0
- /* Restore the registers from the stack of the task pointed to by
- * pxCurrentTCB. */
- POP R15
- MVTACLO R15 /* Accumulator low 32 bits. */
- POP R15
- MVTACHI R15 /* Accumulator high 32 bits. */
- POP R15
- MVTC R15, FPSW /* Floating point status word. */
- POPM R1 - R15 /* R1 to R15 - R0 is not included as it is the SP. */
- RTE /* This pops the remaining registers. */
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ POP R15
+ MVTACLO R15 /* Accumulator low 32 bits. */
+ POP R15
+ MVTACHI R15 /* Accumulator high 32 bits. */
+ POP R15
+ MVTC R15,FPSW /* Floating point status word. */
+ POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */
+ RTE /* This pops the remaining registers. */
NOP
- NOP
+ NOP
}
/*-----------------------------------------------------------*/
#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
void vTickISR( void )
{
- /* Increment the tick, and perform any processing the new tick value
- * necessitates. */
- set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
-
- set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. */
+ set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ set_ipl( configKERNEL_INTERRUPT_PRIORITY );
}
/*-----------------------------------------------------------*/
void vSoftwareInterruptISR( void )
{
- prvYieldHandler();
+ prvYieldHandler();
}
/*-----------------------------------------------------------*/
#pragma inline_asm prvYieldHandler
static void prvYieldHandler( void )
{
- /* Re-enable interrupts. */
- SETPSW I
+ /* Re-enable interrupts. */
+ SETPSW I
- /* Move the data that was automatically pushed onto the interrupt stack when
- * the interrupt occurred from the interrupt stack to the user stack.
- *
- * R15 is saved before it is clobbered. */
- PUSH.L R15
+ /* Move the data that was automatically pushed onto the interrupt stack when
+ the interrupt occurred from the interrupt stack to the user stack.
- /* Read the user stack pointer. */
- MVFC USP, R15
+ R15 is saved before it is clobbered. */
+ PUSH.L R15
- /* Move the address down to the data being moved. */
- SUB # 12, R15
- MVTC R15, USP
+ /* Read the user stack pointer. */
+ MVFC USP, R15
- /* Copy the data across. */
- MOV.L[ R0 ], [ R15 ];
- R15
+ /* Move the address down to the data being moved. */
+ SUB #12, R15
+ MVTC R15, USP
- MOV.L 4[ R0 ], 4[ R15 ];
- PC
- MOV.L 8[ R0 ], 8[ R15 ];
- PSW
+ /* Copy the data across. */
+ MOV.L [ R0 ], [ R15 ] ; R15
+ MOV.L 4[ R0 ], 4[ R15 ] ; PC
+ MOV.L 8[ R0 ], 8[ R15 ] ; PSW
- /* Move the interrupt stack pointer to its new correct position. */
- ADD # 12, R0
+ /* Move the interrupt stack pointer to its new correct position. */
+ ADD #12, R0
- /* All the rest of the registers are saved directly to the user stack. */
- SETPSW U
+ /* All the rest of the registers are saved directly to the user stack. */
+ SETPSW U
- /* Save the rest of the general registers (R15 has been saved already). */
- PUSHM R1 - R14
+ /* Save the rest of the general registers (R15 has been saved already). */
+ PUSHM R1-R14
- /* Save the FPSW and accumulator. */
- MVFC FPSW, R15
- PUSH.L R15
- MVFACHI R15
- PUSH.L R15
- MVFACMI R15;
- Middle order word.
- SHLL # 16, R15;
- Shifted left as it is restored to the low order word.
- PUSH.L R15
+ /* Save the FPSW and accumulator. */
+ MVFC FPSW, R15
+ PUSH.L R15
+ MVFACHI R15
+ PUSH.L R15
+ MVFACMI R15 ; Middle order word.
+ SHLL #16, R15 ; Shifted left as it is restored to the low order word.
+ PUSH.L R15
- /* Save the stack pointer to the TCB. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L R0, [ R15 ]
+ /* Save the stack pointer to the TCB. */
+ MOV.L #_pxCurrentTCB, R15
+ MOV.L [ R15 ], R15
+ MOV.L R0, [ R15 ]
- /* Ensure the interrupt mask is set to the syscall priority while the kernel
- * structures are being accessed. */
- MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel
+ structures are being accessed. */
+ MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
- /* Select the next task to run. */
- BSR.A _vTaskSwitchContext
+ /* Select the next task to run. */
+ BSR.A _vTaskSwitchContext
- /* Reset the interrupt mask as no more data structure access is required. */
- MVTIPL # configKERNEL_INTERRUPT_PRIORITY
+ /* Reset the interrupt mask as no more data structure access is required. */
+ MVTIPL #configKERNEL_INTERRUPT_PRIORITY
- /* Load the stack pointer of the task that is now selected as the Running
- * state task from its TCB. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L[ R15 ], R0
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ MOV.L #_pxCurrentTCB,R15
+ MOV.L [ R15 ], R15
+ MOV.L [ R15 ], R0
- /* Restore the context of the new task. The PSW (Program Status Word) and
- * PC will be popped by the RTE instruction. */
- POP R15
- MVTACLO R15
- POP R15
- MVTACHI R15
- POP R15
- MVTC R15, FPSW
- POPM R1 - R15
- RTE
- NOP
- NOP
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ POP R15
+ MVTACLO R15
+ POP R15
+ MVTACHI R15
+ POP R15
+ MVTC R15,FPSW
+ POPM R1-R15
+ RTE
+ NOP
+ NOP
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
- /* The following line is just to prevent the symbol getting optimised away. */
- ( void ) vTaskSwitchContext();
+ /* The following line is just to prevent the symbol getting optimised away. */
+ ( void ) vTaskSwitchContext();
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/Renesas/RX600/portmacro.h b/portable/Renesas/RX600/portmacro.h
index 94575e6..ab0d603 100644
--- a/portable/Renesas/RX600/portmacro.h
+++ b/portable/Renesas/RX600/portmacro.h
@@ -27,14 +27,14 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Hardware specifics. */
- #include "machine.h"
+#include "machine.h"
/*-----------------------------------------------------------
* Port specific definitions.
@@ -47,95 +47,96 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() nop()
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() nop()
- #pragma inline_asm vPortYield
- static void vPortYield( void )
- {
- /* Save clobbered register - may not actually be necessary if inline asm
- * functions are considered to use the same rules as function calls by the
- * compiler. */
- PUSH.L R5
- /* Set ITU SWINTR. */
- MOV.L # 553696, R5
- MOV.B # 1, [ R5 ]
- /* Read back to ensure the value is taken before proceeding. */
- MOV.L[ R5 ], R5
- /* Restore clobbered register to its previous value. */
- POP R5
- }
- #define portYIELD() vPortYield()
- #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+ /* Save clobbered register - may not actually be necessary if inline asm
+ functions are considered to use the same rules as function calls by the
+ compiler. */
+ PUSH.L R5
+ /* Set ITU SWINTR. */
+ MOV.L #553696, R5
+ MOV.B #1, [R5]
+ /* Read back to ensure the value is taken before proceeding. */
+ MOV.L [R5], R5
+ /* Restore clobbered register to its previous value. */
+ POP R5
+}
+#define portYIELD() vPortYield()
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
- * functions are those that end in FromISR. FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
- #define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 )
- #ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #else
- #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #endif
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+ #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
- #define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/Renesas/RX600v2/port.c b/portable/Renesas/RX600v2/port.c
index eee082c..1169082 100644
--- a/portable/Renesas/RX600v2/port.c
+++ b/portable/Renesas/RX600v2/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RX600 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RX600 port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -38,23 +38,23 @@
/* Hardware specifics. */
#if defined( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H ) && ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
- #include "platform.h"
+ #include "platform.h"
#else
- #include "iodefine.h"
+ #include "iodefine.h"
#endif
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
+PSW is set with U and I set, and PM and IPL clear. */
#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
/*-----------------------------------------------------------*/
/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- * and therefore installed in the vector table, when the FreeRTOS code is built
- * as a library. */
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
extern BaseType_t vSoftwareInterruptEntry;
const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
@@ -84,8 +84,8 @@
/*-----------------------------------------------------------*/
/* This is accessed by the inline assembler functions so is file scope for
- * convenience. */
-extern void * pxCurrentTCB;
+convenience. */
+extern void *pxCurrentTCB;
extern void vTaskSwitchContext( void );
/*-----------------------------------------------------------*/
@@ -93,278 +93,272 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* R0 is not included as it is the stack pointer. */
+ /* R0 is not included as it is the stack pointer. */
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
- /* When debugging it can be useful if every register is set to a known
- * value. Otherwise code space can be saved by just setting the registers
- * that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0xffffffff; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xeeeeeeee;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
- {
- pxTopOfStack -= 15;
- }
- #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0xffffffff; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xeeeeeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= 15;
+ }
+ #endif
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_FPSW;
- pxTopOfStack--;
- *pxTopOfStack = 0x11111111; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444; /* Accumulator 1. */
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555; /* Accumulator 1. */
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666; /* Accumulator 1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_FPSW;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11111111; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444; /* Accumulator 1. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555; /* Accumulator 1. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666; /* Accumulator 1. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate the
- * tick interrupt. This way the application can decide which peripheral to
- * use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
- /* Start the first task. */
- prvStartFirstTask();
- }
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
- /* Just to make sure the function is not optimised away. */
- ( void ) vSoftwareInterruptISR();
+ /* Just to make sure the function is not optimised away. */
+ ( void ) vSoftwareInterruptISR();
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
#pragma inline_asm prvStartFirstTask
static void prvStartFirstTask( void )
{
- /* When starting the scheduler there is nothing that needs moving to the
- * interrupt stack because the function is not called from an interrupt.
- * Just ensure the current stack is the user stack. */
- SETPSW U
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ SETPSW U
- /* Obtain the location of the stack associated with which ever task
- * pxCurrentTCB is currently pointing to. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L[ R15 ], R0
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ MOV.L #_pxCurrentTCB, R15
+ MOV.L [R15], R15
+ MOV.L [R15], R0
- /* Restore the registers from the stack of the task pointed to by
- * pxCurrentTCB. */
- POP R15
- MVTACLO R15, A0 /* Accumulator low 32 bits. */
- POP R15
- MVTACHI R15, A0 /* Accumulator high 32 bits. */
- POP R15
- MVTACGU R15, A0 /* Accumulator guard. */
- POP R15
- MVTACLO R15, A1 /* Accumulator low 32 bits. */
- POP R15
- MVTACHI R15, A1 /* Accumulator high 32 bits. */
- POP R15
- MVTACGU R15, A1 /* Accumulator guard. */
- POP R15
- MVTC R15, FPSW /* Floating point status word. */
- POPM R1 - R15 /* R1 to R15 - R0 is not included as it is the SP. */
- RTE /* This pops the remaining registers. */
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ POP R15
+ MVTACLO R15, A0 /* Accumulator low 32 bits. */
+ POP R15
+ MVTACHI R15, A0 /* Accumulator high 32 bits. */
+ POP R15
+ MVTACGU R15, A0 /* Accumulator guard. */
+ POP R15
+ MVTACLO R15, A1 /* Accumulator low 32 bits. */
+ POP R15
+ MVTACHI R15, A1 /* Accumulator high 32 bits. */
+ POP R15
+ MVTACGU R15, A1 /* Accumulator guard. */
+ POP R15
+ MVTC R15,FPSW /* Floating point status word. */
+ POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */
+ RTE /* This pops the remaining registers. */
NOP
- NOP
+ NOP
}
/*-----------------------------------------------------------*/
#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
void vTickISR( void )
{
- /* Increment the tick, and perform any processing the new tick value
- * necessitates. */
- set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
-
- set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. */
+ set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ set_ipl( configKERNEL_INTERRUPT_PRIORITY );
}
/*-----------------------------------------------------------*/
void vSoftwareInterruptISR( void )
{
- prvYieldHandler();
+ prvYieldHandler();
}
/*-----------------------------------------------------------*/
#pragma inline_asm prvYieldHandler
static void prvYieldHandler( void )
{
- /* Re-enable interrupts. */
- SETPSW I
+ /* Re-enable interrupts. */
+ SETPSW I
- /* Move the data that was automatically pushed onto the interrupt stack when
- * the interrupt occurred from the interrupt stack to the user stack.
- *
- * R15 is saved before it is clobbered. */
- PUSH.L R15
+ /* Move the data that was automatically pushed onto the interrupt stack when
+ the interrupt occurred from the interrupt stack to the user stack.
- /* Read the user stack pointer. */
- MVFC USP, R15
+ R15 is saved before it is clobbered. */
+ PUSH.L R15
- /* Move the address down to the data being moved. */
- SUB # 12, R15
- MVTC R15, USP
+ /* Read the user stack pointer. */
+ MVFC USP, R15
- /* Copy the data across. */
- MOV.L[ R0 ], [ R15 ];
- R15
+ /* Move the address down to the data being moved. */
+ SUB #12, R15
+ MVTC R15, USP
- MOV.L 4[ R0 ], 4[ R15 ];
- PC
- MOV.L 8[ R0 ], 8[ R15 ];
- PSW
+ /* Copy the data across. */
+ MOV.L [ R0 ], [ R15 ] ; R15
+ MOV.L 4[ R0 ], 4[ R15 ] ; PC
+ MOV.L 8[ R0 ], 8[ R15 ] ; PSW
- /* Move the interrupt stack pointer to its new correct position. */
- ADD # 12, R0
+ /* Move the interrupt stack pointer to its new correct position. */
+ ADD #12, R0
- /* All the rest of the registers are saved directly to the user stack. */
- SETPSW U
+ /* All the rest of the registers are saved directly to the user stack. */
+ SETPSW U
- /* Save the rest of the general registers (R15 has been saved already). */
- PUSHM R1 - R14
+ /* Save the rest of the general registers (R15 has been saved already). */
+ PUSHM R1-R14
- /* Save the FPSW and accumulators. */
- MVFC FPSW, R15
- PUSH.L R15
- MVFACGU # 0, A1, R15
- PUSH.L R15
- MVFACHI # 0, A1, R15
- PUSH.L R15
- MVFACLO # 0, A1, R15;
- Low order word.
- PUSH.L R15
- MVFACGU # 0, A0, R15
- PUSH.L R15
- MVFACHI # 0, A0, R15
- PUSH.L R15
- MVFACLO # 0, A0, R15;
- Low order word.
- PUSH.L R15
+ /* Save the FPSW and accumulators. */
+ MVFC FPSW, R15
+ PUSH.L R15
+ MVFACGU #0, A1, R15
+ PUSH.L R15
+ MVFACHI #0, A1, R15
+ PUSH.L R15
+ MVFACLO #0, A1, R15 ; Low order word.
+ PUSH.L R15
+ MVFACGU #0, A0, R15
+ PUSH.L R15
+ MVFACHI #0, A0, R15
+ PUSH.L R15
+ MVFACLO #0, A0, R15 ; Low order word.
+ PUSH.L R15
- /* Save the stack pointer to the TCB. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L R0, [ R15 ]
+ /* Save the stack pointer to the TCB. */
+ MOV.L #_pxCurrentTCB, R15
+ MOV.L [ R15 ], R15
+ MOV.L R0, [ R15 ]
- /* Ensure the interrupt mask is set to the syscall priority while the kernel
- * structures are being accessed. */
- MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel
+ structures are being accessed. */
+ MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
- /* Select the next task to run. */
- BSR.A _vTaskSwitchContext
+ /* Select the next task to run. */
+ BSR.A _vTaskSwitchContext
- /* Reset the interrupt mask as no more data structure access is required. */
- MVTIPL # configKERNEL_INTERRUPT_PRIORITY
+ /* Reset the interrupt mask as no more data structure access is required. */
+ MVTIPL #configKERNEL_INTERRUPT_PRIORITY
- /* Load the stack pointer of the task that is now selected as the Running
- * state task from its TCB. */
- MOV.L # _pxCurrentTCB, R15
- MOV.L[ R15 ], R15
- MOV.L[ R15 ], R0
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ MOV.L #_pxCurrentTCB,R15
+ MOV.L [ R15 ], R15
+ MOV.L [ R15 ], R0
- /* Restore the context of the new task. The PSW (Program Status Word) and
- * PC will be popped by the RTE instruction. */
- POP R15
- MVTACLO R15, A0 /* Accumulator low 32 bits. */
- POP R15
- MVTACHI R15, A0 /* Accumulator high 32 bits. */
- POP R15
- MVTACGU R15, A0 /* Accumulator guard. */
- POP R15
- MVTACLO R15, A1 /* Accumulator low 32 bits. */
- POP R15
- MVTACHI R15, A1 /* Accumulator high 32 bits. */
- POP R15
- MVTACGU R15, A1 /* Accumulator guard. */
- POP R15
- MVTC R15, FPSW
- POPM R1 - R15
- RTE
- NOP
- NOP
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ POP R15
+ MVTACLO R15, A0 /* Accumulator low 32 bits. */
+ POP R15
+ MVTACHI R15, A0 /* Accumulator high 32 bits. */
+ POP R15
+ MVTACGU R15, A0 /* Accumulator guard. */
+ POP R15
+ MVTACLO R15, A1 /* Accumulator low 32 bits. */
+ POP R15
+ MVTACHI R15, A1 /* Accumulator high 32 bits. */
+ POP R15
+ MVTACGU R15, A1 /* Accumulator guard. */
+ POP R15
+ MVTC R15,FPSW
+ POPM R1-R15
+ RTE
+ NOP
+ NOP
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
- /* The following line is just to prevent the symbol getting optimised away. */
- ( void ) vTaskSwitchContext();
+ /* The following line is just to prevent the symbol getting optimised away. */
+ ( void ) vTaskSwitchContext();
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/Renesas/RX600v2/portmacro.h b/portable/Renesas/RX600v2/portmacro.h
index 1f87573..bf742a2 100644
--- a/portable/Renesas/RX600v2/portmacro.h
+++ b/portable/Renesas/RX600v2/portmacro.h
@@ -27,14 +27,14 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Hardware specifics. */
- #include "machine.h"
+#include "machine.h"
/*-----------------------------------------------------------
* Port specific definitions.
@@ -47,95 +47,96 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() nop()
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() nop()
- #pragma inline_asm vPortYield
- static void vPortYield( void )
- {
- /* Save clobbered register - may not actually be necessary if inline asm
- * functions are considered to use the same rules as function calls by the
- * compiler. */
- PUSH.L R5
- /* Set ITU SWINTR. */
- MOV.L # 553696, R5
- MOV.B # 1, [ R5 ]
- /* Read back to ensure the value is taken before proceeding. */
- MOV.L[ R5 ], R5
- /* Restore clobbered register to its previous value. */
- POP R5
- }
- #define portYIELD() vPortYield()
- #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+ /* Save clobbered register - may not actually be necessary if inline asm
+ functions are considered to use the same rules as function calls by the
+ compiler. */
+ PUSH.L R5
+ /* Set ITU SWINTR. */
+ MOV.L #553696, R5
+ MOV.B #1, [R5]
+ /* Read back to ensure the value is taken before proceeding. */
+ MOV.L [R5], R5
+ /* Restore clobbered register to its previous value. */
+ POP R5
+}
+#define portYIELD() vPortYield()
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
- * functions are those that end in FromISR. FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
- #define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 )
- #ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #else
- #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #endif
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+ #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
- #define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/Renesas/SH2A_FPU/port.c b/portable/Renesas/SH2A_FPU/port.c
index 01a992a..c156f2c 100644
--- a/portable/Renesas/SH2A_FPU/port.c
+++ b/portable/Renesas/SH2A_FPU/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the SH2A port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -39,18 +39,18 @@
/*-----------------------------------------------------------*/
/* The SR assigned to a newly created task. The only important thing in this
- * value is for all interrupts to be enabled. */
-#define portINITIAL_SR ( 0UL )
+value is for all interrupts to be enabled. */
+#define portINITIAL_SR ( 0UL )
/* Dimensions the array into which the floating point context is saved.
- * Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4
- * bytes big. If this number is changed then the 72 in portasm.src also needs
- * changing. */
-#define portFLOP_REGISTERS_TO_STORE ( 18 )
-#define portFLOP_STORAGE_SIZE ( portFLOP_REGISTERS_TO_STORE * 4 )
+Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4
+bytes big. If this number is changed then the 72 in portasm.src also needs
+changing. */
+#define portFLOP_REGISTERS_TO_STORE ( 18 )
+#define portFLOP_STORAGE_SIZE ( portFLOP_REGISTERS_TO_STORE * 4 )
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
- #error configSUPPORT_DYNAMIC_ALLOCATION must be 1 to use this port.
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+ #error configSUPPORT_DYNAMIC_ALLOCATION must be 1 to use this port.
#endif
/*-----------------------------------------------------------*/
@@ -75,197 +75,197 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Mark the end of the stack - used for debugging only and can be removed. */
- *pxTopOfStack = 0x11111111UL;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222UL;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333UL;
- pxTopOfStack--;
+ /* Mark the end of the stack - used for debugging only and can be removed. */
+ *pxTopOfStack = 0x11111111UL;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222UL;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333UL;
+ pxTopOfStack--;
- /* SR. */
- *pxTopOfStack = portINITIAL_SR;
- pxTopOfStack--;
+ /* SR. */
+ *pxTopOfStack = portINITIAL_SR;
+ pxTopOfStack--;
- /* PC. */
- *pxTopOfStack = ( uint32_t ) pxCode;
- pxTopOfStack--;
+ /* PC. */
+ *pxTopOfStack = ( uint32_t ) pxCode;
+ pxTopOfStack--;
- /* PR. */
- *pxTopOfStack = 15;
- pxTopOfStack--;
+ /* PR. */
+ *pxTopOfStack = 15;
+ pxTopOfStack--;
- /* 14. */
- *pxTopOfStack = 14;
- pxTopOfStack--;
+ /* 14. */
+ *pxTopOfStack = 14;
+ pxTopOfStack--;
- /* R13. */
- *pxTopOfStack = 13;
- pxTopOfStack--;
+ /* R13. */
+ *pxTopOfStack = 13;
+ pxTopOfStack--;
- /* R12. */
- *pxTopOfStack = 12;
- pxTopOfStack--;
+ /* R12. */
+ *pxTopOfStack = 12;
+ pxTopOfStack--;
- /* R11. */
- *pxTopOfStack = 11;
- pxTopOfStack--;
+ /* R11. */
+ *pxTopOfStack = 11;
+ pxTopOfStack--;
- /* R10. */
- *pxTopOfStack = 10;
- pxTopOfStack--;
+ /* R10. */
+ *pxTopOfStack = 10;
+ pxTopOfStack--;
- /* R9. */
- *pxTopOfStack = 9;
- pxTopOfStack--;
+ /* R9. */
+ *pxTopOfStack = 9;
+ pxTopOfStack--;
- /* R8. */
- *pxTopOfStack = 8;
- pxTopOfStack--;
+ /* R8. */
+ *pxTopOfStack = 8;
+ pxTopOfStack--;
- /* R7. */
- *pxTopOfStack = 7;
- pxTopOfStack--;
+ /* R7. */
+ *pxTopOfStack = 7;
+ pxTopOfStack--;
- /* R6. */
- *pxTopOfStack = 6;
- pxTopOfStack--;
+ /* R6. */
+ *pxTopOfStack = 6;
+ pxTopOfStack--;
- /* R5. */
- *pxTopOfStack = 5;
- pxTopOfStack--;
+ /* R5. */
+ *pxTopOfStack = 5;
+ pxTopOfStack--;
- /* R4. */
- *pxTopOfStack = ( uint32_t ) pvParameters;
- pxTopOfStack--;
+ /* R4. */
+ *pxTopOfStack = ( uint32_t ) pvParameters;
+ pxTopOfStack--;
- /* R3. */
- *pxTopOfStack = 3;
- pxTopOfStack--;
+ /* R3. */
+ *pxTopOfStack = 3;
+ pxTopOfStack--;
- /* R2. */
- *pxTopOfStack = 2;
- pxTopOfStack--;
+ /* R2. */
+ *pxTopOfStack = 2;
+ pxTopOfStack--;
- /* R1. */
- *pxTopOfStack = 1;
- pxTopOfStack--;
+ /* R1. */
+ *pxTopOfStack = 1;
+ pxTopOfStack--;
- /* R0 */
- *pxTopOfStack = 0;
- pxTopOfStack--;
+ /* R0 */
+ *pxTopOfStack = 0;
+ pxTopOfStack--;
- /* MACL. */
- *pxTopOfStack = 16;
- pxTopOfStack--;
+ /* MACL. */
+ *pxTopOfStack = 16;
+ pxTopOfStack--;
- /* MACH. */
- *pxTopOfStack = 17;
- pxTopOfStack--;
+ /* MACH. */
+ *pxTopOfStack = 17;
+ pxTopOfStack--;
- /* GBR. */
- *pxTopOfStack = ulPortGetGBR();
+ /* GBR. */
+ *pxTopOfStack = ulPortGetGBR();
- /* GBR = global base register.
- * VBR = vector base register.
- * TBR = jump table base register.
- * R15 is the stack pointer. */
+ /* GBR = global base register.
+ VBR = vector base register.
+ TBR = jump table base register.
+ R15 is the stack pointer. */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
- /* Call an application function to set up the timer that will generate the
- * tick interrupt. This way the application can decide which peripheral to
- * use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
- /* Start the first task. This will only restore the standard registers and
- * not the flop registers. This does not really matter though because the only
- * flop register that is initialised to a particular value is fpscr, and it is
- * only initialised to the current value, which will still be the current value
- * when the first task starts executing. */
- trapa( portSTART_SCHEDULER_TRAP_NO );
+ /* Start the first task. This will only restore the standard registers and
+ not the flop registers. This does not really matter though because the only
+ flop register that is initialised to a particular value is fpscr, and it is
+ only initialised to the current value, which will still be the current value
+ when the first task starts executing. */
+ trapa( portSTART_SCHEDULER_TRAP_NO );
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented as there is nothing to return to. */
+ /* Not implemented as there is nothing to return to. */
}
/*-----------------------------------------------------------*/
void vPortYield( void )
{
- int32_t lInterruptMask;
+int32_t lInterruptMask;
- /* Ensure the yield trap runs at the same priority as the other interrupts
- * that can cause a context switch. */
- lInterruptMask = get_imask();
+ /* Ensure the yield trap runs at the same priority as the other interrupts
+ that can cause a context switch. */
+ lInterruptMask = get_imask();
- /* taskYIELD() can only be called from a task, not an interrupt, so the
- * current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and
- * the mask can be set without risk of accidentally lowering the mask value. */
- set_imask( portKERNEL_INTERRUPT_PRIORITY );
+ /* taskYIELD() can only be called from a task, not an interrupt, so the
+ current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and
+ the mask can be set without risk of accidentally lowering the mask value. */
+ set_imask( portKERNEL_INTERRUPT_PRIORITY );
- trapa( portYIELD_TRAP_NO );
+ trapa( portYIELD_TRAP_NO );
- /* Restore the interrupt mask to whatever it was previously (when the
- * function was entered). */
- set_imask( ( int ) lInterruptMask );
+ /* Restore the interrupt mask to whatever it was previously (when the
+ function was entered). */
+ set_imask( ( int ) lInterruptMask );
}
/*-----------------------------------------------------------*/
BaseType_t xPortUsesFloatingPoint( TaskHandle_t xTask )
{
- uint32_t * pulFlopBuffer;
- BaseType_t xReturn;
- extern void * volatile pxCurrentTCB;
+uint32_t *pulFlopBuffer;
+BaseType_t xReturn;
+extern void * volatile pxCurrentTCB;
- /* This function tells the kernel that the task referenced by xTask is
- * going to use the floating point registers and therefore requires the
- * floating point registers saved as part of its context. */
+ /* This function tells the kernel that the task referenced by xTask is
+ going to use the floating point registers and therefore requires the
+ floating point registers saved as part of its context. */
- /* Passing NULL as xTask is used to indicate that the calling task is the
- * subject task - so pxCurrentTCB is the task handle. */
- if( xTask == NULL )
- {
- xTask = ( TaskHandle_t ) pxCurrentTCB;
- }
+ /* Passing NULL as xTask is used to indicate that the calling task is the
+ subject task - so pxCurrentTCB is the task handle. */
+ if( xTask == NULL )
+ {
+ xTask = ( TaskHandle_t ) pxCurrentTCB;
+ }
- /* Allocate a buffer large enough to hold all the flop registers. */
- pulFlopBuffer = ( uint32_t * ) pvPortMalloc( portFLOP_STORAGE_SIZE );
+ /* Allocate a buffer large enough to hold all the flop registers. */
+ pulFlopBuffer = ( uint32_t * ) pvPortMalloc( portFLOP_STORAGE_SIZE );
- if( pulFlopBuffer != NULL )
- {
- /* Start with the registers in a benign state. */
- memset( ( void * ) pulFlopBuffer, 0x00, portFLOP_STORAGE_SIZE );
+ if( pulFlopBuffer != NULL )
+ {
+ /* Start with the registers in a benign state. */
+ memset( ( void * ) pulFlopBuffer, 0x00, portFLOP_STORAGE_SIZE );
- /* The first thing to get saved in the buffer is the FPSCR value -
- * initialise this to the current FPSCR value. */
- *pulFlopBuffer = get_fpscr();
+ /* The first thing to get saved in the buffer is the FPSCR value -
+ initialise this to the current FPSCR value. */
+ *pulFlopBuffer = get_fpscr();
- /* Use the task tag to point to the flop buffer. Pass pointer to just
- * above the buffer because the flop save routine uses a pre-decrement. */
- vTaskSetApplicationTaskTag( xTask, ( void * ) ( pulFlopBuffer + portFLOP_REGISTERS_TO_STORE ) );
- xReturn = pdPASS;
- }
- else
- {
- xReturn = pdFAIL;
- }
+ /* Use the task tag to point to the flop buffer. Pass pointer to just
+ above the buffer because the flop save routine uses a pre-decrement. */
+ vTaskSetApplicationTaskTag( xTask, ( void * ) ( pulFlopBuffer + portFLOP_REGISTERS_TO_STORE ) );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
- return xReturn;
+ return xReturn;
}
/*-----------------------------------------------------------*/
+
+
diff --git a/portable/Renesas/SH2A_FPU/portmacro.h b/portable/Renesas/SH2A_FPU/portmacro.h
index c88b066..f0b803c 100644
--- a/portable/Renesas/SH2A_FPU/portmacro.h
+++ b/portable/Renesas/SH2A_FPU/portmacro.h
@@ -27,13 +27,13 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include <machine.h>
+#include <machine.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -46,93 +46,94 @@
*/
/* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8
- #define portSTACK_GROWTH -1
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portNOP() nop()
- #define portSTART_SCHEDULER_TRAP_NO ( 32 )
- #define portYIELD_TRAP_NO ( 33 )
- #define portKERNEL_INTERRUPT_PRIORITY ( 1 )
+#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() nop()
+#define portSTART_SCHEDULER_TRAP_NO ( 32 )
+#define portYIELD_TRAP_NO ( 33 )
+#define portKERNEL_INTERRUPT_PRIORITY ( 1 )
- void vPortYield( void );
- #define portYIELD() vPortYield()
+void vPortYield( void );
+#define portYIELD() vPortYield()
- extern void vTaskSwitchContext( void );
- #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) vTaskSwitchContext()
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) vTaskSwitchContext()
/*
* This function tells the kernel that the task referenced by xTask is going to
* use the floating point registers and therefore requires the floating point
* registers saved as part of its context.
*/
- BaseType_t xPortUsesFloatingPoint( void * xTask );
+BaseType_t xPortUsesFloatingPoint( void* xTask );
/*
* The flop save and restore functions are defined in portasm.src and called by
* the trace "task switched in" and "trace task switched out" macros.
*/
- void vPortSaveFlopRegisters( void * pulBuffer );
- void vPortRestoreFlopRegisters( void * pulBuffer );
+void vPortSaveFlopRegisters( void *pulBuffer );
+void vPortRestoreFlopRegisters( void *pulBuffer );
/*
* pxTaskTag is used to point to the buffer into which the floating point
* context should be saved. If pxTaskTag is NULL then the task does not use
* a floating point context.
*/
- #define traceTASK_SWITCHED_OUT() if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag )
- #define traceTASK_SWITCHED_IN() if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag )
+#define traceTASK_SWITCHED_OUT() if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag )
+#define traceTASK_SWITCHED_IN() if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag )
/*
* These macros should be called directly, but through the taskENTER_CRITICAL()
* and taskEXIT_CRITICAL() macros.
*/
- #define portENABLE_INTERRUPTS() set_imask( 0x00 )
- #define portDISABLE_INTERRUPTS() set_imask( portKERNEL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS() set_imask( 0x00 )
+#define portDISABLE_INTERRUPTS() set_imask( portKERNEL_INTERRUPT_PRIORITY )
/* Critical nesting counts are stored in the TCB. */
- #define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
- extern void vTaskEnterCritical( void );
- extern void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical();
- #define portEXIT_CRITICAL() vTaskExitCritical();
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical();
+#define portEXIT_CRITICAL() vTaskExitCritical();
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/Rowley/MSP430F449/port.c b/portable/Rowley/MSP430F449/port.c
index 241dad9..798e2a1 100644
--- a/portable/Rowley/MSP430F449/port.c
+++ b/portable/Rowley/MSP430F449/port.c
@@ -30,28 +30,28 @@
#include "task.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the MSP430 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
-/* Constants required for hardware setup. The tick ISR runs off the ACLK,
- * not the MCLK. */
-#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
+/* Constants required for hardware setup. The tick ISR runs off the ACLK,
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
-/* Each task maintains a count of the critical section nesting depth. Each
- * time a critical section is entered the count is incremented. Each time a
- * critical section is exited the count is decremented - with interrupts only
- * being re-enabled if the count is zero.
- *
- * usCriticalNesting will get set to zero when the scheduler starts, but must
- * not be initialised to zero as this will cause problems during the startup
- * sequence. */
+/* Each task maintains a count of the critical section nesting depth. Each
+time a critical section is entered the count is incremented. Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
@@ -63,109 +63,110 @@
void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
-/*
- * Initialise the stack of a task to look exactly as if a call to
+/*
+ * Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
- *
+ *
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /*
- * Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging and can be included if required.
- *
- * pxTopOfStack = ( StackType_t ) 0x1111;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x2222;
- * pxTopOfStack--;
- * pxTopOfStack = ( StackType_t ) 0x3333;
- * pxTopOfStack--;
- */
+ /*
+ Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging and can be included if required.
- /* The msp430 automatically pushes the PC then SR onto the stack before
- * executing an ISR. We want the stack to look just as if this has happened
- * so place a pointer to the start of the task on the stack first - followed
- * by the flags we want the task to use when it starts up. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
- *pxTopOfStack = portFLAGS_INT_ENABLED;
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x3333;
+ pxTopOfStack--;
+ */
- /* Next the general purpose registers. */
- *pxTopOfStack = ( StackType_t ) 0x4444;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x5555;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x6666;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x7777;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x8888;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x9999;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaa;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xbbbb;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xcccc;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xdddd;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xeeee;
- pxTopOfStack--;
+ /* The msp430 automatically pushes the PC then SR onto the stack before
+ executing an ISR. We want the stack to look just as if this has happened
+ so place a pointer to the start of the task on the stack first - followed
+ by the flags we want the task to use when it starts up. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+ *pxTopOfStack = portFLAGS_INT_ENABLED;
+ pxTopOfStack--;
- /* When the task starts is will expect to find the function parameter in
- * R15. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
+ /* Next the general purpose registers. */
+ *pxTopOfStack = ( StackType_t ) 0x4444;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x5555;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x6666;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x7777;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x8888;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x9999;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xcccc;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xdddd;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xeeee;
+ pxTopOfStack--;
- /* A variable is used to keep track of the critical section nesting.
- * This variable has to be stored as part of the task context and is
- * initially set to zero. */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+ /* When the task starts is will expect to find the function parameter in
+ R15. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
- /* Return a pointer to the top of the stack we have generated so this can
- * be stored in the task control block for the task. */
- return pxTopOfStack;
+ /* A variable is used to keep track of the critical section nesting.
+ This variable has to be stored as part of the task context and is
+ initially set to zero. */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+ /* Return a pointer to the top of the stack we have generated so this can
+ be stored in the task control block for the task. */
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the MSP430 port will get stopped. If required simply
- * disable the tick interrupt here. */
+ /* It is unlikely that the MSP430 port will get stopped. If required simply
+ disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
/*
* Hardware initialisation to generate the RTOS tick. This uses timer 0
- * but could alternatively use the watchdog timer or timer 1.
+ * but could alternatively use the watchdog timer or timer 1.
*/
void prvSetupTimerInterrupt( void )
{
- /* Ensure the timer is stopped. */
- TACTL = 0;
+ /* Ensure the timer is stopped. */
+ TACTL = 0;
- /* Run the timer of the ACLK. */
- TACTL = TASSEL_1;
+ /* Run the timer of the ACLK. */
+ TACTL = TASSEL_1;
- /* Clear everything to start with. */
- TACTL |= TACLR;
+ /* Clear everything to start with. */
+ TACTL |= TACLR;
- /* Set the compare match value according to the tick rate we want. */
- TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+ /* Set the compare match value according to the tick rate we want. */
+ TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
- /* Enable the interrupts. */
- TACCTL0 = CCIE;
+ /* Enable the interrupts. */
+ TACCTL0 = CCIE;
- /* Start up clean. */
- TACTL |= TACLR;
+ /* Start up clean. */
+ TACTL |= TACLR;
- /* Up mode. */
- TACTL |= MC_1;
+ /* Up mode. */
+ TACTL |= MC_1;
}
/*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/Rowley/MSP430F449/portasm.h b/portable/Rowley/MSP430F449/portasm.h
index 21443bd..0fd15cd 100644
--- a/portable/Rowley/MSP430F449/portasm.h
+++ b/portable/Rowley/MSP430F449/portasm.h
@@ -29,51 +29,52 @@
#define PORT_ASM_H
portSAVE_CONTEXT macro
-/* Save the remaining registers. */
-push r4
-push r5
-push r6
-push r7
-push r8
-push r9
-push r10
-push r11
-push r12
-push r13
-push r14
-push r15
-mov.w &_usCriticalNesting, r14
-push r14
- mov.w &_pxCurrentTCB, r12
- mov.w r1, @r12
-endm
+ /* Save the remaining registers. */
+ push r4
+ push r5
+ push r6
+ push r7
+ push r8
+ push r9
+ push r10
+ push r11
+ push r12
+ push r13
+ push r14
+ push r15
+ mov.w &_usCriticalNesting, r14
+ push r14
+ mov.w &_pxCurrentTCB, r12
+ mov.w r1, @r12
+ endm
/*-----------------------------------------------------------*/
-
+
portRESTORE_CONTEXT macro
- mov.w &_pxCurrentTCB, r12
- mov.w @r12, r1
-pop r15
- mov.w r15, &_usCriticalNesting
-pop r15
-pop r14
-pop r13
-pop r12
-pop r11
-pop r10
-pop r9
-pop r8
-pop r7
-pop r6
-pop r5
-pop r4
+ mov.w &_pxCurrentTCB, r12
+ mov.w @r12, r1
+ pop r15
+ mov.w r15, &_usCriticalNesting
+ pop r15
+ pop r14
+ pop r13
+ pop r12
+ pop r11
+ pop r10
+ pop r9
+ pop r8
+ pop r7
+ pop r6
+ pop r5
+ pop r4
-/* The last thing on the stack will be the status register.
- * Ensure the power down bits are clear ready for the next
- * time this power down register is popped from the stack. */
- bic.w # 0xf0, 0 ( SP )
+ /* The last thing on the stack will be the status register.
+ Ensure the power down bits are clear ready for the next
+ time this power down register is popped from the stack. */
+ bic.w #0xf0,0(SP)
-reti
-endm
+ reti
+ endm
/*-----------------------------------------------------------*/
-#endif /* ifndef PORT_ASM_H */
+#endif
+
diff --git a/portable/Rowley/MSP430F449/portmacro.h b/portable/Rowley/MSP430F449/portmacro.h
index 9bd65aa..42f1d86 100644
--- a/portable/Rowley/MSP430F449/portmacro.h
+++ b/portable/Rowley/MSP430F449/portmacro.h
@@ -39,66 +39,66 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint16_t
-#define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() _DINT(); _NOP()
-#define portENABLE_INTERRUPTS() _EINT();
+#define portDISABLE_INTERRUPTS() _DINT(); _NOP()
+#define portENABLE_INTERRUPTS() _EINT();
/*-----------------------------------------------------------*/
/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
-#define portENTER_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled usCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
- }
+#define portENTER_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled usCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
-#define portEXIT_CRITICAL() \
- { \
- extern volatile uint16_t usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
- }
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
/*-----------------------------------------------------------*/
/* Task utilities. */
@@ -107,25 +107,26 @@
* Manual context switch called by portYIELD or taskYIELD.
*/
extern void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD() vPortYield()
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 2
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portNOP()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) __toplevel
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel
#if configINTERRUPT_EXAMPLE_METHOD == 2
- extern void vTaskSwitchContext( void );
- #define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/SDCC/Cygnal/port.c b/portable/SDCC/Cygnal/port.c
index 786540b..d53e473 100644
--- a/portable/SDCC/Cygnal/port.c
+++ b/portable/SDCC/Cygnal/port.c
@@ -26,8 +26,8 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Cygnal port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Cygnal port.
+ *----------------------------------------------------------*/
/* Standard includes. */
#include <string.h>
@@ -37,292 +37,289 @@
#include "task.h"
/* Constants required to setup timer 2 to produce the RTOS tick. */
-#define portCLOCK_DIVISOR ( ( uint32_t ) 12 )
-#define portMAX_TIMER_VALUE ( ( uint32_t ) 0xffff )
-#define portENABLE_TIMER ( ( uint8_t ) 0x04 )
-#define portTIMER_2_INTERRUPT_ENABLE ( ( uint8_t ) 0x20 )
+#define portCLOCK_DIVISOR ( ( uint32_t ) 12 )
+#define portMAX_TIMER_VALUE ( ( uint32_t ) 0xffff )
+#define portENABLE_TIMER ( ( uint8_t ) 0x04 )
+#define portTIMER_2_INTERRUPT_ENABLE ( ( uint8_t ) 0x20 )
/* The value used in the IE register when a task first starts. */
-#define portGLOBAL_INTERRUPT_BIT ( ( StackType_t ) 0x80 )
+#define portGLOBAL_INTERRUPT_BIT ( ( StackType_t ) 0x80 )
/* The value used in the PSW register when a task first starts. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00 )
+#define portINITIAL_PSW ( ( StackType_t ) 0x00 )
/* Macro to clear the timer 2 interrupt flag. */
-#define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80;
+#define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80;
/* Used during a context switch to store the size of the stack being copied
- * to or from XRAM. */
+to or from XRAM. */
data static uint8_t ucStackBytes;
/* Used during a context switch to point to the next byte in XRAM from/to which
- * a RAM byte is to be copied. */
+a RAM byte is to be copied. */
xdata static StackType_t * data pxXRAMStack;
/* Used during a context switch to point to the next byte in RAM from/to which
- * an XRAM byte is to be copied. */
+an XRAM byte is to be copied. */
data static StackType_t * data pxRAMStack;
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/*
- * Setup the hardware to generate an interrupt off timer 2 at the required
+ * Setup the hardware to generate an interrupt off timer 2 at the required
* frequency.
*/
static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
-
/*
- * Macro that copies the current stack from internal RAM to XRAM. This is
- * required as the 8051 only contains enough internal RAM for a single stack,
+ * Macro that copies the current stack from internal RAM to XRAM. This is
+ * required as the 8051 only contains enough internal RAM for a single stack,
* but we have a stack for every task.
*/
-#define portCOPY_STACK_TO_XRAM() \
- { \
- /* pxCurrentTCB points to a TCB which itself points to the location into \
- * which the first stack byte should be copied. Set pxXRAMStack to point \
- * to the location into which the first stack byte is to be copied. */ \
- pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
- \
- /* Set pxRAMStack to point to the first byte to be coped from the stack. */ \
- pxRAMStack = ( data StackType_t * data ) configSTACK_START; \
- \
- /* Calculate the size of the stack we are about to copy from the current \
- * stack pointer value. */ \
- ucStackBytes = SP - ( configSTACK_START - 1 ); \
- \
- /* Before starting to copy the stack, store the calculated stack size so \
- * the stack can be restored when the task is resumed. */\
- * pxXRAMStack = ucStackBytes; \
- \
- /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \
- * have already stored the stack size into XRAM. */\
- while( ucStackBytes ) \
- { \
- pxXRAMStack ++; \
- * pxXRAMStack = * pxRAMStack; \
- pxRAMStack ++; \
- ucStackBytes --; \
- } \
- }
-/*-----------------------------------------------------------*/
-
-/*
- * Macro that copies the stack of the task being resumed from XRAM into
- * internal RAM.
- */
-#define portCOPY_XRAM_TO_STACK() \
- { \
- /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \
- * copy the data back out of XRAM and into the stack. */ \
- pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
- pxRAMStack = ( data StackType_t * data )( configSTACK_START - 1 ); \
- \
- /* The first value stored in XRAM was the size of the stack - i.e. the \
- * number of bytes we need to copy back. */ \
- ucStackBytes = pxXRAMStack[ 0 ]; \
- \
- /* Copy the required number of bytes back into the stack. */ \
- do \
- { \
- pxXRAMStack ++; \
- pxRAMStack ++; \
- * pxRAMStack = * pxXRAMStack; \
- ucStackBytes --; \
- } while( ucStackBytes ); \
- \
- /* Restore the stack pointer ready to use the restored stack. */ \
- SP = ( uint8_t ) pxRAMStack; \
- }
-/*-----------------------------------------------------------*/
-
-/*
- * Macro to push the current execution context onto the stack, before the stack
- * is moved to XRAM.
- */
-#define portSAVE_CONTEXT() \
- { \
- _asm \
- /* Push ACC first, as when restoring the context it must be restored \
- * last (it is used to set the IE register). */ \
- push ACC \
- /* Store the IE register then disable interrupts. */ \
- push IE \
- clr _EA \
- push DPL \
- push DPH \
- push b \
- push ar2 \
- push ar3 \
- push ar4 \
- push ar5 \
- push ar6 \
- push ar7 \
- push ar0 \
- push ar1 \
- push PSW \
- _endasm; \
- PSW = 0; \
- _asm \
- push _bp \
- _endasm; \
- }
-/*-----------------------------------------------------------*/
-
-/*
- * Macro that restores the execution context from the stack. The execution
- * context was saved into the stack before the stack was copied into XRAM.
- */
-#define portRESTORE_CONTEXT() \
- { \
- _asm \
- pop _bp \
- pop PSW \
- pop ar1 \
- pop ar0 \
- pop ar7 \
- pop ar6 \
- pop ar5 \
- pop ar4 \
- pop ar3 \
- pop ar2 \
- pop b \
- pop DPH \
- pop DPL \
- /* The next byte of the stack is the IE register. Only the global \
- * enable bit forms part of the task context. Pop off the IE then set \
- * the global enable bit to match that of the stored IE register. */\
- pop ACC \
- JB ACC .7, 00 98$ \
- CLR IE .7 \
- LJMP 00 99$ \
- 00 98$ : \
- SETB IE .7 \
- 00 99$ : \
- /* Finally pop off the ACC, which was the first register saved. */ \
- pop ACC \
- reti \
- _endasm; \
- }
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
-{
- uint32_t ulAddress;
- StackType_t * pxStartOfStack;
-
- /* Leave space to write the size of the stack as the first byte. */
- pxStartOfStack = pxTopOfStack;
- pxTopOfStack++;
-
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging and can be uncommented if required.
- * pxTopOfStack = 0x11;
- * pxTopOfStack++;
- * pxTopOfStack = 0x22;
- * pxTopOfStack++;
- * pxTopOfStack = 0x33;
- * pxTopOfStack++;
- */
-
- /* Simulate how the stack would look after a call to the scheduler tick
- * ISR.
- *
- * The return address that would have been pushed by the MCU. */
- ulAddress = ( uint32_t ) pxCode;
- *pxTopOfStack = ( StackType_t ) ulAddress;
- ulAddress >>= 8;
- pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) ( ulAddress );
- pxTopOfStack++;
-
- /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
- *pxTopOfStack = 0xaa; /* acc */
- pxTopOfStack++;
-
- /* We want tasks to start with interrupts enabled. */
- *pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
- pxTopOfStack++;
-
- /* The function parameters will be passed in the DPTR and B register as
- * a three byte generic pointer is used. */
- ulAddress = ( uint32_t ) pvParameters;
- *pxTopOfStack = ( StackType_t ) ulAddress; /* DPL */
- ulAddress >>= 8;
- *pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) ulAddress; /* DPH */
- ulAddress >>= 8;
- pxTopOfStack++;
- *pxTopOfStack = ( StackType_t ) ulAddress; /* b */
- pxTopOfStack++;
-
- /* The remaining registers are straight forward. */
- *pxTopOfStack = 0x02; /* R2 */
- pxTopOfStack++;
- *pxTopOfStack = 0x03; /* R3 */
- pxTopOfStack++;
- *pxTopOfStack = 0x04; /* R4 */
- pxTopOfStack++;
- *pxTopOfStack = 0x05; /* R5 */
- pxTopOfStack++;
- *pxTopOfStack = 0x06; /* R6 */
- pxTopOfStack++;
- *pxTopOfStack = 0x07; /* R7 */
- pxTopOfStack++;
- *pxTopOfStack = 0x00; /* R0 */
- pxTopOfStack++;
- *pxTopOfStack = 0x01; /* R1 */
- pxTopOfStack++;
- *pxTopOfStack = 0x00; /* PSW */
- pxTopOfStack++;
- *pxTopOfStack = 0xbb; /* BP */
-
- /* Dont increment the stack size here as we don't want to include
- * the stack size byte as part of the stack size count.
- *
- * Finally we place the stack size at the beginning. */
- *pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
-
- /* Unlike most ports, we return the start of the stack as this is where the
- * size of the stack is stored. */
- return pxStartOfStack;
+#define portCOPY_STACK_TO_XRAM() \
+{ \
+ /* pxCurrentTCB points to a TCB which itself points to the location into \
+ which the first stack byte should be copied. Set pxXRAMStack to point \
+ to the location into which the first stack byte is to be copied. */ \
+ pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
+ \
+ /* Set pxRAMStack to point to the first byte to be coped from the stack. */ \
+ pxRAMStack = ( data StackType_t * data ) configSTACK_START; \
+ \
+ /* Calculate the size of the stack we are about to copy from the current \
+ stack pointer value. */ \
+ ucStackBytes = SP - ( configSTACK_START - 1 ); \
+ \
+ /* Before starting to copy the stack, store the calculated stack size so \
+ the stack can be restored when the task is resumed. */ \
+ *pxXRAMStack = ucStackBytes; \
+ \
+ /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \
+ have already stored the stack size into XRAM. */ \
+ while( ucStackBytes ) \
+ { \
+ pxXRAMStack++; \
+ *pxXRAMStack = *pxRAMStack; \
+ pxRAMStack++; \
+ ucStackBytes--; \
+ } \
}
/*-----------------------------------------------------------*/
/*
- * See header file for description.
+ * Macro that copies the stack of the task being resumed from XRAM into
+ * internal RAM.
+ */
+#define portCOPY_XRAM_TO_STACK() \
+{ \
+ /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \
+ copy the data back out of XRAM and into the stack. */ \
+ pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
+ pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 ); \
+ \
+ /* The first value stored in XRAM was the size of the stack - i.e. the \
+ number of bytes we need to copy back. */ \
+ ucStackBytes = pxXRAMStack[ 0 ]; \
+ \
+ /* Copy the required number of bytes back into the stack. */ \
+ do \
+ { \
+ pxXRAMStack++; \
+ pxRAMStack++; \
+ *pxRAMStack = *pxXRAMStack; \
+ ucStackBytes--; \
+ } while( ucStackBytes ); \
+ \
+ /* Restore the stack pointer ready to use the restored stack. */ \
+ SP = ( uint8_t ) pxRAMStack; \
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to push the current execution context onto the stack, before the stack
+ * is moved to XRAM.
+ */
+#define portSAVE_CONTEXT() \
+{ \
+ _asm \
+ /* Push ACC first, as when restoring the context it must be restored \
+ last (it is used to set the IE register). */ \
+ push ACC \
+ /* Store the IE register then disable interrupts. */ \
+ push IE \
+ clr _EA \
+ push DPL \
+ push DPH \
+ push b \
+ push ar2 \
+ push ar3 \
+ push ar4 \
+ push ar5 \
+ push ar6 \
+ push ar7 \
+ push ar0 \
+ push ar1 \
+ push PSW \
+ _endasm; \
+ PSW = 0; \
+ _asm \
+ push _bp \
+ _endasm; \
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro that restores the execution context from the stack. The execution
+ * context was saved into the stack before the stack was copied into XRAM.
+ */
+#define portRESTORE_CONTEXT() \
+{ \
+ _asm \
+ pop _bp \
+ pop PSW \
+ pop ar1 \
+ pop ar0 \
+ pop ar7 \
+ pop ar6 \
+ pop ar5 \
+ pop ar4 \
+ pop ar3 \
+ pop ar2 \
+ pop b \
+ pop DPH \
+ pop DPL \
+ /* The next byte of the stack is the IE register. Only the global \
+ enable bit forms part of the task context. Pop off the IE then set \
+ the global enable bit to match that of the stored IE register. */ \
+ pop ACC \
+ JB ACC.7,0098$ \
+ CLR IE.7 \
+ LJMP 0099$ \
+ 0098$: \
+ SETB IE.7 \
+ 0099$: \
+ /* Finally pop off the ACC, which was the first register saved. */ \
+ pop ACC \
+ reti \
+ _endasm; \
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulAddress;
+StackType_t *pxStartOfStack;
+
+ /* Leave space to write the size of the stack as the first byte. */
+ pxStartOfStack = pxTopOfStack;
+ pxTopOfStack++;
+
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging and can be uncommented if required.
+ *pxTopOfStack = 0x11;
+ pxTopOfStack++;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack++;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack++;
+ */
+
+ /* Simulate how the stack would look after a call to the scheduler tick
+ ISR.
+
+ The return address that would have been pushed by the MCU. */
+ ulAddress = ( uint32_t ) pxCode;
+ *pxTopOfStack = ( StackType_t ) ulAddress;
+ ulAddress >>= 8;
+ pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) ( ulAddress );
+ pxTopOfStack++;
+
+ /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
+ *pxTopOfStack = 0xaa; /* acc */
+ pxTopOfStack++;
+
+ /* We want tasks to start with interrupts enabled. */
+ *pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
+ pxTopOfStack++;
+
+ /* The function parameters will be passed in the DPTR and B register as
+ a three byte generic pointer is used. */
+ ulAddress = ( uint32_t ) pvParameters;
+ *pxTopOfStack = ( StackType_t ) ulAddress; /* DPL */
+ ulAddress >>= 8;
+ *pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) ulAddress; /* DPH */
+ ulAddress >>= 8;
+ pxTopOfStack++;
+ *pxTopOfStack = ( StackType_t ) ulAddress; /* b */
+ pxTopOfStack++;
+
+ /* The remaining registers are straight forward. */
+ *pxTopOfStack = 0x02; /* R2 */
+ pxTopOfStack++;
+ *pxTopOfStack = 0x03; /* R3 */
+ pxTopOfStack++;
+ *pxTopOfStack = 0x04; /* R4 */
+ pxTopOfStack++;
+ *pxTopOfStack = 0x05; /* R5 */
+ pxTopOfStack++;
+ *pxTopOfStack = 0x06; /* R6 */
+ pxTopOfStack++;
+ *pxTopOfStack = 0x07; /* R7 */
+ pxTopOfStack++;
+ *pxTopOfStack = 0x00; /* R0 */
+ pxTopOfStack++;
+ *pxTopOfStack = 0x01; /* R1 */
+ pxTopOfStack++;
+ *pxTopOfStack = 0x00; /* PSW */
+ pxTopOfStack++;
+ *pxTopOfStack = 0xbb; /* BP */
+
+ /* Dont increment the stack size here as we don't want to include
+ the stack size byte as part of the stack size count.
+
+ Finally we place the stack size at the beginning. */
+ *pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
+
+ /* Unlike most ports, we return the start of the stack as this is where the
+ size of the stack is stored. */
+ return pxStartOfStack;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup timer 2 to generate the RTOS tick. */
- prvSetupTimerInterrupt();
+ /* Setup timer 2 to generate the RTOS tick. */
+ prvSetupTimerInterrupt();
- /* Make sure we start with the expected SFR page. This line should not
- * really be required. */
- SFRPAGE = 0;
+ /* Make sure we start with the expected SFR page. This line should not
+ really be required. */
+ SFRPAGE = 0;
- /* Copy the stack for the first task to execute from XRAM into the stack,
- * restore the task context from the new stack, then start running the task. */
- portCOPY_XRAM_TO_STACK();
- portRESTORE_CONTEXT();
+ /* Copy the stack for the first task to execute from XRAM into the stack,
+ restore the task context from the new stack, then start running the task. */
+ portCOPY_XRAM_TO_STACK();
+ portRESTORE_CONTEXT();
- /* Should never get here! */
- return pdTRUE;
+ /* Should never get here! */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented for this port. */
+ /* Not implemented for this port. */
}
/*-----------------------------------------------------------*/
@@ -332,92 +329,96 @@
*/
void vPortYield( void ) _naked
{
- /* Save the execution context onto the stack, then copy the entire stack
- * to XRAM. This is necessary as the internal RAM is only large enough to
- * hold one stack, and we want one per task.
- *
- * PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
- * IS REQUIRED. */
- portSAVE_CONTEXT();
- portCOPY_STACK_TO_XRAM();
+ /* Save the execution context onto the stack, then copy the entire stack
+ to XRAM. This is necessary as the internal RAM is only large enough to
+ hold one stack, and we want one per task.
+
+ PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
+ IS REQUIRED. */
+ portSAVE_CONTEXT();
+ portCOPY_STACK_TO_XRAM();
- /* Call the standard scheduler context switch function. */
- vTaskSwitchContext();
+ /* Call the standard scheduler context switch function. */
+ vTaskSwitchContext();
- /* Copy the stack of the task about to execute from XRAM into RAM and
- * restore it's context ready to run on exiting. */
- portCOPY_XRAM_TO_STACK();
- portRESTORE_CONTEXT();
+ /* Copy the stack of the task about to execute from XRAM into RAM and
+ restore it's context ready to run on exiting. */
+ portCOPY_XRAM_TO_STACK();
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 1
- void vTimer2ISR( void ) interrupt 5 _naked
- {
- /* Preemptive context switch function triggered by the timer 2 ISR.
- * This does the same as vPortYield() (see above) with the addition
- * of incrementing the RTOS tick count. */
+ void vTimer2ISR( void ) interrupt 5 _naked
+ {
+ /* Preemptive context switch function triggered by the timer 2 ISR.
+ This does the same as vPortYield() (see above) with the addition
+ of incrementing the RTOS tick count. */
- portSAVE_CONTEXT();
- portCOPY_STACK_TO_XRAM();
+ portSAVE_CONTEXT();
+ portCOPY_STACK_TO_XRAM();
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ portCLEAR_INTERRUPT_FLAG();
+ portCOPY_XRAM_TO_STACK();
+ portRESTORE_CONTEXT();
+ }
+#else
+ void vTimer2ISR( void ) interrupt 5
+ {
+ /* When using the cooperative scheduler the timer 2 ISR is only
+ required to increment the RTOS tick count. */
- portCLEAR_INTERRUPT_FLAG();
- portCOPY_XRAM_TO_STACK();
- portRESTORE_CONTEXT();
- }
-#else /* if configUSE_PREEMPTION == 1 */
- void vTimer2ISR( void ) interrupt 5
- {
- /* When using the cooperative scheduler the timer 2 ISR is only
- * required to increment the RTOS tick count. */
-
- xTaskIncrementTick();
- portCLEAR_INTERRUPT_FLAG();
- }
-#endif /* if configUSE_PREEMPTION == 1 */
+ xTaskIncrementTick();
+ portCLEAR_INTERRUPT_FLAG();
+ }
+#endif
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
- uint8_t ucOriginalSFRPage;
+uint8_t ucOriginalSFRPage;
/* Constants calculated to give the required timer capture values. */
- const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
- const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
- const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
- const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
- const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
+const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
+const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
+const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
+const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
+const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
- /* NOTE: This uses a timer only present on 8052 architecture. */
+ /* NOTE: This uses a timer only present on 8052 architecture. */
- /* Remember the current SFR page so we can restore it at the end of the
- * function. */
- ucOriginalSFRPage = SFRPAGE;
- SFRPAGE = 0;
+ /* Remember the current SFR page so we can restore it at the end of the
+ function. */
+ ucOriginalSFRPage = SFRPAGE;
+ SFRPAGE = 0;
- /* TMR2CF can be left in its default state. */
- TMR2CF = ( uint8_t ) 0;
+ /* TMR2CF can be left in its default state. */
+ TMR2CF = ( uint8_t ) 0;
- /* Setup the overflow reload value. */
- RCAP2L = ucLowCaptureByte;
- RCAP2H = ucHighCaptureByte;
+ /* Setup the overflow reload value. */
+ RCAP2L = ucLowCaptureByte;
+ RCAP2H = ucHighCaptureByte;
- /* The initial load is performed manually. */
- TMR2L = ucLowCaptureByte;
- TMR2H = ucHighCaptureByte;
+ /* The initial load is performed manually. */
+ TMR2L = ucLowCaptureByte;
+ TMR2H = ucHighCaptureByte;
- /* Enable the timer 2 interrupts. */
- IE |= portTIMER_2_INTERRUPT_ENABLE;
+ /* Enable the timer 2 interrupts. */
+ IE |= portTIMER_2_INTERRUPT_ENABLE;
- /* Interrupts are disabled when this is called so the timer can be started
- * here. */
- TMR2CN = portENABLE_TIMER;
+ /* Interrupts are disabled when this is called so the timer can be started
+ here. */
+ TMR2CN = portENABLE_TIMER;
- /* Restore the original SFR page. */
- SFRPAGE = ucOriginalSFRPage;
+ /* Restore the original SFR page. */
+ SFRPAGE = ucOriginalSFRPage;
}
+
+
+
+
diff --git a/portable/SDCC/Cygnal/portmacro.h b/portable/SDCC/Cygnal/portmacro.h
index 2fe0a3f..978bcd2 100644
--- a/portable/SDCC/Cygnal/portmacro.h
+++ b/portable/SDCC/Cygnal/portmacro.h
@@ -29,9 +29,9 @@
#define PORTMACRO_H
#if configUSE_PREEMPTION == 0
- void vTimer2ISR( void ) interrupt 5;
+ void vTimer2ISR( void ) interrupt 5;
#else
- void vTimer2ISR( void ) interrupt 5 _naked;
+ void vTimer2ISR( void ) interrupt 5 _naked;
#endif
void vSerialISR( void ) interrupt 4;
@@ -48,69 +48,68 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE float
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint8_t
-#define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE float
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Critical section management. */
-#define portENTER_CRITICAL() \
- _asm \
- push ACC \
- push IE \
- _endasm; \
- EA = 0;
+#define portENTER_CRITICAL() _asm \
+ push ACC \
+ push IE \
+ _endasm; \
+ EA = 0;
-#define portEXIT_CRITICAL() \
- _asm \
- pop ACC \
- _endasm; \
- ACC &= 0x80; \
- IE |= ACC; \
- _asm \
- pop ACC \
- _endasm;
+#define portEXIT_CRITICAL() _asm \
+ pop ACC \
+ _endasm; \
+ ACC &= 0x80; \
+ IE |= ACC; \
+ _asm \
+ pop ACC \
+ _endasm;
-#define portDISABLE_INTERRUPTS() EA = 0;
-#define portENABLE_INTERRUPTS() EA = 1;
+#define portDISABLE_INTERRUPTS() EA = 0;
+#define portENABLE_INTERRUPTS() EA = 1;
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 1
-#define portSTACK_GROWTH ( 1 )
-#define portTICK_PERIOD_MS ( ( uint32_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 1
+#define portSTACK_GROWTH ( 1 )
+#define portTICK_PERIOD_MS ( ( uint32_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Task utilities. */
void vPortYield( void ) _naked;
-#define portYIELD() vPortYield();
+#define portYIELD() vPortYield();
/*-----------------------------------------------------------*/
-#define portNOP() \
- _asm \
- nop \
- _endasm;
+#define portNOP() _asm \
+ nop \
+ _endasm;
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#endif /* PORTMACRO_H */
+
+
diff --git a/portable/Softune/MB91460/__STD_LIB_sbrk.c b/portable/Softune/MB91460/__STD_LIB_sbrk.c
index 08201ca..fe70d48 100644
--- a/portable/Softune/MB91460/__STD_LIB_sbrk.c
+++ b/portable/Softune/MB91460/__STD_LIB_sbrk.c
@@ -1,25 +1,23 @@
#include "FreeRTOSConfig.h"
#include <stdlib.h>
-static long brk_siz = 0;
-/* #if configTOTAL_HEAP_SIZE != 0 */
-typedef int _heep_t;
-#define ROUNDUP( s ) ( ( ( s ) + sizeof( _heep_t ) - 1 ) & ~( sizeof( _heep_t ) - 1 ) )
-static _heep_t _heep[ ROUNDUP( configTOTAL_HEAP_SIZE ) / sizeof( _heep_t ) ];
-#define _heep_size ROUNDUP( configTOTAL_HEAP_SIZE )
-
+ static long brk_siz = 0;
+// #if configTOTAL_HEAP_SIZE != 0
+ typedef int _heep_t;
+ #define ROUNDUP(s) (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
+ static _heep_t _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
+ #define _heep_size ROUNDUP(configTOTAL_HEAP_SIZE)
/* #else
- * extern char *_heep;
- * extern long _heep_size;
- #endif
- */
-extern char * sbrk( int size )
-{
- if( ( brk_siz + size > _heep_size ) || ( brk_siz + size < 0 ) )
- {
- return( ( char * ) -1 );
- }
+ extern char *_heep;
+ extern long _heep_size;
+ #endif
+*/
+ extern char *sbrk(int size)
+ {
+ if (brk_siz + size > _heep_size || brk_siz + size < 0)
- brk_siz += size;
- return( ( char * ) _heep + brk_siz - size );
-}
+ return((char*)-1);
+ brk_siz += size;
+ return( (char*)_heep + brk_siz - size);
+ }
+
diff --git a/portable/Softune/MB91460/port.c b/portable/Softune/MB91460/port.c
index 23c3195..0f09f40 100644
--- a/portable/Softune/MB91460/port.c
+++ b/portable/Softune/MB91460/port.c
@@ -32,12 +32,12 @@
/*-----------------------------------------------------------*/
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/*-----------------------------------------------------------*/
-
+
#pragma asm
#macro SaveContext
ORCCR #0x20 ;Switch to user stack
@@ -46,21 +46,21 @@
STM1 (R14,R13,R12,R11,R10,R9,R8) ;Store R14-R8
ST MDH, @-R15 ;Store MDH
ST MDL, @-R15 ;Store MDL
-
+
ANDCCR #0xDF ;Switch back to system stack
LD @R15+,R0 ;Store PC to R0
ORCCR #0x20 ;Switch to user stack
ST R0,@-R15 ;Store PC to User stack
-
+
ANDCCR #0xDF ;Switch back to system stack
LD @R15+,R0 ;Store PS to R0
ORCCR #0x20 ;Switch to user stack
ST R0,@-R15 ;Store PS to User stack
-
+
LDI #_pxCurrentTCB, R0 ;Get pxCurrentTCB address
LD @R0, R0 ;Get the pxCurrentTCB->pxTopOfStack address
ST R15,@R0 ;Store USP to pxCurrentTCB->pxTopOfStack
-
+
ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR
#endm
@@ -86,7 +86,7 @@
LDM1 (R14,R13,R12,R11,R10,R9,R8) ;Restore R14-R8
LDM0 (R7,R6,R5,R4,R3,R2,R1,R0) ;Restore R7-R0
LD @R15+, RP ;Restore RP
-
+
ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR
#endm
#pragma endasm
@@ -99,142 +99,140 @@
static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
-/*
- * Initialise the stack of a task to look exactly as if a call to
+/*
+ * Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
- *
+ *
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging. */
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
- *pxTopOfStack = 0x11111111;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
+ *pxTopOfStack = 0x11111111;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
- /* This is a redundant push to the stack, it may be required if
- * in some implementations of the compiler the parameter to the task
- * is passed on to the stack rather than in R4 register. */
- *pxTopOfStack = ( StackType_t ) ( pvParameters );
- pxTopOfStack--;
+ /* This is a redundant push to the stack, it may be required if
+ in some implementations of the compiler the parameter to the task
+ is passed on to the stack rather than in R4 register. */
+ *pxTopOfStack = (StackType_t)(pvParameters);
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0x00000000; /* RP */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00007777; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00006666; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00005555; /* R5 */
+ pxTopOfStack--;
+
+ /* In the current implementation of the compiler the first
+ parameter to the task (or function) is passed via R4 parameter
+ to the task, hence the pvParameters pointer is copied into the R4
+ register. See compiler manual section 4.6.2 for more information. */
+ *pxTopOfStack = ( StackType_t ) (pvParameters); /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00003333; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00002222; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00001111; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000001; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0000EEEE; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0000DDDD; /* R13 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0000CCCC; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0000BBBB; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0000AAAA; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00009999; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00008888; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11110000; /* MDH */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x22220000; /* MDL */
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000; /* RP */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00007777; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00006666; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00005555; /* R5 */
- pxTopOfStack--;
-
- /* In the current implementation of the compiler the first
- * parameter to the task (or function) is passed via R4 parameter
- * to the task, hence the pvParameters pointer is copied into the R4
- * register. See compiler manual section 4.6.2 for more information. */
- *pxTopOfStack = ( StackType_t ) ( pvParameters ); /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00003333; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00002222; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00001111; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000001; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0000EEEE; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0000DDDD; /* R13 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0000CCCC; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0000BBBB; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0000AAAA; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00009999; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00008888; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11110000; /* MDH */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x22220000; /* MDL */
- pxTopOfStack--;
-
- /* The start of the task code. */
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
-
+ /* The start of the task code. */
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+
/* PS - User Mode, USP, ILM=31, Interrupts enabled */
- *pxTopOfStack = ( StackType_t ) 0x001F0030; /* PS */
+ *pxTopOfStack = ( StackType_t ) 0x001F0030; /* PS */
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup the hardware to generate the tick. */
- prvSetupTimerInterrupt();
+ /* Setup the hardware to generate the tick. */
+ prvSetupTimerInterrupt();
- /* Restore the context of the first task that is going to run. */
- #pragma asm
+ /* Restore the context of the first task that is going to run. */
+ #pragma asm
RestoreContext
- #pragma endasm
+ #pragma endasm
- /* Simulate a function call end as generated by the compiler. We will now
- * jump to the start of the task the context of which we have just restored. */
- __asm( " reti " );
+ /* Simulate a function call end as generated by the compiler. We will now
+ jump to the start of the task the context of which we have just restored. */
+ __asm(" reti ");
- /* Should not get here. */
- return pdFAIL;
+ /* Should not get here. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented - unlikely to ever be required as there is nothing to
- * return to. */
+ /* Not implemented - unlikely to ever be required as there is nothing to
+ return to. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
/* The peripheral clock divided by 32 is used by the timer. */
- const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL );
+const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL );
- /* Setup RLT0 to generate a tick interrupt. */
+ /* Setup RLT0 to generate a tick interrupt. */
- TMCSR0_CNTE = 0; /* Count Disable */
- TMCSR0_CSL = 0x2; /* CLKP/32 */
- TMCSR0_MOD = 0; /* Software trigger */
- TMCSR0_RELD = 1; /* Reload */
-
- TMCSR0_UF = 0; /* Clear underflow flag */
- TMRLR0 = usReloadValue;
- TMCSR0_INTE = 1; /* Interrupt Enable */
- TMCSR0_CNTE = 1; /* Count Enable */
- TMCSR0_TRG = 1; /* Trigger */
-
- PORTEN = 0x3; /* Port Enable */
+ TMCSR0_CNTE = 0; /* Count Disable */
+ TMCSR0_CSL = 0x2; /* CLKP/32 */
+ TMCSR0_MOD = 0; /* Software trigger */
+ TMCSR0_RELD = 1; /* Reload */
+
+ TMCSR0_UF = 0; /* Clear underflow flag */
+ TMRLR0 = usReloadValue;
+ TMCSR0_INTE = 1; /* Interrupt Enable */
+ TMCSR0_CNTE = 1; /* Count Enable */
+ TMCSR0_TRG = 1; /* Trigger */
+
+ PORTEN = 0x3; /* Port Enable */
}
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 1
-/*
- * Tick ISR for preemptive scheduler. The tick count is incremented
- * after the context is saved. Then the context is switched if required,
- * and last the context of the task which is to be resumed is restored.
- */
+ /*
+ * Tick ISR for preemptive scheduler. The tick count is incremented
+ * after the context is saved. Then the context is switched if required,
+ * and last the context of the task which is to be resumed is restored.
+ */
- #pragma asm
+ #pragma asm
.global _ReloadTimer0_IRQHandler
_ReloadTimer0_IRQHandler:
@@ -256,28 +254,28 @@
RETI
- #pragma endasm
+ #pragma endasm
+
+#else
+
+ /*
+ * Tick ISR for the cooperative scheduler. All this does is increment the
+ * tick count. We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+ __interrupt void ReloadTimer0_IRQHandler( void )
+ {
+ /* Clear RLT0 interrupt flag */
+ TMCSR0_UF = 0;
+ xTaskIncrementTick();
+ }
-#else /* if configUSE_PREEMPTION == 1 */
+#endif
/*
- * Tick ISR for the cooperative scheduler. All this does is increment the
- * tick count. We don't need to switch context, this can only be done by
- * manual calls to taskYIELD();
- */
- __interrupt void ReloadTimer0_IRQHandler( void )
- {
- /* Clear RLT0 interrupt flag */
- TMCSR0_UF = 0;
- xTaskIncrementTick();
- }
-
-#endif /* if configUSE_PREEMPTION == 1 */
-
-/*
- * Manual context switch. We can use a __nosavereg attribute as the context
- * would be saved by PortSAVE_CONTEXT(). The context is switched and then
- * the context of the new task is restored saved.
+ * Manual context switch. We can use a __nosavereg attribute as the context
+ * would be saved by PortSAVE_CONTEXT(). The context is switched and then
+ * the context of the new task is restored saved.
*/
#pragma asm
@@ -303,10 +301,10 @@
/*-----------------------------------------------------------*/
/*
- * Manual context switch. We can use a __nosavereg attribute as the context
- * would be saved by PortSAVE_CONTEXT(). The context is switched and then
- * the context of the new task is restored saved.
- */
+ * Manual context switch. We can use a __nosavereg attribute as the context
+ * would be saved by PortSAVE_CONTEXT(). The context is switched and then
+ * the context of the new task is restored saved.
+ */
#pragma asm
.global _vPortYield
@@ -315,8 +313,9 @@
SaveContext ;Save context
CALL32 _vTaskSwitchContext,R12 ;Switch context if required
RestoreContext ;Restore context
-
+
RETI
#pragma endasm
/*-----------------------------------------------------------*/
+
diff --git a/portable/Softune/MB91460/portmacro.h b/portable/Softune/MB91460/portmacro.h
index 3c36f22..d6ef265 100644
--- a/portable/Softune/MB91460/portmacro.h
+++ b/portable/Softune/MB91460/portmacro.h
@@ -45,64 +45,65 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Critical section management. */
#if configKERNEL_INTERRUPT_PRIORITY != 30
- #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - 30 (1Eh) being the default.
+ #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - 30 (1Eh) being the default.
#endif
-#define portDISABLE_INTERRUPTS() __asm( " STILM #1Eh " )
-#define portENABLE_INTERRUPTS() __asm( " STILM #1Fh " )
+#define portDISABLE_INTERRUPTS() __asm(" STILM #1Eh ")
+#define portENABLE_INTERRUPTS() __asm(" STILM #1Fh ")
-#define portENTER_CRITICAL() \
- __asm( " ST PS,@-R15 " ); \
- __asm( " ANDCCR #0xef " ); \
+#define portENTER_CRITICAL() \
+ __asm(" ST PS,@-R15 "); \
+ __asm(" ANDCCR #0xef "); \
-#define portEXIT_CRITICAL() \
- __asm( " LD @R15+,PS " ); \
+#define portEXIT_CRITICAL() \
+ __asm(" LD @R15+,PS "); \
/*-----------------------------------------------------------*/
/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 4
-#define portNOP() __asm( " nop " );
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() __asm( " nop " );
/*-----------------------------------------------------------*/
/* portYIELD() uses a SW interrupt */
-#define portYIELD() __asm( " INT #40H " );
+#define portYIELD() __asm( " INT #40H " );
/* portYIELD_FROM_ISR() uses delayed interrupt */
-#define portYIELD_FROM_ISR() DICR_DLYI = 1
+#define portYIELD_FROM_ISR() DICR_DLYI = 1
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
+#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
#endif /* PORTMACRO_H */
+
diff --git a/portable/Softune/MB96340/__STD_LIB_sbrk.c b/portable/Softune/MB96340/__STD_LIB_sbrk.c
index 0906319..a520aff 100644
--- a/portable/Softune/MB96340/__STD_LIB_sbrk.c
+++ b/portable/Softune/MB96340/__STD_LIB_sbrk.c
@@ -2,29 +2,27 @@
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES. */
/* (C) Fujitsu Microelectronics Europe GmbH */
-
/*---------------------------------------------------------------------------
- * __STD_LIB_sbrk.C
- * - Used by heap_3.c for memory accocation and deletion.
- *
- * /*---------------------------------------------------------------------------*/
+ __STD_LIB_sbrk.C
+ - Used by heap_3.c for memory accocation and deletion.
+
+/*---------------------------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include <stdlib.h>
-static long brk_siz = 0;
-typedef int _heep_t;
-#define ROUNDUP( s ) ( ( ( s ) + sizeof( _heep_t ) - 1 ) & ~( sizeof( _heep_t ) - 1 ) )
-static _heep_t _heep[ ROUNDUP( configTOTAL_HEAP_SIZE ) / sizeof( _heep_t ) ];
-#define _heep_size ROUNDUP( configTOTAL_HEAP_SIZE )
+ static long brk_siz = 0;
+ typedef int _heep_t;
+ #define ROUNDUP(s) (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
+ static _heep_t _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
+ #define _heep_size ROUNDUP(configTOTAL_HEAP_SIZE)
-extern char * sbrk( int size )
-{
- if( ( brk_siz + size > _heep_size ) || ( brk_siz + size < 0 ) )
- {
- return( ( char * ) -1 );
- }
+ extern char *sbrk(int size)
+ {
+ if (brk_siz + size > _heep_size || brk_siz + size < 0)
- brk_siz += size;
- return( ( char * ) _heep + brk_siz - size );
-}
+ return((char*)-1);
+ brk_siz += size;
+ return( (char*)_heep + brk_siz - size);
+ }
+
diff --git a/portable/Softune/MB96340/port.c b/portable/Softune/MB96340/port.c
index dea30bd..f7cf2c8 100644
--- a/portable/Softune/MB96340/port.c
+++ b/portable/Softune/MB96340/port.c
@@ -29,16 +29,16 @@
#include "task.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the 16FX port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the 16FX port.
+ *----------------------------------------------------------*/
-/*
- * Get current value of DPR and ADB registers
+/*
+ * Get current value of DPR and ADB registers
*/
-StackType_t xGet_DPR_ADB_bank( void );
+StackType_t xGet_DPR_ADB_bank( void );
-/*
- * Get current value of DTB and PCB registers
+/*
+ * Get current value of DTB and PCB registers
*/
StackType_t xGet_DTB_PCB_bank( void );
@@ -50,176 +50,176 @@
/*-----------------------------------------------------------*/
-/*
+/*
* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type.
+ * any details of its type.
*/
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/*-----------------------------------------------------------*/
-/*
- * Macro to save a task context to the task stack. This macro copies the
- * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from the system
- * stack to task stack pointed by user stack pointer ( USP for SMALL and
+/*
+ * Macro to save a task context to the task stack. This macro copies the
+ * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from the system
+ * stack to task stack pointed by user stack pointer ( USP for SMALL and
* MEDIUM memory model amd USB:USP for COMPACT and LARGE memory model ),
- * then it pushes the general purpose registers RW0-RW7 on to the task
- * stack. Finally the resultant stack pointer value is saved into the
- * task control block so it can be retrieved the next time the task
+ * then it pushes the general purpose registers RW0-RW7 on to the task
+ * stack. Finally the resultant stack pointer value is saved into the
+ * task control block so it can be retrieved the next time the task
* executes.
- */
-#if ( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) )
+ */
+#if( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) )
- #define portSAVE_CONTEXT() \
- { __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
- __asm( " MOVW A, _pxCurrentTCB " ); \
- __asm( " MOVW A, SP " ); \
- __asm( " SWAPW " ); \
- __asm( " MOVW @AL, AH " ); \
- __asm( " OR CCR,#H'20 " ); \
- }
+ #define portSAVE_CONTEXT() \
+ { __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
+ __asm(" MOVW A, _pxCurrentTCB "); \
+ __asm(" MOVW A, SP "); \
+ __asm(" SWAPW "); \
+ __asm(" MOVW @AL, AH "); \
+ __asm(" OR CCR,#H'20 "); \
+ }
-/*
+/*
* Macro to restore a task context from the task stack. This is effecti-
* vely the reverse of SAVE_CONTEXT(). First the stack pointer value
- * (USP for SMALL and MEDIUM memory model amd USB:USP for COMPACT and
- * LARGE memory model ) is loaded from the task control block. Next the
+ * (USP for SMALL and MEDIUM memory model amd USB:USP for COMPACT and
+ * LARGE memory model ) is loaded from the task control block. Next the
* value of all the general purpose registers RW0-RW7 is retrieved. Fina-
- * lly it copies of the context ( AH:AL, DPR:ADB, DTB:PCB, PC and PS) of
- * the task to be executed upon RETI from user stack to system stack.
+ * lly it copies of the context ( AH:AL, DPR:ADB, DTB:PCB, PC and PS) of
+ * the task to be executed upon RETI from user stack to system stack.
*/
+
+ #define portRESTORE_CONTEXT() \
+ { __asm(" MOVW A, _pxCurrentTCB "); \
+ __asm(" MOVW A, @A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" MOVW SP, A "); \
+ __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ }
+
+#elif( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
- #define portRESTORE_CONTEXT() \
- { __asm( " MOVW A, _pxCurrentTCB " ); \
- __asm( " MOVW A, @A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " MOVW SP, A " ); \
- __asm( " POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- }
+ #define portSAVE_CONTEXT() \
+ { __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" POPW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" PUSHW A "); \
+ __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
+ __asm(" MOVL A, _pxCurrentTCB "); \
+ __asm(" MOVL RL2, A "); \
+ __asm(" MOVW A, SP "); \
+ __asm(" MOVW @RL2+0, A "); \
+ __asm(" MOV A, USB "); \
+ __asm(" MOV @RL2+2, A "); \
+ }
+
+ #define portRESTORE_CONTEXT() \
+ { __asm(" MOVL A, _pxCurrentTCB "); \
+ __asm(" MOVL RL2, A "); \
+ __asm(" MOVW A, @RL2+0 "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" MOVW SP, A "); \
+ __asm(" MOV A, @RL2+2 "); \
+ __asm(" MOV USB, A "); \
+ __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ __asm(" AND CCR,#H'DF "); \
+ __asm(" POPW A "); \
+ __asm(" OR CCR,#H'20 "); \
+ __asm(" PUSHW A "); \
+ }
+#endif
-#elif ( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
+/*-----------------------------------------------------------*/
- #define portSAVE_CONTEXT() \
- { __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " POPW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " PUSHW A " ); \
- __asm( " PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
- __asm( " MOVL A, _pxCurrentTCB " ); \
- __asm( " MOVL RL2, A " ); \
- __asm( " MOVW A, SP " ); \
- __asm( " MOVW @RL2+0, A " ); \
- __asm( " MOV A, USB " ); \
- __asm( " MOV @RL2+2, A " ); \
- }
-
- #define portRESTORE_CONTEXT() \
- { __asm( " MOVL A, _pxCurrentTCB " ); \
- __asm( " MOVL RL2, A " ); \
- __asm( " MOVW A, @RL2+0 " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " MOVW SP, A " ); \
- __asm( " MOV A, @RL2+2 " ); \
- __asm( " MOV USB, A " ); \
- __asm( " POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- __asm( " AND CCR,#H'DF " ); \
- __asm( " POPW A " ); \
- __asm( " OR CCR,#H'20 " ); \
- __asm( " PUSHW A " ); \
- }
-#endif /* if ( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) ) */
-
-/*-----------------------------------------------------------*/
-
-/*
+/*
* Functions for obtaining the current value of DPR:ADB, DTB:PCB bank registers
*/
-
+
#pragma asm
.GLOBAL _xGet_DPR_ADB_bank
@@ -254,257 +254,256 @@
#pragma endasm
/*-----------------------------------------------------------*/
-/*
- * Initialise the stack of a task to look exactly as if a call to
+/*
+ * Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
- *
+ *
* See the header file portable.h.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging. */
- *pxTopOfStack = 0x1111;
- pxTopOfStack--;
- *pxTopOfStack = 0x2222;
- pxTopOfStack--;
- *pxTopOfStack = 0x3333;
- pxTopOfStack--;
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
+ *pxTopOfStack = 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x3333;
+ pxTopOfStack--;
- /* Once the task is called the task would push the pointer to the
- * parameter onto the stack. Hence here the pointer would be copied to the stack
- * first. When using the COMPACT or LARGE memory model the pointer would be 24
- * bits, and when using the SMALL or MEDIUM memory model the pointer would be 16
- * bits. */
- #if ( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
- {
- *pxTopOfStack = ( StackType_t ) ( ( uint32_t ) ( pvParameters ) >> 16 );
- pxTopOfStack--;
- }
- #endif
+ /* Once the task is called the task would push the pointer to the
+ parameter onto the stack. Hence here the pointer would be copied to the stack
+ first. When using the COMPACT or LARGE memory model the pointer would be 24
+ bits, and when using the SMALL or MEDIUM memory model the pointer would be 16
+ bits. */
+ #if( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
+ {
+ *pxTopOfStack = ( StackType_t ) ( ( uint32_t ) ( pvParameters ) >> 16 );
+ pxTopOfStack--;
+ }
+ #endif
*pxTopOfStack = ( StackType_t ) ( pvParameters );
- pxTopOfStack--;
+ pxTopOfStack--;
+
+ /* This is redundant push to the stack. This is required in order to introduce
+ an offset so that the task accesses a parameter correctly that is passed on to
+ the task stack. */
+ #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
+ {
+ *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
+ pxTopOfStack--;
+ }
+ #endif
- /* This is redundant push to the stack. This is required in order to introduce
- * an offset so that the task accesses a parameter correctly that is passed on to
- * the task stack. */
- #if ( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
- {
- *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
- pxTopOfStack--;
- }
- #endif
-
- /* This is redundant push to the stack. This is required in order to introduce
- * an offset so the task correctly accesses the parameter passed on the task stack. */
+ /* This is redundant push to the stack. This is required in order to introduce
+ an offset so the task correctly accesses the parameter passed on the task stack. */
*pxTopOfStack = ( StackType_t ) ( pxCode );
- pxTopOfStack--;
+ pxTopOfStack--;
/* PS - User Mode, ILM=7, RB=0, Interrupts enabled,USP */
- *pxTopOfStack = 0xE0C0;
- pxTopOfStack--;
+ *pxTopOfStack = 0xE0C0;
+ pxTopOfStack--;
- /* PC */
- *pxTopOfStack = ( StackType_t ) ( pxCode );
- pxTopOfStack--;
-
+ /* PC */
+ *pxTopOfStack = ( StackType_t ) ( pxCode );
+ pxTopOfStack--;
+
/* DTB | PCB */
- #if configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT
- {
- *pxTopOfStack = xGet_DTB_PCB_bank();
- pxTopOfStack--;
- }
- #endif
+ #if configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT
+ {
+ *pxTopOfStack = xGet_DTB_PCB_bank();
+ pxTopOfStack--;
+ }
+ #endif
- /* DTB | PCB, in case of MEDIUM and LARGE memory models, PCB would be used
- * along with PC to indicate the start address of the function. */
- #if ( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
- {
- *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
- pxTopOfStack--;
- }
- #endif
+ /* DTB | PCB, in case of MEDIUM and LARGE memory models, PCB would be used
+ along with PC to indicate the start address of the function. */
+ #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
+ {
+ *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
+ pxTopOfStack--;
+ }
+ #endif
- /* DPR | ADB */
- *pxTopOfStack = xGet_DPR_ADB_bank();
- pxTopOfStack--;
+ /* DPR | ADB */
+ *pxTopOfStack = xGet_DPR_ADB_bank();
+ pxTopOfStack--;
+
+ /* AL */
+ *pxTopOfStack = ( StackType_t ) 0x9999;
+ pxTopOfStack--;
- /* AL */
- *pxTopOfStack = ( StackType_t ) 0x9999;
- pxTopOfStack--;
-
- /* AH */
- *pxTopOfStack = ( StackType_t ) 0xAAAA;
- pxTopOfStack--;
-
- /* Next the general purpose registers. */
- *pxTopOfStack = ( StackType_t ) 0x7777; /* RW7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x6666; /* RW6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x5555; /* RW5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x4444; /* RW4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x3333; /* RW3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x2222; /* RW2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1111; /* RW1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x8888; /* RW0 */
-
- return pxTopOfStack;
+ /* AH */
+ *pxTopOfStack = ( StackType_t ) 0xAAAA;
+ pxTopOfStack--;
+
+ /* Next the general purpose registers. */
+ *pxTopOfStack = ( StackType_t ) 0x7777; /* RW7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x6666; /* RW6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x5555; /* RW5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x4444; /* RW4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x3333; /* RW3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x2222; /* RW2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1111; /* RW1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x8888; /* RW0 */
+
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvSetupRLT0Interrupt( void )
{
/* The peripheral clock divided by 16 is used by the timer. */
- const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL );
+const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL );
- /* set reload value = 34999+1, TICK Interrupt after 10 ms @ 56MHz of CLKP1 */
- TMRLR0 = usReloadValue;
-
+ /* set reload value = 34999+1, TICK Interrupt after 10 ms @ 56MHz of CLKP1 */
+ TMRLR0 = usReloadValue;
+
/* prescaler 1:16, reload, interrupt enable, count enable, trigger */
- TMCSR0 = 0x041B;
+ TMCSR0 = 0x041B;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Setup the hardware to generate the tick. */
- prvSetupRLT0Interrupt();
+ /* Setup the hardware to generate the tick. */
+ prvSetupRLT0Interrupt();
+
+ /* Restore the context of the first task that is going to run. */
+ portRESTORE_CONTEXT();
- /* Restore the context of the first task that is going to run. */
- portRESTORE_CONTEXT();
-
- /* Simulate a function call end as generated by the compiler. We will now
- * jump to the start of the task the context of which we have just restored. */
- __asm( " reti " );
+ /* Simulate a function call end as generated by the compiler. We will now
+ jump to the start of the task the context of which we have just restored. */
+ __asm(" reti ");
- /* Should not get here. */
- return pdTRUE;
+ /* Should not get here. */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented - unlikely to ever be required as there is nothing to
- * return to. */
+ /* Not implemented - unlikely to ever be required as there is nothing to
+ return to. */
}
/*-----------------------------------------------------------*/
-/*
+/*
* The interrupt service routine used depends on whether the pre-emptive
* scheduler is being used or not.
*/
#if configUSE_PREEMPTION == 1
-/*
- * Tick ISR for preemptive scheduler. We can use a __nosavereg attribute
- * as the context is to be saved by the portSAVE_CONTEXT() macro, not the
- * compiler generated code. The tick count is incremented after the context
- * is saved.
- */
- __nosavereg __interrupt void prvRLT0_TICKISR( void )
- {
- /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
- __DI();
+ /*
+ * Tick ISR for preemptive scheduler. We can use a __nosavereg attribute
+ * as the context is to be saved by the portSAVE_CONTEXT() macro, not the
+ * compiler generated code. The tick count is incremented after the context
+ * is saved.
+ */
+ __nosavereg __interrupt void prvRLT0_TICKISR( void )
+ {
+ /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
+ __DI();
+
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
+
+ /* Enable interrupts */
+ __EI();
+
+ /* Clear RLT0 interrupt flag */
+ TMCSR0_UF = 0;
+
+ /* Increment the tick count then switch to the highest priority task
+ that is ready to run. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
+ /* Disable interrupts so that portRESTORE_CONTEXT() is not interrupted */
+ __DI();
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+
+ /* Enable interrupts */
+ __EI();
+ }
- /* Enable interrupts */
- __EI();
+#else
- /* Clear RLT0 interrupt flag */
- TMCSR0_UF = 0;
+ /*
+ * Tick ISR for the cooperative scheduler. All this does is increment the
+ * tick count. We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+ __interrupt void prvRLT0_TICKISR( void )
+ {
+ /* Clear RLT0 interrupt flag */
+ TMCSR0_UF = 0;
+
+ xTaskIncrementTick();
+ }
- /* Increment the tick count then switch to the highest priority task
- * that is ready to run. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Disable interrupts so that portRESTORE_CONTEXT() is not interrupted */
- __DI();
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
-
- /* Enable interrupts */
- __EI();
- }
-
-#else /* if configUSE_PREEMPTION == 1 */
-
-/*
- * Tick ISR for the cooperative scheduler. All this does is increment the
- * tick count. We don't need to switch context, this can only be done by
- * manual calls to taskYIELD();
- */
- __interrupt void prvRLT0_TICKISR( void )
- {
- /* Clear RLT0 interrupt flag */
- TMCSR0_UF = 0;
-
- xTaskIncrementTick();
- }
-
-#endif /* if configUSE_PREEMPTION == 1 */
+#endif
/*-----------------------------------------------------------*/
/*
- * Manual context switch. We can use a __nosavereg attribute as the context
- * is to be saved by the portSAVE_CONTEXT() macro, not the compiler generated
+ * Manual context switch. We can use a __nosavereg attribute as the context
+ * is to be saved by the portSAVE_CONTEXT() macro, not the compiler generated
* code.
*/
__nosavereg __interrupt void vPortYield( void )
{
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
-
- /* Switch to the highest priority task that is ready to run. */
- vTaskSwitchContext();
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
+
+ /* Switch to the highest priority task that is ready to run. */
+ vTaskSwitchContext();
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
__nosavereg __interrupt void vPortYieldDelayed( void )
-{
- /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
- __DI();
+{
+ /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
+ __DI();
+
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
+
+ /* Enable interrupts */
+ __EI();
+
+ /* Clear delayed interrupt flag */
+ __asm (" CLRB 03A4H:0 ");
+
+ /* Switch to the highest priority task that is ready to run. */
+ vTaskSwitchContext();
+
+ /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
+ __DI();
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
-
- /* Enable interrupts */
- __EI();
-
- /* Clear delayed interrupt flag */
- __asm( " CLRB 03A4H:0 " );
-
- /* Switch to the highest priority task that is ready to run. */
- vTaskSwitchContext();
-
- /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
- __DI();
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
-
- /* Enable interrupts */
- __EI();
-}
+ /* Enable interrupts */
+ __EI();
+}
/*-----------------------------------------------------------*/
+
diff --git a/portable/Softune/MB96340/portmacro.h b/portable/Softune/MB96340/portmacro.h
index 84f3bec..7b27f51 100644
--- a/portable/Softune/MB96340/portmacro.h
+++ b/portable/Softune/MB96340/portmacro.h
@@ -33,11 +33,11 @@
#include <stddef.h>
/* Constants denoting the available memory models. These are used within
- * FreeRTOSConfig.h to set the configMEMMODEL value. */
-#define portSMALL 0
-#define portMEDIUM 1
-#define portCOMPACT 2
-#define portLARGE 3
+FreeRTOSConfig.h to set the configMEMMODEL value. */
+#define portSMALL 0
+#define portMEDIUM 1
+#define portCOMPACT 2
+#define portLARGE 3
/*-----------------------------------------------------------
@@ -51,65 +51,66 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint16_t
-#define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Critical section handling. */
#if configKERNEL_INTERRUPT_PRIORITY != 6
- #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - #06H being the default.
+ #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - #06H being the default.
#endif
-#define portDISABLE_INTERRUPTS() __asm( " MOV ILM, #06h " )
-#define portENABLE_INTERRUPTS() __asm( " MOV ILM, #07h " )
+#define portDISABLE_INTERRUPTS() __asm(" MOV ILM, #06h ")
+#define portENABLE_INTERRUPTS() __asm(" MOV ILM, #07h ")
-#define portENTER_CRITICAL() \
- { __asm( " PUSHW PS " ); \
- portDISABLE_INTERRUPTS(); \
- }
+#define portENTER_CRITICAL() \
+ { __asm(" PUSHW PS "); \
+ portDISABLE_INTERRUPTS(); \
+ }
-#define portEXIT_CRITICAL() \
- { __asm( " POPW PS " ); \
- }
+#define portEXIT_CRITICAL() \
+ { __asm(" POPW PS "); \
+ }
/*-----------------------------------------------------------*/
/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 2
-#define portNOP() __asm( " NOP " );
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portNOP() __asm( " NOP " );
/*-----------------------------------------------------------*/
/* portYIELD() uses SW interrupt */
-#define portYIELD() __asm( " INT #122 " );
+#define portYIELD() __asm( " INT #122 " );
/* portYIELD_FROM_ISR() uses delayed interrupt */
-#define portYIELD_FROM_ISR() __asm( " SETB 03A4H:0 " );
+#define portYIELD_FROM_ISR() __asm( " SETB 03A4H:0 " );
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
+#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
#endif /* PORTMACRO_H */
+
diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
index 6cd0cc9..db8d50f 100644
--- a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
+++ b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
@@ -25,41 +25,39 @@
#include "FreeRTOS.h"
#include "task.h"
-extern void vPortStartTask( void );
+extern void vPortStartTask(void);
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
- * will be set to 0 prior to the first task being started. */
+will be set to 0 prior to the first task being started. */
portLONG ulCriticalNesting = 0x9999UL;
/* Used to record one tack want to swtich task after enter critical area, we need know it
* and implement task switch after exit critical area */
portLONG pendsvflag = 0;
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t * stk = NULL;
+ StackType_t *stk = NULL;
stk = pxTopOfStack;
- *( --stk ) = ( uint32_t ) pxCode; /* Entry Point */
- *( --stk ) = ( uint32_t ) 0xE0000140L; /* PSR */
- *( --stk ) = ( uint32_t ) 0xFFFFFFFEL; /* R15 (LR) (init value will cause fault if ever used) */
- *( --stk ) = ( uint32_t ) 0x13131313L; /* R13 */
- *( --stk ) = ( uint32_t ) 0x12121212L; /* R12 */
- *( --stk ) = ( uint32_t ) 0x11111111L; /* R11 */
- *( --stk ) = ( uint32_t ) 0x10101010L; /* R10 */
- *( --stk ) = ( uint32_t ) 0x09090909L; /* R9 */
- *( --stk ) = ( uint32_t ) 0x08080808L; /* R8 */
- *( --stk ) = ( uint32_t ) 0x07070707L; /* R7 */
- *( --stk ) = ( uint32_t ) 0x06060606L; /* R6 */
- *( --stk ) = ( uint32_t ) 0x05050505L; /* R5 */
- *( --stk ) = ( uint32_t ) 0x04040404L; /* R4 */
- *( --stk ) = ( uint32_t ) 0x03030303L; /* R3 */
- *( --stk ) = ( uint32_t ) 0x02020202L; /* R2 */
- *( --stk ) = ( uint32_t ) 0x01010101L; /* R1 */
- *( --stk ) = ( uint32_t ) pvParameters; /* R0 : argument */
+ *(--stk) = (uint32_t)pxCode; /* Entry Point */
+ *(--stk) = (uint32_t)0xE0000140L; /* PSR */
+ *(--stk) = (uint32_t)0xFFFFFFFEL; /* R15 (LR) (init value will cause fault if ever used) */
+ *(--stk) = (uint32_t)0x13131313L; /* R13 */
+ *(--stk) = (uint32_t)0x12121212L; /* R12 */
+ *(--stk) = (uint32_t)0x11111111L; /* R11 */
+ *(--stk) = (uint32_t)0x10101010L; /* R10 */
+ *(--stk) = (uint32_t)0x09090909L; /* R9 */
+ *(--stk) = (uint32_t)0x08080808L; /* R8 */
+ *(--stk) = (uint32_t)0x07070707L; /* R7 */
+ *(--stk) = (uint32_t)0x06060606L; /* R6 */
+ *(--stk) = (uint32_t)0x05050505L; /* R5 */
+ *(--stk) = (uint32_t)0x04040404L; /* R4 */
+ *(--stk) = (uint32_t)0x03030303L; /* R3 */
+ *(--stk) = (uint32_t)0x02020202L; /* R2 */
+ *(--stk) = (uint32_t)0x01010101L; /* R1 */
+ *(--stk) = (uint32_t)pvParameters; /* R0 : argument */
return stk;
}
@@ -82,25 +80,21 @@
void vPortEnterCritical( void )
{
portDISABLE_INTERRUPTS();
- ulCriticalNesting++;
+ ulCriticalNesting ++;
}
void vPortExitCritical( void )
{
- if( ulCriticalNesting == 0 )
- {
- while( 1 )
- {
- }
+ if (ulCriticalNesting == 0) {
+ while(1);
}
- ulCriticalNesting--;
-
- if( ulCriticalNesting == 0 )
+ ulCriticalNesting --;
+ if (ulCriticalNesting == 0)
{
portENABLE_INTERRUPTS();
- if( pendsvflag )
+ if (pendsvflag)
{
pendsvflag = 0;
portYIELD();
@@ -109,30 +103,30 @@
}
#if configUSE_PREEMPTION == 0
- void xPortSysTickHandler( void )
- {
- portLONG ulDummy;
+void xPortSysTickHandler( void )
+{
+ portLONG ulDummy;
- ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
- xTaskIncrementTick();
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
- }
+ ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ xTaskIncrementTick();
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
#else
- void xPortSysTickHandler( void )
- {
- portLONG ulDummy;
+void xPortSysTickHandler( void )
+{
+ portLONG ulDummy;
- ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ if (xTaskIncrementTick() != pdFALSE)
{
- if( xTaskIncrementTick() != pdFALSE )
- {
- portYIELD_FROM_ISR( pdTRUE );
- }
+ portYIELD_FROM_ISR(pdTRUE);
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
}
-#endif /* if configUSE_PREEMPTION == 0 */
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+#endif
void vPortYieldHandler( void )
{
@@ -145,17 +139,12 @@
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}
-__attribute__( ( weak ) ) void vApplicationStackOverflowHook( xTaskHandle * pxTask,
- signed portCHAR * pcTaskName )
+__attribute__((weak)) void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )
{
- for( ; ; )
- {
- }
+ for(;;);
}
-__attribute__( ( weak ) ) void vApplicationMallocFailedHook( void )
+__attribute__((weak)) void vApplicationMallocFailedHook( void )
{
- for( ; ; )
- {
- }
+ for(;;);
}
diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h b/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
index 5840ea1..6db37cc 100644
--- a/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
+++ b/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
@@ -22,17 +22,17 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #include <stdlib.h>
- #include <stdint.h>
- #include <csi_core.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <csi_core.h>
- extern void vPortYield( void );
- #ifdef __cplusplus
- class vPortYield;
- extern "C" {
- #endif
+extern void vPortYield(void);
+#ifdef __cplusplus
+class vPortYield;
+extern "C" {
+#endif
/*-----------------------------------------------------------
@@ -46,116 +46,114 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
- typedef void (* portvectorfunc)( void );
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+typedef void (*portvectorfunc)(void);
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/* Hardware specifics. */
- #define portBYTE_ALIGNMENT 8
- #define portSTACK_GROWTH -1
- #define portMS_PERIOD_TICK 10
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH -1
+#define portMS_PERIOD_TICK 10
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- static inline void vPortEnableInterrupt( void )
- {
- __enable_irq();
- }
+static inline void vPortEnableInterrupt( void )
+{
+ __enable_irq();
+}
- static inline void vPortDisableInterrupt( void )
- {
- __disable_irq();
- }
+static inline void vPortDisableInterrupt( void )
+{
+ __disable_irq();
+}
- static inline portLONG GetCurrentPSR( void )
- {
- return __get_PSR();
- }
+static inline portLONG GetCurrentPSR (void)
+{
+ return __get_PSR();
+}
- static inline portLONG SaveLocalPSR( void )
- {
- portLONG flags = __get_PSR();
+static inline portLONG SaveLocalPSR (void)
+{
+ portLONG flags = __get_PSR();
+ __disable_irq();
+ return flags;
+}
- __disable_irq();
- return flags;
- }
+static inline void RestoreLocalPSR (portLONG newMask)
+{
+ __asm__ __volatile__(
+ "mtcr %0, psr \n"
+ :
+ :"r" (newMask)
+ :"memory"
+ );
+}
- static inline void RestoreLocalPSR( portLONG newMask )
- {
- __asm__ __volatile__ (
- "mtcr %0, psr \n"
- :
- : "r" ( newMask )
- : "memory"
- );
- }
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern __attribute__((naked)) void cpu_yeild(void);
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern __attribute__( ( naked ) ) void cpu_yeild( void );
+#define portDISABLE_INTERRUPTS() vPortDisableInterrupt()
+#define portENABLE_INTERRUPTS() vPortEnableInterrupt()
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() SaveLocalPSR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(a) RestoreLocalPSR(a)
- #define portDISABLE_INTERRUPTS() vPortDisableInterrupt()
- #define portENABLE_INTERRUPTS() vPortEnableInterrupt()
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
- #define portSET_INTERRUPT_MASK_FROM_ISR() SaveLocalPSR()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( a ) RestoreLocalPSR( a )
+#define portNOP() asm("nop")
- #define portNOP() asm ( "nop" )
+extern portLONG ulCriticalNesting;
+extern portLONG pendsvflag;
- extern portLONG ulCriticalNesting;
- extern portLONG pendsvflag;
-
- #define portYIELD() \
- if( ulCriticalNesting == 0 ) \
- { \
- vPortYield(); \
- } \
- else \
- { \
- pendsvflag = 1; \
- } \
- portNOP(); portNOP()
+#define portYIELD() if (ulCriticalNesting == 0) \
+ { \
+ vPortYield(); \
+ } \
+ else \
+ { \
+ pendsvflag = 1; \
+ } \
+ portNOP();portNOP()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { \
- if( xSwitchRequired != pdFALSE ) \
- { \
- portYIELD(); \
- } \
- } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) do { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ portYIELD(); \
+ } \
+ }while(0)
- #define portYIELD_FROM_ISR( a ) vTaskSwitchContext()
+#define portYIELD_FROM_ISR( a ) vTaskSwitchContext()
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c b/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c
index 900691c..28bf048 100644
--- a/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c
+++ b/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c
@@ -54,7 +54,8 @@
extern void __mw_run_tls_dtor();
extern void __mw_run_tls_ctor();
-extern uint32_t exc_nest_count;
+ extern uint32_t exc_nest_count;
+
/*
* Linker generated symbols to mark .tls section addresses
* first byte .. last byte
diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/port.c b/portable/ThirdParty/GCC/ARC_EM_HS/port.c
index b2e3716..360202a 100644
--- a/portable/ThirdParty/GCC/ARC_EM_HS/port.c
+++ b/portable/ThirdParty/GCC/ARC_EM_HS/port.c
@@ -41,6 +41,7 @@
volatile unsigned int ulCriticalNesting = 999UL;
volatile unsigned int context_switch_reqflg; /* task context switch request flag in exceptions and interrupts handling */
+
/**
* \var exc_nest_count
* \brief the counter for exc/int processing, =0 no int/exc
diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h b/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h
index 6b52deb..5cc3f46 100644
--- a/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h
+++ b/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h
@@ -26,16 +26,18 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
/* record stack high address for stack check */
- #ifndef configRECORD_STACK_HIGH_ADDRESS
- #define configRECORD_STACK_HIGH_ADDRESS 1
- #endif
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+ #define configRECORD_STACK_HIGH_ADDRESS 1
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -48,78 +50,78 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE unsigned int
- #define portBASE_TYPE portLONG
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE unsigned int
+#define portBASE_TYPE portLONG
- #ifndef Asm
- #define Asm __asm__ volatile
- #endif
+#ifndef Asm
+ #define Asm __asm__ volatile
+#endif
/*
* normal constants
*/
- #ifndef NULL
- #define NULL 0 /* invalid pointer */
- #endif /* NULL */
+#ifndef NULL
+ #define NULL 0 /* invalid pointer */
+#endif /* NULL */
- #ifndef true
- #define true 1 /* true */
- #endif /* true */
+#ifndef true
+ #define true 1 /* true */
+#endif /* true */
- #ifndef false
- #define false 0 /* false */
- #endif /* false */
+#ifndef false
+ #define false 0 /* false */
+#endif /* false */
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef unsigned int TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef unsigned int TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
- #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP() Asm( "nop_s" );
- #define IPM_ENABLE_ALL 1
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP() Asm( "nop_s" );
+#define IPM_ENABLE_ALL 1
- #define portYIELD_FROM_ISR() vPortYieldFromIsr()
- #define portYIELD() vPortYield()
+#define portYIELD_FROM_ISR() vPortYieldFromIsr()
+#define portYIELD() vPortYield()
/* Critical section management. */
- #define portDISABLE_INTERRUPTS() \
- { \
- Asm( "clri" ); \
- Asm( "" ::: "memory" ); \
- } \
+#define portDISABLE_INTERRUPTS() \
+ { \
+ Asm( "clri" ); \
+ Asm( "" ::: "memory" ); \
+ } \
- #define portENABLE_INTERRUPTS() \
- { \
- Asm( "" ::: "memory" ); \
- Asm( "seti" ); \
- } \
+#define portENABLE_INTERRUPTS() \
+ { \
+ Asm( "" ::: "memory" ); \
+ Asm( "seti" ); \
+ } \
- extern volatile unsigned int ulCriticalNesting;
+extern volatile unsigned int ulCriticalNesting;
- #define portENTER_CRITICAL() \
+#define portENTER_CRITICAL() \
{ \
portDISABLE_INTERRUPTS() \
ulCriticalNesting++; \
}
- #define portEXIT_CRITICAL() \
+#define portEXIT_CRITICAL() \
{ \
if( ulCriticalNesting > portNO_CRITICAL_NESTING ) \
{ \
@@ -132,24 +134,26 @@
}
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() do {} while( 0 ) /* we use the timer */
- #define portALT_GET_RUN_TIME_COUNTER_VALUE( dest ) ( dest = xTickCount )
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() do {} while( 0 ) /* we use the timer */
+#define portALT_GET_RUN_TIME_COUNTER_VALUE( dest ) ( dest = xTickCount )
- #if defined( __MW__ )
- extern void task_end_hook( void * pxTCB );
- #define portCLEAN_UP_TCB( pxTCB ) task_end_hook( ( void * ) pxTCB )
- #else
- #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB
- #endif
+#if defined( __MW__ )
+ extern void task_end_hook( void * pxTCB );
+ #define portCLEAN_UP_TCB( pxTCB ) task_end_hook( ( void * ) pxTCB )
+#else
+ #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB
+#endif
- void vPortYield( void );
- void vPortYieldFromIsr( void );
+void vPortYield( void );
+void vPortYieldFromIsr( void );
- #ifdef __cplusplus
- }
- #endif
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
#endif /* PORTMACRO_H */
diff --git a/portable/ThirdParty/GCC/ATmega/port.c b/portable/ThirdParty/GCC/ATmega/port.c
index 9b50468..e0bafd5 100644
--- a/portable/ThirdParty/GCC/ATmega/port.c
+++ b/portable/ThirdParty/GCC/ATmega/port.c
@@ -36,166 +36,165 @@
#include "task.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the AVR port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the AVR port.
+ *----------------------------------------------------------*/
/* Start tasks with interrupts enabled. */
-#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
+#define portFLAGS_INT_ENABLED ( (StackType_t) 0x80 )
-#if defined( portUSE_WDTO )
+#if defined( portUSE_WDTO)
#warning "Watchdog Timer used for scheduler."
- #define portSCHEDULER_ISR WDT_vect
+ #define portSCHEDULER_ISR WDT_vect
#elif defined( portUSE_TIMER0 )
/* Hardware constants for Timer0. */
#warning "Timer0 used for scheduler."
- #define portSCHEDULER_ISR TIMER0_COMPA_vect
- #define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) _BV( WGM01 ) )
- #define portPRESCALE_1024 ( ( uint8_t ) ( _BV( CS02 ) | _BV( CS00 ) ) )
- #define portCLOCK_PRESCALER ( ( uint32_t ) 1024 )
- #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) _BV( OCIE0A ) )
- #define portOCRL OCR0A
- #define portTCCRa TCCR0A
- #define portTCCRb TCCR0B
- #define portTIMSK TIMSK0
- #define portTIFR TIFR0
+ #define portSCHEDULER_ISR TIMER0_COMPA_vect
+ #define portCLEAR_COUNTER_ON_MATCH ( (uint8_t) _BV(WGM01) )
+ #define portPRESCALE_1024 ( (uint8_t) (_BV(CS02)|_BV(CS00)) )
+ #define portCLOCK_PRESCALER ( (uint32_t) 1024 )
+ #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( (uint8_t) _BV(OCIE0A) )
+ #define portOCRL OCR0A
+ #define portTCCRa TCCR0A
+ #define portTCCRb TCCR0B
+ #define portTIMSK TIMSK0
+ #define portTIFR TIFR0
-#endif /* if defined( portUSE_WDTO ) */
+#endif
/*-----------------------------------------------------------*/
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
/*-----------------------------------------------------------*/
/**
- * Enable the watchdog timer, configuring it for expire after
- * (value) timeout (which is a combination of the WDP0
- * through WDP3 bits).
- *
- * This function is derived from <avr/wdt.h> but enables only
- * the interrupt bit (WDIE), rather than the reset bit (WDE).
- *
- * Can't find it documented but the WDT, once enabled,
- * rolls over and fires a new interrupt each time.
- *
- * See also the symbolic constants WDTO_15MS et al.
- *
- * Updated to match avr-libc 2.0.0
- */
+ Enable the watchdog timer, configuring it for expire after
+ (value) timeout (which is a combination of the WDP0
+ through WDP3 bits).
-#if defined( portUSE_WDTO )
+ This function is derived from <avr/wdt.h> but enables only
+ the interrupt bit (WDIE), rather than the reset bit (WDE).
- static __inline__
- __attribute__( ( __always_inline__ ) )
- void wdt_interrupt_enable( const uint8_t value )
+ Can't find it documented but the WDT, once enabled,
+ rolls over and fires a new interrupt each time.
+
+ See also the symbolic constants WDTO_15MS et al.
+
+ Updated to match avr-libc 2.0.0
+*/
+
+#if defined( portUSE_WDTO)
+
+static __inline__
+__attribute__ ((__always_inline__))
+void wdt_interrupt_enable (const uint8_t value)
+{
+ if (_SFR_IO_REG_P (_WD_CONTROL_REG))
{
- if( _SFR_IO_REG_P( _WD_CONTROL_REG ) )
- {
- __asm__ __volatile__ (
+ __asm__ __volatile__ (
"in __tmp_reg__,__SREG__" "\n\t"
- "cli" "\n\t"
- "wdr" "\n\t"
- "out %0, %1" "\n\t"
- "out __SREG__,__tmp_reg__" "\n\t"
- "out %0, %2" "\n\t"
+ "cli" "\n\t"
+ "wdr" "\n\t"
+ "out %0, %1" "\n\t"
+ "out __SREG__,__tmp_reg__" "\n\t"
+ "out %0, %2" "\n\t"
: /* no outputs */
- : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ),
- "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
- "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
- _BV( WDIF ) | _BV( WDIE ) | ( value & 0x07 ) ) )
+ : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
+ "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+ "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+ _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
: "r0"
- );
- }
- else
- {
- __asm__ __volatile__ (
- "in __tmp_reg__,__SREG__" "\n\t"
- "cli" "\n\t"
- "wdr" "\n\t"
- "sts %0, %1" "\n\t"
- "out __SREG__,__tmp_reg__" "\n\t"
- "sts %0, %2" "\n\t"
- : /* no outputs */
- : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ),
- "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
- "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
- _BV( WDIF ) | _BV( WDIE ) | ( value & 0x07 ) ) )
- : "r0"
- );
- }
+ );
}
-#endif /* if defined( portUSE_WDTO ) */
+ else
+ {
+ __asm__ __volatile__ (
+ "in __tmp_reg__,__SREG__" "\n\t"
+ "cli" "\n\t"
+ "wdr" "\n\t"
+ "sts %0, %1" "\n\t"
+ "out __SREG__,__tmp_reg__" "\n\t"
+ "sts %0, %2" "\n\t"
+ : /* no outputs */
+ : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
+ "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+ "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+ _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
+ : "r0"
+ );
+ }
+}
+#endif
/*-----------------------------------------------------------*/
-
/**
- * Enable the watchdog timer, configuring it for expire after
- * (value) timeout (which is a combination of the WDP0
- * through WDP3 bits).
- *
- * This function is derived from <avr/wdt.h> but enables both
- * the reset bit (WDE), and the interrupt bit (WDIE).
- *
- * This will ensure that if the interrupt is not serviced
- * before the second timeout, the AVR will reset.
- *
- * Servicing the interrupt automatically clears it,
- * and ensures the AVR does not reset.
- *
- * Can't find it documented but the WDT, once enabled,
- * rolls over and fires a new interrupt each time.
- *
- * See also the symbolic constants WDTO_15MS et al.
- *
- * Updated to match avr-libc 2.0.0
- */
+ Enable the watchdog timer, configuring it for expire after
+ (value) timeout (which is a combination of the WDP0
+ through WDP3 bits).
-#if defined( portUSE_WDTO )
+ This function is derived from <avr/wdt.h> but enables both
+ the reset bit (WDE), and the interrupt bit (WDIE).
- static __inline__
- __attribute__( ( __always_inline__ ) )
- void wdt_interrupt_reset_enable( const uint8_t value )
+ This will ensure that if the interrupt is not serviced
+ before the second timeout, the AVR will reset.
+
+ Servicing the interrupt automatically clears it,
+ and ensures the AVR does not reset.
+
+ Can't find it documented but the WDT, once enabled,
+ rolls over and fires a new interrupt each time.
+
+ See also the symbolic constants WDTO_15MS et al.
+
+ Updated to match avr-libc 2.0.0
+*/
+
+#if defined( portUSE_WDTO)
+
+static __inline__
+__attribute__ ((__always_inline__))
+void wdt_interrupt_reset_enable (const uint8_t value)
+{
+ if (_SFR_IO_REG_P (_WD_CONTROL_REG))
{
- if( _SFR_IO_REG_P( _WD_CONTROL_REG ) )
- {
- __asm__ __volatile__ (
+ __asm__ __volatile__ (
"in __tmp_reg__,__SREG__" "\n\t"
- "cli" "\n\t"
- "wdr" "\n\t"
- "out %0, %1" "\n\t"
- "out __SREG__,__tmp_reg__" "\n\t"
- "out %0, %2" "\n\t"
+ "cli" "\n\t"
+ "wdr" "\n\t"
+ "out %0, %1" "\n\t"
+ "out __SREG__,__tmp_reg__" "\n\t"
+ "out %0, %2" "\n\t"
: /* no outputs */
- : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ),
- "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
- "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
- _BV( WDIF ) | _BV( WDIE ) | _BV( WDE ) | ( value & 0x07 ) ) )
+ : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
+ "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+ "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+ _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
: "r0"
- );
- }
- else
- {
- __asm__ __volatile__ (
- "in __tmp_reg__,__SREG__" "\n\t"
- "cli" "\n\t"
- "wdr" "\n\t"
- "sts %0, %1" "\n\t"
- "out __SREG__,__tmp_reg__" "\n\t"
- "sts %0, %2" "\n\t"
- : /* no outputs */
- : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ),
- "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
- "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
- _BV( WDIF ) | _BV( WDIE ) | _BV( WDE ) | ( value & 0x07 ) ) )
- : "r0"
- );
- }
+ );
}
-#endif /* if defined( portUSE_WDTO ) */
+ else
+ {
+ __asm__ __volatile__ (
+ "in __tmp_reg__,__SREG__" "\n\t"
+ "cli" "\n\t"
+ "wdr" "\n\t"
+ "sts %0, %1" "\n\t"
+ "out __SREG__,__tmp_reg__" "\n\t"
+ "sts %0, %2" "\n\t"
+ : /* no outputs */
+ : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
+ "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+ "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+ _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
+ : "r0"
+ );
+ }
+}
+#endif
/*-----------------------------------------------------------*/
@@ -224,295 +223,295 @@
* The interrupts will have been disabled during the call to portSAVE_CONTEXT()
* so we need not worry about reading/writing to the stack pointer.
*/
-#if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ )
+#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
/* 3-Byte PC Save with RAMPZ */
- #define portSAVE_CONTEXT() \
- __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
- "in __tmp_reg__, __SREG__ \n\t" \
- "cli \n\t" \
- "push __tmp_reg__ \n\t" \
- "in __tmp_reg__, 0x3B \n\t" \
- "push __tmp_reg__ \n\t" \
- "in __tmp_reg__, 0x3C \n\t" \
- "push __tmp_reg__ \n\t" \
- "push __zero_reg__ \n\t" \
- "clr __zero_reg__ \n\t" \
- "push r2 \n\t" \
- "push r3 \n\t" \
- "push r4 \n\t" \
- "push r5 \n\t" \
- "push r6 \n\t" \
- "push r7 \n\t" \
- "push r8 \n\t" \
- "push r9 \n\t" \
- "push r10 \n\t" \
- "push r11 \n\t" \
- "push r12 \n\t" \
- "push r13 \n\t" \
- "push r14 \n\t" \
- "push r15 \n\t" \
- "push r16 \n\t" \
- "push r17 \n\t" \
- "push r18 \n\t" \
- "push r19 \n\t" \
- "push r20 \n\t" \
- "push r21 \n\t" \
- "push r22 \n\t" \
- "push r23 \n\t" \
- "push r24 \n\t" \
- "push r25 \n\t" \
- "push r26 \n\t" \
- "push r27 \n\t" \
- "push r28 \n\t" \
- "push r29 \n\t" \
- "push r30 \n\t" \
- "push r31 \n\t" \
- "lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "in __tmp_reg__, __SP_L__ \n\t" \
- "st x+, __tmp_reg__ \n\t" \
- "in __tmp_reg__, __SP_H__ \n\t" \
- "st x+, __tmp_reg__ \n\t" \
- );
-#elif defined( __AVR_HAVE_RAMPZ__ )
+#define portSAVE_CONTEXT() \
+ __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
+ "in __tmp_reg__, __SREG__ \n\t" \
+ "cli \n\t" \
+ "push __tmp_reg__ \n\t" \
+ "in __tmp_reg__, 0x3B \n\t" \
+ "push __tmp_reg__ \n\t" \
+ "in __tmp_reg__, 0x3C \n\t" \
+ "push __tmp_reg__ \n\t" \
+ "push __zero_reg__ \n\t" \
+ "clr __zero_reg__ \n\t" \
+ "push r2 \n\t" \
+ "push r3 \n\t" \
+ "push r4 \n\t" \
+ "push r5 \n\t" \
+ "push r6 \n\t" \
+ "push r7 \n\t" \
+ "push r8 \n\t" \
+ "push r9 \n\t" \
+ "push r10 \n\t" \
+ "push r11 \n\t" \
+ "push r12 \n\t" \
+ "push r13 \n\t" \
+ "push r14 \n\t" \
+ "push r15 \n\t" \
+ "push r16 \n\t" \
+ "push r17 \n\t" \
+ "push r18 \n\t" \
+ "push r19 \n\t" \
+ "push r20 \n\t" \
+ "push r21 \n\t" \
+ "push r22 \n\t" \
+ "push r23 \n\t" \
+ "push r24 \n\t" \
+ "push r25 \n\t" \
+ "push r26 \n\t" \
+ "push r27 \n\t" \
+ "push r28 \n\t" \
+ "push r29 \n\t" \
+ "push r30 \n\t" \
+ "push r31 \n\t" \
+ "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "in __tmp_reg__, __SP_L__ \n\t" \
+ "st x+, __tmp_reg__ \n\t" \
+ "in __tmp_reg__, __SP_H__ \n\t" \
+ "st x+, __tmp_reg__ \n\t" \
+ );
+#elif defined(__AVR_HAVE_RAMPZ__)
/* 2-Byte PC Save with RAMPZ */
- #define portSAVE_CONTEXT() \
- __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
- "in __tmp_reg__, __SREG__ \n\t" \
- "cli \n\t" \
- "push __tmp_reg__ \n\t" \
- "in __tmp_reg__, 0x3B \n\t" \
- "push __tmp_reg__ \n\t" \
- "push __zero_reg__ \n\t" \
- "clr __zero_reg__ \n\t" \
- "push r2 \n\t" \
- "push r3 \n\t" \
- "push r4 \n\t" \
- "push r5 \n\t" \
- "push r6 \n\t" \
- "push r7 \n\t" \
- "push r8 \n\t" \
- "push r9 \n\t" \
- "push r10 \n\t" \
- "push r11 \n\t" \
- "push r12 \n\t" \
- "push r13 \n\t" \
- "push r14 \n\t" \
- "push r15 \n\t" \
- "push r16 \n\t" \
- "push r17 \n\t" \
- "push r18 \n\t" \
- "push r19 \n\t" \
- "push r20 \n\t" \
- "push r21 \n\t" \
- "push r22 \n\t" \
- "push r23 \n\t" \
- "push r24 \n\t" \
- "push r25 \n\t" \
- "push r26 \n\t" \
- "push r27 \n\t" \
- "push r28 \n\t" \
- "push r29 \n\t" \
- "push r30 \n\t" \
- "push r31 \n\t" \
- "lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "in __tmp_reg__, __SP_L__ \n\t" \
- "st x+, __tmp_reg__ \n\t" \
- "in __tmp_reg__, __SP_H__ \n\t" \
- "st x+, __tmp_reg__ \n\t" \
- );
-#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
+#define portSAVE_CONTEXT() \
+ __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
+ "in __tmp_reg__, __SREG__ \n\t" \
+ "cli \n\t" \
+ "push __tmp_reg__ \n\t" \
+ "in __tmp_reg__, 0x3B \n\t" \
+ "push __tmp_reg__ \n\t" \
+ "push __zero_reg__ \n\t" \
+ "clr __zero_reg__ \n\t" \
+ "push r2 \n\t" \
+ "push r3 \n\t" \
+ "push r4 \n\t" \
+ "push r5 \n\t" \
+ "push r6 \n\t" \
+ "push r7 \n\t" \
+ "push r8 \n\t" \
+ "push r9 \n\t" \
+ "push r10 \n\t" \
+ "push r11 \n\t" \
+ "push r12 \n\t" \
+ "push r13 \n\t" \
+ "push r14 \n\t" \
+ "push r15 \n\t" \
+ "push r16 \n\t" \
+ "push r17 \n\t" \
+ "push r18 \n\t" \
+ "push r19 \n\t" \
+ "push r20 \n\t" \
+ "push r21 \n\t" \
+ "push r22 \n\t" \
+ "push r23 \n\t" \
+ "push r24 \n\t" \
+ "push r25 \n\t" \
+ "push r26 \n\t" \
+ "push r27 \n\t" \
+ "push r28 \n\t" \
+ "push r29 \n\t" \
+ "push r30 \n\t" \
+ "push r31 \n\t" \
+ "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "in __tmp_reg__, __SP_L__ \n\t" \
+ "st x+, __tmp_reg__ \n\t" \
+ "in __tmp_reg__, __SP_H__ \n\t" \
+ "st x+, __tmp_reg__ \n\t" \
+ );
+#else
/* 2-Byte PC Save */
- #define portSAVE_CONTEXT() \
- __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
- "in __tmp_reg__, __SREG__ \n\t" \
- "cli \n\t" \
- "push __tmp_reg__ \n\t" \
- "push __zero_reg__ \n\t" \
- "clr __zero_reg__ \n\t" \
- "push r2 \n\t" \
- "push r3 \n\t" \
- "push r4 \n\t" \
- "push r5 \n\t" \
- "push r6 \n\t" \
- "push r7 \n\t" \
- "push r8 \n\t" \
- "push r9 \n\t" \
- "push r10 \n\t" \
- "push r11 \n\t" \
- "push r12 \n\t" \
- "push r13 \n\t" \
- "push r14 \n\t" \
- "push r15 \n\t" \
- "push r16 \n\t" \
- "push r17 \n\t" \
- "push r18 \n\t" \
- "push r19 \n\t" \
- "push r20 \n\t" \
- "push r21 \n\t" \
- "push r22 \n\t" \
- "push r23 \n\t" \
- "push r24 \n\t" \
- "push r25 \n\t" \
- "push r26 \n\t" \
- "push r27 \n\t" \
- "push r28 \n\t" \
- "push r29 \n\t" \
- "push r30 \n\t" \
- "push r31 \n\t" \
- "lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "in __tmp_reg__, __SP_L__ \n\t" \
- "st x+, __tmp_reg__ \n\t" \
- "in __tmp_reg__, __SP_H__ \n\t" \
- "st x+, __tmp_reg__ \n\t" \
- );
-#endif /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
+#define portSAVE_CONTEXT() \
+ __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
+ "in __tmp_reg__, __SREG__ \n\t" \
+ "cli \n\t" \
+ "push __tmp_reg__ \n\t" \
+ "push __zero_reg__ \n\t" \
+ "clr __zero_reg__ \n\t" \
+ "push r2 \n\t" \
+ "push r3 \n\t" \
+ "push r4 \n\t" \
+ "push r5 \n\t" \
+ "push r6 \n\t" \
+ "push r7 \n\t" \
+ "push r8 \n\t" \
+ "push r9 \n\t" \
+ "push r10 \n\t" \
+ "push r11 \n\t" \
+ "push r12 \n\t" \
+ "push r13 \n\t" \
+ "push r14 \n\t" \
+ "push r15 \n\t" \
+ "push r16 \n\t" \
+ "push r17 \n\t" \
+ "push r18 \n\t" \
+ "push r19 \n\t" \
+ "push r20 \n\t" \
+ "push r21 \n\t" \
+ "push r22 \n\t" \
+ "push r23 \n\t" \
+ "push r24 \n\t" \
+ "push r25 \n\t" \
+ "push r26 \n\t" \
+ "push r27 \n\t" \
+ "push r28 \n\t" \
+ "push r29 \n\t" \
+ "push r30 \n\t" \
+ "push r31 \n\t" \
+ "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "in __tmp_reg__, __SP_L__ \n\t" \
+ "st x+, __tmp_reg__ \n\t" \
+ "in __tmp_reg__, __SP_H__ \n\t" \
+ "st x+, __tmp_reg__ \n\t" \
+ );
+#endif
/*
* Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during
* the context save so we can write to the stack pointer.
*/
-#if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ )
+#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
/* 3-Byte PC Restore with RAMPZ */
- #define portRESTORE_CONTEXT() \
- __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "ld r28, x+ \n\t" \
- "out __SP_L__, r28 \n\t" \
- "ld r29, x+ \n\t" \
- "out __SP_H__, r29 \n\t" \
- "pop r31 \n\t" \
- "pop r30 \n\t" \
- "pop r29 \n\t" \
- "pop r28 \n\t" \
- "pop r27 \n\t" \
- "pop r26 \n\t" \
- "pop r25 \n\t" \
- "pop r24 \n\t" \
- "pop r23 \n\t" \
- "pop r22 \n\t" \
- "pop r21 \n\t" \
- "pop r20 \n\t" \
- "pop r19 \n\t" \
- "pop r18 \n\t" \
- "pop r17 \n\t" \
- "pop r16 \n\t" \
- "pop r15 \n\t" \
- "pop r14 \n\t" \
- "pop r13 \n\t" \
- "pop r12 \n\t" \
- "pop r11 \n\t" \
- "pop r10 \n\t" \
- "pop r9 \n\t" \
- "pop r8 \n\t" \
- "pop r7 \n\t" \
- "pop r6 \n\t" \
- "pop r5 \n\t" \
- "pop r4 \n\t" \
- "pop r3 \n\t" \
- "pop r2 \n\t" \
- "pop __zero_reg__ \n\t" \
- "pop __tmp_reg__ \n\t" \
- "out 0x3C, __tmp_reg__ \n\t" \
- "pop __tmp_reg__ \n\t" \
- "out 0x3B, __tmp_reg__ \n\t" \
- "pop __tmp_reg__ \n\t" \
- "out __SREG__, __tmp_reg__ \n\t" \
- "pop __tmp_reg__ \n\t" \
- );
-#elif defined( __AVR_HAVE_RAMPZ__ )
+#define portRESTORE_CONTEXT() \
+ __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "ld r28, x+ \n\t" \
+ "out __SP_L__, r28 \n\t" \
+ "ld r29, x+ \n\t" \
+ "out __SP_H__, r29 \n\t" \
+ "pop r31 \n\t" \
+ "pop r30 \n\t" \
+ "pop r29 \n\t" \
+ "pop r28 \n\t" \
+ "pop r27 \n\t" \
+ "pop r26 \n\t" \
+ "pop r25 \n\t" \
+ "pop r24 \n\t" \
+ "pop r23 \n\t" \
+ "pop r22 \n\t" \
+ "pop r21 \n\t" \
+ "pop r20 \n\t" \
+ "pop r19 \n\t" \
+ "pop r18 \n\t" \
+ "pop r17 \n\t" \
+ "pop r16 \n\t" \
+ "pop r15 \n\t" \
+ "pop r14 \n\t" \
+ "pop r13 \n\t" \
+ "pop r12 \n\t" \
+ "pop r11 \n\t" \
+ "pop r10 \n\t" \
+ "pop r9 \n\t" \
+ "pop r8 \n\t" \
+ "pop r7 \n\t" \
+ "pop r6 \n\t" \
+ "pop r5 \n\t" \
+ "pop r4 \n\t" \
+ "pop r3 \n\t" \
+ "pop r2 \n\t" \
+ "pop __zero_reg__ \n\t" \
+ "pop __tmp_reg__ \n\t" \
+ "out 0x3C, __tmp_reg__ \n\t" \
+ "pop __tmp_reg__ \n\t" \
+ "out 0x3B, __tmp_reg__ \n\t" \
+ "pop __tmp_reg__ \n\t" \
+ "out __SREG__, __tmp_reg__ \n\t" \
+ "pop __tmp_reg__ \n\t" \
+ );
+#elif defined(__AVR_HAVE_RAMPZ__)
/* 2-Byte PC Restore with RAMPZ */
- #define portRESTORE_CONTEXT() \
- __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "ld r28, x+ \n\t" \
- "out __SP_L__, r28 \n\t" \
- "ld r29, x+ \n\t" \
- "out __SP_H__, r29 \n\t" \
- "pop r31 \n\t" \
- "pop r30 \n\t" \
- "pop r29 \n\t" \
- "pop r28 \n\t" \
- "pop r27 \n\t" \
- "pop r26 \n\t" \
- "pop r25 \n\t" \
- "pop r24 \n\t" \
- "pop r23 \n\t" \
- "pop r22 \n\t" \
- "pop r21 \n\t" \
- "pop r20 \n\t" \
- "pop r19 \n\t" \
- "pop r18 \n\t" \
- "pop r17 \n\t" \
- "pop r16 \n\t" \
- "pop r15 \n\t" \
- "pop r14 \n\t" \
- "pop r13 \n\t" \
- "pop r12 \n\t" \
- "pop r11 \n\t" \
- "pop r10 \n\t" \
- "pop r9 \n\t" \
- "pop r8 \n\t" \
- "pop r7 \n\t" \
- "pop r6 \n\t" \
- "pop r5 \n\t" \
- "pop r4 \n\t" \
- "pop r3 \n\t" \
- "pop r2 \n\t" \
- "pop __zero_reg__ \n\t" \
- "pop __tmp_reg__ \n\t" \
- "out 0x3B, __tmp_reg__ \n\t" \
- "pop __tmp_reg__ \n\t" \
- "out __SREG__, __tmp_reg__ \n\t" \
- "pop __tmp_reg__ \n\t" \
- );
-#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
+#define portRESTORE_CONTEXT() \
+ __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "ld r28, x+ \n\t" \
+ "out __SP_L__, r28 \n\t" \
+ "ld r29, x+ \n\t" \
+ "out __SP_H__, r29 \n\t" \
+ "pop r31 \n\t" \
+ "pop r30 \n\t" \
+ "pop r29 \n\t" \
+ "pop r28 \n\t" \
+ "pop r27 \n\t" \
+ "pop r26 \n\t" \
+ "pop r25 \n\t" \
+ "pop r24 \n\t" \
+ "pop r23 \n\t" \
+ "pop r22 \n\t" \
+ "pop r21 \n\t" \
+ "pop r20 \n\t" \
+ "pop r19 \n\t" \
+ "pop r18 \n\t" \
+ "pop r17 \n\t" \
+ "pop r16 \n\t" \
+ "pop r15 \n\t" \
+ "pop r14 \n\t" \
+ "pop r13 \n\t" \
+ "pop r12 \n\t" \
+ "pop r11 \n\t" \
+ "pop r10 \n\t" \
+ "pop r9 \n\t" \
+ "pop r8 \n\t" \
+ "pop r7 \n\t" \
+ "pop r6 \n\t" \
+ "pop r5 \n\t" \
+ "pop r4 \n\t" \
+ "pop r3 \n\t" \
+ "pop r2 \n\t" \
+ "pop __zero_reg__ \n\t" \
+ "pop __tmp_reg__ \n\t" \
+ "out 0x3B, __tmp_reg__ \n\t" \
+ "pop __tmp_reg__ \n\t" \
+ "out __SREG__, __tmp_reg__ \n\t" \
+ "pop __tmp_reg__ \n\t" \
+ );
+#else
/* 2-Byte PC Restore */
- #define portRESTORE_CONTEXT() \
- __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "ld r28, x+ \n\t" \
- "out __SP_L__, r28 \n\t" \
- "ld r29, x+ \n\t" \
- "out __SP_H__, r29 \n\t" \
- "pop r31 \n\t" \
- "pop r30 \n\t" \
- "pop r29 \n\t" \
- "pop r28 \n\t" \
- "pop r27 \n\t" \
- "pop r26 \n\t" \
- "pop r25 \n\t" \
- "pop r24 \n\t" \
- "pop r23 \n\t" \
- "pop r22 \n\t" \
- "pop r21 \n\t" \
- "pop r20 \n\t" \
- "pop r19 \n\t" \
- "pop r18 \n\t" \
- "pop r17 \n\t" \
- "pop r16 \n\t" \
- "pop r15 \n\t" \
- "pop r14 \n\t" \
- "pop r13 \n\t" \
- "pop r12 \n\t" \
- "pop r11 \n\t" \
- "pop r10 \n\t" \
- "pop r9 \n\t" \
- "pop r8 \n\t" \
- "pop r7 \n\t" \
- "pop r6 \n\t" \
- "pop r5 \n\t" \
- "pop r4 \n\t" \
- "pop r3 \n\t" \
- "pop r2 \n\t" \
- "pop __zero_reg__ \n\t" \
- "pop __tmp_reg__ \n\t" \
- "out __SREG__, __tmp_reg__ \n\t" \
- "pop __tmp_reg__ \n\t" \
- );
-#endif /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
+#define portRESTORE_CONTEXT() \
+ __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "ld r28, x+ \n\t" \
+ "out __SP_L__, r28 \n\t" \
+ "ld r29, x+ \n\t" \
+ "out __SP_H__, r29 \n\t" \
+ "pop r31 \n\t" \
+ "pop r30 \n\t" \
+ "pop r29 \n\t" \
+ "pop r28 \n\t" \
+ "pop r27 \n\t" \
+ "pop r26 \n\t" \
+ "pop r25 \n\t" \
+ "pop r24 \n\t" \
+ "pop r23 \n\t" \
+ "pop r22 \n\t" \
+ "pop r21 \n\t" \
+ "pop r20 \n\t" \
+ "pop r19 \n\t" \
+ "pop r18 \n\t" \
+ "pop r17 \n\t" \
+ "pop r16 \n\t" \
+ "pop r15 \n\t" \
+ "pop r14 \n\t" \
+ "pop r13 \n\t" \
+ "pop r12 \n\t" \
+ "pop r11 \n\t" \
+ "pop r10 \n\t" \
+ "pop r9 \n\t" \
+ "pop r8 \n\t" \
+ "pop r7 \n\t" \
+ "pop r6 \n\t" \
+ "pop r5 \n\t" \
+ "pop r4 \n\t" \
+ "pop r3 \n\t" \
+ "pop r2 \n\t" \
+ "pop __zero_reg__ \n\t" \
+ "pop __tmp_reg__ \n\t" \
+ "out __SREG__, __tmp_reg__ \n\t" \
+ "pop __tmp_reg__ \n\t" \
+ );
+#endif
/*-----------------------------------------------------------*/
/*
@@ -524,17 +523,14 @@
/*
* See header file for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint16_t usAddress;
-
+uint16_t usAddress;
/* Simulate how the stack would look after a call to vPortYield() generated by
- * the compiler. */
+ the compiler. */
/* The start of the task code will be popped off the stack last, so place
- * it on first. */
+ it on first. */
usAddress = ( uint16_t ) pxCode;
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
@@ -543,51 +539,48 @@
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
- #if defined( __AVR_3_BYTE_PC__ )
-
- /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit
- * program counter. When a code address is stored on the stack, it takes 3 bytes
- * instead of 2 for the other ATmega* chips.
- *
- * Store 0 as the top byte since we force all task routines to the bottom 128K
- * of flash. We do this by using the .lowtext label in the linker script.
- *
- * In order to do this properly, we would need to get a full 3-byte pointer to
- * pxCode. That requires a change to GCC. Not likely to happen any time soon.
- */
- *pxTopOfStack = 0;
- pxTopOfStack--;
- #endif
+#if defined(__AVR_3_BYTE_PC__)
+ /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit
+ * program counter. When a code address is stored on the stack, it takes 3 bytes
+ * instead of 2 for the other ATmega* chips.
+ *
+ * Store 0 as the top byte since we force all task routines to the bottom 128K
+ * of flash. We do this by using the .lowtext label in the linker script.
+ *
+ * In order to do this properly, we would need to get a full 3-byte pointer to
+ * pxCode. That requires a change to GCC. Not likely to happen any time soon.
+ */
+ *pxTopOfStack = 0;
+ pxTopOfStack--;
+#endif
/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
- * portSAVE_CONTEXT places the flags on the stack immediately after r0
- * to ensure the interrupts get disabled as soon as possible, and so ensuring
- * the stack use is minimal should a context switch interrupt occur. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+ portSAVE_CONTEXT places the flags on the stack immediately after r0
+ to ensure the interrupts get disabled as soon as possible, and so ensuring
+ the stack use is minimal should a context switch interrupt occur. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
pxTopOfStack--;
- #if defined( __AVR_3_BYTE_PC__ )
+#if defined(__AVR_3_BYTE_PC__)
+ /* If we have an ATmega256x, we are also saving the EIND register.
+ * We should default to 0.
+ */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* EIND */
+ pxTopOfStack--;
+#endif
- /* If we have an ATmega256x, we are also saving the EIND register.
- * We should default to 0.
- */
- *pxTopOfStack = ( StackType_t ) 0x00; /* EIND */
- pxTopOfStack--;
- #endif
-
- #if defined( __AVR_HAVE_RAMPZ__ )
-
- /* We are saving the RAMPZ register.
- * We should default to 0.
- */
- *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
- pxTopOfStack--;
- #endif
+#if defined(__AVR_HAVE_RAMPZ__)
+ /* We are saving the RAMPZ register.
+ * We should default to 0.
+ */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
+ pxTopOfStack--;
+#endif
/* Now the remaining registers. The compiler expects R1 to be 0. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
/* Leave R2 - R23 untouched */
pxTopOfStack -= 23;
@@ -616,7 +609,7 @@
portRESTORE_CONTEXT();
/* Simulate a function call end as generated by the compiler. We will now
- * jump to the start of the task the context of which we have just restored. */
+ jump to the start of the task the context of which we have just restored. */
__asm__ __volatile__ ( "ret" );
/* Should not get here. */
@@ -626,7 +619,7 @@
void vPortEndScheduler( void )
{
- /* It is unlikely that the ATmega port will get stopped. */
+ /* It is unlikely that the ATmega port will get stopped. */
}
/*-----------------------------------------------------------*/
@@ -634,7 +627,7 @@
* Manual context switch. The first thing we do is save the registers so we
* can use a naked attribute.
*/
-void vPortYield( void ) __attribute__( ( hot, flatten, naked ) );
+void vPortYield( void ) __attribute__ ( ( hot, flatten, naked ) );
void vPortYield( void )
{
portSAVE_CONTEXT();
@@ -649,8 +642,8 @@
* Manual context switch callable from ISRs. The first thing we do is save
* the registers so we can use a naked attribute.
*/
-void vPortYieldFromISR( void ) __attribute__( ( hot, flatten, naked ) );
-void vPortYieldFromISR( void )
+void vPortYieldFromISR(void) __attribute__ ( ( hot, flatten, naked ) );
+void vPortYieldFromISR(void)
{
portSAVE_CONTEXT();
vTaskSwitchContext();
@@ -666,111 +659,107 @@
* difference from vPortYield() is the tick count is incremented as the
* call comes from the tick ISR.
*/
-void vPortYieldFromTick( void ) __attribute__( ( hot, flatten, naked ) );
+void vPortYieldFromTick( void ) __attribute__ ( ( hot, flatten, naked ) );
void vPortYieldFromTick( void )
{
portSAVE_CONTEXT();
-
if( xTaskIncrementTick() != pdFALSE )
{
vTaskSwitchContext();
}
-
portRESTORE_CONTEXT();
__asm__ __volatile__ ( "ret" );
}
/*-----------------------------------------------------------*/
-#if defined( portUSE_WDTO )
-
+#if defined(portUSE_WDTO)
/*
* Setup WDT to generate a tick interrupt.
*/
- void prvSetupTimerInterrupt( void )
- {
- /* reset watchdog */
- wdt_reset();
+void prvSetupTimerInterrupt( void )
+{
+ /* reset watchdog */
+ wdt_reset();
- /* set up WDT Interrupt (rather than the WDT Reset). */
- wdt_interrupt_enable( portUSE_WDTO );
- }
+ /* set up WDT Interrupt (rather than the WDT Reset). */
+ wdt_interrupt_enable( portUSE_WDTO );
+}
-#elif defined( portUSE_TIMER0 )
-
+#elif defined (portUSE_TIMER0)
/*
* Setup Timer0 compare match A to generate a tick interrupt.
*/
- static void prvSetupTimerInterrupt( void )
- {
- uint32_t ulCompareMatch;
- uint8_t ucLowByte;
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+uint8_t ucLowByte;
- /* Using 8bit Timer0 to generate the tick. Correct fuses must be
- * selected for the configCPU_CLOCK_HZ clock.*/
+ /* Using 8bit Timer0 to generate the tick. Correct fuses must be
+ selected for the configCPU_CLOCK_HZ clock.*/
- ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
- /* We only have 8 bits so have to scale 1024 to get our required tick rate. */
- ulCompareMatch /= portCLOCK_PRESCALER;
+ /* We only have 8 bits so have to scale 1024 to get our required tick rate. */
+ ulCompareMatch /= portCLOCK_PRESCALER;
- /* Adjust for correct value. */
- ulCompareMatch -= ( uint32_t ) 1;
+ /* Adjust for correct value. */
+ ulCompareMatch -= ( uint32_t ) 1;
- /* Setup compare match value for compare match A. Interrupts are disabled
- * before this is called so we need not worry here. */
- ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
- portOCRL = ucLowByte;
+ /* Setup compare match value for compare match A. Interrupts are disabled
+ before this is called so we need not worry here. */
+ ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+ portOCRL = ucLowByte;
- /* Setup clock source and compare match behaviour. */
- portTCCRa = portCLEAR_COUNTER_ON_MATCH;
- portTCCRb = portPRESCALE_1024;
+ /* Setup clock source and compare match behaviour. */
+ portTCCRa = portCLEAR_COUNTER_ON_MATCH;
+ portTCCRb = portPRESCALE_1024;
- /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */
- ucLowByte = portTIMSK;
- ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
- portTIMSK = ucLowByte;
- }
+ /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */
+ ucLowByte = portTIMSK;
+ ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+ portTIMSK = ucLowByte;
+}
-#endif /* if defined( portUSE_WDTO ) */
+#endif
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 1
-/*
- * Tick ISR for preemptive scheduler. We can use a naked attribute as
- * the context is saved at the start of vPortYieldFromTick(). The tick
- * count is incremented after the context is saved.
- *
- * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
- *
- */
- ISR( portSCHEDULER_ISR, ISR_NAKED ) __attribute__( ( hot, flatten ) );
-
+ /*
+ * Tick ISR for preemptive scheduler. We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick(). The tick
+ * count is incremented after the context is saved.
+ *
+ * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
+ *
+ */
+ ISR(portSCHEDULER_ISR, ISR_NAKED) __attribute__ ((hot, flatten));
/* ISR(portSCHEDULER_ISR, ISR_NAKED ISR_NOBLOCK) __attribute__ ((hot, flatten));
*/
- ISR( portSCHEDULER_ISR )
+ ISR(portSCHEDULER_ISR)
{
vPortYieldFromTick();
__asm__ __volatile__ ( "reti" );
}
-#else /* if configUSE_PREEMPTION == 1 */
+#else
-/*
- * Tick ISR for the cooperative scheduler. All this does is increment the
- * tick count. We don't need to switch context, this can only be done by
- * manual calls to taskYIELD();
- *
- * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
- */
- ISR( portSCHEDULER_ISR ) __attribute__( ( hot, flatten ) );
-
+ /*
+ * Tick ISR for the cooperative scheduler. All this does is increment the
+ * tick count. We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ *
+ * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
+ */
+ ISR(portSCHEDULER_ISR) __attribute__ ((hot, flatten));
/* ISR(portSCHEDULER_ISR, ISR_NOBLOCK) __attribute__ ((hot, flatten));
*/
- ISR( portSCHEDULER_ISR )
+ ISR(portSCHEDULER_ISR)
{
xTaskIncrementTick();
}
-#endif /* if configUSE_PREEMPTION == 1 */
+#endif
+
+
diff --git a/portable/ThirdParty/GCC/ATmega/portmacro.h b/portable/ThirdParty/GCC/ATmega/portmacro.h
index ab3dc1f..b6b5128 100644
--- a/portable/ThirdParty/GCC/ATmega/portmacro.h
+++ b/portable/ThirdParty/GCC/ATmega/portmacro.h
@@ -23,14 +23,14 @@
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
- */
+*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -42,49 +42,47 @@
*-----------------------------------------------------------
*/
- #include <avr/wdt.h>
+#include <avr/wdt.h>
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT int
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
- typedef uint8_t StackType_t;
- typedef int8_t BaseType_t;
- typedef uint8_t UBaseType_t;
+typedef uint8_t StackType_t;
+typedef int8_t BaseType_t;
+typedef uint8_t UBaseType_t;
- #if configUSE_16_BIT_TICKS == 1
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if configUSE_16_BIT_TICKS == 1
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Critical section management. */
- #define portENTER_CRITICAL() \
- __asm__ __volatile__ ( \
- "in __tmp_reg__, __SREG__" "\n\t" \
- "cli" "\n\t" \
- "push __tmp_reg__" "\n\t" \
- ::: "memory" \
- )
+#define portENTER_CRITICAL() __asm__ __volatile__ ( \
+ "in __tmp_reg__, __SREG__" "\n\t" \
+ "cli" "\n\t" \
+ "push __tmp_reg__" "\n\t" \
+ ::: "memory" \
+ )
- #define portEXIT_CRITICAL() \
- __asm__ __volatile__ ( \
- "pop __tmp_reg__" "\n\t" \
- "out __SREG__, __tmp_reg__" "\n\t" \
- ::: "memory" \
- )
+#define portEXIT_CRITICAL() __asm__ __volatile__ ( \
+ "pop __tmp_reg__" "\n\t" \
+ "out __SREG__, __tmp_reg__" "\n\t" \
+ ::: "memory" \
+ )
- #define portDISABLE_INTERRUPTS() __asm__ __volatile__ ( "cli" ::: "memory" )
- #define portENABLE_INTERRUPTS() __asm__ __volatile__ ( "sei" ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm__ __volatile__ ( "cli" ::: "memory")
+#define portENABLE_INTERRUPTS() __asm__ __volatile__ ( "sei" ::: "memory")
/*-----------------------------------------------------------*/
/* Architecture specifics. */
@@ -93,66 +91,66 @@
* Prefer to use the enhanced Watchdog Timer, but also Timer0 is ok.
*/
- #if defined( WDIE ) && defined( WDIF ) /* If Enhanced WDT with interrupt capability is available */
+#if defined(WDIE) && defined(WDIF) /* If Enhanced WDT with interrupt capability is available */
- #define portUSE_WDTO WDTO_15MS /* use the Watchdog Timer for xTaskIncrementTick */
+#define portUSE_WDTO WDTO_15MS /* use the Watchdog Timer for xTaskIncrementTick */
/* Watchdog period options: WDTO_15MS
- * WDTO_30MS
- * WDTO_60MS
- * WDTO_120MS
- * WDTO_250MS
- * WDTO_500MS
- * WDTO_1S
- * WDTO_2S
- */
+ WDTO_30MS
+ WDTO_60MS
+ WDTO_120MS
+ WDTO_250MS
+ WDTO_500MS
+ WDTO_1S
+ WDTO_2S
+*/
- #else
+#else
- #define portUSE_TIMER0 /* use the 8-bit Timer0 for xTaskIncrementTick */
+#define portUSE_TIMER0 /* use the 8-bit Timer0 for xTaskIncrementTick */
- #endif
+#endif
- #define portSTACK_GROWTH ( -1 )
+#define portSTACK_GROWTH ( -1 )
/* Timing for the scheduler.
* Watchdog Timer is 128kHz nominal,
* but 120 kHz at 5V DC and 25 degrees is actually more accurate,
* from data sheet.
*/
- #if defined( portUSE_WDTO )
- #define portTICK_PERIOD_MS ( ( TickType_t ) _BV( portUSE_WDTO + 4 ) )
- #else
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #endif
+#if defined( portUSE_WDTO )
+#define portTICK_PERIOD_MS ( (TickType_t) _BV( portUSE_WDTO + 4 ) )
+#else
+#define portTICK_PERIOD_MS ( (TickType_t) 1000 / configTICK_RATE_HZ )
+#endif
- #define portBYTE_ALIGNMENT 1
- #define portNOP() __asm__ __volatile__ ( "nop" );
+#define portBYTE_ALIGNMENT 1
+#define portNOP() __asm__ __volatile__ ( "nop" );
/*-----------------------------------------------------------*/
/* Kernel utilities. */
- extern void vPortYield( void ) __attribute__( ( naked ) );
- #define portYIELD() vPortYield()
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD() vPortYield()
- extern void vPortYieldFromISR( void ) __attribute__( ( naked ) );
- #define portYIELD_FROM_ISR() vPortYieldFromISR()
+extern void vPortYieldFromISR( void ) __attribute__ ( ( naked ) );
+#define portYIELD_FROM_ISR() vPortYieldFromISR()
/*-----------------------------------------------------------*/
- #if defined( __AVR_3_BYTE_PC__ )
+#if defined(__AVR_3_BYTE_PC__)
/* Task function macros as described on the FreeRTOS.org WEB site. */
/* Add .lowtext tag from the avr linker script avr6.x for ATmega2560 and ATmega2561
* to make sure functions are loaded in low memory.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( section( ".lowtext" ) ) )
- #else
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #endif
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__ ((section (".lowtext")))
+#else
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#endif
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index a63ef7e..a00ab17 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -26,31 +26,31 @@
*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Posix port.
-*
-* Each task has a pthread which eases use of standard debuggers
-* (allowing backtraces of tasks etc). Threads for tasks that are not
-* running are blocked in sigwait().
-*
-* Task switch is done by resuming the thread for the next task by
-* sending it the resume signal (SIGUSR1) and then suspending the
-* current thread.
-*
-* The timer interrupt uses SIGALRM and care is taken to ensure that
-* the signal handler runs only on the thread for the current task.
-*
-* Use of part of the standard C library requires care as some
-* functions can take pthread mutexes internally which can result in
-* deadlocks as the FreeRTOS kernel can switch tasks while they're
-* holding a pthread mutex.
-*
-* Replacement malloc(), free(), calloc(), and realloc() are provided
-* for glibc (see below for more information).
-*
-* stdio (printf() and friends) should be called from a single task
-* only or serialized with a FreeRTOS primitive such as a binary
-* semaphore or mutex.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Posix port.
+ *
+ * Each task has a pthread which eases use of standard debuggers
+ * (allowing backtraces of tasks etc). Threads for tasks that are not
+ * running are blocked in sigwait().
+ *
+ * Task switch is done by resuming the thread for the next task by
+ * sending it the resume signal (SIGUSR1) and then suspending the
+ * current thread.
+ *
+ * The timer interrupt uses SIGALRM and care is taken to ensure that
+ * the signal handler runs only on the thread for the current task.
+ *
+ * Use of part of the standard C library requires care as some
+ * functions can take pthread mutexes internally which can result in
+ * deadlocks as the FreeRTOS kernel can switch tasks while they're
+ * holding a pthread mutex.
+ *
+ * Replacement malloc(), free(), calloc(), and realloc() are provided
+ * for glibc (see below for more information).
+ *
+ * stdio (printf() and friends) should be called from a single task
+ * only or serialized with a FreeRTOS primitive such as a binary
+ * semaphore or mutex.
+ *----------------------------------------------------------*/
#include <errno.h>
#include <pthread.h>
@@ -67,25 +67,25 @@
#include "task.h"
/*-----------------------------------------------------------*/
-#define SIG_RESUME SIGUSR1
+#define SIG_RESUME SIGUSR1
typedef struct THREAD
{
- pthread_t pthread;
- pdTASK_CODE pxCode;
- void * pvParams;
- BaseType_t xDying;
+ pthread_t pthread;
+ pdTASK_CODE pxCode;
+ void *pvParams;
+ BaseType_t xDying;
} Thread_t;
/*
* The additional per-thread data is stored at the beginning of the
* task's stack.
*/
-static inline Thread_t * prvGetThreadFromTask( TaskHandle_t xTask )
+static inline Thread_t *prvGetThreadFromTask(TaskHandle_t xTask)
{
- StackType_t * pxTopOfStack = *( StackType_t ** ) xTask;
+StackType_t *pxTopOfStack = *(StackType_t **)xTask;
- return ( Thread_t * ) ( pxTopOfStack + 1 );
+ return (Thread_t *)(pxTopOfStack + 1);
}
/*-----------------------------------------------------------*/
@@ -94,7 +94,7 @@
static sigset_t xResumeSignals;
static sigset_t xAllSignals;
static sigset_t xSchedulerOriginalSignalMask;
-static pthread_t hMainThread = ( pthread_t ) NULL;
+static pthread_t hMainThread = ( pthread_t )NULL;
static volatile portBASE_TYPE uxCriticalNesting;
/*-----------------------------------------------------------*/
@@ -103,9 +103,8 @@
static void prvSetupSignalsAndSchedulerPolicy( void );
static void prvSetupTimerInterrupt( void );
-static void * prvWaitForStart( void * pvParams );
-static void prvSwitchThread( Thread_t * xThreadToResume,
- Thread_t * xThreadToSuspend );
+static void *prvWaitForStart( void * pvParams );
+static void prvSwitchThread( Thread_t *xThreadToResume, Thread_t *xThreadToSuspend );
static void prvSuspendSelf( void );
static void prvResumeThread( pthread_t xThreadId );
static void vPortSystemTickHandler( int sig );
@@ -132,117 +131,110 @@
* timer (SIGALRM) and other signals.
*/
-extern void * __libc_malloc( size_t );
-extern void __libc_free( void * );
-extern void * __libc_calloc( size_t,
- size_t );
-extern void * __libc_realloc( void * ptr,
- size_t );
+extern void *__libc_malloc(size_t);
+extern void __libc_free(void *);
+extern void *__libc_calloc(size_t, size_t);
+extern void *__libc_realloc(void *ptr, size_t);
-void * malloc( size_t size )
+void *malloc(size_t size)
{
- sigset_t xSavedSignals;
- void * ptr;
+sigset_t xSavedSignals;
+void *ptr;
- pthread_sigmask( SIG_BLOCK, &xAllSignals, &xSavedSignals );
- ptr = __libc_malloc( size );
- pthread_sigmask( SIG_SETMASK, &xSavedSignals, NULL );
+ pthread_sigmask( SIG_BLOCK, &xAllSignals, &xSavedSignals );
+ ptr = __libc_malloc( size );
+ pthread_sigmask( SIG_SETMASK, &xSavedSignals, NULL );
- return ptr;
+ return ptr;
}
-void free( void * ptr )
+void free(void *ptr)
{
- sigset_t xSavedSignals;
+sigset_t xSavedSignals;
- pthread_sigmask( SIG_BLOCK, &xAllSignals, &xSavedSignals );
- __libc_free( ptr );
- pthread_sigmask( SIG_SETMASK, &xSavedSignals, NULL );
+ pthread_sigmask( SIG_BLOCK, &xAllSignals, &xSavedSignals );
+ __libc_free( ptr );
+ pthread_sigmask( SIG_SETMASK, &xSavedSignals, NULL );
}
-void * calloc( size_t nmemb,
- size_t size )
+void *calloc(size_t nmemb, size_t size)
{
- sigset_t xSavedSignals;
- void * ptr;
+sigset_t xSavedSignals;
+void *ptr;
- pthread_sigmask( SIG_BLOCK, &xAllSignals, &xSavedSignals );
- ptr = __libc_calloc( nmemb, size );
- pthread_sigmask( SIG_SETMASK, &xSavedSignals, NULL );
+ pthread_sigmask( SIG_BLOCK, &xAllSignals, &xSavedSignals );
+ ptr = __libc_calloc( nmemb, size );
+ pthread_sigmask( SIG_SETMASK, &xSavedSignals, NULL );
- return ptr;
+ return ptr;
}
-void * realloc( void * ptr,
- size_t size )
+void *realloc(void *ptr, size_t size)
{
- sigset_t xSavedSignals;
+sigset_t xSavedSignals;
- pthread_sigmask( SIG_BLOCK, &xAllSignals, &xSavedSignals );
- ptr = __libc_realloc( ptr, size );
- pthread_sigmask( SIG_SETMASK, &xSavedSignals, NULL );
+ pthread_sigmask( SIG_BLOCK, &xAllSignals, &xSavedSignals );
+ ptr = __libc_realloc( ptr, size );
+ pthread_sigmask( SIG_SETMASK, &xSavedSignals, NULL );
- return ptr;
+ return ptr;
}
-static void prvFatalError( const char * pcCall,
- int iErrno )
+static void prvFatalError( const char *pcCall, int iErrno )
{
- fprintf( stderr, "%s: %s\n", pcCall, strerror( iErrno ) );
- abort();
+ fprintf( stderr, "%s: %s\n", pcCall, strerror( iErrno ) );
+ abort();
}
/*
* See header file for description.
*/
-portSTACK_TYPE * pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack,
- portSTACK_TYPE * pxEndOfStack,
- pdTASK_CODE pxCode,
- void * pvParameters )
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack,
+ portSTACK_TYPE *pxEndOfStack,
+ pdTASK_CODE pxCode, void *pvParameters )
{
- Thread_t * thread;
- pthread_attr_t xThreadAttributes;
- size_t ulStackSize;
- int iRet;
+Thread_t *thread;
+pthread_attr_t xThreadAttributes;
+size_t ulStackSize;
+int iRet;
- ( void ) pthread_once( &hSigSetupThread, prvSetupSignalsAndSchedulerPolicy );
+ (void)pthread_once( &hSigSetupThread, prvSetupSignalsAndSchedulerPolicy );
- /*
- * Store the additional thread data at the start of the stack.
- */
- thread = ( Thread_t * ) ( pxTopOfStack + 1 ) - 1;
- pxTopOfStack = ( portSTACK_TYPE * ) thread - 1;
- ulStackSize = ( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack );
+ /*
+ * Store the additional thread data at the start of the stack.
+ */
+ thread = (Thread_t *)(pxTopOfStack + 1) - 1;
+ pxTopOfStack = (portSTACK_TYPE *)thread - 1;
+ ulStackSize = (pxTopOfStack + 1 - pxEndOfStack) * sizeof(*pxTopOfStack);
- thread->pxCode = pxCode;
- thread->pvParams = pvParameters;
- thread->xDying = pdFALSE;
+ thread->pxCode = pxCode;
+ thread->pvParams = pvParameters;
+ thread->xDying = pdFALSE;
- pthread_attr_init( &xThreadAttributes );
- pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize );
+ pthread_attr_init( &xThreadAttributes );
+ pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize );
- vPortEnterCritical();
+ vPortEnterCritical();
- iRet = pthread_create( &thread->pthread, &xThreadAttributes,
- prvWaitForStart, thread );
+ iRet = pthread_create( &thread->pthread, &xThreadAttributes,
+ prvWaitForStart, thread );
+ if ( iRet )
+ {
+ prvFatalError( "pthread_create", iRet );
+ }
- if( iRet )
- {
- prvFatalError( "pthread_create", iRet );
- }
+ vPortExitCritical();
- vPortExitCritical();
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
void vPortStartFirstTask( void )
{
- Thread_t * pxFirstThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+Thread_t *pxFirstThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
- /* Start the first task. */
- prvResumeThread( pxFirstThread->pthread );
+ /* Start the first task. */
+ prvResumeThread( pxFirstThread->pthread );
}
/*-----------------------------------------------------------*/
@@ -251,126 +243,125 @@
*/
portBASE_TYPE xPortStartScheduler( void )
{
- int iSignal;
- sigset_t xSignals;
+int iSignal;
+sigset_t xSignals;
- hMainThread = pthread_self();
+ hMainThread = pthread_self();
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- prvSetupTimerInterrupt();
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
- /* Start the first task. */
- vPortStartFirstTask();
+ /* Start the first task. */
+ vPortStartFirstTask();
- /* Wait until signaled by vPortEndScheduler(). */
- sigemptyset( &xSignals );
- sigaddset( &xSignals, SIG_RESUME );
+ /* Wait until signaled by vPortEndScheduler(). */
+ sigemptyset( &xSignals );
+ sigaddset( &xSignals, SIG_RESUME );
- while( !xSchedulerEnd )
- {
- sigwait( &xSignals, &iSignal );
- }
+ while ( !xSchedulerEnd )
+ {
+ sigwait( &xSignals, &iSignal );
+ }
- /* Restore original signal mask. */
- ( void ) pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL );
+ /* Restore original signal mask. */
+ (void)pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL );
- return 0;
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- struct itimerval itimer;
- struct sigaction sigtick;
+struct itimerval itimer;
+struct sigaction sigtick;
- /* Stop the timer and ignore any pending SIGALRMs that would end
- * up running on the main thread when it is resumed. */
- itimer.it_value.tv_sec = 0;
- itimer.it_value.tv_usec = 0;
+ /* Stop the timer and ignore any pending SIGALRMs that would end
+ * up running on the main thread when it is resumed. */
+ itimer.it_value.tv_sec = 0;
+ itimer.it_value.tv_usec = 0;
- itimer.it_interval.tv_sec = 0;
- itimer.it_interval.tv_usec = 0;
- ( void ) setitimer( ITIMER_REAL, &itimer, NULL );
+ itimer.it_interval.tv_sec = 0;
+ itimer.it_interval.tv_usec = 0;
+ (void)setitimer( ITIMER_REAL, &itimer, NULL );
- sigtick.sa_flags = 0;
- sigtick.sa_handler = SIG_IGN;
- sigemptyset( &sigtick.sa_mask );
- sigaction( SIGALRM, &sigtick, NULL );
+ sigtick.sa_flags = 0;
+ sigtick.sa_handler = SIG_IGN;
+ sigemptyset( &sigtick.sa_mask );
+ sigaction( SIGALRM, &sigtick, NULL );
- /* Signal the scheduler to exit its loop. */
- xSchedulerEnd = pdTRUE;
- ( void ) pthread_kill( hMainThread, SIG_RESUME );
+ /* Signal the scheduler to exit its loop. */
+ xSchedulerEnd = pdTRUE;
+ (void)pthread_kill( hMainThread, SIG_RESUME );
- prvSuspendSelf();
+ prvSuspendSelf();
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- if( uxCriticalNesting == 0 )
- {
- vPortDisableInterrupts();
- }
-
- uxCriticalNesting++;
+ if ( uxCriticalNesting == 0 )
+ {
+ vPortDisableInterrupts();
+ }
+ uxCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- uxCriticalNesting--;
+ uxCriticalNesting--;
- /* If we have reached 0 then re-enable the interrupts. */
- if( uxCriticalNesting == 0 )
- {
- vPortEnableInterrupts();
- }
+ /* If we have reached 0 then re-enable the interrupts. */
+ if( uxCriticalNesting == 0 )
+ {
+ vPortEnableInterrupts();
+ }
}
/*-----------------------------------------------------------*/
void vPortYieldFromISR( void )
{
- Thread_t * xThreadToSuspend;
- Thread_t * xThreadToResume;
+Thread_t *xThreadToSuspend;
+Thread_t *xThreadToResume;
- xThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+ xThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
- vTaskSwitchContext();
+ vTaskSwitchContext();
- xThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+ xThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
- prvSwitchThread( xThreadToResume, xThreadToSuspend );
+ prvSwitchThread( xThreadToResume, xThreadToSuspend );
}
/*-----------------------------------------------------------*/
void vPortYield( void )
{
- vPortEnterCritical();
+ vPortEnterCritical();
- vPortYieldFromISR();
+ vPortYieldFromISR();
- vPortExitCritical();
+ vPortExitCritical();
}
/*-----------------------------------------------------------*/
void vPortDisableInterrupts( void )
{
- pthread_sigmask( SIG_BLOCK, &xAllSignals, NULL );
+ pthread_sigmask( SIG_BLOCK, &xAllSignals, NULL );
}
/*-----------------------------------------------------------*/
void vPortEnableInterrupts( void )
{
- pthread_sigmask( SIG_UNBLOCK, &xAllSignals, NULL );
+ pthread_sigmask( SIG_UNBLOCK, &xAllSignals, NULL );
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortSetInterruptMask( void )
{
- /* Interrupts are always disabled inside ISRs (signals
- * handlers). */
- return pdTRUE;
+ /* Interrupts are always disabled inside ISRs (signals
+ handlers). */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
@@ -379,13 +370,13 @@
}
/*-----------------------------------------------------------*/
-static uint64_t prvGetTimeNs( void )
+static uint64_t prvGetTimeNs(void)
{
- struct timespec t;
+struct timespec t;
- clock_gettime( CLOCK_MONOTONIC, &t );
+ clock_gettime(CLOCK_MONOTONIC, &t);
- return t.tv_sec * 1000000000ull + t.tv_nsec;
+ return t.tv_sec * 1000000000ull + t.tv_nsec;
}
static uint64_t prvStartTimeNs;
@@ -397,228 +388,218 @@
*/
void prvSetupTimerInterrupt( void )
{
- struct itimerval itimer;
- int iRet;
+struct itimerval itimer;
+int iRet;
- /* Initialise the structure with the current timer information. */
- iRet = getitimer( ITIMER_REAL, &itimer );
+ /* Initialise the structure with the current timer information. */
+ iRet = getitimer( ITIMER_REAL, &itimer );
+ if ( iRet )
+ {
+ prvFatalError( "getitimer", errno );
+ }
- if( iRet )
- {
- prvFatalError( "getitimer", errno );
- }
+ /* Set the interval between timer events. */
+ itimer.it_interval.tv_sec = 0;
+ itimer.it_interval.tv_usec = portTICK_RATE_MICROSECONDS;
- /* Set the interval between timer events. */
- itimer.it_interval.tv_sec = 0;
- itimer.it_interval.tv_usec = portTICK_RATE_MICROSECONDS;
+ /* Set the current count-down. */
+ itimer.it_value.tv_sec = 0;
+ itimer.it_value.tv_usec = portTICK_RATE_MICROSECONDS;
- /* Set the current count-down. */
- itimer.it_value.tv_sec = 0;
- itimer.it_value.tv_usec = portTICK_RATE_MICROSECONDS;
+ /* Set-up the timer interrupt. */
+ iRet = setitimer( ITIMER_REAL, &itimer, NULL );
+ if ( iRet )
+ {
+ prvFatalError( "setitimer", errno );
+ }
- /* Set-up the timer interrupt. */
- iRet = setitimer( ITIMER_REAL, &itimer, NULL );
-
- if( iRet )
- {
- prvFatalError( "setitimer", errno );
- }
-
- prvStartTimeNs = prvGetTimeNs();
+ prvStartTimeNs = prvGetTimeNs();
}
/*-----------------------------------------------------------*/
static void vPortSystemTickHandler( int sig )
{
- Thread_t * pxThreadToSuspend;
- Thread_t * pxThreadToResume;
- uint64_t xExpectedTicks;
+Thread_t *pxThreadToSuspend;
+Thread_t *pxThreadToResume;
+uint64_t xExpectedTicks;
- uxCriticalNesting++; /* Signals are blocked in this signal handler. */
+ uxCriticalNesting++; /* Signals are blocked in this signal handler. */
- pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+ pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
- /* Tick Increment, accounting for any lost signals or drift in
- * the timer. */
- xExpectedTicks = ( prvGetTimeNs() - prvStartTimeNs )
- / ( portTICK_RATE_MICROSECONDS * 1000 );
+ /* Tick Increment, accounting for any lost signals or drift in
+ * the timer. */
+ xExpectedTicks = (prvGetTimeNs() - prvStartTimeNs)
+ / (portTICK_RATE_MICROSECONDS * 1000);
+ do {
+ xTaskIncrementTick();
+ prvTickCount++;
+ } while (prvTickCount < xExpectedTicks);
- do
- {
- xTaskIncrementTick();
- prvTickCount++;
- } while( prvTickCount < xExpectedTicks );
+#if ( configUSE_PREEMPTION == 1 )
+ /* Select Next Task. */
+ vTaskSwitchContext();
- #if ( configUSE_PREEMPTION == 1 )
- /* Select Next Task. */
- vTaskSwitchContext();
+ pxThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
- pxThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+ prvSwitchThread(pxThreadToResume, pxThreadToSuspend);
+#endif
- prvSwitchThread( pxThreadToResume, pxThreadToSuspend );
- #endif
-
- uxCriticalNesting--;
+ uxCriticalNesting--;
}
/*-----------------------------------------------------------*/
-void vPortThreadDying( void * pxTaskToDelete,
- volatile BaseType_t * pxPendYield )
+void vPortThreadDying( void *pxTaskToDelete, volatile BaseType_t *pxPendYield )
{
- Thread_t * pxThread = prvGetThreadFromTask( pxTaskToDelete );
+Thread_t *pxThread = prvGetThreadFromTask( pxTaskToDelete );
- pxThread->xDying = pdTRUE;
+ pxThread->xDying = pdTRUE;
}
-void vPortCancelThread( void * pxTaskToDelete )
+void vPortCancelThread( void *pxTaskToDelete )
{
- Thread_t * pxThreadToCancel = prvGetThreadFromTask( pxTaskToDelete );
+Thread_t *pxThreadToCancel = prvGetThreadFromTask( pxTaskToDelete );
- /*
- * The thread has already been suspended so it can be safely
- * cancelled.
- */
- pthread_cancel( pxThreadToCancel->pthread );
- pthread_join( pxThreadToCancel->pthread, NULL );
+ /*
+ * The thread has already been suspended so it can be safely
+ * cancelled.
+ */
+ pthread_cancel( pxThreadToCancel->pthread );
+ pthread_join( pxThreadToCancel->pthread, NULL );
}
/*-----------------------------------------------------------*/
-static void * prvWaitForStart( void * pvParams )
+static void *prvWaitForStart( void * pvParams )
{
- Thread_t * pxThread = pvParams;
+Thread_t *pxThread = pvParams;
- prvSuspendSelf();
+ prvSuspendSelf();
- /* Resumed for the first time, unblocks all signals. */
- uxCriticalNesting = 0;
- vPortEnableInterrupts();
+ /* Resumed for the first time, unblocks all signals. */
+ uxCriticalNesting = 0;
+ vPortEnableInterrupts();
- /* Call the task's entry point. */
- pxThread->pxCode( pxThread->pvParams );
+ /* Call the task's entry point. */
+ pxThread->pxCode( pxThread->pvParams );
- return NULL;
+ return NULL;
}
/*-----------------------------------------------------------*/
-static void prvSwitchThread( Thread_t * pxThreadToResume,
- Thread_t * pxThreadToSuspend )
+static void prvSwitchThread( Thread_t *pxThreadToResume,
+ Thread_t *pxThreadToSuspend )
{
- BaseType_t uxSavedCriticalNesting;
+BaseType_t uxSavedCriticalNesting;
- if( pxThreadToSuspend != pxThreadToResume )
- {
- /*
- * Switch tasks.
- *
- * The critical section nesting is per-task, so save it on the
- * stack of the current (suspending thread), restoring it when
- * we switch back to this task.
- */
- uxSavedCriticalNesting = uxCriticalNesting;
+ if ( pxThreadToSuspend != pxThreadToResume )
+ {
+ /*
+ * Switch tasks.
+ *
+ * The critical section nesting is per-task, so save it on the
+ * stack of the current (suspending thread), restoring it when
+ * we switch back to this task.
+ */
+ uxSavedCriticalNesting = uxCriticalNesting;
- prvResumeThread( pxThreadToResume->pthread );
+ prvResumeThread( pxThreadToResume->pthread );
+ if ( pxThreadToSuspend->xDying )
+ {
+ pthread_exit( NULL );
+ }
+ prvSuspendSelf();
- if( pxThreadToSuspend->xDying )
- {
- pthread_exit( NULL );
- }
-
- prvSuspendSelf();
-
- uxCriticalNesting = uxSavedCriticalNesting;
- }
+ uxCriticalNesting = uxSavedCriticalNesting;
+ }
}
/*-----------------------------------------------------------*/
static void prvSuspendSelf( void )
{
- int iSig;
+int iSig;
- /*
- * Suspend this thread by waiting for a SIG_RESUME signal.
- *
- * A suspended thread must not handle signals (interrupts) so
- * all signals must be blocked by calling this from:
- *
- * - Inside a critical section (vPortEnterCritical() /
- * vPortExitCritical()).
- *
- * - From a signal handler that has all signals masked.
- *
- * - A thread with all signals blocked with pthread_sigmask().
- */
- sigwait( &xResumeSignals, &iSig );
+ /*
+ * Suspend this thread by waiting for a SIG_RESUME signal.
+ *
+ * A suspended thread must not handle signals (interrupts) so
+ * all signals must be blocked by calling this from:
+ *
+ * - Inside a critical section (vPortEnterCritical() /
+ * vPortExitCritical()).
+ *
+ * - From a signal handler that has all signals masked.
+ *
+ * - A thread with all signals blocked with pthread_sigmask().
+ */
+ sigwait( &xResumeSignals, &iSig );
}
/*-----------------------------------------------------------*/
static void prvResumeThread( pthread_t xThreadId )
{
- if( pthread_self() != xThreadId )
- {
- pthread_kill( xThreadId, SIG_RESUME );
- }
+ if ( pthread_self() != xThreadId )
+ {
+ pthread_kill( xThreadId, SIG_RESUME );
+ }
}
/*-----------------------------------------------------------*/
static void prvSetupSignalsAndSchedulerPolicy( void )
{
- struct sigaction sigresume, sigtick;
- int iRet;
+struct sigaction sigresume, sigtick;
+int iRet;
- hMainThread = pthread_self();
+ hMainThread = pthread_self();
- /* Initialise common signal masks. */
- sigemptyset( &xResumeSignals );
- sigaddset( &xResumeSignals, SIG_RESUME );
- sigfillset( &xAllSignals );
+ /* Initialise common signal masks. */
+ sigemptyset( &xResumeSignals );
+ sigaddset( &xResumeSignals, SIG_RESUME );
+ sigfillset( &xAllSignals );
+ /* Don't block SIGINT so this can be used to break into GDB while
+ * in a critical section. */
+ sigdelset( &xAllSignals, SIGINT );
- /* Don't block SIGINT so this can be used to break into GDB while
- * in a critical section. */
- sigdelset( &xAllSignals, SIGINT );
+ /*
+ * Block all signals in this thread so all new threads
+ * inherits this mask.
+ *
+ * When a thread is resumed for the first time, all signals
+ * will be unblocked.
+ */
+ (void)pthread_sigmask( SIG_SETMASK, &xAllSignals,
+ &xSchedulerOriginalSignalMask );
- /*
- * Block all signals in this thread so all new threads
- * inherits this mask.
- *
- * When a thread is resumed for the first time, all signals
- * will be unblocked.
- */
- ( void ) pthread_sigmask( SIG_SETMASK, &xAllSignals,
- &xSchedulerOriginalSignalMask );
+ /* SIG_RESUME is only used with sigwait() so doesn't need a
+ handler. */
+ sigresume.sa_flags = 0;
+ sigresume.sa_handler = SIG_IGN;
+ sigfillset( &sigresume.sa_mask );
- /* SIG_RESUME is only used with sigwait() so doesn't need a
- * handler. */
- sigresume.sa_flags = 0;
- sigresume.sa_handler = SIG_IGN;
- sigfillset( &sigresume.sa_mask );
+ sigtick.sa_flags = 0;
+ sigtick.sa_handler = vPortSystemTickHandler;
+ sigfillset( &sigtick.sa_mask );
- sigtick.sa_flags = 0;
- sigtick.sa_handler = vPortSystemTickHandler;
- sigfillset( &sigtick.sa_mask );
+ iRet = sigaction( SIG_RESUME, &sigresume, NULL );
+ if ( iRet )
+ {
+ prvFatalError( "sigaction", errno );
+ }
- iRet = sigaction( SIG_RESUME, &sigresume, NULL );
-
- if( iRet )
- {
- prvFatalError( "sigaction", errno );
- }
-
- iRet = sigaction( SIGALRM, &sigtick, NULL );
-
- if( iRet )
- {
- prvFatalError( "sigaction", errno );
- }
+ iRet = sigaction( SIGALRM, &sigtick, NULL );
+ if ( iRet )
+ {
+ prvFatalError( "sigaction", errno );
+ }
}
/*-----------------------------------------------------------*/
unsigned long ulPortGetRunTime( void )
{
- struct tms xTimes;
+struct tms xTimes;
- times( &xTimes );
+ times( &xTimes );
- return ( unsigned long ) xTimes.tms_utime;
+ return ( unsigned long ) xTimes.tms_utime;
}
/*-----------------------------------------------------------*/
diff --git a/portable/ThirdParty/GCC/Posix/portmacro.h b/portable/ThirdParty/GCC/Posix/portmacro.h
index 91d44fe..8046cbc 100644
--- a/portable/ThirdParty/GCC/Posix/portmacro.h
+++ b/portable/ThirdParty/GCC/Posix/portmacro.h
@@ -27,13 +27,13 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
- #include <limits.h>
+#include <limits.h>
/*-----------------------------------------------------------
* Port specific definitions.
@@ -46,72 +46,71 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE unsigned long
- #define portBASE_TYPE long
- #define portPOINTER_SIZE_TYPE intptr_t
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE unsigned long
+#define portBASE_TYPE long
+#define portPOINTER_SIZE_TYPE intptr_t
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- typedef unsigned long TickType_t;
- #define portMAX_DELAY ( TickType_t ) ULONG_MAX
+typedef unsigned long TickType_t;
+#define portMAX_DELAY ( TickType_t ) ULONG_MAX
- #define portTICK_TYPE_IS_ATOMIC 1
+#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portHAS_STACK_OVERFLOW_CHECKING ( 1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portTICK_RATE_MICROSECONDS ( ( portTickType ) 1000000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portHAS_STACK_OVERFLOW_CHECKING ( 1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICK_RATE_MICROSECONDS ( ( portTickType ) 1000000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- extern void vPortYield( void );
+extern void vPortYield( void );
- #define portYIELD() vPortYield()
+#define portYIELD() vPortYield()
- #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) vPortYield()
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) vPortYield()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortDisableInterrupts( void );
- extern void vPortEnableInterrupts( void );
- #define portSET_INTERRUPT_MASK() ( vPortDisableInterrupts() )
- #define portCLEAR_INTERRUPT_MASK() ( vPortEnableInterrupts() )
+extern void vPortDisableInterrupts( void );
+extern void vPortEnableInterrupts( void );
+#define portSET_INTERRUPT_MASK() ( vPortDisableInterrupts() )
+#define portCLEAR_INTERRUPT_MASK() ( vPortEnableInterrupts() )
- extern portBASE_TYPE xPortSetInterruptMask( void );
- extern void vPortClearInterruptMask( portBASE_TYPE xMask );
+extern portBASE_TYPE xPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( portBASE_TYPE xMask );
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
- #define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK()
- #define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK()
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
+#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK()
+#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK()
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
- extern void vPortThreadDying( void * pxTaskToDelete,
- volatile BaseType_t * pxPendYield );
- extern void vPortCancelThread( void * pxTaskToDelete );
- #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) )
- #define portCLEAN_UP_TCB( pxTCB ) vPortCancelThread( pxTCB )
+extern void vPortThreadDying( void *pxTaskToDelete, volatile BaseType_t *pxPendYield );
+extern void vPortCancelThread( void *pxTaskToDelete );
+#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) )
+#define portCLEAN_UP_TCB( pxTCB ) vPortCancelThread( pxTCB )
/*-----------------------------------------------------------*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
/*
@@ -122,14 +121,14 @@
* Thus, only a compilier barrier is needed to prevent the compiler
* reordering.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
- extern unsigned long ulPortGetRunTime( void );
- #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */
- #define portGET_RUN_TIME_COUNTER_VALUE() ulPortGetRunTime()
+extern unsigned long ulPortGetRunTime( void );
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */
+#define portGET_RUN_TIME_COUNTER_VALUE() ulPortGetRunTime()
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
index cce0bd0..dc0c71c 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
@@ -64,26 +64,28 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
- #ifndef __ASSEMBLER__
+#ifndef __ASSEMBLER__
- #include <stdint.h>
+ #include <stdint.h>
- #include <xtensa/hal.h>
- #include <xtensa/config/core.h>
- #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
- #include <xtensa/xtruntime.h>
- #include "esp_timer.h" /* required for FreeRTOS run time stats */
- #include "esp_system.h"
+ #include <xtensa/hal.h>
+ #include <xtensa/config/core.h>
+ #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+ #include <xtensa/xtruntime.h>
+ #include "esp_timer.h" /* required for FreeRTOS run time stats */
+ #include "esp_system.h"
- #include <esp_heap_caps.h>
- #include "soc/soc_memory_layout.h"
+ #include <esp_heap_caps.h>
+ #include "soc/soc_memory_layout.h"
/*#include "xtensa_context.h" */
@@ -99,84 +101,84 @@
/* Type definitions. */
- #define portCHAR int8_t
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG int32_t
- #define portSHORT int16_t
- #define portSTACK_TYPE uint8_t
- #define portBASE_TYPE int
+ #define portCHAR int8_t
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG int32_t
+ #define portSHORT int16_t
+ #define portSTACK_TYPE uint8_t
+ #define portBASE_TYPE int
- typedef portSTACK_TYPE StackType_t;
- typedef portBASE_TYPE BaseType_t;
- typedef unsigned portBASE_TYPE UBaseType_t;
+ typedef portSTACK_TYPE StackType_t;
+ typedef portBASE_TYPE BaseType_t;
+ typedef unsigned portBASE_TYPE UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ #endif
/*-----------------------------------------------------------*/
/* portbenchmark */
- #include "portbenchmark.h"
+ #include "portbenchmark.h"
- #include "sdkconfig.h"
- #include "esp_attr.h"
+ #include "sdkconfig.h"
+ #include "esp_attr.h"
/* "mux" data structure (spinlock) */
- typedef struct
- {
- /* owner field values:
- * 0 - Uninitialized (invalid)
- * portMUX_FREE_VAL - Mux is free, can be locked by either CPU
- * CORE_ID_PRO / CORE_ID_APP - Mux is locked to the particular core
- *
- * Any value other than portMUX_FREE_VAL, CORE_ID_PRO, CORE_ID_APP indicates corruption
- */
- uint32_t owner;
+ typedef struct
+ {
+ /* owner field values:
+ * 0 - Uninitialized (invalid)
+ * portMUX_FREE_VAL - Mux is free, can be locked by either CPU
+ * CORE_ID_PRO / CORE_ID_APP - Mux is locked to the particular core
+ *
+ * Any value other than portMUX_FREE_VAL, CORE_ID_PRO, CORE_ID_APP indicates corruption
+ */
+ uint32_t owner;
- /* count field:
- * If mux is unlocked, count should be zero.
- * If mux is locked, count is non-zero & represents the number of recursive locks on the mux.
- */
- uint32_t count;
- #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
- const char * lastLockedFn;
- int lastLockedLine;
- #endif
- } portMUX_TYPE;
+ /* count field:
+ * If mux is unlocked, count should be zero.
+ * If mux is locked, count is non-zero & represents the number of recursive locks on the mux.
+ */
+ uint32_t count;
+ #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+ const char * lastLockedFn;
+ int lastLockedLine;
+ #endif
+ } portMUX_TYPE;
- #define portMUX_FREE_VAL 0xB33FFFFF
+ #define portMUX_FREE_VAL 0xB33FFFFF
/* Special constants for vPortCPUAcquireMutexTimeout() */
- #define portMUX_NO_TIMEOUT ( -1 ) /* When passed for 'timeout_cycles', spin forever if necessary */
- #define portMUX_TRY_LOCK 0 /* Try to acquire the spinlock a single time only */
+ #define portMUX_NO_TIMEOUT ( -1 ) /* When passed for 'timeout_cycles', spin forever if necessary */
+ #define portMUX_TRY_LOCK 0 /* Try to acquire the spinlock a single time only */
/* Keep this in sync with the portMUX_TYPE struct definition please. */
- #ifndef CONFIG_FREERTOS_PORTMUX_DEBUG
- #define portMUX_INITIALIZER_UNLOCKED \
- { \
- .owner = portMUX_FREE_VAL, \
- .count = 0, \
+ #ifndef CONFIG_FREERTOS_PORTMUX_DEBUG
+ #define portMUX_INITIALIZER_UNLOCKED \
+ { \
+ .owner = portMUX_FREE_VAL, \
+ .count = 0, \
}
- #else
- #define portMUX_INITIALIZER_UNLOCKED \
- { \
- .owner = portMUX_FREE_VAL, \
- .count = 0, \
- .lastLockedFn = "(never locked)", \
- .lastLockedLine = -1 \
+ #else
+ #define portMUX_INITIALIZER_UNLOCKED \
+ { \
+ .owner = portMUX_FREE_VAL, \
+ .count = 0, \
+ .lastLockedFn = "(never locked)", \
+ .lastLockedLine = -1 \
}
- #endif /* ifndef CONFIG_FREERTOS_PORTMUX_DEBUG */
+ #endif /* ifndef CONFIG_FREERTOS_PORTMUX_DEBUG */
- #define portASSERT_IF_IN_ISR() vPortAssertIfInISR()
- void vPortAssertIfInISR();
+ #define portASSERT_IF_IN_ISR() vPortAssertIfInISR()
+ void vPortAssertIfInISR();
- #define portCRITICAL_NESTING_IN_TCB 1
+ #define portCRITICAL_NESTING_IN_TCB 1
/*
* Modifications to portENTER_CRITICAL.
@@ -204,17 +206,17 @@
* that either function can be called both from ISR as well as task context. This is not standard FreeRTOS
* behaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations.
*/
- void vPortCPUInitializeMutex( portMUX_TYPE * mux );
- #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
- #error CONFIG_FREERTOS_PORTMUX_DEBUG not supported in Amazon FreeRTOS
- #endif
+ void vPortCPUInitializeMutex( portMUX_TYPE * mux );
+ #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+ #error CONFIG_FREERTOS_PORTMUX_DEBUG not supported in Amazon FreeRTOS
+ #endif
- void vTaskExitCritical();
- void vTaskEnterCritical();
- static inline void vPortConsumeSpinlockArg( int unused,
- ... )
- {
- }
+ void vTaskExitCritical();
+ void vTaskEnterCritical();
+ static inline void vPortConsumeSpinlockArg( int unused,
+ ... )
+ {
+ }
/** @brief Acquire a portmux spinlock with a timeout
*
@@ -224,35 +226,35 @@
*
* @return true if mutex is successfully acquired, false on timeout.
*/
- bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
- int timeout_cycles );
- void vPortCPUReleaseMutex( portMUX_TYPE * mux );
+ bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
+ int timeout_cycles );
+ void vPortCPUReleaseMutex( portMUX_TYPE * mux );
- #define portENTER_CRITICAL( ... ) do { vTaskEnterCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 )
- #define portEXIT_CRITICAL( ... ) do { vTaskExitCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 )
+ #define portENTER_CRITICAL( ... ) do { vTaskEnterCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 )
+ #define portEXIT_CRITICAL( ... ) do { vTaskExitCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 )
- #define portENTER_CRITICAL_ISR( mux ) vPortCPUAcquireMutexTimeout( mux, portMUX_NO_TIMEOUT )
- #define portEXIT_CRITICAL_ISR( mux ) vPortCPUReleaseMutex( mux )
+ #define portENTER_CRITICAL_ISR( mux ) vPortCPUAcquireMutexTimeout( mux, portMUX_NO_TIMEOUT )
+ #define portEXIT_CRITICAL_ISR( mux ) vPortCPUReleaseMutex( mux )
- #define portENTER_CRITICAL_SAFE( mux ) \
- do { \
- if( xPortInIsrContext() ) { \
- portENTER_CRITICAL_ISR( mux ); \
- } \
- else { \
- portENTER_CRITICAL( mux ); \
- } \
+ #define portENTER_CRITICAL_SAFE( mux ) \
+ do { \
+ if( xPortInIsrContext() ) { \
+ portENTER_CRITICAL_ISR( mux ); \
+ } \
+ else { \
+ portENTER_CRITICAL( mux ); \
+ } \
} while( 0 )
- #define portEXIT_CRITICAL_SAFE( mux ) \
- do { \
- if( xPortInIsrContext() ) { \
- portEXIT_CRITICAL_ISR( mux ); \
- } \
- else { \
- portEXIT_CRITICAL( mux ); \
- } \
+ #define portEXIT_CRITICAL_SAFE( mux ) \
+ do { \
+ if( xPortInIsrContext() ) { \
+ portEXIT_CRITICAL_ISR( mux ); \
+ } \
+ else { \
+ portEXIT_CRITICAL( mux ); \
+ } \
} while( 0 )
@@ -260,37 +262,37 @@
/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */
/* */
/* Only applies to one CPU. See notes above & below for reasons not to use these. */
- #define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 )
- #define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 )
+ #define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 )
+ #define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 )
/* Cleaner solution allows nested interrupts disabling and restoring via local registers or stack. */
/* They can be called from interrupts too. */
/* WARNING: Only applies to current CPU. See notes above. */
- static inline unsigned portENTER_CRITICAL_NESTED()
- {
- unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
+ static inline unsigned portENTER_CRITICAL_NESTED()
+ {
+ unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
- portbenchmarkINTERRUPT_DISABLE();
- return state;
- }
- #define portEXIT_CRITICAL_NESTED( state ) do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 )
+ portbenchmarkINTERRUPT_DISABLE();
+ return state;
+ }
+ #define portEXIT_CRITICAL_NESTED( state ) do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 )
/* These FreeRTOS versions are similar to the nested versions above */
- #define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state ) portEXIT_CRITICAL_NESTED( state )
+ #define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state ) portEXIT_CRITICAL_NESTED( state )
/*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */
/*the stack memory to always be internal. */
- #define pvPortMallocTcbMem( size ) heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
- #define pvPortMallocStackMem( size ) heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
+ #define pvPortMallocTcbMem( size ) heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
+ #define pvPortMallocStackMem( size ) heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
/*xTaskCreateStatic uses these functions to check incoming memory. */
- #define portVALID_TCB_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
- #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
- #define portVALID_STACK_MEM( ptr ) esp_ptr_byte_accessible( ptr )
- #else
- #define portVALID_STACK_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
- #endif
+ #define portVALID_TCB_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
+ #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+ #define portVALID_STACK_MEM( ptr ) esp_ptr_byte_accessible( ptr )
+ #else
+ #define portVALID_STACK_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
+ #endif
/*
* Wrapper for the Xtensa compare-and-set instruction. This subroutine will atomically compare
@@ -301,118 +303,118 @@
* *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the
* ESP32 (portMUX assertions would fail).
*/
- static inline void uxPortCompareSet( volatile uint32_t * addr,
- uint32_t compare,
- uint32_t * set )
- {
- #if ( XCHAL_HAVE_S32C1I > 0 )
- __asm__ __volatile__ (
- "WSR %2,SCOMPARE1 \n"
- "S32C1I %0, %1, 0 \n"
- : "=r" ( *set )
- : "r" ( addr ), "r" ( compare ), "0" ( *set )
- );
- #else
- /* No S32C1I, so do this by disabling and re-enabling interrupts (slower) */
- uint32_t intlevel, old_value;
- __asm__ __volatile__ ( "rsil %0, " XTSTR( XCHAL_EXCM_LEVEL ) "\n"
- : "=r" ( intlevel ) );
+ static inline void uxPortCompareSet( volatile uint32_t * addr,
+ uint32_t compare,
+ uint32_t * set )
+ {
+ #if ( XCHAL_HAVE_S32C1I > 0 )
+ __asm__ __volatile__ (
+ "WSR %2,SCOMPARE1 \n"
+ "S32C1I %0, %1, 0 \n"
+ : "=r" ( *set )
+ : "r" ( addr ), "r" ( compare ), "0" ( *set )
+ );
+ #else
+ /* No S32C1I, so do this by disabling and re-enabling interrupts (slower) */
+ uint32_t intlevel, old_value;
+ __asm__ __volatile__ ( "rsil %0, " XTSTR( XCHAL_EXCM_LEVEL ) "\n"
+ : "=r" ( intlevel ) );
- old_value = *addr;
+ old_value = *addr;
- if( old_value == compare )
- {
- *addr = *set;
- }
+ if( old_value == compare )
+ {
+ *addr = *set;
+ }
- __asm__ __volatile__ ( "memw \n"
- "wsr %0, ps\n"
- : : "r" ( intlevel ) );
+ __asm__ __volatile__ ( "memw \n"
+ "wsr %0, ps\n"
+ : : "r" ( intlevel ) );
- *set = old_value;
- #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */
- }
+ *set = old_value;
+ #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */
+ }
- void uxPortCompareSetExtram( volatile uint32_t * addr,
- uint32_t compare,
- uint32_t * set );
+ void uxPortCompareSetExtram( volatile uint32_t * addr,
+ uint32_t compare,
+ uint32_t * set );
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 4
- #define portNOP() XT_NOP()
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 4
+ #define portNOP() XT_NOP()
/*-----------------------------------------------------------*/
/* Fine resolution time */
- #define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount()
+ #define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount()
/*ccount or esp_timer are initialized elsewhere */
- #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
- #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER
+ #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER
/* Coarse resolution time (us) */
- #define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) x = ( uint32_t ) esp_timer_get_time()
- #endif
+ #define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) x = ( uint32_t ) esp_timer_get_time()
+ #endif
/* Kernel utilities. */
- void vPortYield( void );
- void _frxt_setup_switch( void );
- #define portYIELD() vPortYield()
- #define portYIELD_FROM_ISR() { traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch(); }
+ void vPortYield( void );
+ void _frxt_setup_switch( void );
+ #define portYIELD() vPortYield()
+ #define portYIELD_FROM_ISR() { traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch(); }
- static inline uint32_t xPortGetCoreID();
+ static inline uint32_t xPortGetCoreID();
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/* When coprocessors are defined, we to maintain a pointer to coprocessors area. */
/* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */
/* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */
/* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */
- typedef struct
- {
- #if XCHAL_CP_NUM > 0
- volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */
- #endif
-
- #if portUSING_MPU_WRAPPERS
- /* Define here mpu_settings, which is port dependent */
- int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */
- #endif
-
- #if configUSE_TRACE_FACILITY_2
- struct
- {
- /* Cf. porttraceStamp() */
- int taskstamp; /* Stamp from inside task to see where we are */
- int taskstampcount; /* A counter usually incremented when we restart the task's loop */
- } porttrace;
- #endif
- } xMPU_SETTINGS;
-
-/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */
- #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */
- #undef portUSING_MPU_WRAPPERS
- #define portUSING_MPU_WRAPPERS 1 /* Enable it to allocate coproc area */
- #define MPU_WRAPPERS_H /* Override mpu_wrapper.h to disable unwanted code */
- #define PRIVILEGED_FUNCTION
- #define PRIVILEGED_DATA
+ typedef struct
+ {
+ #if XCHAL_CP_NUM > 0
+ volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */
#endif
- bool vApplicationSleep( TickType_t xExpectedIdleTime );
+ #if portUSING_MPU_WRAPPERS
+ /* Define here mpu_settings, which is port dependent */
+ int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */
+ #endif
- #define portSUPPRESS_TICKS_AND_SLEEP( idleTime ) vApplicationSleep( idleTime )
+ #if configUSE_TRACE_FACILITY_2
+ struct
+ {
+ /* Cf. porttraceStamp() */
+ int taskstamp; /* Stamp from inside task to see where we are */
+ int taskstampcount; /* A counter usually incremented when we restart the task's loop */
+ } porttrace;
+ #endif
+ } xMPU_SETTINGS;
+
+/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */
+ #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */
+ #undef portUSING_MPU_WRAPPERS
+ #define portUSING_MPU_WRAPPERS 1 /* Enable it to allocate coproc area */
+ #define MPU_WRAPPERS_H /* Override mpu_wrapper.h to disable unwanted code */
+ #define PRIVILEGED_FUNCTION
+ #define PRIVILEGED_DATA
+ #endif
+
+ bool vApplicationSleep( TickType_t xExpectedIdleTime );
+
+ #define portSUPPRESS_TICKS_AND_SLEEP( idleTime ) vApplicationSleep( idleTime )
- void _xt_coproc_release( volatile void * coproc_sa_base );
+ void _xt_coproc_release( volatile void * coproc_sa_base );
/*
@@ -422,29 +424,29 @@
* non-FreeRTOS-specific code, and behave the same as
* pvPortMalloc()/vPortFree().
*/
- #define pvPortMalloc heap_caps_malloc_default
- #define vPortFree heap_caps_free
- #define xPortGetFreeHeapSize esp_get_free_heap_size
- #define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size
+ #define pvPortMalloc heap_caps_malloc_default
+ #define vPortFree heap_caps_free
+ #define xPortGetFreeHeapSize esp_get_free_heap_size
+ #define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size
/*
* Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
* watchpoint around.
*/
- void vPortSetStackWatchpoint( void * pxStackStart );
+ void vPortSetStackWatchpoint( void * pxStackStart );
/*
* Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
* aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
*/
- BaseType_t xPortInIsrContext();
+ BaseType_t xPortInIsrContext();
/*
* This function will be called in High prio ISRs. Returns true if the current core was in ISR context
* before calling into high prio ISR context.
*/
- BaseType_t xPortInterruptedFromISRContext();
+ BaseType_t xPortInterruptedFromISRContext();
/*
* The structures and methods of manipulating the MPU are contained within the
@@ -453,46 +455,48 @@
* Fills the xMPUSettings structure with the memory region information
* contained in xRegions.
*/
- #if ( portUSING_MPU_WRAPPERS == 1 )
- struct xMEMORY_REGION;
- void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
- const struct xMEMORY_REGION * const xRegions,
- StackType_t * pxBottomOfStack,
- uint32_t usStackDepth ) PRIVILEGED_FUNCTION;
- void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings );
- #endif
+ #if ( portUSING_MPU_WRAPPERS == 1 )
+ struct xMEMORY_REGION;
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+ const struct xMEMORY_REGION * const xRegions,
+ StackType_t * pxBottomOfStack,
+ uint32_t usStackDepth ) PRIVILEGED_FUNCTION;
+ void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings );
+ #endif
/* Multi-core: get current core ID */
- static inline uint32_t IRAM_ATTR xPortGetCoreID()
- {
- int id;
+ static inline uint32_t IRAM_ATTR xPortGetCoreID()
+ {
+ int id;
- asm (
- "rsr.prid %0\n"
- " extui %0,%0,13,1"
- : "=r" ( id ) );
- return id;
- }
+ asm (
+ "rsr.prid %0\n"
+ " extui %0,%0,13,1"
+ : "=r" ( id ) );
+ return id;
+ }
/* Get tick rate per second */
- uint32_t xPortGetTickRateHz( void );
+ uint32_t xPortGetTickRateHz( void );
/* porttrace */
- #if configUSE_TRACE_FACILITY_2
- #include "porttrace.h"
- #endif
+ #if configUSE_TRACE_FACILITY_2
+ #include "porttrace.h"
+ #endif
/* configASSERT_2 if requested */
- #if configASSERT_2
- #include <stdio.h>
- void exit( int );
- #define configASSERT( x ) if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); }
- #endif
-
- #endif // __ASSEMBLER__
-
- #ifdef __cplusplus
- }
+ #if configASSERT_2
+ #include <stdio.h>
+ void exit( int );
+ #define configASSERT( x ) if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); }
#endif
+#endif // __ASSEMBLER__
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ }
+#endif
+/* *INDENT-ON* */
+
#endif /* PORTMACRO_H */
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
index 414dbfd..70bccf1 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
@@ -154,6 +154,7 @@
/*
* Stack initialization
*/
+/* *INDENT-OFF* */
#if portUSING_MPU_WRAPPERS
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
@@ -164,6 +165,7 @@
TaskFunction_t pxCode,
void * pvParameters )
#endif
+/* *INDENT-ON* */
{
StackType_t * sp, * tp;
XtExcFrame * frame;
@@ -409,7 +411,7 @@
return result;
}
-#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
void vPortCPUAcquireMutex( portMUX_TYPE * mux )
{
unsigned int irqStatus = portENTER_CRITICAL_NESTED();
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c
index 2bf1da7..6378995 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c
@@ -35,9 +35,9 @@
#include "xtensa_rtos.h"
#if CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/clk.h"
+ #include "esp32s2/clk.h"
#elif CONFIG_IDF_TARGET_ESP32
-#include "esp32/clk.h"
+ #include "esp32/clk.h"
#endif
#ifdef XT_RTOS_TIMER_INT
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c
index 93e4160..8e1465d 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c
@@ -35,9 +35,9 @@
#include "freertos/portable.h"
#if CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/ets_sys.h"
+ #include "esp32s2/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32
-#include "esp32/rom/ets_sys.h"
+ #include "esp32/rom/ets_sys.h"
#endif
#if XCHAL_HAVE_EXCEPTIONS
diff --git a/portable/ThirdParty/XCC/Xtensa/port.c b/portable/ThirdParty/XCC/Xtensa/port.c
index 1412639..c16dfed 100644
--- a/portable/ThirdParty/XCC/Xtensa/port.c
+++ b/portable/ThirdParty/XCC/Xtensa/port.c
@@ -1,3 +1,4 @@
+
/*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
@@ -59,155 +60,146 @@
/* Defined in portasm.h */
-extern void _frxt_tick_timer_init( void );
+extern void _frxt_tick_timer_init(void);
/* Defined in xtensa_context.S */
-extern void _xt_coproc_init( void );
+extern void _xt_coproc_init(void);
/*-----------------------------------------------------------*/
/* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
typedef void TCB_t;
extern volatile TCB_t * volatile pxCurrentTCB;
-unsigned port_xSchedulerRunning = 0; /* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */
-unsigned port_interruptNesting = 0; /* Interrupt nesting level */
+unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
+unsigned port_interruptNesting = 0; // Interrupt nesting level
/*-----------------------------------------------------------*/
-/* User exception dispatcher when exiting */
-void _xt_user_exit( void );
+// User exception dispatcher when exiting
+void _xt_user_exit(void);
-/*
+/*
* Stack initialization
*/
#if portUSING_MPU_WRAPPERS
- StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters,
- BaseType_t xRunPrivileged )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
#else
- StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
#endif
{
- StackType_t * sp, * tp;
- XtExcFrame * frame;
+ StackType_t *sp, *tp;
+ XtExcFrame *frame;
+ #if XCHAL_CP_NUM > 0
+ uint32_t *p;
+ #endif
- #if XCHAL_CP_NUM > 0
- uint32_t * p;
- #endif
+ /* Create interrupt stack frame aligned to 16 byte boundary */
+ sp = (StackType_t *) (((UBaseType_t)(pxTopOfStack + 1) - XT_CP_SIZE - XT_STK_FRMSZ) & ~0xf);
- /* Create interrupt stack frame aligned to 16 byte boundary */
- sp = ( StackType_t * ) ( ( ( UBaseType_t ) ( pxTopOfStack + 1 ) - XT_CP_SIZE - XT_STK_FRMSZ ) & ~0xf );
+ /* Clear the entire frame (do not use memset() because we don't depend on C library) */
+ for (tp = sp; tp <= pxTopOfStack; ++tp)
+ *tp = 0;
- /* Clear the entire frame (do not use memset() because we don't depend on C library) */
- for( tp = sp; tp <= pxTopOfStack; ++tp )
- {
- *tp = 0;
- }
+ frame = (XtExcFrame *) sp;
- frame = ( XtExcFrame * ) sp;
+ /* Explicitly initialize certain saved registers */
+ frame->pc = (UBaseType_t) pxCode; /* task entrypoint */
+ frame->a0 = 0; /* to terminate GDB backtrace */
+ frame->a1 = (UBaseType_t) sp + XT_STK_FRMSZ; /* physical top of stack frame */
+ frame->exit = (UBaseType_t) _xt_user_exit; /* user exception exit dispatcher */
- /* Explicitly initialize certain saved registers */
- frame->pc = ( UBaseType_t ) pxCode; /* task entrypoint */
- frame->a0 = 0; /* to terminate GDB backtrace */
- frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ; /* physical top of stack frame */
- frame->exit = ( UBaseType_t ) _xt_user_exit; /* user exception exit dispatcher */
+ /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
+ /* Also set entry point argument parameter. */
+ #ifdef __XTENSA_CALL0_ABI__
+ frame->a2 = (UBaseType_t) pvParameters;
+ frame->ps = PS_UM | PS_EXCM;
+ #else
+ /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
+ frame->a6 = (UBaseType_t) pvParameters;
+ frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);
+ #endif
- /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
- /* Also set entry point argument parameter. */
- #ifdef __XTENSA_CALL0_ABI__
- frame->a2 = ( UBaseType_t ) pvParameters;
- frame->ps = PS_UM | PS_EXCM;
- #else
- /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
- frame->a6 = ( UBaseType_t ) pvParameters;
- frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 );
- #endif
+ #ifdef XT_USE_SWPRI
+ /* Set the initial virtual priority mask value to all 1's. */
+ frame->vpri = 0xFFFFFFFF;
+ #endif
- #ifdef XT_USE_SWPRI
- /* Set the initial virtual priority mask value to all 1's. */
- frame->vpri = 0xFFFFFFFF;
- #endif
-
- #if XCHAL_CP_NUM > 0
- /* Init the coprocessor save area (see xtensa_context.h) */
-
- /* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
+ #if XCHAL_CP_NUM > 0
+ /* Init the coprocessor save area (see xtensa_context.h) */
+ /* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
* //p = (uint32_t *) xMPUSettings->coproc_area;
- */
- p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf );
- p[ 0 ] = 0;
- p[ 1 ] = 0;
- p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN;
- #endif
+ */
+ p = (uint32_t *)(((uint32_t) pxTopOfStack - XT_CP_SIZE) & ~0xf);
+ p[0] = 0;
+ p[1] = 0;
+ p[2] = (((uint32_t) p) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN;
+ #endif
- return sp;
+ return sp;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* It is unlikely that the Xtensa port will get stopped. If required simply
- * disable the tick interrupt here. */
+ /* It is unlikely that the Xtensa port will get stopped. If required simply
+ disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored */
+ // Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
- #if XCHAL_CP_NUM > 0
- /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
- _xt_coproc_init();
- #endif
+ #if XCHAL_CP_NUM > 0
+ /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
+ _xt_coproc_init();
+ #endif
- /* Init the tick divisor value */
- _xt_tick_divisor_init();
+ /* Init the tick divisor value */
+ _xt_tick_divisor_init();
- /* Setup the hardware to generate the tick. */
- _frxt_tick_timer_init();
+ /* Setup the hardware to generate the tick. */
+ _frxt_tick_timer_init();
- #if XT_USE_THREAD_SAFE_CLIB
- /* Init C library */
- vPortClibInit();
- #endif
+ #if XT_USE_THREAD_SAFE_CLIB
+ // Init C library
+ vPortClibInit();
+ #endif
- port_xSchedulerRunning = 1;
+ port_xSchedulerRunning = 1;
- /* Cannot be directly called from C; never returns */
- __asm__ volatile ( "call0 _frxt_dispatch\n" );
+ // Cannot be directly called from C; never returns
+ __asm__ volatile ("call0 _frxt_dispatch\n");
- /* Should not get here. */
- return pdTRUE;
+ /* Should not get here. */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
BaseType_t xPortSysTickHandler( void )
{
- BaseType_t ret;
- uint32_t interruptMask;
+ BaseType_t ret;
+ uint32_t interruptMask;
- portbenchmarkIntLatency();
+ portbenchmarkIntLatency();
- /* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be
- * disabled before calling xTaskIncrementTick as it access the
- * kernel lists. */
- interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- ret = xTaskIncrementTick();
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );
+ /* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be
+ * disabled before calling xTaskIncrementTick as it access the
+ * kernel lists. */
+ interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ ret = xTaskIncrementTick();
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );
- portYIELD_FROM_ISR( ret );
+ portYIELD_FROM_ISR( ret );
- return ret;
+ return ret;
}
/*-----------------------------------------------------------*/
@@ -215,18 +207,16 @@
* Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
*/
#if portUSING_MPU_WRAPPERS
- void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
- const struct xMEMORY_REGION * const xRegions,
- StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
- {
- #if XCHAL_CP_NUM > 0
- xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 ) ) - XT_CP_SIZE ) & ~0xf );
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+{
+ #if XCHAL_CP_NUM > 0
+ xMPUSettings->coproc_area = (StackType_t*)((((uint32_t)(pxBottomOfStack + ulStackDepth - 1)) - XT_CP_SIZE ) & ~0xf);
- /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
- * clear the stack area after we return. This is done in pxPortInitialiseStack().
- */
- #endif
- }
-#endif /* if portUSING_MPU_WRAPPERS */
+ /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
+ * clear the stack area after we return. This is done in pxPortInitialiseStack().
+ */
+ #endif
+}
+#endif
+
diff --git a/portable/ThirdParty/XCC/Xtensa/portbenchmark.h b/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
index 6cbf847..3df6103 100644
--- a/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
+++ b/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -36,7 +37,7 @@
#endif
#define portbenchmarkINTERRUPT_DISABLE()
-#define portbenchmarkINTERRUPT_RESTORE( newstate )
+#define portbenchmarkINTERRUPT_RESTORE(newstate)
#define portbenchmarkIntLatency()
#define portbenchmarkIntWait()
#define portbenchmarkReset()
diff --git a/portable/ThirdParty/XCC/Xtensa/portclib.c b/portable/ThirdParty/XCC/Xtensa/portclib.c
index 67d13bb..7268923 100644
--- a/portable/ThirdParty/XCC/Xtensa/portclib.c
+++ b/portable/ThirdParty/XCC/Xtensa/portclib.c
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -25,204 +26,200 @@
#if XT_USE_THREAD_SAFE_CLIB
- #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
- #include <errno.h>
- #include <sys/reent.h>
+#include <errno.h>
+#include <sys/reent.h>
- #include "semphr.h"
+#include "semphr.h"
- typedef SemaphoreHandle_t _Rmtx;
+typedef SemaphoreHandle_t _Rmtx;
-/*----------------------------------------------------------------------------- */
-/* Override this and set to nonzero to enable locking. */
-/*----------------------------------------------------------------------------- */
- int32_t _xclib_use_mt = 1;
+//-----------------------------------------------------------------------------
+// Override this and set to nonzero to enable locking.
+//-----------------------------------------------------------------------------
+int32_t _xclib_use_mt = 1;
-/*----------------------------------------------------------------------------- */
-/* Init lock. */
-/*----------------------------------------------------------------------------- */
- void _Mtxinit( _Rmtx * mtx )
- {
- *mtx = xSemaphoreCreateRecursiveMutex();
- }
+//-----------------------------------------------------------------------------
+// Init lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxinit(_Rmtx * mtx)
+{
+ *mtx = xSemaphoreCreateRecursiveMutex();
+}
-/*----------------------------------------------------------------------------- */
-/* Destroy lock. */
-/*----------------------------------------------------------------------------- */
- void _Mtxdst( _Rmtx * mtx )
- {
- if( ( mtx != NULL ) && ( *mtx != NULL ) )
- {
- vSemaphoreDelete( *mtx );
- }
- }
+//-----------------------------------------------------------------------------
+// Destroy lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxdst(_Rmtx * mtx)
+{
+ if ((mtx != NULL) && (*mtx != NULL)) {
+ vSemaphoreDelete(*mtx);
+ }
+}
-/*----------------------------------------------------------------------------- */
-/* Lock. */
-/*----------------------------------------------------------------------------- */
- void _Mtxlock( _Rmtx * mtx )
- {
- if( ( mtx != NULL ) && ( *mtx != NULL ) )
- {
- xSemaphoreTakeRecursive( *mtx, portMAX_DELAY );
- }
- }
+//-----------------------------------------------------------------------------
+// Lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxlock(_Rmtx * mtx)
+{
+ if ((mtx != NULL) && (*mtx != NULL)) {
+ xSemaphoreTakeRecursive(*mtx, portMAX_DELAY);
+ }
+}
-/*----------------------------------------------------------------------------- */
-/* Unlock. */
-/*----------------------------------------------------------------------------- */
- void _Mtxunlock( _Rmtx * mtx )
- {
- if( ( mtx != NULL ) && ( *mtx != NULL ) )
- {
- xSemaphoreGiveRecursive( *mtx );
- }
- }
+//-----------------------------------------------------------------------------
+// Unlock.
+//-----------------------------------------------------------------------------
+void
+_Mtxunlock(_Rmtx * mtx)
+{
+ if ((mtx != NULL) && (*mtx != NULL)) {
+ xSemaphoreGiveRecursive(*mtx);
+ }
+}
-/*----------------------------------------------------------------------------- */
-/* Called by malloc() to allocate blocks of memory from the heap. */
-/*----------------------------------------------------------------------------- */
- void * _sbrk_r( struct _reent * reent,
- int32_t incr )
- {
- extern char _end;
- extern char _heap_sentry;
- static char * _heap_sentry_ptr = &_heap_sentry;
- static char * heap_ptr;
- char * base;
+//-----------------------------------------------------------------------------
+// Called by malloc() to allocate blocks of memory from the heap.
+//-----------------------------------------------------------------------------
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+ extern char _end;
+ extern char _heap_sentry;
+ static char * _heap_sentry_ptr = &_heap_sentry;
+ static char * heap_ptr;
+ char * base;
- if( !heap_ptr )
- {
- heap_ptr = ( char * ) &_end;
- }
+ if (!heap_ptr)
+ heap_ptr = (char *) &_end;
- base = heap_ptr;
+ base = heap_ptr;
+ if (heap_ptr + incr >= _heap_sentry_ptr) {
+ reent->_errno = ENOMEM;
+ return (char *) -1;
+ }
- if( heap_ptr + incr >= _heap_sentry_ptr )
- {
- reent->_errno = ENOMEM;
- return ( char * ) -1;
- }
+ heap_ptr += incr;
+ return base;
+}
- heap_ptr += incr;
- return base;
- }
+//-----------------------------------------------------------------------------
+// Global initialization for C library.
+//-----------------------------------------------------------------------------
+void
+vPortClibInit(void)
+{
+}
-/*----------------------------------------------------------------------------- */
-/* Global initialization for C library. */
-/*----------------------------------------------------------------------------- */
- void vPortClibInit( void )
- {
- }
+//-----------------------------------------------------------------------------
+// Per-thread cleanup stub provided for linking, does nothing.
+//-----------------------------------------------------------------------------
+void
+_reclaim_reent(void * ptr)
+{
+}
-/*----------------------------------------------------------------------------- */
-/* Per-thread cleanup stub provided for linking, does nothing. */
-/*----------------------------------------------------------------------------- */
- void _reclaim_reent( void * ptr )
- {
- }
+#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
- #endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
- #if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+#include <errno.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
- #include <errno.h>
- #include <malloc.h>
- #include <stdio.h>
- #include <stdlib.h>
- #include <string.h>
+#include "semphr.h"
- #include "semphr.h"
+static SemaphoreHandle_t xClibMutex;
+static uint32_t ulClibInitDone = 0;
- static SemaphoreHandle_t xClibMutex;
- static uint32_t ulClibInitDone = 0;
+//-----------------------------------------------------------------------------
+// Get C library lock.
+//-----------------------------------------------------------------------------
+void
+__malloc_lock(struct _reent * ptr)
+{
+ if (!ulClibInitDone)
+ return;
-/*----------------------------------------------------------------------------- */
-/* Get C library lock. */
-/*----------------------------------------------------------------------------- */
- void __malloc_lock( struct _reent * ptr )
- {
- if( !ulClibInitDone )
- {
- return;
- }
+ xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY);
+}
- xSemaphoreTakeRecursive( xClibMutex, portMAX_DELAY );
- }
+//-----------------------------------------------------------------------------
+// Release C library lock.
+//-----------------------------------------------------------------------------
+void
+__malloc_unlock(struct _reent * ptr)
+{
+ if (!ulClibInitDone)
+ return;
-/*----------------------------------------------------------------------------- */
-/* Release C library lock. */
-/*----------------------------------------------------------------------------- */
- void __malloc_unlock( struct _reent * ptr )
- {
- if( !ulClibInitDone )
- {
- return;
- }
+ xSemaphoreGiveRecursive(xClibMutex);
+}
- xSemaphoreGiveRecursive( xClibMutex );
- }
-
-/*----------------------------------------------------------------------------- */
-/* Lock for environment. Since we have only one global lock we can just call */
-/* the malloc() lock function. */
-/*----------------------------------------------------------------------------- */
- void __env_lock( struct _reent * ptr )
- {
- __malloc_lock( ptr );
- }
+//-----------------------------------------------------------------------------
+// Lock for environment. Since we have only one global lock we can just call
+// the malloc() lock function.
+//-----------------------------------------------------------------------------
+void
+__env_lock(struct _reent * ptr)
+{
+ __malloc_lock(ptr);
+}
-/*----------------------------------------------------------------------------- */
-/* Unlock environment. */
-/*----------------------------------------------------------------------------- */
- void __env_unlock( struct _reent * ptr )
- {
- __malloc_unlock( ptr );
- }
+//-----------------------------------------------------------------------------
+// Unlock environment.
+//-----------------------------------------------------------------------------
+void
+__env_unlock(struct _reent * ptr)
+{
+ __malloc_unlock(ptr);
+}
-/*----------------------------------------------------------------------------- */
-/* Called by malloc() to allocate blocks of memory from the heap. */
-/*----------------------------------------------------------------------------- */
- void * _sbrk_r( struct _reent * reent,
- int32_t incr )
- {
- extern char _end;
- extern char _heap_sentry;
- static char * _heap_sentry_ptr = &_heap_sentry;
- static char * heap_ptr;
- char * base;
+//-----------------------------------------------------------------------------
+// Called by malloc() to allocate blocks of memory from the heap.
+//-----------------------------------------------------------------------------
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+ extern char _end;
+ extern char _heap_sentry;
+ static char * _heap_sentry_ptr = &_heap_sentry;
+ static char * heap_ptr;
+ char * base;
- if( !heap_ptr )
- {
- heap_ptr = ( char * ) &_end;
- }
+ if (!heap_ptr)
+ heap_ptr = (char *) &_end;
- base = heap_ptr;
+ base = heap_ptr;
+ if (heap_ptr + incr >= _heap_sentry_ptr) {
+ reent->_errno = ENOMEM;
+ return (char *) -1;
+ }
- if( heap_ptr + incr >= _heap_sentry_ptr )
- {
- reent->_errno = ENOMEM;
- return ( char * ) -1;
- }
+ heap_ptr += incr;
+ return base;
+}
- heap_ptr += incr;
- return base;
- }
+//-----------------------------------------------------------------------------
+// Global initialization for C library.
+//-----------------------------------------------------------------------------
+void
+vPortClibInit(void)
+{
+ configASSERT(!ulClibInitDone);
-/*----------------------------------------------------------------------------- */
-/* Global initialization for C library. */
-/*----------------------------------------------------------------------------- */
- void vPortClibInit( void )
- {
- configASSERT( !ulClibInitDone );
+ xClibMutex = xSemaphoreCreateRecursiveMutex();
+ ulClibInitDone = 1;
+}
- xClibMutex = xSemaphoreCreateRecursiveMutex();
- ulClibInitDone = 1;
- }
-
- #endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
+#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
#endif /* XT_USE_THREAD_SAFE_CLIB */
diff --git a/portable/ThirdParty/XCC/Xtensa/portmacro.h b/portable/ThirdParty/XCC/Xtensa/portmacro.h
index d0f68d8..edf48aa 100644
--- a/portable/ThirdParty/XCC/Xtensa/portmacro.h
+++ b/portable/ThirdParty/XCC/Xtensa/portmacro.h
@@ -1,3 +1,4 @@
+
/*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
@@ -50,23 +51,23 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
- #ifndef __ASSEMBLER__
+#ifndef __ASSEMBLER__
- #include <stdint.h>
+#include <stdint.h>
- #include <xtensa/tie/xt_core.h>
- #include <xtensa/hal.h>
- #include <xtensa/config/core.h>
- #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
- #include <xtensa/xtruntime.h>
+#include <xtensa/tie/xt_core.h>
+#include <xtensa/hal.h>
+#include <xtensa/config/core.h>
+#include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+#include <xtensa/xtruntime.h>
-/*#include "xtensa_context.h" */
+//#include "xtensa_context.h"
/*-----------------------------------------------------------
* Port specific definitions.
@@ -80,165 +81,156 @@
/* Type definitions. */
- #define portCHAR int8_t
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG int32_t
- #define portSHORT int16_t
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE int
+#define portCHAR int8_t
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG int32_t
+#define portSHORT int16_t
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE int
- typedef portSTACK_TYPE StackType_t;
- typedef portBASE_TYPE BaseType_t;
- typedef unsigned portBASE_TYPE UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef unsigned portBASE_TYPE UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
-/* portbenchmark */
- #include "portbenchmark.h"
+// portbenchmark
+#include "portbenchmark.h"
/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
-/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */
- #define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 )
- #define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 )
+// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level.
+#define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)
+#define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)
-/* These can be nested */
- #define portCRITICAL_NESTING_IN_TCB 1 /* For now, let FreeRTOS' (tasks.c) manage critical nesting */
- void vTaskEnterCritical( void );
- void vTaskExitCritical( void );
- #define portENTER_CRITICAL() vTaskEnterCritical()
- #define portEXIT_CRITICAL() vTaskExitCritical()
+// These can be nested
+#define portCRITICAL_NESTING_IN_TCB 1 // For now, let FreeRTOS' (tasks.c) manage critical nesting
+void vTaskEnterCritical(void);
+void vTaskExitCritical(void);
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
-/* Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack. */
-/* They can be called from interrupts too. */
- static inline unsigned portENTER_CRITICAL_NESTED()
- {
- unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
+// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack.
+// They can be called from interrupts too.
+static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; }
+#define portEXIT_CRITICAL_NESTED(state) do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0)
- portbenchmarkINTERRUPT_DISABLE();
- return state;
- }
- #define portEXIT_CRITICAL_NESTED( state ) do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 )
-
-/* These FreeRTOS versions are similar to the nested versions above */
- #define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state ) portEXIT_CRITICAL_NESTED( state )
+// These FreeRTOS versions are similar to the nested versions above
+#define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state) portEXIT_CRITICAL_NESTED(state)
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 4
- #define portNOP() XT_NOP()
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() XT_NOP()
/*-----------------------------------------------------------*/
/* Fine resolution time */
- #define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount()
+#define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount()
/* Kernel utilities. */
- void vPortYield( void );
- void _frxt_setup_switch( void );
- #define portYIELD() vPortYield()
- #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) \
- if( ( xHigherPriorityTaskWoken ) != 0 ) { \
- _frxt_setup_switch(); \
- }
+void vPortYield( void );
+void _frxt_setup_switch( void );
+#define portYIELD() vPortYield()
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) \
+ if ( ( xHigherPriorityTaskWoken ) != 0 ) { \
+ _frxt_setup_switch(); \
+ }
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/* When coprocessors are defined, we to maintain a pointer to coprocessors area. */
-/* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */
-/* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */
-/* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */
- typedef struct
- {
- #if XCHAL_CP_NUM > 0
- volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */
- #endif
+// When coprocessors are defined, we to maintain a pointer to coprocessors area.
+// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:
+// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.
+// The field is normally used for memory protection. FreeRTOS should create another general purpose field.
+typedef struct {
+ #if XCHAL_CP_NUM > 0
+ volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST
+ #endif
- #if portUSING_MPU_WRAPPERS
- /* Define here mpu_settings, which is port dependent */
- int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */
- #endif
+ #if portUSING_MPU_WRAPPERS
+ // Define here mpu_settings, which is port dependent
+ int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet
+ #endif
- #if configUSE_TRACE_FACILITY_2
- struct
- {
- /* Cf. porttraceStamp() */
- int taskstamp; /* Stamp from inside task to see where we are */
- int taskstampcount; /* A counter usually incremented when we restart the task's loop */
- } porttrace;
- #endif
- } xMPU_SETTINGS;
+ #if configUSE_TRACE_FACILITY_2
+ struct {
+ // Cf. porttraceStamp()
+ int taskstamp; /* Stamp from inside task to see where we are */
+ int taskstampcount; /* A counter usually incremented when we restart the task's loop */
+ } porttrace;
+ #endif
+} xMPU_SETTINGS;
-/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */
- #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */
- #undef portUSING_MPU_WRAPPERS
- #define portUSING_MPU_WRAPPERS 1 /* Enable it to allocate coproc area */
- #define MPU_WRAPPERS_H /* Override mpu_wrapper.h to disable unwanted code */
- #define PRIVILEGED_FUNCTION
- #define PRIVILEGED_DATA
- #endif
+// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)
+#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS // If MPU wrappers not used, we still need to allocate coproc area
+ #undef portUSING_MPU_WRAPPERS
+ #define portUSING_MPU_WRAPPERS 1 // Enable it to allocate coproc area
+ #define MPU_WRAPPERS_H // Override mpu_wrapper.h to disable unwanted code
+ #define PRIVILEGED_FUNCTION
+ #define PRIVILEGED_DATA
+#endif
-/* porttrace */
- #if configUSE_TRACE_FACILITY_2
- #include "porttrace.h"
- #endif
+// porttrace
+#if configUSE_TRACE_FACILITY_2
+#include "porttrace.h"
+#endif
-/* configASSERT_2 if requested */
- #if configASSERT_2
- #include <stdio.h>
- void exit( int );
- #define configASSERT( x ) if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); }
- #endif
+// configASSERT_2 if requested
+#if configASSERT_2
+#include <stdio.h>
+void exit(int);
+#define configASSERT( x ) if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); }
+#endif
/* C library support -- only XCLIB and NEWLIB are supported. */
/* To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must be
- * defined to be > 0 somewhere above or on the command line. */
+ defined to be > 0 somewhere above or on the command line. */
- #if ( XT_USE_THREAD_SAFE_CLIB > 0u ) && ( XSHAL_CLIB == XTHAL_CLIB_XCLIB )
- extern void vPortClibInit( void );
+#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
+extern void vPortClibInit(void);
-/* No cleanup necessary at this time. */
- #define portCLEAN_UP_TCB( pxTCB )
- #endif // XCLIB support
+// No cleanup necessary at this time.
+#define portCLEAN_UP_TCB(pxTCB)
+#endif // XCLIB support
- #if ( XT_USE_THREAD_SAFE_CLIB > 0u ) && ( XSHAL_CLIB == XTHAL_CLIB_NEWLIB )
- extern void vPortClibInit( void );
+#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_NEWLIB)
+extern void vPortClibInit(void);
-/* This C library cleanup is not currently done by FreeRTOS when deleting a task */
- #include <stdio.h>
- #define portCLEAN_UP_TCB( pxTCB ) vPortCleanUpTcbClib( &( ( pxTCB )->xNewLib_reent ) )
- static inline void vPortCleanUpTcbClib( struct _reent * ptr )
- {
- FILE * fp = &( ptr->__sf[ 0 ] );
- int i;
+// This C library cleanup is not currently done by FreeRTOS when deleting a task
+#include <stdio.h>
+#define portCLEAN_UP_TCB(pxTCB) vPortCleanUpTcbClib(&((pxTCB)->xNewLib_reent))
+static inline void vPortCleanUpTcbClib(struct _reent *ptr)
+{
+ FILE * fp = &(ptr->__sf[0]);
+ int i;
+ for (i = 0; i < 3; ++i, ++fp) {
+ fp->_close = NULL;
+ }
+}
+#endif // NEWLIB support
- for( i = 0; i < 3; ++i, ++fp )
- {
- fp->_close = NULL;
- }
- }
- #endif // NEWLIB support
+#endif // __ASSEMBLER__
- #endif // __ASSEMBLER__
-
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/ThirdParty/XCC/Xtensa/porttrace.h b/portable/ThirdParty/XCC/Xtensa/porttrace.h
index 827a061..498444b 100644
--- a/portable/ThirdParty/XCC/Xtensa/porttrace.h
+++ b/portable/ThirdParty/XCC/Xtensa/porttrace.h
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -25,7 +26,7 @@
* This utility helps tracing the entering and exiting from tasks.
* It maintains a circular buffer of tasks in the order they execute,
* and their execution time. To enable it, set configUSE_TRACE_FACILITY_2
- * to 1 in FreeRTOSConfig.h. You will also need to download the
+ * to 1 in FreeRTOSConfig.h. You will also need to download the
* FreeRTOS_trace patch that contains porttrace.c and the complete version
* of porttrace.h.
*/
@@ -37,7 +38,7 @@
#error "You need to download the FreeRTOS_trace patch that overwrites this file"
#endif
-#define porttracePrint( nelements )
-#define porttraceStamp( stamp, count_incr )
+#define porttracePrint(nelements)
+#define porttraceStamp(stamp, count_incr)
#endif /* PORTTRACE_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_api.h b/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
index 8334a35..1be2905 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -34,91 +35,89 @@
/* Typedef for C-callable interrupt handler function */
-typedef void (* xt_handler)( void * );
+typedef void (*xt_handler)(void *);
/* Typedef for C-callable exception handler function */
-typedef void (* xt_exc_handler)( XtExcFrame * );
+typedef void (*xt_exc_handler)(XtExcFrame *);
/*
- * -------------------------------------------------------------------------------
- * Call this function to set a handler for the specified exception.
- *
- * n - Exception number (type)
- * f - Handler function address, NULL to uninstall handler.
- *
- * The handler will be passed a pointer to the exception frame, which is created
- * on the stack of the thread that caused the exception.
- *
- * If the handler returns, the thread context will be restored and the faulting
- * instruction will be retried. Any values in the exception frame that are
- * modified by the handler will be restored as part of the context. For details
- * of the exception frame structure see xtensa_context.h.
- * -------------------------------------------------------------------------------
- */
-extern xt_exc_handler xt_set_exception_handler( int n,
- xt_exc_handler f );
+-------------------------------------------------------------------------------
+ Call this function to set a handler for the specified exception.
+
+ n - Exception number (type)
+ f - Handler function address, NULL to uninstall handler.
+
+ The handler will be passed a pointer to the exception frame, which is created
+ on the stack of the thread that caused the exception.
+
+ If the handler returns, the thread context will be restored and the faulting
+ instruction will be retried. Any values in the exception frame that are
+ modified by the handler will be restored as part of the context. For details
+ of the exception frame structure see xtensa_context.h.
+-------------------------------------------------------------------------------
+*/
+extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
/*
- * -------------------------------------------------------------------------------
- * Call this function to set a handler for the specified interrupt.
- *
- * n - Interrupt number.
- * f - Handler function address, NULL to uninstall handler.
- * arg - Argument to be passed to handler.
- * -------------------------------------------------------------------------------
- */
-extern xt_handler xt_set_interrupt_handler( int n,
- xt_handler f,
- void * arg );
+-------------------------------------------------------------------------------
+ Call this function to set a handler for the specified interrupt.
+
+ n - Interrupt number.
+ f - Handler function address, NULL to uninstall handler.
+ arg - Argument to be passed to handler.
+-------------------------------------------------------------------------------
+*/
+extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
/*
- * -------------------------------------------------------------------------------
- * Call this function to enable the specified interrupts.
- *
- * mask - Bit mask of interrupts to be enabled.
- *
- * Returns the previous state of the interrupt enables.
- * -------------------------------------------------------------------------------
- */
-extern unsigned int xt_ints_on( unsigned int mask );
+-------------------------------------------------------------------------------
+ Call this function to enable the specified interrupts.
+
+ mask - Bit mask of interrupts to be enabled.
+
+ Returns the previous state of the interrupt enables.
+-------------------------------------------------------------------------------
+*/
+extern unsigned int xt_ints_on(unsigned int mask);
/*
- * -------------------------------------------------------------------------------
- * Call this function to disable the specified interrupts.
- *
- * mask - Bit mask of interrupts to be disabled.
- *
- * Returns the previous state of the interrupt enables.
- * -------------------------------------------------------------------------------
- */
-extern unsigned int xt_ints_off( unsigned int mask );
+-------------------------------------------------------------------------------
+ Call this function to disable the specified interrupts.
+
+ mask - Bit mask of interrupts to be disabled.
+
+ Returns the previous state of the interrupt enables.
+-------------------------------------------------------------------------------
+*/
+extern unsigned int xt_ints_off(unsigned int mask);
/*
- * -------------------------------------------------------------------------------
- * Call this function to set the specified (s/w) interrupt.
- * -------------------------------------------------------------------------------
- */
-static inline void xt_set_intset( unsigned int arg )
+-------------------------------------------------------------------------------
+ Call this function to set the specified (s/w) interrupt.
+-------------------------------------------------------------------------------
+*/
+static inline void xt_set_intset(unsigned int arg)
{
- xthal_set_intset( arg );
+ xthal_set_intset(arg);
}
/*
- * -------------------------------------------------------------------------------
- * Call this function to clear the specified (s/w or edge-triggered)
- * interrupt.
- * -------------------------------------------------------------------------------
- */
-static inline void xt_set_intclear( unsigned int arg )
+-------------------------------------------------------------------------------
+ Call this function to clear the specified (s/w or edge-triggered)
+ interrupt.
+-------------------------------------------------------------------------------
+*/
+static inline void xt_set_intclear(unsigned int arg)
{
- xthal_set_intclear( arg );
+ xthal_set_intclear(arg);
}
#endif /* __XTENSA_API_H__ */
+
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
index 07b1f91..308361f 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -31,151 +32,152 @@
*/
#ifndef XTENSA_CONFIG_H
- #define XTENSA_CONFIG_H
+#define XTENSA_CONFIG_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
- #include <xtensa/hal.h>
- #include <xtensa/config/core.h>
- #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+#include <xtensa/hal.h>
+#include <xtensa/config/core.h>
+#include <xtensa/config/system.h> /* required for XSHAL_CLIB */
- #include "xtensa_context.h"
+#include "xtensa_context.h"
/*-----------------------------------------------------------------------------
- * STACK REQUIREMENTS
- *
- * This section defines the minimum stack size, and the extra space required to
- * be allocated for saving coprocessor state and/or C library state information
- * (if thread safety is enabled for the C library). The sizes are in bytes.
- *
- * Stack sizes for individual tasks should be derived from these minima based on
- * the maximum call depth of the task and the maximum level of interrupt nesting.
- * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
- * on the requirement for a task that calls nothing else but can be interrupted.
- * This assumes that interrupt handlers do not call more than a few levels deep.
- * If this is not true, i.e. one or more interrupt handlers make deep calls then
- * the minimum must be increased.
- *
- * If the Xtensa processor configuration includes coprocessors, then space is
- * allocated to save the coprocessor state on the stack.
- *
- * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
- * is defined) then space is allocated to save the C library context in the TCB.
- *
- * Allocating insufficient stack space is a common source of hard-to-find errors.
- * During development, it is best to enable the FreeRTOS stack checking features.
- *
- * Usage:
- *
- * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
- * use of the C library. This will require extra stack
- * space to be allocated for tasks that use the C library
- * reentrant functions. See below for more information.
- *
- * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
- * support thread safety. Check your core configuration to see which C library
- * was chosen for your system.
- *
- * XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended
- * that you do not use a stack smaller than this for any
- * task. In case you want to use stacks smaller than this
- * size, you must verify that the smaller size(s) will work
- * under all operating conditions.
- *
- * XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task
- * that does not make C library reentrant calls. Add this
- * to the amount of stack space required by the task itself.
- *
- * XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state.
- *
- * -----------------------------------------------------------------------------*/
+* STACK REQUIREMENTS
+*
+* This section defines the minimum stack size, and the extra space required to
+* be allocated for saving coprocessor state and/or C library state information
+* (if thread safety is enabled for the C library). The sizes are in bytes.
+*
+* Stack sizes for individual tasks should be derived from these minima based on
+* the maximum call depth of the task and the maximum level of interrupt nesting.
+* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
+* on the requirement for a task that calls nothing else but can be interrupted.
+* This assumes that interrupt handlers do not call more than a few levels deep.
+* If this is not true, i.e. one or more interrupt handlers make deep calls then
+* the minimum must be increased.
+*
+* If the Xtensa processor configuration includes coprocessors, then space is
+* allocated to save the coprocessor state on the stack.
+*
+* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
+* is defined) then space is allocated to save the C library context in the TCB.
+*
+* Allocating insufficient stack space is a common source of hard-to-find errors.
+* During development, it is best to enable the FreeRTOS stack checking features.
+*
+* Usage:
+*
+* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
+* use of the C library. This will require extra stack
+* space to be allocated for tasks that use the C library
+* reentrant functions. See below for more information.
+*
+* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
+* support thread safety. Check your core configuration to see which C library
+* was chosen for your system.
+*
+* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended
+* that you do not use a stack smaller than this for any
+* task. In case you want to use stacks smaller than this
+* size, you must verify that the smaller size(s) will work
+* under all operating conditions.
+*
+* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task
+* that does not make C library reentrant calls. Add this
+* to the amount of stack space required by the task itself.
+*
+* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state.
+*
+-----------------------------------------------------------------------------*/
/* Extra space required for interrupt/exception hooks. */
- #ifdef XT_INTEXC_HOOKS
- #ifdef __XTENSA_CALL0_ABI__
- #define STK_INTEXC_EXTRA 0x200
- #else
- #define STK_INTEXC_EXTRA 0x180
- #endif
- #else
- #define STK_INTEXC_EXTRA 0
- #endif
+#ifdef XT_INTEXC_HOOKS
+ #ifdef __XTENSA_CALL0_ABI__
+ #define STK_INTEXC_EXTRA 0x200
+ #else
+ #define STK_INTEXC_EXTRA 0x180
+ #endif
+#else
+ #define STK_INTEXC_EXTRA 0
+#endif
/* Check C library thread safety support and compute size of C library save area.
- * For the supported libraries, we enable thread safety by default, and this can
- * be overridden from the compiler/make command line. */
- #if ( XSHAL_CLIB == XTHAL_CLIB_NEWLIB ) || ( XSHAL_CLIB == XTHAL_CLIB_XCLIB )
- #ifndef XT_USE_THREAD_SAFE_CLIB
- #define XT_USE_THREAD_SAFE_CLIB 1
- #endif
- #else
- #define XT_USE_THREAD_SAFE_CLIB 0
+ For the supported libraries, we enable thread safety by default, and this can
+ be overridden from the compiler/make command line. */
+#if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
+ #ifndef XT_USE_THREAD_SAFE_CLIB
+ #define XT_USE_THREAD_SAFE_CLIB 1
+ #endif
+#else
+ #define XT_USE_THREAD_SAFE_CLIB 0
+#endif
+
+#if XT_USE_THREAD_SAFE_CLIB > 0u
+ #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+ #define XT_HAVE_THREAD_SAFE_CLIB 1
+ #if !defined __ASSEMBLER__
+ #include <sys/reent.h>
+ #define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16))
+ #define XT_CLIB_GLOBAL_PTR _reent_ptr
+ #define _REENT_INIT_PTR _init_reent
+ #define _impure_ptr _reent_ptr
+
+ void _reclaim_reent(void * ptr);
#endif
-
- #if XT_USE_THREAD_SAFE_CLIB > 0u
- #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
- #define XT_HAVE_THREAD_SAFE_CLIB 1
- #if !defined __ASSEMBLER__
- #include <sys/reent.h>
- #define XT_CLIB_CONTEXT_AREA_SIZE ( ( sizeof( struct _reent ) + 15 ) + ( -16 ) )
- #define XT_CLIB_GLOBAL_PTR _reent_ptr
- #define _REENT_INIT_PTR _init_reent
- #define _impure_ptr _reent_ptr
-
- void _reclaim_reent( void * ptr );
- #endif
- #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
- #define XT_HAVE_THREAD_SAFE_CLIB 1
- #if !defined __ASSEMBLER__
- #include <sys/reent.h>
- #define XT_CLIB_CONTEXT_AREA_SIZE ( ( sizeof( struct _reent ) + 15 ) + ( -16 ) )
- #define XT_CLIB_GLOBAL_PTR _impure_ptr
- #endif
- #else /* if XSHAL_CLIB == XTHAL_CLIB_XCLIB */
- #define XT_HAVE_THREAD_SAFE_CLIB 0
- #error The selected C runtime library is not thread safe.
- #endif /* if XSHAL_CLIB == XTHAL_CLIB_XCLIB */
- #else /* if XT_USE_THREAD_SAFE_CLIB > 0u */
- #define XT_CLIB_CONTEXT_AREA_SIZE 0
- #endif /* if XT_USE_THREAD_SAFE_CLIB > 0u */
+ #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+ #define XT_HAVE_THREAD_SAFE_CLIB 1
+ #if !defined __ASSEMBLER__
+ #include <sys/reent.h>
+ #define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16))
+ #define XT_CLIB_GLOBAL_PTR _impure_ptr
+ #endif
+ #else
+ #define XT_HAVE_THREAD_SAFE_CLIB 0
+ #error The selected C runtime library is not thread safe.
+ #endif
+#else
+ #define XT_CLIB_CONTEXT_AREA_SIZE 0
+#endif
/*------------------------------------------------------------------------------
- * Extra size -- interrupt frame plus coprocessor save area plus hook space.
- * NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
- * ------------------------------------------------------------------------------*/
- #ifdef __XTENSA_CALL0_ABI__
- #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
- #else
- #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE )
- #endif
+ Extra size -- interrupt frame plus coprocessor save area plus hook space.
+ NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
+------------------------------------------------------------------------------*/
+#ifdef __XTENSA_CALL0_ABI__
+ #define XT_XTRA_SIZE (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)
+#else
+ #define XT_XTRA_SIZE (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)
+#endif
/*------------------------------------------------------------------------------
- * Space allocated for user code -- function calls and local variables.
- * NOTE: This number can be adjusted to suit your needs. You must verify that the
- * amount of space you reserve is adequate for the worst-case conditions in your
- * application.
- * NOTE: The windowed ABI requires more stack, since space has to be reserved
- * for spilling register windows.
- * ------------------------------------------------------------------------------*/
- #ifdef __XTENSA_CALL0_ABI__
- #define XT_USER_SIZE 0x200
- #else
- #define XT_USER_SIZE 0x400
- #endif
+ Space allocated for user code -- function calls and local variables.
+ NOTE: This number can be adjusted to suit your needs. You must verify that the
+ amount of space you reserve is adequate for the worst-case conditions in your
+ application.
+ NOTE: The windowed ABI requires more stack, since space has to be reserved
+ for spilling register windows.
+------------------------------------------------------------------------------*/
+#ifdef __XTENSA_CALL0_ABI__
+ #define XT_USER_SIZE 0x200
+#else
+ #define XT_USER_SIZE 0x400
+#endif
/* Minimum recommended stack size. */
- #define XT_STACK_MIN_SIZE ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) )
+#define XT_STACK_MIN_SIZE ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))
/* OS overhead with and without C library thread context. */
- #define XT_STACK_EXTRA ( XT_XTRA_SIZE )
- #define XT_STACK_EXTRA_CLIB ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE )
+#define XT_STACK_EXTRA (XT_XTRA_SIZE)
+#define XT_STACK_EXTRA_CLIB (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* XTENSA_CONFIG_H */
+
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
index 695d441..122d236 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -38,7 +39,7 @@
#define XTENSA_CONTEXT_H
#ifdef __ASSEMBLER__
- #include <xtensa/coreasm.h>
+#include <xtensa/coreasm.h>
#endif
#include <xtensa/config/tie.h>
@@ -47,310 +48,304 @@
/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
-#define ALIGNUP( n, val ) ( ( ( val ) + ( n ) - 1 ) & -( n ) )
+#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
/*
- * -------------------------------------------------------------------------------
- * Macros that help define structures for both C and assembler.
- * -------------------------------------------------------------------------------
- */
-#if defined( _ASMLANGUAGE ) || defined( __ASSEMBLER__ )
+-------------------------------------------------------------------------------
+ Macros that help define structures for both C and assembler.
+-------------------------------------------------------------------------------
+*/
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
- #define STRUCT_BEGIN .pushsection.text; .struct 0
- #define STRUCT_FIELD( ctype, size, asname, name ) asname:.space size
- #define STRUCT_AFIELD( ctype, size, asname, name, n ) asname:.space( size ) *( n )
- #define STRUCT_END( sname ) sname ## Size:; .popsection
+#define STRUCT_BEGIN .pushsection .text; .struct 0
+#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size
+#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n)
+#define STRUCT_END(sname) sname##Size:; .popsection
#else
- #define STRUCT_BEGIN typedef struct {
- #define STRUCT_FIELD( ctype, size, asname, name ) ctype name;
- #define STRUCT_AFIELD( ctype, size, asname, name, n ) ctype name[ n ];
- #define STRUCT_END( sname ) \
- } \
- sname;
+#define STRUCT_BEGIN typedef struct {
+#define STRUCT_FIELD(ctype,size,asname,name) ctype name;
+#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];
+#define STRUCT_END(sname) } sname;
#endif //_ASMLANGUAGE || __ASSEMBLER__
/*
- * -------------------------------------------------------------------------------
- * INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
- *
- * A stack frame of this structure is allocated for any interrupt or exception.
- * It goes on the current stack. If the RTOS has a system stack for handling
- * interrupts, every thread stack must allow space for just one interrupt stack
- * frame, then nested interrupt stack frames go on the system stack.
- *
- * The frame includes basic registers (explicit) and "extra" registers introduced
- * by user TIE or the use of the MAC16 option in the user's Xtensa config.
- * The frame size is minimized by omitting regs not applicable to user's config.
- *
- * For Windowed ABI, this stack frame includes the interruptee's base save area,
- * another base save area to manage gcc nested functions, and a little temporary
- * space to help manage the spilling of the register windows.
- * -------------------------------------------------------------------------------
- */
+-------------------------------------------------------------------------------
+ INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
-STRUCT_BEGIN STRUCT_FIELD( long,
- 4,
- XT_STK_EXIT,
- exit ) /* exit point for dispatch */
-STRUCT_FIELD( long, 4, XT_STK_PC, pc ) /* return PC */
-STRUCT_FIELD( long, 4, XT_STK_PS, ps ) /* return PS */
-STRUCT_FIELD( long, 4, XT_STK_A0, a0 )
-STRUCT_FIELD( long, 4, XT_STK_A1, a1 ) /* stack pointer before interrupt */
-STRUCT_FIELD( long, 4, XT_STK_A2, a2 )
-STRUCT_FIELD( long, 4, XT_STK_A3, a3 )
-STRUCT_FIELD( long, 4, XT_STK_A4, a4 )
-STRUCT_FIELD( long, 4, XT_STK_A5, a5 )
-STRUCT_FIELD( long, 4, XT_STK_A6, a6 )
-STRUCT_FIELD( long, 4, XT_STK_A7, a7 )
-STRUCT_FIELD( long, 4, XT_STK_A8, a8 )
-STRUCT_FIELD( long, 4, XT_STK_A9, a9 )
-STRUCT_FIELD( long, 4, XT_STK_A10, a10 )
-STRUCT_FIELD( long, 4, XT_STK_A11, a11 )
-STRUCT_FIELD( long, 4, XT_STK_A12, a12 )
-STRUCT_FIELD( long, 4, XT_STK_A13, a13 )
-STRUCT_FIELD( long, 4, XT_STK_A14, a14 )
-STRUCT_FIELD( long, 4, XT_STK_A15, a15 )
-STRUCT_FIELD( long, 4, XT_STK_SAR, sar )
-STRUCT_FIELD( long, 4, XT_STK_EXCCAUSE, exccause )
-STRUCT_FIELD( long, 4, XT_STK_EXCVADDR, excvaddr )
+ A stack frame of this structure is allocated for any interrupt or exception.
+ It goes on the current stack. If the RTOS has a system stack for handling
+ interrupts, every thread stack must allow space for just one interrupt stack
+ frame, then nested interrupt stack frames go on the system stack.
+
+ The frame includes basic registers (explicit) and "extra" registers introduced
+ by user TIE or the use of the MAC16 option in the user's Xtensa config.
+ The frame size is minimized by omitting regs not applicable to user's config.
+
+ For Windowed ABI, this stack frame includes the interruptee's base save area,
+ another base save area to manage gcc nested functions, and a little temporary
+ space to help manage the spilling of the register windows.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */
+STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */
+STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */
+STRUCT_FIELD (long, 4, XT_STK_A0, a0)
+STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */
+STRUCT_FIELD (long, 4, XT_STK_A2, a2)
+STRUCT_FIELD (long, 4, XT_STK_A3, a3)
+STRUCT_FIELD (long, 4, XT_STK_A4, a4)
+STRUCT_FIELD (long, 4, XT_STK_A5, a5)
+STRUCT_FIELD (long, 4, XT_STK_A6, a6)
+STRUCT_FIELD (long, 4, XT_STK_A7, a7)
+STRUCT_FIELD (long, 4, XT_STK_A8, a8)
+STRUCT_FIELD (long, 4, XT_STK_A9, a9)
+STRUCT_FIELD (long, 4, XT_STK_A10, a10)
+STRUCT_FIELD (long, 4, XT_STK_A11, a11)
+STRUCT_FIELD (long, 4, XT_STK_A12, a12)
+STRUCT_FIELD (long, 4, XT_STK_A13, a13)
+STRUCT_FIELD (long, 4, XT_STK_A14, a14)
+STRUCT_FIELD (long, 4, XT_STK_A15, a15)
+STRUCT_FIELD (long, 4, XT_STK_SAR, sar)
+STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
+STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
#if XCHAL_HAVE_LOOPS
- STRUCT_FIELD( long, 4, XT_STK_LBEG, lbeg )
- STRUCT_FIELD( long, 4, XT_STK_LEND, lend )
- STRUCT_FIELD( long, 4, XT_STK_LCOUNT, lcount )
+STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg)
+STRUCT_FIELD (long, 4, XT_STK_LEND, lend)
+STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
#endif
#ifndef __XTENSA_CALL0_ABI__
/* Temporary space for saving stuff during window spill */
- STRUCT_FIELD( long, 4, XT_STK_TMP0, tmp0 )
- STRUCT_FIELD( long, 4, XT_STK_TMP1, tmp1 )
- STRUCT_FIELD( long, 4, XT_STK_TMP2, tmp2 )
+STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0)
+STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1)
+STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2)
#endif
#ifdef XT_USE_SWPRI
/* Storage for virtual priority mask */
- STRUCT_FIELD( long, 4, XT_STK_VPRI, vpri )
+STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri)
#endif
#ifdef XT_USE_OVLY
/* Storage for overlay state */
- STRUCT_FIELD( long, 4, XT_STK_OVLY, ovly )
+STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly)
#endif
-STRUCT_END( XtExcFrame )
+STRUCT_END(XtExcFrame)
-#if defined( _ASMLANGUAGE ) || defined( __ASSEMBLER__ )
-#define XT_STK_NEXT1 XtExcFrameSize
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+#define XT_STK_NEXT1 XtExcFrameSize
#else
-#define XT_STK_NEXT1 sizeof( XtExcFrame )
+#define XT_STK_NEXT1 sizeof(XtExcFrame)
#endif
/* Allocate extra storage if needed */
#if XCHAL_EXTRA_SA_SIZE != 0
- #if XCHAL_EXTRA_SA_ALIGN <= 16
-#define XT_STK_EXTRA ALIGNUP( XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1 )
- #else
+#if XCHAL_EXTRA_SA_ALIGN <= 16
+#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
+#else
/* If need more alignment than stack, add space for dynamic alignment */
-#define XT_STK_EXTRA ( ALIGNUP( XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1 ) + XCHAL_EXTRA_SA_ALIGN )
- #endif
-#define XT_STK_NEXT2 ( XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE )
+#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
+#endif
+#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
#else
-#define XT_STK_NEXT2 XT_STK_NEXT1
+#define XT_STK_NEXT2 XT_STK_NEXT1
-#endif /* if XCHAL_EXTRA_SA_SIZE != 0 */
+#endif
/*
- * -------------------------------------------------------------------------------
- * This is the frame size. Add space for 4 registers (interruptee's base save
- * area) and some space for gcc nested functions if any.
- * -------------------------------------------------------------------------------
- */
-#define XT_STK_FRMSZ ( ALIGNUP( 0x10, XT_STK_NEXT2 ) + 0x20 )
+-------------------------------------------------------------------------------
+ This is the frame size. Add space for 4 registers (interruptee's base save
+ area) and some space for gcc nested functions if any.
+-------------------------------------------------------------------------------
+*/
+#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
/*
- * -------------------------------------------------------------------------------
- * SOLICITED STACK FRAME FOR A THREAD
- *
- * A stack frame of this structure is allocated whenever a thread enters the
- * RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
- * It goes on the current thread's stack.
- *
- * The solicited frame only includes registers that are required to be preserved
- * by the callee according to the compiler's ABI conventions, some space to save
- * the return address for returning to the caller, and the caller's PS register.
- *
- * For Windowed ABI, this stack frame includes the caller's base save area.
- *
- * Note on XT_SOL_EXIT field:
- * It is necessary to distinguish a solicited from an interrupt stack frame.
- * This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
- * always at the same offset (0). It can be written with a code (usually 0)
- * to distinguish a solicted frame from an interrupt frame. An RTOS port may
- * opt to ignore this field if it has another way of distinguishing frames.
- * -------------------------------------------------------------------------------
- */
+-------------------------------------------------------------------------------
+ SOLICITED STACK FRAME FOR A THREAD
+
+ A stack frame of this structure is allocated whenever a thread enters the
+ RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
+ It goes on the current thread's stack.
+
+ The solicited frame only includes registers that are required to be preserved
+ by the callee according to the compiler's ABI conventions, some space to save
+ the return address for returning to the caller, and the caller's PS register.
+
+ For Windowed ABI, this stack frame includes the caller's base save area.
+
+ Note on XT_SOL_EXIT field:
+ It is necessary to distinguish a solicited from an interrupt stack frame.
+ This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
+ always at the same offset (0). It can be written with a code (usually 0)
+ to distinguish a solicted frame from an interrupt frame. An RTOS port may
+ opt to ignore this field if it has another way of distinguishing frames.
+-------------------------------------------------------------------------------
+*/
STRUCT_BEGIN
#ifdef __XTENSA_CALL0_ABI__
- STRUCT_FIELD( long,
- 4,
- XT_SOL_EXIT,
- exit )
- STRUCT_FIELD( long, 4, XT_SOL_PC, pc )
- STRUCT_FIELD( long, 4, XT_SOL_PS, ps )
- STRUCT_FIELD( long, 4, XT_SOL_NEXT, next )
- STRUCT_FIELD( long, 4, XT_SOL_A12, a12 ) /* should be on 16-byte alignment */
- STRUCT_FIELD( long, 4, XT_SOL_A13, a13 )
- STRUCT_FIELD( long, 4, XT_SOL_A14, a14 )
- STRUCT_FIELD( long, 4, XT_SOL_A15, a15 )
-#else /* ifdef __XTENSA_CALL0_ABI__ */
- STRUCT_FIELD( long, 4, XT_SOL_EXIT, exit )
- STRUCT_FIELD( long, 4, XT_SOL_PC, pc )
- STRUCT_FIELD( long, 4, XT_SOL_PS, ps )
- STRUCT_FIELD( long, 4, XT_SOL_NEXT, next )
- STRUCT_FIELD( long, 4, XT_SOL_A0, a0 ) /* should be on 16-byte alignment */
- STRUCT_FIELD( long, 4, XT_SOL_A1, a1 )
- STRUCT_FIELD( long, 4, XT_SOL_A2, a2 )
- STRUCT_FIELD( long, 4, XT_SOL_A3, a3 )
-#endif /* ifdef __XTENSA_CALL0_ABI__ */
-STRUCT_END( XtSolFrame )
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A13, a13)
+STRUCT_FIELD (long, 4, XT_SOL_A14, a14)
+STRUCT_FIELD (long, 4, XT_SOL_A15, a15)
+#else
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A1, a1)
+STRUCT_FIELD (long, 4, XT_SOL_A2, a2)
+STRUCT_FIELD (long, 4, XT_SOL_A3, a3)
+#endif
+STRUCT_END(XtSolFrame)
/* Size of solicited stack frame */
-#define XT_SOL_FRMSZ ALIGNUP( 0x10, XtSolFrameSize )
+#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize)
/*
- * -------------------------------------------------------------------------------
- * CO-PROCESSOR STATE SAVE AREA FOR A THREAD
- *
- * The RTOS must provide an area per thread to save the state of co-processors
- * when that thread does not have control. Co-processors are context-switched
- * lazily (on demand) only when a new thread uses a co-processor instruction,
- * otherwise a thread retains ownership of the co-processor even when it loses
- * control of the processor. An Xtensa co-processor exception is triggered when
- * any co-processor instruction is executed by a thread that is not the owner,
- * and the context switch of that co-processor is then peformed by the handler.
- * Ownership represents which thread's state is currently in the co-processor.
- *
- * Co-processors may not be used by interrupt or exception handlers. If an
- * co-processor instruction is executed by an interrupt or exception handler,
- * the co-processor exception handler will trigger a kernel panic and freeze.
- * This restriction is introduced to reduce the overhead of saving and restoring
- * co-processor state (which can be quite large) and in particular remove that
- * overhead from interrupt handlers.
- *
- * The co-processor state save area may be in any convenient per-thread location
- * such as in the thread control block or above the thread stack area. It need
- * not be in the interrupt stack frame since interrupts don't use co-processors.
- *
- * Along with the save area for each co-processor, two bitmasks with flags per
- * co-processor (laid out as in the CPENABLE reg) help manage context-switching
- * co-processors as efficiently as possible:
- *
- * XT_CPENABLE
- * The contents of a non-running thread's CPENABLE register.
- * It represents the co-processors owned (and whose state is still needed)
- * by the thread. When a thread is preempted, its CPENABLE is saved here.
- * When a thread solicits a context-swtich, its CPENABLE is cleared - the
- * compiler has saved the (caller-saved) co-proc state if it needs to.
- * When a non-running thread loses ownership of a CP, its bit is cleared.
- * When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
- * Avoids co-processor exceptions when no change of ownership is needed.
- *
- * XT_CPSTORED
- * A bitmask with the same layout as CPENABLE, a bit per co-processor.
- * Indicates whether the state of each co-processor is saved in the state
- * save area. When a thread enters the kernel, only the state of co-procs
- * still enabled in CPENABLE is saved. When the co-processor exception
- * handler assigns ownership of a co-processor to a thread, it restores
- * the saved state only if this bit is set, and clears this bit.
- *
- * XT_CP_CS_ST
- * A bitmask with the same layout as CPENABLE, a bit per co-processor.
- * Indicates whether callee-saved state is saved in the state save area.
- * Callee-saved state is saved by itself on a solicited context switch,
- * and restored when needed by the coprocessor exception handler.
- * Unsolicited switches will cause the entire coprocessor to be saved
- * when necessary.
- *
- * XT_CP_ASA
- * Pointer to the aligned save area. Allows it to be aligned more than
- * the overall save area (which might only be stack-aligned or TCB-aligned).
- * Especially relevant for Xtensa cores configured with a very large data
- * path that requires alignment greater than 16 bytes (ABI stack alignment).
- * -------------------------------------------------------------------------------
- */
+-------------------------------------------------------------------------------
+ CO-PROCESSOR STATE SAVE AREA FOR A THREAD
+
+ The RTOS must provide an area per thread to save the state of co-processors
+ when that thread does not have control. Co-processors are context-switched
+ lazily (on demand) only when a new thread uses a co-processor instruction,
+ otherwise a thread retains ownership of the co-processor even when it loses
+ control of the processor. An Xtensa co-processor exception is triggered when
+ any co-processor instruction is executed by a thread that is not the owner,
+ and the context switch of that co-processor is then peformed by the handler.
+ Ownership represents which thread's state is currently in the co-processor.
+
+ Co-processors may not be used by interrupt or exception handlers. If an
+ co-processor instruction is executed by an interrupt or exception handler,
+ the co-processor exception handler will trigger a kernel panic and freeze.
+ This restriction is introduced to reduce the overhead of saving and restoring
+ co-processor state (which can be quite large) and in particular remove that
+ overhead from interrupt handlers.
+
+ The co-processor state save area may be in any convenient per-thread location
+ such as in the thread control block or above the thread stack area. It need
+ not be in the interrupt stack frame since interrupts don't use co-processors.
+
+ Along with the save area for each co-processor, two bitmasks with flags per
+ co-processor (laid out as in the CPENABLE reg) help manage context-switching
+ co-processors as efficiently as possible:
+
+ XT_CPENABLE
+ The contents of a non-running thread's CPENABLE register.
+ It represents the co-processors owned (and whose state is still needed)
+ by the thread. When a thread is preempted, its CPENABLE is saved here.
+ When a thread solicits a context-swtich, its CPENABLE is cleared - the
+ compiler has saved the (caller-saved) co-proc state if it needs to.
+ When a non-running thread loses ownership of a CP, its bit is cleared.
+ When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
+ Avoids co-processor exceptions when no change of ownership is needed.
+
+ XT_CPSTORED
+ A bitmask with the same layout as CPENABLE, a bit per co-processor.
+ Indicates whether the state of each co-processor is saved in the state
+ save area. When a thread enters the kernel, only the state of co-procs
+ still enabled in CPENABLE is saved. When the co-processor exception
+ handler assigns ownership of a co-processor to a thread, it restores
+ the saved state only if this bit is set, and clears this bit.
+
+ XT_CP_CS_ST
+ A bitmask with the same layout as CPENABLE, a bit per co-processor.
+ Indicates whether callee-saved state is saved in the state save area.
+ Callee-saved state is saved by itself on a solicited context switch,
+ and restored when needed by the coprocessor exception handler.
+ Unsolicited switches will cause the entire coprocessor to be saved
+ when necessary.
+
+ XT_CP_ASA
+ Pointer to the aligned save area. Allows it to be aligned more than
+ the overall save area (which might only be stack-aligned or TCB-aligned).
+ Especially relevant for Xtensa cores configured with a very large data
+ path that requires alignment greater than 16 bytes (ABI stack alignment).
+-------------------------------------------------------------------------------
+*/
#if XCHAL_CP_NUM > 0
/* Offsets of each coprocessor save area within the 'aligned save area': */
-#define XT_CP0_SA 0
-#define XT_CP1_SA ALIGNUP( XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE )
-#define XT_CP2_SA ALIGNUP( XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE )
-#define XT_CP3_SA ALIGNUP( XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE )
-#define XT_CP4_SA ALIGNUP( XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE )
-#define XT_CP5_SA ALIGNUP( XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE )
-#define XT_CP6_SA ALIGNUP( XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE )
-#define XT_CP7_SA ALIGNUP( XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE )
-#define XT_CP_SA_SIZE ALIGNUP( 16, XT_CP7_SA + XCHAL_CP7_SA_SIZE )
+#define XT_CP0_SA 0
+#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
+#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
+#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
+#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
+#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
+#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
+#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
+#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
/* Offsets within the overall save area: */
-#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */
-#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */
-#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */
-#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */
+#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */
+#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */
+#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */
+#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */
/* Overall size allows for dynamic alignment: */
-#define XT_CP_SIZE ( 12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN )
-#else /* if XCHAL_CP_NUM > 0 */
-#define XT_CP_SIZE 0
-#endif /* if XCHAL_CP_NUM > 0 */
+#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
+#else
+#define XT_CP_SIZE 0
+#endif
/*
- * -------------------------------------------------------------------------------
- * MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
- *
- * Convenient where the frame size requirements are the same for both ABIs.
- * ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
- * ENTRY0, RET0 are for frameless functions (no locals, no calls).
- *
- * where size = size of stack frame in bytes (must be >0 and aligned to 16).
- * For framed functions the frame is created and the return address saved at
- * base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
- * For frameless functions, there is no frame and return address remains in a0.
- * Note: Because CPP macros expand to a single line, macros requiring multi-line
- * expansions are implemented as assembler macros.
- * -------------------------------------------------------------------------------
- */
+-------------------------------------------------------------------------------
+ MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
+
+ Convenient where the frame size requirements are the same for both ABIs.
+ ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
+ ENTRY0, RET0 are for frameless functions (no locals, no calls).
+
+ where size = size of stack frame in bytes (must be >0 and aligned to 16).
+ For framed functions the frame is created and the return address saved at
+ base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
+ For frameless functions, there is no frame and return address remains in a0.
+ Note: Because CPP macros expand to a single line, macros requiring multi-line
+ expansions are implemented as assembler macros.
+-------------------------------------------------------------------------------
+*/
#ifdef __ASSEMBLER__
- #ifdef __XTENSA_CALL0_ABI__
- /* Call0 */
-#define ENTRY( sz ) entry1 sz
- .macro entry1 size = 0x10
- addi sp, sp, -\ size
- s32i a0, sp, 0
- .endm
-#define ENTRY0
-#define RET( sz ) ret1 sz
- .macro ret1 size = 0x10
- l32i a0, sp, 0
- addi sp, sp, \ size
- ret
- .endm
-#define RET0 ret
- #else /* ifdef __XTENSA_CALL0_ABI__ */
- /* Windowed */
-#define ENTRY( sz ) entry sp, sz
-#define ENTRY0 entry sp, 0x10
-#define RET( sz ) retw
-#define RET0 retw
- #endif /* ifdef __XTENSA_CALL0_ABI__ */
-#endif /* ifdef __ASSEMBLER__ */
+#ifdef __XTENSA_CALL0_ABI__
+ /* Call0 */
+ #define ENTRY(sz) entry1 sz
+ .macro entry1 size=0x10
+ addi sp, sp, -\size
+ s32i a0, sp, 0
+ .endm
+ #define ENTRY0
+ #define RET(sz) ret1 sz
+ .macro ret1 size=0x10
+ l32i a0, sp, 0
+ addi sp, sp, \size
+ ret
+ .endm
+ #define RET0 ret
+#else
+ /* Windowed */
+ #define ENTRY(sz) entry sp, sz
+ #define ENTRY0 entry sp, 0x10
+ #define RET(sz) retw
+ #define RET0 retw
+#endif
+#endif
#endif /* XTENSA_CONTEXT_H */
+
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_init.c b/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
index f227186..da8bf2d 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -30,31 +31,36 @@
#ifdef XT_BOARD
- #include <xtensa/xtbsp.h>
+#include <xtensa/xtbsp.h>
#endif
#include "xtensa_rtos.h"
#ifdef XT_RTOS_TIMER_INT
- unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */
+unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */
/*
- * Compute and initialize at run-time the tick divisor (the number of
- * processor clock cycles in an RTOS tick, used to set the tick timer).
- * Called when the processor clock frequency is not known at compile-time.
- */
- void _xt_tick_divisor_init( void )
- {
- #ifdef XT_CLOCK_FREQ
- _xt_tick_divisor = ( XT_CLOCK_FREQ / XT_TICK_PER_SEC );
- #else
- #ifdef XT_BOARD
- _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
- #else
- #error "No way to obtain processor clock frequency"
- #endif /* XT_BOARD */
- #endif /* XT_CLOCK_FREQ */
- }
+Compute and initialize at run-time the tick divisor (the number of
+processor clock cycles in an RTOS tick, used to set the tick timer).
+Called when the processor clock frequency is not known at compile-time.
+*/
+void _xt_tick_divisor_init(void)
+{
+#ifdef XT_CLOCK_FREQ
+
+ _xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC);
+
+#else
+
+ #ifdef XT_BOARD
+ _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
+ #else
+ #error "No way to obtain processor clock frequency"
+ #endif /* XT_BOARD */
+
+#endif /* XT_CLOCK_FREQ */
+}
#endif /* XT_RTOS_TIMER_INT */
+
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
index b79c9ed..846aafb 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -37,110 +38,96 @@
/* Handler table is in xtensa_intr_asm.S */
- extern xt_exc_handler _xt_exception_table[ XCHAL_EXCCAUSE_NUM ];
+extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];
/*
- * Default handler for unhandled exceptions.
- */
- void xt_unhandled_exception( XtExcFrame * frame )
- {
- exit( -1 );
- }
+ Default handler for unhandled exceptions.
+*/
+void xt_unhandled_exception(XtExcFrame *frame)
+{
+ exit(-1);
+}
/*
- * This function registers a handler for the specified exception.
- * The function returns the address of the previous handler.
- * On error, it returns 0.
- */
- xt_exc_handler xt_set_exception_handler( int n,
- xt_exc_handler f )
- {
- xt_exc_handler old;
+ This function registers a handler for the specified exception.
+ The function returns the address of the previous handler.
+ On error, it returns 0.
+*/
+xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f)
+{
+ xt_exc_handler old;
- if( ( n < 0 ) || ( n >= XCHAL_EXCCAUSE_NUM ) )
- {
- return 0; /* invalid exception number */
- }
+ if( n < 0 || n >= XCHAL_EXCCAUSE_NUM )
+ return 0; /* invalid exception number */
- old = _xt_exception_table[ n ];
+ old = _xt_exception_table[n];
- if( f )
- {
- _xt_exception_table[ n ] = f;
- }
- else
- {
- _xt_exception_table[ n ] = &xt_unhandled_exception;
- }
-
- return( ( old == &xt_unhandled_exception ) ? 0 : old );
+ if (f) {
+ _xt_exception_table[n] = f;
+ }
+ else {
+ _xt_exception_table[n] = &xt_unhandled_exception;
}
-#endif /* if XCHAL_HAVE_EXCEPTIONS */
+ return ((old == &xt_unhandled_exception) ? 0 : old);
+}
+
+#endif
#if XCHAL_HAVE_INTERRUPTS
/* Handler table is in xtensa_intr_asm.S */
- typedef struct xt_handler_table_entry
- {
- void * handler;
- void * arg;
- } xt_handler_table_entry;
+typedef struct xt_handler_table_entry {
+ void * handler;
+ void * arg;
+} xt_handler_table_entry;
- extern xt_handler_table_entry _xt_interrupt_table[ XCHAL_NUM_INTERRUPTS ];
+extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS];
/*
- * Default handler for unhandled interrupts.
- */
- void xt_unhandled_interrupt( void * arg )
- {
- exit( -1 );
- }
+ Default handler for unhandled interrupts.
+*/
+void xt_unhandled_interrupt(void * arg)
+{
+ exit(-1);
+}
/*
- * This function registers a handler for the specified interrupt. The "arg"
- * parameter specifies the argument to be passed to the handler when it is
- * invoked. The function returns the address of the previous handler.
- * On error, it returns 0.
- */
- xt_handler xt_set_interrupt_handler( int n,
- xt_handler f,
- void * arg )
- {
- xt_handler_table_entry * entry;
- xt_handler old;
+ This function registers a handler for the specified interrupt. The "arg"
+ parameter specifies the argument to be passed to the handler when it is
+ invoked. The function returns the address of the previous handler.
+ On error, it returns 0.
+*/
+xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)
+{
+ xt_handler_table_entry * entry;
+ xt_handler old;
- if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) )
- {
- return 0; /* invalid interrupt number */
- }
+ if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
+ return 0; /* invalid interrupt number */
+ if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL )
+ return 0; /* priority level too high to safely handle in C */
- if( Xthal_intlevel[ n ] > XCHAL_EXCM_LEVEL )
- {
- return 0; /* priority level too high to safely handle in C */
- }
+ entry = _xt_interrupt_table + n;
+ old = entry->handler;
- entry = _xt_interrupt_table + n;
- old = entry->handler;
-
- if( f )
- {
- entry->handler = f;
- entry->arg = arg;
- }
- else
- {
- entry->handler = &xt_unhandled_interrupt;
- entry->arg = ( void * ) n;
- }
-
- return( ( old == &xt_unhandled_interrupt ) ? 0 : old );
+ if (f) {
+ entry->handler = f;
+ entry->arg = arg;
}
+ else {
+ entry->handler = &xt_unhandled_interrupt;
+ entry->arg = (void*)n;
+ }
+
+ return ((old == &xt_unhandled_interrupt) ? 0 : old);
+}
#endif /* XCHAL_HAVE_INTERRUPTS */
+
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c b/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
index f82d2d6..050b495 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -33,7 +34,7 @@
/* Mutex object that controls access to the overlay. Currently only one
* overlay region is supported so one mutex suffices.
*/
- static SemaphoreHandle_t xt_overlay_mutex;
+static SemaphoreHandle_t xt_overlay_mutex;
/* This function should be overridden to provide OS specific init such
@@ -41,30 +42,30 @@
* Typically this mutex would be set up with priority inheritance. See
* overlay manager documentation for more details.
*/
- void xt_overlay_init_os( void )
- {
- /* Create the mutex for overlay access. Priority inheritance is
- * required.
- */
- xt_overlay_mutex = xSemaphoreCreateMutex();
- }
+void xt_overlay_init_os(void)
+{
+ /* Create the mutex for overlay access. Priority inheritance is
+ * required.
+ */
+ xt_overlay_mutex = xSemaphoreCreateMutex();
+}
/* This function locks access to shared overlay resources, typically
* by acquiring a mutex.
*/
- void xt_overlay_lock( void )
- {
- xSemaphoreTake( xt_overlay_mutex, 0 );
- }
+void xt_overlay_lock(void)
+{
+ xSemaphoreTake(xt_overlay_mutex, 0);
+}
/* This function releases access to shared overlay resources, typically
* by unlocking a mutex.
*/
- void xt_overlay_unlock( void )
- {
- xSemaphoreGive( xt_overlay_mutex );
- }
+void xt_overlay_unlock(void)
+{
+ xSemaphoreGive(xt_overlay_mutex);
+}
-#endif /* if configUSE_MUTEX */
+#endif
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h b/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
index 2123a7f..207a76c 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -32,10 +33,10 @@
* Macros in this header map callouts from generic Xtensa files to specific
* RTOS functions. It may also be included in C source files.
*
- * Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
- * architecture, using the Xtensa hardware abstraction layer (HAL) to deal
+ * Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
+ * architecture, using the Xtensa hardware abstraction layer (HAL) to deal
* with configuration specifics.
- *
+ *
* Should be included by all Xtensa generic and RTOS port-specific sources.
*/
@@ -43,9 +44,9 @@
#define XTENSA_RTOS_H
#ifdef __ASSEMBLER__
- #include <xtensa/coreasm.h>
+#include <xtensa/coreasm.h>
#else
- #include <xtensa/config/core.h>
+#include <xtensa/config/core.h>
#endif
#include <xtensa/corebits.h>
@@ -53,180 +54,181 @@
#include <xtensa/simcall.h>
/*
- * Include any RTOS specific definitions that are needed by this header.
- */
+Include any RTOS specific definitions that are needed by this header.
+*/
#include <FreeRTOSConfig.h>
/*
- * Convert FreeRTOSConfig definitions to XTENSA definitions.
- * However these can still be overridden from the command line.
- */
+Convert FreeRTOSConfig definitions to XTENSA definitions.
+However these can still be overridden from the command line.
+*/
#ifndef XT_SIMULATOR
- #if configXT_SIMULATOR
- #define XT_SIMULATOR 1 /* Simulator mode */
- #endif
+ #if configXT_SIMULATOR
+ #define XT_SIMULATOR 1 /* Simulator mode */
+ #endif
#endif
#ifndef XT_BOARD
- #if configXT_BOARD
- #define XT_BOARD 1 /* Board mode */
- #endif
+ #if configXT_BOARD
+ #define XT_BOARD 1 /* Board mode */
+ #endif
#endif
#ifndef XT_TIMER_INDEX
- #if defined configXT_TIMER_INDEX
- #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */
- #endif
+ #if defined configXT_TIMER_INDEX
+ #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */
+ #endif
#endif
#ifndef XT_INTEXC_HOOKS
- #if configXT_INTEXC_HOOKS
- #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */
- #endif
+ #if configXT_INTEXC_HOOKS
+ #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */
+ #endif
#endif
-#if ( !XT_SIMULATOR ) && ( !XT_BOARD )
- #error Either XT_SIMULATOR or XT_BOARD must be defined.
+#if (!XT_SIMULATOR) && (!XT_BOARD)
+ #error Either XT_SIMULATOR or XT_BOARD must be defined.
#endif
/*
- * Name of RTOS (for messages).
- */
+Name of RTOS (for messages).
+*/
#define XT_RTOS_NAME FreeRTOS
/*
- * Check some Xtensa configuration requirements and report error if not met.
- * Error messages can be customize to the RTOS port.
- */
+Check some Xtensa configuration requirements and report error if not met.
+Error messages can be customize to the RTOS port.
+*/
#if !XCHAL_HAVE_XEA2
- #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
+#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
#endif
/*******************************************************************************
-*
-* RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
-*
-* Define callout macros used in generic Xtensa code to interact with the RTOS.
-* The macros are simply the function names for use in calls from assembler code.
-* Some of these functions may call back to generic functions in xtensa_context.h .
-*
+
+RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
+
+Define callout macros used in generic Xtensa code to interact with the RTOS.
+The macros are simply the function names for use in calls from assembler code.
+Some of these functions may call back to generic functions in xtensa_context.h .
+
*******************************************************************************/
/*
- * Inform RTOS of entry into an interrupt handler that will affect it.
- * Allows RTOS to manage switch to any system stack and count nesting level.
- * Called after minimal context has been saved, with interrupts disabled.
- * RTOS port can call0 _xt_context_save to save the rest of the context.
- * May only be called from assembly code by the 'call0' instruction.
- */
-/* void XT_RTOS_INT_ENTER(void) */
-#define XT_RTOS_INT_ENTER _frxt_int_enter
+Inform RTOS of entry into an interrupt handler that will affect it.
+Allows RTOS to manage switch to any system stack and count nesting level.
+Called after minimal context has been saved, with interrupts disabled.
+RTOS port can call0 _xt_context_save to save the rest of the context.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_ENTER(void)
+#define XT_RTOS_INT_ENTER _frxt_int_enter
/*
- * Inform RTOS of completion of an interrupt handler, and give control to
- * RTOS to perform thread/task scheduling, switch back from any system stack
- * and restore the context, and return to the exit dispatcher saved in the
- * stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
- * to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
- * leaving only a minimal part of the context to be restored by the exit
- * dispatcher. This function does not return to the place it was called from.
- * May only be called from assembly code by the 'call0' instruction.
- */
-/* void XT_RTOS_INT_EXIT(void) */
+Inform RTOS of completion of an interrupt handler, and give control to
+RTOS to perform thread/task scheduling, switch back from any system stack
+and restore the context, and return to the exit dispatcher saved in the
+stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
+to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
+leaving only a minimal part of the context to be restored by the exit
+dispatcher. This function does not return to the place it was called from.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_EXIT(void)
#define XT_RTOS_INT_EXIT _frxt_int_exit
/*
- * Inform RTOS of the occurrence of a tick timer interrupt.
- * If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
- * May be coded in or called from C or assembly, per ABI conventions.
- * RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
- */
-/* void XT_RTOS_TIMER_INT(void) */
-#define XT_RTOS_TIMER_INT _frxt_timer_int
-#define XT_TICK_PER_SEC configTICK_RATE_HZ
+Inform RTOS of the occurrence of a tick timer interrupt.
+If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
+May be coded in or called from C or assembly, per ABI conventions.
+RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
+*/
+// void XT_RTOS_TIMER_INT(void)
+#define XT_RTOS_TIMER_INT _frxt_timer_int
+#define XT_TICK_PER_SEC configTICK_RATE_HZ
/*
- * Return in a15 the base address of the co-processor state save area for the
- * thread that triggered a co-processor exception, or 0 if no thread was running.
- * The state save area is structured as defined in xtensa_context.h and has size
- * XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
- * in interrupt handlers or the RTOS kernel. May only be called from assembly code
- * and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
- * The implementation may use only a2-4, a15 (all other regs must be preserved).
- */
-/* void* XT_RTOS_CP_STATE(void) */
+Return in a15 the base address of the co-processor state save area for the
+thread that triggered a co-processor exception, or 0 if no thread was running.
+The state save area is structured as defined in xtensa_context.h and has size
+XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
+in interrupt handlers or the RTOS kernel. May only be called from assembly code
+and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
+The implementation may use only a2-4, a15 (all other regs must be preserved).
+*/
+// void* XT_RTOS_CP_STATE(void)
#define XT_RTOS_CP_STATE _frxt_task_coproc_state
/*******************************************************************************
-*
-* HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
-*
-* This Xtensa RTOS port provides hooks for dynamically installing exception
-* and interrupt handlers to facilitate automated testing where each test
-* case can install its own handler for user exceptions and each interrupt
-* priority (level). This consists of an array of function pointers indexed
-* by interrupt priority, with index 0 being the user exception handler hook.
-* Each entry in the array is initially 0, and may be replaced by a function
-* pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
-*
-* The handler for low and medium priority obeys ABI conventions so may be coded
-* in C. For the exception handler, the cause is the contents of the EXCCAUSE
-* reg, and the result is -1 if handled, else the cause (still needs handling).
-* For interrupt handlers, the cause is a mask of pending enabled interrupts at
-* that level, and the result is the same mask with the bits for the handled
-* interrupts cleared (those not cleared still need handling). This allows a test
-* case to either pre-handle or override the default handling for the exception
-* or interrupt level (see xtensa_vectors.S).
-*
-* High priority handlers (including NMI) must be coded in assembly, are always
-* called by 'call0' regardless of ABI, must preserve all registers except a0,
-* and must not use or modify the interrupted stack. The hook argument 'cause'
-* is not passed and the result is ignored, so as not to burden the caller with
-* saving and restoring a2 (it assumes only one interrupt per level - see the
-* discussion in high priority interrupts in xtensa_vectors.S). The handler
-* therefore should be coded to prototype 'void h(void)' even though it plugs
-* into an array of handlers of prototype 'unsigned h(unsigned)'.
-*
-* To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
-*
+
+HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
+
+This Xtensa RTOS port provides hooks for dynamically installing exception
+and interrupt handlers to facilitate automated testing where each test
+case can install its own handler for user exceptions and each interrupt
+priority (level). This consists of an array of function pointers indexed
+by interrupt priority, with index 0 being the user exception handler hook.
+Each entry in the array is initially 0, and may be replaced by a function
+pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
+
+The handler for low and medium priority obeys ABI conventions so may be coded
+in C. For the exception handler, the cause is the contents of the EXCCAUSE
+reg, and the result is -1 if handled, else the cause (still needs handling).
+For interrupt handlers, the cause is a mask of pending enabled interrupts at
+that level, and the result is the same mask with the bits for the handled
+interrupts cleared (those not cleared still need handling). This allows a test
+case to either pre-handle or override the default handling for the exception
+or interrupt level (see xtensa_vectors.S).
+
+High priority handlers (including NMI) must be coded in assembly, are always
+called by 'call0' regardless of ABI, must preserve all registers except a0,
+and must not use or modify the interrupted stack. The hook argument 'cause'
+is not passed and the result is ignored, so as not to burden the caller with
+saving and restoring a2 (it assumes only one interrupt per level - see the
+discussion in high priority interrupts in xtensa_vectors.S). The handler
+therefore should be coded to prototype 'void h(void)' even though it plugs
+into an array of handlers of prototype 'unsigned h(unsigned)'.
+
+To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
+
*******************************************************************************/
-#define XT_INTEXC_HOOK_NUM ( 1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI )
+#define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
#ifndef __ASSEMBLER__
- typedef unsigned (* XT_INTEXC_HOOK)( unsigned cause );
- extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[ XT_INTEXC_HOOK_NUM ];
+typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
+extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
#endif
/*******************************************************************************
-*
-* CONVENIENCE INCLUSIONS.
-*
-* Ensures RTOS specific files need only include this one Xtensa-generic header.
-* These headers are included last so they can use the RTOS definitions above.
-*
+
+CONVENIENCE INCLUSIONS.
+
+Ensures RTOS specific files need only include this one Xtensa-generic header.
+These headers are included last so they can use the RTOS definitions above.
+
*******************************************************************************/
#include "xtensa_context.h"
#ifdef XT_RTOS_TIMER_INT
- #include "xtensa_timer.h"
+#include "xtensa_timer.h"
#endif
/*******************************************************************************
-*
-* Xtensa Port Version.
-*
+
+Xtensa Port Version.
+
*******************************************************************************/
-#define XTENSA_PORT_VERSION 1.7
-#define XTENSA_PORT_VERSION_STRING "1.7"
+#define XTENSA_PORT_VERSION 1.7
+#define XTENSA_PORT_VERSION_STRING "1.7"
#endif /* XTENSA_RTOS_H */
+
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h b/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
index 89a55d6..7d7acaa 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
@@ -41,118 +42,119 @@
#define XTENSA_TIMER_H
#ifdef __ASSEMBLER__
- #include <xtensa/coreasm.h>
+#include <xtensa/coreasm.h>
#endif
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
-#include "xtensa_rtos.h" /* in case this wasn't included directly */
+#include "xtensa_rtos.h" /* in case this wasn't included directly */
#include <FreeRTOSConfig.h>
/*
- * Select timer to use for periodic tick, and determine its interrupt number
- * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
- * in which case its validity is checked (it must exist in this core and must
- * not be on a high priority interrupt - an error will be reported in invalid).
- * Otherwise select the first low or medium priority interrupt timer available.
- */
+Select timer to use for periodic tick, and determine its interrupt number
+and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
+in which case its validity is checked (it must exist in this core and must
+not be on a high priority interrupt - an error will be reported in invalid).
+Otherwise select the first low or medium priority interrupt timer available.
+*/
#if XCHAL_NUM_TIMERS == 0
- #error "This Xtensa configuration is unsupported, it has no timers."
+ #error "This Xtensa configuration is unsupported, it has no timers."
#else
- #ifndef XT_TIMER_INDEX
- #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
- #if XCHAL_INT_LEVEL( XCHAL_TIMER3_INTERRUPT ) <= XCHAL_EXCM_LEVEL
- #undef XT_TIMER_INDEX
- #define XT_TIMER_INDEX 3
- #endif
- #endif
- #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
- #if XCHAL_INT_LEVEL( XCHAL_TIMER2_INTERRUPT ) <= XCHAL_EXCM_LEVEL
- #undef XT_TIMER_INDEX
- #define XT_TIMER_INDEX 2
- #endif
- #endif
- #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
- #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL
- #undef XT_TIMER_INDEX
- #define XT_TIMER_INDEX 1
- #endif
- #endif
- #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
- #if XCHAL_INT_LEVEL( XCHAL_TIMER0_INTERRUPT ) <= XCHAL_EXCM_LEVEL
- #undef XT_TIMER_INDEX
- #define XT_TIMER_INDEX 0
- #endif
- #endif
- #endif /* ifndef XT_TIMER_INDEX */
- #ifndef XT_TIMER_INDEX
- #error "There is no suitable timer in this Xtensa configuration."
+#ifndef XT_TIMER_INDEX
+ #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+ #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
+ #undef XT_TIMER_INDEX
+ #define XT_TIMER_INDEX 3
#endif
-
- #define XT_CCOMPARE ( CCOMPARE + XT_TIMER_INDEX )
- #define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT( XT_TIMER_INDEX )
- #define XT_TIMER_INTPRI XCHAL_INT_LEVEL( XT_TIMER_INTNUM )
- #define XT_TIMER_INTEN ( 1 << XT_TIMER_INTNUM )
-
- #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
- #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
- #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
- #error "The timer interrupt cannot be high priority (use medium or low)."
+ #endif
+ #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+ #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
+ #undef XT_TIMER_INDEX
+ #define XT_TIMER_INDEX 2
#endif
+ #endif
+ #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+ #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
+ #undef XT_TIMER_INDEX
+ #define XT_TIMER_INDEX 1
+ #endif
+ #endif
+ #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+ #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
+ #undef XT_TIMER_INDEX
+ #define XT_TIMER_INDEX 0
+ #endif
+ #endif
+#endif
+#ifndef XT_TIMER_INDEX
+ #error "There is no suitable timer in this Xtensa configuration."
+#endif
+
+#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX)
+#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
+#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
+#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM)
+
+#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
+ #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
+#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
+ #error "The timer interrupt cannot be high priority (use medium or low)."
+#endif
#endif /* XCHAL_NUM_TIMERS */
/*
- * Set processor clock frequency, used to determine clock divisor for timer tick.
- * User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
- * If using a supported board via the board-independent API defined in xtbsp.h,
- * this may be left undefined and frequency and tick divisor will be computed
- * and cached during run-time initialization.
- *
- * NOTE ON SIMULATOR:
- * Under the Xtensa instruction set simulator, the frequency can only be estimated
- * because it depends on the speed of the host and the version of the simulator.
- * Also because it runs much slower than hardware, it is not possible to achieve
- * real-time performance for most applications under the simulator. A frequency
- * too low does not allow enough time between timer interrupts, starving threads.
- * To obtain a more convenient but non-real-time tick duration on the simulator,
- * compile with xt-xcc option "-DXT_SIMULATOR".
- * Adjust this frequency to taste (it's not real-time anyway!).
- */
-#if defined( XT_SIMULATOR ) && !defined( XT_CLOCK_FREQ )
- #define XT_CLOCK_FREQ configCPU_CLOCK_HZ
+Set processor clock frequency, used to determine clock divisor for timer tick.
+User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
+If using a supported board via the board-independent API defined in xtbsp.h,
+this may be left undefined and frequency and tick divisor will be computed
+and cached during run-time initialization.
+
+NOTE ON SIMULATOR:
+Under the Xtensa instruction set simulator, the frequency can only be estimated
+because it depends on the speed of the host and the version of the simulator.
+Also because it runs much slower than hardware, it is not possible to achieve
+real-time performance for most applications under the simulator. A frequency
+too low does not allow enough time between timer interrupts, starving threads.
+To obtain a more convenient but non-real-time tick duration on the simulator,
+compile with xt-xcc option "-DXT_SIMULATOR".
+Adjust this frequency to taste (it's not real-time anyway!).
+*/
+#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
+#define XT_CLOCK_FREQ configCPU_CLOCK_HZ
#endif
-#if !defined( XT_CLOCK_FREQ ) && !defined( XT_BOARD )
- #error "XT_CLOCK_FREQ must be defined for the target platform."
+#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
+ #error "XT_CLOCK_FREQ must be defined for the target platform."
#endif
/*
- * Default number of timer "ticks" per second (default 100 for 10ms tick).
- * RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
- * User may redefine this to an optimal value for the application, either by
- * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
- * "-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
- */
+Default number of timer "ticks" per second (default 100 for 10ms tick).
+RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
+User may redefine this to an optimal value for the application, either by
+editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
+"-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
+*/
#ifndef XT_TICK_PER_SEC
- #define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */
+#define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */
#endif
/*
- * Derivation of clock divisor for timer tick and interrupt (one per tick).
- */
+Derivation of clock divisor for timer tick and interrupt (one per tick).
+*/
#ifdef XT_CLOCK_FREQ
- #define XT_TICK_DIVISOR ( XT_CLOCK_FREQ / XT_TICK_PER_SEC )
+#define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
#endif
#ifndef __ASSEMBLER__
- extern unsigned _xt_tick_divisor;
- extern void _xt_tick_divisor_init( void );
+extern unsigned _xt_tick_divisor;
+extern void _xt_tick_divisor_init(void);
#endif
-#endif /* XTENSA_TIMER_H */
+#endif /* XTENSA_TIMER_H */
+
diff --git a/portable/WizC/PIC18/Drivers/Tick/Tick.c b/portable/WizC/PIC18/Drivers/Tick/Tick.c
index c85de50..28902c7 100644
--- a/portable/WizC/PIC18/Drivers/Tick/Tick.c
+++ b/portable/WizC/PIC18/Drivers/Tick/Tick.c
@@ -25,51 +25,51 @@
* 1 tab == 4 spaces!
*/
-/*
- * Changes from V3.0.0
- + ISRcode is pulled inline and portTICKisr() is therefore
- + deleted from this file.
- +
- + Prescaler logic for Timer1 added to allow for a wider
- + range of TickRates.
- +
- + Changes from V3.0.1
- */
+/*
+Changes from V3.0.0
+ + ISRcode is pulled inline and portTICKisr() is therefore
+ deleted from this file.
+
+ + Prescaler logic for Timer1 added to allow for a wider
+ range of TickRates.
+
+Changes from V3.0.1
+*/
#include <FreeRTOS.h>
#include <task.h>
/* IO port constants. */
-#define portBIT_SET ( 1 )
-#define portBIT_CLEAR ( 0 )
+#define portBIT_SET (1)
+#define portBIT_CLEAR (0)
-/*
+/*
* Hardware setup for the tick.
* We use a compare match on timer1. Depending on MPU-frequency
* and requested tickrate, a prescaled value with a matching
* prescaler are determined.
*/
-#define portTIMER_COMPARE_BASE ( ( APROCFREQ / 4 ) / configTICK_RATE_HZ )
+#define portTIMER_COMPARE_BASE ((APROCFREQ/4)/configTICK_RATE_HZ)
-#if portTIMER_COMPARE_BASE < 0x10000
- #define portTIMER_COMPARE_VALUE ( portTIMER_COMPARE_BASE )
- #define portTIMER_COMPARE_PS1 ( portBIT_CLEAR )
- #define portTIMER_COMPARE_PS0 ( portBIT_CLEAR )
+#if portTIMER_COMPARE_BASE < 0x10000
+ #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE)
+ #define portTIMER_COMPARE_PS1 (portBIT_CLEAR)
+ #define portTIMER_COMPARE_PS0 (portBIT_CLEAR)
#elif portTIMER_COMPARE_BASE < 0x20000
- #define portTIMER_COMPARE_VALUE ( portTIMER_COMPARE_BASE / 2 )
- #define portTIMER_COMPARE_PS1 ( portBIT_CLEAR )
- #define portTIMER_COMPARE_PS0 ( portBIT_SET )
+ #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 2)
+ #define portTIMER_COMPARE_PS1 (portBIT_CLEAR)
+ #define portTIMER_COMPARE_PS0 (portBIT_SET)
#elif portTIMER_COMPARE_BASE < 0x40000
- #define portTIMER_COMPARE_VALUE ( portTIMER_COMPARE_BASE / 4 )
- #define portTIMER_COMPARE_PS1 ( portBIT_SET )
- #define portTIMER_COMPARE_PS0 ( portBIT_CLEAR )
+ #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 4)
+ #define portTIMER_COMPARE_PS1 (portBIT_SET)
+ #define portTIMER_COMPARE_PS0 (portBIT_CLEAR)
#elif portTIMER_COMPARE_BASE < 0x80000
- #define portTIMER_COMPARE_VALUE ( portTIMER_COMPARE_BASE / 8 )
- #define portTIMER_COMPARE_PS1 ( portBIT_SET )
- #define portTIMER_COMPARE_PS0 ( portBIT_SET )
-#else /* if portTIMER_COMPARE_BASE < 0x10000 */
- #error "TickRate out of range"
-#endif /* if portTIMER_COMPARE_BASE < 0x10000 */
+ #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 8)
+ #define portTIMER_COMPARE_PS1 (portBIT_SET)
+ #define portTIMER_COMPARE_PS0 (portBIT_SET)
+#else
+ #error "TickRate out of range"
+#endif
/*-----------------------------------------------------------*/
@@ -78,61 +78,61 @@
*/
void portSetupTick( void )
{
- /*
- * Interrupts are disabled when this function is called.
- */
+ /*
+ * Interrupts are disabled when this function is called.
+ */
- /*
- * Setup CCP1
- * Provide the tick interrupt using a compare match on timer1.
- */
+ /*
+ * Setup CCP1
+ * Provide the tick interrupt using a compare match on timer1.
+ */
- /*
- * Set the compare match value.
- */
- CCPR1H = ( uint8_t ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff );
- CCPR1L = ( uint8_t ) ( portTIMER_COMPARE_VALUE & 0xff );
+ /*
+ * Set the compare match value.
+ */
+ CCPR1H = ( uint8_t ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff );
+ CCPR1L = ( uint8_t ) ( portTIMER_COMPARE_VALUE & 0xff );
- /*
- * Set Compare Special Event Trigger Mode
- */
- bCCP1M3 = portBIT_SET;
- bCCP1M2 = portBIT_CLEAR;
- bCCP1M1 = portBIT_SET;
- bCCP1M0 = portBIT_SET;
+ /*
+ * Set Compare Special Event Trigger Mode
+ */
+ bCCP1M3 = portBIT_SET;
+ bCCP1M2 = portBIT_CLEAR;
+ bCCP1M1 = portBIT_SET;
+ bCCP1M0 = portBIT_SET;
- /*
- * Enable CCP1 interrupt
- */
- bCCP1IE = portBIT_SET;
+ /*
+ * Enable CCP1 interrupt
+ */
+ bCCP1IE = portBIT_SET;
- /*
- * We are only going to use the global interrupt bit, so disable
- * interruptpriorities and enable peripheral interrupts.
- */
- bIPEN = portBIT_CLEAR;
- bPEIE = portBIT_SET;
+ /*
+ * We are only going to use the global interrupt bit, so disable
+ * interruptpriorities and enable peripheral interrupts.
+ */
+ bIPEN = portBIT_CLEAR;
+ bPEIE = portBIT_SET;
- /*
- * Set up timer1
- * It will produce the system tick.
- */
+ /*
+ * Set up timer1
+ * It will produce the system tick.
+ */
- /*
- * Clear the time count
- */
- TMR1H = ( uint8_t ) 0x00;
- TMR1L = ( uint8_t ) 0x00;
+ /*
+ * Clear the time count
+ */
+ TMR1H = ( uint8_t ) 0x00;
+ TMR1L = ( uint8_t ) 0x00;
- /*
- * Setup the timer
- */
- bRD16 = portBIT_SET; /* 16-bit */
- bT1CKPS1 = portTIMER_COMPARE_PS1; /* prescaler */
- bT1CKPS0 = portTIMER_COMPARE_PS0; /* prescaler */
- bT1OSCEN = portBIT_SET; /* Oscillator enable */
- bT1SYNC = portBIT_SET; /* No external clock sync */
- bTMR1CS = portBIT_CLEAR; /* Internal clock */
-
- bTMR1ON = portBIT_SET; /* Start timer1 */
+ /*
+ * Setup the timer
+ */
+ bRD16 = portBIT_SET; // 16-bit
+ bT1CKPS1 = portTIMER_COMPARE_PS1; // prescaler
+ bT1CKPS0 = portTIMER_COMPARE_PS0; // prescaler
+ bT1OSCEN = portBIT_SET; // Oscillator enable
+ bT1SYNC = portBIT_SET; // No external clock sync
+ bTMR1CS = portBIT_CLEAR; // Internal clock
+
+ bTMR1ON = portBIT_SET; // Start timer1
}
diff --git a/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/portable/WizC/PIC18/Drivers/Tick/isrTick.c
index 34dd599..e5eee6d 100644
--- a/portable/WizC/PIC18/Drivers/Tick/isrTick.c
+++ b/portable/WizC/PIC18/Drivers/Tick/isrTick.c
@@ -25,54 +25,54 @@
* 1 tab == 4 spaces!
*/
-/*
- * Changes from V3.0.0
- + ISRcode pulled inline to reduce stack-usage.
- +
- + Added functionality to only call vTaskSwitchContext() once
- + when handling multiple interruptsources in a single interruptcall.
- +
- + Filename changed to a .c extension to allow stepping through code
- + using F7.
- +
- + Changes from V3.0.1
- */
+/*
+Changes from V3.0.0
+ + ISRcode pulled inline to reduce stack-usage.
+
+ + Added functionality to only call vTaskSwitchContext() once
+ when handling multiple interruptsources in a single interruptcall.
+
+ + Filename changed to a .c extension to allow stepping through code
+ using F7.
+
+Changes from V3.0.1
+*/
/*
* ISR for the tick.
- * This increments the tick count and, if using the preemptive scheduler,
- * performs a context switch. This must be identical to the manual
- * context switch in how it stores the context of a task.
+ * This increments the tick count and, if using the preemptive scheduler,
+ * performs a context switch. This must be identical to the manual
+ * context switch in how it stores the context of a task.
*/
#ifndef _FREERTOS_DRIVERS_TICK_ISRTICK_C
#define _FREERTOS_DRIVERS_TICK_ISRTICK_C
{
- /*
- * Was the interrupt the SystemClock?
- */
- if( bCCP1IF && bCCP1IE )
- {
- /*
- * Reset the interrupt flag
- */
- bCCP1IF = 0;
-
- /*
- * Maintain the tick count.
- */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /*
- * Ask for a switch to the highest priority task
- * that is ready to run.
- */
- uxSwitchRequested = pdTRUE;
- }
- }
+ /*
+ * Was the interrupt the SystemClock?
+ */
+ if( bCCP1IF && bCCP1IE )
+ {
+ /*
+ * Reset the interrupt flag
+ */
+ bCCP1IF = 0;
+
+ /*
+ * Maintain the tick count.
+ */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /*
+ * Ask for a switch to the highest priority task
+ * that is ready to run.
+ */
+ uxSwitchRequested = pdTRUE;
+ }
+ }
}
#pragma wizcpp uselib "$__PATHNAME__/Tick.c"
-#endif /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */
+#endif /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */
diff --git a/portable/WizC/PIC18/addFreeRTOS.h b/portable/WizC/PIC18/addFreeRTOS.h
index 8d14df7..8b2e7a5 100644
--- a/portable/WizC/PIC18/addFreeRTOS.h
+++ b/portable/WizC/PIC18/addFreeRTOS.h
@@ -26,13 +26,13 @@
*/
/*
- * Changes from V3.0.0
- *
- * Changes from V3.0.1
- *
- * Changes from V4.0.1
- * Uselib pragma added for Croutine.c
- */
+Changes from V3.0.0
+
+Changes from V3.0.1
+
+Changes from V4.0.1
+ Uselib pragma added for Croutine.c
+*/
/*
* The installation script will automatically prepend this file to the default FreeRTOS.h.
@@ -41,7 +41,7 @@
#ifndef WIZC_FREERTOS_H
#define WIZC_FREERTOS_H
-#pragma noheap
+#pragma noheap
#pragma wizcpp expandnl on
#pragma wizcpp searchpath "$__PATHNAME__/libFreeRTOS/Include/"
#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Croutine.c"
@@ -50,4 +50,4 @@
#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/List.c"
#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Port.c"
-#endif /* WIZC_FREERTOS_H */
+#endif /* WIZC_FREERTOS_H */
diff --git a/portable/WizC/PIC18/port.c b/portable/WizC/PIC18/port.c
index e918253..a52fe73 100644
--- a/portable/WizC/PIC18/port.c
+++ b/portable/WizC/PIC18/port.c
@@ -26,19 +26,19 @@
*/
/*
- * Changes from V3.2.1
- + CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12.
- +
- + Changes from V3.2.0
- + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves
- + an error on devices with more than 64kB ROM.
- +
- + Changes from V3.0.0
- + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being
- + handled before the scheduler is started.
- +
- + Changes from V3.0.1
- */
+Changes from V3.2.1
+ + CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12.
+
+Changes from V3.2.0
+ + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves
+ an error on devices with more than 64kB ROM.
+
+Changes from V3.0.0
+ + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being
+ handled before the scheduler is started.
+
+Changes from V3.0.1
+*/
/* Scheduler include files. */
#include <FreeRTOS.h>
@@ -77,17 +77,17 @@
* 16 bytes: Free space on stack
*/
#if _ROMSIZE > 0x8000
- #define portSTACK_FSR_BYTES ( 15 )
- #define portSTACK_CALLRETURN_ENTRY_SIZE ( 3 )
+ #define portSTACK_FSR_BYTES ( 15 )
+ #define portSTACK_CALLRETURN_ENTRY_SIZE ( 3 )
#else
- #define portSTACK_FSR_BYTES ( 13 )
- #define portSTACK_CALLRETURN_ENTRY_SIZE ( 2 )
+ #define portSTACK_FSR_BYTES ( 13 )
+ #define portSTACK_CALLRETURN_ENTRY_SIZE ( 2 )
#endif
-#define portSTACK_MINIMAL_CALLRETURN_DEPTH ( 10 )
-#define portSTACK_OTHER_BYTES ( 20 )
+#define portSTACK_MINIMAL_CALLRETURN_DEPTH ( 10 )
+#define portSTACK_OTHER_BYTES ( 20 )
-uint16_t usCalcMinStackSize = 0;
+uint16_t usCalcMinStackSize = 0;
/*-----------------------------------------------------------*/
@@ -105,156 +105,154 @@
* Initialise the stack of a new task.
* See portSAVE_CONTEXT macro for description.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- uint8_t ucScratch;
+uint8_t ucScratch;
+ /*
+ * Get the size of the RAMarea in page 0 used by the compiler
+ * We do this here already to avoid W-register conflicts.
+ */
+ _Pragma("asm")
+ movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
+ movwf PRODL,ACCESS ; PRODL is used as temp register
+ _Pragma("asmend")
+ ucScratch = PRODL;
- /*
- * Get the size of the RAMarea in page 0 used by the compiler
- * We do this here already to avoid W-register conflicts.
- */
- _Pragma( "asm" )
- movlw OVERHEADPAGE0 - LOCOPTSIZE + MAXLOCOPTSIZE
- movwf PRODL, ACCESS;
- PRODL is used as temp register _Pragma( "asmend" )
- ucScratch = PRODL;
+ /*
+ * Place a few bytes of known values on the bottom of the stack.
+ * This is just useful for debugging.
+ */
+// *pxTopOfStack-- = 0x11;
+// *pxTopOfStack-- = 0x22;
+// *pxTopOfStack-- = 0x33;
- /*
- * Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging.
- */
-/* *pxTopOfStack-- = 0x11; */
-/* *pxTopOfStack-- = 0x22; */
-/* *pxTopOfStack-- = 0x33; */
+ /*
+ * Simulate how the stack would look after a call to vPortYield()
+ * generated by the compiler.
+ */
- /*
- * Simulate how the stack would look after a call to vPortYield()
- * generated by the compiler.
- */
+ /*
+ * First store the function parameters. This is where the task expects
+ * to find them when it starts running.
+ */
+ *pxTopOfStack-- = ( StackType_t ) ( (( uint16_t ) pvParameters >> 8) & 0x00ff );
+ *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pvParameters & 0x00ff );
- /*
- * First store the function parameters. This is where the task expects
- * to find them when it starts running.
- */
- *pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pvParameters >> 8 ) & 0x00ff );
- *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pvParameters & 0x00ff );
+ /*
+ * Next are all the registers that form part of the task context.
+ */
+ *pxTopOfStack-- = ( StackType_t ) 0x11; /* STATUS. */
+ *pxTopOfStack-- = ( StackType_t ) 0x22; /* WREG. */
+ *pxTopOfStack-- = ( StackType_t ) 0x33; /* BSR. */
+ *pxTopOfStack-- = ( StackType_t ) 0x44; /* PRODH. */
+ *pxTopOfStack-- = ( StackType_t ) 0x55; /* PRODL. */
+ *pxTopOfStack-- = ( StackType_t ) 0x66; /* FSR0H. */
+ *pxTopOfStack-- = ( StackType_t ) 0x77; /* FSR0L. */
+ *pxTopOfStack-- = ( StackType_t ) 0x88; /* FSR1H. */
+ *pxTopOfStack-- = ( StackType_t ) 0x99; /* FSR1L. */
+ *pxTopOfStack-- = ( StackType_t ) 0xAA; /* TABLAT. */
+#if _ROMSIZE > 0x8000
+ *pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */
+#endif
+ *pxTopOfStack-- = ( StackType_t ) 0xCC; /* TBLPTRH. */
+ *pxTopOfStack-- = ( StackType_t ) 0xDD; /* TBLPTRL. */
+#if _ROMSIZE > 0x8000
+ *pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */
+#endif
+ *pxTopOfStack-- = ( StackType_t ) 0xFF; /* PCLATH. */
- /*
- * Next are all the registers that form part of the task context.
- */
- *pxTopOfStack-- = ( StackType_t ) 0x11; /* STATUS. */
- *pxTopOfStack-- = ( StackType_t ) 0x22; /* WREG. */
- *pxTopOfStack-- = ( StackType_t ) 0x33; /* BSR. */
- *pxTopOfStack-- = ( StackType_t ) 0x44; /* PRODH. */
- *pxTopOfStack-- = ( StackType_t ) 0x55; /* PRODL. */
- *pxTopOfStack-- = ( StackType_t ) 0x66; /* FSR0H. */
- *pxTopOfStack-- = ( StackType_t ) 0x77; /* FSR0L. */
- *pxTopOfStack-- = ( StackType_t ) 0x88; /* FSR1H. */
- *pxTopOfStack-- = ( StackType_t ) 0x99; /* FSR1L. */
- *pxTopOfStack-- = ( StackType_t ) 0xAA; /* TABLAT. */
- #if _ROMSIZE > 0x8000
- *pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */
- #endif
- *pxTopOfStack-- = ( StackType_t ) 0xCC; /* TBLPTRH. */
- *pxTopOfStack-- = ( StackType_t ) 0xDD; /* TBLPTRL. */
- #if _ROMSIZE > 0x8000
- *pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */
- #endif
- *pxTopOfStack-- = ( StackType_t ) 0xFF; /* PCLATH. */
+ /*
+ * Next the compiler's scratchspace.
+ */
+ while(ucScratch-- > 0)
+ {
+ *pxTopOfStack-- = ( StackType_t ) 0;
+ }
- /*
- * Next the compiler's scratchspace.
- */
- while( ucScratch-- > 0 )
- {
- *pxTopOfStack-- = ( StackType_t ) 0;
- }
+ /*
+ * The only function return address so far is the address of the task entry.
+ * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the
+ * stack, too. TOSU is always written as zero here because wizC does not allow
+ * functionpointers to point above 64kB in ROM.
+ */
+#if _ROMSIZE > 0x8000
+ *pxTopOfStack-- = ( StackType_t ) 0;
+#endif
+ *pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pxCode >> 8 ) & 0x00ff );
+ *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pxCode & 0x00ff );
- /*
- * The only function return address so far is the address of the task entry.
- * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the
- * stack, too. TOSU is always written as zero here because wizC does not allow
- * functionpointers to point above 64kB in ROM.
- */
- #if _ROMSIZE > 0x8000
- *pxTopOfStack-- = ( StackType_t ) 0;
- #endif
- *pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pxCode >> 8 ) & 0x00ff );
- *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pxCode & 0x00ff );
+ /*
+ * Store the number of return addresses on the hardware stack.
+ * So far only the address of the task entry point.
+ */
+ *pxTopOfStack-- = ( StackType_t ) 1;
- /*
- * Store the number of return addresses on the hardware stack.
- * So far only the address of the task entry point.
- */
- *pxTopOfStack-- = ( StackType_t ) 1;
+ /*
+ * The code generated by wizC does not maintain separate
+ * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot
+ * use the stack as per other ports. Instead a variable is used to keep
+ * track of the critical section nesting. This variable has to be stored
+ * as part of the task context and is initially set to zero.
+ */
+ *pxTopOfStack-- = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
- /*
- * The code generated by wizC does not maintain separate
- * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot
- * use the stack as per other ports. Instead a variable is used to keep
- * track of the critical section nesting. This variable has to be stored
- * as part of the task context and is initially set to zero.
- */
- *pxTopOfStack-- = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void )
{
- /*
- * Fetch the size of compiler's scratchspace.
- */
- _Pragma( "asm" )
- movlw OVERHEADPAGE0 - LOCOPTSIZE + MAXLOCOPTSIZE
- movlb usCalcMinStackSize >> 8
- movwf usCalcMinStackSize, BANKED _Pragma( "asmend" )
+ /*
+ * Fetch the size of compiler's scratchspace.
+ */
+ _Pragma("asm")
+ movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
+ movlb usCalcMinStackSize>>8
+ movwf usCalcMinStackSize,BANKED
+ _Pragma("asmend")
- /*
- * Add minimum needed stackspace
- */
- usCalcMinStackSize += ( portSTACK_FSR_BYTES )
- + ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE )
- + ( portSTACK_OTHER_BYTES );
+ /*
+ * Add minimum needed stackspace
+ */
+ usCalcMinStackSize += ( portSTACK_FSR_BYTES )
+ + ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE )
+ + ( portSTACK_OTHER_BYTES );
- return( usCalcMinStackSize );
+ return(usCalcMinStackSize);
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- extern void portSetupTick( void );
+ extern void portSetupTick( void );
- /*
- * Setup a timer for the tick ISR for the preemptive scheduler.
- */
- portSetupTick();
+ /*
+ * Setup a timer for the tick ISR for the preemptive scheduler.
+ */
+ portSetupTick();
- /*
- * Restore the context of the first task to run.
- */
- portRESTORE_CONTEXT();
+ /*
+ * Restore the context of the first task to run.
+ */
+ portRESTORE_CONTEXT();
- /*
- * This point should never be reached during execution.
- */
- return pdTRUE;
+ /*
+ * This point should never be reached during execution.
+ */
+ return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /*
- * It is unlikely that the scheduler for the PIC port will get stopped
- * once running. When called a reset is done which is probably the
- * most valid action.
- */
- _Pragma( asmline reset );
+ /*
+ * It is unlikely that the scheduler for the PIC port will get stopped
+ * once running. When called a reset is done which is probably the
+ * most valid action.
+ */
+ _Pragma(asmline reset);
}
/*-----------------------------------------------------------*/
@@ -266,54 +264,54 @@
*/
void vPortYield( void )
{
- /*
- * Save the context of the current task.
- */
- portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
+ /*
+ * Save the context of the current task.
+ */
+ portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
- /*
- * Switch to the highest priority task that is ready to run.
- */
- vTaskSwitchContext();
+ /*
+ * Switch to the highest priority task that is ready to run.
+ */
+ vTaskSwitchContext();
- /*
- * Start executing the task we have just switched to.
- */
- portRESTORE_CONTEXT();
+ /*
+ * Start executing the task we have just switched to.
+ */
+ portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- void * pvPortMalloc( uint16_t usWantedSize )
- {
- void * pvReturn;
+ void *pvPortMalloc( uint16_t usWantedSize )
+ {
+ void *pvReturn;
- vTaskSuspendAll();
- {
- pvReturn = malloc( ( malloc_t ) usWantedSize );
- }
- xTaskResumeAll();
+ vTaskSuspendAll();
+ {
+ pvReturn = malloc( ( malloc_t ) usWantedSize );
+ }
+ xTaskResumeAll();
- return pvReturn;
- }
+ return pvReturn;
+ }
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- void vPortFree( void * pv )
- {
- if( pv )
- {
- vTaskSuspendAll();
- {
- free( pv );
- }
- xTaskResumeAll();
- }
- }
+ void vPortFree( void *pv )
+ {
+ if( pv )
+ {
+ vTaskSuspendAll();
+ {
+ free( pv );
+ }
+ xTaskResumeAll();
+ }
+ }
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
\ No newline at end of file
diff --git a/portable/WizC/PIC18/portmacro.h b/portable/WizC/PIC18/portmacro.h
index f56855b..871fcd2 100644
--- a/portable/WizC/PIC18/portmacro.h
+++ b/portable/WizC/PIC18/portmacro.h
@@ -26,46 +26,46 @@
*/
/*
- * Changes from V3.0.0
- *
- * Changes from V3.0.1
- */
+Changes from V3.0.0
+
+Changes from V3.0.1
+*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #if !defined( _SERIES ) || _SERIES != 18
- #error "WizC supports FreeRTOS on the Microchip PIC18-series only"
- #endif
+#if !defined(_SERIES) || _SERIES != 18
+ #error "WizC supports FreeRTOS on the Microchip PIC18-series only"
+#endif
- #if !defined( QUICKCALL ) || QUICKCALL != 1
- #error "QuickCall must be enabled (see ProjectOptions/Optimisations)"
- #endif
+#if !defined(QUICKCALL) || QUICKCALL != 1
+ #error "QuickCall must be enabled (see ProjectOptions/Optimisations)"
+#endif
- #include <stddef.h>
- #include <pic.h>
+#include <stddef.h>
+#include <pic.h>
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE portFLOAT
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint8_t
- #define portBASE_TYPE char
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE portFLOAT
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
- typedef portSTACK_TYPE StackType_t;
- typedef signed char BaseType_t;
- typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) ( 0xFFFF )
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFF )
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) ( 0xFFFF )
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFF )
+#endif
- #define portBYTE_ALIGNMENT 1
+#define portBYTE_ALIGNMENT 1
/*-----------------------------------------------------------*/
@@ -73,78 +73,78 @@
* Constant used for context switch macro when we require the interrupt
* enable state to be forced when the interrupted task is switched back in.
*/
- #define portINTERRUPTS_FORCED ( 0x01 )
+#define portINTERRUPTS_FORCED (0x01)
/*
* Constant used for context switch macro when we require the interrupt
* enable state to be unchanged when the interrupted task is switched back in.
*/
- #define portINTERRUPTS_UNCHANGED ( 0x00 )
+#define portINTERRUPTS_UNCHANGED (0x00)
/* Initial interrupt enable state for newly created tasks. This value is
* used when a task switches in for the first time.
*/
- #define portINTERRUPTS_INITIAL_STATE ( portINTERRUPTS_FORCED )
+#define portINTERRUPTS_INITIAL_STATE (portINTERRUPTS_FORCED)
/*
* Macros to modify the global interrupt enable bit in INTCON.
*/
- #define portDISABLE_INTERRUPTS() \
- do \
- { \
- bGIE = 0; \
- } while( bGIE ) /* MicroChip recommends this check! */
+#define portDISABLE_INTERRUPTS() \
+ do \
+ { \
+ bGIE=0; \
+ } while(bGIE) // MicroChip recommends this check!
- #define portENABLE_INTERRUPTS() \
- do \
- { \
- bGIE = 1; \
- } while( 0 )
+#define portENABLE_INTERRUPTS() \
+ do \
+ { \
+ bGIE=1; \
+ } while(0)
/*-----------------------------------------------------------*/
/*
* Critical section macros.
*/
- extern uint8_t ucCriticalNesting;
+extern uint8_t ucCriticalNesting;
- #define portNO_CRITICAL_SECTION_NESTING ( ( uint8_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( uint8_t ) 0 )
- #define portENTER_CRITICAL() \
- do \
- { \
- portDISABLE_INTERRUPTS(); \
- \
- /* \
- * Now interrupts are disabled ucCriticalNesting \
- * can be accessed directly. Increment \
- * ucCriticalNesting to keep a count of how \
- * many times portENTER_CRITICAL() has been called. \
- */ \
- ucCriticalNesting++; \
- } while( 0 )
+#define portENTER_CRITICAL() \
+ do \
+ { \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* \
+ * Now interrupts are disabled ucCriticalNesting \
+ * can be accessed directly. Increment \
+ * ucCriticalNesting to keep a count of how \
+ * many times portENTER_CRITICAL() has been called. \
+ */ \
+ ucCriticalNesting++; \
+ } while(0)
- #define portEXIT_CRITICAL() \
- do \
- { \
- if( ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* \
- * Decrement the nesting count as we are leaving a \
- * critical section. \
- */ \
- ucCriticalNesting--; \
- } \
- \
- /* \
- * If the nesting level has reached zero then \
- * interrupts should be re-enabled. \
- */ \
- if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } while( 0 )
+#define portEXIT_CRITICAL() \
+ do \
+ { \
+ if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING) \
+ { \
+ /* \
+ * Decrement the nesting count as we are leaving a \
+ * critical section. \
+ */ \
+ ucCriticalNesting--; \
+ } \
+ \
+ /* \
+ * If the nesting level has reached zero then \
+ * interrupts should be re-enabled. \
+ */ \
+ if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } while(0)
/*-----------------------------------------------------------*/
@@ -153,18 +153,18 @@
* portMINIMAL_STACK_SIZE. Some input to this calculation is
* compiletime determined, other input is port-defined (see port.c)
*/
- extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void );
- extern uint16_t usCalcMinStackSize;
+extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void );
+extern uint16_t usCalcMinStackSize;
- #define portMINIMAL_STACK_SIZE \
- ( ( usCalcMinStackSize == 0 ) \
- ? usPortCALCULATE_MINIMAL_STACK_SIZE() \
- : usCalcMinStackSize )
+#define portMINIMAL_STACK_SIZE \
+ ((usCalcMinStackSize == 0) \
+ ? usPortCALCULATE_MINIMAL_STACK_SIZE() \
+ : usCalcMinStackSize )
/*
* WizC uses a downgrowing stack
*/
- #define portSTACK_GROWTH ( -1 )
+#define portSTACK_GROWTH ( -1 )
/*-----------------------------------------------------------*/
@@ -200,120 +200,120 @@
* assembler definitions.
*/
- #define portSAVE_CONTEXT( ucInterruptForced ) \
- do \
- { \
- portDISABLE_INTERRUPTS(); \
- \
- _Pragma( "asm" ) \
- ; \
- ; Push the relevant SFR 's onto the task's stack \
- ; \
- movff STATUS, POSTDEC2 \
- movff WREG, POSTDEC2 \
- movff BSR, POSTDEC2 \
- movff PRODH, POSTDEC2 \
- movff PRODL, POSTDEC2 \
- movff FSR0H, POSTDEC2 \
- movff FSR0L, POSTDEC2 \
- movff FSR1H, POSTDEC2 \
- movff FSR1L, POSTDEC2 \
- movff TABLAT, POSTDEC2 \
- if __ROMSIZE > 0x8000 \
- movff TBLPTRU, POSTDEC2 \
- endif \
- movff TBLPTRH, POSTDEC2 \
- movff TBLPTRL, POSTDEC2 \
- if __ROMSIZE > 0x8000 \
- movff PCLATU, POSTDEC2 \
- endif \
- movff PCLATH, POSTDEC2 \
- ; \
- ; Store the compiler - scratch - area as described above. \
- ; \
- movlw OVERHEADPAGE0 - LOCOPTSIZE + MAXLOCOPTSIZE \
- clrf FSR0L, ACCESS \
- clrf FSR0H, ACCESS \
-_rtos_S1: \
- movff POSTINC0, POSTDEC2 \
- decfsz WREG, W, ACCESS \
- SMARTJUMP _rtos_S1 \
- ; \
- ; Save the pic call / return -stack belonging to the \
- ; current task by copying it to the task 's software- \
+#define portSAVE_CONTEXT( ucInterruptForced ) \
+ do \
+ { \
+ portDISABLE_INTERRUPTS(); \
+ \
+ _Pragma("asm") \
+ ; \
+ ; Push the relevant SFR's onto the task's stack \
+ ; \
+ movff STATUS,POSTDEC2 \
+ movff WREG,POSTDEC2 \
+ movff BSR,POSTDEC2 \
+ movff PRODH,POSTDEC2 \
+ movff PRODL,POSTDEC2 \
+ movff FSR0H,POSTDEC2 \
+ movff FSR0L,POSTDEC2 \
+ movff FSR1H,POSTDEC2 \
+ movff FSR1L,POSTDEC2 \
+ movff TABLAT,POSTDEC2 \
+ if __ROMSIZE > 0x8000 \
+ movff TBLPTRU,POSTDEC2 \
+ endif \
+ movff TBLPTRH,POSTDEC2 \
+ movff TBLPTRL,POSTDEC2 \
+ if __ROMSIZE > 0x8000 \
+ movff PCLATU,POSTDEC2 \
+ endif \
+ movff PCLATH,POSTDEC2 \
+ ; \
+ ; Store the compiler-scratch-area as described above. \
+ ; \
+ movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \
+ clrf FSR0L,ACCESS \
+ clrf FSR0H,ACCESS \
+ _rtos_S1: \
+ movff POSTINC0,POSTDEC2 \
+ decfsz WREG,W,ACCESS \
+ SMARTJUMP _rtos_S1 \
+ ; \
+ ; Save the pic call/return-stack belonging to the \
+ ; current task by copying it to the task's software- \
; stack. We save the hardware stack pointer (which \
; is the number of addresses on the stack) in the \
; W-register first because we need it later and it \
- ; is modified in the save-loop by executing pop's. \
- ; After the loop the W - register is stored on the \
- ; stack, too. \
- ; \
- movf STKPTR, W, ACCESS \
- bz _rtos_s3 \
-_rtos_S2: \
- if __ROMSIZE > 0x8000 \
- movff TOSU, POSTDEC2 \
- endif \
- movff TOSH, POSTDEC2 \
- movff TOSL, POSTDEC2 \
- pop \
- tstfsz STKPTR, ACCESS \
- SMARTJUMP _rtos_S2 \
-_rtos_s3: \
- movwf POSTDEC2, ACCESS \
- ; \
- ; Next the value for ucCriticalNesting used by the \
- ; task is stored on the stack.When \
- ; ( ucInterruptForced == portINTERRUPTS_FORCED ), we save \
- ; it as 0 ( portNO_CRITICAL_SECTION_NESTING ). \
- ; \
- if ucInterruptForced == portINTERRUPTS_FORCED \
- clrf POSTDEC2, ACCESS \
- else{ \
- movff ucCriticalNesting, POSTDEC2 \
- endif \
- ; } \
- ; Save the new top of the software stack in the TCB. \
- ; \
- movff pxCurrentTCB, FSR0L \
- movff pxCurrentTCB + 1, FSR0H \
- movff FSR2L, POSTINC0 \
- movff FSR2H, POSTINC0 \
- _Pragma( "asmend" ) \
- } while( 0 )
+ ; is modified in the save-loop by executing pop's. \
+ ; After the loop the W-register is stored on the \
+ ; stack, too. \
+ ; \
+ movf STKPTR,W,ACCESS \
+ bz _rtos_s3 \
+ _rtos_S2: \
+ if __ROMSIZE > 0x8000 \
+ movff TOSU,POSTDEC2 \
+ endif \
+ movff TOSH,POSTDEC2 \
+ movff TOSL,POSTDEC2 \
+ pop \
+ tstfsz STKPTR,ACCESS \
+ SMARTJUMP _rtos_S2 \
+ _rtos_s3: \
+ movwf POSTDEC2,ACCESS \
+ ; \
+ ; Next the value for ucCriticalNesting used by the \
+ ; task is stored on the stack. When \
+ ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \
+ ; it as 0 (portNO_CRITICAL_SECTION_NESTING). \
+ ; \
+ if ucInterruptForced == portINTERRUPTS_FORCED \
+ clrf POSTDEC2,ACCESS \
+ else \
+ movff ucCriticalNesting,POSTDEC2 \
+ endif \
+ ; \
+ ; Save the new top of the software stack in the TCB. \
+ ; \
+ movff pxCurrentTCB,FSR0L \
+ movff pxCurrentTCB+1,FSR0H \
+ movff FSR2L,POSTINC0 \
+ movff FSR2H,POSTINC0 \
+ _Pragma("asmend") \
+ } while(0)
/************************************************************/
/*
* This is the reverse of portSAVE_CONTEXT.
*/
- #define portRESTORE_CONTEXT() \
- do \
- { \
- _Pragma( "asm" ) \
- ; \
- ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack. \
- ; \
- movff pxCurrentTCB, FSR0L \
- movff pxCurrentTCB + 1, FSR0H \
- ; \
- ; De - reference FSR0 to set the address it holds into \
- ; FSR2( i.e. *( pxCurrentTCB->pxTopOfStack ) ).FSR2 \
- ; is used by wizC as stackpointer. \
- ; \
- movff POSTINC0, FSR2L \
- movff POSTINC0, FSR2H \
- ; \
- ; Next, the value for ucCriticalNesting used by the \
- ; task is retrieved from the stack. \
- ; \
- movff PREINC2, ucCriticalNesting \
- ; \
- ; Rebuild the pic call / return -stack.The number of \
- ; return addresses is the next item on the task stack. \
- ; Save this number in PRODL.Then fetch the addresses \
- ; and store them on the hardwarestack. \
- ; The datasheets say we can 't use movff here... \
+#define portRESTORE_CONTEXT() \
+ do \
+ { \
+ _Pragma("asm") \
+ ; \
+ ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack. \
+ ; \
+ movff pxCurrentTCB,FSR0L \
+ movff pxCurrentTCB+1,FSR0H \
+ ; \
+ ; De-reference FSR0 to set the address it holds into \
+ ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2 \
+ ; is used by wizC as stackpointer. \
+ ; \
+ movff POSTINC0,FSR2L \
+ movff POSTINC0,FSR2H \
+ ; \
+ ; Next, the value for ucCriticalNesting used by the \
+ ; task is retrieved from the stack. \
+ ; \
+ movff PREINC2,ucCriticalNesting \
+ ; \
+ ; Rebuild the pic call/return-stack. The number of \
+ ; return addresses is the next item on the task stack. \
+ ; Save this number in PRODL. Then fetch the addresses \
+ ; and store them on the hardwarestack. \
+ ; The datasheets say we can't use movff here... \
; \
movff PREINC2,PRODL // Use PRODL as tempregister \
clrf STKPTR,ACCESS \
@@ -332,18 +332,18 @@
decfsz PRODL,F,ACCESS \
SMARTJUMP _rtos_R1 \
; \
- ; Restore the compiler's working storage area to page 0 \
- ; \
- movlw OVERHEADPAGE0 - LOCOPTSIZE + MAXLOCOPTSIZE \
- movwf FSR0L, ACCESS \
- clrf FSR0H, ACCESS \
-_rtos_R2: \
- decf FSR0L, F, ACCESS \
- movff PREINC2, INDF0 \
- tstfsz FSR0L, ACCESS \
- SMARTJUMP _rtos_R2 \
- ; \
- ; Restore the sfr 's forming the tasks context. \
+ ; Restore the compiler's working storage area to page 0 \
+ ; \
+ movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \
+ movwf FSR0L,ACCESS \
+ clrf FSR0H,ACCESS \
+ _rtos_R2: \
+ decf FSR0L,F,ACCESS \
+ movff PREINC2,INDF0 \
+ tstfsz FSR0L,ACCESS \
+ SMARTJUMP _rtos_R2 \
+ ; \
+ ; Restore the sfr's forming the tasks context. \
; We cannot yet restore bsr, w and status because \
; we need these registers for a final test. \
; \
@@ -374,8 +374,8 @@
; retfie instruction because we need the \
; interrupt-enabling and the return to the restored \
; task to be uninterruptable. \
- ; Because bsr, status and W are affected by the test \
- ; they are restored after the test. \
+ ; Because bsr, status and W are affected by the test \
+ ; they are restored after the test. \
; \
movlb ucCriticalNesting>>8 \
tstfsz ucCriticalNesting,BANKED \
@@ -408,7 +408,7 @@
/*-----------------------------------------------------------*/
-#define portTASK_FUNCTION( xFunction, pvParameters ) \
+#define portTASK_FUNCTION( xFunction, pvParameters ) \
void pointed xFunction( void *pvParameters ) \
_Pragma(asmfunc xFunction)
@@ -421,14 +421,3 @@
#endif /* PORTMACRO_H */
-
-
-
-
-
-
-
-
-
-
-
diff --git a/portable/oWatcom/16BitDOS/Flsh186/port.c b/portable/oWatcom/16BitDOS/Flsh186/port.c
index cdc5255..e419958 100644
--- a/portable/oWatcom/16BitDOS/Flsh186/port.c
+++ b/portable/oWatcom/16BitDOS/Flsh186/port.c
@@ -26,27 +26,27 @@
*/
/*
- * Changes from V1.00:
- *
- + Call to taskYIELD() from within tick ISR has been replaced by the more
- + efficient portSWITCH_CONTEXT().
- + ISR function definitions renamed to include the prv prefix.
- +
- + Changes from V1.2.0:
- +
- + portRESET_PIC() is now called last thing before the end of the preemptive
- + tick routine.
- +
- + Changes from V2.6.1
- +
- + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
- + macro to be consistent with the later ports.
- */
+Changes from V1.00:
+
+ + Call to taskYIELD() from within tick ISR has been replaced by the more
+ efficient portSWITCH_CONTEXT().
+ + ISR function definitions renamed to include the prv prefix.
+
+Changes from V1.2.0:
+
+ + portRESET_PIC() is now called last thing before the end of the preemptive
+ tick routine.
+
+Changes from V2.6.1
+
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+ macro to be consistent with the later ports.
+*/
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Flashlite 186
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Flashlite 186
+ * port.
+ *----------------------------------------------------------*/
#include <stdlib.h>
#include <i86.h>
@@ -59,13 +59,13 @@
/*lint -e950 Non ANSI reserved words okay in this file only. */
-#define portTIMER_EOI_TYPE ( 8 )
-#define portRESET_PIC() portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
-#define portTIMER_INT_NUMBER 0x12
+#define portTIMER_EOI_TYPE ( 8 )
+#define portRESET_PIC() portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
+#define portTIMER_INT_NUMBER 0x12
-#define portTIMER_1_CONTROL_REGISTER ( ( uint16_t ) 0xff5e )
-#define portTIMER_0_CONTROL_REGISTER ( ( uint16_t ) 0xff56 )
-#define portTIMER_INTERRUPT_ENABLE ( ( uint16_t ) 0x2000 )
+#define portTIMER_1_CONTROL_REGISTER ( ( uint16_t ) 0xff5e )
+#define portTIMER_0_CONTROL_REGISTER ( ( uint16_t ) 0xff56 )
+#define portTIMER_INTERRUPT_ENABLE ( ( uint16_t ) 0x2000 )
/* Setup the hardware to generate the required tick frequency. */
static void prvSetTickFrequency( uint32_t ulTickRateHz );
@@ -74,15 +74,13 @@
static void prvExitFunction( void );
#if configUSE_PREEMPTION == 1
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
- static void __interrupt __far prvPreemptiveTick( void );
+ /* Tick service routine used by the scheduler when preemptive scheduling is
+ being used. */
+ static void __interrupt __far prvPreemptiveTick( void );
#else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
- static void __interrupt __far prvNonPreemptiveTick( void );
+ /* Tick service routine used by the scheduler when cooperative scheduling is
+ being used. */
+ static void __interrupt __far prvNonPreemptiveTick( void );
#endif
/* Trap routine used by taskYIELD() to manually cause a context switch. */
@@ -94,7 +92,7 @@
static int16_t sSchedulerRunning = pdFALSE;
/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISR )();
+static void ( __interrupt __far *pxOldSwitchISR )();
/* Used to restore the original DOS context when the scheduler is ended. */
static jmp_buf xJumpBuf;
@@ -104,145 +102,145 @@
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- /* This is called with interrupts already disabled. */
+ /* This is called with interrupts already disabled. */
- /* Remember what was on the interrupts we are going to use
- * so we can put them back later if required. */
- pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+ /* Remember what was on the interrupts we are going to use
+ so we can put them back later if required. */
+ pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
- /* Put our manual switch (yield) function on a known
- * vector. */
- _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+ /* Put our manual switch (yield) function on a known
+ vector. */
+ _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
- #if configUSE_PREEMPTION == 1
- {
- /* Put our tick switch function on the timer interrupt. */
- _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
- }
- #else
- {
- /* We want the timer interrupt to just increment the tick count. */
- _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
- }
- #endif
+ #if configUSE_PREEMPTION == 1
+ {
+ /* Put our tick switch function on the timer interrupt. */
+ _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+ }
+ #else
+ {
+ /* We want the timer interrupt to just increment the tick count. */
+ _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+ }
+ #endif
- prvSetTickFrequency( configTICK_RATE_HZ );
+ prvSetTickFrequency( configTICK_RATE_HZ );
- /* Clean up function if we want to return to DOS. */
- if( setjmp( xJumpBuf ) != 0 )
- {
- prvExitFunction();
- sSchedulerRunning = pdFALSE;
- }
- else
- {
- sSchedulerRunning = pdTRUE;
+ /* Clean up function if we want to return to DOS. */
+ if( setjmp( xJumpBuf ) != 0 )
+ {
+ prvExitFunction();
+ sSchedulerRunning = pdFALSE;
+ }
+ else
+ {
+ sSchedulerRunning = pdTRUE;
- /* Kick off the scheduler by setting up the context of the first task. */
- portFIRST_CONTEXT();
- }
+ /* Kick off the scheduler by setting up the context of the first task. */
+ portFIRST_CONTEXT();
+ }
- return sSchedulerRunning;
+ return sSchedulerRunning;
}
/*-----------------------------------------------------------*/
/* The tick ISR used depend on whether or not the preemptive or cooperative
- * kernel is being used. */
+kernel is being used. */
#if configUSE_PREEMPTION == 1
- static void __interrupt __far prvPreemptiveTick( void )
- {
- /* Get the scheduler to update the task states following the tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Switch in the context of the next task to be run. */
- portSWITCH_CONTEXT();
- }
+ static void __interrupt __far prvPreemptiveTick( void )
+ {
+ /* Get the scheduler to update the task states following the tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Switch in the context of the next task to be run. */
+ portSWITCH_CONTEXT();
+ }
- /* Reset the PIC ready for the next time. */
- portRESET_PIC();
- }
-#else /* if configUSE_PREEMPTION == 1 */
- static void __interrupt __far prvNonPreemptiveTick( void )
- {
- /* Same as preemptive tick, but the cooperative scheduler is being used
- * so we don't have to switch in the context of the next task. */
- xTaskIncrementTick();
- portRESET_PIC();
- }
-#endif /* if configUSE_PREEMPTION == 1 */
+ /* Reset the PIC ready for the next time. */
+ portRESET_PIC();
+ }
+#else
+ static void __interrupt __far prvNonPreemptiveTick( void )
+ {
+ /* Same as preemptive tick, but the cooperative scheduler is being used
+ so we don't have to switch in the context of the next task. */
+ xTaskIncrementTick();
+ portRESET_PIC();
+ }
+#endif
/*-----------------------------------------------------------*/
static void __interrupt __far prvYieldProcessor( void )
{
- /* Switch in the context of the next task to be run. */
- portSWITCH_CONTEXT();
+ /* Switch in the context of the next task to be run. */
+ portSWITCH_CONTEXT();
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Jump back to the processor state prior to starting the
- * scheduler. This means we are not going to be using a
- * task stack frame so the task can be deleted. */
- longjmp( xJumpBuf, 1 );
+ /* Jump back to the processor state prior to starting the
+ scheduler. This means we are not going to be using a
+ task stack frame so the task can be deleted. */
+ longjmp( xJumpBuf, 1 );
}
/*-----------------------------------------------------------*/
static void prvExitFunction( void )
{
- const uint16_t usTimerDisable = 0x0000;
- uint16_t usTimer0Control;
+const uint16_t usTimerDisable = 0x0000;
+uint16_t usTimer0Control;
- /* Interrupts should be disabled here anyway - but no
- * harm in making sure. */
- portDISABLE_INTERRUPTS();
+ /* Interrupts should be disabled here anyway - but no
+ harm in making sure. */
+ portDISABLE_INTERRUPTS();
+ if( sSchedulerRunning == pdTRUE )
+ {
+ /* Put back the switch interrupt routines that was in place
+ before the scheduler started. */
+ _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+ }
- if( sSchedulerRunning == pdTRUE )
- {
- /* Put back the switch interrupt routines that was in place
- * before the scheduler started. */
- _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
- }
+ /* Disable the timer used for the tick to ensure the scheduler is
+ not called before restoring interrupts. There was previously nothing
+ on this timer so there is no old ISR to restore. */
+ portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
- /* Disable the timer used for the tick to ensure the scheduler is
- * not called before restoring interrupts. There was previously nothing
- * on this timer so there is no old ISR to restore. */
- portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
-
- /* Restart the DOS tick. */
- usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
- usTimer0Control |= portTIMER_INTERRUPT_ENABLE;
- portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+ /* Restart the DOS tick. */
+ usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+ usTimer0Control |= portTIMER_INTERRUPT_ENABLE;
+ portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
- portENABLE_INTERRUPTS();
+ portENABLE_INTERRUPTS();
}
/*-----------------------------------------------------------*/
static void prvSetTickFrequency( uint32_t ulTickRateHz )
{
- const uint16_t usMaxCountRegister = 0xff5a;
- const uint16_t usTimerPriorityRegister = 0xff32;
- const uint16_t usTimerEnable = 0xC000;
- const uint16_t usRetrigger = 0x0001;
- const uint16_t usTimerHighPriority = 0x0000;
- uint16_t usTimer0Control;
+const uint16_t usMaxCountRegister = 0xff5a;
+const uint16_t usTimerPriorityRegister = 0xff32;
+const uint16_t usTimerEnable = 0xC000;
+const uint16_t usRetrigger = 0x0001;
+const uint16_t usTimerHighPriority = 0x0000;
+uint16_t usTimer0Control;
/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
- const uint32_t ulClockFrequency = 0x7f31a0;
+const uint32_t ulClockFrequency = 0x7f31a0;
- uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
+uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
- portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
- portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
- portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );
+ portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
+ portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
+ portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );
- /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */
- usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
- usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;
- portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+ /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */
+ usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+ usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;
+ portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
}
/*lint +e950 */
+
diff --git a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
index 57414c6..75dbff0 100644
--- a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
+++ b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -44,66 +44,67 @@
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE long
- #define portLONG long
- #define portSHORT int
- #define portSTACK_TYPE uint16_t
- #define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE long
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
- typedef portSTACK_TYPE StackType_t;
- typedef short BaseType_t;
- typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Critical section management. */
- void portENTER_CRITICAL( void );
- #pragma aux portENTER_CRITICAL = "pushf" \
- "cli";
+void portENTER_CRITICAL( void );
+#pragma aux portENTER_CRITICAL = "pushf" \
+ "cli";
- void portEXIT_CRITICAL( void );
- #pragma aux portEXIT_CRITICAL = "popf";
+void portEXIT_CRITICAL( void );
+#pragma aux portEXIT_CRITICAL = "popf";
- void portDISABLE_INTERRUPTS( void );
- #pragma aux portDISABLE_INTERRUPTS = "cli";
+void portDISABLE_INTERRUPTS( void );
+#pragma aux portDISABLE_INTERRUPTS = "cli";
- void portENABLE_INTERRUPTS( void );
- #pragma aux portENABLE_INTERRUPTS = "sti";
+void portENABLE_INTERRUPTS( void );
+#pragma aux portENABLE_INTERRUPTS = "sti";
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portSWITCH_INT_NUMBER 0x80
- #define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 2
- #define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
- #define portNOP() __asm{ nop }
+#define portSTACK_GROWTH ( -1 )
+#define portSWITCH_INT_NUMBER 0x80
+#define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 2
+#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
+#define portNOP() __asm{ nop }
/*-----------------------------------------------------------*/
/* Compiler specifics. */
- #define portINPUT_BYTE( xAddr ) inp( xAddr )
- #define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
- #define portINPUT_WORD( xAddr ) inpw( xAddr )
- #define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr ) inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr ) inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/oWatcom/16BitDOS/PC/port.c b/portable/oWatcom/16BitDOS/PC/port.c
index 7ef979d..c20ad7c 100644
--- a/portable/oWatcom/16BitDOS/PC/port.c
+++ b/portable/oWatcom/16BitDOS/PC/port.c
@@ -26,27 +26,27 @@
*/
/*
- * Changes from V1.00:
- *
- + Call to taskYIELD() from within tick ISR has been replaced by the more
- + efficient portSWITCH_CONTEXT().
- + ISR function definitions renamed to include the prv prefix.
- +
- + Changes from V1.2.0:
- +
- + prvPortResetPIC() is now called last thing before the end of the
- + preemptive tick routine.
- +
- + Changes from V2.6.1
- +
- + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
- + macro to be consistent with the later ports.
- +
- + Changes from V4.0.1
- +
- + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
- + its proper value when the scheduler exits.
- */
+Changes from V1.00:
+
+ + Call to taskYIELD() from within tick ISR has been replaced by the more
+ efficient portSWITCH_CONTEXT().
+ + ISR function definitions renamed to include the prv prefix.
+
+Changes from V1.2.0:
+
+ + prvPortResetPIC() is now called last thing before the end of the
+ preemptive tick routine.
+
+Changes from V2.6.1
+
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+ macro to be consistent with the later ports.
+
+Changes from V4.0.1
+
+ + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+ its proper value when the scheduler exits.
+*/
#include <stdlib.h>
#include <stdio.h>
@@ -59,13 +59,13 @@
#include "portasm.h"
/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the industrial
-* PC port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the industrial
+ * PC port.
+ *----------------------------------------------------------*/
/*lint -e950 Non ANSI reserved words okay in this file only. */
-#define portTIMER_INT_NUMBER 0x08
+#define portTIMER_INT_NUMBER 0x08
/* Setup hardware for required tick interrupt rate. */
static void prvSetTickFrequency( uint32_t ulTickRateHz );
@@ -74,43 +74,41 @@
static void prvExitFunction( void );
/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
- * directly. We chain to the DOS tick as close as possible to the standard DOS
- * tick rate. */
+directly. We chain to the DOS tick as close as possible to the standard DOS
+tick rate. */
static void prvPortResetPIC( void );
/* The tick ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
+is being used. */
#if configUSE_PREEMPTION == 1
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
- static void __interrupt __far prvPreemptiveTick( void );
+ /* Tick service routine used by the scheduler when preemptive scheduling is
+ being used. */
+ static void __interrupt __far prvPreemptiveTick( void );
#else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
- static void __interrupt __far prvNonPreemptiveTick( void );
+ /* Tick service routine used by the scheduler when cooperative scheduling is
+ being used. */
+ static void __interrupt __far prvNonPreemptiveTick( void );
#endif
/* Trap routine used by taskYIELD() to manually cause a context switch. */
static void __interrupt __far prvYieldProcessor( void );
/* Set the tick frequency back so the floppy drive works correctly when the
- * scheduler exits. */
+scheduler exits. */
static void prvSetTickFrequencyDefault( void );
/*lint -e956 File scopes necessary here. */
/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */
-static int16_t sDOSTickCounter;
+static int16_t sDOSTickCounter;
/* Set true when the vectors are set so the scheduler will service the tick. */
-static int16_t sSchedulerRunning = pdFALSE;
+static int16_t sSchedulerRunning = pdFALSE;
/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISR )();
+static void ( __interrupt __far *pxOldSwitchISR )();
/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISRPlus1 )();
+static void ( __interrupt __far *pxOldSwitchISRPlus1 )();
/* Used to restore the original DOS context when the scheduler is ended. */
static jmp_buf xJumpBuf;
@@ -120,190 +118,185 @@
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
- pxISR pxOriginalTickISR;
+pxISR pxOriginalTickISR;
+
+ /* This is called with interrupts already disabled. */
- /* This is called with interrupts already disabled. */
+ /* Remember what was on the interrupts we are going to use
+ so we can put them back later if required. */
+ pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+ pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
+ pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
- /* Remember what was on the interrupts we are going to use
- * so we can put them back later if required. */
- pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
- pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
- pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+ prvSetTickFrequency( configTICK_RATE_HZ );
- prvSetTickFrequency( configTICK_RATE_HZ );
+ /* Put our manual switch (yield) function on a known
+ vector. */
+ _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
- /* Put our manual switch (yield) function on a known
- * vector. */
- _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+ /* Put the old tick on a different interrupt number so we can
+ call it when we want. */
+ _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
- /* Put the old tick on a different interrupt number so we can
- * call it when we want. */
- _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
+ #if configUSE_PREEMPTION == 1
+ {
+ /* Put our tick switch function on the timer interrupt. */
+ _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+ }
+ #else
+ {
+ /* We want the timer interrupt to just increment the tick count. */
+ _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+ }
+ #endif
- #if configUSE_PREEMPTION == 1
- {
- /* Put our tick switch function on the timer interrupt. */
- _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
- }
- #else
- {
- /* We want the timer interrupt to just increment the tick count. */
- _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
- }
- #endif
+ /* Setup a counter that is used to call the DOS interrupt as close
+ to it's original frequency as can be achieved given our chosen tick
+ frequency. */
+ sDOSTickCounter = portTICKS_PER_DOS_TICK;
- /* Setup a counter that is used to call the DOS interrupt as close
- * to it's original frequency as can be achieved given our chosen tick
- * frequency. */
- sDOSTickCounter = portTICKS_PER_DOS_TICK;
+ /* Clean up function if we want to return to DOS. */
+ if( setjmp( xJumpBuf ) != 0 )
+ {
+ prvExitFunction();
+ sSchedulerRunning = pdFALSE;
+ }
+ else
+ {
+ sSchedulerRunning = pdTRUE;
- /* Clean up function if we want to return to DOS. */
- if( setjmp( xJumpBuf ) != 0 )
- {
- prvExitFunction();
- sSchedulerRunning = pdFALSE;
- }
- else
- {
- sSchedulerRunning = pdTRUE;
+ /* Kick off the scheduler by setting up the context of the first task. */
+ portFIRST_CONTEXT();
+ }
- /* Kick off the scheduler by setting up the context of the first task. */
- portFIRST_CONTEXT();
- }
-
- return sSchedulerRunning;
+ return sSchedulerRunning;
}
/*-----------------------------------------------------------*/
/* The tick ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
+is being used. */
#if configUSE_PREEMPTION == 1
+ /* Tick service routine used by the scheduler when preemptive scheduling is
+ being used. */
+ static void __interrupt __far prvPreemptiveTick( void )
+ {
+ /* Get the scheduler to update the task states following the tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Switch in the context of the next task to be run. */
+ portSWITCH_CONTEXT();
+ }
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
- static void __interrupt __far prvPreemptiveTick( void )
- {
- /* Get the scheduler to update the task states following the tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Switch in the context of the next task to be run. */
- portSWITCH_CONTEXT();
- }
-
- /* Reset the PIC ready for the next time. */
- prvPortResetPIC();
- }
-#else /* if configUSE_PREEMPTION == 1 */
- static void __interrupt __far prvNonPreemptiveTick( void )
- {
- /* Same as preemptive tick, but the cooperative scheduler is being used
- * so we don't have to switch in the context of the next task. */
- xTaskIncrementTick();
- prvPortResetPIC();
- }
-#endif /* if configUSE_PREEMPTION == 1 */
+ /* Reset the PIC ready for the next time. */
+ prvPortResetPIC();
+ }
+#else
+ static void __interrupt __far prvNonPreemptiveTick( void )
+ {
+ /* Same as preemptive tick, but the cooperative scheduler is being used
+ so we don't have to switch in the context of the next task. */
+ xTaskIncrementTick();
+ prvPortResetPIC();
+ }
+#endif
/*-----------------------------------------------------------*/
static void __interrupt __far prvYieldProcessor( void )
{
- /* Switch in the context of the next task to be run. */
- portSWITCH_CONTEXT();
+ /* Switch in the context of the next task to be run. */
+ portSWITCH_CONTEXT();
}
/*-----------------------------------------------------------*/
static void prvPortResetPIC( void )
{
- /* We are going to call the DOS tick interrupt at as close a
- * frequency to the normal DOS tick as possible. */
+ /* We are going to call the DOS tick interrupt at as close a
+ frequency to the normal DOS tick as possible. */
- /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
- --sDOSTickCounter;
-
- if( sDOSTickCounter <= 0 )
- {
- sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
- __asm {
- int portSWITCH_INT_NUMBER + 1
- };
- }
- else
- {
- /* Reset the PIC as the DOS tick is not being called to
- * do it. */
- __asm
- {
- mov al, 20H
- out 20H, al
- };
- }
+ /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
+ --sDOSTickCounter;
+ if( sDOSTickCounter <= 0 )
+ {
+ sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
+ __asm{ int portSWITCH_INT_NUMBER + 1 };
+ }
+ else
+ {
+ /* Reset the PIC as the DOS tick is not being called to
+ do it. */
+ __asm
+ {
+ mov al, 20H
+ out 20H, al
+ };
+ }
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Jump back to the processor state prior to starting the
- * scheduler. This means we are not going to be using a
- * task stack frame so the task can be deleted. */
- longjmp( xJumpBuf, 1 );
+ /* Jump back to the processor state prior to starting the
+ scheduler. This means we are not going to be using a
+ task stack frame so the task can be deleted. */
+ longjmp( xJumpBuf, 1 );
}
/*-----------------------------------------------------------*/
static void prvExitFunction( void )
{
- void( __interrupt __far * pxOriginalTickISR )();
+void ( __interrupt __far *pxOriginalTickISR )();
- /* Interrupts should be disabled here anyway - but no
- * harm in making sure. */
- portDISABLE_INTERRUPTS();
+ /* Interrupts should be disabled here anyway - but no
+ harm in making sure. */
+ portDISABLE_INTERRUPTS();
+ if( sSchedulerRunning == pdTRUE )
+ {
+ /* Set the DOS tick back onto the timer ticker. */
+ pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+ _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );
+ prvSetTickFrequencyDefault();
- if( sSchedulerRunning == pdTRUE )
- {
- /* Set the DOS tick back onto the timer ticker. */
- pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
- _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );
- prvSetTickFrequencyDefault();
-
- /* Put back the switch interrupt routines that was in place
- * before the scheduler started. */
- _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
- _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
- }
-
- /* The tick timer is back how DOS wants it. We can re-enable
- * interrupts without the scheduler being called. */
- portENABLE_INTERRUPTS();
+ /* Put back the switch interrupt routines that was in place
+ before the scheduler started. */
+ _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+ _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
+ }
+ /* The tick timer is back how DOS wants it. We can re-enable
+ interrupts without the scheduler being called. */
+ portENABLE_INTERRUPTS();
}
/*-----------------------------------------------------------*/
static void prvSetTickFrequency( uint32_t ulTickRateHz )
{
- const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
- const uint16_t usPIT0 = ( uint16_t ) 0x40;
- const uint32_t ulPIT_CONST = ( uint32_t ) 1193180;
- const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
- uint32_t ulOutput;
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint32_t ulPIT_CONST = ( uint32_t ) 1193180;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+uint32_t ulOutput;
- /* Setup the 8245 to tick at the wanted frequency. */
- portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
- ulOutput = ulPIT_CONST / ulTickRateHz;
-
- portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
- ulOutput >>= 8;
- portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
+ /* Setup the 8245 to tick at the wanted frequency. */
+ portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+ ulOutput = ulPIT_CONST / ulTickRateHz;
+
+ portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
+ ulOutput >>= 8;
+ portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
}
/*-----------------------------------------------------------*/
static void prvSetTickFrequencyDefault( void )
{
- const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
- const uint16_t usPIT0 = ( uint16_t ) 0x40;
- const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
- portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
- portOUTPUT_BYTE( usPIT0, 0 );
- portOUTPUT_BYTE( usPIT0, 0 );
+ portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+ portOUTPUT_BYTE( usPIT0,0 );
+ portOUTPUT_BYTE( usPIT0,0 );
}
/*lint +e950 */
+
diff --git a/portable/oWatcom/16BitDOS/PC/portmacro.h b/portable/oWatcom/16BitDOS/PC/portmacro.h
index 7489ffe..d65ed36 100644
--- a/portable/oWatcom/16BitDOS/PC/portmacro.h
+++ b/portable/oWatcom/16BitDOS/PC/portmacro.h
@@ -26,11 +26,11 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+extern "C" {
+#endif
/*-----------------------------------------------------------
* Port specific definitions.
@@ -43,69 +43,70 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT int
- #define portSTACK_TYPE uint16_t
- #define portBASE_TYPE short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
- typedef portSTACK_TYPE StackType_t;
- typedef short BaseType_t;
- typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- #endif
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
/*-----------------------------------------------------------*/
/* Critical section definitions. portENTER_CRITICAL() must be defined as a
- * macro for portable.h to work properly. */
- void portLOCAL_ENTER_CRITICAL( void );
- #pragma aux portLOCAL_ENTER_CRITICAL = "pushf" \
- "cli";
- #define portENTER_CRITICAL() portLOCAL_ENTER_CRITICAL()
+macro for portable.h to work properly. */
+void portLOCAL_ENTER_CRITICAL( void );
+#pragma aux portLOCAL_ENTER_CRITICAL = "pushf" \
+ "cli";
+#define portENTER_CRITICAL() portLOCAL_ENTER_CRITICAL()
- void portEXIT_CRITICAL( void );
- #pragma aux portEXIT_CRITICAL = "popf";
+void portEXIT_CRITICAL( void );
+#pragma aux portEXIT_CRITICAL = "popf";
- void portDISABLE_INTERRUPTS( void );
- #pragma aux portDISABLE_INTERRUPTS = "cli";
+void portDISABLE_INTERRUPTS( void );
+#pragma aux portDISABLE_INTERRUPTS = "cli";
- void portENABLE_INTERRUPTS( void );
- #pragma aux portENABLE_INTERRUPTS = "sti";
+void portENABLE_INTERRUPTS( void );
+#pragma aux portENABLE_INTERRUPTS = "sti";
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portSWITCH_INT_NUMBER 0x80
- #define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
- #define portDOS_TICK_RATE ( 18.20648 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portTICKS_PER_DOS_TICK ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
- #define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
- #define portBYTE_ALIGNMENT ( 2 )
+#define portSTACK_GROWTH ( -1 )
+#define portSWITCH_INT_NUMBER 0x80
+#define portYIELD() __asm{ int portSWITCH_INT_NUMBER }
+#define portDOS_TICK_RATE ( 18.20648 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICKS_PER_DOS_TICK ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
+#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
+#define portBYTE_ALIGNMENT ( 2 )
/*-----------------------------------------------------------*/
/* Compiler specifics. */
- #define portINPUT_BYTE( xAddr ) inp( xAddr )
- #define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
- #define portNOP() __asm{ nop }
+#define portINPUT_BYTE( xAddr ) inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue )
+#define portNOP() __asm{ nop }
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void * pvParameters )
- #define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+}
+#endif
#endif /* PORTMACRO_H */
+
diff --git a/portable/oWatcom/16BitDOS/common/portasm.h b/portable/oWatcom/16BitDOS/common/portasm.h
index bb5b9e7..5a3f250 100644
--- a/portable/oWatcom/16BitDOS/common/portasm.h
+++ b/portable/oWatcom/16BitDOS/common/portasm.h
@@ -29,10 +29,10 @@
extern volatile TCB_t * volatile pxCurrentTCB;
extern void vTaskSwitchContext( void );
-/*
- * Saves the stack pointer for one task into its TCB, calls
- * vTaskSwitchContext() to update the TCB being used, then restores the stack
- * from the new TCB read to run the task.
+/*
+ * Saves the stack pointer for one task into its TCB, calls
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack
+ * from the new TCB read to run the task.
*/
void portSWITCH_CONTEXT( void );
@@ -44,65 +44,67 @@
void portFIRST_CONTEXT( void );
/* There are slightly different versions depending on whether you are building
- * to include debugger information. If debugger information is used then there
- * are a couple of extra bytes left of the ISR stack (presumably for use by the
- * debugger). The true stack pointer is then stored in the bp register. We add
- * 2 to the stack pointer to remove the extra bytes before we restore our context. */
+to include debugger information. If debugger information is used then there
+are a couple of extra bytes left of the ISR stack (presumably for use by the
+debugger). The true stack pointer is then stored in the bp register. We add
+2 to the stack pointer to remove the extra bytes before we restore our context. */
#ifdef DEBUG_BUILD
- #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \
- "mov ds, ax" \
- "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \
- "mov es:0x2[ bx ], ss" \
- "mov es:[ bx ], sp" \
- "call vTaskSwitchContext" /* Perform the switch. */ \
- "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \
- "mov ds, ax" \
- "les bx, dword ptr pxCurrentTCB" \
- "mov ss, es:[ bx + 2 ]" \
- "mov sp, es:[ bx ]" \
- "mov bp, sp" /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */\
- "add bp, 0x0002"
+ #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \
+ "mov ds, ax" \
+ "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \
+ "mov es:0x2[ bx ], ss" \
+ "mov es:[ bx ], sp" \
+ "call vTaskSwitchContext" /* Perform the switch. */ \
+ "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \
+ "mov ds, ax" \
+ "les bx, dword ptr pxCurrentTCB" \
+ "mov ss, es:[ bx + 2 ]" \
+ "mov sp, es:[ bx ]" \
+ "mov bp, sp" /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \
+ "add bp, 0x0002"
+
+
+
+ #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \
+ "mov ds, ax" \
+ "les bx, dword ptr pxCurrentTCB" \
+ "mov ss, es:[ bx + 2 ]" \
+ "mov sp, es:[ bx ]" \
+ "add sp, 0x0002" /* Remove the extra bytes that exist in debug builds before restoring the context. */ \
+ "pop ax" \
+ "pop ax" \
+ "pop es" \
+ "pop ds" \
+ "popa" \
+ "iret"
+#else
+
+ #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \
+ "mov ds, ax" \
+ "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \
+ "mov es:0x2[ bx ], ss" \
+ "mov es:[ bx ], sp" \
+ "call vTaskSwitchContext" /* Perform the switch. */ \
+ "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \
+ "mov ds, ax" \
+ "les bx, dword ptr pxCurrentTCB" \
+ "mov ss, es:[ bx + 2 ]" \
+ "mov sp, es:[ bx ]"
+
+
+ #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \
+ "mov ds, ax" \
+ "les bx, dword ptr pxCurrentTCB" \
+ "mov ss, es:[ bx + 2 ]" \
+ "mov sp, es:[ bx ]" \
+ "pop ax" \
+ "pop ax" \
+ "pop es" \
+ "pop ds" \
+ "popa" \
+ "iret"
+#endif
-
- #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \
- "mov ds, ax" \
- "les bx, dword ptr pxCurrentTCB" \
- "mov ss, es:[ bx + 2 ]" \
- "mov sp, es:[ bx ]" \
- "add sp, 0x0002" /* Remove the extra bytes that exist in debug builds before restoring the context. */\
- "pop ax" \
- "pop ax" \
- "pop es" \
- "pop ds" \
- "popa" \
- "iret"
-#else /* ifdef DEBUG_BUILD */
-
- #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \
- "mov ds, ax" \
- "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */\
- "mov es:0x2[ bx ], ss" \
- "mov es:[ bx ], sp" \
- "call vTaskSwitchContext" /* Perform the switch. */ \
- "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */\
- "mov ds, ax" \
- "les bx, dword ptr pxCurrentTCB" \
- "mov ss, es:[ bx + 2 ]" \
- "mov sp, es:[ bx ]"
-
-
- #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB"\
- "mov ds, ax" \
- "les bx, dword ptr pxCurrentTCB" \
- "mov ss, es:[ bx + 2 ]" \
- "mov sp, es:[ bx ]" \
- "pop ax" \
- "pop ax" \
- "pop es" \
- "pop ds" \
- "popa" \
- "iret"
-#endif /* ifdef DEBUG_BUILD */
diff --git a/portable/oWatcom/16BitDOS/common/portcomn.c b/portable/oWatcom/16BitDOS/common/portcomn.c
index 3e03a50..5abca63 100644
--- a/portable/oWatcom/16BitDOS/common/portcomn.c
+++ b/portable/oWatcom/16BitDOS/common/portcomn.c
@@ -26,23 +26,23 @@
*/
/*
- * Changes from V1.00:
- *
- + pxPortInitialiseStack() now initialises the stack of new tasks to the
- + same format used by the compiler. This allows the compiler generated
- + interrupt mechanism to be used for context switches.
- +
- + Changes from V2.4.2:
- +
- + pvPortMalloc and vPortFree have been removed. The projects now use
- + the definitions from the source/portable/MemMang directory.
- +
- + Changes from V2.6.1:
- +
- + usPortCheckFreeStackSpace() has been moved to tasks.c.
- */
+Changes from V1.00:
+
+ + pxPortInitialiseStack() now initialises the stack of new tasks to the
+ same format used by the compiler. This allows the compiler generated
+ interrupt mechanism to be used for context switches.
+Changes from V2.4.2:
+ + pvPortMalloc and vPortFree have been removed. The projects now use
+ the definitions from the source/portable/MemMang directory.
+
+Changes from V2.6.1:
+
+ + usPortCheckFreeStackSpace() has been moved to tasks.c.
+*/
+
+
#include <stdlib.h>
#include "FreeRTOS.h"
@@ -50,95 +50,92 @@
/*-----------------------------------------------------------*/
/* See header file for description. */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- StackType_t DS_Reg = 0, * pxOriginalSP;
+StackType_t DS_Reg = 0, *pxOriginalSP;
- /* Place a few bytes of known values on the bottom of the stack.
- * This is just useful for debugging. */
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
- *pxTopOfStack = 0x1111;
- pxTopOfStack--;
- *pxTopOfStack = 0x2222;
- pxTopOfStack--;
- *pxTopOfStack = 0x3333;
- pxTopOfStack--;
- *pxTopOfStack = 0x4444;
- pxTopOfStack--;
- *pxTopOfStack = 0x5555;
- pxTopOfStack--;
+ *pxTopOfStack = 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x3333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x4444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x5555;
+ pxTopOfStack--;
- /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
- /* We are going to start the scheduler using a return from interrupt
- * instruction to load the program counter, so first there would be the
- * status register and interrupt return address. We make this the start
- * of the task. */
- *pxTopOfStack = portINITIAL_SW;
- pxTopOfStack--;
- *pxTopOfStack = FP_SEG( pxCode );
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pxCode );
- pxTopOfStack--;
+ /* We are going to start the scheduler using a return from interrupt
+ instruction to load the program counter, so first there would be the
+ status register and interrupt return address. We make this the start
+ of the task. */
+ *pxTopOfStack = portINITIAL_SW;
+ pxTopOfStack--;
+ *pxTopOfStack = FP_SEG( pxCode );
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pxCode );
+ pxTopOfStack--;
- /* We are going to setup the stack for the new task to look like
- * the stack frame was setup by a compiler generated ISR. We need to know
- * the address of the existing stack top to place in the SP register within
- * the stack frame. pxOriginalSP holds SP before (simulated) pusha was
- * called. */
- pxOriginalSP = pxTopOfStack;
+ /* We are going to setup the stack for the new task to look like
+ the stack frame was setup by a compiler generated ISR. We need to know
+ the address of the existing stack top to place in the SP register within
+ the stack frame. pxOriginalSP holds SP before (simulated) pusha was
+ called. */
+ pxOriginalSP = pxTopOfStack;
- /* The remaining registers would be pushed on the stack by our context
- * switch function. These are loaded with values simply to make debugging
- * easier. */
- *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */
- pxTopOfStack--;
- *pxTopOfStack = FP_SEG( pvParameters ); /* DX */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pxOriginalSP ); /* SP */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */
+ /* The remaining registers would be pushed on the stack by our context
+ switch function. These are loaded with values simply to make debugging
+ easier. */
+ *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */
+ pxTopOfStack--;
+ *pxTopOfStack = FP_SEG( pvParameters ); /* DX */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pxOriginalSP ); /* SP */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */
- /* We need the true data segment. */
- __asm {
- MOV DS_Reg, DS
- };
+ /* We need the true data segment. */
+ __asm{ MOV DS_Reg, DS };
- pxTopOfStack--;
- *pxTopOfStack = DS_Reg; /* DS */
+ pxTopOfStack--;
+ *pxTopOfStack = DS_Reg; /* DS */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */
- /* The AX register is pushed again twice - don't know why. */
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
- pxTopOfStack--;
- *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
+ /* The AX register is pushed again twice - don't know why. */
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
+ pxTopOfStack--;
+ *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
- #ifdef DEBUG_BUILD
+ #ifdef DEBUG_BUILD
+ /* The compiler adds space to each ISR stack if building to
+ include debug information. Presumably this is used by the
+ debugger - we don't need to initialise it to anything just
+ make sure it is there. */
+ pxTopOfStack--;
+ #endif
- /* The compiler adds space to each ISR stack if building to
- * include debug information. Presumably this is used by the
- * debugger - we don't need to initialise it to anything just
- * make sure it is there. */
- pxTopOfStack--;
- #endif
+ /*lint +e950 +e611 +e923 */
- /*lint +e950 +e611 +e923 */
-
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
+
+
