fix typos in comments: interace -> interface, swtich -> switch (#1022)
Fix typos in comments: interace -> interface, swtich -> switch.
Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
diff --git a/portable/GCC/ARM_AARCH64/README.md b/portable/GCC/ARM_AARCH64/README.md
index 0bee969..60f6701 100644
--- a/portable/GCC/ARM_AARCH64/README.md
+++ b/portable/GCC/ARM_AARCH64/README.md
@@ -20,4 +20,4 @@
application processors.
* ARM_AARCH64
- * Memory mapped interace to access Arm GIC registers
+ * Memory mapped interface to access Arm GIC registers
diff --git a/portable/GCC/ARM_AARCH64_SRE/README.md b/portable/GCC/ARM_AARCH64_SRE/README.md
index 4c9a55a..129b0e3 100644
--- a/portable/GCC/ARM_AARCH64_SRE/README.md
+++ b/portable/GCC/ARM_AARCH64_SRE/README.md
@@ -20,4 +20,4 @@
application processors.
* ARM_AARCH64_SRE
- * System Register interace to access Arm GIC registers
+ * System Register interface to access Arm GIC registers
diff --git a/portable/GCC/ARM_CA53_64_BIT/README.md b/portable/GCC/ARM_CA53_64_BIT/README.md
index a8df29e..578b475 100644
--- a/portable/GCC/ARM_CA53_64_BIT/README.md
+++ b/portable/GCC/ARM_CA53_64_BIT/README.md
@@ -4,7 +4,7 @@
Arm Cortex-A53 processor.
* ARM_CA53_64_BIT
- * Memory mapped interace to access Arm GIC registers
+ * Memory mapped interface to access Arm GIC registers
This port is generic and can be used as a starting point for other Armv8-A
application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as
@@ -13,4 +13,4 @@
**NOTE**
-This port uses memory mapped interace to access Arm GIC registers.
+This port uses memory mapped interface to access Arm GIC registers.
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/README.md b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
index a5d415f..9951f81 100644
--- a/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
+++ b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
@@ -4,7 +4,7 @@
Arm Cortex-A53 processor.
* ARM_CA53_64_BIT_SRE
- * System Register interace to access Arm GIC registers
+ * System Register interface to access Arm GIC registers
This port is generic and can be used as a starting point for other Armv8-A
application processors. Therefore, the port `ARM_AARCH64_SRE` is renamed as
@@ -13,4 +13,4 @@
**NOTE**
-This port uses System Register interace to access Arm GIC registers.
+This port uses System Register interface to access Arm GIC registers.
diff --git a/portable/GCC/ARM_CA9/portASM.S b/portable/GCC/ARM_CA9/portASM.S
index 6efeaba..5e4b870 100644
--- a/portable/GCC/ARM_CA9/portASM.S
+++ b/portable/GCC/ARM_CA9/portASM.S
@@ -246,7 +246,7 @@
MOVS PC, LR
switch_before_exit:
- /* A context swtich is to be performed. Clear the context switch pending
+ /* A context switch is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]
diff --git a/portable/GCC/ARM_CR5/portASM.S b/portable/GCC/ARM_CR5/portASM.S
index e14cddd..1590ee4 100644
--- a/portable/GCC/ARM_CR5/portASM.S
+++ b/portable/GCC/ARM_CR5/portASM.S
@@ -242,7 +242,7 @@
MOVS PC, LR
switch_before_exit:
- /* A context swtich is to be performed. Clear the context switch pending
+ /* A context switch is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]
diff --git a/portable/GCC/ARM_CRx_MPU/portASM.S b/portable/GCC/ARM_CRx_MPU/portASM.S
index cac0fc4..bc0345a 100644
--- a/portable/GCC/ARM_CRx_MPU/portASM.S
+++ b/portable/GCC/ARM_CRx_MPU/portASM.S
@@ -446,7 +446,7 @@
* ulPortInterruptNesting. */
STR R1, [R0]
- /* Context swtich is only performed when interrupt nesting count is 0. */
+ /* Context switch is only performed when interrupt nesting count is 0. */
CMP R1, #0
BNE exit_without_switch
@@ -464,7 +464,7 @@
RFE SP!
switch_before_exit:
- /* A context swtich is to be performed. Clear ulPortYieldRequired. R1 holds
+ /* A context switch is to be performed. Clear ulPortYieldRequired. R1 holds
* the address of ulPortYieldRequired. */
MOV R0, #0
STR R0, [R1]
diff --git a/portable/GCC/ARM_CRx_No_GIC/portASM.S b/portable/GCC/ARM_CRx_No_GIC/portASM.S
index 960d46f..349a940 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portASM.S
+++ b/portable/GCC/ARM_CRx_No_GIC/portASM.S
@@ -223,7 +223,7 @@
MOVS PC, LR
switch_before_exit:
- /* A context swtich is to be performed. Clear the context switch pending
+ /* A context switch is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]
diff --git a/portable/IAR/ARM_CRx_No_GIC/portASM.s b/portable/IAR/ARM_CRx_No_GIC/portASM.s
index fb2a797..f37ad57 100644
--- a/portable/IAR/ARM_CRx_No_GIC/portASM.s
+++ b/portable/IAR/ARM_CRx_No_GIC/portASM.s
@@ -215,7 +215,7 @@
MOVS PC, LR
switch_before_exit:
- /* A context swtich is to be performed. Clear the context switch pending
+ /* A context switch is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]
diff --git a/portable/RVDS/ARM_CA9/portASM.s b/portable/RVDS/ARM_CA9/portASM.s
index f099ef2..771b140 100644
--- a/portable/RVDS/ARM_CA9/portASM.s
+++ b/portable/RVDS/ARM_CA9/portASM.s
@@ -143,7 +143,7 @@
MOVS PC, LR
switch_before_exit
- ; A context swtich is to be performed. Clear the context switch pending
+ ; A context switch is to be performed. Clear the context switch pending
; flag.
MOV r0, #0
STR r0, [r1]
diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
index 6e953a0..8f5ab7d 100644
--- a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
+++ b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
@@ -32,7 +32,7 @@
* will be set to 0 prior to the first task being started. */
portLONG ulCriticalNesting = 0x9999UL;
-/* Used to record one tack want to swtich task after enter critical area, we need know it
+/* Used to record one tack want to switch task after enter critical area, we need know it
* and implement task switch after exit critical area */
portLONG pendsvflag = 0;
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
index 256e715..8756213 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
@@ -254,7 +254,7 @@
The contents of a non-running thread's CPENABLE register.
It represents the co-processors owned (and whose state is still needed)
by the thread. When a thread is preempted, its CPENABLE is saved here.
- When a thread solicits a context-swtich, its CPENABLE is cleared - the
+ When a thread solicits a context-switch, its CPENABLE is cleared - the
compiler has saved the (caller-saved) co-proc state if it needs to.
When a non-running thread loses ownership of a CP, its bit is cleared.
When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
