/** | |
* \file | |
* | |
* \brief Chip-specific system clock manager configuration | |
* | |
* Copyright (c) 2012 Atmel Corporation. All rights reserved. | |
* | |
* \asf_license_start | |
* | |
* \page License | |
* | |
* Redistribution and use in source and binary forms, with or without | |
* modification, are permitted provided that the following conditions are met: | |
* | |
* 1. Redistributions of source code must retain the above copyright notice, | |
* this list of conditions and the following disclaimer. | |
* | |
* 2. Redistributions in binary form must reproduce the above copyright notice, | |
* this list of conditions and the following disclaimer in the documentation | |
* and/or other materials provided with the distribution. | |
* | |
* 3. The name of Atmel may not be used to endorse or promote products derived | |
* from this software without specific prior written permission. | |
* | |
* 4. This software may only be redistributed and used in connection with an | |
* Atmel microcontroller product. | |
* | |
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED | |
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE | |
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR | |
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN | |
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* \asf_license_stop | |
* | |
*/ | |
#ifndef CONF_CLOCK_H_INCLUDED | |
#define CONF_CLOCK_H_INCLUDED | |
//#define CONFIG_SYSCLK_INIT_CPUMASK 0 | |
//#define CONFIG_SYSCLK_INIT_PBAMASK ((1 << SYSCLK_USART2)) | |
//#define CONFIG_SYSCLK_INIT_PBBMASK ((1 << SYSCLK_HFLASHC_REGS)) | |
//#define CONFIG_SYSCLK_INIT_PBCMASK ((1 << SYSCLK_PM) | (1 << SYSCLK_SCIF) | (1 << SYSCLK_GPIO)) | |
//#define CONFIG_SYSCLK_INIT_PBDMASK ((1 << SYSCLK_BPM) | (1 << SYSCLK_BSCIF) | (1 << SYSCLK_AST)) | |
//#define CONFIG_SYSCLK_INIT_HSBMASK ((1 << SYSCLK_HFLASHC_DATA) | (SYSCLK_PBA_BRIDGE) | (SYSCLK_PBC_BRIDGE) | (SYSCLK_PBD_BRIDGE)) | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCSYS | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_OSC0 | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0 | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_DFLL | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC80M | |
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCFAST | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC1M | |
/* RCFAST frequency selection: 0 for 4MHz, 1 for 8MHz and 2 for 12MHz */ | |
//#define CONFIG_RCFAST_FRANGE 0 | |
//#define CONFIG_RCFAST_FRANGE 1 | |
#define CONFIG_RCFAST_FRANGE 2 | |
/* Fbus = Fsys / (2 ^ BUS_div) */ | |
#define CONFIG_SYSCLK_CPU_DIV 0 | |
#define CONFIG_SYSCLK_PBA_DIV 0 | |
#define CONFIG_SYSCLK_PBB_DIV 0 | |
#define CONFIG_SYSCLK_PBC_DIV 2 | |
#define CONFIG_SYSCLK_PBD_DIV 2 | |
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC0 | |
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 | |
/* Fusb = Fsys / USB_div */ | |
//#define CONFIG_USBCLK_DIV 1 | |
//#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0 | |
/* Fpll0 = (Fclk * PLL_mul) / PLL_div */ | |
//#define CONFIG_PLL0_MUL (48000000UL / BOARD_OSC0_HZ) | |
//#define CONFIG_PLL0_DIV 1 | |
//#define CONFIG_DFLL0_SOURCE GENCLK_SRC_OSC0 | |
//#define CONFIG_DFLL0_SOURCE GENCLK_SRC_RCSYS | |
//#define CONFIG_DFLL0_SOURCE GENCLK_SRC_OSC32K | |
//#define CONFIG_DFLL0_SOURCE GENCLK_SRC_RC80M | |
//#define CONFIG_DFLL0_SOURCE GENCLK_SRC_RC32K | |
/* Fdfll = (Fclk * DFLL_mul) / DFLL_div */ | |
//#define CONFIG_DFLL0_FREQ 96000000UL | |
//#define CONFIG_DFLL0_MUL (CONFIG_DFLL0_FREQ / BOARD_OSC0_HZ) | |
//#define CONFIG_DFLL0_DIV 2 | |
#endif /* CONF_CLOCK_H_INCLUDED */ | |