FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_g.c

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*
* CAUTION: This file is automatically generated by HSI.
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* 
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xttcps.h"

/*
* The configuration table for devices
*/

XTtcPs_Config XTtcPs_ConfigTable[] =
{
	{
		XPAR_PSU_TTC_0_DEVICE_ID,
		XPAR_PSU_TTC_0_BASEADDR,
		XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_1_DEVICE_ID,
		XPAR_PSU_TTC_1_BASEADDR,
		XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_2_DEVICE_ID,
		XPAR_PSU_TTC_2_BASEADDR,
		XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_3_DEVICE_ID,
		XPAR_PSU_TTC_3_BASEADDR,
		XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_4_DEVICE_ID,
		XPAR_PSU_TTC_4_BASEADDR,
		XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_5_DEVICE_ID,
		XPAR_PSU_TTC_5_BASEADDR,
		XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_6_DEVICE_ID,
		XPAR_PSU_TTC_6_BASEADDR,
		XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_7_DEVICE_ID,
		XPAR_PSU_TTC_7_BASEADDR,
		XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_8_DEVICE_ID,
		XPAR_PSU_TTC_8_BASEADDR,
		XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_9_DEVICE_ID,
		XPAR_PSU_TTC_9_BASEADDR,
		XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_10_DEVICE_ID,
		XPAR_PSU_TTC_10_BASEADDR,
		XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ
	},
	{
		XPAR_PSU_TTC_11_DEVICE_ID,
		XPAR_PSU_TTC_11_BASEADDR,
		XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ
	}
};