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pigweed / third_party / github / FreeRTOS / FreeRTOS-Kernel / 9c0c37ab9b56f2c90085b78df2f58b5833e473db / . / FreeRTOS / Demo / CORTEX_M4F_Infineon_XMC4000_IAR / system / XMC4400.h
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/****************************************************************************************************//**
* @file XMC4400.h
*
* @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
* XMC4400 from Infineon.
*
* @version V1.1.0 (Reference Manual v1.1)
* @date 13. December 2012
*
* @note Generated with SVDConv V2.78b
* from CMSIS SVD File 'XMC4400_Processed_SVD.xml' Version 1.1.0 (Reference Manual v1.1),
*******************************************************************************************************/
/** @addtogroup Infineon
* @{
*/
/** @addtogroup XMC4400
* @{
*/
#ifndef XMC4400_H
#define XMC4400_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum {
/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
/* --------------------- XMC4400 Specific Interrupt Numbers --------------------- */
SCU_0_IRQn = 0, /*!< 0 SCU_0 */
ERU0_0_IRQn = 1, /*!< 1 ERU0_0 */
ERU0_1_IRQn = 2, /*!< 2 ERU0_1 */
ERU0_2_IRQn = 3, /*!< 3 ERU0_2 */
ERU0_3_IRQn = 4, /*!< 4 ERU0_3 */
ERU1_0_IRQn = 5, /*!< 5 ERU1_0 */
ERU1_1_IRQn = 6, /*!< 6 ERU1_1 */
ERU1_2_IRQn = 7, /*!< 7 ERU1_2 */
ERU1_3_IRQn = 8, /*!< 8 ERU1_3 */
PMU0_0_IRQn = 12, /*!< 12 PMU0_0 */
VADC0_C0_0_IRQn = 14, /*!< 14 VADC0_C0_0 */
VADC0_C0_1_IRQn = 15, /*!< 15 VADC0_C0_1 */
VADC0_C0_2_IRQn = 16, /*!< 16 VADC0_C0_2 */
VADC0_C0_3_IRQn = 17, /*!< 17 VADC0_C0_3 */
VADC0_G0_0_IRQn = 18, /*!< 18 VADC0_G0_0 */
VADC0_G0_1_IRQn = 19, /*!< 19 VADC0_G0_1 */
VADC0_G0_2_IRQn = 20, /*!< 20 VADC0_G0_2 */
VADC0_G0_3_IRQn = 21, /*!< 21 VADC0_G0_3 */
VADC0_G1_0_IRQn = 22, /*!< 22 VADC0_G1_0 */
VADC0_G1_1_IRQn = 23, /*!< 23 VADC0_G1_1 */
VADC0_G1_2_IRQn = 24, /*!< 24 VADC0_G1_2 */
VADC0_G1_3_IRQn = 25, /*!< 25 VADC0_G1_3 */
VADC0_G2_0_IRQn = 26, /*!< 26 VADC0_G2_0 */
VADC0_G2_1_IRQn = 27, /*!< 27 VADC0_G2_1 */
VADC0_G2_2_IRQn = 28, /*!< 28 VADC0_G2_2 */
VADC0_G2_3_IRQn = 29, /*!< 29 VADC0_G2_3 */
VADC0_G3_0_IRQn = 30, /*!< 30 VADC0_G3_0 */
VADC0_G3_1_IRQn = 31, /*!< 31 VADC0_G3_1 */
VADC0_G3_2_IRQn = 32, /*!< 32 VADC0_G3_2 */
VADC0_G3_3_IRQn = 33, /*!< 33 VADC0_G3_3 */
DSD0_M_0_IRQn = 34, /*!< 34 DSD0_M_0 */
DSD0_M_1_IRQn = 35, /*!< 35 DSD0_M_1 */
DSD0_M_2_IRQn = 36, /*!< 36 DSD0_M_2 */
DSD0_M_3_IRQn = 37, /*!< 37 DSD0_M_3 */
DSD0_A_4_IRQn = 38, /*!< 38 DSD0_A_4 */
DSD0_A_5_IRQn = 39, /*!< 39 DSD0_A_5 */
DSD0_A_6_IRQn = 40, /*!< 40 DSD0_A_6 */
DSD0_A_7_IRQn = 41, /*!< 41 DSD0_A_7 */
DAC0_0_IRQn = 42, /*!< 42 DAC0_0 */
DAC0_1_IRQn = 43, /*!< 43 DAC0_1 */
CCU40_0_IRQn = 44, /*!< 44 CCU40_0 */
CCU40_1_IRQn = 45, /*!< 45 CCU40_1 */
CCU40_2_IRQn = 46, /*!< 46 CCU40_2 */
CCU40_3_IRQn = 47, /*!< 47 CCU40_3 */
CCU41_0_IRQn = 48, /*!< 48 CCU41_0 */
CCU41_1_IRQn = 49, /*!< 49 CCU41_1 */
CCU41_2_IRQn = 50, /*!< 50 CCU41_2 */
CCU41_3_IRQn = 51, /*!< 51 CCU41_3 */
CCU42_0_IRQn = 52, /*!< 52 CCU42_0 */
CCU42_1_IRQn = 53, /*!< 53 CCU42_1 */
CCU42_2_IRQn = 54, /*!< 54 CCU42_2 */
CCU42_3_IRQn = 55, /*!< 55 CCU42_3 */
CCU43_0_IRQn = 56, /*!< 56 CCU43_0 */
CCU43_1_IRQn = 57, /*!< 57 CCU43_1 */
CCU43_2_IRQn = 58, /*!< 58 CCU43_2 */
CCU43_3_IRQn = 59, /*!< 59 CCU43_3 */
CCU80_0_IRQn = 60, /*!< 60 CCU80_0 */
CCU80_1_IRQn = 61, /*!< 61 CCU80_1 */
CCU80_2_IRQn = 62, /*!< 62 CCU80_2 */
CCU80_3_IRQn = 63, /*!< 63 CCU80_3 */
CCU81_0_IRQn = 64, /*!< 64 CCU81_0 */
CCU81_1_IRQn = 65, /*!< 65 CCU81_1 */
CCU81_2_IRQn = 66, /*!< 66 CCU81_2 */
CCU81_3_IRQn = 67, /*!< 67 CCU81_3 */
POSIF0_0_IRQn = 68, /*!< 68 POSIF0_0 */
POSIF0_1_IRQn = 69, /*!< 69 POSIF0_1 */
POSIF1_0_IRQn = 70, /*!< 70 POSIF1_0 */
POSIF1_1_IRQn = 71, /*!< 71 POSIF1_1 */
HRPWM_0_IRQn = 72, /*!< 72 HRPWM_0 */
HRPWM_1_IRQn = 73, /*!< 73 HRPWM_1 */
HRPWM_2_IRQn = 74, /*!< 72 HRPWM_2 */
HRPWM_3_IRQn = 75, /*!< 73 HRPWM_3 */
CAN0_0_IRQn = 76, /*!< 76 CAN0_0 */
CAN0_1_IRQn = 77, /*!< 77 CAN0_1 */
CAN0_2_IRQn = 78, /*!< 78 CAN0_2 */
CAN0_3_IRQn = 79, /*!< 79 CAN0_3 */
CAN0_4_IRQn = 80, /*!< 80 CAN0_4 */
CAN0_5_IRQn = 81, /*!< 81 CAN0_5 */
CAN0_6_IRQn = 82, /*!< 82 CAN0_6 */
CAN0_7_IRQn = 83, /*!< 83 CAN0_7 */
USIC0_0_IRQn = 84, /*!< 84 USIC0_0 */
USIC0_1_IRQn = 85, /*!< 85 USIC0_1 */
USIC0_2_IRQn = 86, /*!< 86 USIC0_2 */
USIC0_3_IRQn = 87, /*!< 87 USIC0_3 */
USIC0_4_IRQn = 88, /*!< 88 USIC0_4 */
USIC0_5_IRQn = 89, /*!< 89 USIC0_5 */
USIC1_0_IRQn = 90, /*!< 90 USIC1_0 */
USIC1_1_IRQn = 91, /*!< 91 USIC1_1 */
USIC1_2_IRQn = 92, /*!< 92 USIC1_2 */
USIC1_3_IRQn = 93, /*!< 93 USIC1_3 */
USIC1_4_IRQn = 94, /*!< 94 USIC1_4 */
USIC1_5_IRQn = 95, /*!< 95 USIC1_5 */
LEDTS0_0_IRQn = 102, /*!< 102 LEDTS0_0 */
FCE0_0_IRQn = 104, /*!< 104 FCE0_0 */
GPDMA0_0_IRQn = 105, /*!< 105 GPDMA0_0 */
USB0_0_IRQn = 107, /*!< 107 USB0_0 */
ETH0_0_IRQn = 108, /*!< 108 ETH0_0 */
} IRQn_Type;
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
#define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present or not */
/** @} */ /* End of group Configuration_of_CMSIS */
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
#include "system_XMC4400.h" /*!< XMC4400 System */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/* Macro to modify desired bitfields of a register */
#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \
((uint32_t)mask)) | \
(reg & ((uint32_t)~((uint32_t)mask)))
/* Macro to modify desired bitfields of a register */
#define WR_REG_SIZE(reg, mask, pos, val, size) { \
uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \
uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \
uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \
uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \
reg = (uint##size##_t) (VAL2 | VAL4);\
}
/** Macro to read bitfields from a register */
#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)
/** Macro to read bitfields from a register */
#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \
(uint32_t)mask) >> pos) )
/** Macro to set a bit in register */
#define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos))
/** Macro to clear a bit in register */
#define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )
/*
* ==========================================================================
* ---------- Interrupt Handler Definition ----------------------------------
* ==========================================================================
*/
#define IRQ_Hdlr_0 SCU_0_IRQHandler
#define IRQ_Hdlr_1 ERU0_0_IRQHandler
#define IRQ_Hdlr_2 ERU0_1_IRQHandler
#define IRQ_Hdlr_3 ERU0_2_IRQHandler
#define IRQ_Hdlr_4 ERU0_3_IRQHandler
#define IRQ_Hdlr_5 ERU1_0_IRQHandler
#define IRQ_Hdlr_6 ERU1_1_IRQHandler
#define IRQ_Hdlr_7 ERU1_2_IRQHandler
#define IRQ_Hdlr_8 ERU1_3_IRQHandler
#define IRQ_Hdlr_12 PMU0_0_IRQHandler
#define IRQ_Hdlr_14 VADC0_C0_0_IRQHandler
#define IRQ_Hdlr_15 VADC0_C0_1_IRQHandler
#define IRQ_Hdlr_16 VADC0_C0_2_IRQHandler
#define IRQ_Hdlr_17 VADC0_C0_3_IRQHandler
#define IRQ_Hdlr_18 VADC0_G0_0_IRQHandler
#define IRQ_Hdlr_19 VADC0_G0_1_IRQHandler
#define IRQ_Hdlr_20 VADC0_G0_2_IRQHandler
#define IRQ_Hdlr_21 VADC0_G0_3_IRQHandler
#define IRQ_Hdlr_22 VADC0_G1_0_IRQHandler
#define IRQ_Hdlr_23 VADC0_G1_1_IRQHandler
#define IRQ_Hdlr_24 VADC0_G1_2_IRQHandler
#define IRQ_Hdlr_25 VADC0_G1_3_IRQHandler
#define IRQ_Hdlr_26 VADC0_G2_0_IRQHandler
#define IRQ_Hdlr_27 VADC0_G2_1_IRQHandler
#define IRQ_Hdlr_28 VADC0_G2_2_IRQHandler
#define IRQ_Hdlr_29 VADC0_G2_3_IRQHandler
#define IRQ_Hdlr_30 VADC0_G3_0_IRQHandler
#define IRQ_Hdlr_31 VADC0_G3_1_IRQHandler
#define IRQ_Hdlr_32 VADC0_G3_2_IRQHandler
#define IRQ_Hdlr_33 VADC0_G3_3_IRQHandler
#define IRQ_Hdlr_34 DSD0_0_IRQHandler
#define IRQ_Hdlr_35 DSD0_1_IRQHandler
#define IRQ_Hdlr_36 DSD0_2_IRQHandler
#define IRQ_Hdlr_37 DSD0_3_IRQHandler
#define IRQ_Hdlr_38 DSD0_4_IRQHandler
#define IRQ_Hdlr_39 DSD0_5_IRQHandler
#define IRQ_Hdlr_40 DSD0_6_IRQHandler
#define IRQ_Hdlr_41 DSD0_7_IRQHandler
#define IRQ_Hdlr_42 DAC0_0_IRQHandler
#define IRQ_Hdlr_43 DAC0_1_IRQHandler
#define IRQ_Hdlr_44 CCU40_0_IRQHandler
#define IRQ_Hdlr_45 CCU40_1_IRQHandler
#define IRQ_Hdlr_46 CCU40_2_IRQHandler
#define IRQ_Hdlr_47 CCU40_3_IRQHandler
#define IRQ_Hdlr_48 CCU41_0_IRQHandler
#define IRQ_Hdlr_49 CCU41_1_IRQHandler
#define IRQ_Hdlr_50 CCU41_2_IRQHandler
#define IRQ_Hdlr_51 CCU41_3_IRQHandler
#define IRQ_Hdlr_52 CCU42_0_IRQHandler
#define IRQ_Hdlr_53 CCU42_1_IRQHandler
#define IRQ_Hdlr_54 CCU42_2_IRQHandler
#define IRQ_Hdlr_55 CCU42_3_IRQHandler
#define IRQ_Hdlr_56 CCU43_0_IRQHandler
#define IRQ_Hdlr_57 CCU43_1_IRQHandler
#define IRQ_Hdlr_58 CCU43_2_IRQHandler
#define IRQ_Hdlr_59 CCU43_3_IRQHandler
#define IRQ_Hdlr_60 CCU80_0_IRQHandler
#define IRQ_Hdlr_61 CCU80_1_IRQHandler
#define IRQ_Hdlr_62 CCU80_2_IRQHandler
#define IRQ_Hdlr_63 CCU80_3_IRQHandler
#define IRQ_Hdlr_64 CCU81_0_IRQHandler
#define IRQ_Hdlr_65 CCU81_1_IRQHandler
#define IRQ_Hdlr_66 CCU81_2_IRQHandler
#define IRQ_Hdlr_67 CCU81_3_IRQHandler
#define IRQ_Hdlr_68 POSIF0_0_IRQHandler
#define IRQ_Hdlr_69 POSIF0_1_IRQHandler
#define IRQ_Hdlr_70 POSIF1_0_IRQHandler
#define IRQ_Hdlr_71 POSIF1_1_IRQHandler
#define IRQ_Hdlr_72 HRPWM_0_IRQHandler
#define IRQ_Hdlr_73 HRPWM_1_IRQHandler
#define IRQ_Hdlr_74 HRPWM_2_IRQHandler
#define IRQ_Hdlr_75 HRPWM_3_IRQHandler
#define IRQ_Hdlr_76 CAN0_0_IRQHandler
#define IRQ_Hdlr_77 CAN0_1_IRQHandler
#define IRQ_Hdlr_78 CAN0_2_IRQHandler
#define IRQ_Hdlr_79 CAN0_3_IRQHandler
#define IRQ_Hdlr_80 CAN0_4_IRQHandler
#define IRQ_Hdlr_81 CAN0_5_IRQHandler
#define IRQ_Hdlr_82 CAN0_6_IRQHandler
#define IRQ_Hdlr_83 CAN0_7_IRQHandler
#define IRQ_Hdlr_84 USIC0_0_IRQHandler
#define IRQ_Hdlr_85 USIC0_1_IRQHandler
#define IRQ_Hdlr_86 USIC0_2_IRQHandler
#define IRQ_Hdlr_87 USIC0_3_IRQHandler
#define IRQ_Hdlr_88 USIC0_4_IRQHandler
#define IRQ_Hdlr_89 USIC0_5_IRQHandler
#define IRQ_Hdlr_90 USIC1_0_IRQHandler
#define IRQ_Hdlr_91 USIC1_1_IRQHandler
#define IRQ_Hdlr_92 USIC1_2_IRQHandler
#define IRQ_Hdlr_93 USIC1_3_IRQHandler
#define IRQ_Hdlr_94 USIC1_4_IRQHandler
#define IRQ_Hdlr_95 USIC1_5_IRQHandler
#define IRQ_Hdlr_101 USIC2_5_IRQHandler
#define IRQ_Hdlr_102 LEDTS0_0_IRQHandler
#define IRQ_Hdlr_104 FCE0_0_IRQHandler
#define IRQ_Hdlr_105 GPDMA0_0_IRQHandler
#define IRQ_Hdlr_107 USB0_0_IRQHandler
#define IRQ_Hdlr_108 ETH0_0_IRQHandler
/*
* ==========================================================================
* ---------- Interrupt Handler retrieval macro -----------------------------
* ==========================================================================
*/
#define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N
/** @addtogroup Device_Peripheral_Registers
* @{
*/
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ PPB ================ */
/* ================================================================================ */
/**
* @brief Cortex-M4 Private Peripheral Block (PPB)
*/
typedef struct { /*!< (@ 0xE000E000) PPB Structure */
__I uint32_t RESERVED0[2];
__IO uint32_t ACTLR; /*!< (@ 0xE000E008) Auxiliary Control Register */
__I uint32_t RESERVED1;
__IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */
__IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */
__IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */
__IO uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register r */
__I uint32_t RESERVED2[56];
__IO uint32_t NVIC_ISER0; /*!< (@ 0xE000E100) Interrupt Set-enable Register 0 */
__IO uint32_t NVIC_ISER1; /*!< (@ 0xE000E104) Interrupt Set-enable Register 1 */
__IO uint32_t NVIC_ISER2; /*!< (@ 0xE000E108) Interrupt Set-enable Register 2 */
__IO uint32_t NVIC_ISER3; /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3 */
__I uint32_t RESERVED3[28];
__IO uint32_t NVIC_ICER0; /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0 */
__IO uint32_t NVIC_ICER1; /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1 */
__IO uint32_t NVIC_ICER2; /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2 */
__IO uint32_t NVIC_ICER3; /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3 */
__I uint32_t RESERVED4[28];
__IO uint32_t NVIC_ISPR0; /*!< (@ 0xE000E200) Interrupt Set-pending Register 0 */
__IO uint32_t NVIC_ISPR1; /*!< (@ 0xE000E204) Interrupt Set-pending Register 1 */
__IO uint32_t NVIC_ISPR2; /*!< (@ 0xE000E208) Interrupt Set-pending Register 2 */
__IO uint32_t NVIC_ISPR3; /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3 */
__I uint32_t RESERVED5[28];
__IO uint32_t NVIC_ICPR0; /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0 */
__IO uint32_t NVIC_ICPR1; /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1 */
__IO uint32_t NVIC_ICPR2; /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2 */
__IO uint32_t NVIC_ICPR3; /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3 */
__I uint32_t RESERVED6[28];
__IO uint32_t NVIC_IABR0; /*!< (@ 0xE000E300) Interrupt Active Bit Register 0 */
__IO uint32_t NVIC_IABR1; /*!< (@ 0xE000E304) Interrupt Active Bit Register 1 */
__IO uint32_t NVIC_IABR2; /*!< (@ 0xE000E308) Interrupt Active Bit Register 2 */
__IO uint32_t NVIC_IABR3; /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3 */
__I uint32_t RESERVED7[60];
__IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */
__IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */
__IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */
__IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */
__IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */
__IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */
__IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */
__IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */
__IO uint32_t NVIC_IPR8; /*!< (@ 0xE000E420) Interrupt Priority Register 8 */
__IO uint32_t NVIC_IPR9; /*!< (@ 0xE000E424) Interrupt Priority Register 9 */
__IO uint32_t NVIC_IPR10; /*!< (@ 0xE000E428) Interrupt Priority Register 10 */
__IO uint32_t NVIC_IPR11; /*!< (@ 0xE000E42C) Interrupt Priority Register 11 */
__IO uint32_t NVIC_IPR12; /*!< (@ 0xE000E430) Interrupt Priority Register 12 */
__IO uint32_t NVIC_IPR13; /*!< (@ 0xE000E434) Interrupt Priority Register 13 */
__IO uint32_t NVIC_IPR14; /*!< (@ 0xE000E438) Interrupt Priority Register 14 */
__IO uint32_t NVIC_IPR15; /*!< (@ 0xE000E43C) Interrupt Priority Register 15 */
__IO uint32_t NVIC_IPR16; /*!< (@ 0xE000E440) Interrupt Priority Register 16 */
__IO uint32_t NVIC_IPR17; /*!< (@ 0xE000E444) Interrupt Priority Register 17 */
__IO uint32_t NVIC_IPR18; /*!< (@ 0xE000E448) Interrupt Priority Register 18 */
__IO uint32_t NVIC_IPR19; /*!< (@ 0xE000E44C) Interrupt Priority Register 19 */
__IO uint32_t NVIC_IPR20; /*!< (@ 0xE000E450) Interrupt Priority Register 20 */
__IO uint32_t NVIC_IPR21; /*!< (@ 0xE000E454) Interrupt Priority Register 21 */
__IO uint32_t NVIC_IPR22; /*!< (@ 0xE000E458) Interrupt Priority Register 22 */
__IO uint32_t NVIC_IPR23; /*!< (@ 0xE000E45C) Interrupt Priority Register 23 */
__IO uint32_t NVIC_IPR24; /*!< (@ 0xE000E460) Interrupt Priority Register 24 */
__IO uint32_t NVIC_IPR25; /*!< (@ 0xE000E464) Interrupt Priority Register 25 */
__IO uint32_t NVIC_IPR26; /*!< (@ 0xE000E468) Interrupt Priority Register 26 */
__IO uint32_t NVIC_IPR27; /*!< (@ 0xE000E46C) Interrupt Priority Register 27 */
__I uint32_t RESERVED8[548];
__I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */
__IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */
__IO uint32_t VTOR; /*!< (@ 0xE000ED08) Vector Table Offset Register */
__IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */
__IO uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */
__IO uint32_t SHPR1; /*!< (@ 0xE000ED18) System Handler Priority Register 1 */
__IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */
__IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */
__IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */
__IO uint32_t CFSR; /*!< (@ 0xE000ED28) Configurable Fault Status Register */
__IO uint32_t HFSR; /*!< (@ 0xE000ED2C) HardFault Status Register */
__I uint32_t RESERVED9;
__IO uint32_t MMFAR; /*!< (@ 0xE000ED34) MemManage Fault Address Register */
__IO uint32_t BFAR; /*!< (@ 0xE000ED38) BusFault Address Register */
__IO uint32_t AFSR; /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register */
__I uint32_t RESERVED10[18];
__IO uint32_t CPACR; /*!< (@ 0xE000ED88) Coprocessor Access Control Register */
__I uint32_t RESERVED11;
__I uint32_t MPU_TYPE; /*!< (@ 0xE000ED90) MPU Type Register */
__IO uint32_t MPU_CTRL; /*!< (@ 0xE000ED94) MPU Control Register */
__IO uint32_t MPU_RNR; /*!< (@ 0xE000ED98) MPU Region Number Register */
__IO uint32_t MPU_RBAR; /*!< (@ 0xE000ED9C) MPU Region Base Address Register */
__IO uint32_t MPU_RASR; /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register */
__IO uint32_t MPU_RBAR_A1; /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1 */
__IO uint32_t MPU_RASR_A1; /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1 */
__IO uint32_t MPU_RBAR_A2; /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2 */
__IO uint32_t MPU_RASR_A2; /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2 */
__IO uint32_t MPU_RBAR_A3; /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3 */
__IO uint32_t MPU_RASR_A3; /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3 */
__I uint32_t RESERVED12[81];
__O uint32_t STIR; /*!< (@ 0xE000EF00) Software Trigger Interrupt Register */
__I uint32_t RESERVED13[12];
__IO uint32_t FPCCR; /*!< (@ 0xE000EF34) Floating-point Context Control Register */
__IO uint32_t FPCAR; /*!< (@ 0xE000EF38) Floating-point Context Address Register */
__IO uint32_t FPDSCR; /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register */
} PPB_Type;
/* ================================================================================ */
/* ================ DLR ================ */
/* ================================================================================ */
/**
* @brief DMA Line Router (DLR)
*/
typedef struct { /*!< (@ 0x50004900) DLR Structure */
__I uint32_t OVRSTAT; /*!< (@ 0x50004900) Overrun Status */
__O uint32_t OVRCLR; /*!< (@ 0x50004904) Overrun Clear */
__IO uint32_t SRSEL0; /*!< (@ 0x50004908) Service Request Selection 0 */
__I uint32_t RESERVED0;
__IO uint32_t LNEN; /*!< (@ 0x50004910) Line Enable */
} DLR_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ ERU [ERU0] ================ */
/* ================================================================================ */
/**
* @brief Event Request Unit 0 (ERU)
*/
typedef struct { /*!< (@ 0x50004800) ERU Structure */
__IO uint32_t EXISEL; /*!< (@ 0x50004800) Event Input Select */
__I uint32_t RESERVED0[3];
__IO uint32_t EXICON[4]; /*!< (@ 0x50004810) Event Input Control */
__IO uint32_t EXOCON[4]; /*!< (@ 0x50004820) Event Output Trigger Control */
} ERU_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ GPDMA0 ================ */
/* ================================================================================ */
/**
* @brief General Purpose DMA Unit 0 (GPDMA0)
*/
typedef struct { /*!< (@ 0x500142C0) GPDMA0 Structure */
__IO uint32_t RAWTFR; /*!< (@ 0x500142C0) Raw IntTfr Status */
__I uint32_t RESERVED0;
__IO uint32_t RAWBLOCK; /*!< (@ 0x500142C8) Raw IntBlock Status */
__I uint32_t RESERVED1;
__IO uint32_t RAWSRCTRAN; /*!< (@ 0x500142D0) Raw IntSrcTran Status */
__I uint32_t RESERVED2;
__IO uint32_t RAWDSTTRAN; /*!< (@ 0x500142D8) Raw IntBlock Status */
__I uint32_t RESERVED3;
__IO uint32_t RAWERR; /*!< (@ 0x500142E0) Raw IntErr Status */
__I uint32_t RESERVED4;
__I uint32_t STATUSTFR; /*!< (@ 0x500142E8) IntTfr Status */
__I uint32_t RESERVED5;
__I uint32_t STATUSBLOCK; /*!< (@ 0x500142F0) IntBlock Status */
__I uint32_t RESERVED6;
__I uint32_t STATUSSRCTRAN; /*!< (@ 0x500142F8) IntSrcTran Status */
__I uint32_t RESERVED7;
__I uint32_t STATUSDSTTRAN; /*!< (@ 0x50014300) IntBlock Status */
__I uint32_t RESERVED8;
__I uint32_t STATUSERR; /*!< (@ 0x50014308) IntErr Status */
__I uint32_t RESERVED9;
__IO uint32_t MASKTFR; /*!< (@ 0x50014310) Mask for Raw IntTfr Status */
__I uint32_t RESERVED10;
__IO uint32_t MASKBLOCK; /*!< (@ 0x50014318) Mask for Raw IntBlock Status */
__I uint32_t RESERVED11;
__IO uint32_t MASKSRCTRAN; /*!< (@ 0x50014320) Mask for Raw IntSrcTran Status */
__I uint32_t RESERVED12;
__IO uint32_t MASKDSTTRAN; /*!< (@ 0x50014328) Mask for Raw IntBlock Status */
__I uint32_t RESERVED13;
__IO uint32_t MASKERR; /*!< (@ 0x50014330) Mask for Raw IntErr Status */
__I uint32_t RESERVED14;
__O uint32_t CLEARTFR; /*!< (@ 0x50014338) IntTfr Status */
__I uint32_t RESERVED15;
__O uint32_t CLEARBLOCK; /*!< (@ 0x50014340) IntBlock Status */
__I uint32_t RESERVED16;
__O uint32_t CLEARSRCTRAN; /*!< (@ 0x50014348) IntSrcTran Status */
__I uint32_t RESERVED17;
__O uint32_t CLEARDSTTRAN; /*!< (@ 0x50014350) IntBlock Status */
__I uint32_t RESERVED18;
__O uint32_t CLEARERR; /*!< (@ 0x50014358) IntErr Status */
__I uint32_t RESERVED19;
__I uint32_t STATUSINT; /*!< (@ 0x50014360) Combined Interrupt Status Register */
__I uint32_t RESERVED20;
__IO uint32_t REQSRCREG; /*!< (@ 0x50014368) Source Software Transaction Request Register */
__I uint32_t RESERVED21;
__IO uint32_t REQDSTREG; /*!< (@ 0x50014370) Destination Software Transaction Request Register */
__I uint32_t RESERVED22;
__IO uint32_t SGLREQSRCREG; /*!< (@ 0x50014378) Single Source Transaction Request Register */
__I uint32_t RESERVED23;
__IO uint32_t SGLREQDSTREG; /*!< (@ 0x50014380) Single Destination Transaction Request Register */
__I uint32_t RESERVED24;
__IO uint32_t LSTSRCREG; /*!< (@ 0x50014388) Last Source Transaction Request Register */
__I uint32_t RESERVED25;
__IO uint32_t LSTDSTREG; /*!< (@ 0x50014390) Last Destination Transaction Request Register */
__I uint32_t RESERVED26;
__IO uint32_t DMACFGREG; /*!< (@ 0x50014398) GPDMA Configuration Register */
__I uint32_t RESERVED27;
__IO uint32_t CHENREG; /*!< (@ 0x500143A0) GPDMA Channel Enable Register */
__I uint32_t RESERVED28;
__I uint32_t ID; /*!< (@ 0x500143A8) GPDMA0 ID Register */
__I uint32_t RESERVED29[19];
__I uint32_t TYPE; /*!< (@ 0x500143F8) GPDMA Component Type */
__I uint32_t VERSION; /*!< (@ 0x500143FC) DMA Component Version */
} GPDMA0_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ GPDMA0_CH0_1 [GPDMA0_CH0] ================ */
/* ================================================================================ */
/**
* @brief General Purpose DMA Unit 0 (GPDMA0_CH0_1)
*/
typedef struct { /*!< (@ 0x50014000) GPDMA0_CH0_1 Structure */
__IO uint32_t SAR; /*!< (@ 0x50014000) Source Address Register */
__I uint32_t RESERVED0;
__IO uint32_t DAR; /*!< (@ 0x50014008) Destination Address Register */
__I uint32_t RESERVED1;
__IO uint32_t LLP; /*!< (@ 0x50014010) Linked List Pointer Register */
__I uint32_t RESERVED2;
__IO uint32_t CTLL; /*!< (@ 0x50014018) Control Register Low */
__IO uint32_t CTLH; /*!< (@ 0x5001401C) Control Register High */
__IO uint32_t SSTAT; /*!< (@ 0x50014020) Source Status Register */
__I uint32_t RESERVED3;
__IO uint32_t DSTAT; /*!< (@ 0x50014028) Destination Status Register */
__I uint32_t RESERVED4;
__IO uint32_t SSTATAR; /*!< (@ 0x50014030) Source Status Address Register */
__I uint32_t RESERVED5;
__IO uint32_t DSTATAR; /*!< (@ 0x50014038) Destination Status Address Register */
__I uint32_t RESERVED6;
__IO uint32_t CFGL; /*!< (@ 0x50014040) Configuration Register Low */
__IO uint32_t CFGH; /*!< (@ 0x50014044) Configuration Register High */
__IO uint32_t SGR; /*!< (@ 0x50014048) Source Gather Register */
__I uint32_t RESERVED7;
__IO uint32_t DSR; /*!< (@ 0x50014050) Destination Scatter Register */
} GPDMA0_CH_TypeDef;
/* ================================================================================ */
/* ================ GPDMA0_CH2_7 [GPDMA0_CH2] ================ */
/* ================================================================================ */
/**
* @brief General Purpose DMA Unit 0 (GPDMA0_CH2_7)
*/
typedef struct { /*!< (@ 0x500140B0) GPDMA0_CH2_7 Structure */
__IO uint32_t SAR; /*!< (@ 0x500140B0) Source Address Register */
__I uint32_t RESERVED0;
__IO uint32_t DAR; /*!< (@ 0x500140B8) Destination Address Register */
__I uint32_t RESERVED1[3];
__IO uint32_t CTLL; /*!< (@ 0x500140C8) Control Register Low */
__IO uint32_t CTLH; /*!< (@ 0x500140CC) Control Register High */
__I uint32_t RESERVED2[8];
__IO uint32_t CFGL; /*!< (@ 0x500140F0) Configuration Register Low */
__IO uint32_t CFGH; /*!< (@ 0x500140F4) Configuration Register High */
} GPDMA0_CH2_7_Type;
/* ================================================================================ */
/* ================ FCE ================ */
/* ================================================================================ */
/**
* @brief Flexible CRC Engine (FCE)
*/
typedef struct { /*!< (@ 0x50020000) FCE Structure */
__IO uint32_t CLC; /*!< (@ 0x50020000) Clock Control Register */
__I uint32_t RESERVED0;
__I uint32_t ID; /*!< (@ 0x50020008) Module Identification Register */
} FCE_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ FCE_KE [FCE_KE0] ================ */
/* ================================================================================ */
/**
* @brief Flexible CRC Engine (FCE_KE)
*/
typedef struct { /*!< (@ 0x50020020) FCE_KE Structure */
__IO uint32_t IR; /*!< (@ 0x50020020) Input Register */
__I uint32_t RES; /*!< (@ 0x50020024) CRC Result Register */
__IO uint32_t CFG; /*!< (@ 0x50020028) CRC Configuration Register */
__IO uint32_t STS; /*!< (@ 0x5002002C) CRC Status Register */
__IO uint32_t LENGTH; /*!< (@ 0x50020030) CRC Length Register */
__IO uint32_t CHECK; /*!< (@ 0x50020034) CRC Check Register */
__IO uint32_t CRC; /*!< (@ 0x50020038) CRC Register */
__IO uint32_t CTR; /*!< (@ 0x5002003C) CRC Test Register */
} FCE_KE_TypeDef;
/* ================================================================================ */
/* ================ PBA [PBA0] ================ */
/* ================================================================================ */
/**
* @brief Peripheral Bridge AHB 0 (PBA)
*/
typedef struct { /*!< (@ 0x40000000) PBA Structure */
__IO uint32_t STS; /*!< (@ 0x40000000) Peripheral Bridge Status Register */
__I uint32_t WADDR; /*!< (@ 0x40000004) PBA Write Error Address Register */
} PBA_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ FLASH [FLASH0] ================ */
/* ================================================================================ */
/**
* @brief Flash Memory Controller (FLASH)
*/
typedef struct { /*!< (@ 0x58001000) FLASH Structure */
__I uint32_t RESERVED0[1026];
__I uint32_t ID; /*!< (@ 0x58002008) Flash Module Identification Register */
__I uint32_t RESERVED1;
__I uint32_t FSR; /*!< (@ 0x58002010) Flash Status Register */
__IO uint32_t FCON; /*!< (@ 0x58002014) Flash Configuration Register */
__IO uint32_t MARP; /*!< (@ 0x58002018) Margin Control Register PFLASH */
__I uint32_t RESERVED2;
__I uint32_t PROCON0; /*!< (@ 0x58002020) Flash Protection Configuration Register User
0 */
__I uint32_t PROCON1; /*!< (@ 0x58002024) Flash Protection Configuration Register User
1 */
__I uint32_t PROCON2; /*!< (@ 0x58002028) Flash Protection Configuration Register User
2 */
} FLASH0_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ PREF ================ */
/* ================================================================================ */
/**
* @brief Prefetch Unit (PREF)
*/
typedef struct { /*!< (@ 0x58004000) PREF Structure */
__IO uint32_t PCON; /*!< (@ 0x58004000) Prefetch Configuration Register */
} PREF_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ PMU [PMU0] ================ */
/* ================================================================================ */
/**
* @brief Program Management Unit (PMU)
*/
typedef struct { /*!< (@ 0x58000508) PMU Structure */
__I uint32_t ID; /*!< (@ 0x58000508) PMU0 Identification Register */
} PMU0_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ WDT ================ */
/* ================================================================================ */
/**
* @brief Watch Dog Timer (WDT)
*/
typedef struct { /*!< (@ 0x50008000) WDT Structure */
__I uint32_t ID; /*!< (@ 0x50008000) WDT ID Register */
__IO uint32_t CTR; /*!< (@ 0x50008004) WDT Control Register */
__O uint32_t SRV; /*!< (@ 0x50008008) WDT Service Register */
__I uint32_t TIM; /*!< (@ 0x5000800C) WDT Timer Register */
__IO uint32_t WLB; /*!< (@ 0x50008010) WDT Window Lower Bound Register */
__IO uint32_t WUB; /*!< (@ 0x50008014) WDT Window Upper Bound Register */
__I uint32_t WDTSTS; /*!< (@ 0x50008018) WDT Status Register */
__O uint32_t WDTCLR; /*!< (@ 0x5000801C) WDT Clear Register */
} WDT_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ RTC ================ */
/* ================================================================================ */
/**
* @brief Real Time Clock (RTC)
*/
typedef struct { /*!< (@ 0x50004A00) RTC Structure */
__I uint32_t ID; /*!< (@ 0x50004A00) RTC ID Register */
__IO uint32_t CTR; /*!< (@ 0x50004A04) RTC Control Register */
__I uint32_t RAWSTAT; /*!< (@ 0x50004A08) RTC Raw Service Request Register */
__I uint32_t STSSR; /*!< (@ 0x50004A0C) RTC Service Request Status Register */
__IO uint32_t MSKSR; /*!< (@ 0x50004A10) RTC Service Request Mask Register */
__O uint32_t CLRSR; /*!< (@ 0x50004A14) RTC Clear Service Request Register */
__IO uint32_t ATIM0; /*!< (@ 0x50004A18) RTC Alarm Time Register 0 */
__IO uint32_t ATIM1; /*!< (@ 0x50004A1C) RTC Alarm Time Register 1 */
__IO uint32_t TIM0; /*!< (@ 0x50004A20) RTC Time Register 0 */
__IO uint32_t TIM1; /*!< (@ 0x50004A24) RTC Time Register 1 */
} RTC_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ SCU_CLK ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_CLK)
*/
typedef struct { /*!< (@ 0x50004600) SCU_CLK Structure */
__I uint32_t CLKSTAT; /*!< (@ 0x50004600) Clock Status Register */
__O uint32_t CLKSET; /*!< (@ 0x50004604) CLK Set Register */
__O uint32_t CLKCLR; /*!< (@ 0x50004608) CLK Clear Register */
__IO uint32_t SYSCLKCR; /*!< (@ 0x5000460C) System Clock Control Register */
__IO uint32_t CPUCLKCR; /*!< (@ 0x50004610) CPU Clock Control Register */
__IO uint32_t PBCLKCR; /*!< (@ 0x50004614) Peripheral Bus Clock Control Register */
__IO uint32_t USBCLKCR; /*!< (@ 0x50004618) USB Clock Control Register */
__I uint32_t RESERVED0;
__IO uint32_t CCUCLKCR; /*!< (@ 0x50004620) CCU Clock Control Register */
__IO uint32_t WDTCLKCR; /*!< (@ 0x50004624) WDT Clock Control Register */
__IO uint32_t EXTCLKCR; /*!< (@ 0x50004628) External Clock Control */
__IO uint32_t MLINKCLKCR; /*!< (@ 0x5000462C) Multi-Link Clock Control */
__IO uint32_t SLEEPCR; /*!< (@ 0x50004630) Sleep Control Register */
__IO uint32_t DSLEEPCR; /*!< (@ 0x50004634) Deep Sleep Control Register */
__I uint32_t RESERVED1[2];
__I uint32_t CGATSTAT0; /*!< (@ 0x50004640) Peripheral 0 Clock Gating Status */
__O uint32_t CGATSET0; /*!< (@ 0x50004644) Peripheral 0 Clock Gating Set */
__O uint32_t CGATCLR0; /*!< (@ 0x50004648) Peripheral 0 Clock Gating Clear */
__I uint32_t CGATSTAT1; /*!< (@ 0x5000464C) Peripheral 1 Clock Gating Status */
__O uint32_t CGATSET1; /*!< (@ 0x50004650) Peripheral 1 Clock Gating Set */
__O uint32_t CGATCLR1; /*!< (@ 0x50004654) Peripheral 1 Clock Gating Clear */
__I uint32_t CGATSTAT2; /*!< (@ 0x50004658) Peripheral 2 Clock Gating Status */
__O uint32_t CGATSET2; /*!< (@ 0x5000465C) Peripheral 2 Clock Gating Set */
__O uint32_t CGATCLR2; /*!< (@ 0x50004660) Peripheral 2 Clock Gating Clear */
} SCU_CLK_TypeDef;
/* ================================================================================ */
/* ================ SCU_OSC ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_OSC)
*/
typedef struct { /*!< (@ 0x50004700) SCU_OSC Structure */
__I uint32_t OSCHPSTAT; /*!< (@ 0x50004700) OSC_HP Status Register */
__IO uint32_t OSCHPCTRL; /*!< (@ 0x50004704) OSC_HP Control Register */
__I uint32_t RESERVED0;
__IO uint32_t CLKCALCONST; /*!< (@ 0x5000470C) Clock Calibration Constant Register */
} SCU_OSC_TypeDef;
/* ================================================================================ */
/* ================ SCU_PLL ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_PLL)
*/
typedef struct { /*!< (@ 0x50004710) SCU_PLL Structure */
__I uint32_t PLLSTAT; /*!< (@ 0x50004710) PLL Status Register */
__IO uint32_t PLLCON0; /*!< (@ 0x50004714) PLL Configuration 0 Register */
__IO uint32_t PLLCON1; /*!< (@ 0x50004718) PLL Configuration 1 Register */
__IO uint32_t PLLCON2; /*!< (@ 0x5000471C) PLL Configuration 2 Register */
__I uint32_t USBPLLSTAT; /*!< (@ 0x50004720) USB PLL Status Register */
__IO uint32_t USBPLLCON; /*!< (@ 0x50004724) USB PLL Configuration Register */
__I uint32_t RESERVED0[4];
__I uint32_t CLKMXSTAT; /*!< (@ 0x50004738) Clock Multiplexing Status Register */
} SCU_PLL_TypeDef;
/* ================================================================================ */
/* ================ SCU_GENERAL ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_GENERAL)
*/
typedef struct { /*!< (@ 0x50004000) SCU_GENERAL Structure */
__I uint32_t ID; /*!< (@ 0x50004000) SCU Module ID Register */
__I uint32_t IDCHIP; /*!< (@ 0x50004004) Chip ID Register */
__I uint32_t IDMANUF; /*!< (@ 0x50004008) Manufactory ID Register */
__I uint32_t RESERVED0;
__IO uint32_t STCON; /*!< (@ 0x50004010) Startup Configuration Register */
__I uint32_t RESERVED1[6];
__IO uint32_t GPR[2]; /*!< (@ 0x5000402C) General Purpose Register 0 */
__I uint32_t RESERVED2[6];
__IO uint32_t CCUCON; /*!< (@ 0x5000404C) CCU Control Register */
__I uint32_t RESERVED3[15];
__IO uint32_t DTSCON; /*!< (@ 0x5000408C) Die Temperature Sensor Control Register */
__I uint32_t DTSSTAT; /*!< (@ 0x50004090) Die Temperature Sensor Status Register */
__I uint32_t RESERVED4[3];
__IO uint32_t GORCEN[2]; /*!< (@ 0x500040A0) Out of Range Comparator Enable Register 0 */
__IO uint32_t DTEMPLIM; /*!< (@ 0x500040A8) Die Temperature Sensor Limit Register */
__I uint32_t DTEMPALARM; /*!< (@ 0x500040AC) Die Temperature Sensor Alarm Register */
__I uint32_t RESERVED5[5];
__I uint32_t MIRRSTS; /*!< (@ 0x500040C4) Mirror Write Status Register */
__IO uint32_t RMACR; /*!< (@ 0x500040C8) Retention Memory Access Control Register */
__IO uint32_t RMDATA; /*!< (@ 0x500040CC) Retention Memory Access Data Register */
__I uint32_t MIRRALLSTAT; /*!< (@ 0x500040D0) Mirror All Status */
__O uint32_t MIRRALLREQ; /*!< (@ 0x500040D4) Mirror All Request */
} SCU_GENERAL_TypeDef;
/* ================================================================================ */
/* ================ SCU_INTERRUPT ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_INTERRUPT)
*/
typedef struct { /*!< (@ 0x50004074) SCU_INTERRUPT Structure */
__I uint32_t SRSTAT; /*!< (@ 0x50004074) SCU Service Request Status */
__I uint32_t SRRAW; /*!< (@ 0x50004078) SCU Raw Service Request Status */
__IO uint32_t SRMSK; /*!< (@ 0x5000407C) SCU Service Request Mask */
__O uint32_t SRCLR; /*!< (@ 0x50004080) SCU Service Request Clear */
__O uint32_t SRSET; /*!< (@ 0x50004084) SCU Service Request Set */
__IO uint32_t NMIREQEN; /*!< (@ 0x50004088) SCU Service Request Mask */
} SCU_INTERRUPT_TypeDef;
/* ================================================================================ */
/* ================ SCU_PARITY ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_PARITY)
*/
typedef struct { /*!< (@ 0x5000413C) SCU_PARITY Structure */
__IO uint32_t PEEN; /*!< (@ 0x5000413C) Parity Error Enable Register */
__IO uint32_t MCHKCON; /*!< (@ 0x50004140) Memory Checking Control Register */
__IO uint32_t PETE; /*!< (@ 0x50004144) Parity Error Trap Enable Register */
__IO uint32_t PERSTEN; /*!< (@ 0x50004148) Parity Error Reset Enable Register */
__I uint32_t RESERVED0;
__IO uint32_t PEFLAG; /*!< (@ 0x50004150) Parity Error Flag Register */
__IO uint32_t PMTPR; /*!< (@ 0x50004154) Parity Memory Test Pattern Register */
__IO uint32_t PMTSR; /*!< (@ 0x50004158) Parity Memory Test Select Register */
} SCU_PARITY_TypeDef;
/* ================================================================================ */
/* ================ SCU_TRAP ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_TRAP)
*/
typedef struct { /*!< (@ 0x50004160) SCU_TRAP Structure */
__I uint32_t TRAPSTAT; /*!< (@ 0x50004160) Trap Status Register */
__I uint32_t TRAPRAW; /*!< (@ 0x50004164) Trap Raw Status Register */
__IO uint32_t TRAPDIS; /*!< (@ 0x50004168) Trap Disable Register */
__O uint32_t TRAPCLR; /*!< (@ 0x5000416C) Trap Clear Register */
__O uint32_t TRAPSET; /*!< (@ 0x50004170) Trap Set Register */
} SCU_TRAP_TypeDef;
/* ================================================================================ */
/* ================ SCU_HIBERNATE ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_HIBERNATE)
*/
typedef struct { /*!< (@ 0x50004300) SCU_HIBERNATE Structure */
__I uint32_t HDSTAT; /*!< (@ 0x50004300) Hibernate Domain Status Register */
__O uint32_t HDCLR; /*!< (@ 0x50004304) Hibernate Domain Status Clear Register */
__O uint32_t HDSET; /*!< (@ 0x50004308) Hibernate Domain Status Set Register */
__IO uint32_t HDCR; /*!< (@ 0x5000430C) Hibernate Domain Control Register */
__I uint32_t RESERVED0;
__IO uint32_t OSCSICTRL; /*!< (@ 0x50004314) fOSI Control Register */
__I uint32_t OSCULSTAT; /*!< (@ 0x50004318) OSC_ULP Status Register */
__IO uint32_t OSCULCTRL; /*!< (@ 0x5000431C) OSC_ULP Control Register */
__IO uint32_t LPACCONF; /*!< (@ 0x50004320) Analog Wake-up Configuration Register */
__IO uint32_t LPACTH0; /*!< (@ 0x50004324) LPAC Threshold Register 0 */
__IO uint32_t LPACTH1; /*!< (@ 0x50004328) LPAC Threshold Register 1 */
__I uint32_t LPACST; /*!< (@ 0x5000432C) Hibernate Analog Control State Register */
__O uint32_t LPACCLR; /*!< (@ 0x50004330) LPAC Control Clear Register */
__O uint32_t LPACSET; /*!< (@ 0x50004334) LPAC Control Set Register */
__I uint32_t HINTST; /*!< (@ 0x50004338) Hibernate Internal Control State Register */
__O uint32_t HINTCLR; /*!< (@ 0x5000433C) Hibernate Internal Control Clear Register */
__O uint32_t HINTSET; /*!< (@ 0x50004340) Hibernate Internal Control Set Register */
} SCU_HIBERNATE_TypeDef;
/* ================================================================================ */
/* ================ SCU_POWER ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_POWER)
*/
typedef struct { /*!< (@ 0x50004200) SCU_POWER Structure */
__I uint32_t PWRSTAT; /*!< (@ 0x50004200) PCU Status Register */
__O uint32_t PWRSET; /*!< (@ 0x50004204) PCU Set Control Register */
__O uint32_t PWRCLR; /*!< (@ 0x50004208) PCU Clear Control Register */
__I uint32_t RESERVED0;
__I uint32_t EVRSTAT; /*!< (@ 0x50004210) EVR Status Register */
__I uint32_t EVRVADCSTAT; /*!< (@ 0x50004214) EVR VADC Status Register */
__I uint32_t RESERVED1[5];
__IO uint32_t PWRMON; /*!< (@ 0x5000422C) Power Monitor Control */
} SCU_POWER_TypeDef;
/* ================================================================================ */
/* ================ SCU_RESET ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_RESET)
*/
typedef struct { /*!< (@ 0x50004400) SCU_RESET Structure */
__I uint32_t RSTSTAT; /*!< (@ 0x50004400) RCU Reset Status */
__O uint32_t RSTSET; /*!< (@ 0x50004404) RCU Reset Set Register */
__O uint32_t RSTCLR; /*!< (@ 0x50004408) RCU Reset Clear Register */
__I uint32_t PRSTAT0; /*!< (@ 0x5000440C) RCU Peripheral 0 Reset Status */
__O uint32_t PRSET0; /*!< (@ 0x50004410) RCU Peripheral 0 Reset Set */
__O uint32_t PRCLR0; /*!< (@ 0x50004414) RCU Peripheral 0 Reset Clear */
__I uint32_t PRSTAT1; /*!< (@ 0x50004418) RCU Peripheral 1 Reset Status */
__O uint32_t PRSET1; /*!< (@ 0x5000441C) RCU Peripheral 1 Reset Set */
__O uint32_t PRCLR1; /*!< (@ 0x50004420) RCU Peripheral 1 Reset Clear */
__I uint32_t PRSTAT2; /*!< (@ 0x50004424) RCU Peripheral 2 Reset Status */
__O uint32_t PRSET2; /*!< (@ 0x50004428) RCU Peripheral 2 Reset Set */
__O uint32_t PRCLR2; /*!< (@ 0x5000442C) RCU Peripheral 2 Reset Clear */
} SCU_RESET_TypeDef;
/* ================================================================================ */
/* ================ LEDTS [LEDTS0] ================ */
/* ================================================================================ */
/**
* @brief LED and Touch Sense Unit 0 (LEDTS)
*/
typedef struct { /*!< (@ 0x48010000) LEDTS Structure */
__I uint32_t ID; /*!< (@ 0x48010000) Module Identification Register */
__IO uint32_t GLOBCTL; /*!< (@ 0x48010004) Global Control Register */
__IO uint32_t FNCTL; /*!< (@ 0x48010008) Function Control Register */
__O uint32_t EVFR; /*!< (@ 0x4801000C) Event Flag Register */
__IO uint32_t TSVAL; /*!< (@ 0x48010010) Touch-sense TS-Counter Value */
__IO uint32_t LINE0; /*!< (@ 0x48010014) Line Pattern Register 0 */
__IO uint32_t LINE1; /*!< (@ 0x48010018) Line Pattern Register 1 */
__IO uint32_t LDCMP0; /*!< (@ 0x4801001C) LED Compare Register 0 */
__IO uint32_t LDCMP1; /*!< (@ 0x48010020) LED Compare Register 1 */
__IO uint32_t TSCMP0; /*!< (@ 0x48010024) Touch-sense Compare Register 0 */
__IO uint32_t TSCMP1; /*!< (@ 0x48010028) Touch-sense Compare Register 1 */
} LEDTS0_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ ETH0_CON ================ */
/* ================================================================================ */
/**
* @brief Ethernet Control Register (ETH0_CON)
*/
typedef struct { /*!< (@ 0x50004040) ETH0_CON Structure */
__IO uint32_t CON; /*!< (@ 0x50004040) Ethernet 0 Port Control Register */
} ETH0_CON_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ ETH [ETH0] ================ */
/* ================================================================================ */
/**
* @brief Ethernet Unit 0 (ETH)
*/
typedef struct { /*!< (@ 0x5000C000) ETH Structure */
__IO uint32_t MAC_CONFIGURATION; /*!< (@ 0x5000C000) MAC Configuration Register */
__IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x5000C004) MAC Frame Filter */
__IO uint32_t HASH_TABLE_HIGH; /*!< (@ 0x5000C008) Hash Table High Register */
__IO uint32_t HASH_TABLE_LOW; /*!< (@ 0x5000C00C) Hash Table Low Register */
__IO uint32_t GMII_ADDRESS; /*!< (@ 0x5000C010) MII Address Register */
__IO uint32_t GMII_DATA; /*!< (@ 0x5000C014) MII Data Register */
__IO uint32_t FLOW_CONTROL; /*!< (@ 0x5000C018) Flow Control Register */
__IO uint32_t VLAN_TAG; /*!< (@ 0x5000C01C) VLAN Tag Register */
__I uint32_t VERSION; /*!< (@ 0x5000C020) Version Register */
__I uint32_t DEBUG; /*!< (@ 0x5000C024) Debug Register */
__IO uint32_t REMOTE_WAKE_UP_FRAME_FILTER; /*!< (@ 0x5000C028) Remote Wake Up Frame Filter Register */
__IO uint32_t PMT_CONTROL_STATUS; /*!< (@ 0x5000C02C) PMT Control and Status Register */
__I uint32_t RESERVED0[2];
__I uint32_t INTERRUPT_STATUS; /*!< (@ 0x5000C038) Interrupt Register */
__IO uint32_t INTERRUPT_MASK; /*!< (@ 0x5000C03C) Interrupt Mask Register */
__IO uint32_t MAC_ADDRESS0_HIGH; /*!< (@ 0x5000C040) MAC Address0 High Register */
__IO uint32_t MAC_ADDRESS0_LOW; /*!< (@ 0x5000C044) MAC Address0 Low Register */
__IO uint32_t MAC_ADDRESS1_HIGH; /*!< (@ 0x5000C048) MAC Address1 High Register */
__IO uint32_t MAC_ADDRESS1_LOW; /*!< (@ 0x5000C04C) MAC Address1 Low Register */
__IO uint32_t MAC_ADDRESS2_HIGH; /*!< (@ 0x5000C050) MAC Address2 High Register */
__IO uint32_t MAC_ADDRESS2_LOW; /*!< (@ 0x5000C054) MAC Address2 Low Register */
__IO uint32_t MAC_ADDRESS3_HIGH; /*!< (@ 0x5000C058) MAC Address3 High Register */
__IO uint32_t MAC_ADDRESS3_LOW; /*!< (@ 0x5000C05C) MAC Address3 Low Register */
__I uint32_t RESERVED1[40];
__IO uint32_t MMC_CONTROL; /*!< (@ 0x5000C100) MMC Control Register */
__I uint32_t MMC_RECEIVE_INTERRUPT; /*!< (@ 0x5000C104) MMC Receive Interrupt Register */
__I uint32_t MMC_TRANSMIT_INTERRUPT; /*!< (@ 0x5000C108) MMC Transmit Interrupt Register */
__IO uint32_t MMC_RECEIVE_INTERRUPT_MASK; /*!< (@ 0x5000C10C) MMC Reveive Interrupt Mask Register */
__IO uint32_t MMC_TRANSMIT_INTERRUPT_MASK; /*!< (@ 0x5000C110) MMC Transmit Interrupt Mask Register */
__I uint32_t TX_OCTET_COUNT_GOOD_BAD; /*!< (@ 0x5000C114) Transmit Octet Count for Good and Bad Frames
Register */
__I uint32_t TX_FRAME_COUNT_GOOD_BAD; /*!< (@ 0x5000C118) Transmit Frame Count for Goodand Bad Frames Register */
__I uint32_t TX_BROADCAST_FRAMES_GOOD; /*!< (@ 0x5000C11C) Transmit Frame Count for Good Broadcast Frames */
__I uint32_t TX_MULTICAST_FRAMES_GOOD; /*!< (@ 0x5000C120) Transmit Frame Count for Good Multicast Frames */
__I uint32_t TX_64OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C124) Transmit Octet Count for Good and Bad 64 Byte
Frames */
__I uint32_t TX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C128) Transmit Octet Count for Good and Bad 65 to 127
Bytes Frames */
__I uint32_t TX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C12C) Transmit Octet Count for Good and Bad 128 to
255 Bytes Frames */
__I uint32_t TX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C130) Transmit Octet Count for Good and Bad 256 to
511 Bytes Frames */
__I uint32_t TX_512TO1023OCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C134) Transmit Octet Count for Good and Bad 512 to
1023 Bytes Frames */
__I uint32_t TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C138) Transmit Octet Count for Good and Bad 1024 to
Maxsize Bytes Frames */
__I uint32_t TX_UNICAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C13C) Transmit Frame Count for Good and Bad Unicast
Frames */
__I uint32_t TX_MULTICAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C140) Transmit Frame Count for Good and Bad Multicast
Frames */
__I uint32_t TX_BROADCAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C144) Transmit Frame Count for Good and Bad Broadcast
Frames */
__I uint32_t TX_UNDERFLOW_ERROR_FRAMES; /*!< (@ 0x5000C148) Transmit Frame Count for Underflow Error Frames */
__I uint32_t TX_SINGLE_COLLISION_GOOD_FRAMES; /*!< (@ 0x5000C14C) Transmit Frame Count for Frames Transmitted after
Single Collision */
__I uint32_t TX_MULTIPLE_COLLISION_GOOD_FRAMES; /*!< (@ 0x5000C150) Transmit Frame Count for Frames Transmitted after
Multiple Collision */
__I uint32_t TX_DEFERRED_FRAMES; /*!< (@ 0x5000C154) Tx Deferred Frames Register */
__I uint32_t TX_LATE_COLLISION_FRAMES; /*!< (@ 0x5000C158) Transmit Frame Count for Late Collision Error
Frames */
__I uint32_t TX_EXCESSIVE_COLLISION_FRAMES; /*!< (@ 0x5000C15C) Transmit Frame Count for Excessive Collision
Error Frames */
__I uint32_t TX_CARRIER_ERROR_FRAMES; /*!< (@ 0x5000C160) Transmit Frame Count for Carrier Sense Error
Frames */
__I uint32_t TX_OCTET_COUNT_GOOD; /*!< (@ 0x5000C164) Tx Octet Count Good Register */
__I uint32_t TX_FRAME_COUNT_GOOD; /*!< (@ 0x5000C168) Tx Frame Count Good Register */
__I uint32_t TX_EXCESSIVE_DEFERRAL_ERROR; /*!< (@ 0x5000C16C) Transmit Frame Count for Excessive Deferral Error
Frames */
__I uint32_t TX_PAUSE_FRAMES; /*!< (@ 0x5000C170) Transmit Frame Count for Good PAUSE Frames */
__I uint32_t TX_VLAN_FRAMES_GOOD; /*!< (@ 0x5000C174) Transmit Frame Count for Good VLAN Frames */
__I uint32_t TX_OSIZE_FRAMES_GOOD; /*!< (@ 0x5000C178) Transmit Frame Count for Good Oversize Frames */
__I uint32_t RESERVED2;
__I uint32_t RX_FRAMES_COUNT_GOOD_BAD; /*!< (@ 0x5000C180) Receive Frame Count for Good and Bad Frames */
__I uint32_t RX_OCTET_COUNT_GOOD_BAD; /*!< (@ 0x5000C184) Receive Octet Count for Good and Bad Frames */
__I uint32_t RX_OCTET_COUNT_GOOD; /*!< (@ 0x5000C188) Rx Octet Count Good Register */
__I uint32_t RX_BROADCAST_FRAMES_GOOD; /*!< (@ 0x5000C18C) Receive Frame Count for Good Broadcast Frames */
__I uint32_t RX_MULTICAST_FRAMES_GOOD; /*!< (@ 0x5000C190) Receive Frame Count for Good Multicast Frames */
__I uint32_t RX_CRC_ERROR_FRAMES; /*!< (@ 0x5000C194) Receive Frame Count for CRC Error Frames */
__I uint32_t RX_ALIGNMENT_ERROR_FRAMES; /*!< (@ 0x5000C198) Receive Frame Count for Alignment Error Frames */
__I uint32_t RX_RUNT_ERROR_FRAMES; /*!< (@ 0x5000C19C) Receive Frame Count for Runt Error Frames */
__I uint32_t RX_JABBER_ERROR_FRAMES; /*!< (@ 0x5000C1A0) Receive Frame Count for Jabber Error Frames */
__I uint32_t RX_UNDERSIZE_FRAMES_GOOD; /*!< (@ 0x5000C1A4) Receive Frame Count for Undersize Frames */
__I uint32_t RX_OVERSIZE_FRAMES_GOOD; /*!< (@ 0x5000C1A8) Rx Oversize Frames Good Register */
__I uint32_t RX_64OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1AC) Receive Frame Count for Good and Bad 64 Byte
Frames */
__I uint32_t RX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B0) Receive Frame Count for Good and Bad 65 to 127
Bytes Frames */
__I uint32_t RX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B4) Receive Frame Count for Good and Bad 128 to 255
Bytes Frames */
__I uint32_t RX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B8) Receive Frame Count for Good and Bad 256 to 511
Bytes Frames */
__I uint32_t RX_512TO1023OCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C1BC) Receive Frame Count for Good and Bad 512 to 1,023
Bytes Frames */
__I uint32_t RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C1C0) Receive Frame Count for Good and Bad 1,024 to
Maxsize Bytes Frames */
__I uint32_t RX_UNICAST_FRAMES_GOOD; /*!< (@ 0x5000C1C4) Receive Frame Count for Good Unicast Frames */
__I uint32_t RX_LENGTH_ERROR_FRAMES; /*!< (@ 0x5000C1C8) Receive Frame Count for Length Error Frames */
__I uint32_t RX_OUT_OF_RANGE_TYPE_FRAMES; /*!< (@ 0x5000C1CC) Receive Frame Count for Out of Range Frames */
__I uint32_t RX_PAUSE_FRAMES; /*!< (@ 0x5000C1D0) Receive Frame Count for PAUSE Frames */
__I uint32_t RX_FIFO_OVERFLOW_FRAMES; /*!< (@ 0x5000C1D4) Receive Frame Count for FIFO Overflow Frames */
__I uint32_t RX_VLAN_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1D8) Receive Frame Count for Good and Bad VLAN Frames */
__I uint32_t RX_WATCHDOG_ERROR_FRAMES; /*!< (@ 0x5000C1DC) Receive Frame Count for Watchdog Error Frames */
__I uint32_t RX_RECEIVE_ERROR_FRAMES; /*!< (@ 0x5000C1E0) Receive Frame Count for Receive Error Frames */
__I uint32_t RX_CONTROL_FRAMES_GOOD; /*!< (@ 0x5000C1E4) Receive Frame Count for Good Control Frames Frames */
__I uint32_t RESERVED3[6];
__IO uint32_t MMC_IPC_RECEIVE_INTERRUPT_MASK; /*!< (@ 0x5000C200) MMC Receive Checksum Offload Interrupt Mask Register */
__I uint32_t RESERVED4;
__I uint32_t MMC_IPC_RECEIVE_INTERRUPT; /*!< (@ 0x5000C208) MMC Receive Checksum Offload Interrupt Register */
__I uint32_t RESERVED5;
__I uint32_t RXIPV4_GOOD_FRAMES; /*!< (@ 0x5000C210) RxIPv4 Good Frames Register */
__I uint32_t RXIPV4_HEADER_ERROR_FRAMES; /*!< (@ 0x5000C214) Receive IPV4 Header Error Frame Counter Register */
__I uint32_t RXIPV4_NO_PAYLOAD_FRAMES; /*!< (@ 0x5000C218) Receive IPV4 No Payload Frame Counter Register */
__I uint32_t RXIPV4_FRAGMENTED_FRAMES; /*!< (@ 0x5000C21C) Receive IPV4 Fragmented Frame Counter Register */
__I uint32_t RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES;/*!< (@ 0x5000C220) Receive IPV4 UDP Checksum Disabled Frame Counter
Register */
__I uint32_t RXIPV6_GOOD_FRAMES; /*!< (@ 0x5000C224) RxIPv6 Good Frames Register */
__I uint32_t RXIPV6_HEADER_ERROR_FRAMES; /*!< (@ 0x5000C228) Receive IPV6 Header Error Frame Counter Register */
__I uint32_t RXIPV6_NO_PAYLOAD_FRAMES; /*!< (@ 0x5000C22C) Receive IPV6 No Payload Frame Counter Register */
__I uint32_t RXUDP_GOOD_FRAMES; /*!< (@ 0x5000C230) RxUDP Good Frames Register */
__I uint32_t RXUDP_ERROR_FRAMES; /*!< (@ 0x5000C234) RxUDP Error Frames Register */
__I uint32_t RXTCP_GOOD_FRAMES; /*!< (@ 0x5000C238) RxTCP Good Frames Register */
__I uint32_t RXTCP_ERROR_FRAMES; /*!< (@ 0x5000C23C) RxTCP Error Frames Register */
__I uint32_t RXICMP_GOOD_FRAMES; /*!< (@ 0x5000C240) RxICMP Good Frames Register */
__I uint32_t RXICMP_ERROR_FRAMES; /*!< (@ 0x5000C244) RxICMP Error Frames Register */
__I uint32_t RESERVED6[2];
__I uint32_t RXIPV4_GOOD_OCTETS; /*!< (@ 0x5000C250) RxIPv4 Good Octets Register */
__I uint32_t RXIPV4_HEADER_ERROR_OCTETS; /*!< (@ 0x5000C254) Receive IPV4 Header Error Octet Counter Register */
__I uint32_t RXIPV4_NO_PAYLOAD_OCTETS; /*!< (@ 0x5000C258) Receive IPV4 No Payload Octet Counter Register */
__I uint32_t RXIPV4_FRAGMENTED_OCTETS; /*!< (@ 0x5000C25C) Receive IPV4 Fragmented Octet Counter Register */
__I uint32_t RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS;/*!< (@ 0x5000C260) Receive IPV4 Fragmented Octet Counter Register */
__I uint32_t RXIPV6_GOOD_OCTETS; /*!< (@ 0x5000C264) RxIPv6 Good Octets Register */
__I uint32_t RXIPV6_HEADER_ERROR_OCTETS; /*!< (@ 0x5000C268) Receive IPV6 Header Error Octet Counter Register */
__I uint32_t RXIPV6_NO_PAYLOAD_OCTETS; /*!< (@ 0x5000C26C) Receive IPV6 No Payload Octet Counter Register */
__I uint32_t RXUDP_GOOD_OCTETS; /*!< (@ 0x5000C270) Receive UDP Good Octets Register */
__I uint32_t RXUDP_ERROR_OCTETS; /*!< (@ 0x5000C274) Receive UDP Error Octets Register */
__I uint32_t RXTCP_GOOD_OCTETS; /*!< (@ 0x5000C278) Receive TCP Good Octets Register */
__I uint32_t RXTCP_ERROR_OCTETS; /*!< (@ 0x5000C27C) Receive TCP Error Octets Register */
__I uint32_t RXICMP_GOOD_OCTETS; /*!< (@ 0x5000C280) Receive ICMP Good Octets Register */
__I uint32_t RXICMP_ERROR_OCTETS; /*!< (@ 0x5000C284) Receive ICMP Error Octets Register */
__I uint32_t RESERVED7[286];
__IO uint32_t TIMESTAMP_CONTROL; /*!< (@ 0x5000C700) Timestamp Control Register */
__IO uint32_t SUB_SECOND_INCREMENT; /*!< (@ 0x5000C704) Sub-Second Increment Register */
__I uint32_t SYSTEM_TIME_SECONDS; /*!< (@ 0x5000C708) System Time - Seconds Register */
__I uint32_t SYSTEM_TIME_NANOSECONDS; /*!< (@ 0x5000C70C) System Time Nanoseconds Register */
__IO uint32_t SYSTEM_TIME_SECONDS_UPDATE; /*!< (@ 0x5000C710) System Time - Seconds Update Register */
__IO uint32_t SYSTEM_TIME_NANOSECONDS_UPDATE; /*!< (@ 0x5000C714) System Time Nanoseconds Update Register */
__IO uint32_t TIMESTAMP_ADDEND; /*!< (@ 0x5000C718) Timestamp Addend Register */
__IO uint32_t TARGET_TIME_SECONDS; /*!< (@ 0x5000C71C) Target Time Seconds Register */
__IO uint32_t TARGET_TIME_NANOSECONDS; /*!< (@ 0x5000C720) Target Time Nanoseconds Register */
__IO uint32_t SYSTEM_TIME_HIGHER_WORD_SECONDS; /*!< (@ 0x5000C724) System Time - Higher Word Seconds Register */
__I uint32_t TIMESTAMP_STATUS; /*!< (@ 0x5000C728) Timestamp Status Register */
__IO uint32_t PPS_CONTROL; /*!< (@ 0x5000C72C) PPS Control Register */
__I uint32_t RESERVED8[564];
__IO uint32_t BUS_MODE; /*!< (@ 0x5000D000) Bus Mode Register */
__IO uint32_t TRANSMIT_POLL_DEMAND; /*!< (@ 0x5000D004) Transmit Poll Demand Register */
__IO uint32_t RECEIVE_POLL_DEMAND; /*!< (@ 0x5000D008) Receive Poll Demand Register */
__IO uint32_t RECEIVE_DESCRIPTOR_LIST_ADDRESS; /*!< (@ 0x5000D00C) Receive Descriptor Address Register */
__IO uint32_t TRANSMIT_DESCRIPTOR_LIST_ADDRESS; /*!< (@ 0x5000D010) Transmit descripter Address Register */
__IO uint32_t STATUS; /*!< (@ 0x5000D014) Status Register */
__IO uint32_t OPERATION_MODE; /*!< (@ 0x5000D018) Operation Mode Register */
__IO uint32_t INTERRUPT_ENABLE; /*!< (@ 0x5000D01C) Interrupt Enable Register */
__I uint32_t MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER;/*!< (@ 0x5000D020) Missed Frame and Buffer Overflow Counter Register */
__IO uint32_t RECEIVE_INTERRUPT_WATCHDOG_TIMER; /*!< (@ 0x5000D024) Receive Interrupt Watchdog Timer Register */
__I uint32_t RESERVED9;
__I uint32_t AHB_STATUS; /*!< (@ 0x5000D02C) AHB Status Register */
__I uint32_t RESERVED10[6];
__I uint32_t CURRENT_HOST_TRANSMIT_DESCRIPTOR; /*!< (@ 0x5000D048) Current Host Transmit Descriptor Register */
__I uint32_t CURRENT_HOST_RECEIVE_DESCRIPTOR; /*!< (@ 0x5000D04C) Current Host Receive Descriptor Register */
__I uint32_t CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS;/*!< (@ 0x5000D050) Current Host Transmit Buffer Address Register */
__I uint32_t CURRENT_HOST_RECEIVE_BUFFER_ADDRESS;/*!< (@ 0x5000D054) Current Host Receive Buffer Address Register */
__IO uint32_t HW_FEATURE; /*!< (@ 0x5000D058) HW Feature Register */
} ETH_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ USB [USB0] ================ */
/* ================================================================================ */
/**
* @brief Universal Serial Bus (USB)
*/
typedef struct { /*!< (@ 0x50040000) USB Structure */
__IO uint32_t GOTGCTL; /*!< (@ 0x50040000) Control and Status Register */
__IO uint32_t GOTGINT; /*!< (@ 0x50040004) OTG Interrupt Register */
__IO uint32_t GAHBCFG; /*!< (@ 0x50040008) AHB Configuration Register */
__IO uint32_t GUSBCFG; /*!< (@ 0x5004000C) USB Configuration Register */
__IO uint32_t GRSTCTL; /*!< (@ 0x50040010) Reset Register */
union {
__IO uint32_t GINTSTS_DEVICEMODE; /*!< (@ 0x50040014) Interrupt Register [DEVICEMODE] */
__IO uint32_t GINTSTS_HOSTMODE; /*!< (@ 0x50040014) Interrupt Register [HOSTMODE] */
};
union {
__IO uint32_t GINTMSK_DEVICEMODE; /*!< (@ 0x50040018) Interrupt Mask Register [DEVICEMODE] */
__IO uint32_t GINTMSK_HOSTMODE; /*!< (@ 0x50040018) Interrupt Mask Register [HOSTMODE] */
};
union {
__I uint32_t GRXSTSR_DEVICEMODE; /*!< (@ 0x5004001C) Receive Status Debug Read Register [DEVICEMODE] */
__I uint32_t GRXSTSR_HOSTMODE; /*!< (@ 0x5004001C) Receive Status Debug Read Register [HOSTMODE] */
};
union {
__I uint32_t GRXSTSP_HOSTMODE; /*!< (@ 0x50040020) Receive Status Read and Pop Register [HOSTMODE] */
__I uint32_t GRXSTSP_DEVICEMODE; /*!< (@ 0x50040020) Receive Status Read and Pop Register [DEVICEMODE] */
};
__IO uint32_t GRXFSIZ; /*!< (@ 0x50040024) Receive FIFO Size Register */
union {
__IO uint32_t GNPTXFSIZ_DEVICEMODE; /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register [DEVICEMODE] */
__IO uint32_t GNPTXFSIZ_HOSTMODE; /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register [HOSTMODE] */
};
__I uint32_t GNPTXSTS; /*!< (@ 0x5004002C) Non-Periodic Transmit FIFO/Queue Status Register */
__I uint32_t RESERVED0[3];
__IO uint32_t GUID; /*!< (@ 0x5004003C) USB Module Identification Register */
__I uint32_t RESERVED1[7];
__IO uint32_t GDFIFOCFG; /*!< (@ 0x5004005C) Global DFIFO Software Config Register */
__I uint32_t RESERVED2[40];
__IO uint32_t HPTXFSIZ; /*!< (@ 0x50040100) Host Periodic Transmit FIFO Size Register */
__IO uint32_t DIEPTXF1; /*!< (@ 0x50040104) Device IN Endpoint Transmit FIFO Size Register */
__IO uint32_t DIEPTXF2; /*!< (@ 0x50040108) Device IN Endpoint Transmit FIFO Size Register */
__IO uint32_t DIEPTXF3; /*!< (@ 0x5004010C) Device IN Endpoint Transmit FIFO Size Register */
__IO uint32_t DIEPTXF4; /*!< (@ 0x50040110) Device IN Endpoint Transmit FIFO Size Register */
__IO uint32_t DIEPTXF5; /*!< (@ 0x50040114) Device IN Endpoint Transmit FIFO Size Register */
__IO uint32_t DIEPTXF6; /*!< (@ 0x50040118) Device IN Endpoint Transmit FIFO Size Register */
__I uint32_t RESERVED3[185];
__IO uint32_t HCFG; /*!< (@ 0x50040400) Host Configuration Register */
__IO uint32_t HFIR; /*!< (@ 0x50040404) Host Frame Interval Register */
__IO uint32_t HFNUM; /*!< (@ 0x50040408) Host Frame Number/Frame Time Remaining Register */
__I uint32_t RESERVED4;
__IO uint32_t HPTXSTS; /*!< (@ 0x50040410) Host Periodic Transmit FIFO/ Queue Status Register */
__I uint32_t HAINT; /*!< (@ 0x50040414) Host All Channels Interrupt Register */
__IO uint32_t HAINTMSK; /*!< (@ 0x50040418) Host All Channels Interrupt Mask Register */
__IO uint32_t HFLBADDR; /*!< (@ 0x5004041C) Host Frame List Base Address Register */
__I uint32_t RESERVED5[8];
__IO uint32_t HPRT; /*!< (@ 0x50040440) Host Port Control and Status Register */
__I uint32_t RESERVED6[239];
__IO uint32_t DCFG; /*!< (@ 0x50040800) Device Configuration Register */
__IO uint32_t DCTL; /*!< (@ 0x50040804) Device Control Register */
__I uint32_t DSTS; /*!< (@ 0x50040808) Device Status Register */
__I uint32_t RESERVED7;
__IO uint32_t DIEPMSK; /*!< (@ 0x50040810) Device IN Endpoint Common Interrupt Mask Register */
__IO uint32_t DOEPMSK; /*!< (@ 0x50040814) Device OUT Endpoint Common Interrupt Mask Register */
__I uint32_t DAINT; /*!< (@ 0x50040818) Device All Endpoints Interrupt Register */
__IO uint32_t DAINTMSK; /*!< (@ 0x5004081C) Device All Endpoints Interrupt Mask Register */
__I uint32_t RESERVED8[2];
__IO uint32_t DVBUSDIS; /*!< (@ 0x50040828) Device VBUS Discharge Time Register */
__IO uint32_t DVBUSPULSE; /*!< (@ 0x5004082C) Device VBUS Pulsing Time Register */
__I uint32_t RESERVED9;
__IO uint32_t DIEPEMPMSK; /*!< (@ 0x50040834) Device IN Endpoint FIFO Empty Interrupt Mask
Register */
__I uint32_t RESERVED10[370];
__IO uint32_t PCGCCTL; /*!< (@ 0x50040E00) Power and Clock Gating Control Register */
} USB0_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ USB0_EP0 ================ */
/* ================================================================================ */
/**
* @brief Universal Serial Bus (USB0_EP0)
*/
typedef struct { /*!< (@ 0x50040900) USB0_EP0 Structure */
__IO uint32_t DIEPCTL0; /*!< (@ 0x50040900) Device Control IN Endpoint Control Register */
__I uint32_t RESERVED0;
__IO uint32_t DIEPINT0; /*!< (@ 0x50040908) Device Endpoint Interrupt Register */
__I uint32_t RESERVED1;
__IO uint32_t DIEPTSIZ0; /*!< (@ 0x50040910) Device IN Endpoint Transfer Size Register */
__IO uint32_t DIEPDMA0; /*!< (@ 0x50040914) Device Endpoint DMA Address Register */
__I uint32_t DTXFSTS0; /*!< (@ 0x50040918) Device IN Endpoint Transmit FIFO Status Register */
__I uint32_t DIEPDMAB0; /*!< (@ 0x5004091C) Device Endpoint DMA Buffer Address Register */
__I uint32_t RESERVED2[120];
__IO uint32_t DOEPCTL0; /*!< (@ 0x50040B00) Device Control OUT Endpoint Control Register */
__I uint32_t RESERVED3;
__IO uint32_t DOEPINT0; /*!< (@ 0x50040B08) Device Endpoint Interrupt Register */
__I uint32_t RESERVED4;
__IO uint32_t DOEPTSIZ0; /*!< (@ 0x50040B10) Device OUT Endpoint Transfer Size Register */
__IO uint32_t DOEPDMA0; /*!< (@ 0x50040B14) Device Endpoint DMA Address Register */
__I uint32_t RESERVED5;
__I uint32_t DOEPDMAB0; /*!< (@ 0x50040B1C) Device Endpoint DMA Buffer Address Register */
} USB0_EP0_TypeDef;
/* ================================================================================ */
/* ================ USB_EP [USB0_EP1] ================ */
/* ================================================================================ */
/**
* @brief Universal Serial Bus (USB_EP)
*/
typedef struct { /*!< (@ 0x50040920) USB_EP Structure */
union {
__IO uint32_t DIEPCTL_INTBULK; /*!< (@ 0x50040920) Device Endpoint Control Register [INTBULK] */
__IO uint32_t DIEPCTL_ISOCONT; /*!< (@ 0x50040920) Device Endpoint Control Register [ISOCONT] */
};
__I uint32_t RESERVED0;
__IO uint32_t DIEPINT; /*!< (@ 0x50040928) Device Endpoint Interrupt Register */
__I uint32_t RESERVED1;
__IO uint32_t DIEPTSIZ; /*!< (@ 0x50040930) Device Endpoint Transfer Size Register */
__IO uint32_t DIEPDMA; /*!< (@ 0x50040934) Device Endpoint DMA Address Register */
__I uint32_t DTXFSTS; /*!< (@ 0x50040938) Device IN Endpoint Transmit FIFO Status Register */
__I uint32_t DIEPDMAB; /*!< (@ 0x5004093C) Device Endpoint DMA Buffer Address Register */
__I uint32_t RESERVED2[120];
union {
__IO uint32_t DOEPCTL_INTBULK; /*!< (@ 0x50040B20) Device Endpoint Control Register [INTBULK] */
__IO uint32_t DOEPCTL_ISOCONT; /*!< (@ 0x50040B20) Device Endpoint Control Register [ISOCONT] */
};
__I uint32_t RESERVED3;
__IO uint32_t DOEPINT; /*!< (@ 0x50040B28) Device Endpoint Interrupt Register */
__I uint32_t RESERVED4;
union {
__IO uint32_t DOEPTSIZ_CONTROL; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [CONT] */
__IO uint32_t DOEPTSIZ_ISO; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [ISO] */
};
__IO uint32_t DOEPDMA; /*!< (@ 0x50040B34) Device Endpoint DMA Address Register */
__I uint32_t RESERVED5;
__I uint32_t DOEPDMAB; /*!< (@ 0x50040B3C) Device Endpoint DMA Buffer Address Register */
} USB0_EP_TypeDef;
/* ================================================================================ */
/* ================ USB_CH [USB0_CH0] ================ */
/* ================================================================================ */
/**
* @brief Universal Serial Bus (USB_CH)
*/
typedef struct { /*!< (@ 0x50040500) USB_CH Structure */
__IO uint32_t HCCHAR; /*!< (@ 0x50040500) Host Channel Characteristics Register */
__I uint32_t RESERVED0;
__IO uint32_t HCINT; /*!< (@ 0x50040508) Host Channel Interrupt Register */
__IO uint32_t HCINTMSK; /*!< (@ 0x5004050C) Host Channel Interrupt Mask Register */
union {
__IO uint32_t HCTSIZ_SCATGATHER; /*!< (@ 0x50040510) Host Channel Transfer Size Register [SCATGATHER] */
__IO uint32_t HCTSIZ_BUFFERMODE; /*!< (@ 0x50040510) Host Channel Transfer Size Register [BUFFERMODE] */
};
union {
__IO uint32_t HCDMA_SCATGATHER; /*!< (@ 0x50040514) Host Channel DMA Address Register [SCATGATHER] */
__IO uint32_t HCDMA_BUFFERMODE; /*!< (@ 0x50040514) Host Channel DMA Address Register [BUFFERMODE] */
};
__I uint32_t RESERVED1;
__I uint32_t HCDMAB; /*!< (@ 0x5004051C) Host Channel DMA Buffer Address Register */
} USB0_CH_TypeDef;
/* ================================================================================ */
/* ================ USIC [USIC0] ================ */
/* ================================================================================ */
/**
* @brief Universal Serial Interface Controller 0 (USIC)
*/
typedef struct { /*!< (@ 0x40030008) USIC Structure */
__I uint32_t ID; /*!< (@ 0x40030008) Module Identification Register */
} USIC_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ USIC_CH [USIC0_CH0] ================ */
/* ================================================================================ */
/**
* @brief Universal Serial Interface Controller 0 (USIC_CH)
*/
typedef struct { /*!< (@ 0x40030000) USIC_CH Structure */
__I uint32_t RESERVED0;
__I uint32_t CCFG; /*!< (@ 0x40030004) Channel Configuration Register */
__I uint32_t RESERVED1;
__IO uint32_t KSCFG; /*!< (@ 0x4003000C) Kernel State Configuration Register */
__IO uint32_t FDR; /*!< (@ 0x40030010) Fractional Divider Register */
__IO uint32_t BRG; /*!< (@ 0x40030014) Baud Rate Generator Register */
__IO uint32_t INPR; /*!< (@ 0x40030018) Interrupt Node Pointer Register */
__IO uint32_t DX0CR; /*!< (@ 0x4003001C) Input Control Register 0 */
__IO uint32_t DX1CR; /*!< (@ 0x40030020) Input Control Register 1 */
__IO uint32_t DX2CR; /*!< (@ 0x40030024) Input Control Register 2 */
__IO uint32_t DX3CR; /*!< (@ 0x40030028) Input Control Register 3 */
__IO uint32_t DX4CR; /*!< (@ 0x4003002C) Input Control Register 4 */
__IO uint32_t DX5CR; /*!< (@ 0x40030030) Input Control Register 5 */
__IO uint32_t SCTR; /*!< (@ 0x40030034) Shift Control Register */
__IO uint32_t TCSR; /*!< (@ 0x40030038) Transmit Control/Status Register */
union {
__IO uint32_t PCR_IICMode; /*!< (@ 0x4003003C) Protocol Control Register [IIC Mode] */
__IO uint32_t PCR_IISMode; /*!< (@ 0x4003003C) Protocol Control Register [IIS Mode] */
__IO uint32_t PCR_SSCMode; /*!< (@ 0x4003003C) Protocol Control Register [SSC Mode] */
__IO uint32_t PCR; /*!< (@ 0x4003003C) Protocol Control Register */
__IO uint32_t PCR_ASCMode; /*!< (@ 0x4003003C) Protocol Control Register [ASC Mode] */
};
__IO uint32_t CCR; /*!< (@ 0x40030040) Channel Control Register */
__IO uint32_t CMTR; /*!< (@ 0x40030044) Capture Mode Timer Register */
union {
__IO uint32_t PSR_IICMode; /*!< (@ 0x40030048) Protocol Status Register [IIC Mode] */
__IO uint32_t PSR_IISMode; /*!< (@ 0x40030048) Protocol Status Register [IIS Mode] */
__IO uint32_t PSR_SSCMode; /*!< (@ 0x40030048) Protocol Status Register [SSC Mode] */
__IO uint32_t PSR; /*!< (@ 0x40030048) Protocol Status Register */
__IO uint32_t PSR_ASCMode; /*!< (@ 0x40030048) Protocol Status Register [ASC Mode] */
};
__O uint32_t PSCR; /*!< (@ 0x4003004C) Protocol Status Clear Register */
__I uint32_t RBUFSR; /*!< (@ 0x40030050) Receiver Buffer Status Register */
__I uint32_t RBUF; /*!< (@ 0x40030054) Receiver Buffer Register */
__I uint32_t RBUFD; /*!< (@ 0x40030058) Receiver Buffer Register for Debugger */
__I uint32_t RBUF0; /*!< (@ 0x4003005C) Receiver Buffer Register 0 */
__I uint32_t RBUF1; /*!< (@ 0x40030060) Receiver Buffer Register 1 */
__I uint32_t RBUF01SR; /*!< (@ 0x40030064) Receiver Buffer 01 Status Register */
__O uint32_t FMR; /*!< (@ 0x40030068) Flag Modification Register */
__I uint32_t RESERVED2[5];
__IO uint32_t TBUF[32]; /*!< (@ 0x40030080) Transmit Buffer */
__IO uint32_t BYP; /*!< (@ 0x40030100) Bypass Data Register */
__IO uint32_t BYPCR; /*!< (@ 0x40030104) Bypass Control Register */
__IO uint32_t TBCTR; /*!< (@ 0x40030108) Transmitter Buffer Control Register */
__IO uint32_t RBCTR; /*!< (@ 0x4003010C) Receiver Buffer Control Register */
__I uint32_t TRBPTR; /*!< (@ 0x40030110) Transmit/Receive Buffer Pointer Register */
__IO uint32_t TRBSR; /*!< (@ 0x40030114) Transmit/Receive Buffer Status Register */
__O uint32_t TRBSCR; /*!< (@ 0x40030118) Transmit/Receive Buffer Status Clear Register */
__I uint32_t OUTR; /*!< (@ 0x4003011C) Receiver Buffer Output Register */
__I uint32_t OUTDR; /*!< (@ 0x40030120) Receiver Buffer Output Register L for Debugger */
__I uint32_t RESERVED3[23];
__O uint32_t IN[32]; /*!< (@ 0x40030180) Transmit FIFO Buffer */
} USIC_CH_TypeDef;
/* ================================================================================ */
/* ================ CAN ================ */
/* ================================================================================ */
/**
* @brief Controller Area Networks (CAN)
*/
typedef struct { /*!< (@ 0x48014000) CAN Structure */
__IO uint32_t CLC; /*!< (@ 0x48014000) CAN Clock Control Register */
__I uint32_t RESERVED0;
__I uint32_t ID; /*!< (@ 0x48014008) Module Identification Register */
__IO uint32_t FDR; /*!< (@ 0x4801400C) CAN Fractional Divider Register */
__I uint32_t RESERVED1[60];
__I uint32_t LIST[8]; /*!< (@ 0x48014100) List Register */
__I uint32_t RESERVED2[8];
__IO uint32_t MSPND[8]; /*!< (@ 0x48014140) Message Pending Register */
__I uint32_t RESERVED3[8];
__I uint32_t MSID[8]; /*!< (@ 0x48014180) Message Index Register */
__I uint32_t RESERVED4[8];
__IO uint32_t MSIMASK; /*!< (@ 0x480141C0) Message Index Mask Register */
__IO uint32_t PANCTR; /*!< (@ 0x480141C4) Panel Control Register */
__IO uint32_t MCR; /*!< (@ 0x480141C8) Module Control Register */
__O uint32_t MITR; /*!< (@ 0x480141CC) Module Interrupt Trigger Register */
} CAN_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ CAN_NODE [CAN_NODE0] ================ */
/* ================================================================================ */
/**
* @brief Controller Area Networks (CAN_NODE)
*/
typedef struct { /*!< (@ 0x48014200) CAN_NODE Structure */
__IO uint32_t NCR; /*!< (@ 0x48014200) Node Control Register */
__IO uint32_t NSR; /*!< (@ 0x48014204) Node Status Register */
__IO uint32_t NIPR; /*!< (@ 0x48014208) Node Interrupt Pointer Register */
__IO uint32_t NPCR; /*!< (@ 0x4801420C) Node Port Control Register */
__IO uint32_t NBTR; /*!< (@ 0x48014210) Node Bit Timing Register */
__IO uint32_t NECNT; /*!< (@ 0x48014214) Node Error Counter Register */
__IO uint32_t NFCR; /*!< (@ 0x48014218) Node Frame Counter Register */
} CAN_NODE_TypeDef;
/* ================================================================================ */
/* ================ CAN_MO [CAN_MO0] ================ */
/* ================================================================================ */
/**
* @brief Controller Area Networks (CAN_MO)
*/
typedef struct { /*!< (@ 0x48015000) CAN_MO Structure */
__IO uint32_t MOFCR; /*!< (@ 0x48015000) Message Object Function Control Register */
__IO uint32_t MOFGPR; /*!< (@ 0x48015004) Message Object FIFO/Gateway Pointer Register */
__IO uint32_t MOIPR; /*!< (@ 0x48015008) Message Object Interrupt Pointer Register */
__IO uint32_t MOAMR; /*!< (@ 0x4801500C) Message Object Acceptance Mask Register */
__IO uint32_t MODATAL; /*!< (@ 0x48015010) Message Object Data Register Low */
__IO uint32_t MODATAH; /*!< (@ 0x48015014) Message Object Data Register High */
__IO uint32_t MOAR; /*!< (@ 0x48015018) Message Object Arbitration Register */
union {
__I uint32_t MOSTAT; /*!< (@ 0x4801501C) Message Object Status Register */
__O uint32_t MOCTR; /*!< (@ 0x4801501C) Message Object Control Register */
};
} CAN_MO_TypeDef;
/* ================================================================================ */
/* ================ VADC ================ */
/* ================================================================================ */
/**
* @brief Analog to Digital Converter (VADC)
*/
typedef struct { /*!< (@ 0x40004000) VADC Structure */
__IO uint32_t CLC; /*!< (@ 0x40004000) Clock Control Register */
__I uint32_t RESERVED0;
__I uint32_t ID; /*!< (@ 0x40004008) Module Identification Register */
__I uint32_t RESERVED1[7];
__IO uint32_t OCS; /*!< (@ 0x40004028) OCDS Control and Status Register */
__I uint32_t RESERVED2[21];
__IO uint32_t GLOBCFG; /*!< (@ 0x40004080) Global Configuration Register */
__I uint32_t RESERVED3[7];
__IO uint32_t GLOBICLASS[2]; /*!< (@ 0x400040A0) Input Class Register, Global */
__I uint32_t RESERVED4[4];
__IO uint32_t GLOBBOUND; /*!< (@ 0x400040B8) Global Boundary Select Register */
__I uint32_t RESERVED5[9];
__IO uint32_t GLOBEFLAG; /*!< (@ 0x400040E0) Global Event Flag Register */
__I uint32_t RESERVED6[23];
__IO uint32_t GLOBEVNP; /*!< (@ 0x40004140) Global Event Node Pointer Register */
__I uint32_t RESERVED7[7];
__IO uint32_t GLOBTF; /*!< (@ 0x40004160) Global Test Functions Register */
__I uint32_t RESERVED8[7];
__IO uint32_t BRSSEL[4]; /*!< (@ 0x40004180) Background Request Source Channel Select Register */
__I uint32_t RESERVED9[12];
__IO uint32_t BRSPND[4]; /*!< (@ 0x400041C0) Background Request Source Pending Register */
__I uint32_t RESERVED10[12];
__IO uint32_t BRSCTRL; /*!< (@ 0x40004200) Background Request Source Control Register */
__IO uint32_t BRSMR; /*!< (@ 0x40004204) Background Request Source Mode Register */
__I uint32_t RESERVED11[30];
__IO uint32_t GLOBRCR; /*!< (@ 0x40004280) Global Result Control Register */
__I uint32_t RESERVED12[31];
__IO uint32_t GLOBRES; /*!< (@ 0x40004300) Global Result Register */
__I uint32_t RESERVED13[31];
__IO uint32_t GLOBRESD; /*!< (@ 0x40004380) Global Result Register, Debug */
__I uint32_t RESERVED14[27];
__IO uint32_t EMUXSEL; /*!< (@ 0x400043F0) External Multiplexer Select Register */
} VADC_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ VADC_G [VADC_G0] ================ */
/* ================================================================================ */
/**
* @brief Analog to Digital Converter (VADC_G)
*/
typedef struct { /*!< (@ 0x40004400) VADC_G Structure */
__I uint32_t RESERVED0[32];
__IO uint32_t ARBCFG; /*!< (@ 0x40004480) Arbitration Configuration Register */
__IO uint32_t ARBPR; /*!< (@ 0x40004484) Arbitration Priority Register */
__IO uint32_t CHASS; /*!< (@ 0x40004488) Channel Assignment Register */
__I uint32_t RESERVED1[5];
__IO uint32_t ICLASS[2]; /*!< (@ 0x400044A0) Input Class Register */
__I uint32_t RESERVED2[2];
__IO uint32_t ALIAS; /*!< (@ 0x400044B0) Alias Register */
__I uint32_t RESERVED3;
__IO uint32_t BOUND; /*!< (@ 0x400044B8) Boundary Select Register */
__I uint32_t RESERVED4;
__IO uint32_t SYNCTR; /*!< (@ 0x400044C0) Synchronization Control Register */
__I uint32_t RESERVED5;
__IO uint32_t BFL; /*!< (@ 0x400044C8) Boundary Flag Register */
__I uint32_t RESERVED6[13];
__IO uint32_t QCTRL0; /*!< (@ 0x40004500) Queue 0 Source Control Register */
__IO uint32_t QMR0; /*!< (@ 0x40004504) Queue 0 Mode Register */
__I uint32_t QSR0; /*!< (@ 0x40004508) Queue 0 Status Register */
__I uint32_t Q0R0; /*!< (@ 0x4000450C) Queue 0 Register 0 */
union {
__I uint32_t QBUR0; /*!< (@ 0x40004510) Queue 0 Backup Register */
__O uint32_t QINR0; /*!< (@ 0x40004510) Queue 0 Input Register */
};
__I uint32_t RESERVED7[3];
__IO uint32_t ASCTRL; /*!< (@ 0x40004520) Autoscan Source Control Register */
__IO uint32_t ASMR; /*!< (@ 0x40004524) Autoscan Source Mode Register */
__IO uint32_t ASSEL; /*!< (@ 0x40004528) Autoscan Source Channel Select Register */
__IO uint32_t ASPND; /*!< (@ 0x4000452C) Autoscan Source Pending Register */
__I uint32_t RESERVED8[20];
__IO uint32_t CEFLAG; /*!< (@ 0x40004580) Channel Event Flag Register */
__IO uint32_t REFLAG; /*!< (@ 0x40004584) Result Event Flag Register */
__IO uint32_t SEFLAG; /*!< (@ 0x40004588) Source Event Flag Register */
__I uint32_t RESERVED9;
__O uint32_t CEFCLR; /*!< (@ 0x40004590) Channel Event Flag Clear Register */
__O uint32_t REFCLR; /*!< (@ 0x40004594) Result Event Flag Clear Register */
__O uint32_t SEFCLR; /*!< (@ 0x40004598) Source Event Flag Clear Register */
__I uint32_t RESERVED10;
__IO uint32_t CEVNP0; /*!< (@ 0x400045A0) Channel Event Node Pointer Register 0 */
__I uint32_t RESERVED11[3];
__IO uint32_t REVNP0; /*!< (@ 0x400045B0) Result Event Node Pointer Register 0 */
__IO uint32_t REVNP1; /*!< (@ 0x400045B4) Result Event Node Pointer Register 1 */
__I uint32_t RESERVED12[2];
__IO uint32_t SEVNP; /*!< (@ 0x400045C0) Source Event Node Pointer Register */
__I uint32_t RESERVED13;
__O uint32_t SRACT; /*!< (@ 0x400045C8) Service Request Software Activation Trigger */
__I uint32_t RESERVED14[9];
__IO uint32_t EMUXCTR; /*!< (@ 0x400045F0) E0ternal Multiplexer Control Register */
__I uint32_t RESERVED15;
__IO uint32_t VFR; /*!< (@ 0x400045F8) Valid Flag Register */
__I uint32_t RESERVED16;
__IO uint32_t CHCTR[8]; /*!< (@ 0x40004600) Channel Ctrl. Reg. */
__I uint32_t RESERVED17[24];
__IO uint32_t RCR[16]; /*!< (@ 0x40004680) Result Control Register */
__I uint32_t RESERVED18[16];
__IO uint32_t RES[16]; /*!< (@ 0x40004700) Result Register */
__I uint32_t RESERVED19[16];
__I uint32_t RESD[16]; /*!< (@ 0x40004780) Result Register, Debug */
} VADC_G_TypeDef;
/* ================================================================================ */
/* ================ DSD ================ */
/* ================================================================================ */
/**
* @brief Delta Sigma Demodulator (DSD)
*/
typedef struct { /*!< (@ 0x40008000) DSD Structure */
__IO uint32_t CLC; /*!< (@ 0x40008000) Clock Control Register */
__I uint32_t RESERVED0;
__I uint32_t ID; /*!< (@ 0x40008008) Module Identification Register */
__I uint32_t RESERVED1[7];
__IO uint32_t OCS; /*!< (@ 0x40008028) OCDS Control and Status Register */
__I uint32_t RESERVED2[21];
__IO uint32_t GLOBCFG; /*!< (@ 0x40008080) Global Configuration Register */
__I uint32_t RESERVED3;
__IO uint32_t GLOBRC; /*!< (@ 0x40008088) Global Run Control Register */
__I uint32_t RESERVED4[5];
__IO uint32_t CGCFG; /*!< (@ 0x400080A0) Carrier Generator Configuration Register */
__I uint32_t RESERVED5[15];
__IO uint32_t EVFLAG; /*!< (@ 0x400080E0) Event Flag Register */
__O uint32_t EVFLAGCLR; /*!< (@ 0x400080E4) Event Flag Clear Register */
} DSD_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ DSD_CH [DSD_CH0] ================ */
/* ================================================================================ */
/**
* @brief Delta Sigma Demodulator (DSD_CH)
*/
typedef struct { /*!< (@ 0x40008100) DSD_CH Structure */
__IO uint32_t MODCFG; /*!< (@ 0x40008100) Modulator Configuration Register */
__I uint32_t RESERVED0;
__IO uint32_t DICFG; /*!< (@ 0x40008108) Demodulator Input Configuration Register */
__I uint32_t RESERVED1[2];
__IO uint32_t FCFGC; /*!< (@ 0x40008114) Filter Configuration Register, Main CIC Filter */
__IO uint32_t FCFGA; /*!< (@ 0x40008118) Filter Configuration Register, Auxiliary Filter */
__I uint32_t RESERVED2;
__IO uint32_t IWCTR; /*!< (@ 0x40008120) Integration Window Control Register */
__I uint32_t RESERVED3;
__IO uint32_t BOUNDSEL; /*!< (@ 0x40008128) Boundary Select Register */
__I uint32_t RESERVED4;
__I uint32_t RESM; /*!< (@ 0x40008130) Result Register, Main Filter */
__I uint32_t RESERVED5;
__IO uint32_t OFFM; /*!< (@ 0x40008138) Offset Register, Main Filter */
__I uint32_t RESERVED6;
__I uint32_t RESA; /*!< (@ 0x40008140) Result Register, Auxiliary Filter */
__I uint32_t RESERVED7[3];
__I uint32_t TSTMP; /*!< (@ 0x40008150) Time-Stamp Register */
__I uint32_t RESERVED8[19];
__IO uint32_t CGSYNC; /*!< (@ 0x400081A0) Carrier Generator Synchronization Register */
__I uint32_t RESERVED9;
__IO uint32_t RECTCFG; /*!< (@ 0x400081A8) Rectification Configuration Register */
} DSD_CH_TypeDef;
/* ================================================================================ */
/* ================ DAC ================ */
/* ================================================================================ */
/**
* @brief Digital to Analog Converter (DAC)
*/
typedef struct { /*!< (@ 0x48018000) DAC Structure */
__I uint32_t ID; /*!< (@ 0x48018000) Module Identification Register */
__IO uint32_t DAC0CFG0; /*!< (@ 0x48018004) DAC0 Configuration Register 0 */
__IO uint32_t DAC0CFG1; /*!< (@ 0x48018008) DAC0 Configuration Register 1 */
__IO uint32_t DAC1CFG0; /*!< (@ 0x4801800C) DAC1 Configuration Register 0 */
__IO uint32_t DAC1CFG1; /*!< (@ 0x48018010) DAC1 Configuration Register 1 */
__IO uint32_t DAC0DATA; /*!< (@ 0x48018014) DAC0 Data Register */
__IO uint32_t DAC1DATA; /*!< (@ 0x48018018) DAC1 Data Register */
__IO uint32_t DAC01DATA; /*!< (@ 0x4801801C) DAC01 Data Register */
__IO uint32_t DAC0PATL; /*!< (@ 0x48018020) DAC0 Lower Pattern Register */
__IO uint32_t DAC0PATH; /*!< (@ 0x48018024) DAC0 Higher Pattern Register */
__IO uint32_t DAC1PATL; /*!< (@ 0x48018028) DAC1 Lower Pattern Register */
__IO uint32_t DAC1PATH; /*!< (@ 0x4801802C) DAC1 Higher Pattern Register */
} DAC_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ CCU4 [CCU40] ================ */
/* ================================================================================ */
/**
* @brief Capture Compare Unit 4 - Unit 0 (CCU4)
*/
typedef struct { /*!< (@ 0x4000C000) CCU4 Structure */
__IO uint32_t GCTRL; /*!< (@ 0x4000C000) Global Control Register */
__I uint32_t GSTAT; /*!< (@ 0x4000C004) Global Status Register */
__O uint32_t GIDLS; /*!< (@ 0x4000C008) Global Idle Set */
__O uint32_t GIDLC; /*!< (@ 0x4000C00C) Global Idle Clear */
__O uint32_t GCSS; /*!< (@ 0x4000C010) Global Channel Set */
__O uint32_t GCSC; /*!< (@ 0x4000C014) Global Channel Clear */
__I uint32_t GCST; /*!< (@ 0x4000C018) Global Channel Status */
__I uint32_t RESERVED0[13];
__I uint32_t ECRD; /*!< (@ 0x4000C050) Extended Capture Mode Read */
__I uint32_t RESERVED1[11];
__I uint32_t MIDR; /*!< (@ 0x4000C080) Module Identification */
} CCU4_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ CCU4_CC4 [CCU40_CC40] ================ */
/* ================================================================================ */
/**
* @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4)
*/
typedef struct { /*!< (@ 0x4000C100) CCU4_CC4 Structure */
__IO uint32_t INS; /*!< (@ 0x4000C100) Input Selector Configuration */
__IO uint32_t CMC; /*!< (@ 0x4000C104) Connection Matrix Control */
__I uint32_t TCST; /*!< (@ 0x4000C108) Slice Timer Status */
__O uint32_t TCSET; /*!< (@ 0x4000C10C) Slice Timer Run Set */
__O uint32_t TCCLR; /*!< (@ 0x4000C110) Slice Timer Clear */
__IO uint32_t TC; /*!< (@ 0x4000C114) Slice Timer Control */
__IO uint32_t PSL; /*!< (@ 0x4000C118) Passive Level Config */
__I uint32_t DIT; /*!< (@ 0x4000C11C) Dither Config */
__IO uint32_t DITS; /*!< (@ 0x4000C120) Dither Shadow Register */
__IO uint32_t PSC; /*!< (@ 0x4000C124) Prescaler Control */
__IO uint32_t FPC; /*!< (@ 0x4000C128) Floating Prescaler Control */
__IO uint32_t FPCS; /*!< (@ 0x4000C12C) Floating Prescaler Shadow */
__I uint32_t PR; /*!< (@ 0x4000C130) Timer Period Value */
__IO uint32_t PRS; /*!< (@ 0x4000C134) Timer Shadow Period Value */
__I uint32_t CR; /*!< (@ 0x4000C138) Timer Compare Value */
__IO uint32_t CRS; /*!< (@ 0x4000C13C) Timer Shadow Compare Value */
__I uint32_t RESERVED0[12];
__IO uint32_t TIMER; /*!< (@ 0x4000C170) Timer Value */
__I uint32_t CV[4]; /*!< (@ 0x4000C174) Capture Register 0 */
__I uint32_t RESERVED1[7];
__I uint32_t INTS; /*!< (@ 0x4000C1A0) Interrupt Status */
__IO uint32_t INTE; /*!< (@ 0x4000C1A4) Interrupt Enable Control */
__IO uint32_t SRS; /*!< (@ 0x4000C1A8) Service Request Selector */
__O uint32_t SWS; /*!< (@ 0x4000C1AC) Interrupt Status Set */
__O uint32_t SWR; /*!< (@ 0x4000C1B0) Interrupt Status Clear */
} CCU4_CC4_TypeDef;
/* ================================================================================ */
/* ================ CCU8 [CCU80] ================ */
/* ================================================================================ */
/**
* @brief Capture Compare Unit 8 - Unit 0 (CCU8)
*/
typedef struct { /*!< (@ 0x40020000) CCU8 Structure */
__IO uint32_t GCTRL; /*!< (@ 0x40020000) Global Control Register */
__I uint32_t GSTAT; /*!< (@ 0x40020004) Global Status Register */
__O uint32_t GIDLS; /*!< (@ 0x40020008) Global Idle Set */
__O uint32_t GIDLC; /*!< (@ 0x4002000C) Global Idle Clear */
__O uint32_t GCSS; /*!< (@ 0x40020010) Global Channel Set */
__O uint32_t GCSC; /*!< (@ 0x40020014) Global Channel Clear */
__I uint32_t GCST; /*!< (@ 0x40020018) Global Channel status */
__IO uint32_t GPCHK; /*!< (@ 0x4002001C) Parity Checker Configuration */
__I uint32_t RESERVED0[12];
__I uint32_t ECRD; /*!< (@ 0x40020050) Extended Capture Mode Read */
__I uint32_t RESERVED1[11];
__I uint32_t MIDR; /*!< (@ 0x40020080) Module Identification */
} CCU8_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ CCU8_CC8 [CCU80_CC80] ================ */
/* ================================================================================ */
/**
* @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8)
*/
typedef struct { /*!< (@ 0x40020100) CCU8_CC8 Structure */
__IO uint32_t INS; /*!< (@ 0x40020100) Input Selector Configuration */
__IO uint32_t CMC; /*!< (@ 0x40020104) Connection Matrix Control */
__I uint32_t TCST; /*!< (@ 0x40020108) Slice Timer Status */
__O uint32_t TCSET; /*!< (@ 0x4002010C) Slice Timer Run Set */
__O uint32_t TCCLR; /*!< (@ 0x40020110) Slice Timer Clear */
__IO uint32_t TC; /*!< (@ 0x40020114) Slice Timer Control */
__IO uint32_t PSL; /*!< (@ 0x40020118) Passive Level Config */
__I uint32_t DIT; /*!< (@ 0x4002011C) Dither Config */
__IO uint32_t DITS; /*!< (@ 0x40020120) Dither Shadow Register */
__IO uint32_t PSC; /*!< (@ 0x40020124) Prescaler Control */
__IO uint32_t FPC; /*!< (@ 0x40020128) Floating Prescaler Control */
__IO uint32_t FPCS; /*!< (@ 0x4002012C) Floating Prescaler Shadow */
__I uint32_t PR; /*!< (@ 0x40020130) Timer Period Value */
__IO uint32_t PRS; /*!< (@ 0x40020134) Timer Shadow Period Value */
__I uint32_t CR1; /*!< (@ 0x40020138) Channel 1 Compare Value */
__IO uint32_t CR1S; /*!< (@ 0x4002013C) Channel 1 Compare Shadow Value */
__I uint32_t CR2; /*!< (@ 0x40020140) Channel 2 Compare Value */
__IO uint32_t CR2S; /*!< (@ 0x40020144) Channel 2 Compare Shadow Value */
__IO uint32_t CHC; /*!< (@ 0x40020148) Channel Control */
__IO uint32_t DTC; /*!< (@ 0x4002014C) Dead Time Control */
__IO uint32_t DC1R; /*!< (@ 0x40020150) Channel 1 Dead Time Values */
__IO uint32_t DC2R; /*!< (@ 0x40020154) Channel 2 Dead Time Values */
__I uint32_t RESERVED0[6];
__IO uint32_t TIMER; /*!< (@ 0x40020170) Timer Value */
__I uint32_t CV[4]; /*!< (@ 0x40020174) Capture Register 0 */
__I uint32_t RESERVED1[7];
__I uint32_t INTS; /*!< (@ 0x400201A0) Interrupt Status */
__IO uint32_t INTE; /*!< (@ 0x400201A4) Interrupt Enable Control */
__IO uint32_t SRS; /*!< (@ 0x400201A8) Service Request Selector */
__O uint32_t SWS; /*!< (@ 0x400201AC) Interrupt Status Set */
__O uint32_t SWR; /*!< (@ 0x400201B0) Interrupt Status Clear */
} CCU8_CC8_TypeDef;
/* ================================================================================ */
/* ================ HRPWM0 ================ */
/* ================================================================================ */
/**
* @brief High Resolution PWM Unit (HRPWM0)
*/
typedef struct { /*!< (@ 0x40020900) HRPWM0 Structure */
__IO uint32_t HRBSC; /*!< (@ 0x40020900) Bias and suspend configuration */
__I uint32_t RESERVED0;
__I uint32_t MIDR; /*!< (@ 0x40020908) Module identification register */
__I uint32_t RESERVED1[2];
__IO uint32_t GLBANA; /*!< (@ 0x40020914) Global Analog Configuration */
__I uint32_t RESERVED2[2];
__IO uint32_t CSGCFG; /*!< (@ 0x40020920) Global CSG configuration */
__O uint32_t CSGSETG; /*!< (@ 0x40020924) Global CSG run bit set */
__O uint32_t CSGCLRG; /*!< (@ 0x40020928) Global CSG run bit clear */
__I uint32_t CSGSTATG; /*!< (@ 0x4002092C) Global CSG run bit status */
__O uint32_t CSGFCG; /*!< (@ 0x40020930) Global CSG slope/prescaler control */
__I uint32_t CSGFSG; /*!< (@ 0x40020934) Global CSG slope/prescaler status */
__O uint32_t CSGTRG; /*!< (@ 0x40020938) Global CSG shadow/switch trigger */
__O uint32_t CSGTRC; /*!< (@ 0x4002093C) Global CSG shadow trigger clear */
__I uint32_t CSGTRSG; /*!< (@ 0x40020940) Global CSG shadow/switch status */
__I uint32_t RESERVED3[7];
__IO uint32_t HRCCFG; /*!< (@ 0x40020960) Global HRC configuration */
__O uint32_t HRCSTRG; /*!< (@ 0x40020964) Global HRC shadow trigger set */
__O uint32_t HRCCTRG; /*!< (@ 0x40020968) Global HRC shadow trigger clear */
__I uint32_t HRCSTSG; /*!< (@ 0x4002096C) Global HRC shadow transfer status */
__I uint32_t HRGHRS; /*!< (@ 0x40020970) High Resolution Generation Status */
} HRPWM0_Type;
/* ================================================================================ */
/* ================ HRPWM0_CSG [HRPWM0_CSG0] ================ */
/* ================================================================================ */
/**
* @brief High Resolution PWM Unit (HRPWM0_CSG)
*/
typedef struct { /*!< (@ 0x40020A00) HRPWM0_CSG Structure */
__IO uint32_t DCI; /*!< (@ 0x40020A00) External input selection */
__IO uint32_t IES; /*!< (@ 0x40020A04) External input selection */
__IO uint32_t SC; /*!< (@ 0x40020A08) Slope generation control */
__I uint32_t PC; /*!< (@ 0x40020A0C) Pulse swallow configuration */
__I uint32_t DSV1; /*!< (@ 0x40020A10) DAC reference value 1 */
__IO uint32_t DSV2; /*!< (@ 0x40020A14) DAC reference value 1 */
__IO uint32_t SDSV1; /*!< (@ 0x40020A18) Shadow reference value 1 */
__IO uint32_t SPC; /*!< (@ 0x40020A1C) Shadow Pulse swallow value */
__IO uint32_t CC; /*!< (@ 0x40020A20) Comparator configuration */
__IO uint32_t PLC; /*!< (@ 0x40020A24) Passive level configuration */
__IO uint32_t BLV; /*!< (@ 0x40020A28) Comparator blanking value */
__IO uint32_t SRE; /*!< (@ 0x40020A2C) Service request enable */
__IO uint32_t SRS; /*!< (@ 0x40020A30) Service request line selector */
__O uint32_t SWS; /*!< (@ 0x40020A34) Service request SW set */
__O uint32_t SWC; /*!< (@ 0x40020A38) Service request SW clear */
__I uint32_t ISTAT; /*!< (@ 0x40020A3C) Service request status */
} HRPWM0_CSG_Type;
/* ================================================================================ */
/* ================ HRPWM0_HRC [HRPWM0_HRC0] ================ */
/* ================================================================================ */
/**
* @brief High Resolution PWM Unit (HRPWM0_HRC)
*/
typedef struct { /*!< (@ 0x40021300) HRPWM0_HRC Structure */
__IO uint32_t GC; /*!< (@ 0x40021300) HRC mode configuration */
__IO uint32_t PL; /*!< (@ 0x40021304) HRC output passive level */
__IO uint32_t GSEL; /*!< (@ 0x40021308) HRC global control selection */
__IO uint32_t TSEL; /*!< (@ 0x4002130C) HRC timer selection */
__I uint32_t SC; /*!< (@ 0x40021310) HRC current source for shadow */
__I uint32_t DCR; /*!< (@ 0x40021314) HRC dead time rising value */
__I uint32_t DCF; /*!< (@ 0x40021318) HRC dead time falling value */
__I uint32_t CR1; /*!< (@ 0x4002131C) HRC rising edge value */
__I uint32_t CR2; /*!< (@ 0x40021320) HRC falling edge value */
__IO uint32_t SSC; /*!< (@ 0x40021324) HRC next source for shadow */
__IO uint32_t SDCR; /*!< (@ 0x40021328) HRC shadow dead time rising */
__IO uint32_t SDCF; /*!< (@ 0x4002132C) HRC shadow dead time falling */
__IO uint32_t SCR1; /*!< (@ 0x40021330) HRC shadow rising edge value */
__IO uint32_t SCR2; /*!< (@ 0x40021334) HRC shadow falling edge value */
} HRPWM0_HRC_Type;
/* ================================================================================ */
/* ================ POSIF [POSIF0] ================ */
/* ================================================================================ */
/**
* @brief Position Interface 0 (POSIF)
*/
typedef struct { /*!< (@ 0x40028000) POSIF Structure */
__IO uint32_t PCONF; /*!< (@ 0x40028000) Service Request Processing configuration */
__IO uint32_t PSUS; /*!< (@ 0x40028004) Service Request Processing Suspend Config */
__O uint32_t PRUNS; /*!< (@ 0x40028008) Service Request Processing Run Bit Set */
__O uint32_t PRUNC; /*!< (@ 0x4002800C) Service Request Processing Run Bit Clear */
__I uint32_t PRUN; /*!< (@ 0x40028010) Service Request Processing Run Bit Status */
__I uint32_t RESERVED0[3];
__I uint32_t MIDR; /*!< (@ 0x40028020) Module Identification register */
__I uint32_t RESERVED1[3];
__I uint32_t HALP; /*!< (@ 0x40028030) Hall Sensor Patterns */
__IO uint32_t HALPS; /*!< (@ 0x40028034) Hall Sensor Shadow Patterns */
__I uint32_t RESERVED2[2];
__I uint32_t MCM; /*!< (@ 0x40028040) Multi-Channel Pattern */
__IO uint32_t MCSM; /*!< (@ 0x40028044) Multi-Channel Shadow Pattern */
__O uint32_t MCMS; /*!< (@ 0x40028048) Multi-Channel Pattern Control set */
__O uint32_t MCMC; /*!< (@ 0x4002804C) Multi-Channel Pattern Control clear */
__I uint32_t MCMF; /*!< (@ 0x40028050) Multi-Channel Pattern Control flag */
__I uint32_t RESERVED3[3];
__IO uint32_t QDC; /*!< (@ 0x40028060) Quadrature Decoder Control */
__I uint32_t RESERVED4[3];
__I uint32_t PFLG; /*!< (@ 0x40028070) Service Request Processing Interrupt Flags */
__IO uint32_t PFLGE; /*!< (@ 0x40028074) Service Request Processing Interrupt Enable */
__O uint32_t SPFLG; /*!< (@ 0x40028078) Service Request Processing Interrupt Set */
__O uint32_t RPFLG; /*!< (@ 0x4002807C) Service Request Processing Interrupt Clear */
__I uint32_t RESERVED5[32];
__I uint32_t PDBG; /*!< (@ 0x40028100) POSIF Debug register */
} POSIF_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ PORT0 ================ */
/* ================================================================================ */
/**
* @brief Port 0 (PORT0)
*/
typedef struct { /*!< (@ 0x48028000) PORT0 Structure */
__IO uint32_t OUT; /*!< (@ 0x48028000) Port 0 Output Register */
__O uint32_t OMR; /*!< (@ 0x48028004) Port 0 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x48028010) Port 0 Input/Output Control Register 0 */
__IO uint32_t IOCR4; /*!< (@ 0x48028014) Port 0 Input/Output Control Register 4 */
__IO uint32_t IOCR8; /*!< (@ 0x48028018) Port 0 Input/Output Control Register 8 */
__IO uint32_t IOCR12; /*!< (@ 0x4802801C) Port 0 Input/Output Control Register 12 */
__I uint32_t RESERVED1;
__I uint32_t IN; /*!< (@ 0x48028024) Port 0 Input Register */
__I uint32_t RESERVED2[6];
__IO uint32_t PDR0; /*!< (@ 0x48028040) Port 0 Pad Driver Mode 0 Register */
__IO uint32_t PDR1; /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Register */
__I uint32_t RESERVED3[6];
__I uint32_t PDISC; /*!< (@ 0x48028060) Port 0 Pin Function Decision Control Register */
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /*!< (@ 0x48028070) Port 0 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x48028074) Port 0 Pin Hardware Select Register */
} PORT0_Type;
/* ================================================================================ */
/* ================ PORT1 ================ */
/* ================================================================================ */
/**
* @brief Port 1 (PORT1)
*/
typedef struct { /*!< (@ 0x48028100) PORT1 Structure */
__IO uint32_t OUT; /*!< (@ 0x48028100) Port 1 Output Register */
__O uint32_t OMR; /*!< (@ 0x48028104) Port 1 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x48028110) Port 1 Input/Output Control Register 0 */
__IO uint32_t IOCR4; /*!< (@ 0x48028114) Port 1 Input/Output Control Register 4 */
__IO uint32_t IOCR8; /*!< (@ 0x48028118) Port 1 Input/Output Control Register 8 */
__IO uint32_t IOCR12; /*!< (@ 0x4802811C) Port 1 Input/Output Control Register 12 */
__I uint32_t RESERVED1;
__I uint32_t IN; /*!< (@ 0x48028124) Port 1 Input Register */
__I uint32_t RESERVED2[6];
__IO uint32_t PDR0; /*!< (@ 0x48028140) Port 1 Pad Driver Mode 0 Register */
__IO uint32_t PDR1; /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Register */
__I uint32_t RESERVED3[6];
__I uint32_t PDISC; /*!< (@ 0x48028160) Port 1 Pin Function Decision Control Register */
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /*!< (@ 0x48028170) Port 1 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x48028174) Port 1 Pin Hardware Select Register */
} PORT1_Type;
/* ================================================================================ */
/* ================ PORT2 ================ */
/* ================================================================================ */
/**
* @brief Port 2 (PORT2)
*/
typedef struct { /*!< (@ 0x48028200) PORT2 Structure */
__IO uint32_t OUT; /*!< (@ 0x48028200) Port 2 Output Register */
__O uint32_t OMR; /*!< (@ 0x48028204) Port 2 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x48028210) Port 2 Input/Output Control Register 0 */
__IO uint32_t IOCR4; /*!< (@ 0x48028214) Port 2 Input/Output Control Register 4 */
__IO uint32_t IOCR8; /*!< (@ 0x48028218) Port 2 Input/Output Control Register 8 */
__IO uint32_t IOCR12; /*!< (@ 0x4802821C) Port 2 Input/Output Control Register 12 */
__I uint32_t RESERVED1;
__I uint32_t IN; /*!< (@ 0x48028224) Port 2 Input Register */
__I uint32_t RESERVED2[6];
__IO uint32_t PDR0; /*!< (@ 0x48028240) Port 2 Pad Driver Mode 0 Register */
__IO uint32_t PDR1; /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Register */
__I uint32_t RESERVED3[6];
__I uint32_t PDISC; /*!< (@ 0x48028260) Port 2 Pin Function Decision Control Register */
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /*!< (@ 0x48028270) Port 2 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x48028274) Port 2 Pin Hardware Select Register */
} PORT2_Type;
/* ================================================================================ */
/* ================ PORT3 ================ */
/* ================================================================================ */
/**
* @brief Port 3 (PORT3)
*/
typedef struct { /*!< (@ 0x48028300) PORT3 Structure */
__IO uint32_t OUT; /*!< (@ 0x48028300) Port 3 Output Register */
__O uint32_t OMR; /*!< (@ 0x48028304) Port 3 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x48028310) Port 3 Input/Output Control Register 0 */
__IO uint32_t IOCR4; /*!< (@ 0x48028314) Port 3 Input/Output Control Register 4 */
__I uint32_t RESERVED1[3];
__I uint32_t IN; /*!< (@ 0x48028324) Port 3 Input Register */
__I uint32_t RESERVED2[6];
__IO uint32_t PDR0; /*!< (@ 0x48028340) Port 3 Pad Driver Mode 0 Register */
__I uint32_t RESERVED3[7];
__I uint32_t PDISC; /*!< (@ 0x48028360) Port 3 Pin Function Decision Control Register */
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /*!< (@ 0x48028370) Port 3 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x48028374) Port 3 Pin Hardware Select Register */
} PORT3_Type;
/* ================================================================================ */
/* ================ PORT4 ================ */
/* ================================================================================ */
/**
* @brief Port 4 (PORT4)
*/
typedef struct { /*!< (@ 0x48028400) PORT4 Structure */
__IO uint32_t OUT; /*!< (@ 0x48028400) Port 4 Output Register */
__O uint32_t OMR; /*!< (@ 0x48028404) Port 4 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x48028410) Port 4 Input/Output Control Register 0 */
__I uint32_t RESERVED1[4];
__I uint32_t IN; /*!< (@ 0x48028424) Port 4 Input Register */
__I uint32_t RESERVED2[6];
__IO uint32_t PDR0; /*!< (@ 0x48028440) Port 4 Pad Driver Mode 0 Register */
__I uint32_t RESERVED3[7];
__I uint32_t PDISC; /*!< (@ 0x48028460) Port 4 Pin Function Decision Control Register */
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /*!< (@ 0x48028470) Port 4 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x48028474) Port 4 Pin Hardware Select Register */
} PORT4_Type;
/* ================================================================================ */
/* ================ PORT5 ================ */
/* ================================================================================ */
/**
* @brief Port 5 (PORT5)
*/
typedef struct { /*!< (@ 0x48028500) PORT5 Structure */
__IO uint32_t OUT; /*!< (@ 0x48028500) Port 5 Output Register */
__O uint32_t OMR; /*!< (@ 0x48028504) Port 5 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x48028510) Port 5 Input/Output Control Register 0 */
__IO uint32_t IOCR4; /*!< (@ 0x48028514) Port 5 Input/Output Control Register 4 */
__I uint32_t RESERVED1[3];
__I uint32_t IN; /*!< (@ 0x48028524) Port 5 Input Register */
__I uint32_t RESERVED2[6];
__IO uint32_t PDR0; /*!< (@ 0x48028540) Port 5 Pad Driver Mode 0 Register */
__I uint32_t RESERVED3[7];
__I uint32_t PDISC; /*!< (@ 0x48028560) Port 5 Pin Function Decision Control Register */
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /*!< (@ 0x48028570) Port 5 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x48028574) Port 5 Pin Hardware Select Register */
} PORT5_Type;
/* ================================================================================ */
/* ================ PORT14 ================ */
/* ================================================================================ */
/**
* @brief Port 14 (PORT14)
*/
typedef struct { /*!< (@ 0x48028E00) PORT14 Structure */
__IO uint32_t OUT; /*!< (@ 0x48028E00) Port 14 Output Register */
__O uint32_t OMR; /*!< (@ 0x48028E04) Port 14 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x48028E10) Port 14 Input/Output Control Register 0 */
__IO uint32_t IOCR4; /*!< (@ 0x48028E14) Port 14 Input/Output Control Register 4 */
__IO uint32_t IOCR8; /*!< (@ 0x48028E18) Port 14 Input/Output Control Register 8 */
__IO uint32_t IOCR12; /*!< (@ 0x48028E1C) Port 14 Input/Output Control Register 12 */
__I uint32_t RESERVED1;
__I uint32_t IN; /*!< (@ 0x48028E24) Port 14 Input Register */
__I uint32_t RESERVED2[14];
__IO uint32_t PDISC; /*!< (@ 0x48028E60) Port 14 Pin Function Decision Control Register */
__I uint32_t RESERVED3[3];
__IO uint32_t PPS; /*!< (@ 0x48028E70) Port 14 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x48028E74) Port 14 Pin Hardware Select Register */
} PORT14_Type;
/* ================================================================================ */
/* ================ PORT15 ================ */
/* ================================================================================ */
/**
* @brief Port 15 (PORT15)
*/
typedef struct { /*!< (@ 0x48028F00) PORT15 Structure */
__IO uint32_t OUT; /*!< (@ 0x48028F00) Port 15 Output Register */
__O uint32_t OMR; /*!< (@ 0x48028F04) Port 15 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x48028F10) Port 15 Input/Output Control Register 0 */
__IO uint32_t IOCR4; /*!< (@ 0x48028F14) Port 15 Input/Output Control Register 4 */
__IO uint32_t IOCR8; /*!< (@ 0x48028F18) Port 15 Input/Output Control Register 8 */
__I uint32_t RESERVED1[2];
__I uint32_t IN; /*!< (@ 0x48028F24) Port 15 Input Register */
__I uint32_t RESERVED2[14];
__IO uint32_t PDISC; /*!< (@ 0x48028F60) Port 15 Pin Function Decision Control Register */
__I uint32_t RESERVED3[3];
__IO uint32_t PPS; /*!< (@ 0x48028F70) Port 15 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x48028F74) Port 15 Pin Hardware Select Register */
} PORT15_Type;
/* -------------------- End of section using anonymous unions ------------------- */
#if defined(__CC_ARM)
#pragma pop
#elif defined(__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning restore
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ struct 'PPB' Position & Mask ================ */
/* ================================================================================ */
/* ---------------------------------- PPB_ACTLR --------------------------------- */
#define PPB_ACTLR_DISMCYCINT_Pos 0 /*!< PPB ACTLR: DISMCYCINT Position */
#define PPB_ACTLR_DISMCYCINT_Msk (0x01UL << PPB_ACTLR_DISMCYCINT_Pos) /*!< PPB ACTLR: DISMCYCINT Mask */
#define PPB_ACTLR_DISDEFWBUF_Pos 1 /*!< PPB ACTLR: DISDEFWBUF Position */
#define PPB_ACTLR_DISDEFWBUF_Msk (0x01UL << PPB_ACTLR_DISDEFWBUF_Pos) /*!< PPB ACTLR: DISDEFWBUF Mask */
#define PPB_ACTLR_DISFOLD_Pos 2 /*!< PPB ACTLR: DISFOLD Position */
#define PPB_ACTLR_DISFOLD_Msk (0x01UL << PPB_ACTLR_DISFOLD_Pos) /*!< PPB ACTLR: DISFOLD Mask */
#define PPB_ACTLR_DISFPCA_Pos 8 /*!< PPB ACTLR: DISFPCA Position */
#define PPB_ACTLR_DISFPCA_Msk (0x01UL << PPB_ACTLR_DISFPCA_Pos) /*!< PPB ACTLR: DISFPCA Mask */
#define PPB_ACTLR_DISOOFP_Pos 9 /*!< PPB ACTLR: DISOOFP Position */
#define PPB_ACTLR_DISOOFP_Msk (0x01UL << PPB_ACTLR_DISOOFP_Pos) /*!< PPB ACTLR: DISOOFP Mask */
/* -------------------------------- PPB_SYST_CSR -------------------------------- */
#define PPB_SYST_CSR_ENABLE_Pos 0 /*!< PPB SYST_CSR: ENABLE Position */
#define PPB_SYST_CSR_ENABLE_Msk (0x01UL << PPB_SYST_CSR_ENABLE_Pos) /*!< PPB SYST_CSR: ENABLE Mask */
#define PPB_SYST_CSR_TICKINT_Pos 1 /*!< PPB SYST_CSR: TICKINT Position */
#define PPB_SYST_CSR_TICKINT_Msk (0x01UL << PPB_SYST_CSR_TICKINT_Pos) /*!< PPB SYST_CSR: TICKINT Mask */
#define PPB_SYST_CSR_CLKSOURCE_Pos 2 /*!< PPB SYST_CSR: CLKSOURCE Position */
#define PPB_SYST_CSR_CLKSOURCE_Msk (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos) /*!< PPB SYST_CSR: CLKSOURCE Mask */
#define PPB_SYST_CSR_COUNTFLAG_Pos 16 /*!< PPB SYST_CSR: COUNTFLAG Position */
#define PPB_SYST_CSR_COUNTFLAG_Msk (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos) /*!< PPB SYST_CSR: COUNTFLAG Mask */
/* -------------------------------- PPB_SYST_RVR -------------------------------- */
#define PPB_SYST_RVR_RELOAD_Pos 0 /*!< PPB SYST_RVR: RELOAD Position */
#define PPB_SYST_RVR_RELOAD_Msk (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos) /*!< PPB SYST_RVR: RELOAD Mask */
/* -------------------------------- PPB_SYST_CVR -------------------------------- */
#define PPB_SYST_CVR_CURRENT_Pos 0 /*!< PPB SYST_CVR: CURRENT Position */
#define PPB_SYST_CVR_CURRENT_Msk (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos) /*!< PPB SYST_CVR: CURRENT Mask */
/* ------------------------------- PPB_SYST_CALIB ------------------------------- */
#define PPB_SYST_CALIB_TENMS_Pos 0 /*!< PPB SYST_CALIB: TENMS Position */
#define PPB_SYST_CALIB_TENMS_Msk (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos) /*!< PPB SYST_CALIB: TENMS Mask */
#define PPB_SYST_CALIB_SKEW_Pos 30 /*!< PPB SYST_CALIB: SKEW Position */
#define PPB_SYST_CALIB_SKEW_Msk (0x01UL << PPB_SYST_CALIB_SKEW_Pos) /*!< PPB SYST_CALIB: SKEW Mask */
#define PPB_SYST_CALIB_NOREF_Pos 31 /*!< PPB SYST_CALIB: NOREF Position */
#define PPB_SYST_CALIB_NOREF_Msk (0x01UL << PPB_SYST_CALIB_NOREF_Pos) /*!< PPB SYST_CALIB: NOREF Mask */
/* ------------------------------- PPB_NVIC_ISER0 ------------------------------- */
#define PPB_NVIC_ISER0_SETENA_Pos 0 /*!< PPB NVIC_ISER0: SETENA Position */
#define PPB_NVIC_ISER0_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER0_SETENA_Pos) /*!< PPB NVIC_ISER0: SETENA Mask */
/* ------------------------------- PPB_NVIC_ISER1 ------------------------------- */
#define PPB_NVIC_ISER1_SETENA_Pos 0 /*!< PPB NVIC_ISER1: SETENA Position */
#define PPB_NVIC_ISER1_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER1_SETENA_Pos) /*!< PPB NVIC_ISER1: SETENA Mask */
/* ------------------------------- PPB_NVIC_ISER2 ------------------------------- */
#define PPB_NVIC_ISER2_SETENA_Pos 0 /*!< PPB NVIC_ISER2: SETENA Position */
#define PPB_NVIC_ISER2_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER2_SETENA_Pos) /*!< PPB NVIC_ISER2: SETENA Mask */
/* ------------------------------- PPB_NVIC_ISER3 ------------------------------- */
#define PPB_NVIC_ISER3_SETENA_Pos 0 /*!< PPB NVIC_ISER3: SETENA Position */
#define PPB_NVIC_ISER3_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER3_SETENA_Pos) /*!< PPB NVIC_ISER3: SETENA Mask */
/* ------------------------------- PPB_NVIC_ICER0 ------------------------------- */
#define PPB_NVIC_ICER0_CLRENA_Pos 0 /*!< PPB NVIC_ICER0: CLRENA Position */
#define PPB_NVIC_ICER0_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER0_CLRENA_Pos) /*!< PPB NVIC_ICER0: CLRENA Mask */
/* ------------------------------- PPB_NVIC_ICER1 ------------------------------- */
#define PPB_NVIC_ICER1_CLRENA_Pos 0 /*!< PPB NVIC_ICER1: CLRENA Position */
#define PPB_NVIC_ICER1_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER1_CLRENA_Pos) /*!< PPB NVIC_ICER1: CLRENA Mask */
/* ------------------------------- PPB_NVIC_ICER2 ------------------------------- */
#define PPB_NVIC_ICER2_CLRENA_Pos 0 /*!< PPB NVIC_ICER2: CLRENA Position */
#define PPB_NVIC_ICER2_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER2_CLRENA_Pos) /*!< PPB NVIC_ICER2: CLRENA Mask */
/* ------------------------------- PPB_NVIC_ICER3 ------------------------------- */
#define PPB_NVIC_ICER3_CLRENA_Pos 0 /*!< PPB NVIC_ICER3: CLRENA Position */
#define PPB_NVIC_ICER3_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER3_CLRENA_Pos) /*!< PPB NVIC_ICER3: CLRENA Mask */
/* ------------------------------- PPB_NVIC_ISPR0 ------------------------------- */
#define PPB_NVIC_ISPR0_SETPEND_Pos 0 /*!< PPB NVIC_ISPR0: SETPEND Position */
#define PPB_NVIC_ISPR0_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR0_SETPEND_Pos) /*!< PPB NVIC_ISPR0: SETPEND Mask */
/* ------------------------------- PPB_NVIC_ISPR1 ------------------------------- */
#define PPB_NVIC_ISPR1_SETPEND_Pos 0 /*!< PPB NVIC_ISPR1: SETPEND Position */
#define PPB_NVIC_ISPR1_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR1_SETPEND_Pos) /*!< PPB NVIC_ISPR1: SETPEND Mask */
/* ------------------------------- PPB_NVIC_ISPR2 ------------------------------- */
#define PPB_NVIC_ISPR2_SETPEND_Pos 0 /*!< PPB NVIC_ISPR2: SETPEND Position */
#define PPB_NVIC_ISPR2_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR2_SETPEND_Pos) /*!< PPB NVIC_ISPR2: SETPEND Mask */
/* ------------------------------- PPB_NVIC_ISPR3 ------------------------------- */
#define PPB_NVIC_ISPR3_SETPEND_Pos 0 /*!< PPB NVIC_ISPR3: SETPEND Position */
#define PPB_NVIC_ISPR3_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR3_SETPEND_Pos) /*!< PPB NVIC_ISPR3: SETPEND Mask */
/* ------------------------------- PPB_NVIC_ICPR0 ------------------------------- */
#define PPB_NVIC_ICPR0_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR0: CLRPEND Position */
#define PPB_NVIC_ICPR0_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR0_CLRPEND_Pos) /*!< PPB NVIC_ICPR0: CLRPEND Mask */
/* ------------------------------- PPB_NVIC_ICPR1 ------------------------------- */
#define PPB_NVIC_ICPR1_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR1: CLRPEND Position */
#define PPB_NVIC_ICPR1_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR1_CLRPEND_Pos) /*!< PPB NVIC_ICPR1: CLRPEND Mask */
/* ------------------------------- PPB_NVIC_ICPR2 ------------------------------- */
#define PPB_NVIC_ICPR2_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR2: CLRPEND Position */
#define PPB_NVIC_ICPR2_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR2_CLRPEND_Pos) /*!< PPB NVIC_ICPR2: CLRPEND Mask */
/* ------------------------------- PPB_NVIC_ICPR3 ------------------------------- */
#define PPB_NVIC_ICPR3_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR3: CLRPEND Position */
#define PPB_NVIC_ICPR3_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR3_CLRPEND_Pos) /*!< PPB NVIC_ICPR3: CLRPEND Mask */
/* ------------------------------- PPB_NVIC_IABR0 ------------------------------- */
#define PPB_NVIC_IABR0_ACTIVE_Pos 0 /*!< PPB NVIC_IABR0: ACTIVE Position */
#define PPB_NVIC_IABR0_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR0_ACTIVE_Pos) /*!< PPB NVIC_IABR0: ACTIVE Mask */
/* ------------------------------- PPB_NVIC_IABR1 ------------------------------- */
#define PPB_NVIC_IABR1_ACTIVE_Pos 0 /*!< PPB NVIC_IABR1: ACTIVE Position */
#define PPB_NVIC_IABR1_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR1_ACTIVE_Pos) /*!< PPB NVIC_IABR1: ACTIVE Mask */
/* ------------------------------- PPB_NVIC_IABR2 ------------------------------- */
#define PPB_NVIC_IABR2_ACTIVE_Pos 0 /*!< PPB NVIC_IABR2: ACTIVE Position */
#define PPB_NVIC_IABR2_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR2_ACTIVE_Pos) /*!< PPB NVIC_IABR2: ACTIVE Mask */
/* ------------------------------- PPB_NVIC_IABR3 ------------------------------- */
#define PPB_NVIC_IABR3_ACTIVE_Pos 0 /*!< PPB NVIC_IABR3: ACTIVE Position */
#define PPB_NVIC_IABR3_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR3_ACTIVE_Pos) /*!< PPB NVIC_IABR3: ACTIVE Mask */
/* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */
#define PPB_NVIC_IPR0_PRI_0_Pos 0 /*!< PPB NVIC_IPR0: PRI_0 Position */
#define PPB_NVIC_IPR0_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos) /*!< PPB NVIC_IPR0: PRI_0 Mask */
#define PPB_NVIC_IPR0_PRI_1_Pos 8 /*!< PPB NVIC_IPR0: PRI_1 Position */
#define PPB_NVIC_IPR0_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos) /*!< PPB NVIC_IPR0: PRI_1 Mask */
#define PPB_NVIC_IPR0_PRI_2_Pos 16 /*!< PPB NVIC_IPR0: PRI_2 Position */
#define PPB_NVIC_IPR0_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos) /*!< PPB NVIC_IPR0: PRI_2 Mask */
#define PPB_NVIC_IPR0_PRI_3_Pos 24 /*!< PPB NVIC_IPR0: PRI_3 Position */
#define PPB_NVIC_IPR0_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos) /*!< PPB NVIC_IPR0: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */
#define PPB_NVIC_IPR1_PRI_0_Pos 0 /*!< PPB NVIC_IPR1: PRI_0 Position */
#define PPB_NVIC_IPR1_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos) /*!< PPB NVIC_IPR1: PRI_0 Mask */
#define PPB_NVIC_IPR1_PRI_1_Pos 8 /*!< PPB NVIC_IPR1: PRI_1 Position */
#define PPB_NVIC_IPR1_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos) /*!< PPB NVIC_IPR1: PRI_1 Mask */
#define PPB_NVIC_IPR1_PRI_2_Pos 16 /*!< PPB NVIC_IPR1: PRI_2 Position */
#define PPB_NVIC_IPR1_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos) /*!< PPB NVIC_IPR1: PRI_2 Mask */
#define PPB_NVIC_IPR1_PRI_3_Pos 24 /*!< PPB NVIC_IPR1: PRI_3 Position */
#define PPB_NVIC_IPR1_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos) /*!< PPB NVIC_IPR1: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */
#define PPB_NVIC_IPR2_PRI_0_Pos 0 /*!< PPB NVIC_IPR2: PRI_0 Position */
#define PPB_NVIC_IPR2_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos) /*!< PPB NVIC_IPR2: PRI_0 Mask */
#define PPB_NVIC_IPR2_PRI_1_Pos 8 /*!< PPB NVIC_IPR2: PRI_1 Position */
#define PPB_NVIC_IPR2_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos) /*!< PPB NVIC_IPR2: PRI_1 Mask */
#define PPB_NVIC_IPR2_PRI_2_Pos 16 /*!< PPB NVIC_IPR2: PRI_2 Position */
#define PPB_NVIC_IPR2_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos) /*!< PPB NVIC_IPR2: PRI_2 Mask */
#define PPB_NVIC_IPR2_PRI_3_Pos 24 /*!< PPB NVIC_IPR2: PRI_3 Position */
#define PPB_NVIC_IPR2_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos) /*!< PPB NVIC_IPR2: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */
#define PPB_NVIC_IPR3_PRI_0_Pos 0 /*!< PPB NVIC_IPR3: PRI_0 Position */
#define PPB_NVIC_IPR3_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos) /*!< PPB NVIC_IPR3: PRI_0 Mask */
#define PPB_NVIC_IPR3_PRI_1_Pos 8 /*!< PPB NVIC_IPR3: PRI_1 Position */
#define PPB_NVIC_IPR3_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos) /*!< PPB NVIC_IPR3: PRI_1 Mask */
#define PPB_NVIC_IPR3_PRI_2_Pos 16 /*!< PPB NVIC_IPR3: PRI_2 Position */
#define PPB_NVIC_IPR3_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos) /*!< PPB NVIC_IPR3: PRI_2 Mask */
#define PPB_NVIC_IPR3_PRI_3_Pos 24 /*!< PPB NVIC_IPR3: PRI_3 Position */
#define PPB_NVIC_IPR3_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos) /*!< PPB NVIC_IPR3: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */
#define PPB_NVIC_IPR4_PRI_0_Pos 0 /*!< PPB NVIC_IPR4: PRI_0 Position */
#define PPB_NVIC_IPR4_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos) /*!< PPB NVIC_IPR4: PRI_0 Mask */
#define PPB_NVIC_IPR4_PRI_1_Pos 8 /*!< PPB NVIC_IPR4: PRI_1 Position */
#define PPB_NVIC_IPR4_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos) /*!< PPB NVIC_IPR4: PRI_1 Mask */
#define PPB_NVIC_IPR4_PRI_2_Pos 16 /*!< PPB NVIC_IPR4: PRI_2 Position */
#define PPB_NVIC_IPR4_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos) /*!< PPB NVIC_IPR4: PRI_2 Mask */
#define PPB_NVIC_IPR4_PRI_3_Pos 24 /*!< PPB NVIC_IPR4: PRI_3 Position */
#define PPB_NVIC_IPR4_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos) /*!< PPB NVIC_IPR4: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */
#define PPB_NVIC_IPR5_PRI_0_Pos 0 /*!< PPB NVIC_IPR5: PRI_0 Position */
#define PPB_NVIC_IPR5_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos) /*!< PPB NVIC_IPR5: PRI_0 Mask */
#define PPB_NVIC_IPR5_PRI_1_Pos 8 /*!< PPB NVIC_IPR5: PRI_1 Position */
#define PPB_NVIC_IPR5_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos) /*!< PPB NVIC_IPR5: PRI_1 Mask */
#define PPB_NVIC_IPR5_PRI_2_Pos 16 /*!< PPB NVIC_IPR5: PRI_2 Position */
#define PPB_NVIC_IPR5_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos) /*!< PPB NVIC_IPR5: PRI_2 Mask */
#define PPB_NVIC_IPR5_PRI_3_Pos 24 /*!< PPB NVIC_IPR5: PRI_3 Position */
#define PPB_NVIC_IPR5_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos) /*!< PPB NVIC_IPR5: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */
#define PPB_NVIC_IPR6_PRI_0_Pos 0 /*!< PPB NVIC_IPR6: PRI_0 Position */
#define PPB_NVIC_IPR6_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos) /*!< PPB NVIC_IPR6: PRI_0 Mask */
#define PPB_NVIC_IPR6_PRI_1_Pos 8 /*!< PPB NVIC_IPR6: PRI_1 Position */
#define PPB_NVIC_IPR6_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos) /*!< PPB NVIC_IPR6: PRI_1 Mask */
#define PPB_NVIC_IPR6_PRI_2_Pos 16 /*!< PPB NVIC_IPR6: PRI_2 Position */
#define PPB_NVIC_IPR6_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos) /*!< PPB NVIC_IPR6: PRI_2 Mask */
#define PPB_NVIC_IPR6_PRI_3_Pos 24 /*!< PPB NVIC_IPR6: PRI_3 Position */
#define PPB_NVIC_IPR6_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos) /*!< PPB NVIC_IPR6: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */
#define PPB_NVIC_IPR7_PRI_0_Pos 0 /*!< PPB NVIC_IPR7: PRI_0 Position */
#define PPB_NVIC_IPR7_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos) /*!< PPB NVIC_IPR7: PRI_0 Mask */
#define PPB_NVIC_IPR7_PRI_1_Pos 8 /*!< PPB NVIC_IPR7: PRI_1 Position */
#define PPB_NVIC_IPR7_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos) /*!< PPB NVIC_IPR7: PRI_1 Mask */
#define PPB_NVIC_IPR7_PRI_2_Pos 16 /*!< PPB NVIC_IPR7: PRI_2 Position */
#define PPB_NVIC_IPR7_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos) /*!< PPB NVIC_IPR7: PRI_2 Mask */
#define PPB_NVIC_IPR7_PRI_3_Pos 24 /*!< PPB NVIC_IPR7: PRI_3 Position */
#define PPB_NVIC_IPR7_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos) /*!< PPB NVIC_IPR7: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR8 ------------------------------- */
#define PPB_NVIC_IPR8_PRI_0_Pos 0 /*!< PPB NVIC_IPR8: PRI_0 Position */
#define PPB_NVIC_IPR8_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_0_Pos) /*!< PPB NVIC_IPR8: PRI_0 Mask */
#define PPB_NVIC_IPR8_PRI_1_Pos 8 /*!< PPB NVIC_IPR8: PRI_1 Position */
#define PPB_NVIC_IPR8_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_1_Pos) /*!< PPB NVIC_IPR8: PRI_1 Mask */
#define PPB_NVIC_IPR8_PRI_2_Pos 16 /*!< PPB NVIC_IPR8: PRI_2 Position */
#define PPB_NVIC_IPR8_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_2_Pos) /*!< PPB NVIC_IPR8: PRI_2 Mask */
#define PPB_NVIC_IPR8_PRI_3_Pos 24 /*!< PPB NVIC_IPR8: PRI_3 Position */
#define PPB_NVIC_IPR8_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_3_Pos) /*!< PPB NVIC_IPR8: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR9 ------------------------------- */
#define PPB_NVIC_IPR9_PRI_0_Pos 0 /*!< PPB NVIC_IPR9: PRI_0 Position */
#define PPB_NVIC_IPR9_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_0_Pos) /*!< PPB NVIC_IPR9: PRI_0 Mask */
#define PPB_NVIC_IPR9_PRI_1_Pos 8 /*!< PPB NVIC_IPR9: PRI_1 Position */
#define PPB_NVIC_IPR9_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_1_Pos) /*!< PPB NVIC_IPR9: PRI_1 Mask */
#define PPB_NVIC_IPR9_PRI_2_Pos 16 /*!< PPB NVIC_IPR9: PRI_2 Position */
#define PPB_NVIC_IPR9_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_2_Pos) /*!< PPB NVIC_IPR9: PRI_2 Mask */
#define PPB_NVIC_IPR9_PRI_3_Pos 24 /*!< PPB NVIC_IPR9: PRI_3 Position */
#define PPB_NVIC_IPR9_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_3_Pos) /*!< PPB NVIC_IPR9: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR10 ------------------------------- */
#define PPB_NVIC_IPR10_PRI_0_Pos 0 /*!< PPB NVIC_IPR10: PRI_0 Position */
#define PPB_NVIC_IPR10_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_0_Pos) /*!< PPB NVIC_IPR10: PRI_0 Mask */
#define PPB_NVIC_IPR10_PRI_1_Pos 8 /*!< PPB NVIC_IPR10: PRI_1 Position */
#define PPB_NVIC_IPR10_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_1_Pos) /*!< PPB NVIC_IPR10: PRI_1 Mask */
#define PPB_NVIC_IPR10_PRI_2_Pos 16 /*!< PPB NVIC_IPR10: PRI_2 Position */
#define PPB_NVIC_IPR10_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_2_Pos) /*!< PPB NVIC_IPR10: PRI_2 Mask */
#define PPB_NVIC_IPR10_PRI_3_Pos 24 /*!< PPB NVIC_IPR10: PRI_3 Position */
#define PPB_NVIC_IPR10_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_3_Pos) /*!< PPB NVIC_IPR10: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR11 ------------------------------- */
#define PPB_NVIC_IPR11_PRI_0_Pos 0 /*!< PPB NVIC_IPR11: PRI_0 Position */
#define PPB_NVIC_IPR11_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_0_Pos) /*!< PPB NVIC_IPR11: PRI_0 Mask */
#define PPB_NVIC_IPR11_PRI_1_Pos 8 /*!< PPB NVIC_IPR11: PRI_1 Position */
#define PPB_NVIC_IPR11_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_1_Pos) /*!< PPB NVIC_IPR11: PRI_1 Mask */
#define PPB_NVIC_IPR11_PRI_2_Pos 16 /*!< PPB NVIC_IPR11: PRI_2 Position */
#define PPB_NVIC_IPR11_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_2_Pos) /*!< PPB NVIC_IPR11: PRI_2 Mask */
#define PPB_NVIC_IPR11_PRI_3_Pos 24 /*!< PPB NVIC_IPR11: PRI_3 Position */
#define PPB_NVIC_IPR11_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_3_Pos) /*!< PPB NVIC_IPR11: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR12 ------------------------------- */
#define PPB_NVIC_IPR12_PRI_0_Pos 0 /*!< PPB NVIC_IPR12: PRI_0 Position */
#define PPB_NVIC_IPR12_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_0_Pos) /*!< PPB NVIC_IPR12: PRI_0 Mask */
#define PPB_NVIC_IPR12_PRI_1_Pos 8 /*!< PPB NVIC_IPR12: PRI_1 Position */
#define PPB_NVIC_IPR12_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_1_Pos) /*!< PPB NVIC_IPR12: PRI_1 Mask */
#define PPB_NVIC_IPR12_PRI_2_Pos 16 /*!< PPB NVIC_IPR12: PRI_2 Position */
#define PPB_NVIC_IPR12_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_2_Pos) /*!< PPB NVIC_IPR12: PRI_2 Mask */
#define PPB_NVIC_IPR12_PRI_3_Pos 24 /*!< PPB NVIC_IPR12: PRI_3 Position */
#define PPB_NVIC_IPR12_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_3_Pos) /*!< PPB NVIC_IPR12: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR13 ------------------------------- */
#define PPB_NVIC_IPR13_PRI_0_Pos 0 /*!< PPB NVIC_IPR13: PRI_0 Position */
#define PPB_NVIC_IPR13_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_0_Pos) /*!< PPB NVIC_IPR13: PRI_0 Mask */
#define PPB_NVIC_IPR13_PRI_1_Pos 8 /*!< PPB NVIC_IPR13: PRI_1 Position */
#define PPB_NVIC_IPR13_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_1_Pos) /*!< PPB NVIC_IPR13: PRI_1 Mask */
#define PPB_NVIC_IPR13_PRI_2_Pos 16 /*!< PPB NVIC_IPR13: PRI_2 Position */
#define PPB_NVIC_IPR13_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_2_Pos) /*!< PPB NVIC_IPR13: PRI_2 Mask */
#define PPB_NVIC_IPR13_PRI_3_Pos 24 /*!< PPB NVIC_IPR13: PRI_3 Position */
#define PPB_NVIC_IPR13_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_3_Pos) /*!< PPB NVIC_IPR13: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR14 ------------------------------- */
#define PPB_NVIC_IPR14_PRI_0_Pos 0 /*!< PPB NVIC_IPR14: PRI_0 Position */
#define PPB_NVIC_IPR14_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_0_Pos) /*!< PPB NVIC_IPR14: PRI_0 Mask */
#define PPB_NVIC_IPR14_PRI_1_Pos 8 /*!< PPB NVIC_IPR14: PRI_1 Position */
#define PPB_NVIC_IPR14_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_1_Pos) /*!< PPB NVIC_IPR14: PRI_1 Mask */
#define PPB_NVIC_IPR14_PRI_2_Pos 16 /*!< PPB NVIC_IPR14: PRI_2 Position */
#define PPB_NVIC_IPR14_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_2_Pos) /*!< PPB NVIC_IPR14: PRI_2 Mask */
#define PPB_NVIC_IPR14_PRI_3_Pos 24 /*!< PPB NVIC_IPR14: PRI_3 Position */
#define PPB_NVIC_IPR14_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_3_Pos) /*!< PPB NVIC_IPR14: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR15 ------------------------------- */
#define PPB_NVIC_IPR15_PRI_0_Pos 0 /*!< PPB NVIC_IPR15: PRI_0 Position */
#define PPB_NVIC_IPR15_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_0_Pos) /*!< PPB NVIC_IPR15: PRI_0 Mask */
#define PPB_NVIC_IPR15_PRI_1_Pos 8 /*!< PPB NVIC_IPR15: PRI_1 Position */
#define PPB_NVIC_IPR15_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_1_Pos) /*!< PPB NVIC_IPR15: PRI_1 Mask */
#define PPB_NVIC_IPR15_PRI_2_Pos 16 /*!< PPB NVIC_IPR15: PRI_2 Position */
#define PPB_NVIC_IPR15_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_2_Pos) /*!< PPB NVIC_IPR15: PRI_2 Mask */
#define PPB_NVIC_IPR15_PRI_3_Pos 24 /*!< PPB NVIC_IPR15: PRI_3 Position */
#define PPB_NVIC_IPR15_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_3_Pos) /*!< PPB NVIC_IPR15: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR16 ------------------------------- */
#define PPB_NVIC_IPR16_PRI_0_Pos 0 /*!< PPB NVIC_IPR16: PRI_0 Position */
#define PPB_NVIC_IPR16_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_0_Pos) /*!< PPB NVIC_IPR16: PRI_0 Mask */
#define PPB_NVIC_IPR16_PRI_1_Pos 8 /*!< PPB NVIC_IPR16: PRI_1 Position */
#define PPB_NVIC_IPR16_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_1_Pos) /*!< PPB NVIC_IPR16: PRI_1 Mask */
#define PPB_NVIC_IPR16_PRI_2_Pos 16 /*!< PPB NVIC_IPR16: PRI_2 Position */
#define PPB_NVIC_IPR16_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_2_Pos) /*!< PPB NVIC_IPR16: PRI_2 Mask */
#define PPB_NVIC_IPR16_PRI_3_Pos 24 /*!< PPB NVIC_IPR16: PRI_3 Position */
#define PPB_NVIC_IPR16_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_3_Pos) /*!< PPB NVIC_IPR16: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR17 ------------------------------- */
#define PPB_NVIC_IPR17_PRI_0_Pos 0 /*!< PPB NVIC_IPR17: PRI_0 Position */
#define PPB_NVIC_IPR17_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_0_Pos) /*!< PPB NVIC_IPR17: PRI_0 Mask */
#define PPB_NVIC_IPR17_PRI_1_Pos 8 /*!< PPB NVIC_IPR17: PRI_1 Position */
#define PPB_NVIC_IPR17_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_1_Pos) /*!< PPB NVIC_IPR17: PRI_1 Mask */
#define PPB_NVIC_IPR17_PRI_2_Pos 16 /*!< PPB NVIC_IPR17: PRI_2 Position */
#define PPB_NVIC_IPR17_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_2_Pos) /*!< PPB NVIC_IPR17: PRI_2 Mask */
#define PPB_NVIC_IPR17_PRI_3_Pos 24 /*!< PPB NVIC_IPR17: PRI_3 Position */
#define PPB_NVIC_IPR17_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_3_Pos) /*!< PPB NVIC_IPR17: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR18 ------------------------------- */
#define PPB_NVIC_IPR18_PRI_0_Pos 0 /*!< PPB NVIC_IPR18: PRI_0 Position */
#define PPB_NVIC_IPR18_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_0_Pos) /*!< PPB NVIC_IPR18: PRI_0 Mask */
#define PPB_NVIC_IPR18_PRI_1_Pos 8 /*!< PPB NVIC_IPR18: PRI_1 Position */
#define PPB_NVIC_IPR18_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_1_Pos) /*!< PPB NVIC_IPR18: PRI_1 Mask */
#define PPB_NVIC_IPR18_PRI_2_Pos 16 /*!< PPB NVIC_IPR18: PRI_2 Position */
#define PPB_NVIC_IPR18_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_2_Pos) /*!< PPB NVIC_IPR18: PRI_2 Mask */
#define PPB_NVIC_IPR18_PRI_3_Pos 24 /*!< PPB NVIC_IPR18: PRI_3 Position */
#define PPB_NVIC_IPR18_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_3_Pos) /*!< PPB NVIC_IPR18: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR19 ------------------------------- */
#define PPB_NVIC_IPR19_PRI_0_Pos 0 /*!< PPB NVIC_IPR19: PRI_0 Position */
#define PPB_NVIC_IPR19_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_0_Pos) /*!< PPB NVIC_IPR19: PRI_0 Mask */
#define PPB_NVIC_IPR19_PRI_1_Pos 8 /*!< PPB NVIC_IPR19: PRI_1 Position */
#define PPB_NVIC_IPR19_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_1_Pos) /*!< PPB NVIC_IPR19: PRI_1 Mask */
#define PPB_NVIC_IPR19_PRI_2_Pos 16 /*!< PPB NVIC_IPR19: PRI_2 Position */
#define PPB_NVIC_IPR19_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_2_Pos) /*!< PPB NVIC_IPR19: PRI_2 Mask */
#define PPB_NVIC_IPR19_PRI_3_Pos 24 /*!< PPB NVIC_IPR19: PRI_3 Position */
#define PPB_NVIC_IPR19_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_3_Pos) /*!< PPB NVIC_IPR19: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR20 ------------------------------- */
#define PPB_NVIC_IPR20_PRI_0_Pos 0 /*!< PPB NVIC_IPR20: PRI_0 Position */
#define PPB_NVIC_IPR20_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_0_Pos) /*!< PPB NVIC_IPR20: PRI_0 Mask */
#define PPB_NVIC_IPR20_PRI_1_Pos 8 /*!< PPB NVIC_IPR20: PRI_1 Position */
#define PPB_NVIC_IPR20_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_1_Pos) /*!< PPB NVIC_IPR20: PRI_1 Mask */
#define PPB_NVIC_IPR20_PRI_2_Pos 16 /*!< PPB NVIC_IPR20: PRI_2 Position */
#define PPB_NVIC_IPR20_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_2_Pos) /*!< PPB NVIC_IPR20: PRI_2 Mask */
#define PPB_NVIC_IPR20_PRI_3_Pos 24 /*!< PPB NVIC_IPR20: PRI_3 Position */
#define PPB_NVIC_IPR20_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_3_Pos) /*!< PPB NVIC_IPR20: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR21 ------------------------------- */
#define PPB_NVIC_IPR21_PRI_0_Pos 0 /*!< PPB NVIC_IPR21: PRI_0 Position */
#define PPB_NVIC_IPR21_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_0_Pos) /*!< PPB NVIC_IPR21: PRI_0 Mask */
#define PPB_NVIC_IPR21_PRI_1_Pos 8 /*!< PPB NVIC_IPR21: PRI_1 Position */
#define PPB_NVIC_IPR21_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_1_Pos) /*!< PPB NVIC_IPR21: PRI_1 Mask */
#define PPB_NVIC_IPR21_PRI_2_Pos 16 /*!< PPB NVIC_IPR21: PRI_2 Position */
#define PPB_NVIC_IPR21_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_2_Pos) /*!< PPB NVIC_IPR21: PRI_2 Mask */
#define PPB_NVIC_IPR21_PRI_3_Pos 24 /*!< PPB NVIC_IPR21: PRI_3 Position */
#define PPB_NVIC_IPR21_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_3_Pos) /*!< PPB NVIC_IPR21: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR22 ------------------------------- */
#define PPB_NVIC_IPR22_PRI_0_Pos 0 /*!< PPB NVIC_IPR22: PRI_0 Position */
#define PPB_NVIC_IPR22_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_0_Pos) /*!< PPB NVIC_IPR22: PRI_0 Mask */
#define PPB_NVIC_IPR22_PRI_1_Pos 8 /*!< PPB NVIC_IPR22: PRI_1 Position */
#define PPB_NVIC_IPR22_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_1_Pos) /*!< PPB NVIC_IPR22: PRI_1 Mask */
#define PPB_NVIC_IPR22_PRI_2_Pos 16 /*!< PPB NVIC_IPR22: PRI_2 Position */
#define PPB_NVIC_IPR22_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_2_Pos) /*!< PPB NVIC_IPR22: PRI_2 Mask */
#define PPB_NVIC_IPR22_PRI_3_Pos 24 /*!< PPB NVIC_IPR22: PRI_3 Position */
#define PPB_NVIC_IPR22_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_3_Pos) /*!< PPB NVIC_IPR22: PRI_3 Mask */
/* ------------------------------- PPB_NVIC_IPR23 ------------------------------- */
#define PPB_NVIC_IPR23_PRI_0_Pos 0 /*!< PPB NVIC_IPR23: PRI_0 Position */
#define PPB_NVIC_IPR23_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR23_PRI_0_Pos