/**************************************************************************//** | |
* @file cmsis_armcc.h | |
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file | |
* @version V5.0.4 | |
* @date 10. January 2018 | |
******************************************************************************/ | |
/* | |
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. | |
* | |
* SPDX-License-Identifier: Apache-2.0 | |
* | |
* Licensed under the Apache License, Version 2.0 (the License); you may | |
* not use this file except in compliance with the License. | |
* You may obtain a copy of the License at | |
* | |
* www.apache.org/licenses/LICENSE-2.0 | |
* | |
* Unless required by applicable law or agreed to in writing, software | |
* distributed under the License is distributed on an AS IS BASIS, WITHOUT | |
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |
* See the License for the specific language governing permissions and | |
* limitations under the License. | |
*/ | |
#ifndef __CMSIS_ARMCC_H | |
#define __CMSIS_ARMCC_H | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) | |
#error "Please use Arm Compiler Toolchain V4.0.677 or later!" | |
#endif | |
/* CMSIS compiler control architecture macros */ | |
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ | |
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) | |
#define __ARM_ARCH_6M__ 1 | |
#endif | |
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) | |
#define __ARM_ARCH_7M__ 1 | |
#endif | |
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) | |
#define __ARM_ARCH_7EM__ 1 | |
#endif | |
/* __ARM_ARCH_8M_BASE__ not applicable */ | |
/* __ARM_ARCH_8M_MAIN__ not applicable */ | |
/* CMSIS compiler specific defines */ | |
#ifndef __ASM | |
#define __ASM __asm | |
#endif | |
#ifndef __INLINE | |
#define __INLINE __inline | |
#endif | |
#ifndef __STATIC_INLINE | |
#define __STATIC_INLINE static __inline | |
#endif | |
#ifndef __STATIC_FORCEINLINE | |
#define __STATIC_FORCEINLINE static __forceinline | |
#endif | |
#ifndef __NO_RETURN | |
#define __NO_RETURN __declspec(noreturn) | |
#endif | |
#ifndef __USED | |
#define __USED __attribute__((used)) | |
#endif | |
#ifndef __WEAK | |
#define __WEAK __attribute__((weak)) | |
#endif | |
#ifndef __PACKED | |
#define __PACKED __attribute__((packed)) | |
#endif | |
#ifndef __PACKED_STRUCT | |
#define __PACKED_STRUCT __packed struct | |
#endif | |
#ifndef __PACKED_UNION | |
#define __PACKED_UNION __packed union | |
#endif | |
#ifndef __UNALIGNED_UINT32 /* deprecated */ | |
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) | |
#endif | |
#ifndef __UNALIGNED_UINT16_WRITE | |
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) | |
#endif | |
#ifndef __UNALIGNED_UINT16_READ | |
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) | |
#endif | |
#ifndef __UNALIGNED_UINT32_WRITE | |
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) | |
#endif | |
#ifndef __UNALIGNED_UINT32_READ | |
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) | |
#endif | |
#ifndef __ALIGNED | |
#define __ALIGNED(x) __attribute__((aligned(x))) | |
#endif | |
#ifndef __RESTRICT | |
#define __RESTRICT __restrict | |
#endif | |
/* ########################### Core Function Access ########################### */ | |
/** \ingroup CMSIS_Core_FunctionInterface | |
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions | |
@{ | |
*/ | |
/** | |
\brief Enable IRQ Interrupts | |
\details Enables IRQ interrupts by clearing the I-bit in the CPSR. | |
Can only be executed in Privileged modes. | |
*/ | |
/* intrinsic void __enable_irq(); */ | |
/** | |
\brief Disable IRQ Interrupts | |
\details Disables IRQ interrupts by setting the I-bit in the CPSR. | |
Can only be executed in Privileged modes. | |
*/ | |
/* intrinsic void __disable_irq(); */ | |
/** | |
\brief Get Control Register | |
\details Returns the content of the Control Register. | |
\return Control Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_CONTROL(void) | |
{ | |
register uint32_t __regControl __ASM("control"); | |
return(__regControl); | |
} | |
/** | |
\brief Set Control Register | |
\details Writes the given value to the Control Register. | |
\param [in] control Control Register value to set | |
*/ | |
__STATIC_INLINE void __set_CONTROL(uint32_t control) | |
{ | |
register uint32_t __regControl __ASM("control"); | |
__regControl = control; | |
} | |
/** | |
\brief Get IPSR Register | |
\details Returns the content of the IPSR Register. | |
\return IPSR Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_IPSR(void) | |
{ | |
register uint32_t __regIPSR __ASM("ipsr"); | |
return(__regIPSR); | |
} | |
/** | |
\brief Get APSR Register | |
\details Returns the content of the APSR Register. | |
\return APSR Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_APSR(void) | |
{ | |
register uint32_t __regAPSR __ASM("apsr"); | |
return(__regAPSR); | |
} | |
/** | |
\brief Get xPSR Register | |
\details Returns the content of the xPSR Register. | |
\return xPSR Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_xPSR(void) | |
{ | |
register uint32_t __regXPSR __ASM("xpsr"); | |
return(__regXPSR); | |
} | |
/** | |
\brief Get Process Stack Pointer | |
\details Returns the current value of the Process Stack Pointer (PSP). | |
\return PSP Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_PSP(void) | |
{ | |
register uint32_t __regProcessStackPointer __ASM("psp"); | |
return(__regProcessStackPointer); | |
} | |
/** | |
\brief Set Process Stack Pointer | |
\details Assigns the given value to the Process Stack Pointer (PSP). | |
\param [in] topOfProcStack Process Stack Pointer value to set | |
*/ | |
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) | |
{ | |
register uint32_t __regProcessStackPointer __ASM("psp"); | |
__regProcessStackPointer = topOfProcStack; | |
} | |
/** | |
\brief Get Main Stack Pointer | |
\details Returns the current value of the Main Stack Pointer (MSP). | |
\return MSP Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_MSP(void) | |
{ | |
register uint32_t __regMainStackPointer __ASM("msp"); | |
return(__regMainStackPointer); | |
} | |
/** | |
\brief Set Main Stack Pointer | |
\details Assigns the given value to the Main Stack Pointer (MSP). | |
\param [in] topOfMainStack Main Stack Pointer value to set | |
*/ | |
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) | |
{ | |
register uint32_t __regMainStackPointer __ASM("msp"); | |
__regMainStackPointer = topOfMainStack; | |
} | |
/** | |
\brief Get Priority Mask | |
\details Returns the current state of the priority mask bit from the Priority Mask Register. | |
\return Priority Mask value | |
*/ | |
__STATIC_INLINE uint32_t __get_PRIMASK(void) | |
{ | |
register uint32_t __regPriMask __ASM("primask"); | |
return(__regPriMask); | |
} | |
/** | |
\brief Set Priority Mask | |
\details Assigns the given value to the Priority Mask Register. | |
\param [in] priMask Priority Mask | |
*/ | |
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) | |
{ | |
register uint32_t __regPriMask __ASM("primask"); | |
__regPriMask = (priMask); | |
} | |
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ | |
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) | |
/** | |
\brief Enable FIQ | |
\details Enables FIQ interrupts by clearing the F-bit in the CPSR. | |
Can only be executed in Privileged modes. | |
*/ | |
#define __enable_fault_irq __enable_fiq | |
/** | |
\brief Disable FIQ | |
\details Disables FIQ interrupts by setting the F-bit in the CPSR. | |
Can only be executed in Privileged modes. | |
*/ | |
#define __disable_fault_irq __disable_fiq | |
/** | |
\brief Get Base Priority | |
\details Returns the current value of the Base Priority register. | |
\return Base Priority register value | |
*/ | |
__STATIC_INLINE uint32_t __get_BASEPRI(void) | |
{ | |
register uint32_t __regBasePri __ASM("basepri"); | |
return(__regBasePri); | |
} | |
/** | |
\brief Set Base Priority | |
\details Assigns the given value to the Base Priority register. | |
\param [in] basePri Base Priority value to set | |
*/ | |
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) | |
{ | |
register uint32_t __regBasePri __ASM("basepri"); | |
__regBasePri = (basePri & 0xFFU); | |
} | |
/** | |
\brief Set Base Priority with condition | |
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, | |
or the new value increases the BASEPRI priority level. | |
\param [in] basePri Base Priority value to set | |
*/ | |
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) | |
{ | |
register uint32_t __regBasePriMax __ASM("basepri_max"); | |
__regBasePriMax = (basePri & 0xFFU); | |
} | |
/** | |
\brief Get Fault Mask | |
\details Returns the current value of the Fault Mask register. | |
\return Fault Mask register value | |
*/ | |
__STATIC_INLINE uint32_t __get_FAULTMASK(void) | |
{ | |
register uint32_t __regFaultMask __ASM("faultmask"); | |
return(__regFaultMask); | |
} | |
/** | |
\brief Set Fault Mask | |
\details Assigns the given value to the Fault Mask register. | |
\param [in] faultMask Fault Mask value to set | |
*/ | |
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) | |
{ | |
register uint32_t __regFaultMask __ASM("faultmask"); | |
__regFaultMask = (faultMask & (uint32_t)1U); | |
} | |
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ | |
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ | |
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) | |
/** | |
\brief Get FPSCR | |
\details Returns the current value of the Floating Point Status/Control register. | |
\return Floating Point Status/Control register value | |
*/ | |
__STATIC_INLINE uint32_t __get_FPSCR(void) | |
{ | |
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ | |
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) | |
register uint32_t __regfpscr __ASM("fpscr"); | |
return(__regfpscr); | |
#else | |
return(0U); | |
#endif | |
} | |
/** | |
\brief Set FPSCR | |
\details Assigns the given value to the Floating Point Status/Control register. | |
\param [in] fpscr Floating Point Status/Control value to set | |
*/ | |
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) | |
{ | |
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ | |
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) | |
register uint32_t __regfpscr __ASM("fpscr"); | |
__regfpscr = (fpscr); | |
#else | |
(void)fpscr; | |
#endif | |
} | |
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ | |
/*@} end of CMSIS_Core_RegAccFunctions */ | |
/* ########################## Core Instruction Access ######################### */ | |
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface | |
Access to dedicated instructions | |
@{ | |
*/ | |
/** | |
\brief No Operation | |
\details No Operation does nothing. This instruction can be used for code alignment purposes. | |
*/ | |
#define __NOP __nop | |
/** | |
\brief Wait For Interrupt | |
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. | |
*/ | |
#define __WFI __wfi | |
/** | |
\brief Wait For Event | |
\details Wait For Event is a hint instruction that permits the processor to enter | |
a low-power state until one of a number of events occurs. | |
*/ | |
#define __WFE __wfe | |
/** | |
\brief Send Event | |
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU. | |
*/ | |
#define __SEV __sev | |
/** | |
\brief Instruction Synchronization Barrier | |
\details Instruction Synchronization Barrier flushes the pipeline in the processor, | |
so that all instructions following the ISB are fetched from cache or memory, | |
after the instruction has been completed. | |
*/ | |
#define __ISB() do {\ | |
__schedule_barrier();\ | |
__isb(0xF);\ | |
__schedule_barrier();\ | |
} while (0U) | |
/** | |
\brief Data Synchronization Barrier | |
\details Acts as a special kind of Data Memory Barrier. | |
It completes when all explicit memory accesses before this instruction complete. | |
*/ | |
#define __DSB() do {\ | |
__schedule_barrier();\ | |
__dsb(0xF);\ | |
__schedule_barrier();\ | |
} while (0U) | |
/** | |
\brief Data Memory Barrier | |
\details Ensures the apparent order of the explicit memory operations before | |
and after the instruction, without ensuring their completion. | |
*/ | |
#define __DMB() do {\ | |
__schedule_barrier();\ | |
__dmb(0xF);\ | |
__schedule_barrier();\ | |
} while (0U) | |
/** | |
\brief Reverse byte order (32 bit) | |
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. | |
\param [in] value Value to reverse | |
\return Reversed value | |
*/ | |
#define __REV __rev | |
/** | |
\brief Reverse byte order (16 bit) | |
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. | |
\param [in] value Value to reverse | |
\return Reversed value | |
*/ | |
#ifndef __NO_EMBEDDED_ASM | |
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) | |
{ | |
rev16 r0, r0 | |
bx lr | |
} | |
#endif | |
/** | |
\brief Reverse byte order (16 bit) | |
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. | |
\param [in] value Value to reverse | |
\return Reversed value | |
*/ | |
#ifndef __NO_EMBEDDED_ASM | |
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) | |
{ | |
revsh r0, r0 | |
bx lr | |
} | |
#endif | |
/** | |
\brief Rotate Right in unsigned value (32 bit) | |
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. | |
\param [in] op1 Value to rotate | |
\param [in] op2 Number of Bits to rotate | |
\return Rotated value | |
*/ | |
#define __ROR __ror | |
/** | |
\brief Breakpoint | |
\details Causes the processor to enter Debug state. | |
Debug tools can use this to investigate system state when the instruction at a particular address is reached. | |
\param [in] value is ignored by the processor. | |
If required, a debugger can use it to store additional information about the breakpoint. | |
*/ | |
#define __BKPT(value) __breakpoint(value) | |
/** | |
\brief Reverse bit order of value | |
\details Reverses the bit order of the given value. | |
\param [in] value Value to reverse | |
\return Reversed value | |
*/ | |
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ | |
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) | |
#define __RBIT __rbit | |
#else | |
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) | |
{ | |
uint32_t result; | |
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ | |
result = value; /* r will be reversed bits of v; first get LSB of v */ | |
for (value >>= 1U; value != 0U; value >>= 1U) | |
{ | |
result <<= 1U; | |
result |= value & 1U; | |
s--; | |
} | |
result <<= s; /* shift when v's highest bits are zero */ | |
return result; | |
} | |
#endif | |
/** | |
\brief Count leading zeros | |
\details Counts the number of leading zeros of a data value. | |
\param [in] value Value to count the leading zeros | |
\return number of leading zeros in value | |
*/ | |
#define __CLZ __clz | |
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ | |
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) | |
/** | |
\brief LDR Exclusive (8 bit) | |
\details Executes a exclusive LDR instruction for 8 bit value. | |
\param [in] ptr Pointer to data | |
\return value of type uint8_t at (*ptr) | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) | |
#else | |
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") | |
#endif | |
/** | |
\brief LDR Exclusive (16 bit) | |
\details Executes a exclusive LDR instruction for 16 bit values. | |
\param [in] ptr Pointer to data | |
\return value of type uint16_t at (*ptr) | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) | |
#else | |
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") | |
#endif | |
/** | |
\brief LDR Exclusive (32 bit) | |
\details Executes a exclusive LDR instruction for 32 bit values. | |
\param [in] ptr Pointer to data | |
\return value of type uint32_t at (*ptr) | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) | |
#else | |
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") | |
#endif | |
/** | |
\brief STR Exclusive (8 bit) | |
\details Executes a exclusive STR instruction for 8 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
\return 0 Function succeeded | |
\return 1 Function failed | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __STREXB(value, ptr) __strex(value, ptr) | |
#else | |
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") | |
#endif | |
/** | |
\brief STR Exclusive (16 bit) | |
\details Executes a exclusive STR instruction for 16 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
\return 0 Function succeeded | |
\return 1 Function failed | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __STREXH(value, ptr) __strex(value, ptr) | |
#else | |
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") | |
#endif | |
/** | |
\brief STR Exclusive (32 bit) | |
\details Executes a exclusive STR instruction for 32 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
\return 0 Function succeeded | |
\return 1 Function failed | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __STREXW(value, ptr) __strex(value, ptr) | |
#else | |
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") | |
#endif | |
/** | |
\brief Remove the exclusive lock | |
\details Removes the exclusive lock which is created by LDREX. | |
*/ | |
#define __CLREX __clrex | |
/** | |
\brief Signed Saturate | |
\details Saturates a signed value. | |
\param [in] value Value to be saturated | |
\param [in] sat Bit position to saturate to (1..32) | |
\return Saturated value | |
*/ | |
#define __SSAT __ssat | |
/** | |
\brief Unsigned Saturate | |
\details Saturates an unsigned value. | |
\param [in] value Value to be saturated | |
\param [in] sat Bit position to saturate to (0..31) | |
\return Saturated value | |
*/ | |
#define __USAT __usat | |
/** | |
\brief Rotate Right with Extend (32 bit) | |
\details Moves each bit of a bitstring right by one bit. | |
The carry input is shifted in at the left end of the bitstring. | |
\param [in] value Value to rotate | |
\return Rotated value | |
*/ | |
#ifndef __NO_EMBEDDED_ASM | |
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) | |
{ | |
rrx r0, r0 | |
bx lr | |
} | |
#endif | |
/** | |
\brief LDRT Unprivileged (8 bit) | |
\details Executes a Unprivileged LDRT instruction for 8 bit value. | |
\param [in] ptr Pointer to data | |
\return value of type uint8_t at (*ptr) | |
*/ | |
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) | |
/** | |
\brief LDRT Unprivileged (16 bit) | |
\details Executes a Unprivileged LDRT instruction for 16 bit values. | |
\param [in] ptr Pointer to data | |
\return value of type uint16_t at (*ptr) | |
*/ | |
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) | |
/** | |
\brief LDRT Unprivileged (32 bit) | |
\details Executes a Unprivileged LDRT instruction for 32 bit values. | |
\param [in] ptr Pointer to data | |
\return value of type uint32_t at (*ptr) | |
*/ | |
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) | |
/** | |
\brief STRT Unprivileged (8 bit) | |
\details Executes a Unprivileged STRT instruction for 8 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
*/ | |
#define __STRBT(value, ptr) __strt(value, ptr) | |
/** | |
\brief STRT Unprivileged (16 bit) | |
\details Executes a Unprivileged STRT instruction for 16 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
*/ | |
#define __STRHT(value, ptr) __strt(value, ptr) | |
/** | |
\brief STRT Unprivileged (32 bit) | |
\details Executes a Unprivileged STRT instruction for 32 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
*/ | |
#define __STRT(value, ptr) __strt(value, ptr) | |
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ | |
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ | |
/** | |
\brief Signed Saturate | |
\details Saturates a signed value. | |
\param [in] value Value to be saturated | |
\param [in] sat Bit position to saturate to (1..32) | |
\return Saturated value | |
*/ | |
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) | |
{ | |
if ((sat >= 1U) && (sat <= 32U)) | |
{ | |
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); | |
const int32_t min = -1 - max ; | |
if (val > max) | |
{ | |
return max; | |
} | |
else if (val < min) | |
{ | |
return min; | |
} | |
} | |
return val; | |
} | |
/** | |
\brief Unsigned Saturate | |
\details Saturates an unsigned value. | |
\param [in] value Value to be saturated | |
\param [in] sat Bit position to saturate to (0..31) | |
\return Saturated value | |
*/ | |
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) | |
{ | |
if (sat <= 31U) | |
{ | |
const uint32_t max = ((1U << sat) - 1U); | |
if (val > (int32_t)max) | |
{ | |
return max; | |
} | |
else if (val < 0) | |
{ | |
return 0U; | |
} | |
} | |
return (uint32_t)val; | |
} | |
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ | |
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ | |
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ | |
/* ################### Compiler specific Intrinsics ########################### */ | |
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics | |
Access to dedicated SIMD instructions | |
@{ | |
*/ | |
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) | |
#define __SADD8 __sadd8 | |
#define __QADD8 __qadd8 | |
#define __SHADD8 __shadd8 | |
#define __UADD8 __uadd8 | |
#define __UQADD8 __uqadd8 | |
#define __UHADD8 __uhadd8 | |
#define __SSUB8 __ssub8 | |
#define __QSUB8 __qsub8 | |
#define __SHSUB8 __shsub8 | |
#define __USUB8 __usub8 | |
#define __UQSUB8 __uqsub8 | |
#define __UHSUB8 __uhsub8 | |
#define __SADD16 __sadd16 | |
#define __QADD16 __qadd16 | |
#define __SHADD16 __shadd16 | |
#define __UADD16 __uadd16 | |
#define __UQADD16 __uqadd16 | |
#define __UHADD16 __uhadd16 | |
#define __SSUB16 __ssub16 | |
#define __QSUB16 __qsub16 | |
#define __SHSUB16 __shsub16 | |
#define __USUB16 __usub16 | |
#define __UQSUB16 __uqsub16 | |
#define __UHSUB16 __uhsub16 | |
#define __SASX __sasx | |
#define __QASX __qasx | |
#define __SHASX __shasx | |
#define __UASX __uasx | |
#define __UQASX __uqasx | |
#define __UHASX __uhasx | |
#define __SSAX __ssax | |
#define __QSAX __qsax | |
#define __SHSAX __shsax | |
#define __USAX __usax | |
#define __UQSAX __uqsax | |
#define __UHSAX __uhsax | |
#define __USAD8 __usad8 | |
#define __USADA8 __usada8 | |
#define __SSAT16 __ssat16 | |
#define __USAT16 __usat16 | |
#define __UXTB16 __uxtb16 | |
#define __UXTAB16 __uxtab16 | |
#define __SXTB16 __sxtb16 | |
#define __SXTAB16 __sxtab16 | |
#define __SMUAD __smuad | |
#define __SMUADX __smuadx | |
#define __SMLAD __smlad | |
#define __SMLADX __smladx | |
#define __SMLALD __smlald | |
#define __SMLALDX __smlaldx | |
#define __SMUSD __smusd | |
#define __SMUSDX __smusdx | |
#define __SMLSD __smlsd | |
#define __SMLSDX __smlsdx | |
#define __SMLSLD __smlsld | |
#define __SMLSLDX __smlsldx | |
#define __SEL __sel | |
#define __QADD __qadd | |
#define __QSUB __qsub | |
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ | |
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) | |
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ | |
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) | |
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ | |
((int64_t)(ARG3) << 32U) ) >> 32U)) | |
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ | |
/*@} end of group CMSIS_SIMD_intrinsics */ | |
#endif /* __CMSIS_ARMCC_H */ |