/* | |
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd. | |
*************************************************************************** | |
* * | |
* FreeRTOS tutorial books are available in pdf and paperback. * | |
* Complete, revised, and edited pdf reference manuals are also * | |
* available. * | |
* * | |
* Purchasing FreeRTOS documentation will not only help you, by * | |
* ensuring you get running as quickly as possible and with an * | |
* in-depth knowledge of how to use FreeRTOS, it will also help * | |
* the FreeRTOS project to continue with its mission of providing * | |
* professional grade, cross platform, de facto standard solutions * | |
* for microcontrollers - completely free of charge! * | |
* * | |
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< * | |
* * | |
* Thank you for using FreeRTOS, and thank you for your support! * | |
* * | |
*************************************************************************** | |
This file is part of the FreeRTOS distribution. | |
FreeRTOS is free software; you can redistribute it and/or modify it under | |
the terms of the GNU General Public License (version 2) as published by the | |
Free Software Foundation AND MODIFIED BY the FreeRTOS exception. | |
>>>NOTE<<< The modification to the GPL is included to allow you to | |
distribute a combined work that includes FreeRTOS without being obliged to | |
provide the source code for proprietary components outside of the FreeRTOS | |
kernel. FreeRTOS is distributed in the hope that it will be useful, but | |
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
more details. You should have received a copy of the GNU General Public | |
License and the FreeRTOS license exception along with FreeRTOS; if not it | |
can be viewed here: http://www.freertos.org/a00114.html and also obtained | |
by writing to Richard Barry, contact details for whom are available on the | |
FreeRTOS WEB site. | |
1 tab == 4 spaces! | |
http://www.FreeRTOS.org - Documentation, latest information, license and | |
contact details. | |
http://www.SafeRTOS.com - A version that is certified for use in safety | |
critical systems. | |
http://www.OpenRTOS.com - Commercial support, development, porting, | |
licensing and training services. | |
*/ | |
/* | |
* This file contains the non-portable and therefore RX62N specific parts of | |
* the IntQueue standard demo task - namely the configuration of the timers | |
* that generate the interrupts and the interrupt entry points. | |
*/ | |
/* Scheduler includes. */ | |
#include "FreeRTOS.h" | |
#include "task.h" | |
/* Demo includes. */ | |
#include "IntQueueTimer.h" | |
#include "IntQueue.h" | |
/* Hardware specifics. */ | |
#include "iodefine.h" | |
#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) | |
#define tmrTIMER_2_3_FREQUENCY ( 2001UL ) | |
/* Handlers for the two timers used. See the documentation page | |
for this port on http://www.FreeRTOS.org for more information on writing | |
interrupt handlers. */ | |
void vT0_1_ISR_Handler( void ) __attribute((interrupt)); | |
void vT2_3_ISR_Handler( void ) __attribute((interrupt)); | |
void vInitialiseTimerForIntQueueTest( void ) | |
{ | |
/* Ensure interrupts do not start until full configuration is complete. */ | |
portENTER_CRITICAL(); | |
{ | |
/* Cascade two 8bit timer channels to generate the interrupts. | |
8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are | |
utilised for this test. */ | |
/* Enable the timers. */ | |
SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; | |
SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; | |
/* Enable compare match A interrupt request. */ | |
TMR0.TCR.BIT.CMIEA = 1; | |
TMR2.TCR.BIT.CMIEA = 1; | |
/* Clear the timer on compare match A. */ | |
TMR0.TCR.BIT.CCLR = 1; | |
TMR2.TCR.BIT.CCLR = 1; | |
/* Set the compare match value. */ | |
TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); | |
TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); | |
/* 16 bit operation ( count from timer 1,2 ). */ | |
TMR0.TCCR.BIT.CSS = 3; | |
TMR2.TCCR.BIT.CSS = 3; | |
/* Use PCLK as the input. */ | |
TMR1.TCCR.BIT.CSS = 1; | |
TMR3.TCCR.BIT.CSS = 1; | |
/* Divide PCLK by 8. */ | |
TMR1.TCCR.BIT.CKS = 2; | |
TMR3.TCCR.BIT.CKS = 2; | |
/* Enable TMR 0, 2 interrupts. */ | |
IEN( TMR0, CMIA0 ) = 1; | |
IEN( TMR2, CMIA2 ) = 1; | |
/* Set the timer interrupts to be above the kernel. The interrupts are | |
assigned different priorities so they nest with each other. */ | |
IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; | |
IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 ); | |
} | |
portEXIT_CRITICAL(); | |
/* Ensure the interrupts are clear as they are edge detected. */ | |
IR( TMR0, CMIA0 ) = 0; | |
IR( TMR2, CMIA2 ) = 0; | |
} | |
/*-----------------------------------------------------------*/ | |
void vT0_1_ISR_Handler( void ) | |
{ | |
/* Re-enabled interrupts. */ | |
__asm volatile( "SETPSW I" ); | |
/* Call the handler that is part of the common code - this is where the | |
non-portable code ends and the actual test is performed. */ | |
portYIELD_FROM_ISR( xFirstTimerHandler() ); | |
} | |
/*-----------------------------------------------------------*/ | |
void vT2_3_ISR_Handler( void ) | |
{ | |
/* Re-enabled interrupts. */ | |
__asm volatile( "SETPSW I" ); | |
/* Call the handler that is part of the common code - this is where the | |
non-portable code ends and the actual test is performed. */ | |
portYIELD_FROM_ISR( xSecondTimerHandler() ); | |
} | |
/*-----------------------------------------------------------*/ | |