Armv8-M (except Cortex-M23) interrupt priority checking (#673)
* Armv8-M: Formatting changes
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
* Armv8-M: Add support for interrupt priority check
FreeRTOS provides `FromISR` system calls which can be called directly
from interrupt service routines. It is crucial that the priority of
these ISRs is set to same or lower value (numerically higher) than that
of `configMAX_SYSCALL_INTERRUPT_PRIORITY`. For more information refer
to https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html.
Add a check to trigger an assert when an ISR with priority higher
(numerically lower) than `configMAX_SYSCALL_INTERRUPT_PRIORITY` calls
`FromISR` system calls if `configASSERT` macro is defined.
In addition, add a config option
`configQEMU_DISABLE_INTERRUPT_PRIO_BITS_CHECK` to disable interrupt
priority check while running on QEMU. Based on the discussion
https://gitlab.com/qemu-project/qemu/-/issues/1122, The interrupt
priority bits in QEMU do not match the real hardware. Therefore the
assert that checks the number of implemented bits and __NVIC_PRIO_BITS
will always fail. The config option
`configQEMU_DISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
`FreeRTOSConfig.h` for QEMU targets.
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
* Use SHPR2 for calculating interrupt priority bits
This removes the dependency on the secure software to mark the interrupt
as non-secure.
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---------
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
index 6a2ed74..746f734 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -50,12 +48,17 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portDONT_DISCARD __attribute__( ( used ) )
-#define portNORETURN __attribute__( ( noreturn ) )
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_BASEPRI 0
+#define portDONT_DISCARD __attribute__( ( used ) )
+#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
-#if( configTOTAL_MPU_REGIONS == 16 )
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
/*-----------------------------------------------------------*/
@@ -63,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
index 6a2ed74..746f734 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -50,12 +48,17 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portDONT_DISCARD __attribute__( ( used ) )
-#define portNORETURN __attribute__( ( noreturn ) )
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_BASEPRI 0
+#define portDONT_DISCARD __attribute__( ( used ) )
+#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
-#if( configTOTAL_MPU_REGIONS == 16 )
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
/*-----------------------------------------------------------*/
@@ -63,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
index 27da496..19da9b0 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,10 +49,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M33"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
index 27da496..19da9b0 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,10 +49,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M33"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
index dfc8365..cc64345 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,10 +49,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M35P"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
index 3cde19a..c9bad40 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,10 +54,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M55"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
index 0fd11fc..c45dd21 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,10 +54,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M85"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
index b4d11df..9cf0e87 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -50,11 +48,16 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_BASEPRI 0
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
-#if( configTOTAL_MPU_REGIONS == 16 )
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
/*-----------------------------------------------------------*/
@@ -62,8 +65,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
index b4d11df..9cf0e87 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -50,11 +48,16 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_BASEPRI 0
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
-#if( configTOTAL_MPU_REGIONS == 16 )
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
/*-----------------------------------------------------------*/
@@ -62,8 +65,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
index cbfa602..380768f 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,6 +49,7 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M33"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
@@ -59,6 +58,10 @@
#endif
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
index cbfa602..815dca0 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,9 +49,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M33"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
index 70b73a3..46bc4e2 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,9 +49,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M35P"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
index 7783218..7829ee6 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,9 +54,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M55"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
index 7aba706..3b51cb5 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,9 +54,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M85"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h
index 6a2ed74..746f734 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -50,12 +48,17 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portDONT_DISCARD __attribute__( ( used ) )
-#define portNORETURN __attribute__( ( noreturn ) )
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_BASEPRI 0
+#define portDONT_DISCARD __attribute__( ( used ) )
+#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
-#if( configTOTAL_MPU_REGIONS == 16 )
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
/*-----------------------------------------------------------*/
@@ -63,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index 6a2ed74..746f734 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -50,12 +48,17 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portDONT_DISCARD __attribute__( ( used ) )
-#define portNORETURN __attribute__( ( noreturn ) )
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_BASEPRI 0
+#define portDONT_DISCARD __attribute__( ( used ) )
+#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
-#if( configTOTAL_MPU_REGIONS == 16 )
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
/*-----------------------------------------------------------*/
@@ -63,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h
index 27da496..19da9b0 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,10 +49,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M33"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index 27da496..19da9b0 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,10 +49,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M33"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
index dfc8365..cc64345 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,10 +49,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M35P"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
index dfc8365..cc64345 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,10 +49,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M35P"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacro.h b/portable/GCC/ARM_CM55/non_secure/portmacro.h
index 3cde19a..c9bad40 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,10 +54,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M55"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
index 3cde19a..c9bad40 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,10 +54,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M55"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacro.h b/portable/GCC/ARM_CM85/non_secure/portmacro.h
index 0fd11fc..c45dd21 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,10 +54,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M85"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
index 0fd11fc..c45dd21 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,10 +54,15 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M85"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __attribute__( ( used ) )
#define portNORETURN __attribute__( ( noreturn ) )
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h
index b4d11df..9cf0e87 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -50,11 +48,16 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_BASEPRI 0
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
-#if( configTOTAL_MPU_REGIONS == 16 )
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
/*-----------------------------------------------------------*/
@@ -62,8 +65,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index b4d11df..9cf0e87 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -50,11 +48,16 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_BASEPRI 0
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
-#if( configTOTAL_MPU_REGIONS == 16 )
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
+#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
/*-----------------------------------------------------------*/
@@ -62,8 +65,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h
index cbfa602..380768f 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,6 +49,7 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M33"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
@@ -59,6 +58,10 @@
#endif
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index cbfa602..815dca0 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,9 +49,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M33"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
index 70b73a3..46bc4e2 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,9 +49,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M35P"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
index 70b73a3..46bc4e2 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -51,9 +49,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M35P"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacro.h b/portable/IAR/ARM_CM55/non_secure/portmacro.h
index 7783218..7829ee6 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,9 +54,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M55"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
index 7783218..7829ee6 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,9 +54,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M55"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacro.h b/portable/IAR/ARM_CM85/non_secure/portmacro.h
index 7aba706..3b51cb5 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,9 +54,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M85"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 9976dae..7bbe1b7 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -95,6 +95,19 @@
/*-----------------------------------------------------------*/
/**
+ * @brief Constants required to check the validity of an interrupt priority.
+ */
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) )
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+/*-----------------------------------------------------------*/
+
+/**
* @brief Constants required to manipulate the FPU.
*/
#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
@@ -369,6 +382,19 @@
PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
#endif /* configENABLE_TRUSTZONE */
+/**
+ * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
@@ -944,6 +970,7 @@
}
}
/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#if ( configENABLE_MPU == 1 )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
@@ -1069,6 +1096,114 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint32_t ulImplementedPrioBits = 0;
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = portNVIC_SHPR2_REG;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ portNVIC_SHPR2_REG = 0xFF000000;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulImplementedPrioBits++;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ if( ulImplementedPrioBits == 8 )
+ {
+ /* When the hardware implements 8 priority bits, there is no way for
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+ ulMaxPRIGROUPValue = 0;
+ }
+ else
+ {
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+ }
+
+ /* The interrupt priority bits are not modelled in QEMU and the assert that
+ * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
+ * Therefore, this assert is not adding any value for QEMU targets. The config
+ * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
+ * `FreeRTOSConfig.h` for QEMU targets. */
+ #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
+ {
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
+ }
+ #endif /* __NVIC_PRIO_BITS */
+
+ #ifdef configPRIO_BITS
+ {
+ /*
+ * Check that the number of implemented priority bits queried from
+ * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
+ */
+ configASSERT( ulImplementedPrioBits == configPRIO_BITS );
+ }
+ #endif /* configPRIO_BITS */
+ }
+ #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ portNVIC_SHPR2_REG = ulOriginalPriority;
+ }
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -1259,3 +1394,64 @@
return xReturn;
}
/*-----------------------------------------------------------*/
+
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
index 7aba706..3b51cb5 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -35,8 +35,6 @@
#endif
/* *INDENT-ON* */
-#include "portmacrocommon.h"
-
/*------------------------------------------------------------------------------
* Port specific definitions.
*
@@ -56,9 +54,14 @@
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M85"
+#define portHAS_BASEPRI 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
+/* ARMv8-M common port configurations. */
+#include "portmacrocommon.h"
+/*-----------------------------------------------------------*/
+
#if( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index a6b5b98..c2ca5fa 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACROCOMMON_H
- #define PORTMACROCOMMON_H
+#define PORTMACROCOMMON_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -45,114 +45,114 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
/**
* @brief Type definitions.
*/
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
/*-----------------------------------------------------------*/
/**
* @brief Extern declarations.
*/
- extern BaseType_t xPortIsInsideInterrupt( void );
+extern BaseType_t xPortIsInsideInterrupt( void );
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
+#if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief MPU specific constants.
*/
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
+ #define configTOTAL_MPU_REGIONS ( 8UL )
#endif
/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
/* Device memory attributes used in MPU_MAIR registers.
*
@@ -164,92 +164,105 @@
* 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
/*-----------------------------------------------------------*/
/**
* @brief Settings to define an MPU region.
*/
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
/**
* @brief MPU settings as stored in the TCB.
*/
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
/*-----------------------------------------------------------*/
/**
+ * @brief Validate priority of ISRs that are allowed to call FreeRTOS
+ * system calls.
+ */
+#ifdef configASSERT
+ #if ( portHAS_BASEPRI == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+#endif
+
+/**
* @brief SVC numbers.
*/
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
/*-----------------------------------------------------------*/
/**
* @brief Scheduler utilities.
*/
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+ while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/**
* @brief Tickless idle/low power functionality.
*/
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Task function macros as described on the FreeRTOS.org WEB site.
*/
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #if ( configENABLE_TRUSTZONE == 1 )
+#if ( configENABLE_TRUSTZONE == 1 )
/**
* @brief Allocate a secure context for the task.
@@ -260,7 +273,7 @@
*
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
*/
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
/**
* @brief Called when a task is deleted to delete the task's secure context,
@@ -268,18 +281,18 @@
*
* @param[in] pxTCB The TCB of the task being deleted.
*/
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#endif /* configENABLE_TRUSTZONE */
/*-----------------------------------------------------------*/
- #if ( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+ #define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
@@ -288,24 +301,24 @@
* then it raises the privilege. If this is called from any other place,
* the privilege is not raised.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
/**
* @brief Barriers.
*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
