Remove unused library files from the STM32F100 TrueStudio project.
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h
deleted file mode 100644
index 26e725f..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h
+++ /dev/null
@@ -1,482 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_adc.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the ADC firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_ADC_H
-#define __STM32F10x_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/** @defgroup ADC_Exported_Types
- * @{
- */
-
-/**
- * @brief ADC Init structure definition
- */
-
-typedef struct
-{
- uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
- dual mode.
- This parameter can be a value of @ref ADC_mode */
-
- FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
- Scan (multichannels) or Single (one channel) mode.
- This parameter can be set to ENABLE or DISABLE */
-
- FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
- Continuous or Single mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
- to digital conversion of regular channels. This parameter
- can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
-
- uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
- This parameter can be a value of @ref ADC_data_align */
-
- uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
- using the sequencer for regular channel group.
- This parameter must range from 1 to 16. */
-}ADC_InitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Constants
- * @{
- */
-
-#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
- ((PERIPH) == ADC2) || \
- ((PERIPH) == ADC3))
-
-#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
- ((PERIPH) == ADC3))
-
-/** @defgroup ADC_mode
- * @{
- */
-
-#define ADC_Mode_Independent ((uint32_t)0x00000000)
-#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
-#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
-#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
-#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
-#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
-#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
-#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
-#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
-#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
-
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
- ((MODE) == ADC_Mode_RegInjecSimult) || \
- ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
- ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
- ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
- ((MODE) == ADC_Mode_InjecSimult) || \
- ((MODE) == ADC_Mode_RegSimult) || \
- ((MODE) == ADC_Mode_FastInterl) || \
- ((MODE) == ADC_Mode_SlowInterl) || \
- ((MODE) == ADC_Mode_AlterTrig))
-/**
- * @}
- */
-
-/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
- * @{
- */
-
-#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
-#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
-#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
-#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
-#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
-#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
-
-#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
-#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
-
-#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
-#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
-#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
-#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
-#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
-#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
-
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
- ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
- ((REGTRIG) == ADC_ExternalTrigConv_None) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
-/**
- * @}
- */
-
-/** @defgroup ADC_data_align
- * @{
- */
-
-#define ADC_DataAlign_Right ((uint32_t)0x00000000)
-#define ADC_DataAlign_Left ((uint32_t)0x00000800)
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
- ((ALIGN) == ADC_DataAlign_Left))
-/**
- * @}
- */
-
-/** @defgroup ADC_channels
- * @{
- */
-
-#define ADC_Channel_0 ((uint8_t)0x00)
-#define ADC_Channel_1 ((uint8_t)0x01)
-#define ADC_Channel_2 ((uint8_t)0x02)
-#define ADC_Channel_3 ((uint8_t)0x03)
-#define ADC_Channel_4 ((uint8_t)0x04)
-#define ADC_Channel_5 ((uint8_t)0x05)
-#define ADC_Channel_6 ((uint8_t)0x06)
-#define ADC_Channel_7 ((uint8_t)0x07)
-#define ADC_Channel_8 ((uint8_t)0x08)
-#define ADC_Channel_9 ((uint8_t)0x09)
-#define ADC_Channel_10 ((uint8_t)0x0A)
-#define ADC_Channel_11 ((uint8_t)0x0B)
-#define ADC_Channel_12 ((uint8_t)0x0C)
-#define ADC_Channel_13 ((uint8_t)0x0D)
-#define ADC_Channel_14 ((uint8_t)0x0E)
-#define ADC_Channel_15 ((uint8_t)0x0F)
-#define ADC_Channel_16 ((uint8_t)0x10)
-#define ADC_Channel_17 ((uint8_t)0x11)
-
-#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
-#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
- ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
- ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
- ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
- ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
- ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
- ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
- ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
- ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
-/**
- * @}
- */
-
-/** @defgroup ADC_sampling_time
- * @{
- */
-
-#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
-#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
-#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
-#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
-#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
-#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
-#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
-#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
- ((TIME) == ADC_SampleTime_7Cycles5) || \
- ((TIME) == ADC_SampleTime_13Cycles5) || \
- ((TIME) == ADC_SampleTime_28Cycles5) || \
- ((TIME) == ADC_SampleTime_41Cycles5) || \
- ((TIME) == ADC_SampleTime_55Cycles5) || \
- ((TIME) == ADC_SampleTime_71Cycles5) || \
- ((TIME) == ADC_SampleTime_239Cycles5))
-/**
- * @}
- */
-
-/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
- * @{
- */
-
-#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
-#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
-#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
-#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
-#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
-
-#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
-#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
-#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
-
-#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
-#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
-#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
-#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
-#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
-
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_channel_selection
- * @{
- */
-
-#define ADC_InjectedChannel_1 ((uint8_t)0x14)
-#define ADC_InjectedChannel_2 ((uint8_t)0x18)
-#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
-#define ADC_InjectedChannel_4 ((uint8_t)0x20)
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
- ((CHANNEL) == ADC_InjectedChannel_2) || \
- ((CHANNEL) == ADC_InjectedChannel_3) || \
- ((CHANNEL) == ADC_InjectedChannel_4))
-/**
- * @}
- */
-
-/** @defgroup ADC_analog_watchdog_selection
- * @{
- */
-
-#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
-#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
-#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
-#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
-#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
-
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_None))
-/**
- * @}
- */
-
-/** @defgroup ADC_interrupts_definition
- * @{
- */
-
-#define ADC_IT_EOC ((uint16_t)0x0220)
-#define ADC_IT_AWD ((uint16_t)0x0140)
-#define ADC_IT_JEOC ((uint16_t)0x0480)
-
-#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
-
-#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
- ((IT) == ADC_IT_JEOC))
-/**
- * @}
- */
-
-/** @defgroup ADC_flags_definition
- * @{
- */
-
-#define ADC_FLAG_AWD ((uint8_t)0x01)
-#define ADC_FLAG_EOC ((uint8_t)0x02)
-#define ADC_FLAG_JEOC ((uint8_t)0x04)
-#define ADC_FLAG_JSTRT ((uint8_t)0x08)
-#define ADC_FLAG_STRT ((uint8_t)0x10)
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
- ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
- ((FLAG) == ADC_FLAG_STRT))
-/**
- * @}
- */
-
-/** @defgroup ADC_thresholds
- * @{
- */
-
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_offset
- * @{
- */
-
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_length
- * @{
- */
-
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_rank
- * @{
- */
-
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_regular_length
- * @{
- */
-
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_rank
- * @{
- */
-
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_discontinuous_mode_number
- * @{
- */
-
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions
- * @{
- */
-
-void ADC_DeInit(ADC_TypeDef* ADCx);
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
-void ADC_ResetCalibration(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
-void ADC_StartCalibration(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
-void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
-uint32_t ADC_GetDualModeConversionValue(void);
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
-void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_ADC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h
deleted file mode 100644
index dc40ec2..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_bkp.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the BKP firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_BKP_H
-#define __STM32F10x_BKP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup BKP
- * @{
- */
-
-/** @defgroup BKP_Exported_Types
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup BKP_Exported_Constants
- * @{
- */
-
-/** @defgroup Tamper_Pin_active_level
- * @{
- */
-
-#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
-#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
-#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
- ((LEVEL) == BKP_TamperPinLevel_Low))
-/**
- * @}
- */
-
-/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
- * @{
- */
-
-#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
-#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
-#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
-#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
-#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
- ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
- ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
- ((SOURCE) == BKP_RTCOutputSource_Second))
-/**
- * @}
- */
-
-/** @defgroup Data_Backup_Register
- * @{
- */
-
-#define BKP_DR1 ((uint16_t)0x0004)
-#define BKP_DR2 ((uint16_t)0x0008)
-#define BKP_DR3 ((uint16_t)0x000C)
-#define BKP_DR4 ((uint16_t)0x0010)
-#define BKP_DR5 ((uint16_t)0x0014)
-#define BKP_DR6 ((uint16_t)0x0018)
-#define BKP_DR7 ((uint16_t)0x001C)
-#define BKP_DR8 ((uint16_t)0x0020)
-#define BKP_DR9 ((uint16_t)0x0024)
-#define BKP_DR10 ((uint16_t)0x0028)
-#define BKP_DR11 ((uint16_t)0x0040)
-#define BKP_DR12 ((uint16_t)0x0044)
-#define BKP_DR13 ((uint16_t)0x0048)
-#define BKP_DR14 ((uint16_t)0x004C)
-#define BKP_DR15 ((uint16_t)0x0050)
-#define BKP_DR16 ((uint16_t)0x0054)
-#define BKP_DR17 ((uint16_t)0x0058)
-#define BKP_DR18 ((uint16_t)0x005C)
-#define BKP_DR19 ((uint16_t)0x0060)
-#define BKP_DR20 ((uint16_t)0x0064)
-#define BKP_DR21 ((uint16_t)0x0068)
-#define BKP_DR22 ((uint16_t)0x006C)
-#define BKP_DR23 ((uint16_t)0x0070)
-#define BKP_DR24 ((uint16_t)0x0074)
-#define BKP_DR25 ((uint16_t)0x0078)
-#define BKP_DR26 ((uint16_t)0x007C)
-#define BKP_DR27 ((uint16_t)0x0080)
-#define BKP_DR28 ((uint16_t)0x0084)
-#define BKP_DR29 ((uint16_t)0x0088)
-#define BKP_DR30 ((uint16_t)0x008C)
-#define BKP_DR31 ((uint16_t)0x0090)
-#define BKP_DR32 ((uint16_t)0x0094)
-#define BKP_DR33 ((uint16_t)0x0098)
-#define BKP_DR34 ((uint16_t)0x009C)
-#define BKP_DR35 ((uint16_t)0x00A0)
-#define BKP_DR36 ((uint16_t)0x00A4)
-#define BKP_DR37 ((uint16_t)0x00A8)
-#define BKP_DR38 ((uint16_t)0x00AC)
-#define BKP_DR39 ((uint16_t)0x00B0)
-#define BKP_DR40 ((uint16_t)0x00B4)
-#define BKP_DR41 ((uint16_t)0x00B8)
-#define BKP_DR42 ((uint16_t)0x00BC)
-
-#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
- ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
- ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
- ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
- ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
- ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
- ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
- ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
- ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
- ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
- ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
- ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
- ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
- ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
-
-#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup BKP_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup BKP_Exported_Functions
- * @{
- */
-
-void BKP_DeInit(void);
-void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
-void BKP_TamperPinCmd(FunctionalState NewState);
-void BKP_ITConfig(FunctionalState NewState);
-void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
-void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
-void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
-uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
-FlagStatus BKP_GetFlagStatus(void);
-void BKP_ClearFlag(void);
-ITStatus BKP_GetITStatus(void);
-void BKP_ClearITPendingBit(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_BKP_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h
deleted file mode 100644
index 544d779..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h
+++ /dev/null
@@ -1,583 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_can.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the CAN firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CAN_H
-#define __STM32F10x_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CAN
- * @{
- */
-
-/** @defgroup CAN_Exported_Types
- * @{
- */
-
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
- ((PERIPH) == CAN2))
-
-/**
- * @brief CAN init structure definition
- */
-
-typedef struct
-{
- uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */
-
- uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
-
- uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware
- is allowed to lengthen or shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
- uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
- uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
- FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_InitTypeDef;
-
-/**
- * @brief CAN filter init structure definition
- */
-
-typedef struct
-{
- uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
- configuration, first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
- configuration, second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
- according to the mode (MSBs for a 32-bit configuration,
- first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
- according to the mode (LSBs for a 32-bit configuration,
- second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
- This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
-
- uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
- This parameter can be a value of @ref CAN_filter_mode */
-
- uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
- This parameter can be a value of @ref CAN_filter_scale */
-
- FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_FilterInitTypeDef;
-
-/**
- * @brief CAN Tx message structure definition
- */
-
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
- This parameter can be a value of @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter can be a value between 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */
-} CanTxMsg;
-
-/**
- * @brief CAN Rx message structure definition
- */
-
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter can be a value between 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */
-
- uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
- This parameter can be a value between 0 to 0xFF */
-} CanRxMsg;
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Exported_Constants
- * @{
- */
-
-/** @defgroup CAN_sleep_constants
- * @{
- */
-
-#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_operating_mode
- * @{
- */
-
-#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
-#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
-#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
-#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
- ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))
-/**
- * @}
- */
-
-/** @defgroup CAN_synchronisation_jump_width
- * @{
- */
-
-#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
- ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1
- * @{
- */
-
-#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
-#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
-#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
-#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
-#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
-#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
-#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
-#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2
- * @{
- */
-
-#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
-
-/**
- * @}
- */
-
-/** @defgroup CAN_clock_prescaler
- * @{
- */
-
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_number
- * @{
- */
-#ifndef STM32F10X_CL
- #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
-#else
- #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-#endif /* STM32F10X_CL */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode
- * @{
- */
-
-#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */
-#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
- ((MODE) == CAN_FilterMode_IdList))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_scale
- * @{
- */
-
-#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
- ((SCALE) == CAN_FilterScale_32bit))
-
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_FIFO
- * @{
- */
-
-#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
- ((FIFO) == CAN_FilterFIFO1))
-
-/**
- * @}
- */
-
-/** @defgroup Start_bank_filter_for_slave_CAN
- * @{
- */
-#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
-/**
- * @}
- */
-
-/** @defgroup CAN_Tx
- * @{
- */
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-
-/**
- * @}
- */
-
-/** @defgroup CAN_identifier_type
- * @{
- */
-
-#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
-#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))
-
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request
- * @{
- */
-
-#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
-#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-
-/**
- * @}
- */
-
-/** @defgroup CAN_transmit_constants
- * @{
- */
-
-#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */
-#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number_constants
- * @{
- */
-
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-
-/**
- * @}
- */
-
-/** @defgroup CAN_sleep_constants
- * @{
- */
-
-#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
-#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_wake_up_constants
- * @{
- */
-
-#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
-#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_flags
- * @{
- */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
-#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
-#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
-#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
-#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
-#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
-#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
-#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
-#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
-/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
-#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
-#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
-#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
-
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
- ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
- ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
- ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_SLAK ))
-
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
- ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
-/**
- * @}
- */
-
-
-/** @defgroup CAN_interrupts
- * @{
- */
-
-
-
-#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
-#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
-#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
-#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
-#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
-#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
-#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
-
-/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
-#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
-#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
-#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
-#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-
-
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
- ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Exported_Functions
- * @{
- */
-
-void CAN_DeInit(CAN_TypeDef* CANx);
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
-uint8_t CAN_Sleep(CAN_TypeDef* CANx);
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_CAN_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h
deleted file mode 100644
index 10aaba7..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_cec.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the CEC firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CEC_H
-#define __STM32F10x_CEC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CEC
- * @{
- */
-
-
-/** @defgroup CEC_Exported_Types
- * @{
- */
-
-/**
- * @brief CEC Init structure definition
- */
-typedef struct
-{
- uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
- This parameter can be a value of @ref CEC_BitTiming_Mode */
- uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
- This parameter can be a value of @ref CEC_BitPeriod_Mode */
-}CEC_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Exported_Constants
- * @{
- */
-
-/** @defgroup CEC_BitTiming_Mode
- * @{
- */
-#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
-#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
-
-#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
- ((MODE) == CEC_BitTimingErrFreeMode))
-/**
- * @}
- */
-
-/** @defgroup CEC_BitPeriod_Mode
- * @{
- */
-#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
-#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
-
-#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
- ((MODE) == CEC_BitPeriodFlexibleMode))
-/**
- * @}
- */
-
-
-/** @defgroup CEC_interrupts_definition
- * @{
- */
-#define CEC_IT_TERR CEC_CSR_TERR
-#define CEC_IT_TBTRF CEC_CSR_TBTRF
-#define CEC_IT_RERR CEC_CSR_RERR
-#define CEC_IT_RBTF CEC_CSR_RBTF
-#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
- ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
-/**
- * @}
- */
-
-
-/** @defgroup CEC_Own_Addres
- * @{
- */
-#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
-/**
- * @}
- */
-
-/** @defgroup CEC_Prescaler
- * @{
- */
-#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
-
-/**
- * @}
- */
-
-/** @defgroup CEC_flags_definition
- * @{
- */
-
-/**
- * @brief ESR register flags
- */
-#define CEC_FLAG_BTE ((uint32_t)0x10010000)
-#define CEC_FLAG_BPE ((uint32_t)0x10020000)
-#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
-#define CEC_FLAG_SBE ((uint32_t)0x10080000)
-#define CEC_FLAG_ACKE ((uint32_t)0x10100000)
-#define CEC_FLAG_LINE ((uint32_t)0x10200000)
-#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
-
-/**
- * @brief CSR register flags
- */
-#define CEC_FLAG_TEOM ((uint32_t)0x00000002)
-#define CEC_FLAG_TERR ((uint32_t)0x00000004)
-#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
-#define CEC_FLAG_RSOM ((uint32_t)0x00000010)
-#define CEC_FLAG_REOM ((uint32_t)0x00000020)
-#define CEC_FLAG_RERR ((uint32_t)0x00000040)
-#define CEC_FLAG_RBTF ((uint32_t)0x00000080)
-
-#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
- ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
- ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
- ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
- ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
- ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
- ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Exported_Functions
- * @{
- */
-void CEC_DeInit(void);
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_Cmd(FunctionalState NewState);
-void CEC_ITConfig(FunctionalState NewState);
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
-void CEC_SetPrescaler(uint16_t CEC_Prescaler);
-void CEC_SendDataByte(uint8_t Data);
-uint8_t CEC_ReceiveDataByte(void);
-void CEC_StartOfMessage(void);
-void CEC_EndOfMessageCmd(FunctionalState NewState);
-FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
-void CEC_ClearFlag(uint32_t CEC_FLAG);
-ITStatus CEC_GetITStatus(uint8_t CEC_IT);
-void CEC_ClearITPendingBit(uint16_t CEC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_CEC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
deleted file mode 100644
index 12acce0..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_crc.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the CRC firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CRC_H
-#define __STM32F10x_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CRC
- * @{
- */
-
-/** @defgroup CRC_Exported_Types
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Functions
- * @{
- */
-
-void CRC_ResetDR(void);
-uint32_t CRC_CalcCRC(uint32_t Data);
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t CRC_GetCRC(void);
-void CRC_SetIDRegister(uint8_t IDValue);
-uint8_t CRC_GetIDRegister(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_CRC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h
deleted file mode 100644
index 9abd636..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_dac.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the DAC firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_DAC_H
-#define __STM32F10x_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DAC
- * @{
- */
-
-/** @defgroup DAC_Exported_Types
- * @{
- */
-
-/**
- * @brief DAC Init structure definition
- */
-
-typedef struct
-{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
-
- uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
- are generated, or whether no wave is generated.
- This parameter can be a value of @ref DAC_wave_generation */
-
- uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
- the maximum amplitude triangle generation for the DAC channel.
- This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
-
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-}DAC_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Constants
- * @{
- */
-
-/** @defgroup DAC_trigger_selection
- * @{
- */
-
-#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
- only in High-density devices*/
-#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
- only in Connectivity line, Medium-density and Low-density Value Line devices */
-#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
- only in Medium-density and Low-density Value Line devices*/
-#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
- ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
- ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
- ((TRIGGER) == DAC_Trigger_Software))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @{
- */
-
-#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
-#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
-#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
- ((WAVE) == DAC_WaveGeneration_Noise) || \
- ((WAVE) == DAC_WaveGeneration_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_lfsrunmask_triangleamplitude
- * @{
- */
-
-#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
-#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
-#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
-#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
-#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
-#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
-#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
-#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
-#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
- ((VALUE) == DAC_TriangleAmplitude_1) || \
- ((VALUE) == DAC_TriangleAmplitude_3) || \
- ((VALUE) == DAC_TriangleAmplitude_7) || \
- ((VALUE) == DAC_TriangleAmplitude_15) || \
- ((VALUE) == DAC_TriangleAmplitude_31) || \
- ((VALUE) == DAC_TriangleAmplitude_63) || \
- ((VALUE) == DAC_TriangleAmplitude_127) || \
- ((VALUE) == DAC_TriangleAmplitude_255) || \
- ((VALUE) == DAC_TriangleAmplitude_511) || \
- ((VALUE) == DAC_TriangleAmplitude_1023) || \
- ((VALUE) == DAC_TriangleAmplitude_2047) || \
- ((VALUE) == DAC_TriangleAmplitude_4095))
-/**
- * @}
- */
-
-/** @defgroup DAC_output_buffer
- * @{
- */
-
-#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
-#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
- ((STATE) == DAC_OutputBuffer_Disable))
-/**
- * @}
- */
-
-/** @defgroup DAC_Channel_selection
- * @{
- */
-
-#define DAC_Channel_1 ((uint32_t)0x00000000)
-#define DAC_Channel_2 ((uint32_t)0x00000010)
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
- ((CHANNEL) == DAC_Channel_2))
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignement
- * @{
- */
-
-#define DAC_Align_12b_R ((uint32_t)0x00000000)
-#define DAC_Align_12b_L ((uint32_t)0x00000004)
-#define DAC_Align_8b_R ((uint32_t)0x00000008)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
- ((ALIGN) == DAC_Align_12b_L) || \
- ((ALIGN) == DAC_Align_8b_R))
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @{
- */
-
-#define DAC_Wave_Noise ((uint32_t)0x00000040)
-#define DAC_Wave_Triangle ((uint32_t)0x00000080)
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
- ((WAVE) == DAC_Wave_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_data
- * @{
- */
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
-/**
- * @}
- */
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-/** @defgroup DAC_interrupts_definition
- * @{
- */
-
-#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_flags_definition
- * @{
- */
-
-#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
-
-/**
- * @}
- */
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions
- * @{
- */
-
-void DAC_DeInit(void);
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
-#endif
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_DAC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
deleted file mode 100644
index 918e25f..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_dbgmcu.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the DBGMCU
- * firmware library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_DBGMCU_H
-#define __STM32F10x_DBGMCU_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DBGMCU
- * @{
- */
-
-/** @defgroup DBGMCU_Exported_Types
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Exported_Constants
- * @{
- */
-
-#define DBGMCU_SLEEP ((uint32_t)0x00000001)
-#define DBGMCU_STOP ((uint32_t)0x00000002)
-#define DBGMCU_STANDBY ((uint32_t)0x00000004)
-#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
-#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
-#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
-#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
-#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
-#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
-#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
-#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
-#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
-#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
-#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
-#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
-#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
-#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
-#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
-#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
-#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
-#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
-#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
-#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
-#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
-#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
-#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
-
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Exported_Functions
- * @{
- */
-
-uint32_t DBGMCU_GetREVID(void);
-uint32_t DBGMCU_GetDEVID(void);
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_DBGMCU_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
deleted file mode 100644
index 2c5302b..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
+++ /dev/null
@@ -1,438 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_dma.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the DMA firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_DMA_H
-#define __STM32F10x_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/** @defgroup DMA_Exported_Types
- * @{
- */
-
-/**
- * @brief DMA Init structure definition
- */
-
-typedef struct
-{
- uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
-
- uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
-
- uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
- This parameter can be a value of @ref DMA_data_transfer_direction */
-
- uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
- The data unit is equal to the configuration set in DMA_PeripheralDataSize
- or DMA_MemoryDataSize members depending in the transfer direction. */
-
- uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
- This parameter can be a value of @ref DMA_peripheral_incremented_mode */
-
- uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
- This parameter can be a value of @ref DMA_memory_incremented_mode */
-
- uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_peripheral_data_size */
-
- uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_memory_data_size */
-
- uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
- This parameter can be a value of @ref DMA_circular_normal_mode.
- @note: The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
-
- uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
- This parameter can be a value of @ref DMA_priority_level */
-
- uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
- This parameter can be a value of @ref DMA_memory_to_memory */
-}DMA_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Constants
- * @{
- */
-
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
- ((PERIPH) == DMA1_Channel2) || \
- ((PERIPH) == DMA1_Channel3) || \
- ((PERIPH) == DMA1_Channel4) || \
- ((PERIPH) == DMA1_Channel5) || \
- ((PERIPH) == DMA1_Channel6) || \
- ((PERIPH) == DMA1_Channel7) || \
- ((PERIPH) == DMA2_Channel1) || \
- ((PERIPH) == DMA2_Channel2) || \
- ((PERIPH) == DMA2_Channel3) || \
- ((PERIPH) == DMA2_Channel4) || \
- ((PERIPH) == DMA2_Channel5))
-
-/** @defgroup DMA_data_transfer_direction
- * @{
- */
-
-#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
-#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
-#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
- ((DIR) == DMA_DIR_PeripheralSRC))
-/**
- * @}
- */
-
-/** @defgroup DMA_peripheral_incremented_mode
- * @{
- */
-
-#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
- ((STATE) == DMA_PeripheralInc_Disable))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_incremented_mode
- * @{
- */
-
-#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
- ((STATE) == DMA_MemoryInc_Disable))
-/**
- * @}
- */
-
-/** @defgroup DMA_peripheral_data_size
- * @{
- */
-
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
-#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
- ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
- ((SIZE) == DMA_PeripheralDataSize_Word))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_data_size
- * @{
- */
-
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
-#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
- ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
- ((SIZE) == DMA_MemoryDataSize_Word))
-/**
- * @}
- */
-
-/** @defgroup DMA_circular_normal_mode
- * @{
- */
-
-#define DMA_Mode_Circular ((uint32_t)0x00000020)
-#define DMA_Mode_Normal ((uint32_t)0x00000000)
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
-/**
- * @}
- */
-
-/** @defgroup DMA_priority_level
- * @{
- */
-
-#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
-#define DMA_Priority_High ((uint32_t)0x00002000)
-#define DMA_Priority_Medium ((uint32_t)0x00001000)
-#define DMA_Priority_Low ((uint32_t)0x00000000)
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
- ((PRIORITY) == DMA_Priority_High) || \
- ((PRIORITY) == DMA_Priority_Medium) || \
- ((PRIORITY) == DMA_Priority_Low))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_to_memory
- * @{
- */
-
-#define DMA_M2M_Enable ((uint32_t)0x00004000)
-#define DMA_M2M_Disable ((uint32_t)0x00000000)
-#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
-
-/**
- * @}
- */
-
-/** @defgroup DMA_interrupts_definition
- * @{
- */
-
-#define DMA_IT_TC ((uint32_t)0x00000002)
-#define DMA_IT_HT ((uint32_t)0x00000004)
-#define DMA_IT_TE ((uint32_t)0x00000008)
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
-
-#define DMA1_IT_GL1 ((uint32_t)0x00000001)
-#define DMA1_IT_TC1 ((uint32_t)0x00000002)
-#define DMA1_IT_HT1 ((uint32_t)0x00000004)
-#define DMA1_IT_TE1 ((uint32_t)0x00000008)
-#define DMA1_IT_GL2 ((uint32_t)0x00000010)
-#define DMA1_IT_TC2 ((uint32_t)0x00000020)
-#define DMA1_IT_HT2 ((uint32_t)0x00000040)
-#define DMA1_IT_TE2 ((uint32_t)0x00000080)
-#define DMA1_IT_GL3 ((uint32_t)0x00000100)
-#define DMA1_IT_TC3 ((uint32_t)0x00000200)
-#define DMA1_IT_HT3 ((uint32_t)0x00000400)
-#define DMA1_IT_TE3 ((uint32_t)0x00000800)
-#define DMA1_IT_GL4 ((uint32_t)0x00001000)
-#define DMA1_IT_TC4 ((uint32_t)0x00002000)
-#define DMA1_IT_HT4 ((uint32_t)0x00004000)
-#define DMA1_IT_TE4 ((uint32_t)0x00008000)
-#define DMA1_IT_GL5 ((uint32_t)0x00010000)
-#define DMA1_IT_TC5 ((uint32_t)0x00020000)
-#define DMA1_IT_HT5 ((uint32_t)0x00040000)
-#define DMA1_IT_TE5 ((uint32_t)0x00080000)
-#define DMA1_IT_GL6 ((uint32_t)0x00100000)
-#define DMA1_IT_TC6 ((uint32_t)0x00200000)
-#define DMA1_IT_HT6 ((uint32_t)0x00400000)
-#define DMA1_IT_TE6 ((uint32_t)0x00800000)
-#define DMA1_IT_GL7 ((uint32_t)0x01000000)
-#define DMA1_IT_TC7 ((uint32_t)0x02000000)
-#define DMA1_IT_HT7 ((uint32_t)0x04000000)
-#define DMA1_IT_TE7 ((uint32_t)0x08000000)
-
-#define DMA2_IT_GL1 ((uint32_t)0x10000001)
-#define DMA2_IT_TC1 ((uint32_t)0x10000002)
-#define DMA2_IT_HT1 ((uint32_t)0x10000004)
-#define DMA2_IT_TE1 ((uint32_t)0x10000008)
-#define DMA2_IT_GL2 ((uint32_t)0x10000010)
-#define DMA2_IT_TC2 ((uint32_t)0x10000020)
-#define DMA2_IT_HT2 ((uint32_t)0x10000040)
-#define DMA2_IT_TE2 ((uint32_t)0x10000080)
-#define DMA2_IT_GL3 ((uint32_t)0x10000100)
-#define DMA2_IT_TC3 ((uint32_t)0x10000200)
-#define DMA2_IT_HT3 ((uint32_t)0x10000400)
-#define DMA2_IT_TE3 ((uint32_t)0x10000800)
-#define DMA2_IT_GL4 ((uint32_t)0x10001000)
-#define DMA2_IT_TC4 ((uint32_t)0x10002000)
-#define DMA2_IT_HT4 ((uint32_t)0x10004000)
-#define DMA2_IT_TE4 ((uint32_t)0x10008000)
-#define DMA2_IT_GL5 ((uint32_t)0x10010000)
-#define DMA2_IT_TC5 ((uint32_t)0x10020000)
-#define DMA2_IT_HT5 ((uint32_t)0x10040000)
-#define DMA2_IT_TE5 ((uint32_t)0x10080000)
-
-#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
-
-#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
- ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
- ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
- ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
- ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
- ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
- ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
- ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
- ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
- ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
- ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
- ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
- ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
- ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
- ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
- ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
- ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
- ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
- ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
- ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
- ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
- ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
- ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
- ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
-
-/**
- * @}
- */
-
-/** @defgroup DMA_flags_definition
- * @{
- */
-#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
-#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
-#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
-#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
-#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
-#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
-#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
-#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
-#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
-#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
-#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
-#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
-#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
-#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
-#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
-#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
-#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
-#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
-#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
-#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
-#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
-#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
-#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
-#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
-#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
-#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
-#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
-#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
-
-#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
-#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
-#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
-#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
-#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
-#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
-#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
-#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
-#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
-#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
-#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
-#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
-#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
-#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
-#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
-#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
-#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
-#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
-#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
-#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
-
-#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
-
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
- ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
- ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
- ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
- ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
- ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
- ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
- ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
- ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
- ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
- ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
- ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
- ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
- ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
- ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
- ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
- ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
- ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
- ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
- ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
- ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
- ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
- ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
- ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
-/**
- * @}
- */
-
-/** @defgroup DMA_Buffer_Size
- * @{
- */
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions
- * @{
- */
-
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
-void DMA_ClearFlag(uint32_t DMA_FLAG);
-ITStatus DMA_GetITStatus(uint32_t DMA_IT);
-void DMA_ClearITPendingBit(uint32_t DMA_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_DMA_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h
deleted file mode 100644
index 5e2047d..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h
+++ /dev/null
@@ -1,425 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_flash.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the FLASH
- * firmware library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_FLASH_H
-#define __STM32F10x_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/** @defgroup FLASH_Exported_Types
- * @{
- */
-
-/**
- * @brief FLASH Status
- */
-
-typedef enum
-{
- FLASH_BUSY = 1,
- FLASH_ERROR_PG,
- FLASH_ERROR_WRP,
- FLASH_COMPLETE,
- FLASH_TIMEOUT
-}FLASH_Status;
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Constants
- * @{
- */
-
-/** @defgroup Flash_Latency
- * @{
- */
-
-#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
-#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
-#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
- ((LATENCY) == FLASH_Latency_1) || \
- ((LATENCY) == FLASH_Latency_2))
-/**
- * @}
- */
-
-/** @defgroup Half_Cycle_Enable_Disable
- * @{
- */
-
-#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
-#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
-#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
- ((STATE) == FLASH_HalfCycleAccess_Disable))
-/**
- * @}
- */
-
-/** @defgroup Prefetch_Buffer_Enable_Disable
- * @{
- */
-
-#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
-#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
-#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
- ((STATE) == FLASH_PrefetchBuffer_Disable))
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_Write_Protection
- * @{
- */
-
-/* Values to be used with STM32 Low and Medium density devices */
-#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
-#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
-#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
-#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
-#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
-#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
-#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
-#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
-
-/* Values to be used with STM32 Medium-density devices */
-#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
-#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
-#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
-#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
-#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
-#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
-#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
-#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
-#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
-#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
-#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
-#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
-#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
-#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
-#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
-#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
-#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
-#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
-#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
-#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
-#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
-#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
-#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
-#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
-
-/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
-#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 0 to 1 */
-#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 2 to 3 */
-#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 4 to 5 */
-#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 6 to 7 */
-#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 8 to 9 */
-#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 10 to 11 */
-#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 12 to 13 */
-#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 14 to 15 */
-#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 16 to 17 */
-#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 18 to 19 */
-#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 20 to 21 */
-#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 22 to 23 */
-#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 24 to 25 */
-#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 26 to 27 */
-#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 28 to 29 */
-#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 30 to 31 */
-#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 32 to 33 */
-#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 34 to 35 */
-#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 36 to 37 */
-#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 38 to 39 */
-#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 40 to 41 */
-#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 42 to 43 */
-#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 44 to 45 */
-#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 46 to 47 */
-#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 48 to 49 */
-#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 50 to 51 */
-#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 52 to 53 */
-#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 54 to 55 */
-#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 56 to 57 */
-#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 58 to 59 */
-#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
- Write protection of page 60 to 61 */
-#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
-#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
-#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
-
-#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
-
-#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
-
-#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
-
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_IWatchdog
- * @{
- */
-
-#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_nRST_STOP
- * @{
- */
-
-#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_nRST_STDBY
- * @{
- */
-
-#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-
-#ifdef STM32F10X_XL
-/**
- * @}
- */
-/** @defgroup FLASH_Boot
- * @{
- */
-#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
- and this parameter is selected the device will boot from Bank1(Default) */
-#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
- and this parameter is selected the device will boot from Bank 2 or Bank 1,
- depending on the activation of the bank */
-#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
-#endif
-/**
- * @}
- */
-/** @defgroup FLASH_Interrupts
- * @{
- */
-#ifdef STM32F10X_XL
-#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */
-#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */
-
-#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
-#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
-
-#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */
-#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
-#else
-#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
-#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
-#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
-
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Flags
- * @{
- */
-#ifdef STM32F10X_XL
-#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */
-#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */
-#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */
-#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */
-
-#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
-#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
-#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
-#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
-
-#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
-#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
-#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
-#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
-
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
- ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
- ((FLAG) == FLASH_FLAG_OPTERR)|| \
- ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
- ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
- ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
- ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
-#else
-#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
-#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
-#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
-#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
-
-#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
-#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
-#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
-#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
-
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
- ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
- ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
- ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
- ((FLAG) == FLASH_FLAG_OPTERR))
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions
- * @{
- */
-
-/*------------ Functions used for all STM32F10x devices -----*/
-void FLASH_SetLatency(uint32_t FLASH_Latency);
-void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
-void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
-void FLASH_Unlock(void);
-void FLASH_Lock(void);
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
-FLASH_Status FLASH_EraseAllPages(void);
-FLASH_Status FLASH_EraseOptionBytes(void);
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
-FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
-FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
-FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
-uint32_t FLASH_GetUserOptionByte(void);
-uint32_t FLASH_GetWriteProtectionOptionByte(void);
-FlagStatus FLASH_GetReadOutProtectionStatus(void);
-FlagStatus FLASH_GetPrefetchBufferStatus(void);
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
-
-/*------------ New function used for all STM32F10x devices -----*/
-void FLASH_UnlockBank1(void);
-void FLASH_LockBank1(void);
-FLASH_Status FLASH_EraseAllBank1Pages(void);
-FLASH_Status FLASH_GetBank1Status(void);
-FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
-
-#ifdef STM32F10X_XL
-/*---- New Functions used only with STM32F10x_XL density devices -----*/
-void FLASH_UnlockBank2(void);
-void FLASH_LockBank2(void);
-FLASH_Status FLASH_EraseAllBank2Pages(void);
-FLASH_Status FLASH_GetBank2Status(void);
-FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
-FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_FLASH_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h
deleted file mode 100644
index 9cf9847..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h
+++ /dev/null
@@ -1,732 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_fsmc.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the FSMC firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_FSMC_H
-#define __STM32F10x_FSMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FSMC
- * @{
- */
-
-/** @defgroup FSMC_Exported_Types
- * @{
- */
-
-/**
- * @brief Timing parameters For NOR/SRAM Banks
- */
-
-typedef struct
-{
- uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between 0 and 0xF.
- @note: It is not used with synchronous NOR Flash memories. */
-
- uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between 0 and 0xF.
- @note: It is not used with synchronous NOR Flash memories.*/
-
- uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between 0 and 0xFF.
- @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
-
- uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between 0 and 0xF.
- @note: It is only used for multiplexed NOR Flash memories. */
-
- uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
- This parameter can be a value between 1 and 0xF.
- @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
-
- uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The value of this parameter depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is dont care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between 0 and 0xF in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
-}FSMC_NORSRAMTimingInitTypeDef;
-
-/**
- * @brief FSMC NOR/SRAM Init structure definition
- */
-
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
- uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the databus or not.
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
- uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory bank.
- This parameter can be a value of @ref FSMC_Memory_Type */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
- uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FSMC_AsynchronousWait */
-
- uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
- uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FSMC_Wrap_Mode */
-
- uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Timing */
-
- uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
- This parameter can be a value of @ref FSMC_Write_Operation */
-
- uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal */
-
- uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FSMC_Extended_Mode */
-
- uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
-}FSMC_NORSRAMInitTypeDef;
-
-/**
- * @brief Timing parameters For FSMC NAND and PCCARD Banks
- */
-
-typedef struct
-{
- uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND-Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between 0 and 0xFF.*/
-
- uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND-Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command deassertion
- for NAND-Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- databus is kept in HiZ after the start of a NAND-Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-}FSMC_NAND_PCCARDTimingInitTypeDef;
-
-/**
- * @brief FSMC NAND Init structure definition
- */
-
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FSMC_ECC */
-
- uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-}FSMC_NANDInitTypeDef;
-
-/**
- * @brief FSMC PCCARD Init structure definition
- */
-
-typedef struct
-{
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
-}FSMC_PCCARDInitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Exported_Constants
- * @{
- */
-
-/** @defgroup FSMC_NORSRAM_Bank
- * @{
- */
-#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
-#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
-#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
-#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Bank
- * @{
- */
-#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
-#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Bank
- * @{
- */
-#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
-/**
- * @}
- */
-
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
- ((BANK) == FSMC_Bank1_NORSRAM2) || \
- ((BANK) == FSMC_Bank1_NORSRAM3) || \
- ((BANK) == FSMC_Bank1_NORSRAM4))
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND))
-
-#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-/** @defgroup NOR_SRAM_Controller
- * @{
- */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing
- * @{
- */
-
-#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
-#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
- ((MUX) == FSMC_DataAddressMux_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Memory_Type
- * @{
- */
-
-#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
-#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
-#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
- ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
- ((MEMORY) == FSMC_MemoryType_NOR))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Width
- * @{
- */
-
-#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
-#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
- ((WIDTH) == FSMC_MemoryDataWidth_16b))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Burst_Access_Mode
- * @{
- */
-
-#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
-#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
- ((STATE) == FSMC_BurstAccessMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_AsynchronousWait
- * @{
- */
-#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
-#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
- ((STATE) == FSMC_AsynchronousWait_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal_Polarity
- * @{
- */
-
-#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
-#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
- ((POLARITY) == FSMC_WaitSignalPolarity_High))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wrap_Mode
- * @{
- */
-
-#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
-#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
- ((MODE) == FSMC_WrapMode_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Timing
- * @{
- */
-
-#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
-#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
- ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Operation
- * @{
- */
-
-#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
- ((OPERATION) == FSMC_WriteOperation_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal
- * @{
- */
-
-#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
-#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
- ((SIGNAL) == FSMC_WaitSignal_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Extended_Mode
- * @{
- */
-
-#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
-#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
-
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
- ((MODE) == FSMC_ExtendedMode_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Burst
- * @{
- */
-
-#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
- ((BURST) == FSMC_WriteBurst_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Setup_Time
- * @{
- */
-
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Hold_Time
- * @{
- */
-
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Setup_Time
- * @{
- */
-
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration
- * @{
- */
-
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_CLK_Division
- * @{
- */
-
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Latency
- * @{
- */
-
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Access_Mode
- * @{
- */
-
-#define FSMC_AccessMode_A ((uint32_t)0x00000000)
-#define FSMC_AccessMode_B ((uint32_t)0x10000000)
-#define FSMC_AccessMode_C ((uint32_t)0x20000000)
-#define FSMC_AccessMode_D ((uint32_t)0x30000000)
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
- ((MODE) == FSMC_AccessMode_B) || \
- ((MODE) == FSMC_AccessMode_C) || \
- ((MODE) == FSMC_AccessMode_D))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup NAND_PCCARD_Controller
- * @{
- */
-
-/** @defgroup FSMC_Wait_feature
- * @{
- */
-
-#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
-#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
- ((FEATURE) == FSMC_Waitfeature_Enable))
-
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_ECC
- * @{
- */
-
-#define FSMC_ECC_Disable ((uint32_t)0x00000000)
-#define FSMC_ECC_Enable ((uint32_t)0x00000040)
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
- ((STATE) == FSMC_ECC_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_ECC_Page_Size
- * @{
- */
-
-#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
-#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
-#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
-#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
-#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
-#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_8192Bytes))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_TCLR_Setup_Time
- * @{
- */
-
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_TAR_Setup_Time
- * @{
- */
-
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Setup_Time
- * @{
- */
-
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Setup_Time
- * @{
- */
-
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Hold_Setup_Time
- * @{
- */
-
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_HiZ_Setup_Time
- * @{
- */
-
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Interrupt_sources
- * @{
- */
-
-#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
-#define FSMC_IT_Level ((uint32_t)0x00000010)
-#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
- ((IT) == FSMC_IT_Level) || \
- ((IT) == FSMC_IT_FallingEdge))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Flags
- * @{
- */
-
-#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
-#define FSMC_FLAG_Level ((uint32_t)0x00000002)
-#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
-#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
- ((FLAG) == FSMC_FLAG_Level) || \
- ((FLAG) == FSMC_FLAG_FallingEdge) || \
- ((FLAG) == FSMC_FLAG_FEMPT))
-
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Exported_Functions
- * @{
- */
-
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
-void FSMC_NANDDeInit(uint32_t FSMC_Bank);
-void FSMC_PCCARDDeInit(void);
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_PCCARDCmd(FunctionalState NewState);
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_FSMC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h
deleted file mode 100644
index 4726509..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h
+++ /dev/null
@@ -1,670 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_i2c.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the I2C firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_I2C_H
-#define __STM32F10x_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/** @defgroup I2C_Exported_Types
- * @{
- */
-
-/**
- * @brief I2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz */
-
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.
- This parameter can be a value of @ref I2C_mode */
-
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref I2C_acknowledgement */
-
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref I2C_acknowledged_address */
-}I2C_InitTypeDef;
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
- ((PERIPH) == I2C2))
-/** @defgroup I2C_mode
- * @{
- */
-
-#define I2C_Mode_I2C ((uint16_t)0x0000)
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
- ((MODE) == I2C_Mode_SMBusDevice) || \
- ((MODE) == I2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode
- * @{
- */
-
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
- ((CYCLE) == I2C_DutyCycle_2))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledgement
- * @{
- */
-
-#define I2C_Ack_Enable ((uint16_t)0x0400)
-#define I2C_Ack_Disable ((uint16_t)0x0000)
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
- ((STATE) == I2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_transfer_direction
- * @{
- */
-
-#define I2C_Direction_Transmitter ((uint8_t)0x00)
-#define I2C_Direction_Receiver ((uint8_t)0x01)
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
- ((DIRECTION) == I2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledged_address
- * @{
- */
-
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup I2C_registers
- * @{
- */
-
-#define I2C_Register_CR1 ((uint8_t)0x00)
-#define I2C_Register_CR2 ((uint8_t)0x04)
-#define I2C_Register_OAR1 ((uint8_t)0x08)
-#define I2C_Register_OAR2 ((uint8_t)0x0C)
-#define I2C_Register_DR ((uint8_t)0x10)
-#define I2C_Register_SR1 ((uint8_t)0x14)
-#define I2C_Register_SR2 ((uint8_t)0x18)
-#define I2C_Register_CCR ((uint8_t)0x1C)
-#define I2C_Register_TRISE ((uint8_t)0x20)
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
- ((REGISTER) == I2C_Register_CR2) || \
- ((REGISTER) == I2C_Register_OAR1) || \
- ((REGISTER) == I2C_Register_OAR2) || \
- ((REGISTER) == I2C_Register_DR) || \
- ((REGISTER) == I2C_Register_SR1) || \
- ((REGISTER) == I2C_Register_SR2) || \
- ((REGISTER) == I2C_Register_CCR) || \
- ((REGISTER) == I2C_Register_TRISE))
-/**
- * @}
- */
-
-/** @defgroup I2C_SMBus_alert_pin_level
- * @{
- */
-
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
- ((ALERT) == I2C_SMBusAlert_High))
-/**
- * @}
- */
-
-/** @defgroup I2C_PEC_position
- * @{
- */
-
-#define I2C_PECPosition_Next ((uint16_t)0x0800)
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
- ((POSITION) == I2C_PECPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_BUF ((uint16_t)0x0400)
-#define I2C_IT_EVT ((uint16_t)0x0200)
-#define I2C_IT_ERR ((uint16_t)0x0100)
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
-#define I2C_IT_PECERR ((uint32_t)0x01001000)
-#define I2C_IT_OVR ((uint32_t)0x01000800)
-#define I2C_IT_AF ((uint32_t)0x01000400)
-#define I2C_IT_ARLO ((uint32_t)0x01000200)
-#define I2C_IT_BERR ((uint32_t)0x01000100)
-#define I2C_IT_TXE ((uint32_t)0x06000080)
-#define I2C_IT_RXNE ((uint32_t)0x06000040)
-#define I2C_IT_STOPF ((uint32_t)0x02000010)
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)
-#define I2C_IT_BTF ((uint32_t)0x02000004)
-#define I2C_IT_ADDR ((uint32_t)0x02000002)
-#define I2C_IT_SB ((uint32_t)0x02000001)
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_flags_definition
- * @{
- */
-
-/**
- * @brief SR2 register flags
- */
-
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)
-
-/**
- * @brief SR1 register flags
- */
-
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)
-#define I2C_FLAG_AF ((uint32_t)0x10000400)
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
-#define I2C_FLAG_SB ((uint32_t)0x10000001)
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
- ((FLAG) == I2C_FLAG_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_Events
- * @{
- */
-
-/*========================================
-
- I2C Master Events (Events grouped in order of communication)
- ==========================================*/
-/**
- * @brief Communication start
- *
- * After sending the START condition (I2C_GenerateSTART() function) the master
- * has to wait for this event. It means that the Start condition has been correctly
- * released on the I2C bus (the bus is free, no other devices is communicating).
- *
- */
-/* --EV5 */
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
-
-/**
- * @brief Address Acknowledge
- *
- * After checking on EV5 (start condition correctly released on the bus), the
- * master sends the address of the slave(s) with which it will communicate
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
- * his address. If an acknowledge is sent on the bus, one of the following events will
- * be set:
- *
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
- * event is set.
- *
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
- * is set
- *
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
- * function). Then master should wait on EV9. It means that the 10-bit addressing
- * header has been correctly sent on the bus. Then master should send the second part of
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
- * should wait for event EV6.
- *
- */
-
-/* --EV6 */
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
-/* --EV9 */
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
-
-/**
- * @brief Communication events
- *
- * If a communication is established (START condition generated and slave address
- * acknowledged) then the master has to check on one of the following events for
- * communication procedures:
- *
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
- * the data received from the slave (I2C_ReceiveData() function).
- *
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
- * function) then to wait on event EV8 or EV8_2.
- * These two events are similar:
- * - EV8 means that the data has been written in the data register and is
- * being shifted out.
- * - EV8_2 means that the data has been physically shifted out and output
- * on the bus.
- * In most cases, using EV8 is sufficient for the application.
- * Using EV8_2 leads to a slower communication but ensure more reliable test.
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission
- * (before Stop condition generation).
- *
- * @note In case the user software does not guarantee that this event EV7 is
- * managed before the current byte end of transfer, then user may check on EV7
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Master RECEIVER mode -----------------------------*/
-/* --EV7 */
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
-
-/* Master TRANSMITTER mode --------------------------*/
-/* --EV8 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
-/* --EV8_2 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
-
-
-/*========================================
-
- I2C Slave Events (Events grouped in order of communication)
- ==========================================*/
-
-/**
- * @brief Communication start events
- *
- * Wait on one of these events at the start of the communication. It means that
- * the I2C peripheral detected a Start condition on the bus (generated by master
- * device) followed by the peripheral address. The peripheral generates an ACK
- * condition on the bus (if the acknowledge feature is enabled through function
- * I2C_AcknowledgeConfig()) and the events listed above are set :
- *
- * 1) In normal case (only one address managed by the slave), when the address
- * sent by the master matches the own address of the peripheral (configured by
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
- * (where XXX could be TRANSMITTER or RECEIVER).
- *
- * 2) In case the address sent by the master matches the second address of the
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
- * (where XXX could be TRANSMITTER or RECEIVER) are set.
- *
- * 3) In case the address sent by the master is General Call (address 0x00) and
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
- *
- */
-
-/* --EV1 (all the events below are variants of EV1) */
-/* 1) Case of One Single Address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
-
-/* 2) Case of Dual address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
-
-/* 3) Case of General Call enabled for the slave */
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
-
-/**
- * @brief Communication events
- *
- * Wait on one of these events when EV1 has already been checked and:
- *
- * - Slave RECEIVER mode:
- * - EV2: When the application is expecting a data byte to be received.
- * - EV4: When the application is expecting the end of the communication: master
- * sends a stop condition and data transmission is stopped.
- *
- * - Slave Transmitter mode:
- * - EV3: When a byte has been transmitted by the slave and the application is expecting
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
- * used when the user software doesn't guarantee the EV3 is managed before the
- * current byte end of tranfer.
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
- * shall end (before sending the STOP condition). In this case slave has to stop sending
- * data bytes and expect a Stop condition on the bus.
- *
- * @note In case the user software does not guarantee that the event EV2 is
- * managed before the current byte end of transfer, then user may check on EV2
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Slave RECEIVER mode --------------------------*/
-/* --EV2 */
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
-/* --EV4 */
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
-
-/* Slave TRANSMITTER mode -----------------------*/
-/* --EV3 */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
-/* --EV3_2 */
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
-
-/*=========================== End of Events Description ==========================================*/
-
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address1
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
-/**
- * @}
- */
-
-/** @defgroup I2C_clock_speed
- * @{
- */
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions
- * @{
- */
-
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
-
-/**
- * @brief
- ****************************************************************************************
- *
- * I2C State Monitoring Functions
- *
- ****************************************************************************************
- * This I2C driver provides three different ways for I2C state monitoring
- * depending on the application requirements and constraints:
- *
- *
- * 1) Basic state monitoring:
- * Using I2C_CheckEvent() function:
- * It compares the status registers (SR1 and SR2) content to a given event
- * (can be the combination of one or more flags).
- * It returns SUCCESS if the current status includes the given flags
- * and returns ERROR if one or more flags are missing in the current status.
- * - When to use:
- * - This function is suitable for most applications as well as for startup
- * activity since the events are fully described in the product reference manual
- * (RM0008).
- * - It is also suitable for users who need to define their own events.
- * - Limitations:
- * - If an error occurs (ie. error flags are set besides to the monitored flags),
- * the I2C_CheckEvent() function may return SUCCESS despite the communication
- * hold or corrupted real state.
- * In this case, it is advised to use error interrupts to monitor the error
- * events and handle them in the interrupt IRQ handler.
- *
- * @note
- * For error management, it is advised to use the following functions:
- * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.
- * Where x is the peripheral instance (I2C1, I2C2 ...)
- * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
- * in order to determine which error occured.
- * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- * and/or I2C_GenerateStop() in order to clear the error flag and source,
- * and return to correct communication status.
- *
- *
- * 2) Advanced state monitoring:
- * Using the function I2C_GetLastEvent() which returns the image of both status
- * registers in a single word (uint32_t) (Status Register 2 value is shifted left
- * by 16 bits and concatenated to Status Register 1).
- * - When to use:
- * - This function is suitable for the same applications above but it allows to
- * overcome the limitations of I2C_GetFlagStatus() function (see below).
- * The returned value could be compared to events already defined in the
- * library (stm32f10x_i2c.h) or to custom values defined by user.
- * - This function is suitable when multiple flags are monitored at the same time.
- * - At the opposite of I2C_CheckEvent() function, this function allows user to
- * choose when an event is accepted (when all events flags are set and no
- * other flags are set or just when the needed flags are set like
- * I2C_CheckEvent() function).
- * - Limitations:
- * - User may need to define his own events.
- * - Same remark concerning the error management is applicable for this
- * function if user decides to check only regular communication flags (and
- * ignores error flags).
- *
- *
- * 3) Flag-based state monitoring:
- * Using the function I2C_GetFlagStatus() which simply returns the status of
- * one single flag (ie. I2C_FLAG_RXNE ...).
- * - When to use:
- * - This function could be used for specific applications or in debug phase.
- * - It is suitable when only one flag checking is needed (most I2C events
- * are monitored through multiple flags).
- * - Limitations:
- * - When calling this function, the Status register is accessed. Some flags are
- * cleared when the status register is accessed. So checking the status
- * of one Flag, may clear other ones.
- * - Function may need to be called twice or more in order to monitor one
- * single event.
- *
- */
-
-/**
- *
- * 1) Basic state monitoring
- *******************************************************************************
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
-/**
- *
- * 2) Advanced state monitoring
- *******************************************************************************
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
-/**
- *
- * 3) Flag-based state monitoring
- *******************************************************************************
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-/**
- *
- *******************************************************************************
- */
-
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_I2C_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
deleted file mode 100644
index 4325ad4..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_iwdg.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the IWDG
- * firmware library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IWDG_H
-#define __STM32F10x_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup IWDG
- * @{
- */
-
-/** @defgroup IWDG_Exported_Types
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup IWDG_WriteAccess
- * @{
- */
-
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
- ((ACCESS) == IWDG_WriteAccess_Disable))
-/**
- * @}
- */
-
-/** @defgroup IWDG_prescaler
- * @{
- */
-
-#define IWDG_Prescaler_4 ((uint8_t)0x00)
-#define IWDG_Prescaler_8 ((uint8_t)0x01)
-#define IWDG_Prescaler_16 ((uint8_t)0x02)
-#define IWDG_Prescaler_32 ((uint8_t)0x03)
-#define IWDG_Prescaler_64 ((uint8_t)0x04)
-#define IWDG_Prescaler_128 ((uint8_t)0x05)
-#define IWDG_Prescaler_256 ((uint8_t)0x06)
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
- ((PRESCALER) == IWDG_Prescaler_8) || \
- ((PRESCALER) == IWDG_Prescaler_16) || \
- ((PRESCALER) == IWDG_Prescaler_32) || \
- ((PRESCALER) == IWDG_Prescaler_64) || \
- ((PRESCALER) == IWDG_Prescaler_128)|| \
- ((PRESCALER) == IWDG_Prescaler_256))
-/**
- * @}
- */
-
-/** @defgroup IWDG_Flag
- * @{
- */
-
-#define IWDG_FLAG_PVU ((uint16_t)0x0001)
-#define IWDG_FLAG_RVU ((uint16_t)0x0002)
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Exported_Functions
- * @{
- */
-
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
-void IWDG_SetReload(uint16_t Reload);
-void IWDG_ReloadCounter(void);
-void IWDG_Enable(void);
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_IWDG_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h
deleted file mode 100644
index ad93abd..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_pwr.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the PWR firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_PWR_H
-#define __STM32F10x_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/** @defgroup PWR_Exported_Types
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Constants
- * @{
- */
-
-/** @defgroup PVD_detection_level
- * @{
- */
-
-#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
-#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
-#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
-#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
-#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
-#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
-#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
-#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
- ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
- ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
- ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
-/**
- * @}
- */
-
-/** @defgroup Regulator_state_is_STOP_mode
- * @{
- */
-
-#define PWR_Regulator_ON ((uint32_t)0x00000000)
-#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
- ((REGULATOR) == PWR_Regulator_LowPower))
-/**
- * @}
- */
-
-/** @defgroup STOP_mode_entry
- * @{
- */
-
-#define PWR_STOPEntry_WFI ((uint8_t)0x01)
-#define PWR_STOPEntry_WFE ((uint8_t)0x02)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag
- * @{
- */
-
-#define PWR_FLAG_WU ((uint32_t)0x00000001)
-#define PWR_FLAG_SB ((uint32_t)0x00000002)
-#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
- ((FLAG) == PWR_FLAG_PVDO))
-
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Functions
- * @{
- */
-
-void PWR_DeInit(void);
-void PWR_BackupAccessCmd(FunctionalState NewState);
-void PWR_PVDCmd(FunctionalState NewState);
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
-void PWR_WakeUpPinCmd(FunctionalState NewState);
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterSTANDBYMode(void);
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
-void PWR_ClearFlag(uint32_t PWR_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_PWR_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h
deleted file mode 100644
index ac34ca9..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_rtc.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the RTC firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_RTC_H
-#define __STM32F10x_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/** @defgroup RTC_Exported_Types
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Constants
- * @{
- */
-
-/** @defgroup RTC_interrupts_define
- * @{
- */
-
-#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
-#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
-#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
-#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
- ((IT) == RTC_IT_SEC))
-/**
- * @}
- */
-
-/** @defgroup RTC_interrupts_flags
- * @{
- */
-
-#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
-#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
-#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
-#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
-#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
-#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
- ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
- ((FLAG) == RTC_FLAG_SEC))
-#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions
- * @{
- */
-
-void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
-void RTC_EnterConfigMode(void);
-void RTC_ExitConfigMode(void);
-uint32_t RTC_GetCounter(void);
-void RTC_SetCounter(uint32_t CounterValue);
-void RTC_SetPrescaler(uint32_t PrescalerValue);
-void RTC_SetAlarm(uint32_t AlarmValue);
-uint32_t RTC_GetDivider(void);
-void RTC_WaitForLastTask(void);
-void RTC_WaitForSynchro(void);
-FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
-void RTC_ClearFlag(uint16_t RTC_FLAG);
-ITStatus RTC_GetITStatus(uint16_t RTC_IT);
-void RTC_ClearITPendingBit(uint16_t RTC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_RTC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
deleted file mode 100644
index d15556c..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_sdio.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the SDIO firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_SDIO_H
-#define __STM32F10x_SDIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SDIO
- * @{
- */
-
-/** @defgroup SDIO_Exported_Types
- * @{
- */
-
-typedef struct
-{
- uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref SDIO_Clock_Edge */
-
- uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
- enabled or disabled.
- This parameter can be a value of @ref SDIO_Clock_Bypass */
-
- uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
- disabled when the bus is idle.
- This parameter can be a value of @ref SDIO_Clock_Power_Save */
-
- uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
- This parameter can be a value of @ref SDIO_Bus_Wide */
-
- uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
- This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
-
- uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
- This parameter can be a value between 0x00 and 0xFF. */
-
-} SDIO_InitTypeDef;
-
-typedef struct
-{
- uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
- to a card as part of a command message. If a command
- contains an argument, it must be loaded into this register
- before writing the command to the command register */
-
- uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
-
- uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
- This parameter can be a value of @ref SDIO_Response_Type */
-
- uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
- This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
-
- uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDIO_CPSM_State */
-} SDIO_CmdInitTypeDef;
-
-typedef struct
-{
- uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
-
- uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
-
- uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
- This parameter can be a value of @ref SDIO_Data_Block_Size */
-
- uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
- is a read or write.
- This parameter can be a value of @ref SDIO_Transfer_Direction */
-
- uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
- This parameter can be a value of @ref SDIO_Transfer_Type */
-
- uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDIO_DPSM_State */
-} SDIO_DataInitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Exported_Constants
- * @{
- */
-
-/** @defgroup SDIO_Clock_Edge
- * @{
- */
-
-#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
-#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
- ((EDGE) == SDIO_ClockEdge_Falling))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Clock_Bypass
- * @{
- */
-
-#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
-#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
- ((BYPASS) == SDIO_ClockBypass_Enable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Clock_Power_Save
- * @{
- */
-
-#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
-#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
- ((SAVE) == SDIO_ClockPowerSave_Enable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Bus_Wide
- * @{
- */
-
-#define SDIO_BusWide_1b ((uint32_t)0x00000000)
-#define SDIO_BusWide_4b ((uint32_t)0x00000800)
-#define SDIO_BusWide_8b ((uint32_t)0x00001000)
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
- ((WIDE) == SDIO_BusWide_8b))
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Hardware_Flow_Control
- * @{
- */
-
-#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
-#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
- ((CONTROL) == SDIO_HardwareFlowControl_Enable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Power_State
- * @{
- */
-
-#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
-#define SDIO_PowerState_ON ((uint32_t)0x00000003)
-#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
-/**
- * @}
- */
-
-
-/** @defgroup SDIO_Interrupt_soucres
- * @{
- */
-
-#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
-#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
-#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
-#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
-#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
-#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
-#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
-#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
-#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
-#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
-#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
-#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
-#define SDIO_IT_TXACT ((uint32_t)0x00001000)
-#define SDIO_IT_RXACT ((uint32_t)0x00002000)
-#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
-#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
-#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
-#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
-#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
-#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
-#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
-#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
-#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
-#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
-#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Command_Index
- * @{
- */
-
-#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
-/**
- * @}
- */
-
-/** @defgroup SDIO_Response_Type
- * @{
- */
-
-#define SDIO_Response_No ((uint32_t)0x00000000)
-#define SDIO_Response_Short ((uint32_t)0x00000040)
-#define SDIO_Response_Long ((uint32_t)0x000000C0)
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
- ((RESPONSE) == SDIO_Response_Short) || \
- ((RESPONSE) == SDIO_Response_Long))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Wait_Interrupt_State
- * @{
- */
-
-#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
-#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
-#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
- ((WAIT) == SDIO_Wait_Pend))
-/**
- * @}
- */
-
-/** @defgroup SDIO_CPSM_State
- * @{
- */
-
-#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
-#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Response_Registers
- * @{
- */
-
-#define SDIO_RESP1 ((uint32_t)0x00000000)
-#define SDIO_RESP2 ((uint32_t)0x00000004)
-#define SDIO_RESP3 ((uint32_t)0x00000008)
-#define SDIO_RESP4 ((uint32_t)0x0000000C)
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
- ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Data_Length
- * @{
- */
-
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
-/**
- * @}
- */
-
-/** @defgroup SDIO_Data_Block_Size
- * @{
- */
-
-#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
-#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
-#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
-#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
-#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
-#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
-#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
-#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
-#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
-#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
-#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
-#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
-#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
-#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
-#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
- ((SIZE) == SDIO_DataBlockSize_2b) || \
- ((SIZE) == SDIO_DataBlockSize_4b) || \
- ((SIZE) == SDIO_DataBlockSize_8b) || \
- ((SIZE) == SDIO_DataBlockSize_16b) || \
- ((SIZE) == SDIO_DataBlockSize_32b) || \
- ((SIZE) == SDIO_DataBlockSize_64b) || \
- ((SIZE) == SDIO_DataBlockSize_128b) || \
- ((SIZE) == SDIO_DataBlockSize_256b) || \
- ((SIZE) == SDIO_DataBlockSize_512b) || \
- ((SIZE) == SDIO_DataBlockSize_1024b) || \
- ((SIZE) == SDIO_DataBlockSize_2048b) || \
- ((SIZE) == SDIO_DataBlockSize_4096b) || \
- ((SIZE) == SDIO_DataBlockSize_8192b) || \
- ((SIZE) == SDIO_DataBlockSize_16384b))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Transfer_Direction
- * @{
- */
-
-#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
-#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
- ((DIR) == SDIO_TransferDir_ToSDIO))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Transfer_Type
- * @{
- */
-
-#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
-#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
- ((MODE) == SDIO_TransferMode_Block))
-/**
- * @}
- */
-
-/** @defgroup SDIO_DPSM_State
- * @{
- */
-
-#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
-#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Flags
- * @{
- */
-
-#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
-#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
-#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
-#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
-#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
-#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
-#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
-#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
-#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
-#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
-#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
-#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
-#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
-#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
-#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
-#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
-#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
-#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
-#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
-#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
-#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
-#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
-#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
-#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
-#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
- ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
- ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
- ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
- ((FLAG) == SDIO_FLAG_TXUNDERR) || \
- ((FLAG) == SDIO_FLAG_RXOVERR) || \
- ((FLAG) == SDIO_FLAG_CMDREND) || \
- ((FLAG) == SDIO_FLAG_CMDSENT) || \
- ((FLAG) == SDIO_FLAG_DATAEND) || \
- ((FLAG) == SDIO_FLAG_STBITERR) || \
- ((FLAG) == SDIO_FLAG_DBCKEND) || \
- ((FLAG) == SDIO_FLAG_CMDACT) || \
- ((FLAG) == SDIO_FLAG_TXACT) || \
- ((FLAG) == SDIO_FLAG_RXACT) || \
- ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
- ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
- ((FLAG) == SDIO_FLAG_TXFIFOF) || \
- ((FLAG) == SDIO_FLAG_RXFIFOF) || \
- ((FLAG) == SDIO_FLAG_TXFIFOE) || \
- ((FLAG) == SDIO_FLAG_RXFIFOE) || \
- ((FLAG) == SDIO_FLAG_TXDAVL) || \
- ((FLAG) == SDIO_FLAG_RXDAVL) || \
- ((FLAG) == SDIO_FLAG_SDIOIT) || \
- ((FLAG) == SDIO_FLAG_CEATAEND))
-
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
-
-#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
- ((IT) == SDIO_IT_DCRCFAIL) || \
- ((IT) == SDIO_IT_CTIMEOUT) || \
- ((IT) == SDIO_IT_DTIMEOUT) || \
- ((IT) == SDIO_IT_TXUNDERR) || \
- ((IT) == SDIO_IT_RXOVERR) || \
- ((IT) == SDIO_IT_CMDREND) || \
- ((IT) == SDIO_IT_CMDSENT) || \
- ((IT) == SDIO_IT_DATAEND) || \
- ((IT) == SDIO_IT_STBITERR) || \
- ((IT) == SDIO_IT_DBCKEND) || \
- ((IT) == SDIO_IT_CMDACT) || \
- ((IT) == SDIO_IT_TXACT) || \
- ((IT) == SDIO_IT_RXACT) || \
- ((IT) == SDIO_IT_TXFIFOHE) || \
- ((IT) == SDIO_IT_RXFIFOHF) || \
- ((IT) == SDIO_IT_TXFIFOF) || \
- ((IT) == SDIO_IT_RXFIFOF) || \
- ((IT) == SDIO_IT_TXFIFOE) || \
- ((IT) == SDIO_IT_RXFIFOE) || \
- ((IT) == SDIO_IT_TXDAVL) || \
- ((IT) == SDIO_IT_RXDAVL) || \
- ((IT) == SDIO_IT_SDIOIT) || \
- ((IT) == SDIO_IT_CEATAEND))
-
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Read_Wait_Mode
- * @{
- */
-
-#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
-#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
- ((MODE) == SDIO_ReadWaitMode_DATA2))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Exported_Functions
- * @{
- */
-
-void SDIO_DeInit(void);
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
-void SDIO_ClockCmd(FunctionalState NewState);
-void SDIO_SetPowerState(uint32_t SDIO_PowerState);
-uint32_t SDIO_GetPowerState(void);
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
-void SDIO_DMACmd(FunctionalState NewState);
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
-uint8_t SDIO_GetCommandResponse(void);
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-uint32_t SDIO_GetDataCounter(void);
-uint32_t SDIO_ReadData(void);
-void SDIO_WriteData(uint32_t Data);
-uint32_t SDIO_GetFIFOCount(void);
-void SDIO_StartSDIOReadWait(FunctionalState NewState);
-void SDIO_StopSDIOReadWait(FunctionalState NewState);
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
-void SDIO_SetSDIOOperation(FunctionalState NewState);
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
-void SDIO_CommandCompletionCmd(FunctionalState NewState);
-void SDIO_CEATAITCmd(FunctionalState NewState);
-void SDIO_SendCEATACmd(FunctionalState NewState);
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
-void SDIO_ClearFlag(uint32_t SDIO_FLAG);
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_SDIO_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
deleted file mode 100644
index 30b558b..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
+++ /dev/null
@@ -1,486 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_spi.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the SPI firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_SPI_H
-#define __STM32F10x_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/** @defgroup SPI_Exported_Types
- * @{
- */
-
-/**
- * @brief SPI Init structure definition
- */
-
-typedef struct
-{
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_data_direction */
-
- uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_mode */
-
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_data_size */
-
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler.
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
-}SPI_InitTypeDef;
-
-/**
- * @brief I2S Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
-
- uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
-
- uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
-
- uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
-
- uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
-
- uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
-}I2S_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Constants
- * @{
- */
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3))
-
-#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3))
-
-/** @defgroup SPI_data_direction
- * @{
- */
-
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \
- ((MODE) == SPI_Direction_1Line_Rx) || \
- ((MODE) == SPI_Direction_1Line_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_mode
- * @{
- */
-
-#define SPI_Mode_Master ((uint16_t)0x0104)
-#define SPI_Mode_Slave ((uint16_t)0x0000)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
- ((MODE) == SPI_Mode_Slave))
-/**
- * @}
- */
-
-/** @defgroup SPI_data_size
- * @{
- */
-
-#define SPI_DataSize_16b ((uint16_t)0x0800)
-#define SPI_DataSize_8b ((uint16_t)0x0000)
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
- ((DATASIZE) == SPI_DataSize_8b))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity
- * @{
- */
-
-#define SPI_CPOL_Low ((uint16_t)0x0000)
-#define SPI_CPOL_High ((uint16_t)0x0002)
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
- ((CPOL) == SPI_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase
- * @{
- */
-
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
- ((CPHA) == SPI_CPHA_2Edge))
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management
- * @{
- */
-
-#define SPI_NSS_Soft ((uint16_t)0x0200)
-#define SPI_NSS_Hard ((uint16_t)0x0000)
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
- ((NSS) == SPI_NSS_Hard))
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler
- * @{
- */
-
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_256))
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission
- * @{
- */
-
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)
-#define SPI_FirstBit_LSB ((uint16_t)0x0080)
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
- ((BIT) == SPI_FirstBit_LSB))
-/**
- * @}
- */
-
-/** @defgroup I2S_Mode
- * @{
- */
-
-#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
-#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
-#define I2S_Mode_MasterTx ((uint16_t)0x0200)
-#define I2S_Mode_MasterRx ((uint16_t)0x0300)
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
- ((MODE) == I2S_Mode_SlaveRx) || \
- ((MODE) == I2S_Mode_MasterTx) || \
- ((MODE) == I2S_Mode_MasterRx) )
-/**
- * @}
- */
-
-/** @defgroup I2S_Standard
- * @{
- */
-
-#define I2S_Standard_Phillips ((uint16_t)0x0000)
-#define I2S_Standard_MSB ((uint16_t)0x0010)
-#define I2S_Standard_LSB ((uint16_t)0x0020)
-#define I2S_Standard_PCMShort ((uint16_t)0x0030)
-#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
- ((STANDARD) == I2S_Standard_MSB) || \
- ((STANDARD) == I2S_Standard_LSB) || \
- ((STANDARD) == I2S_Standard_PCMShort) || \
- ((STANDARD) == I2S_Standard_PCMLong))
-/**
- * @}
- */
-
-/** @defgroup I2S_Data_Format
- * @{
- */
-
-#define I2S_DataFormat_16b ((uint16_t)0x0000)
-#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
-#define I2S_DataFormat_24b ((uint16_t)0x0003)
-#define I2S_DataFormat_32b ((uint16_t)0x0005)
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
- ((FORMAT) == I2S_DataFormat_16bextended) || \
- ((FORMAT) == I2S_DataFormat_24b) || \
- ((FORMAT) == I2S_DataFormat_32b))
-/**
- * @}
- */
-
-/** @defgroup I2S_MCLK_Output
- * @{
- */
-
-#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
-#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
- ((OUTPUT) == I2S_MCLKOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2S_Audio_Frequency
- * @{
- */
-
-#define I2S_AudioFreq_192k ((uint32_t)192000)
-#define I2S_AudioFreq_96k ((uint32_t)96000)
-#define I2S_AudioFreq_48k ((uint32_t)48000)
-#define I2S_AudioFreq_44k ((uint32_t)44100)
-#define I2S_AudioFreq_32k ((uint32_t)32000)
-#define I2S_AudioFreq_22k ((uint32_t)22050)
-#define I2S_AudioFreq_16k ((uint32_t)16000)
-#define I2S_AudioFreq_11k ((uint32_t)11025)
-#define I2S_AudioFreq_8k ((uint32_t)8000)
-#define I2S_AudioFreq_Default ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
- ((FREQ) <= I2S_AudioFreq_192k)) || \
- ((FREQ) == I2S_AudioFreq_Default))
-/**
- * @}
- */
-
-/** @defgroup I2S_Clock_Polarity
- * @{
- */
-
-#define I2S_CPOL_Low ((uint16_t)0x0000)
-#define I2S_CPOL_High ((uint16_t)0x0008)
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
- ((CPOL) == I2S_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_DMA_transfer_requests
- * @{
- */
-
-#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
-#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
-#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup SPI_NSS_internal_software_mangement
- * @{
- */
-
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Transmit_Receive
- * @{
- */
-
-#define SPI_CRC_Tx ((uint8_t)0x00)
-#define SPI_CRC_Rx ((uint8_t)0x01)
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
-/**
- * @}
- */
-
-/** @defgroup SPI_direction_transmit_receive
- * @{
- */
-
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx ((uint16_t)0x4000)
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
- ((DIRECTION) == SPI_Direction_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_interrupts_definition
- * @{
- */
-
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_I2S_IT_RXNE) || \
- ((IT) == SPI_I2S_IT_ERR))
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)
-#define SPI_IT_MODF ((uint8_t)0x55)
-#define SPI_IT_CRCERR ((uint8_t)0x54)
-#define I2S_IT_UDR ((uint8_t)0x53)
-#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
- ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_flags_definition
- * @{
- */
-
-#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
-#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
-#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
-#define I2S_FLAG_UDR ((uint16_t)0x0008)
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
-#define SPI_FLAG_MODF ((uint16_t)0x0020)
-#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
-#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
-#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
- ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_polynomial
- * @{
- */
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions
- * @{
- */
-
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_SPI_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
deleted file mode 100644
index 6529c0b..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
+++ /dev/null
@@ -1,1137 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_tim.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the TIM firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_TIM_H
-#define __STM32F10x_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/** @defgroup TIM_Exported_Types
- * @{
- */
-
-/**
- * @brief TIM Time Base Init structure definition
- * @note This sturcture is used with all TIMx except for TIM6 and TIM7.
- */
-
-typedef struct
-{
- uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between 0x0000 and 0xFFFF. */
-
- uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_Clock_Division_CKD */
-
- uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_TimeBaseInitTypeDef;
-
-/**
- * @brief TIM Output Compare Init structure definition
- */
-
-typedef struct
-{
- uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_state */
-
- uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_N_state
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OCInitTypeDef;
-
-/**
- * @brief TIM Input Capture Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t TIM_Channel; /*!< Specifies the TIM channel.
- This parameter can be a value of @ref TIM_Channel */
-
- uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint16_t TIM_ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between 0x0 and 0xF */
-} TIM_ICInitTypeDef;
-
-/**
- * @brief BDTR structure definition
- * @note This sturcture is used only with TIM1 and TIM8.
- */
-
-typedef struct
-{
-
- uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
-
- uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
-
- uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref Lock_level */
-
- uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
- switching-on of the outputs.
- This parameter can be a number between 0x00 and 0xFF */
-
- uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
- This parameter can be a value of @ref Break_Input_enable_disable */
-
- uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref Break_Polarity */
-
- uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BDTRInitTypeDef;
-
-/** @defgroup TIM_Exported_constants
- * @{
- */
-
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM10)|| \
- ((PERIPH) == TIM11)|| \
- ((PERIPH) == TIM12)|| \
- ((PERIPH) == TIM13)|| \
- ((PERIPH) == TIM14)|| \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST1: TIM 1 and 8 */
-#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM8))
-
-/* LIST2: TIM 1, 8, 15 16 and 17 */
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8))
-
-/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM15))
-
-/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
-#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM12)|| \
- ((PERIPH) == TIM15))
-
-/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
-#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM12)|| \
- ((PERIPH) == TIM15))
-
-/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */
-#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM10)|| \
- ((PERIPH) == TIM11)|| \
- ((PERIPH) == TIM12)|| \
- ((PERIPH) == TIM13)|| \
- ((PERIPH) == TIM14)|| \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
-#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes
- * @{
- */
-
-#define TIM_OCMode_Timing ((uint16_t)0x0000)
-#define TIM_OCMode_Active ((uint16_t)0x0010)
-#define TIM_OCMode_Inactive ((uint16_t)0x0020)
-#define TIM_OCMode_Toggle ((uint16_t)0x0030)
-#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
-#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2))
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2) || \
- ((MODE) == TIM_ForcedAction_Active) || \
- ((MODE) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode
- * @{
- */
-
-#define TIM_OPMode_Single ((uint16_t)0x0008)
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
- ((MODE) == TIM_OPMode_Repetitive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel
- * @{
- */
-
-#define TIM_Channel_1 ((uint16_t)0x0000)
-#define TIM_Channel_2 ((uint16_t)0x0004)
-#define TIM_Channel_3 ((uint16_t)0x0008)
-#define TIM_Channel_4 ((uint16_t)0x000C)
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3) || \
- ((CHANNEL) == TIM_Channel_4))
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2))
-#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Division_CKD
- * @{
- */
-
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
- ((DIV) == TIM_CKD_DIV2) || \
- ((DIV) == TIM_CKD_DIV4))
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode
- * @{
- */
-
-#define TIM_CounterMode_Up ((uint16_t)0x0000)
-#define TIM_CounterMode_Down ((uint16_t)0x0010)
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
- ((MODE) == TIM_CounterMode_Down) || \
- ((MODE) == TIM_CounterMode_CenterAligned1) || \
- ((MODE) == TIM_CounterMode_CenterAligned2) || \
- ((MODE) == TIM_CounterMode_CenterAligned3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity
- * @{
- */
-
-#define TIM_OCPolarity_High ((uint16_t)0x0000)
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
- ((POLARITY) == TIM_OCPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity
- * @{
- */
-
-#define TIM_OCNPolarity_High ((uint16_t)0x0000)
-#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
- ((POLARITY) == TIM_OCNPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_state
- * @{
- */
-
-#define TIM_OutputState_Disable ((uint16_t)0x0000)
-#define TIM_OutputState_Enable ((uint16_t)0x0001)
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
- ((STATE) == TIM_OutputState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_state
- * @{
- */
-
-#define TIM_OutputNState_Disable ((uint16_t)0x0000)
-#define TIM_OutputNState_Enable ((uint16_t)0x0004)
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
- ((STATE) == TIM_OutputNState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_state
- * @{
- */
-
-#define TIM_CCx_Enable ((uint16_t)0x0001)
-#define TIM_CCx_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
- ((CCX) == TIM_CCx_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_N_state
- * @{
- */
-
-#define TIM_CCxN_Enable ((uint16_t)0x0004)
-#define TIM_CCxN_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
- ((CCXN) == TIM_CCxN_Disable))
-/**
- * @}
- */
-
-/** @defgroup Break_Input_enable_disable
- * @{
- */
-
-#define TIM_Break_Enable ((uint16_t)0x1000)
-#define TIM_Break_Disable ((uint16_t)0x0000)
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
- ((STATE) == TIM_Break_Disable))
-/**
- * @}
- */
-
-/** @defgroup Break_Polarity
- * @{
- */
-
-#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
-#define TIM_BreakPolarity_High ((uint16_t)0x2000)
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
- ((POLARITY) == TIM_BreakPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset
- * @{
- */
-
-#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
-#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
- ((STATE) == TIM_AutomaticOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup Lock_level
- * @{
- */
-
-#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
-#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
-#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
-#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
- ((LEVEL) == TIM_LOCKLevel_1) || \
- ((LEVEL) == TIM_LOCKLevel_2) || \
- ((LEVEL) == TIM_LOCKLevel_3))
-/**
- * @}
- */
-
-/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state
- * @{
- */
-
-#define TIM_OSSIState_Enable ((uint16_t)0x0400)
-#define TIM_OSSIState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
- ((STATE) == TIM_OSSIState_Disable))
-/**
- * @}
- */
-
-/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state
- * @{
- */
-
-#define TIM_OSSRState_Enable ((uint16_t)0x0800)
-#define TIM_OSSRState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
- ((STATE) == TIM_OSSRState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State
- * @{
- */
-
-#define TIM_OCIdleState_Set ((uint16_t)0x0100)
-#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
- ((STATE) == TIM_OCIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State
- * @{
- */
-
-#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
-#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
- ((STATE) == TIM_OCNIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity
- * @{
- */
-
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
-#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
- ((POLARITY) == TIM_ICPolarity_Falling))
-#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
- ((POLARITY) == TIM_ICPolarity_Falling)|| \
- ((POLARITY) == TIM_ICPolarity_BothEdge))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection
- * @{
- */
-
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively. */
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
- ((SELECTION) == TIM_ICSelection_IndirectTI) || \
- ((SELECTION) == TIM_ICSelection_TRC))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler
- * @{
- */
-
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_interrupt_sources
- * @{
- */
-
-#define TIM_IT_Update ((uint16_t)0x0001)
-#define TIM_IT_CC1 ((uint16_t)0x0002)
-#define TIM_IT_CC2 ((uint16_t)0x0004)
-#define TIM_IT_CC3 ((uint16_t)0x0008)
-#define TIM_IT_CC4 ((uint16_t)0x0010)
-#define TIM_IT_COM ((uint16_t)0x0020)
-#define TIM_IT_Trigger ((uint16_t)0x0040)
-#define TIM_IT_Break ((uint16_t)0x0080)
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
- ((IT) == TIM_IT_CC1) || \
- ((IT) == TIM_IT_CC2) || \
- ((IT) == TIM_IT_CC3) || \
- ((IT) == TIM_IT_CC4) || \
- ((IT) == TIM_IT_COM) || \
- ((IT) == TIM_IT_Trigger) || \
- ((IT) == TIM_IT_Break))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address
- * @{
- */
-
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)
-#define TIM_DMABase_DIER ((uint16_t)0x0003)
-#define TIM_DMABase_SR ((uint16_t)0x0004)
-#define TIM_DMABase_EGR ((uint16_t)0x0005)
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
-#define TIM_DMABase_CCER ((uint16_t)0x0008)
-#define TIM_DMABase_CNT ((uint16_t)0x0009)
-#define TIM_DMABase_PSC ((uint16_t)0x000A)
-#define TIM_DMABase_ARR ((uint16_t)0x000B)
-#define TIM_DMABase_RCR ((uint16_t)0x000C)
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
-#define TIM_DMABase_BDTR ((uint16_t)0x0011)
-#define TIM_DMABase_DCR ((uint16_t)0x0012)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- ((BASE) == TIM_DMABase_CR2) || \
- ((BASE) == TIM_DMABase_SMCR) || \
- ((BASE) == TIM_DMABase_DIER) || \
- ((BASE) == TIM_DMABase_SR) || \
- ((BASE) == TIM_DMABase_EGR) || \
- ((BASE) == TIM_DMABase_CCMR1) || \
- ((BASE) == TIM_DMABase_CCMR2) || \
- ((BASE) == TIM_DMABase_CCER) || \
- ((BASE) == TIM_DMABase_CNT) || \
- ((BASE) == TIM_DMABase_PSC) || \
- ((BASE) == TIM_DMABase_ARR) || \
- ((BASE) == TIM_DMABase_RCR) || \
- ((BASE) == TIM_DMABase_CCR1) || \
- ((BASE) == TIM_DMABase_CCR2) || \
- ((BASE) == TIM_DMABase_CCR3) || \
- ((BASE) == TIM_DMABase_CCR4) || \
- ((BASE) == TIM_DMABase_BDTR) || \
- ((BASE) == TIM_DMABase_DCR))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length
- * @{
- */
-
-#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
- ((LENGTH) == TIM_DMABurstLength_2Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_3Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_4Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_5Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_6Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_7Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_8Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_9Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_10Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_11Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_12Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_13Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_14Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_15Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_16Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_17Bytes) || \
- ((LENGTH) == TIM_DMABurstLength_18Bytes))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources
- * @{
- */
-
-#define TIM_DMA_Update ((uint16_t)0x0100)
-#define TIM_DMA_CC1 ((uint16_t)0x0200)
-#define TIM_DMA_CC2 ((uint16_t)0x0400)
-#define TIM_DMA_CC3 ((uint16_t)0x0800)
-#define TIM_DMA_CC4 ((uint16_t)0x1000)
-#define TIM_DMA_COM ((uint16_t)0x2000)
-#define TIM_DMA_Trigger ((uint16_t)0x4000)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Prescaler
- * @{
- */
-
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_Internal_Trigger_Selection
- * @{
- */
-
-#define TIM_TS_ITR0 ((uint16_t)0x0000)
-#define TIM_TS_ITR1 ((uint16_t)0x0010)
-#define TIM_TS_ITR2 ((uint16_t)0x0020)
-#define TIM_TS_ITR3 ((uint16_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
-#define TIM_TS_ETRF ((uint16_t)0x0070)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-/**
- * @}
- */
-
-/** @defgroup TIM_TIx_External_Clock_Source
- * @{
- */
-
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
-#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
- ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
- ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Polarity
- * @{
- */
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
- ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
-/**
- * @}
- */
-
-/** @defgroup TIM_Prescaler_Reload_Mode
- * @{
- */
-
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
- ((RELOAD) == TIM_PSCReloadMode_Immediate))
-/**
- * @}
- */
-
-/** @defgroup TIM_Forced_Action
- * @{
- */
-
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
- ((ACTION) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode
- * @{
- */
-
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
- ((MODE) == TIM_EncoderMode_TI2) || \
- ((MODE) == TIM_EncoderMode_TI12))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Event_Source
- * @{
- */
-
-#define TIM_EventSource_Update ((uint16_t)0x0001)
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)
-#define TIM_EventSource_COM ((uint16_t)0x0020)
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)
-#define TIM_EventSource_Break ((uint16_t)0x0080)
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Update_Source
- * @{
- */
-
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
- or the setting of UG bit, or an update generation
- through the slave mode controller. */
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
- ((SOURCE) == TIM_UpdateSource_Regular))
-/**
- * @}
- */
-
-/** @defgroup TIM_Ouput_Compare_Preload_State
- * @{
- */
-
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
- ((STATE) == TIM_OCPreload_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Ouput_Compare_Fast_State
- * @{
- */
-
-#define TIM_OCFast_Enable ((uint16_t)0x0004)
-#define TIM_OCFast_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
- ((STATE) == TIM_OCFast_Disable))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Ouput_Compare_Clear_State
- * @{
- */
-
-#define TIM_OCClear_Enable ((uint16_t)0x0080)
-#define TIM_OCClear_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
- ((STATE) == TIM_OCClear_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Output_Source
- * @{
- */
-
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
- ((SOURCE) == TIM_TRGOSource_Enable) || \
- ((SOURCE) == TIM_TRGOSource_Update) || \
- ((SOURCE) == TIM_TRGOSource_OC1) || \
- ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC4Ref))
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode
- * @{
- */
-
-#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
-#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
-#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
-#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
- ((MODE) == TIM_SlaveMode_Gated) || \
- ((MODE) == TIM_SlaveMode_Trigger) || \
- ((MODE) == TIM_SlaveMode_External1))
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode
- * @{
- */
-
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
- ((STATE) == TIM_MasterSlaveMode_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Flags
- * @{
- */
-
-#define TIM_FLAG_Update ((uint16_t)0x0001)
-#define TIM_FLAG_CC1 ((uint16_t)0x0002)
-#define TIM_FLAG_CC2 ((uint16_t)0x0004)
-#define TIM_FLAG_CC3 ((uint16_t)0x0008)
-#define TIM_FLAG_CC4 ((uint16_t)0x0010)
-#define TIM_FLAG_COM ((uint16_t)0x0020)
-#define TIM_FLAG_Trigger ((uint16_t)0x0040)
-#define TIM_FLAG_Break ((uint16_t)0x0080)
-#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
-#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
-#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
-#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_COM) || \
- ((FLAG) == TIM_FLAG_Trigger) || \
- ((FLAG) == TIM_FLAG_Break) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
-
-
-#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Filer_Value
- * @{
- */
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Filter
- * @{
- */
-
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions
- * @{
- */
-
-void TIM_DeInit(TIM_TypeDef* TIMx);
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
-uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
-uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
-uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
-uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
-uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_TIM_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
deleted file mode 100644
index 8d3c381..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
+++ /dev/null
@@ -1,411 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_usart.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the USART
- * firmware library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_USART_H
-#define __STM32F10x_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/** @defgroup USART_Exported_Types
- * @{
- */
-
-/**
- * @brief USART Init Structure definition
- */
-
-typedef struct
-{
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
-
- uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_Word_Length */
-
- uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
-
- uint16_t USART_Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref USART_Hardware_Flow_Control */
-} USART_InitTypeDef;
-
-/**
- * @brief USART Clock Init Structure definition
- */
-
-typedef struct
-{
-
- uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
- This parameter can be a value of @ref USART_Clock */
-
- uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
-
- uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
-
- uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Constants
- * @{
- */
-
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3) || \
- ((PERIPH) == UART4) || \
- ((PERIPH) == UART5))
-
-#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3))
-
-#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3) || \
- ((PERIPH) == UART4))
-/** @defgroup USART_Word_Length
- * @{
- */
-
-#define USART_WordLength_8b ((uint16_t)0x0000)
-#define USART_WordLength_9b ((uint16_t)0x1000)
-
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
- ((LENGTH) == USART_WordLength_9b))
-/**
- * @}
- */
-
-/** @defgroup USART_Stop_Bits
- * @{
- */
-
-#define USART_StopBits_1 ((uint16_t)0x0000)
-#define USART_StopBits_0_5 ((uint16_t)0x1000)
-#define USART_StopBits_2 ((uint16_t)0x2000)
-#define USART_StopBits_1_5 ((uint16_t)0x3000)
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
- ((STOPBITS) == USART_StopBits_0_5) || \
- ((STOPBITS) == USART_StopBits_2) || \
- ((STOPBITS) == USART_StopBits_1_5))
-/**
- * @}
- */
-
-/** @defgroup USART_Parity
- * @{
- */
-
-#define USART_Parity_No ((uint16_t)0x0000)
-#define USART_Parity_Even ((uint16_t)0x0400)
-#define USART_Parity_Odd ((uint16_t)0x0600)
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
- ((PARITY) == USART_Parity_Even) || \
- ((PARITY) == USART_Parity_Odd))
-/**
- * @}
- */
-
-/** @defgroup USART_Mode
- * @{
- */
-
-#define USART_Mode_Rx ((uint16_t)0x0004)
-#define USART_Mode_Tx ((uint16_t)0x0008)
-#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup USART_Hardware_Flow_Control
- * @{
- */
-#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
-#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
-#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
-#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == USART_HardwareFlowControl_None) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock
- * @{
- */
-#define USART_Clock_Disable ((uint16_t)0x0000)
-#define USART_Clock_Enable ((uint16_t)0x0800)
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
- ((CLOCK) == USART_Clock_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity
- * @{
- */
-
-#define USART_CPOL_Low ((uint16_t)0x0000)
-#define USART_CPOL_High ((uint16_t)0x0400)
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase
- * @{
- */
-
-#define USART_CPHA_1Edge ((uint16_t)0x0000)
-#define USART_CPHA_2Edge ((uint16_t)0x0200)
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit
- * @{
- */
-
-#define USART_LastBit_Disable ((uint16_t)0x0000)
-#define USART_LastBit_Enable ((uint16_t)0x0100)
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
- ((LASTBIT) == USART_LastBit_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition
- * @{
- */
-
-#define USART_IT_PE ((uint16_t)0x0028)
-#define USART_IT_TXE ((uint16_t)0x0727)
-#define USART_IT_TC ((uint16_t)0x0626)
-#define USART_IT_RXNE ((uint16_t)0x0525)
-#define USART_IT_IDLE ((uint16_t)0x0424)
-#define USART_IT_LBD ((uint16_t)0x0846)
-#define USART_IT_CTS ((uint16_t)0x096A)
-#define USART_IT_ERR ((uint16_t)0x0060)
-#define USART_IT_ORE ((uint16_t)0x0360)
-#define USART_IT_NE ((uint16_t)0x0260)
-#define USART_IT_FE ((uint16_t)0x0160)
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
- ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Requests
- * @{
- */
-
-#define USART_DMAReq_Tx ((uint16_t)0x0080)
-#define USART_DMAReq_Rx ((uint16_t)0x0040)
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup USART_WakeUp_methods
- * @{
- */
-
-#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
-#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
-#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
- ((WAKEUP) == USART_WakeUp_AddressMark))
-/**
- * @}
- */
-
-/** @defgroup USART_LIN_Break_Detection_Length
- * @{
- */
-
-#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
-#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \
- ((LENGTH) == USART_LINBreakDetectLength_11b))
-/**
- * @}
- */
-
-/** @defgroup USART_IrDA_Low_Power
- * @{
- */
-
-#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
-#define USART_IrDAMode_Normal ((uint16_t)0x0000)
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
- ((MODE) == USART_IrDAMode_Normal))
-/**
- * @}
- */
-
-/** @defgroup USART_Flags
- * @{
- */
-
-#define USART_FLAG_CTS ((uint16_t)0x0200)
-#define USART_FLAG_LBD ((uint16_t)0x0100)
-#define USART_FLAG_TXE ((uint16_t)0x0080)
-#define USART_FLAG_TC ((uint16_t)0x0040)
-#define USART_FLAG_RXNE ((uint16_t)0x0020)
-#define USART_FLAG_IDLE ((uint16_t)0x0010)
-#define USART_FLAG_ORE ((uint16_t)0x0008)
-#define USART_FLAG_NE ((uint16_t)0x0004)
-#define USART_FLAG_FE ((uint16_t)0x0002)
-#define USART_FLAG_PE ((uint16_t)0x0001)
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
-
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
-#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
- ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
- || ((USART_FLAG) != USART_FLAG_CTS))
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
-#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Functions
- * @{
- */
-
-void USART_DeInit(USART_TypeDef* USARTx);
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-void USART_SendBreak(USART_TypeDef* USARTx);
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_USART_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h
deleted file mode 100644
index 8595698..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_wwdg.h
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file contains all the functions prototypes for the WWDG firmware
- * library.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_WWDG_H
-#define __STM32F10x_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup WWDG
- * @{
- */
-
-/** @defgroup WWDG_Exported_Types
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup WWDG_Prescaler
- * @{
- */
-
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
- ((PRESCALER) == WWDG_Prescaler_2) || \
- ((PRESCALER) == WWDG_Prescaler_4) || \
- ((PRESCALER) == WWDG_Prescaler_8))
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup WWDG_Exported_Functions
- * @{
- */
-
-void WWDG_DeInit(void);
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
-void WWDG_SetWindowValue(uint8_t WindowValue);
-void WWDG_EnableIT(void);
-void WWDG_SetCounter(uint8_t Counter);
-void WWDG_Enable(uint8_t Counter);
-FlagStatus WWDG_GetFlagStatus(void);
-void WWDG_ClearFlag(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_WWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c
deleted file mode 100644
index 663b9bb..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c
+++ /dev/null
@@ -1,1306 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_adc.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the ADC firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_adc.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup ADC
- * @brief ADC driver modules
- * @{
- */
-
-/** @defgroup ADC_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Private_Defines
- * @{
- */
-
-/* ADC DISCNUM mask */
-#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
-
-/* ADC DISCEN mask */
-#define CR1_DISCEN_Set ((uint32_t)0x00000800)
-#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
-
-/* ADC JAUTO mask */
-#define CR1_JAUTO_Set ((uint32_t)0x00000400)
-#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
-
-/* ADC JDISCEN mask */
-#define CR1_JDISCEN_Set ((uint32_t)0x00001000)
-#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
-
-/* ADC AWDCH mask */
-#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
-
-/* ADC Analog watchdog enable mode mask */
-#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
-
-/* CR1 register Mask */
-#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
-
-/* ADC ADON mask */
-#define CR2_ADON_Set ((uint32_t)0x00000001)
-#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
-
-/* ADC DMA mask */
-#define CR2_DMA_Set ((uint32_t)0x00000100)
-#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
-
-/* ADC RSTCAL mask */
-#define CR2_RSTCAL_Set ((uint32_t)0x00000008)
-
-/* ADC CAL mask */
-#define CR2_CAL_Set ((uint32_t)0x00000004)
-
-/* ADC SWSTART mask */
-#define CR2_SWSTART_Set ((uint32_t)0x00400000)
-
-/* ADC EXTTRIG mask */
-#define CR2_EXTTRIG_Set ((uint32_t)0x00100000)
-#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
-
-/* ADC Software start mask */
-#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
-#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
-
-/* ADC JEXTSEL mask */
-#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
-
-/* ADC JEXTTRIG mask */
-#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)
-#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
-
-/* ADC JSWSTART mask */
-#define CR2_JSWSTART_Set ((uint32_t)0x00200000)
-
-/* ADC injected software start mask */
-#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
-#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
-
-/* ADC TSPD mask */
-#define CR2_TSVREFE_Set ((uint32_t)0x00800000)
-#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
-
-/* CR2 register Mask */
-#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
-
-/* ADC SQx mask */
-#define SQR3_SQ_Set ((uint32_t)0x0000001F)
-#define SQR2_SQ_Set ((uint32_t)0x0000001F)
-#define SQR1_SQ_Set ((uint32_t)0x0000001F)
-
-/* SQR1 register Mask */
-#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
-
-/* ADC JSQx mask */
-#define JSQR_JSQ_Set ((uint32_t)0x0000001F)
-
-/* ADC JL mask */
-#define JSQR_JL_Set ((uint32_t)0x00300000)
-#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
-
-/* ADC SMPx mask */
-#define SMPR1_SMP_Set ((uint32_t)0x00000007)
-#define SMPR2_SMP_Set ((uint32_t)0x00000007)
-
-/* ADC JDRx registers offset */
-#define JDR_Offset ((uint8_t)0x28)
-
-/* ADC1 DR register base address */
-#define DR_ADDRESS ((uint32_t)0x4001244C)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the ADCx peripheral registers to their default reset values.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_DeInit(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- if (ADCx == ADC1)
- {
- /* Enable ADC1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
- /* Release ADC1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
- }
- else if (ADCx == ADC2)
- {
- /* Enable ADC2 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
- /* Release ADC2 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
- }
- else
- {
- if (ADCx == ADC3)
- {
- /* Enable ADC3 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
- /* Release ADC3 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
- * the configuration information for the specified ADC peripheral.
- * @retval None
- */
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
-{
- uint32_t tmpreg1 = 0;
- uint8_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
-
- /*---------------------------- ADCx CR1 Configuration -----------------*/
- /* Get the ADCx CR1 value */
- tmpreg1 = ADCx->CR1;
- /* Clear DUALMOD and SCAN bits */
- tmpreg1 &= CR1_CLEAR_Mask;
- /* Configure ADCx: Dual mode and scan conversion mode */
- /* Set DUALMOD bits according to ADC_Mode value */
- /* Set SCAN bit according to ADC_ScanConvMode value */
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
- /* Write to ADCx CR1 */
- ADCx->CR1 = tmpreg1;
-
- /*---------------------------- ADCx CR2 Configuration -----------------*/
- /* Get the ADCx CR2 value */
- tmpreg1 = ADCx->CR2;
- /* Clear CONT, ALIGN and EXTSEL bits */
- tmpreg1 &= CR2_CLEAR_Mask;
- /* Configure ADCx: external trigger event and continuous conversion mode */
- /* Set ALIGN bit according to ADC_DataAlign value */
- /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
- /* Set CONT bit according to ADC_ContinuousConvMode value */
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
- ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
- /* Write to ADCx CR2 */
- ADCx->CR2 = tmpreg1;
-
- /*---------------------------- ADCx SQR1 Configuration -----------------*/
- /* Get the ADCx SQR1 value */
- tmpreg1 = ADCx->SQR1;
- /* Clear L bits */
- tmpreg1 &= SQR1_CLEAR_Mask;
- /* Configure ADCx: regular channel sequence length */
- /* Set L bits according to ADC_NbrOfChannel value */
- tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
- tmpreg1 |= (uint32_t)tmpreg2 << 20;
- /* Write to ADCx SQR1 */
- ADCx->SQR1 = tmpreg1;
-}
-
-/**
- * @brief Fills each ADC_InitStruct member with its default value.
- * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
-{
- /* Reset ADC init structure parameters values */
- /* Initialize the ADC_Mode member */
- ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
- /* initialize the ADC_ScanConvMode member */
- ADC_InitStruct->ADC_ScanConvMode = DISABLE;
- /* Initialize the ADC_ContinuousConvMode member */
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
- /* Initialize the ADC_ExternalTrigConv member */
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
- /* Initialize the ADC_DataAlign member */
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
- /* Initialize the ADC_NbrOfChannel member */
- ADC_InitStruct->ADC_NbrOfChannel = 1;
-}
-
-/**
- * @brief Enables or disables the specified ADC peripheral.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the ADCx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the ADON bit to wake up the ADC from power down mode */
- ADCx->CR2 |= CR2_ADON_Set;
- }
- else
- {
- /* Disable the selected ADC peripheral */
- ADCx->CR2 &= CR2_ADON_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified ADC DMA request.
- * @param ADCx: where x can be 1 or 3 to select the ADC peripheral.
- * Note: ADC2 hasn't a DMA capability.
- * @param NewState: new state of the selected ADC DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_DMA_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request */
- ADCx->CR2 |= CR2_DMA_Set;
- }
- else
- {
- /* Disable the selected ADC DMA request */
- ADCx->CR2 &= CR2_DMA_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified ADC interrupts.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @param NewState: new state of the specified ADC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
-{
- uint8_t itmask = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_ADC_IT(ADC_IT));
- /* Get the ADC IT index */
- itmask = (uint8_t)ADC_IT;
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC interrupts */
- ADCx->CR1 |= itmask;
- }
- else
- {
- /* Disable the selected ADC interrupts */
- ADCx->CR1 &= (~(uint32_t)itmask);
- }
-}
-
-/**
- * @brief Resets the selected ADC calibration registers.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_ResetCalibration(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Resets the selected ADC calibartion registers */
- ADCx->CR2 |= CR2_RSTCAL_Set;
-}
-
-/**
- * @brief Gets the selected ADC reset calibration registers status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC reset calibration registers (SET or RESET).
- */
-FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Check the status of RSTCAL bit */
- if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
- {
- /* RSTCAL bit is set */
- bitstatus = SET;
- }
- else
- {
- /* RSTCAL bit is reset */
- bitstatus = RESET;
- }
- /* Return the RSTCAL bit status */
- return bitstatus;
-}
-
-/**
- * @brief Starts the selected ADC calibration process.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_StartCalibration(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Enable the selected ADC calibration process */
- ADCx->CR2 |= CR2_CAL_Set;
-}
-
-/**
- * @brief Gets the selected ADC calibration status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC calibration (SET or RESET).
- */
-FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Check the status of CAL bit */
- if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
- {
- /* CAL bit is set: calibration on going */
- bitstatus = SET;
- }
- else
- {
- /* CAL bit is reset: end of calibration */
- bitstatus = RESET;
- }
- /* Return the CAL bit status */
- return bitstatus;
-}
-
-/**
- * @brief Enables or disables the selected ADC software start conversion .
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC software start conversion.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC conversion on external event and start the selected
- ADC conversion */
- ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
- }
- else
- {
- /* Disable the selected ADC conversion on external event and stop the selected
- ADC conversion */
- ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
- }
-}
-
-/**
- * @brief Gets the selected ADC Software start conversion Status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC software start conversion (SET or RESET).
- */
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Check the status of SWSTART bit */
- if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
- {
- /* SWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* SWSTART bit is reset */
- bitstatus = RESET;
- }
- /* Return the SWSTART bit status */
- return bitstatus;
-}
-
-/**
- * @brief Configures the discontinuous mode for the selected ADC regular
- * group channel.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param Number: specifies the discontinuous mode regular channel
- * count value. This number must be between 1 and 8.
- * @retval None
- */
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
- /* Get the old register value */
- tmpreg1 = ADCx->CR1;
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= CR1_DISCNUM_Reset;
- /* Set the discontinuous mode channel count */
- tmpreg2 = Number - 1;
- tmpreg1 |= tmpreg2 << 13;
- /* Store the new register value */
- ADCx->CR1 = tmpreg1;
-}
-
-/**
- * @brief Enables or disables the discontinuous mode on regular group
- * channel for the specified ADC
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode
- * on regular group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC regular discontinuous mode */
- ADCx->CR1 |= CR1_DISCEN_Set;
- }
- else
- {
- /* Disable the selected ADC regular discontinuous mode */
- ADCx->CR1 &= CR1_DISCEN_Reset;
- }
-}
-
-/**
- * @brief Configures for the selected ADC regular channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
- * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
- * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
- * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
- * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
- * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
- * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
- * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
- * @retval None
- */
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_REGULAR_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
- /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
- /* Clear the old channel sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
- /* Set the new channel sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
- /* Clear the old channel sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
- /* Set the new channel sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* For Rank 1 to 6 */
- if (Rank < 7)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR3;
- /* Calculate the mask to clear */
- tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SQR3 = tmpreg1;
- }
- /* For Rank 7 to 12 */
- else if (Rank < 13)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR2;
- /* Calculate the mask to clear */
- tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SQR2 = tmpreg1;
- }
- /* For Rank 13 to 16 */
- else
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR1;
- /* Calculate the mask to clear */
- tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SQR1 = tmpreg1;
- }
-}
-
-/**
- * @brief Enables or disables the ADCx conversion through external trigger.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC external trigger start of conversion.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC conversion on external event */
- ADCx->CR2 |= CR2_EXTTRIG_Set;
- }
- else
- {
- /* Disable the selected ADC conversion on external event */
- ADCx->CR2 &= CR2_EXTTRIG_Reset;
- }
-}
-
-/**
- * @brief Returns the last ADCx conversion result data for regular channel.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Return the selected ADC conversion value */
- return (uint16_t) ADCx->DR;
-}
-
-/**
- * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.
- * @retval The Data conversion value.
- */
-uint32_t ADC_GetDualModeConversionValue(void)
-{
- /* Return the dual mode conversion value */
- return (*(__IO uint32_t *) DR_ADDRESS);
-}
-
-/**
- * @brief Enables or disables the selected ADC automatic injected group
- * conversion after regular one.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC auto injected conversion
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC automatic injected group conversion */
- ADCx->CR1 |= CR1_JAUTO_Set;
- }
- else
- {
- /* Disable the selected ADC automatic injected group conversion */
- ADCx->CR1 &= CR1_JAUTO_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the discontinuous mode for injected group
- * channel for the specified ADC
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode
- * on injected group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC injected discontinuous mode */
- ADCx->CR1 |= CR1_JDISCEN_Set;
- }
- else
- {
- /* Disable the selected ADC injected discontinuous mode */
- ADCx->CR1 &= CR1_JDISCEN_Reset;
- }
-}
-
-/**
- * @brief Configures the ADCx external trigger for injected channels conversion.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
- * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
- * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
- * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
- * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
- * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
- * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
- * capture compare4 event selected (for ADC1 and ADC2)
- * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
- * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)
- * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
- * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)
- * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)
- * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
- * by external trigger (for ADC1, ADC2 and ADC3)
- * @retval None
- */
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
- /* Get the old register value */
- tmpreg = ADCx->CR2;
- /* Clear the old external event selection for injected group */
- tmpreg &= CR2_JEXTSEL_Reset;
- /* Set the external event selection for injected group */
- tmpreg |= ADC_ExternalTrigInjecConv;
- /* Store the new register value */
- ADCx->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the ADCx injected channels conversion through
- * external trigger
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC external trigger start of
- * injected conversion.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC external event selection for injected group */
- ADCx->CR2 |= CR2_JEXTTRIG_Set;
- }
- else
- {
- /* Disable the selected ADC external event selection for injected group */
- ADCx->CR2 &= CR2_JEXTTRIG_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the selected ADC start of the injected
- * channels conversion.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC software start injected conversion.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC conversion for injected group on external event and start the selected
- ADC injected conversion */
- ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
- }
- else
- {
- /* Disable the selected ADC conversion on external event for injected group and stop the selected
- ADC injected conversion */
- ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
- }
-}
-
-/**
- * @brief Gets the selected ADC Software start injected conversion Status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC software start injected conversion (SET or RESET).
- */
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Check the status of JSWSTART bit */
- if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
- {
- /* JSWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* JSWSTART bit is reset */
- bitstatus = RESET;
- }
- /* Return the JSWSTART bit status */
- return bitstatus;
-}
-
-/**
- * @brief Configures for the selected ADC injected channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
- * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
- * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
- * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
- * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
- * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
- * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
- * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
- * @retval None
- */
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_INJECTED_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
- /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
- /* Clear the old channel sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
- /* Set the new channel sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
- /* Clear the old channel sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
- /* Set the new channel sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* Rank configuration */
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
- /* Get JL value: Number = JL+1 */
- tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
- /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
- /* Clear the old JSQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
- /* Set the JSQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Configures the sequencer length for injected channels
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param Length: The sequencer length.
- * This parameter must be a number between 1 to 4.
- * @retval None
- */
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_LENGTH(Length));
-
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
- /* Clear the old injected sequnence lenght JL bits */
- tmpreg1 &= JSQR_JL_Reset;
- /* Set the injected sequnence lenght JL bits */
- tmpreg2 = Length - 1;
- tmpreg1 |= tmpreg2 << 20;
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Set the injected channels conversion value offset
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
- * @param Offset: the offset value for the selected ADC injected channel
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
- assert_param(IS_ADC_OFFSET(Offset));
-
- tmp = (uint32_t)ADCx;
- tmp += ADC_InjectedChannel;
-
- /* Set the selected injected channel data offset */
- *(__IO uint32_t *) tmp = (uint32_t)Offset;
-}
-
-/**
- * @brief Returns the ADC injected channel conversion result
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InjectedChannel: the converted ADC injected channel.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
-
- tmp = (uint32_t)ADCx;
- tmp += ADC_InjectedChannel + JDR_Offset;
-
- /* Returns the selected injected channel conversion data value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-
-/**
- * @brief Enables or disables the analog watchdog on single/all regular
- * or injected channels
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
- * This parameter can be one of the following values:
- * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
- * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
- * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
- * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
- * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
- * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
- * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
- * @retval None
- */
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
- /* Get the old register value */
- tmpreg = ADCx->CR1;
- /* Clear AWDEN, AWDENJ and AWDSGL bits */
- tmpreg &= CR1_AWDMode_Reset;
- /* Set the analog watchdog enable mode */
- tmpreg |= ADC_AnalogWatchdog;
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-
-/**
- * @brief Configures the high and low thresholds of the analog watchdog.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 12bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
- uint16_t LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_THRESHOLD(HighThreshold));
- assert_param(IS_ADC_THRESHOLD(LowThreshold));
- /* Set the ADCx high threshold */
- ADCx->HTR = HighThreshold;
- /* Set the ADCx low threshold */
- ADCx->LTR = LowThreshold;
-}
-
-/**
- * @brief Configures the analog watchdog guarded single channel
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @retval None
- */
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- /* Get the old register value */
- tmpreg = ADCx->CR1;
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= CR1_AWDCH_Reset;
- /* Set the Analog watchdog channel */
- tmpreg |= ADC_Channel;
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the temperature sensor and Vrefint channel.
- * @param NewState: new state of the temperature sensor.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_TempSensorVrefintCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the temperature sensor and Vrefint channel*/
- ADC1->CR2 |= CR2_TSVREFE_Set;
- }
- else
- {
- /* Disable the temperature sensor and Vrefint channel*/
- ADC1->CR2 &= CR2_TSVREFE_Reset;
- }
-}
-
-/**
- * @brief Checks whether the specified ADC flag is set or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag
- * @retval The new state of ADC_FLAG (SET or RESET).
- */
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
- /* Check the status of the specified ADC flag */
- if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
- {
- /* ADC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's pending flags.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag
- * @retval None
- */
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
- /* Clear the selected ADC flags */
- ADCx->SR = ~(uint32_t)ADC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified ADC interrupt has occurred or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @retval The new state of ADC_IT (SET or RESET).
- */
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itmask = 0, enablestatus = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_IT(ADC_IT));
- /* Get the ADC IT index */
- itmask = ADC_IT >> 8;
- /* Get the ADC_IT enable bit status */
- enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
- /* Check the status of the specified ADC interrupt */
- if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
- {
- /* ADC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCxs interrupt pending bits.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @retval None
- */
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
-{
- uint8_t itmask = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
- /* Get the ADC IT index */
- itmask = (uint8_t)(ADC_IT >> 8);
- /* Clear the selected ADC interrupt pending bits */
- ADCx->SR = ~(uint32_t)itmask;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
deleted file mode 100644
index 3ad63af..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_bkp.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the BKP firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup BKP
- * @brief BKP driver modules
- * @{
- */
-
-/** @defgroup BKP_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup BKP_Private_Defines
- * @{
- */
-
-/* ------------ BKP registers bit address in the alias region --------------- */
-#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
-
-/* --- CR Register ----*/
-
-/* Alias word address of TPAL bit */
-#define CR_OFFSET (BKP_OFFSET + 0x30)
-#define TPAL_BitNumber 0x01
-#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
-
-/* Alias word address of TPE bit */
-#define TPE_BitNumber 0x00
-#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of TPIE bit */
-#define CSR_OFFSET (BKP_OFFSET + 0x34)
-#define TPIE_BitNumber 0x02
-#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
-
-/* Alias word address of TIF bit */
-#define TIF_BitNumber 0x09
-#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
-
-/* Alias word address of TEF bit */
-#define TEF_BitNumber 0x08
-#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
-
-/* ---------------------- BKP registers bit mask ------------------------ */
-
-/* RTCCR register bit mask */
-#define RTCCR_CAL_MASK ((uint16_t)0xFF80)
-#define RTCCR_MASK ((uint16_t)0xFC7F)
-
-/**
- * @}
- */
-
-
-/** @defgroup BKP_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup BKP_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup BKP_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup BKP_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the BKP peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void BKP_DeInit(void)
-{
- RCC_BackupResetCmd(ENABLE);
- RCC_BackupResetCmd(DISABLE);
-}
-
-/**
- * @brief Configures the Tamper Pin active level.
- * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
- * This parameter can be one of the following values:
- * @arg BKP_TamperPinLevel_High: Tamper pin active on high level
- * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
- * @retval None
- */
-void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
-{
- /* Check the parameters */
- assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
- *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
-}
-
-/**
- * @brief Enables or disables the Tamper Pin activation.
- * @param NewState: new state of the Tamper Pin activation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void BKP_TamperPinCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Tamper Pin Interrupt.
- * @param NewState: new state of the Tamper Pin Interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void BKP_ITConfig(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Select the RTC output source to output on the Tamper pin.
- * @param BKP_RTCOutputSource: specifies the RTC output source.
- * This parameter can be one of the following values:
- * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
- * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
- * divided by 64 on the Tamper pin.
- * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
- * the Tamper pin.
- * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
- * the Tamper pin.
- * @retval None
- */
-void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
-{
- uint16_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
- tmpreg = BKP->RTCCR;
- /* Clear CCO, ASOE and ASOS bits */
- tmpreg &= RTCCR_MASK;
-
- /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
- tmpreg |= BKP_RTCOutputSource;
- /* Store the new value */
- BKP->RTCCR = tmpreg;
-}
-
-/**
- * @brief Sets RTC Clock Calibration value.
- * @param CalibrationValue: specifies the RTC Clock Calibration value.
- * This parameter must be a number between 0 and 0x7F.
- * @retval None
- */
-void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
-{
- uint16_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
- tmpreg = BKP->RTCCR;
- /* Clear CAL[6:0] bits */
- tmpreg &= RTCCR_CAL_MASK;
- /* Set CAL[6:0] bits according to CalibrationValue value */
- tmpreg |= CalibrationValue;
- /* Store the new value */
- BKP->RTCCR = tmpreg;
-}
-
-/**
- * @brief Writes user data to the specified Data Backup Register.
- * @param BKP_DR: specifies the Data Backup Register.
- * This parameter can be BKP_DRx where x:[1, 42]
- * @param Data: data to write
- * @retval None
- */
-void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_BKP_DR(BKP_DR));
-
- tmp = (uint32_t)BKP_BASE;
- tmp += BKP_DR;
-
- *(__IO uint32_t *) tmp = Data;
-}
-
-/**
- * @brief Reads data from the specified Data Backup Register.
- * @param BKP_DR: specifies the Data Backup Register.
- * This parameter can be BKP_DRx where x:[1, 42]
- * @retval The content of the specified Data Backup Register
- */
-uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_BKP_DR(BKP_DR));
-
- tmp = (uint32_t)BKP_BASE;
- tmp += BKP_DR;
-
- return (*(__IO uint16_t *) tmp);
-}
-
-/**
- * @brief Checks whether the Tamper Pin Event flag is set or not.
- * @param None
- * @retval The new state of the Tamper Pin Event flag (SET or RESET).
- */
-FlagStatus BKP_GetFlagStatus(void)
-{
- return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
-}
-
-/**
- * @brief Clears Tamper Pin Event pending flag.
- * @param None
- * @retval None
- */
-void BKP_ClearFlag(void)
-{
- /* Set CTE bit to clear Tamper Pin Event flag */
- BKP->CSR |= BKP_CSR_CTE;
-}
-
-/**
- * @brief Checks whether the Tamper Pin Interrupt has occurred or not.
- * @param None
- * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
- */
-ITStatus BKP_GetITStatus(void)
-{
- return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
-}
-
-/**
- * @brief Clears Tamper Pin Interrupt pending bit.
- * @param None
- * @retval None
- */
-void BKP_ClearITPendingBit(void)
-{
- /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
- BKP->CSR |= BKP_CSR_CTI;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
deleted file mode 100644
index 043819a..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
+++ /dev/null
@@ -1,1166 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_can.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the CAN firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_can.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CAN
- * @brief CAN driver modules
- * @{
- */
-
-/** @defgroup CAN_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Private_Defines
- * @{
- */
-
-/* CAN Master Control Register bits */
-
-#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
-
-/* CAN Mailbox Transmit Request */
-#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
-
-/* CAN Filter Master Register bits */
-#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
-
-/* Time out for INAK bit */
-#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
-
-
-
-/* Flags in TSR register */
-#define CAN_FLAGS_TSR ((uint32_t)0x08000000)
-/* Flags in RF1R register */
-#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
-/* Flags in RF0R register */
-#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
-/* Flags in MSR register */
-#define CAN_FLAGS_MSR ((uint32_t)0x01000000)
-/* Flags in ESR register */
-#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
-
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Private_FunctionPrototypes
- * @{
- */
-
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the CAN peripheral registers to their default reset values.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
- * @retval None.
- */
-void CAN_DeInit(CAN_TypeDef* CANx)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- if (CANx == CAN1)
- {
- /* Enable CAN1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
- /* Release CAN1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
- }
- else
- {
- /* Enable CAN2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
- /* Release CAN2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
- }
-}
-
-/**
- * @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_InitStruct.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
- * contains the configuration information for the CAN peripheral.
- * @retval Constant indicates initialization succeed which will be
- * CANINITFAILED or CANINITOK.
- */
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
-{
- uint8_t InitStatus = CANINITFAILED;
- uint32_t wait_ack = 0x00000000;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
- assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
- assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
- assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
- assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
- assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
-
- /* exit from sleep mode */
- CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
- /* Request initialisation */
- CANx->MCR |= CAN_MCR_INRQ ;
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* ...and check acknowledged */
- if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
- {
- InitStatus = CANINITFAILED;
- }
- else
- {
- /* Set the time triggered communication mode */
- if (CAN_InitStruct->CAN_TTCM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TTCM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
- }
-
- /* Set the automatic bus-off management */
- if (CAN_InitStruct->CAN_ABOM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_ABOM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
- }
-
- /* Set the automatic wake-up mode */
- if (CAN_InitStruct->CAN_AWUM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_AWUM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
- }
-
- /* Set the no automatic retransmission */
- if (CAN_InitStruct->CAN_NART == ENABLE)
- {
- CANx->MCR |= CAN_MCR_NART;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
- }
-
- /* Set the receive FIFO locked mode */
- if (CAN_InitStruct->CAN_RFLM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_RFLM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
- }
-
- /* Set the transmit FIFO priority */
- if (CAN_InitStruct->CAN_TXFP == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TXFP;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
- }
-
- /* Set the bit timing register */
- CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |
- ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |
- ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
-
- /* Request leave initialisation */
- CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
- /* Wait the acknowledge */
- wait_ack = 0x00;
-
- while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* ...and check acknowledged */
- if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- InitStatus = CANINITFAILED;
- }
- else
- {
- InitStatus = CANINITOK ;
- }
- }
-
- /* At this step, return the status of initialization */
- return InitStatus;
-}
-
-/**
- * @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
- * structure that contains the configuration information.
- * @retval None.
- */
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
-{
- uint32_t filter_number_bit_pos = 0;
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
-
- filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber;
-
- /* Initialisation mode for the filter */
- CAN1->FMR |= FMR_FINIT;
-
- /* Filter Deactivation */
- CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* Filter Scale */
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
- {
- /* 16-bit scale for the filter */
- CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
- }
-
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
- {
- /* 32-bit scale for the filter */
- CAN1->FS1R |= filter_number_bit_pos;
- /* 32-bit identifier or First 32-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
- /* 32-bit mask or Second 32-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
- }
-
- /* Filter Mode */
- if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
- {
- /*Id/Mask mode for the filter*/
- CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter FIFO assignment */
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)
- {
- /* FIFO 0 assignation for the filter */
- CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
- }
-
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)
- {
- /* FIFO 1 assignation for the filter */
- CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter activation */
- if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
- {
- CAN1->FA1R |= filter_number_bit_pos;
- }
-
- /* Leave the initialisation mode for the filter */
- CAN1->FMR &= ~FMR_FINIT;
-}
-
-/**
- * @brief Fills each CAN_InitStruct member with its default value.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
- * will be initialized.
- * @retval None.
- */
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
-{
- /* Reset CAN init structure parameters values */
- /* Initialize the time triggered communication mode */
- CAN_InitStruct->CAN_TTCM = DISABLE;
- /* Initialize the automatic bus-off management */
- CAN_InitStruct->CAN_ABOM = DISABLE;
- /* Initialize the automatic wake-up mode */
- CAN_InitStruct->CAN_AWUM = DISABLE;
- /* Initialize the no automatic retransmission */
- CAN_InitStruct->CAN_NART = DISABLE;
- /* Initialize the receive FIFO locked mode */
- CAN_InitStruct->CAN_RFLM = DISABLE;
- /* Initialize the transmit FIFO priority */
- CAN_InitStruct->CAN_TXFP = DISABLE;
- /* Initialize the CAN_Mode member */
- CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
- /* Initialize the CAN_SJW member */
- CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
- /* Initialize the CAN_BS1 member */
- CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
- /* Initialize the CAN_BS2 member */
- CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
- /* Initialize the CAN_Prescaler member */
- CAN_InitStruct->CAN_Prescaler = 1;
-}
-
-/**
- * @brief Select the start bank filter for slave CAN.
- * @note This function applies only to STM32 Connectivity line devices.
- * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
- * @retval None.
- */
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
- /* enter Initialisation mode for the filter */
- CAN1->FMR |= FMR_FINIT;
- /* Select the start slave bank */
- CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
- CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
- /* Leave Initialisation mode for the filter */
- CAN1->FMR &= ~FMR_FINIT;
-}
-
-/**
- * @brief Enables or disables the specified CANx interrupts.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
- * This parameter can be:
- * -CAN_IT_TME,
- * -CAN_IT_FMP0,
- * -CAN_IT_FF0,
- * -CAN_IT_FOV0,
- * -CAN_IT_FMP1,
- * -CAN_IT_FF1,
- * -CAN_IT_FOV1,
- * -CAN_IT_EWG,
- * -CAN_IT_EPV,
- * -CAN_IT_LEC,
- * -CAN_IT_ERR,
- * -CAN_IT_WKU or
- * -CAN_IT_SLK.
- * @param NewState: new state of the CAN interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CANx interrupt */
- CANx->IER |= CAN_IT;
- }
- else
- {
- /* Disable the selected CANx interrupt */
- CANx->IER &= ~CAN_IT;
- }
-}
-
-/**
- * @brief Initiates the transmission of a message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param TxMessage: pointer to a structure which contains CAN Id, CAN
- * DLC and CAN datas.
- * @retval The number of the mailbox that is used for transmission
- * or CAN_NO_MB if there is no empty mailbox.
- */
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
-{
- uint8_t transmit_mailbox = 0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
- assert_param(IS_CAN_RTR(TxMessage->RTR));
- assert_param(IS_CAN_DLC(TxMessage->DLC));
-
- /* Select one empty transmit mailbox */
- if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
- {
- transmit_mailbox = 0;
- }
- else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmit_mailbox = 1;
- }
- else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
- {
- transmit_mailbox = 2;
- }
- else
- {
- transmit_mailbox = CAN_NO_MB;
- }
-
- if (transmit_mailbox != CAN_NO_MB)
- {
- /* Set up the Id */
- CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
- if (TxMessage->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(TxMessage->StdId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(TxMessage->ExtId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE |
- TxMessage->RTR);
- }
-
-
- /* Set up the DLC */
- TxMessage->DLC &= (uint8_t)0x0000000F;
- CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
- CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
-
- /* Set up the data field */
- CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
- ((uint32_t)TxMessage->Data[2] << 16) |
- ((uint32_t)TxMessage->Data[1] << 8) |
- ((uint32_t)TxMessage->Data[0]));
- CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
- ((uint32_t)TxMessage->Data[6] << 16) |
- ((uint32_t)TxMessage->Data[5] << 8) |
- ((uint32_t)TxMessage->Data[4]));
- /* Request transmission */
- CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
- }
- return transmit_mailbox;
-}
-
-/**
- * @brief Checks the transmission of a message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param TransmitMailbox: the number of the mailbox that is used for transmission.
- * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case.
- */
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
-{
- /* RQCP, TXOK and TME bits */
- uint8_t state = 0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
- switch (TransmitMailbox)
- {
- case (0): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP0) << 2);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK0) >> 0);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TME0) >> 26);
- break;
- case (1): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP1) >> 6);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK1) >> 8);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TME1) >> 27);
- break;
- case (2): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP2) >> 14);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK2) >> 16);
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TME2) >> 28);
- break;
- default:
- state = CANTXFAILED;
- break;
- }
- switch (state)
- {
- /* transmit pending */
- case (0x0): state = CANTXPENDING;
- break;
- /* transmit failed */
- case (0x5): state = CANTXFAILED;
- break;
- /* transmit succedeed */
- case (0x7): state = CANTXOK;
- break;
- default:
- state = CANTXFAILED;
- break;
- }
- return state;
-}
-
-/**
- * @brief Cancels a transmit request.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param Mailbox: Mailbox number.
- * @retval None.
- */
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
- /* abort transmission */
- switch (Mailbox)
- {
- case (0): CANx->TSR |= CAN_TSR_ABRQ0;
- break;
- case (1): CANx->TSR |= CAN_TSR_ABRQ1;
- break;
- case (2): CANx->TSR |= CAN_TSR_ABRQ2;
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Releases a FIFO.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
- * @retval None.
- */
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R |= CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R |= CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Returns the number of pending messages.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval NbMessage which is the number of pending message.
- */
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- uint8_t message_pending=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- if (FIFONumber == CAN_FIFO0)
- {
- message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
- }
- else if (FIFONumber == CAN_FIFO1)
- {
- message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
- }
- else
- {
- message_pending = 0;
- }
- return message_pending;
-}
-
-/**
- * @brief Receives a message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @param RxMessage: pointer to a structure receive message which
- * contains CAN Id, CAN DLC, CAN datas and FMI number.
- * @retval None.
- */
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Get the Id */
- RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
- if (RxMessage->IDE == CAN_ID_STD)
- {
- RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
- }
- else
- {
- RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
- }
-
- RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
- /* Get the data field */
- RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
- RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
- RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
- RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
- RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
- RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
- RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
- RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
- /* Release the FIFO */
- CAN_FIFORelease(CANx, FIFONumber);
-}
-
-/**
- * @brief Enables or disables the DBG Freeze for CAN.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param NewState: new state of the CAN peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Debug Freeze */
- CANx->MCR |= MCR_DBF;
- }
- else
- {
- /* Disable Debug Freeze */
- CANx->MCR &= ~MCR_DBF;
- }
-}
-
-/**
- * @brief Enters the low power mode.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.
- */
-uint8_t CAN_Sleep(CAN_TypeDef* CANx)
-{
- uint8_t sleepstatus = CANSLEEPFAILED;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Request Sleep mode */
- CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Sleep mode status */
- if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
- {
- /* Sleep mode not entered */
- sleepstatus = CANSLEEPOK;
- }
- /* At this step, sleep mode status */
- return (uint8_t)sleepstatus;
-}
-
-/**
- * @brief Wakes the CAN up.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.
- */
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
-{
- uint32_t wait_slak = SLAK_TIMEOUT;
- uint8_t wakeupstatus = CANWAKEUPFAILED;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Wake up request */
- CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
- /* Sleep mode status */
- while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
- {
- wait_slak--;
- }
- if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
- {
- /* Sleep mode exited */
- wakeupstatus = CANWAKEUPOK;
- }
- /* At this step, sleep mode status */
- return (uint8_t)wakeupstatus;
-}
-
-/**
- * @brief Checks whether the specified CAN flag is set or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to check.
- * This parameter can be one of the following flags:
- * - CAN_FLAG_EWG
- * - CAN_FLAG_EPV
- * - CAN_FLAG_BOF
- * - CAN_FLAG_RQCP0
- * - CAN_FLAG_RQCP1
- * - CAN_FLAG_RQCP2
- * - CAN_FLAG_FMP1
- * - CAN_FLAG_FF1
- * - CAN_FLAG_FOV1
- * - CAN_FLAG_FMP0
- * - CAN_FLAG_FF0
- * - CAN_FLAG_FOV0
- * - CAN_FLAG_WKU
- * - CAN_FLAG_SLAK
- * - CAN_FLAG_LEC
- * @retval The new state of CAN_FLAG (SET or RESET).
- */
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
-
-
- if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
- {
- /* Check the status of the specified CAN flag */
- if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- /* Return the CAN_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CAN's pending flags.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to clear.
- * This parameter can be one of the following flags:
- * - CAN_FLAG_RQCP0
- * - CAN_FLAG_RQCP1
- * - CAN_FLAG_RQCP2
- * - CAN_FLAG_FF1
- * - CAN_FLAG_FOV1
- * - CAN_FLAG_FF0
- * - CAN_FLAG_FOV0
- * - CAN_FLAG_WKU
- * - CAN_FLAG_SLAK
- * - CAN_FLAG_LEC
- * @retval None.
- */
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- uint32_t flagtmp=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
-
- if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
- {
- /* Clear the selected CAN flags */
- CANx->ESR = (uint32_t)RESET;
- }
- else /* MSR or TSR or RF0R or RF1R */
- {
- flagtmp = CAN_FLAG & 0x000FFFFF;
-
- if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF0R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF1R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
- {
- /* Transmit Flags */
- CANx->TSR = (uint32_t)(flagtmp);
- }
- else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
- {
- /* Operating mode Flags */
- CANx->MSR = (uint32_t)(flagtmp);
- }
- }
-}
-
-/**
- * @brief Checks whether the specified CANx interrupt has occurred or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt source to check.
- * This parameter can be one of the following flags:
- * - CAN_IT_TME
- * - CAN_IT_FMP0
- * - CAN_IT_FF0
- * - CAN_IT_FOV0
- * - CAN_IT_FMP1
- * - CAN_IT_FF1
- * - CAN_IT_FOV1
- * - CAN_IT_WKU
- * - CAN_IT_SLK
- * - CAN_IT_EWG
- * - CAN_IT_EPV
- * - CAN_IT_BOF
- * - CAN_IT_LEC
- * - CAN_IT_ERR
- * @retval The current state of CAN_IT (SET or RESET).
- */
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- ITStatus itstatus = RESET;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
-
- /* check the enable interrupt bit */
- if((CANx->IER & CAN_IT) != RESET)
- {
- /* in case the Interrupt is enabled, .... */
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Check CAN_TSR_RQCPx bits */
- itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
- break;
- case CAN_IT_FMP0:
- /* Check CAN_RF0R_FMP0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
- break;
- case CAN_IT_FF0:
- /* Check CAN_RF0R_FULL0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
- break;
- case CAN_IT_FOV0:
- /* Check CAN_RF0R_FOVR0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
- break;
- case CAN_IT_FMP1:
- /* Check CAN_RF1R_FMP1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
- break;
- case CAN_IT_FF1:
- /* Check CAN_RF1R_FULL1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
- break;
- case CAN_IT_FOV1:
- /* Check CAN_RF1R_FOVR1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
- break;
- case CAN_IT_WKU:
- /* Check CAN_MSR_WKUI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
- break;
- case CAN_IT_SLK:
- /* Check CAN_MSR_SLAKI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
- break;
- case CAN_IT_EWG:
- /* Check CAN_ESR_EWGF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
- break;
- case CAN_IT_EPV:
- /* Check CAN_ESR_EPVF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
- break;
- case CAN_IT_BOF:
- /* Check CAN_ESR_BOFF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
- break;
- case CAN_IT_LEC:
- /* Check CAN_ESR_LEC bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
- break;
- case CAN_IT_ERR:
- /* Check CAN_MSR_ERRI, CAN_ESR_EWGF, CAN_ESR_EPVF, CAN_ESR_BOFF and CAN_ESR_LEC bits */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC);
- itstatus |= CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
- break;
- default :
- /* in case of error, return RESET */
- itstatus = RESET;
- break;
- }
- }
- else
- {
- /* in case the Interrupt is not enabled, return RESET */
- itstatus = RESET;
- }
-
- /* Return the CAN_IT status */
- return itstatus;
-}
-
-/**
- * @brief Clears the CANxs interrupt pending bits.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the interrupt pending bit to clear.
- * - CAN_IT_TME
- * - CAN_IT_FF0
- * - CAN_IT_FOV0
- * - CAN_IT_FF1
- * - CAN_IT_FOV1
- * - CAN_IT_WKU
- * - CAN_IT_SLK
- * - CAN_IT_EWG
- * - CAN_IT_EPV
- * - CAN_IT_BOF
- * - CAN_IT_LEC
- * - CAN_IT_ERR
- * @retval None.
- */
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_IT(CAN_IT));
-
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Clear CAN_TSR_RQCPx (rc_w1)*/
- CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
- break;
- case CAN_IT_FF0:
- /* Clear CAN_RF0R_FULL0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FULL0;
- break;
- case CAN_IT_FOV0:
- /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FOVR0;
- break;
- case CAN_IT_FF1:
- /* Clear CAN_RF1R_FULL1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FULL1;
- break;
- case CAN_IT_FOV1:
- /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FOVR1;
- break;
- case CAN_IT_WKU:
- /* Clear CAN_MSR_WKUI (rc_w1)*/
- CANx->MSR = CAN_MSR_WKUI;
- break;
- case CAN_IT_SLK:
- /* Clear CAN_MSR_SLAKI (rc_w1)*/
- CANx->MSR = CAN_MSR_SLAKI;
- break;
- case CAN_IT_EWG:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/
- break;
- case CAN_IT_EPV:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/
- break;
- case CAN_IT_BOF:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/
- break;
- case CAN_IT_LEC:
- /* Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- break;
- case CAN_IT_ERR:
- /*Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending of the CAN Bus status*/
- break;
- default :
- break;
- }
-}
-
-/**
- * @brief Checks whether the CAN interrupt has occurred or not.
- * @param CAN_Reg: specifies the CAN interrupt register to check.
- * @param It_Bit: specifies the interrupt source bit to check.
- * @retval The new state of the CAN Interrupt (SET or RESET).
- */
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
-{
- ITStatus pendingbitstatus = RESET;
-
- if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
- {
- /* CAN_IT is set */
- pendingbitstatus = SET;
- }
- else
- {
- /* CAN_IT is reset */
- pendingbitstatus = RESET;
- }
- return pendingbitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
deleted file mode 100644
index 5b3f9b5..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_cec.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the CEC firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_cec.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CEC
- * @brief CEC driver modules
- * @{
- */
-
-/** @defgroup CEC_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup CEC_Private_Defines
- * @{
- */
-
-/* ------------ CEC registers bit address in the alias region ----------- */
-#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
-
-/* --- CFGR Register ---*/
-
-/* Alias word address of PE bit */
-#define CFGR_OFFSET (CEC_OFFSET + 0x00)
-#define PE_BitNumber 0x00
-#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
-
-/* Alias word address of IE bit */
-#define IE_BitNumber 0x01
-#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of TSOM bit */
-#define CSR_OFFSET (CEC_OFFSET + 0x10)
-#define TSOM_BitNumber 0x00
-#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
-
-/* Alias word address of TEOM bit */
-#define TEOM_BitNumber 0x01
-#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
-
-#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
-#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
-
-/**
- * @}
- */
-
-
-/** @defgroup CEC_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup CEC_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup CEC_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup CEC_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the CEC peripheral registers to their default reset
- * values.
- * @param None
- * @retval None
- */
-void CEC_DeInit(void)
-{
- /* Enable CEC reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
- /* Release CEC from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
-}
-
-
-/**
- * @brief Initializes the CEC peripheral according to the specified
- * parameters in the CEC_InitStruct.
- * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
- * contains the configuration information for the specified
- * CEC peripheral.
- * @retval None
- */
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
- assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
-
- /*---------------------------- CEC CFGR Configuration -----------------*/
- /* Get the CEC CFGR value */
- tmpreg = CEC->CFGR;
-
- /* Clear BTEM and BPEM bits */
- tmpreg &= CFGR_CLEAR_Mask;
-
- /* Configure CEC: Bit Timing Error and Bit Period Error */
- tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
-
- /* Write to CEC CFGR register*/
- CEC->CFGR = tmpreg;
-
-}
-
-/**
- * @brief Enables or disables the specified CEC peripheral.
- * @param NewState: new state of the CEC peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
-
- if(NewState == DISABLE)
- {
- /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
- while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
- {
- }
- }
-}
-
-/**
- * @brief Enables or disables the CEC interrupt.
- * @param NewState: new state of the CEC interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_ITConfig(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Defines the Own Address of the CEC device.
- * @param CEC_OwnAddress: The CEC own address
- * @retval None
- */
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
-{
- /* Check the parameters */
- assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
-
- /* Set the CEC own address */
- CEC->OAR = CEC_OwnAddress;
-}
-
-/**
- * @brief Sets the CEC prescaler value.
- * @param CEC_Prescaler: CEC prescaler new value
- * @retval None
- */
-void CEC_SetPrescaler(uint16_t CEC_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
-
- /* Set the Prescaler value*/
- CEC->PRES = CEC_Prescaler;
-}
-
-/**
- * @brief Transmits single data through the CEC peripheral.
- * @param Data: the data to transmit.
- * @retval None
- */
-void CEC_SendDataByte(uint8_t Data)
-{
- /* Transmit Data */
- CEC->TXD = Data ;
-}
-
-
-/**
- * @brief Returns the most recent received data by the CEC peripheral.
- * @param None
- * @retval The received data.
- */
-uint8_t CEC_ReceiveDataByte(void)
-{
- /* Receive Data */
- return (uint8_t)(CEC->RXD);
-}
-
-/**
- * @brief Starts a new message.
- * @param None
- * @retval None
- */
-void CEC_StartOfMessage(void)
-{
- /* Starts of new message */
- *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
-}
-
-/**
- * @brief Transmits message with or without an EOM bit.
- * @param NewState: new state of the CEC Tx End Of Message.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_EndOfMessageCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* The data byte will be transmitted with or without an EOM bit*/
- *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Gets the CEC flag status
- * @param CEC_FLAG: specifies the CEC flag to check.
- * This parameter can be one of the following values:
- * @arg CEC_FLAG_BTE: Bit Timing Error
- * @arg CEC_FLAG_BPE: Bit Period Error
- * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
- * @arg CEC_FLAG_SBE: Start Bit Error
- * @arg CEC_FLAG_ACKE: Block Acknowledge Error
- * @arg CEC_FLAG_LINE: Line Error
- * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error
- * @arg CEC_FLAG_TEOM: Tx End Of Message
- * @arg CEC_FLAG_TERR: Tx Error
- * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
- * @arg CEC_FLAG_RSOM: Rx Start Of Message
- * @arg CEC_FLAG_REOM: Rx End Of Message
- * @arg CEC_FLAG_RERR: Rx Error
- * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
- * @retval The new state of CEC_FLAG (SET or RESET)
- */
-FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t cecreg = 0, cecbase = 0;
-
- /* Check the parameters */
- assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
-
- /* Get the CEC peripheral base address */
- cecbase = (uint32_t)(CEC_BASE);
-
- /* Read flag register index */
- cecreg = CEC_FLAG >> 28;
-
- /* Get bit[23:0] of the flag */
- CEC_FLAG &= FLAG_Mask;
-
- if(cecreg != 0)
- {
- /* Flag in CEC ESR Register */
- CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
-
- /* Get the CEC ESR register address */
- cecbase += 0xC;
- }
- else
- {
- /* Get the CEC CSR register address */
- cecbase += 0x10;
- }
-
- if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
- {
- /* CEC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CEC_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the CEC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CEC's pending flags.
- * @param CEC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg CEC_FLAG_TERR: Tx Error
- * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
- * @arg CEC_FLAG_RSOM: Rx Start Of Message
- * @arg CEC_FLAG_REOM: Rx End Of Message
- * @arg CEC_FLAG_RERR: Rx Error
- * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
- * @retval None
- */
-void CEC_ClearFlag(uint32_t CEC_FLAG)
-{
- uint32_t tmp = 0x0;
-
- /* Check the parameters */
- assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
-
- tmp = CEC->CSR & 0x2;
-
- /* Clear the selected CEC flags */
- CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
-}
-
-/**
- * @brief Checks whether the specified CEC interrupt has occurred or not.
- * @param CEC_IT: specifies the CEC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CEC_IT_TERR: Tx Error
- * @arg CEC_IT_TBTF: Tx Block Transfer Finished
- * @arg CEC_IT_RERR: Rx Error
- * @arg CEC_IT_RBTF: Rx Block Transfer Finished
- * @retval The new state of CEC_IT (SET or RESET).
- */
-ITStatus CEC_GetITStatus(uint8_t CEC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_CEC_GET_IT(CEC_IT));
-
- /* Get the CEC IT enable bit status */
- enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
-
- /* Check the status of the specified CEC interrupt */
- if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* CEC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* CEC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the CEC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CEC's interrupt pending bits.
- * @param CEC_IT: specifies the CEC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg CEC_IT_TERR: Tx Error
- * @arg CEC_IT_TBTF: Tx Block Transfer Finished
- * @arg CEC_IT_RERR: Rx Error
- * @arg CEC_IT_RBTF: Rx Block Transfer Finished
- * @retval None
- */
-void CEC_ClearITPendingBit(uint16_t CEC_IT)
-{
- uint32_t tmp = 0x0;
-
- /* Check the parameters */
- assert_param(IS_CEC_GET_IT(CEC_IT));
-
- tmp = CEC->CSR & 0x2;
-
- /* Clear the selected CEC interrupt pending bits */
- CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
deleted file mode 100644
index 511a7b9..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_crc.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the CRC firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_crc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRC
- * @brief CRC driver modules
- * @{
- */
-
-/** @defgroup CRC_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Private_Functions
- * @{
- */
-
-/**
- * @brief Resets the CRC Data register (DR).
- * @param None
- * @retval None
- */
-void CRC_ResetDR(void)
-{
- /* Reset CRC generator */
- CRC->CR = CRC_CR_RESET;
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given data word(32-bit).
- * @param Data: data word(32-bit) to compute its CRC
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcCRC(uint32_t Data)
-{
- CRC->DR = Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
- * @param pBuffer: pointer to the buffer containing the data to be computed
- * @param BufferLength: length of the buffer to be computed
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0;
-
- for(index = 0; index < BufferLength; index++)
- {
- CRC->DR = pBuffer[index];
- }
- return (CRC->DR);
-}
-
-/**
- * @brief Returns the current CRC value.
- * @param None
- * @retval 32-bit CRC
- */
-uint32_t CRC_GetCRC(void)
-{
- return (CRC->DR);
-}
-
-/**
- * @brief Stores a 8-bit data in the Independent Data(ID) register.
- * @param IDValue: 8-bit value to be stored in the ID register
- * @retval None
- */
-void CRC_SetIDRegister(uint8_t IDValue)
-{
- CRC->IDR = IDValue;
-}
-
-/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register
- * @param None
- * @retval 8-bit value of the ID register
- */
-uint8_t CRC_GetIDRegister(void)
-{
- return (CRC->IDR);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c
deleted file mode 100644
index 55e91c0..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_dac.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the DAC firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_dac.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DAC
- * @brief DAC driver modules
- * @{
- */
-
-/** @defgroup DAC_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Private_Defines
- * @{
- */
-
-/* CR register Mask */
-#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
-
-/* DAC Dual Channels SWTRIG masks */
-#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
-#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
-
-/* DHR registers offsets */
-#define DHR12R1_OFFSET ((uint32_t)0x00000008)
-#define DHR12R2_OFFSET ((uint32_t)0x00000014)
-#define DHR12RD_OFFSET ((uint32_t)0x00000020)
-
-/* DOR register offset */
-#define DOR_OFFSET ((uint32_t)0x0000002C)
-/**
- * @}
- */
-
-/** @defgroup DAC_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the DAC peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void DAC_DeInit(void)
-{
- /* Enable DAC reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
- /* Release DAC from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
-}
-
-/**
- * @brief Initializes the DAC peripheral according to the specified
- * parameters in the DAC_InitStruct.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
- * contains the configuration information for the specified DAC channel.
- * @retval None
- */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
- /* Check the DAC parameters */
- assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
-/*---------------------------- DAC CR Configuration --------------------------*/
- /* Get the DAC CR value */
- tmpreg1 = DAC->CR;
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
- tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
- /* Configure for the selected DAC channel: buffer output, trigger, wave genration,
- mask/amplitude for wave genration */
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- /* Set WAVEx bits according to DAC_WaveGeneration value */
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
- /* Set BOFFx bit according to DAC_OutputBuffer value */
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
- /* Calculate CR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << DAC_Channel;
- /* Write to DAC CR */
- DAC->CR = tmpreg1;
-}
-
-/**
- * @brief Fills each DAC_InitStruct member with its default value.
- * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
-{
-/*--------------- Reset DAC init structure parameters values -----------------*/
- /* Initialize the DAC_Trigger member */
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
- /* Initialize the DAC_WaveGeneration member */
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
- /* Initialize the DAC_OutputBuffer member */
- DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-}
-
-/**
- * @brief Enables or disables the specified DAC channel.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the DAC channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel */
- DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel */
- DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
- }
-}
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-/**
- * @brief Enables or disables the specified DAC interrupts.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @param NewState: new state of the specified DAC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_DAC_IT(DAC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC interrupts */
- DAC->CR |= (DAC_IT << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC interrupts */
- DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
- }
-}
-#endif
-
-/**
- * @brief Enables or disables the specified DAC channel DMA request.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the selected DAC channel DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel DMA request */
- DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel DMA request */
- DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel software trigger.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the selected DAC channel software trigger.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable software trigger for the selected DAC channel */
- DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
- }
- else
- {
- /* Disable software trigger for the selected DAC channel */
- DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
- }
-}
-
-/**
- * @brief Enables or disables simultaneously the two DAC channels software
- * triggers.
- * @param NewState: new state of the DAC channels software triggers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable software trigger for both DAC channels */
- DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
- }
- else
- {
- /* Disable software trigger for both DAC channels */
- DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel wave generation.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_Wave: Specifies the wave type to enable or disable.
- * This parameter can be one of the following values:
- * @arg DAC_Wave_Noise: noise wave generation
- * @arg DAC_Wave_Triangle: triangle wave generation
- * @param NewState: new state of the selected DAC channel wave generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_WAVE(DAC_Wave));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected wave generation for the selected DAC channel */
- DAC->CR |= DAC_Wave << DAC_Channel;
- }
- else
- {
- /* Disable the selected wave generation for the selected DAC channel */
- DAC->CR &= ~(DAC_Wave << DAC_Channel);
- }
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel1.
- * @param DAC_Align: Specifies the data alignement for DAC channel1.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignement selected
- * @arg DAC_Align_12b_L: 12bit left data alignement selected
- * @arg DAC_Align_12b_R: 12bit right data alignement selected
- * @param Data : Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12R1_OFFSET + DAC_Align;
-
- /* Set the DAC channel1 selected data holding register */
- *(__IO uint32_t *) tmp = Data;
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel2.
- * @param DAC_Align: Specifies the data alignement for DAC channel2.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignement selected
- * @arg DAC_Align_12b_L: 12bit left data alignement selected
- * @arg DAC_Align_12b_R: 12bit right data alignement selected
- * @param Data : Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12R2_OFFSET + DAC_Align;
-
- /* Set the DAC channel2 selected data holding register */
- *(__IO uint32_t *)tmp = Data;
-}
-
-/**
- * @brief Set the specified data holding register value for dual channel
- * DAC.
- * @param DAC_Align: Specifies the data alignement for dual channel DAC.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignement selected
- * @arg DAC_Align_12b_L: 12bit left data alignement selected
- * @arg DAC_Align_12b_R: 12bit right data alignement selected
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data
- * holding register.
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data
- * holding register.
- * @retval None
- */
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
-{
- uint32_t data = 0, tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (DAC_Align == DAC_Align_8b_R)
- {
- data = ((uint32_t)Data2 << 8) | Data1;
- }
- else
- {
- data = ((uint32_t)Data2 << 16) | Data1;
- }
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12RD_OFFSET + DAC_Align;
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)tmp = data;
-}
-
-/**
- * @brief Returns the last data output value of the selected DAC cahnnel.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @retval The selected DAC channel data output value.
- */
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
-
- tmp = (uint32_t) DAC_BASE ;
- tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
-
- /* Returns the DAC channel data output register value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-/**
- * @brief Checks whether the specified DAC flag is set or not.
- * @param DAC_Channel: thee selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_FLAG: specifies the flag to check.
- * This parameter can be only of the following value:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @retval The new state of DAC_FLAG (SET or RESET).
- */
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Check the status of the specified DAC flag */
- if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
- {
- /* DAC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channelx's pending flags.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_FLAG: specifies the flag to clear.
- * This parameter can be of the following value:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @retval None
- */
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Clear the selected DAC flags */
- DAC->SR = (DAC_FLAG << DAC_Channel);
-}
-
-/**
- * @brief Checks whether the specified DAC interrupt has occurred or not.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt source to check.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @retval The new state of DAC_IT (SET or RESET).
- */
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Get the DAC_IT enable bit status */
- enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
-
- /* Check the status of the specified DAC interrupt */
- if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
- {
- /* DAC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channelxs interrupt pending bits.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt pending bit to clear.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @retval None
- */
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Clear the selected DAC interrupt pending bits */
- DAC->SR = (DAC_IT << DAC_Channel);
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
deleted file mode 100644
index 3f4e627..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_dbgmcu.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the DBGMCU firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_dbgmcu.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DBGMCU
- * @brief DBGMCU driver modules
- * @{
- */
-
-/** @defgroup DBGMCU_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Private_Defines
- * @{
- */
-
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Private_Functions
- * @{
- */
-
-/**
- * @brief Returns the device revision identifier.
- * @param None
- * @retval Device revision identifier
- */
-uint32_t DBGMCU_GetREVID(void)
-{
- return(DBGMCU->IDCODE >> 16);
-}
-
-/**
- * @brief Returns the device identifier.
- * @param None
- * @retval Device identifier
- */
-uint32_t DBGMCU_GetDEVID(void)
-{
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
- * @brief Configures the specified peripheral and low power mode behavior
- * when the MCU under Debug mode.
- * @param DBGMCU_Periph: specifies the peripheral and low power mode.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
- * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
- * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
- * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
- * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
- * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
- * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
- * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
- * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
- * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
- * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
- * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
- * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
- * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
- * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
- * @param NewState: new state of the specified peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->CR |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->CR &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
deleted file mode 100644
index 7f72b54..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
+++ /dev/null
@@ -1,711 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_dma.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the DMA firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_dma.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DMA
- * @brief DMA driver modules
- * @{
- */
-
-/** @defgroup DMA_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup DMA_Private_Defines
- * @{
- */
-
-
-/* DMA1 Channelx interrupt pending bit masks */
-#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
-#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
-
-/* DMA2 Channelx interrupt pending bit masks */
-#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-
-/* DMA2 FLAG mask */
-#define FLAG_Mask ((uint32_t)0x10000000)
-
-/* DMA registers Masks */
-#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the DMAy Channelx registers to their default reset
- * values.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @retval None
- */
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
-
- /* Reset DMAy Channelx control register */
- DMAy_Channelx->CCR = 0;
-
- /* Reset DMAy Channelx remaining bytes register */
- DMAy_Channelx->CNDTR = 0;
-
- /* Reset DMAy Channelx peripheral address register */
- DMAy_Channelx->CPAR = 0;
-
- /* Reset DMAy Channelx memory address register */
- DMAy_Channelx->CMAR = 0;
-
- if (DMAy_Channelx == DMA1_Channel1)
- {
- /* Reset interrupt pending bits for DMA1 Channel1 */
- DMA1->IFCR |= DMA1_Channel1_IT_Mask;
- }
- else if (DMAy_Channelx == DMA1_Channel2)
- {
- /* Reset interrupt pending bits for DMA1 Channel2 */
- DMA1->IFCR |= DMA1_Channel2_IT_Mask;
- }
- else if (DMAy_Channelx == DMA1_Channel3)
- {
- /* Reset interrupt pending bits for DMA1 Channel3 */
- DMA1->IFCR |= DMA1_Channel3_IT_Mask;
- }
- else if (DMAy_Channelx == DMA1_Channel4)
- {
- /* Reset interrupt pending bits for DMA1 Channel4 */
- DMA1->IFCR |= DMA1_Channel4_IT_Mask;
- }
- else if (DMAy_Channelx == DMA1_Channel5)
- {
- /* Reset interrupt pending bits for DMA1 Channel5 */
- DMA1->IFCR |= DMA1_Channel5_IT_Mask;
- }
- else if (DMAy_Channelx == DMA1_Channel6)
- {
- /* Reset interrupt pending bits for DMA1 Channel6 */
- DMA1->IFCR |= DMA1_Channel6_IT_Mask;
- }
- else if (DMAy_Channelx == DMA1_Channel7)
- {
- /* Reset interrupt pending bits for DMA1 Channel7 */
- DMA1->IFCR |= DMA1_Channel7_IT_Mask;
- }
- else if (DMAy_Channelx == DMA2_Channel1)
- {
- /* Reset interrupt pending bits for DMA2 Channel1 */
- DMA2->IFCR |= DMA2_Channel1_IT_Mask;
- }
- else if (DMAy_Channelx == DMA2_Channel2)
- {
- /* Reset interrupt pending bits for DMA2 Channel2 */
- DMA2->IFCR |= DMA2_Channel2_IT_Mask;
- }
- else if (DMAy_Channelx == DMA2_Channel3)
- {
- /* Reset interrupt pending bits for DMA2 Channel3 */
- DMA2->IFCR |= DMA2_Channel3_IT_Mask;
- }
- else if (DMAy_Channelx == DMA2_Channel4)
- {
- /* Reset interrupt pending bits for DMA2 Channel4 */
- DMA2->IFCR |= DMA2_Channel4_IT_Mask;
- }
- else
- {
- if (DMAy_Channelx == DMA2_Channel5)
- {
- /* Reset interrupt pending bits for DMA2 Channel5 */
- DMA2->IFCR |= DMA2_Channel5_IT_Mask;
- }
- }
-}
-
-/**
- * @brief Initializes the DMAy Channelx according to the specified
- * parameters in the DMA_InitStruct.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
- * contains the configuration information for the specified DMA Channel.
- * @retval None
- */
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
- assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
-
-/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
- /* Get the DMAy_Channelx CCR value */
- tmpreg = DMAy_Channelx->CCR;
- /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmpreg &= CCR_CLEAR_Mask;
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
- /* Set DIR bit according to DMA_DIR value */
- /* Set CIRC bit according to DMA_Mode value */
- /* Set PINC bit according to DMA_PeripheralInc value */
- /* Set MINC bit according to DMA_MemoryInc value */
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */
- /* Set MSIZE bits according to DMA_MemoryDataSize value */
- /* Set PL bits according to DMA_Priority value */
- /* Set the MEM2MEM bit according to DMA_M2M value */
- tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
- DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
-
- /* Write to DMAy Channelx CCR */
- DMAy_Channelx->CCR = tmpreg;
-
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
- /* Write to DMAy Channelx CNDTR */
- DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
-
-/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
- /* Write to DMAy Channelx CPAR */
- DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
-/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
- /* Write to DMAy Channelx CMAR */
- DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
-}
-
-/**
- * @brief Fills each DMA_InitStruct member with its default value.
- * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
-/*-------------- Reset DMA init structure parameters values ------------------*/
- /* Initialize the DMA_PeripheralBaseAddr member */
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
- /* Initialize the DMA_MemoryBaseAddr member */
- DMA_InitStruct->DMA_MemoryBaseAddr = 0;
- /* Initialize the DMA_DIR member */
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
- /* Initialize the DMA_BufferSize member */
- DMA_InitStruct->DMA_BufferSize = 0;
- /* Initialize the DMA_PeripheralInc member */
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
- /* Initialize the DMA_MemoryInc member */
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
- /* Initialize the DMA_PeripheralDataSize member */
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
- /* Initialize the DMA_MemoryDataSize member */
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
- /* Initialize the DMA_Mode member */
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
- /* Initialize the DMA_Priority member */
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
- /* Initialize the DMA_M2M member */
- DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
-}
-
-/**
- * @brief Enables or disables the specified DMAy Channelx.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @param NewState: new state of the DMAy Channelx.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMAy Channelx */
- DMAy_Channelx->CCR |= DMA_CCR1_EN;
- }
- else
- {
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
- }
-}
-
-/**
- * @brief Enables or disables the specified DMAy Channelx interrupts.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @param DMA_IT: specifies the DMA interrupts sources to be enabled
- * or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @param NewState: new state of the specified DMA interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA interrupts */
- DMAy_Channelx->CCR |= DMA_IT;
- }
- else
- {
- /* Disable the selected DMA interrupts */
- DMAy_Channelx->CCR &= ~DMA_IT;
- }
-}
-
-/**
- * @brief Sets the number of data units in the current DMAy Channelx transfer.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @param DataNumber: The number of data units in the current DMAy Channelx
- * transfer.
- * @note This function can only be used when the DMAy_Channelx is disabled.
- * @retval None.
- */
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
- /* Write to DMAy Channelx CNDTR */
- DMAy_Channelx->CNDTR = DataNumber;
-}
-
-/**
- * @brief Returns the number of remaining data units in the current
- * DMAy Channelx transfer.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @retval The number of remaining data units in the current DMAy Channelx
- * transfer.
- */
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- /* Return the number of remaining data units for DMAy Channelx */
- return ((uint16_t)(DMAy_Channelx->CNDTR));
-}
-
-/**
- * @brief Checks whether the specified DMAy Channelx flag is set or not.
- * @param DMA_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
- * @retval The new state of DMA_FLAG (SET or RESET).
- */
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
-
- /* Calculate the used DMA */
- if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
- {
- /* Get DMA2 ISR register value */
- tmpreg = DMA2->ISR ;
- }
- else
- {
- /* Get DMA1 ISR register value */
- tmpreg = DMA1->ISR ;
- }
-
- /* Check the status of the specified DMA flag */
- if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
- {
- /* DMA_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Channelx's pending flags.
- * @param DMA_FLAG: specifies the flag to clear.
- * This parameter can be any combination (for the same DMA) of the following values:
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
- * @retval None
- */
-void DMA_ClearFlag(uint32_t DMA_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
- /* Calculate the used DMA */
-
- if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
- {
- /* Clear the selected DMA flags */
- DMA2->IFCR = DMA_FLAG;
- }
- else
- {
- /* Clear the selected DMA flags */
- DMA1->IFCR = DMA_FLAG;
- }
-}
-
-/**
- * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
- * @param DMA_IT: specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
- * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
- * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
- * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
- * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
- * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
- * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
- * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
- * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
- * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
- * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
- * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
- * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
- * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
- * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
- * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
- * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
- * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
- * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
- * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
- * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
- * @retval The new state of DMA_IT (SET or RESET).
- */
-ITStatus DMA_GetITStatus(uint32_t DMA_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_DMA_GET_IT(DMA_IT));
-
- /* Calculate the used DMA */
- if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
- {
- /* Get DMA2 ISR register value */
- tmpreg = DMA2->ISR ;
- }
- else
- {
- /* Get DMA1 ISR register value */
- tmpreg = DMA1->ISR ;
- }
-
- /* Check the status of the specified DMA interrupt */
- if ((tmpreg & DMA_IT) != (uint32_t)RESET)
- {
- /* DMA_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DMA_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Channelxs interrupt pending bits.
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
- * This parameter can be any combination (for the same DMA) of the following values:
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
- * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
- * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
- * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
- * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
- * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
- * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
- * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
- * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
- * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
- * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
- * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
- * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
- * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
- * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
- * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
- * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
- * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
- * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
- * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
- * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
- * @retval None
- */
-void DMA_ClearITPendingBit(uint32_t DMA_IT)
-{
- /* Check the parameters */
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));
-
- /* Calculate the used DMA */
- if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
- {
- /* Clear the selected DMA interrupt pending bits */
- DMA2->IFCR = DMA_IT;
- }
- else
- {
- /* Clear the selected DMA interrupt pending bits */
- DMA1->IFCR = DMA_IT;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
deleted file mode 100644
index 57bb715..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
+++ /dev/null
@@ -1,1683 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_flash.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the FLASH firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_flash.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FLASH
- * @brief FLASH driver modules
- * @{
- */
-
-/** @defgroup FLASH_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Private_Defines
- * @{
- */
-
-/* Flash Access Control Register bits */
-#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
-#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
-#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
-
-/* Flash Access Control Register bits */
-#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
-
-/* Flash Control Register bits */
-#define CR_PG_Set ((uint32_t)0x00000001)
-#define CR_PG_Reset ((uint32_t)0x00001FFE)
-#define CR_PER_Set ((uint32_t)0x00000002)
-#define CR_PER_Reset ((uint32_t)0x00001FFD)
-#define CR_MER_Set ((uint32_t)0x00000004)
-#define CR_MER_Reset ((uint32_t)0x00001FFB)
-#define CR_OPTPG_Set ((uint32_t)0x00000010)
-#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
-#define CR_OPTER_Set ((uint32_t)0x00000020)
-#define CR_OPTER_Reset ((uint32_t)0x00001FDF)
-#define CR_STRT_Set ((uint32_t)0x00000040)
-#define CR_LOCK_Set ((uint32_t)0x00000080)
-
-/* FLASH Mask */
-#define RDPRT_Mask ((uint32_t)0x00000002)
-#define WRP0_Mask ((uint32_t)0x000000FF)
-#define WRP1_Mask ((uint32_t)0x0000FF00)
-#define WRP2_Mask ((uint32_t)0x00FF0000)
-#define WRP3_Mask ((uint32_t)0xFF000000)
-#define OB_USER_BFB2 ((uint16_t)0x0008)
-
-/* FLASH Keys */
-#define RDP_Key ((uint16_t)0x00A5)
-#define FLASH_KEY1 ((uint32_t)0x45670123)
-#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
-
-/* FLASH BANK address */
-#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
-
-/* Delay definition */
-#define EraseTimeout ((uint32_t)0x000B0000)
-#define ProgramTimeout ((uint32_t)0x00002000)
-/**
- * @}
- */
-
-/** @defgroup FLASH_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Private_Functions
- * @{
- */
-
-/**
-@code
-
- This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
- including the latest STM32F10x_XL density devices.
-
- STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
- - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
- - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
- While other STM32F10x devices features only one bank with memory up to 512 Kbytes.
-
- In version V3.3.0, some functions were updated and new ones were added to support
- STM32F10x_XL devices. Thus some functions manages all devices, while other are
- dedicated for XL devices only.
-
- The table below presents the list of available functions depending on the used STM32F10x devices.
-
- ***************************************************
- * Legacy functions used for all STM32F10x devices *
- ***************************************************
- +----------------------------------------------------------------------------------------------------------------------------------+
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
- | | devices | devices | |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_SetLatency | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_HalfCycleAccessCmd | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_PrefetchBufferCmd | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. |
- | | | | - For other devices: unlock Bank1 and it is equivalent |
- | | | | to FLASH_UnlockBank1 function. |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. |
- | | | | - For other devices: lock Bank1 and it is equivalent |
- | | | | to FLASH_LockBank1 function. |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 |
- | | | | - For other devices: erase a page in Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
- | | | | - For other devices: erase all pages in Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_EraseOptionBytes | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ProgramOptionByteData | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_EnableWriteProtection | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ReadOutProtection | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_UserOptionByteConfig | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetUserOptionByte | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
- | | | | - For other devices: enable Bank1's interrupts |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
- | | | | - For other devices: return Bank1's flag status |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag |
- | | | | - For other devices: clear Bank1's flag |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) |
- | | | | equivalent to FLASH_GetBank1Status function |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) |
- | | | | equivalent to: FLASH_WaitForLastBank1Operation function |
- +----------------------------------------------------------------------------------------------------------------------------------+
-
- ************************************************************************************************************************
- * New functions used for all STM32F10x devices to manage Bank1: *
- * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
- * - For other devices, these functions are optional (covered by functions listed above) *
- ************************************************************************************************************************
- +----------------------------------------------------------------------------------------------------------------------------------+
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
- | | devices | devices | |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation |
- +----------------------------------------------------------------------------------------------------------------------------------+
-
- *****************************************************************************
- * New Functions used only with STM32F10x_XL density devices to manage Bank2 *
- *****************************************************************************
- +----------------------------------------------------------------------------------------------------------------------------------+
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
- | | devices | devices | |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_LockBank2 | Yes | No | - Lock Bank2 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 |
- +----------------------------------------------------------------------------------------------------------------------------------+
-@endcode
-*/
-
-
-/**
- * @brief Sets the code latency value.
- * @note This function can be used for all STM32F10x devices.
- * @param FLASH_Latency: specifies the FLASH Latency value.
- * This parameter can be one of the following values:
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle
- * @arg FLASH_Latency_1: FLASH One Latency cycle
- * @arg FLASH_Latency_2: FLASH Two Latency cycles
- * @retval None
- */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
- /* Read the ACR register */
- tmpreg = FLASH->ACR;
-
- /* Sets the Latency value */
- tmpreg &= ACR_LATENCY_Mask;
- tmpreg |= FLASH_Latency;
-
- /* Write the ACR register */
- FLASH->ACR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Half cycle flash access.
- * @note This function can be used for all STM32F10x devices.
- * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
- * This parameter can be one of the following values:
- * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
- * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
- * @retval None
- */
-void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
-
- /* Enable or disable the Half cycle access */
- FLASH->ACR &= ACR_HLFCYA_Mask;
- FLASH->ACR |= FLASH_HalfCycleAccess;
-}
-
-/**
- * @brief Enables or disables the Prefetch Buffer.
- * @note This function can be used for all STM32F10x devices.
- * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
- * This parameter can be one of the following values:
- * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
- * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
- * @retval None
- */
-void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
-
- /* Enable or disable the Prefetch Buffer */
- FLASH->ACR &= ACR_PRFTBE_Mask;
- FLASH->ACR |= FLASH_PrefetchBuffer;
-}
-
-/**
- * @brief Unlocks the FLASH Program Erase Controller.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
- * - For all other devices it unlocks Bank1 and it is equivalent
- * to FLASH_UnlockBank1 function..
- * @param None
- * @retval None
- */
-void FLASH_Unlock(void)
-{
- /* Authorize the FPEC of Bank1 Access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
-
-#ifdef STM32F10X_XL
- /* Authorize the FPEC of Bank2 Access */
- FLASH->KEYR2 = FLASH_KEY1;
- FLASH->KEYR2 = FLASH_KEY2;
-#endif /* STM32F10X_XL */
-}
-/**
- * @brief Unlocks the FLASH Bank1 Program Erase Controller.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices this function unlocks Bank1.
- * - For all other devices it unlocks Bank1 and it is
- * equivalent to FLASH_Unlock function.
- * @param None
- * @retval None
- */
-void FLASH_UnlockBank1(void)
-{
- /* Authorize the FPEC of Bank1 Access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Unlocks the FLASH Bank2 Program Erase Controller.
- * @note This function can be used only for STM32F10X_XL density devices.
- * @param None
- * @retval None
- */
-void FLASH_UnlockBank2(void)
-{
- /* Authorize the FPEC of Bank2 Access */
- FLASH->KEYR2 = FLASH_KEY1;
- FLASH->KEYR2 = FLASH_KEY2;
-
-}
-#endif /* STM32F10X_XL */
-
-/**
- * @brief Locks the FLASH Program Erase Controller.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices this function Locks Bank1 and Bank2.
- * - For all other devices it Locks Bank1 and it is equivalent
- * to FLASH_LockBank1 function.
- * @param None
- * @retval None
- */
-void FLASH_Lock(void)
-{
- /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
- FLASH->CR |= CR_LOCK_Set;
-
-#ifdef STM32F10X_XL
- /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
- FLASH->CR2 |= CR_LOCK_Set;
-#endif /* STM32F10X_XL */
-}
-
-/**
- * @brief Locks the FLASH Bank1 Program Erase Controller.
- * @note this function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices this function Locks Bank1.
- * - For all other devices it Locks Bank1 and it is equivalent
- * to FLASH_Lock function.
- * @param None
- * @retval None
- */
-void FLASH_LockBank1(void)
-{
- /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
- FLASH->CR |= CR_LOCK_Set;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Locks the FLASH Bank2 Program Erase Controller.
- * @note This function can be used only for STM32F10X_XL density devices.
- * @param None
- * @retval None
- */
-void FLASH_LockBank2(void)
-{
- /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
- FLASH->CR2 |= CR_LOCK_Set;
-}
-#endif /* STM32F10X_XL */
-
-/**
- * @brief Erases a specified FLASH page.
- * @note This function can be used for all STM32F10x devices.
- * @param Page_Address: The page address to be erased.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Page_Address));
-
-#ifdef STM32F10X_XL
- if(Page_Address < FLASH_BANK1_END_ADDRESS)
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the page */
- FLASH->CR|= CR_PER_Set;
- FLASH->AR = Page_Address;
- FLASH->CR|= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
- /* Disable the PER Bit */
- FLASH->CR &= CR_PER_Reset;
- }
- }
- else
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the page */
- FLASH->CR2|= CR_PER_Set;
- FLASH->AR2 = Page_Address;
- FLASH->CR2|= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-
- /* Disable the PER Bit */
- FLASH->CR2 &= CR_PER_Reset;
- }
- }
-#else
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the page */
- FLASH->CR|= CR_PER_Set;
- FLASH->AR = Page_Address;
- FLASH->CR|= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- /* Disable the PER Bit */
- FLASH->CR &= CR_PER_Reset;
- }
-#endif /* STM32F10X_XL */
-
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all FLASH pages.
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseAllPages(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
-#ifdef STM32F10X_XL
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR |= CR_MER_Set;
- FLASH->CR |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
- /* Disable the MER Bit */
- FLASH->CR &= CR_MER_Reset;
- }
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR2 |= CR_MER_Set;
- FLASH->CR2 |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-
- /* Disable the MER Bit */
- FLASH->CR2 &= CR_MER_Reset;
- }
-#else
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR |= CR_MER_Set;
- FLASH->CR |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- /* Disable the MER Bit */
- FLASH->CR &= CR_MER_Reset;
- }
-#endif /* STM32F10X_XL */
-
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all Bank1 FLASH pages.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices this function erases all Bank1 pages.
- * - For all other devices it erases all Bank1 pages and it is equivalent
- * to FLASH_EraseAllPages function.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseAllBank1Pages(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR |= CR_MER_Set;
- FLASH->CR |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
- /* Disable the MER Bit */
- FLASH->CR &= CR_MER_Reset;
- }
- /* Return the Erase Status */
- return status;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Erases all Bank2 FLASH pages.
- * @note This function can be used only for STM32F10x_XL density devices.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseAllBank2Pages(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR2 |= CR_MER_Set;
- FLASH->CR2 |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-
- /* Disable the MER Bit */
- FLASH->CR2 &= CR_MER_Reset;
- }
- /* Return the Erase Status */
- return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
- * @brief Erases the FLASH option bytes.
- * @note This functions erases all option bytes except the Read protection (RDP).
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseOptionBytes(void)
-{
- uint16_t rdptmp = RDP_Key;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Get the actual read protection Option Byte value */
- if(FLASH_GetReadOutProtectionStatus() != RESET)
- {
- rdptmp = 0x00;
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* if the previous operation is completed, proceed to erase the option bytes */
- FLASH->CR |= CR_OPTER_Set;
- FLASH->CR |= CR_STRT_Set;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= CR_OPTER_Reset;
-
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
- /* Restore the last read protection Option Byte value */
- OB->RDP = (uint16_t)rdptmp;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- else
- {
- if (status != FLASH_TIMEOUT)
- {
- /* Disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- }
- /* Return the erase status */
- return status;
-}
-
-/**
- * @brief Programs a word at a specified address.
- * @note This function can be used for all STM32F10x devices.
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
-#ifdef STM32F10X_XL
- if(Address < FLASH_BANK1_END_ADDRESS - 2)
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new second
- half word */
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- }
- }
- else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new second
- half word */
- FLASH->CR2 |= CR_PG_Set;
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR2 &= CR_PG_Reset;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR2 &= CR_PG_Reset;
- }
- }
- else
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR2 |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new second
- half word */
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR2 &= CR_PG_Reset;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR2 &= CR_PG_Reset;
- }
- }
- }
-#else
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new second
- half word */
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- }
-#endif /* STM32F10X_XL */
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word at a specified address.
- * @note This function can be used for all STM32F10x devices.
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
-#ifdef STM32F10X_XL
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(Address < FLASH_BANK1_END_ADDRESS)
- {
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- }
- else
- {
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR2 |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR2 &= CR_PG_Reset;
- }
- }
-#else
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
-#endif /* STM32F10X_XL */
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word at a specified Option Byte Data address.
- * @note This function can be used for all STM32F10x devices.
- * @param Address: specifies the address to be programmed.
- * This parameter can be 0x1FFFF804 or 0x1FFFF806.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_OB_DATA_ADDRESS(Address));
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
- /* Enables the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the Option Byte Data Program Status */
- return status;
-}
-
-/**
- * @brief Write protects the desired pages
- * @note This function can be used for all STM32F10x devices.
- * @param FLASH_Pages: specifies the address of the pages to be write protected.
- * This parameter can be:
- * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
- * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
- * and FLASH_WRProt_Pages124to127
- * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
- * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
- * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
- * @arg FLASH_WRProt_AllPages
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
-{
- uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
-
- FLASH_Pages = (uint32_t)(~FLASH_Pages);
- WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
- WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
- WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
- WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Authorizes the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
- FLASH->CR |= CR_OPTPG_Set;
- if(WRP0_Data != 0xFF)
- {
- OB->WRP0 = WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
- if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
- {
- OB->WRP1 = WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
- if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
- {
- OB->WRP2 = WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
-
- if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
- {
- OB->WRP3 = WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the write protection operation Status */
- return status;
-}
-
-/**
- * @brief Enables or disables the read out protection.
- * @note If the user has already programmed the other option bytes before calling
- * this function, he must re-program them since this function erases all option bytes.
- * @note This function can be used for all STM32F10x devices.
- * @param Newstate: new state of the ReadOut Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- status = FLASH_WaitForLastOperation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* Authorizes the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
- FLASH->CR |= CR_OPTER_Set;
- FLASH->CR |= CR_STRT_Set;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* if the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= CR_OPTER_Reset;
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
- if(NewState != DISABLE)
- {
- OB->RDP = 0x00;
- }
- else
- {
- OB->RDP = RDP_Key;
- }
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- else
- {
- if(status != FLASH_TIMEOUT)
- {
- /* Disable the OPTER Bit */
- FLASH->CR &= CR_OPTER_Reset;
- }
- }
- }
- /* Return the protection operation Status */
- return status;
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- * @note This function can be used for all STM32F10x devices.
- * @param OB_IWDG: Selects the IWDG mode
- * This parameter can be one of the following values:
- * @arg OB_IWDG_SW: Software IWDG selected
- * @arg OB_IWDG_HW: Hardware IWDG selected
- * @param OB_STOP: Reset event when entering STOP mode.
- * This parameter can be one of the following values:
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP
- * @arg OB_STOP_RST: Reset generated when entering in STOP
- * @param OB_STDBY: Reset event when entering Standby mode.
- * This parameter can be one of the following values:
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
-
- OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Configures to boot from Bank1 or Bank2.
- * @note This function can be used only for STM32F10x_XL density devices.
- * @param FLASH_BOOT: select the FLASH Bank to boot from.
- * This parameter can be one of the following values:
- * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash
- * position and this parameter is selected the device will boot from Bank1(Default).
- * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash
- * position and this parameter is selected the device will boot from Bank2 or Bank1,
- * depending on the activation of the bank. The active banks are checked in
- * the following order: Bank2, followed by Bank1.
- * The active bank is recognized by the value programmed at the base address
- * of the respective bank (corresponding to the initial stack pointer value
- * in the interrupt vector table).
- * For more information, please refer to AN2606 from www.st.com.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
-{
- FLASH_Status status = FLASH_COMPLETE;
- assert_param(IS_FLASH_BOOT(FLASH_BOOT));
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
-
- if(FLASH_BOOT == FLASH_BOOT_Bank1)
- {
- OB->USER |= OB_USER_BFB2;
- }
- else
- {
- OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
- }
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
- * @brief Returns the FLASH User Option Bytes values.
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
- * and RST_STDBY(Bit2).
- */
-uint32_t FLASH_GetUserOptionByte(void)
-{
- /* Return the User Option Byte */
- return (uint32_t)(FLASH->OBR >> 2);
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes Register value.
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval The FLASH Write Protection Option Bytes Register value
- */
-uint32_t FLASH_GetWriteProtectionOptionByte(void)
-{
- /* Return the Falsh write protection Register value */
- return (uint32_t)(FLASH->WRPR);
-}
-
-/**
- * @brief Checks whether the FLASH Read Out Protection Status is set or not.
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval FLASH ReadOut Protection Status(SET or RESET)
- */
-FlagStatus FLASH_GetReadOutProtectionStatus(void)
-{
- FlagStatus readoutstatus = RESET;
- if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
- {
- readoutstatus = SET;
- }
- else
- {
- readoutstatus = RESET;
- }
- return readoutstatus;
-}
-
-/**
- * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval FLASH Prefetch Buffer Status (SET or RESET).
- */
-FlagStatus FLASH_GetPrefetchBufferStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Enables or disables the specified FLASH interrupts.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts
- for Bank1 and Bank2.
- * - For other devices it enables or disables the specified FLASH interrupts for Bank1.
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_ERROR: FLASH Error Interrupt
- * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
- * @param NewState: new state of the specified Flash interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
-#ifdef STM32F10X_XL
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if((FLASH_IT & 0x80000000) != 0x0)
- {
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
- }
- }
- else
- {
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
- }
-#else
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
-#endif /* STM32F10X_XL */
-}
-
-/**
- * @brief Checks whether the specified FLASH flag is set or not.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices, this function checks whether the specified
- * Bank1 or Bank2 flag is set or not.
- * - For other devices, it checks whether the specified Bank1 flag is
- * set or not.
- * @param FLASH_FLAG: specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_BSY: FLASH Busy flag
- * @arg FLASH_FLAG_PGERR: FLASH Program error flag
- * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
-#ifdef STM32F10X_XL
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
- if(FLASH_FLAG == FLASH_FLAG_OPTERR)
- {
- if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- else
- {
- if((FLASH_FLAG & 0x80000000) != 0x0)
- {
- if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- }
-#else
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
- if(FLASH_FLAG == FLASH_FLAG_OPTERR)
- {
- if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
-#endif /* STM32F10X_XL */
-
- /* Return the new state of FLASH_FLAG (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FLASHs pending flags.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices, this function clears Bank1 or Bank2s pending flags
- * - For other devices, it clears Bank1s pending flags.
- * @param FLASH_FLAG: specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_PGERR: FLASH Program error flag
- * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @retval None
- */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
-#ifdef STM32F10X_XL
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
-
- if((FLASH_FLAG & 0x80000000) != 0x0)
- {
- /* Clear the flags */
- FLASH->SR2 = FLASH_FLAG;
- }
- else
- {
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
- }
-
-#else
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
-
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
-#endif /* STM32F10X_XL */
-}
-
-/**
- * @brief Returns the FLASH Status.
- * @note This function can be used for all STM32F10x devices, it is equivalent
- * to FLASH_GetBank1Status function.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP or FLASH_COMPLETE
- */
-FLASH_Status FLASH_GetStatus(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
- {
- flashstatus = FLASH_ERROR_PG;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- /* Return the Flash Status */
- return flashstatus;
-}
-
-/**
- * @brief Returns the FLASH Bank1 Status.
- * @note This function can be used for all STM32F10x devices, it is equivalent
- * to FLASH_GetStatus function.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP or FLASH_COMPLETE
- */
-FLASH_Status FLASH_GetBank1Status(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
- {
- flashstatus = FLASH_ERROR_PG;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- /* Return the Flash Status */
- return flashstatus;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Returns the FLASH Bank2 Status.
- * @note This function can be used for STM32F10x_XL density devices.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP or FLASH_COMPLETE
- */
-FLASH_Status FLASH_GetBank2Status(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF))
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
- {
- flashstatus = FLASH_ERROR_PG;
- }
- else
- {
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- /* Return the Flash Status */
- return flashstatus;
-}
-#endif /* STM32F10X_XL */
-/**
- * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
- * @note This function can be used for all STM32F10x devices,
- * it is equivalent to FLASH_WaitForLastBank1Operation.
- * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation
- * to complete or a TIMEOUT to occur.
- * - For all other devices it waits for a Flash operation to complete
- * or a TIMEOUT to occur.
- * @param Timeout: FLASH progamming Timeout
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the Flash Status */
- status = FLASH_GetBank1Status();
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */
- while((status == FLASH_BUSY) && (Timeout != 0x00))
- {
- status = FLASH_GetBank1Status();
- Timeout--;
- }
- if(Timeout == 0x00 )
- {
- status = FLASH_TIMEOUT;
- }
- /* Return the operation status */
- return status;
-}
-
-/**
- * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
- * @note This function can be used for all STM32F10x devices,
- * it is equivalent to FLASH_WaitForLastOperation.
- * @param Timeout: FLASH progamming Timeout
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the Flash Status */
- status = FLASH_GetBank1Status();
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */
- while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
- {
- status = FLASH_GetBank1Status();
- Timeout--;
- }
- if(Timeout == 0x00 )
- {
- status = FLASH_TIMEOUT;
- }
- /* Return the operation status */
- return status;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
- * @note This function can be used only for STM32F10x_XL density devices.
- * @param Timeout: FLASH progamming Timeout
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the Flash Status */
- status = FLASH_GetBank2Status();
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */
- while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
- {
- status = FLASH_GetBank2Status();
- Timeout--;
- }
- if(Timeout == 0x00 )
- {
- status = FLASH_TIMEOUT;
- }
- /* Return the operation status */
- return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c
deleted file mode 100644
index db9a5aa..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c
+++ /dev/null
@@ -1,863 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_fsmc.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the FSMC firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FSMC
- * @brief FSMC driver modules
- * @{
- */
-
-/** @defgroup FSMC_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup FSMC_Private_Defines
- * @{
- */
-
-/* --------------------- FSMC registers bit mask ---------------------------- */
-
-/* FSMC BCRx Mask */
-#define BCR_MBKEN_Set ((uint32_t)0x00000001)
-#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
-#define BCR_FACCEN_Set ((uint32_t)0x00000040)
-
-/* FSMC PCRx Mask */
-#define PCR_PBKEN_Set ((uint32_t)0x00000004)
-#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
-#define PCR_ECCEN_Set ((uint32_t)0x00000040)
-#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
-#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
- * reset values.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
- * @retval None
- */
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
-
- /* FSMC_Bank1_NORSRAM1 */
- if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
- {
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
- }
- /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
- else
- {
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
- }
- FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
- FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
-}
-
-/**
- * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @retval None
- */
-void FSMC_NANDDeInit(uint32_t FSMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Set the FSMC_Bank2 registers to their reset values */
- FSMC_Bank2->PCR2 = 0x00000018;
- FSMC_Bank2->SR2 = 0x00000040;
- FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
- FSMC_Bank2->PATT2 = 0xFCFCFCFC;
- }
- /* FSMC_Bank3_NAND */
- else
- {
- /* Set the FSMC_Bank3 registers to their reset values */
- FSMC_Bank3->PCR3 = 0x00000018;
- FSMC_Bank3->SR3 = 0x00000040;
- FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
- FSMC_Bank3->PATT3 = 0xFCFCFCFC;
- }
-}
-
-/**
- * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
- * @param None
- * @retval None
- */
-void FSMC_PCCARDDeInit(void)
-{
- /* Set the FSMC_Bank4 registers to their reset values */
- FSMC_Bank4->PCR4 = 0x00000018;
- FSMC_Bank4->SR4 = 0x00000000;
- FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
- FSMC_Bank4->PATT4 = 0xFCFCFCFC;
- FSMC_Bank4->PIO4 = 0xFCFCFCFC;
-}
-
-/**
- * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
- * parameters in the FSMC_NORSRAMInitStruct.
- * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
- * structure that contains the configuration information for
- * the FSMC NOR/SRAM specified Banks.
- * @retval None
- */
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
- assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
- assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
- assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
- assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
- assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
- assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
- assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
- assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
- assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
- assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
- assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
- assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
- assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
-
- /* Bank1 NOR/SRAM control register configuration */
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
- FSMC_NORSRAMInitStruct->FSMC_MemoryType |
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
- FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
- FSMC_NORSRAMInitStruct->FSMC_WrapMode |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
-
- if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
- {
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
- }
-
- /* Bank1 NOR/SRAM timing register configuration */
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
-
-
- /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
- if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
- {
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
- }
- else
- {
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
- }
-}
-
-/**
- * @brief Initializes the FSMC NAND Banks according to the specified
- * parameters in the FSMC_NANDInitStruct.
- * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
- * structure that contains the configuration information for the FSMC NAND specified Banks.
- * @retval None
- */
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
-{
- uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
-
- /* Check the parameters */
- assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
- assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
- assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
- assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
- assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
- assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
- assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
-
- /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
- tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
- PCR_MemoryType_NAND |
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
- FSMC_NANDInitStruct->FSMC_ECC |
- FSMC_NANDInitStruct->FSMC_ECCPageSize |
- (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
- (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
-
- /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
- tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
- tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* FSMC_Bank2_NAND registers configuration */
- FSMC_Bank2->PCR2 = tmppcr;
- FSMC_Bank2->PMEM2 = tmppmem;
- FSMC_Bank2->PATT2 = tmppatt;
- }
- else
- {
- /* FSMC_Bank3_NAND registers configuration */
- FSMC_Bank3->PCR3 = tmppcr;
- FSMC_Bank3->PMEM3 = tmppmem;
- FSMC_Bank3->PATT3 = tmppatt;
- }
-}
-
-/**
- * @brief Initializes the FSMC PCCARD Bank according to the specified
- * parameters in the FSMC_PCCARDInitStruct.
- * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
- * structure that contains the configuration information for the FSMC PCCARD Bank.
- * @retval None
- */
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
- assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
- assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
-
- /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
- FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
- FSMC_MemoryDataWidth_16b |
- (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
- (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
-
- /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
- FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
- FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
- FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-}
-
-/**
- * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
- * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
-{
- /* Reset NOR/SRAM Init structure parameters values */
- FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
- FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
- FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
- FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
-}
-
-/**
- * @brief Fills each FSMC_NANDInitStruct member with its default value.
- * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
-{
- /* Reset NAND Init structure parameters values */
- FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
- FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
- FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
- FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
- FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
- FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
-}
-
-/**
- * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
- * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
-{
- /* Reset PCCARD Init structure parameters values */
- FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
- FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
- FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
-}
-
-/**
- * @brief Enables or disables the specified NOR/SRAM Memory Bank.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
- FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
- }
- else
- {
- /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
- FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified NAND Memory Bank.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
- }
- else
- {
- FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
- }
- }
- else
- {
- /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
- }
- else
- {
- FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
- }
- }
-}
-
-/**
- * @brief Enables or disables the PCCARD Memory Bank.
- * @param NewState: new state of the PCCARD Memory Bank.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_PCCARDCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
- FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
- }
- else
- {
- /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
- FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the FSMC NAND ECC feature.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @param NewState: new state of the FSMC NAND ECC feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
- }
- else
- {
- FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
- }
- }
- else
- {
- /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
- }
- else
- {
- FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
- }
- }
-}
-
-/**
- * @brief Returns the error correction code register value.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @retval The Error Correction Code (ECC) value.
- */
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
-{
- uint32_t eccval = 0x00000000;
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Get the ECCR2 register value */
- eccval = FSMC_Bank2->ECCR2;
- }
- else
- {
- /* Get the ECCR3 register value */
- eccval = FSMC_Bank3->ECCR3;
- }
- /* Return the error correction code value */
- return(eccval);
-}
-
-/**
- * @brief Enables or disables the specified FSMC interrupts.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FSMC_IT_Level: Level edge detection interrupt.
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
- * @param NewState: new state of the specified FSMC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
-{
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_IT(FSMC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected FSMC_Bank2 interrupts */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 |= FSMC_IT;
- }
- /* Enable the selected FSMC_Bank3 interrupts */
- else if (FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 |= FSMC_IT;
- }
- /* Enable the selected FSMC_Bank4 interrupts */
- else
- {
- FSMC_Bank4->SR4 |= FSMC_IT;
- }
- }
- else
- {
- /* Disable the selected FSMC_Bank2 interrupts */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
-
- FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
- }
- /* Disable the selected FSMC_Bank3 interrupts */
- else if (FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
- }
- /* Disable the selected FSMC_Bank4 interrupts */
- else
- {
- FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
- }
- }
-}
-
-/**
- * @brief Checks whether the specified FSMC flag is set or not.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
- * @arg FSMC_FLAG_Level: Level detection Flag.
- * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
- * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
- * @retval The new state of FSMC_FLAG (SET or RESET).
- */
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpsr = 0x00000000;
-
- /* Check the parameters */
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
- assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- tmpsr = FSMC_Bank2->SR2;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- tmpsr = FSMC_Bank3->SR3;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- tmpsr = FSMC_Bank4->SR4;
- }
-
- /* Get the flag status */
- if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FSMCs pending flags.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
- * @arg FSMC_FLAG_Level: Level detection Flag.
- * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
- * @retval None
- */
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
- assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 &= ~FSMC_FLAG;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= ~FSMC_FLAG;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- FSMC_Bank4->SR4 &= ~FSMC_FLAG;
- }
-}
-
-/**
- * @brief Checks whether the specified FSMC interrupt has occurred or not.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_IT: specifies the FSMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FSMC_IT_Level: Level edge detection interrupt.
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
- * @retval The new state of FSMC_IT (SET or RESET).
- */
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_GET_IT(FSMC_IT));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- tmpsr = FSMC_Bank2->SR2;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- tmpsr = FSMC_Bank3->SR3;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- tmpsr = FSMC_Bank4->SR4;
- }
-
- itstatus = tmpsr & FSMC_IT;
-
- itenable = tmpsr & (FSMC_IT >> 3);
- if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the FSMCs interrupt pending bits.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FSMC_IT_Level: Level edge detection interrupt.
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
- * @retval None
- */
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_IT(FSMC_IT));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
deleted file mode 100644
index 5a2521c..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
+++ /dev/null
@@ -1,1285 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_i2c.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the I2C firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_rcc.h"
-
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup I2C
- * @brief I2C driver modules
- * @{
- */
-
-/** @defgroup I2C_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_Defines
- * @{
- */
-
-/* I2C SPE mask */
-#define CR1_PE_Set ((uint16_t)0x0001)
-#define CR1_PE_Reset ((uint16_t)0xFFFE)
-
-/* I2C START mask */
-#define CR1_START_Set ((uint16_t)0x0100)
-#define CR1_START_Reset ((uint16_t)0xFEFF)
-
-/* I2C STOP mask */
-#define CR1_STOP_Set ((uint16_t)0x0200)
-#define CR1_STOP_Reset ((uint16_t)0xFDFF)
-
-/* I2C ACK mask */
-#define CR1_ACK_Set ((uint16_t)0x0400)
-#define CR1_ACK_Reset ((uint16_t)0xFBFF)
-
-/* I2C ENGC mask */
-#define CR1_ENGC_Set ((uint16_t)0x0040)
-#define CR1_ENGC_Reset ((uint16_t)0xFFBF)
-
-/* I2C SWRST mask */
-#define CR1_SWRST_Set ((uint16_t)0x8000)
-#define CR1_SWRST_Reset ((uint16_t)0x7FFF)
-
-/* I2C PEC mask */
-#define CR1_PEC_Set ((uint16_t)0x1000)
-#define CR1_PEC_Reset ((uint16_t)0xEFFF)
-
-/* I2C ENPEC mask */
-#define CR1_ENPEC_Set ((uint16_t)0x0020)
-#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)
-
-/* I2C ENARP mask */
-#define CR1_ENARP_Set ((uint16_t)0x0010)
-#define CR1_ENARP_Reset ((uint16_t)0xFFEF)
-
-/* I2C NOSTRETCH mask */
-#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)
-#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
-
-/* I2C registers Masks */
-#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)
-
-/* I2C DMAEN mask */
-#define CR2_DMAEN_Set ((uint16_t)0x0800)
-#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)
-
-/* I2C LAST mask */
-#define CR2_LAST_Set ((uint16_t)0x1000)
-#define CR2_LAST_Reset ((uint16_t)0xEFFF)
-
-/* I2C FREQ mask */
-#define CR2_FREQ_Reset ((uint16_t)0xFFC0)
-
-/* I2C ADD0 mask */
-#define OAR1_ADD0_Set ((uint16_t)0x0001)
-#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)
-
-/* I2C ENDUAL mask */
-#define OAR2_ENDUAL_Set ((uint16_t)0x0001)
-#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
-
-/* I2C ADD2 mask */
-#define OAR2_ADD2_Reset ((uint16_t)0xFF01)
-
-/* I2C F/S mask */
-#define CCR_FS_Set ((uint16_t)0x8000)
-
-/* I2C CCR mask */
-#define CCR_CCR_Set ((uint16_t)0x0FFF)
-
-/* I2C FLAG mask */
-#define FLAG_Mask ((uint32_t)0x00FFFFFF)
-
-/* I2C Interrupt Enable mask */
-#define ITEN_Mask ((uint32_t)0x07000000)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval None
- */
-void I2C_DeInit(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- if (I2Cx == I2C1)
- {
- /* Enable I2C1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
- /* Release I2C1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
- }
- else
- {
- /* Enable I2C2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
- /* Release I2C2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
- }
-}
-
-/**
- * @brief Initializes the I2Cx peripheral according to the specified
- * parameters in the I2C_InitStruct.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
- * contains the configuration information for the specified I2C peripheral.
- * @retval None
- */
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
-{
- uint16_t tmpreg = 0, freqrange = 0;
- uint16_t result = 0x04;
- uint32_t pclk1 = 8000000;
- RCC_ClocksTypeDef rcc_clocks;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/
- /* Get the I2Cx CR2 value */
- tmpreg = I2Cx->CR2;
- /* Clear frequency FREQ[5:0] bits */
- tmpreg &= CR2_FREQ_Reset;
- /* Get pclk1 frequency value */
- RCC_GetClocksFreq(&rcc_clocks);
- pclk1 = rcc_clocks.PCLK1_Frequency;
- /* Set frequency bits depending on pclk1 value */
- freqrange = (uint16_t)(pclk1 / 1000000);
- tmpreg |= freqrange;
- /* Write to I2Cx CR2 */
- I2Cx->CR2 = tmpreg;
-
-/*---------------------------- I2Cx CCR Configuration ------------------------*/
- /* Disable the selected I2C peripheral to configure TRISE */
- I2Cx->CR1 &= CR1_PE_Reset;
- /* Reset tmpreg value */
- /* Clear F/S, DUTY and CCR[11:0] bits */
- tmpreg = 0;
-
- /* Configure speed in standard mode */
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
- {
- /* Standard mode speed calculate */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
- /* Test if CCR value is under 0x4*/
- if (result < 0x04)
- {
- /* Set minimum allowed value */
- result = 0x04;
- }
- /* Set speed value for standard mode */
- tmpreg |= result;
- /* Set Maximum Rise Time for standard mode */
- I2Cx->TRISE = freqrange + 1;
- }
- /* Configure speed in fast mode */
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
- {
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
- {
- /* Fast mode speed calculate: Tlow/Thigh = 2 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
- }
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
- {
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
- /* Set DUTY bit */
- result |= I2C_DutyCycle_16_9;
- }
-
- /* Test if CCR value is under 0x1*/
- if ((result & CCR_CCR_Set) == 0)
- {
- /* Set minimum allowed value */
- result |= (uint16_t)0x0001;
- }
- /* Set speed value and set F/S bit for fast mode */
- tmpreg |= (uint16_t)(result | CCR_FS_Set);
- /* Set Maximum Rise Time for fast mode */
- I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
- }
-
- /* Write to I2Cx CCR */
- I2Cx->CCR = tmpreg;
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= CR1_PE_Set;
-
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/
- /* Get the I2Cx CR1 value */
- tmpreg = I2Cx->CR1;
- /* Clear ACK, SMBTYPE and SMBUS bits */
- tmpreg &= CR1_CLEAR_Mask;
- /* Configure I2Cx: mode and acknowledgement */
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
- /* Set ACK bit according to I2C_Ack value */
- tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
- /* Write to I2Cx CR1 */
- I2Cx->CR1 = tmpreg;
-
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
- /* Set I2Cx Own Address1 and acknowledged address */
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
-}
-
-/**
- * @brief Fills each I2C_InitStruct member with its default value.
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
-/*---------------- Reset I2C init structure parameters values ----------------*/
- /* initialize the I2C_ClockSpeed member */
- I2C_InitStruct->I2C_ClockSpeed = 5000;
- /* Initialize the I2C_Mode member */
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
- /* Initialize the I2C_DutyCycle member */
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
- /* Initialize the I2C_OwnAddress1 member */
- I2C_InitStruct->I2C_OwnAddress1 = 0;
- /* Initialize the I2C_Ack member */
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
- /* Initialize the I2C_AcknowledgedAddress member */
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
- * @brief Enables or disables the specified I2C peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= CR1_PE_Set;
- }
- else
- {
- /* Disable the selected I2C peripheral */
- I2Cx->CR1 &= CR1_PE_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C DMA requests.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C DMA requests */
- I2Cx->CR2 |= CR2_DMAEN_Set;
- }
- else
- {
- /* Disable the selected I2C DMA requests */
- I2Cx->CR2 &= CR2_DMAEN_Reset;
- }
-}
-
-/**
- * @brief Specifies if the next DMA transfer will be the last one.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Next DMA transfer is the last transfer */
- I2Cx->CR2 |= CR2_LAST_Set;
- }
- else
- {
- /* Next DMA transfer is not the last transfer */
- I2Cx->CR2 &= CR2_LAST_Reset;
- }
-}
-
-/**
- * @brief Generates I2Cx communication START condition.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- I2Cx->CR1 |= CR1_START_Set;
- }
- else
- {
- /* Disable the START condition generation */
- I2Cx->CR1 &= CR1_START_Reset;
- }
-}
-
-/**
- * @brief Generates I2Cx communication STOP condition.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- I2Cx->CR1 |= CR1_STOP_Set;
- }
- else
- {
- /* Disable the STOP condition generation */
- I2Cx->CR1 &= CR1_STOP_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C acknowledge feature.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C Acknowledgement.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the acknowledgement */
- I2Cx->CR1 |= CR1_ACK_Set;
- }
- else
- {
- /* Disable the acknowledgement */
- I2Cx->CR1 &= CR1_ACK_Reset;
- }
-}
-
-/**
- * @brief Configures the specified I2C own address2.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the 7bit I2C own address2.
- * @retval None.
- */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Get the old register value */
- tmpreg = I2Cx->OAR2;
-
- /* Reset I2Cx Own address2 bit [7:1] */
- tmpreg &= OAR2_ADD2_Reset;
-
- /* Set I2Cx Own address2 */
- tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
-
- /* Store the new register value */
- I2Cx->OAR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the specified I2C dual addressing mode.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C dual addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable dual addressing mode */
- I2Cx->OAR2 |= OAR2_ENDUAL_Set;
- }
- else
- {
- /* Disable dual addressing mode */
- I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C general call feature.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C General call.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable generall call */
- I2Cx->CR1 |= CR1_ENGC_Set;
- }
- else
- {
- /* Disable generall call */
- I2Cx->CR1 &= CR1_ENGC_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C interrupts.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_BUF: Buffer interrupt mask
- * @arg I2C_IT_EVT: Event interrupt mask
- * @arg I2C_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified I2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C interrupts */
- I2Cx->CR2 |= I2C_IT;
- }
- else
- {
- /* Disable the selected I2C interrupts */
- I2Cx->CR2 &= (uint16_t)~I2C_IT;
- }
-}
-
-/**
- * @brief Sends a data byte through the I2Cx peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Data: Byte to be transmitted..
- * @retval None
- */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Write in the DR register the data to be sent */
- I2Cx->DR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the I2Cx peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the received data.
- */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the data in the DR register */
- return (uint8_t)I2Cx->DR;
-}
-
-/**
- * @brief Transmits the address byte to select the slave device.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address which will be transmitted
- * @param I2C_Direction: specifies whether the I2C device will be a
- * Transmitter or a Receiver. This parameter can be one of the following values
- * @arg I2C_Direction_Transmitter: Transmitter mode
- * @arg I2C_Direction_Receiver: Receiver mode
- * @retval None.
- */
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIRECTION(I2C_Direction));
- /* Test on the direction to set/reset the read/write bit */
- if (I2C_Direction != I2C_Direction_Transmitter)
- {
- /* Set the address bit0 for read */
- Address |= OAR1_ADD0_Set;
- }
- else
- {
- /* Reset the address bit0 for write */
- Address &= OAR1_ADD0_Reset;
- }
- /* Send the address */
- I2Cx->DR = Address;
-}
-
-/**
- * @brief Reads the specified I2C register and returns its value.
- * @param I2C_Register: specifies the register to read.
- * This parameter can be one of the following values:
- * @arg I2C_Register_CR1: CR1 register.
- * @arg I2C_Register_CR2: CR2 register.
- * @arg I2C_Register_OAR1: OAR1 register.
- * @arg I2C_Register_OAR2: OAR2 register.
- * @arg I2C_Register_DR: DR register.
- * @arg I2C_Register_SR1: SR1 register.
- * @arg I2C_Register_SR2: SR2 register.
- * @arg I2C_Register_CCR: CCR register.
- * @arg I2C_Register_TRISE: TRISE register.
- * @retval The value of the read register.
- */
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_REGISTER(I2C_Register));
-
- tmp = (uint32_t) I2Cx;
- tmp += I2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint16_t *) tmp);
-}
-
-/**
- * @brief Enables or disables the specified I2C software reset.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C software reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Peripheral under reset */
- I2Cx->CR1 |= CR1_SWRST_Set;
- }
- else
- {
- /* Peripheral not under reset */
- I2Cx->CR1 &= CR1_SWRST_Reset;
- }
-}
-
-/**
- * @brief Drives the SMBusAlert pin high or low for the specified I2C.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_SMBusAlert: specifies SMBAlert pin level.
- * This parameter can be one of the following values:
- * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
- * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
- * @retval None
- */
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
- {
- /* Drive the SMBusAlert pin Low */
- I2Cx->CR1 |= I2C_SMBusAlert_Low;
- }
- else
- {
- /* Drive the SMBusAlert pin High */
- I2Cx->CR1 &= I2C_SMBusAlert_High;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C PEC transfer.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C PEC transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC transmission */
- I2Cx->CR1 |= CR1_PEC_Set;
- }
- else
- {
- /* Disable the selected I2C PEC transmission */
- I2Cx->CR1 &= CR1_PEC_Reset;
- }
-}
-
-/**
- * @brief Selects the specified I2C PEC position.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_PECPosition: specifies the PEC position.
- * This parameter can be one of the following values:
- * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
- * @arg I2C_PECPosition_Current: indicates that current byte is PEC
- * @retval None
- */
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
- if (I2C_PECPosition == I2C_PECPosition_Next)
- {
- /* Next byte in shift register is PEC */
- I2Cx->CR1 |= I2C_PECPosition_Next;
- }
- else
- {
- /* Current byte in shift register is PEC */
- I2Cx->CR1 &= I2C_PECPosition_Current;
- }
-}
-
-/**
- * @brief Enables or disables the PEC value calculation of the transfered bytes.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC calculation */
- I2Cx->CR1 |= CR1_ENPEC_Set;
- }
- else
- {
- /* Disable the selected I2C PEC calculation */
- I2Cx->CR1 &= CR1_ENPEC_Reset;
- }
-}
-
-/**
- * @brief Returns the PEC value for the specified I2C.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The PEC value.
- */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the selected I2C PEC value */
- return ((I2Cx->SR2) >> 8);
-}
-
-/**
- * @brief Enables or disables the specified I2C ARP.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx ARP.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C ARP */
- I2Cx->CR1 |= CR1_ENARP_Set;
- }
- else
- {
- /* Disable the selected I2C ARP */
- I2Cx->CR1 &= CR1_ENARP_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C Clock stretching.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState == DISABLE)
- {
- /* Enable the selected I2C Clock stretching */
- I2Cx->CR1 |= CR1_NOSTRETCH_Set;
- }
- else
- {
- /* Disable the selected I2C Clock stretching */
- I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
- }
-}
-
-/**
- * @brief Selects the specified I2C fast mode duty cycle.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_DutyCycle: specifies the fast mode duty cycle.
- * This parameter can be one of the following values:
- * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
- * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
- * @retval None
- */
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)
- {
- /* I2C fast mode Tlow/Thigh=2 */
- I2Cx->CCR &= I2C_DutyCycle_2;
- }
- else
- {
- /* I2C fast mode Tlow/Thigh=16/9 */
- I2Cx->CCR |= I2C_DutyCycle_16_9;
- }
-}
-
-
-
-/**
- * @brief
- ****************************************************************************************
- *
- * I2C State Monitoring Functions
- *
- ****************************************************************************************
- * This I2C driver provides three different ways for I2C state monitoring
- * depending on the application requirements and constraints:
- *
- *
- * 1) Basic state monitoring:
- * Using I2C_CheckEvent() function:
- * It compares the status registers (SR1 and SR2) content to a given event
- * (can be the combination of one or more flags).
- * It returns SUCCESS if the current status includes the given flags
- * and returns ERROR if one or more flags are missing in the current status.
- * - When to use:
- * - This function is suitable for most applciations as well as for startup
- * activity since the events are fully described in the product reference manual
- * (RM0008).
- * - It is also suitable for users who need to define their own events.
- * - Limitations:
- * - If an error occurs (ie. error flags are set besides to the monitored flags),
- * the I2C_CheckEvent() function may return SUCCESS despite the communication
- * hold or corrupted real state.
- * In this case, it is advised to use error interrupts to monitor the error
- * events and handle them in the interrupt IRQ handler.
- *
- * @note
- * For error management, it is advised to use the following functions:
- * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.
- * Where x is the peripheral instance (I2C1, I2C2 ...)
- * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
- * in order to determine which error occured.
- * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- * and/or I2C_GenerateStop() in order to clear the error flag and source,
- * and return to correct communication status.
- *
- *
- * 2) Advanced state monitoring:
- * Using the function I2C_GetLastEvent() which returns the image of both status
- * registers in a single word (uint32_t) (Status Register 2 value is shifted left
- * by 16 bits and concatenated to Status Register 1).
- * - When to use:
- * - This function is suitable for the same applications above but it allows to
- * overcome the mentionned limitation of I2C_GetFlagStatus() function.
- * The returned value could be compared to events already defined in the
- * library (stm32f10x_i2c.h) or to custom values defiend by user.
- * - This function is suitable when multiple flags are monitored at the same time.
- * - At the opposite of I2C_CheckEvent() function, this function allows user to
- * choose when an event is accepted (when all events flags are set and no
- * other flags are set or just when the needed flags are set like
- * I2C_CheckEvent() function).
- * - Limitations:
- * - User may need to define his own events.
- * - Same remark concerning the error management is applicable for this
- * function if user decides to check only regular communication flags (and
- * ignores error flags).
- *
- *
- * 3) Flag-based state monitoring:
- * Using the function I2C_GetFlagStatus() which simply returns the status of
- * one single flag (ie. I2C_FLAG_RXNE ...).
- * - When to use:
- * - This function could be used for specific applications or in debug phase.
- * - It is suitable when only one flag checking is needed (most I2C events
- * are monitored through multiple flags).
- * - Limitations:
- * - When calling this function, the Status register is accessed. Some flags are
- * cleared when the status register is accessed. So checking the status
- * of one Flag, may clear other ones.
- * - Function may need to be called twice or more in order to monitor one
- * single event.
- *
- * For detailed description of Events, please refer to section I2C_Events in
- * stm32f10x_i2c.h file.
- *
- */
-
-/**
- *
- * 1) Basic state monitoring
- *******************************************************************************
- */
-
-/**
- * @brief Checks whether the last I2Cx Event is equal to the one passed
- * as parameter.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_EVENT: specifies the event to be checked.
- * This parameter can be one of the following values:
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1
- * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
- * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
- * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
- * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
- * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4
- * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5
- * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
- * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
- * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
- * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
- *
- * @note: For detailed description of Events, please refer to section
- * I2C_Events in stm32f10x_i2c.h file.
- *
- * @retval An ErrorStatus enumuration value:
- * - SUCCESS: Last event is equal to the I2C_EVENT
- * - ERROR: Last event is different from the I2C_EVENT
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_EVENT(I2C_EVENT));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_Mask;
-
- /* Check whether the last event contains the I2C_EVENT */
- if ((lastevent & I2C_EVENT) == I2C_EVENT)
- {
- /* SUCCESS: last event is equal to I2C_EVENT */
- status = SUCCESS;
- }
- else
- {
- /* ERROR: last event is different from I2C_EVENT */
- status = ERROR;
- }
- /* Return status */
- return status;
-}
-
-/**
- *
- * 2) Advanced state monitoring
- *******************************************************************************
- */
-
-/**
- * @brief Returns the last I2Cx Event.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- *
- * @note: For detailed description of Events, please refer to section
- * I2C_Events in stm32f10x_i2c.h file.
- *
- * @retval The last event
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_Mask;
-
- /* Return status */
- return lastevent;
-}
-
-/**
- *
- * 3) Flag-based state monitoring
- *******************************************************************************
- */
-
-/**
- * @brief Checks whether the specified I2C flag is set or not.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
- * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
- * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
- * @arg I2C_FLAG_BUSY: Bus busy flag
- * @arg I2C_FLAG_MSL: Master/Slave flag
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
- * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_FLAG_BTF: Byte transfer finished flag
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) ADSL
- * Address matched flag (Slave mode)ENDAD
- * @arg I2C_FLAG_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- FlagStatus bitstatus = RESET;
- __IO uint32_t i2creg = 0, i2cxbase = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
- /* Get the I2Cx peripheral base address */
- i2cxbase = (uint32_t)I2Cx;
-
- /* Read flag register index */
- i2creg = I2C_FLAG >> 28;
-
- /* Get bit[23:0] of the flag */
- I2C_FLAG &= FLAG_Mask;
-
- if(i2creg != 0)
- {
- /* Get the I2Cx SR1 register address */
- i2cxbase += 0x14;
- }
- else
- {
- /* Flag in I2Cx SR2 Register */
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
- /* Get the I2Cx SR2 register address */
- i2cxbase += 0x18;
- }
-
- if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
- {
- /* I2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the I2C_FLAG status */
- return bitstatus;
-}
-
-
-
-/**
- * @brief Clears the I2Cx's pending flags.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- *
- * @note
- * - STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
- * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * - ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
- * second byte of the address in DR register.
- * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * - ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
- * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
- * register (I2C_SendData()).
- * @retval None
- */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
- /* Get the I2C flag position */
- flagpos = I2C_FLAG & FLAG_Mask;
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @brief Checks whether the specified I2C interrupt has occurred or not.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert flag
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_IT_PECERR: PEC error in reception flag
- * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure flag
- * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_IT_BERR: Bus error flag
- * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
- * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_IT_BTF: Byte transfer finished flag
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) ADSL
- * Address matched flag (Slave mode)ENDAD
- * @arg I2C_IT_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_IT (SET or RESET).
- */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_IT(I2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
-
- /* Get bit[23:0] of the flag */
- I2C_IT &= FLAG_Mask;
-
- /* Check the status of the specified I2C flag */
- if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* I2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_IT is reset */
- bitstatus = RESET;
- }
- /* Return the I2C_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cxs interrupt pending bits.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
- * @arg I2C_IT_PECERR: PEC error in reception interrupt
- * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure interrupt
- * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
- * @arg I2C_IT_BERR: Bus error interrupt
- *
- * @note
- * - STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * - ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
- * byte of the address in I2C_DR register.
- * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * - ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * - SB (Start Bit) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_DR register (I2C_SendData()).
- * @retval None
- */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));
- /* Get the I2C flag position */
- flagpos = I2C_IT & FLAG_Mask;
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
deleted file mode 100644
index 7738cf3..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_iwdg.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the IWDG firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_iwdg.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup IWDG
- * @brief IWDG driver modules
- * @{
- */
-
-/** @defgroup IWDG_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Private_Defines
- * @{
- */
-
-/* ---------------------- IWDG registers bit mask ----------------------------*/
-
-/* KR register bit mask */
-#define KR_KEY_Reload ((uint16_t)0xAAAA)
-#define KR_KEY_Enable ((uint16_t)0xCCCC)
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Private_Functions
- * @{
- */
-
-/**
- * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
- * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
- * This parameter can be one of the following values:
- * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
- * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
- * @retval None
- */
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
- IWDG->KR = IWDG_WriteAccess;
-}
-
-/**
- * @brief Sets IWDG Prescaler value.
- * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
- * This parameter can be one of the following values:
- * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
- * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
- * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
- * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
- * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
- * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
- * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
- * @retval None
- */
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
- IWDG->PR = IWDG_Prescaler;
-}
-
-/**
- * @brief Sets IWDG Reload value.
- * @param Reload: specifies the IWDG Reload value.
- * This parameter must be a number between 0 and 0x0FFF.
- * @retval None
- */
-void IWDG_SetReload(uint16_t Reload)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_RELOAD(Reload));
- IWDG->RLR = Reload;
-}
-
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_ReloadCounter(void)
-{
- IWDG->KR = KR_KEY_Reload;
-}
-
-/**
- * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_Enable(void)
-{
- IWDG->KR = KR_KEY_Enable;
-}
-
-/**
- * @brief Checks whether the specified IWDG flag is set or not.
- * @param IWDG_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
- * @arg IWDG_FLAG_RVU: Reload Value Update on going
- * @retval The new state of IWDG_FLAG (SET or RESET).
- */
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));
- if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
deleted file mode 100644
index 8eeeec2..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_pwr.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the PWR firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup PWR
- * @brief PWR driver modules
- * @{
- */
-
-/** @defgroup PWR_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_Defines
- * @{
- */
-
-/* --------- PWR registers bit address in the alias region ---------- */
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of DBP bit */
-#define CR_OFFSET (PWR_OFFSET + 0x00)
-#define DBP_BitNumber 0x08
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber 0x04
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber 0x08
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
-
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void PWR_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
- * @brief Enables or disables access to the RTC and backup registers.
- * @param NewState: new state of the access to the RTC and backup registers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Power Voltage Detector(PVD).
- * @param NewState: new state of the PVD.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_PVDCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param PWR_PVDLevel: specifies the PVD detection level
- * This parameter can be one of the following values:
- * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
- * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
- * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
- * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
- * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
- * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
- * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
- * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
- * @retval None
- */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
- tmpreg = PWR->CR;
- /* Clear PLS[7:5] bits */
- tmpreg &= CR_PLS_MASK;
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */
- tmpreg |= PWR_PVDLevel;
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the WakeUp Pin functionality.
- * @param NewState: new state of the WakeUp Pin functionality.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_WakeUpPinCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enters STOP mode.
- * @param PWR_Regulator: specifies the regulator state in STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_ON: STOP mode with regulator ON
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
- * @retval None
- */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDS bits */
- tmpreg &= CR_DS_MASK;
- /* Set LPDS bit according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
- /* Store the new value */
- PWR->CR = tmpreg;
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
-
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
-}
-
-/**
- * @brief Enters STANDBY mode.
- * @param None
- * @retval None
- */
-void PWR_EnterSTANDBYMode(void)
-{
- /* Clear Wake-up flag */
- PWR->CR |= PWR_CR_CWUF;
- /* Select STANDBY mode */
- PWR->CR |= PWR_CR_PDDS;
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP;
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM )
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @brief Checks whether the specified PWR flag is set or not.
- * @param PWR_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- * @arg PWR_FLAG_PVDO: PVD Output
- * @retval The new state of PWR_FLAG (SET or RESET).
- */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the PWR's pending flags.
- * @param PWR_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- * @retval None
- */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-
- PWR->CR |= PWR_FLAG << 2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
deleted file mode 100644
index dc69f64..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_rtc.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the RTC firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_rtc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RTC
- * @brief RTC driver modules
- * @{
- */
-
-/** @defgroup RTC_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup RTC_Private_Defines
- * @{
- */
-#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
-#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Private_Functions
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RTC interrupts.
- * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_OW: Overflow interrupt
- * @arg RTC_IT_ALR: Alarm interrupt
- * @arg RTC_IT_SEC: Second interrupt
- * @param NewState: new state of the specified RTC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_IT(RTC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RTC->CRH |= RTC_IT;
- }
- else
- {
- RTC->CRH &= (uint16_t)~RTC_IT;
- }
-}
-
-/**
- * @brief Enters the RTC configuration mode.
- * @param None
- * @retval None
- */
-void RTC_EnterConfigMode(void)
-{
- /* Set the CNF flag to enter in the Configuration Mode */
- RTC->CRL |= RTC_CRL_CNF;
-}
-
-/**
- * @brief Exits from the RTC configuration mode.
- * @param None
- * @retval None
- */
-void RTC_ExitConfigMode(void)
-{
- /* Reset the CNF flag to exit from the Configuration Mode */
- RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
-}
-
-/**
- * @brief Gets the RTC counter value.
- * @param None
- * @retval RTC counter value.
- */
-uint32_t RTC_GetCounter(void)
-{
- uint16_t tmp = 0;
- tmp = RTC->CNTL;
- return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
-}
-
-/**
- * @brief Sets the RTC counter value.
- * @param CounterValue: RTC counter new value.
- * @retval None
- */
-void RTC_SetCounter(uint32_t CounterValue)
-{
- RTC_EnterConfigMode();
- /* Set RTC COUNTER MSB word */
- RTC->CNTH = CounterValue >> 16;
- /* Set RTC COUNTER LSB word */
- RTC->CNTL = (CounterValue & RTC_LSB_MASK);
- RTC_ExitConfigMode();
-}
-
-/**
- * @brief Sets the RTC prescaler value.
- * @param PrescalerValue: RTC prescaler new value.
- * @retval None
- */
-void RTC_SetPrescaler(uint32_t PrescalerValue)
-{
- /* Check the parameters */
- assert_param(IS_RTC_PRESCALER(PrescalerValue));
-
- RTC_EnterConfigMode();
- /* Set RTC PRESCALER MSB word */
- RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
- /* Set RTC PRESCALER LSB word */
- RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
- RTC_ExitConfigMode();
-}
-
-/**
- * @brief Sets the RTC alarm value.
- * @param AlarmValue: RTC alarm new value.
- * @retval None
- */
-void RTC_SetAlarm(uint32_t AlarmValue)
-{
- RTC_EnterConfigMode();
- /* Set the ALARM MSB word */
- RTC->ALRH = AlarmValue >> 16;
- /* Set the ALARM LSB word */
- RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
- RTC_ExitConfigMode();
-}
-
-/**
- * @brief Gets the RTC divider value.
- * @param None
- * @retval RTC Divider value.
- */
-uint32_t RTC_GetDivider(void)
-{
- uint32_t tmp = 0x00;
- tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
- tmp |= RTC->DIVL;
- return tmp;
-}
-
-/**
- * @brief Waits until last write operation on RTC registers has finished.
- * @note This function must be called before any write to RTC registers.
- * @param None
- * @retval None
- */
-void RTC_WaitForLastTask(void)
-{
- /* Loop until RTOFF flag is set */
- while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
- {
- }
-}
-
-/**
- * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
- * are synchronized with RTC APB clock.
- * @note This function must be called before any read operation after an APB reset
- * or an APB clock stop.
- * @param None
- * @retval None
- */
-void RTC_WaitForSynchro(void)
-{
- /* Clear RSF flag */
- RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
- /* Loop until RSF flag is set */
- while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
- {
- }
-}
-
-/**
- * @brief Checks whether the specified RTC flag is set or not.
- * @param RTC_FLAG: specifies the flag to check.
- * This parameter can be one the following values:
- * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @arg RTC_FLAG_OW: Overflow flag
- * @arg RTC_FLAG_ALR: Alarm flag
- * @arg RTC_FLAG_SEC: Second flag
- * @retval The new state of RTC_FLAG (SET or RESET).
- */
-FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
-
- if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTCs pending flags.
- * @param RTC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
- * an APB reset or an APB Clock stop.
- * @arg RTC_FLAG_OW: Overflow flag
- * @arg RTC_FLAG_ALR: Alarm flag
- * @arg RTC_FLAG_SEC: Second flag
- * @retval None
- */
-void RTC_ClearFlag(uint16_t RTC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
-
- /* Clear the coressponding RTC flag */
- RTC->CRL &= (uint16_t)~RTC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified RTC interrupt has occured or not.
- * @param RTC_IT: specifies the RTC interrupts sources to check.
- * This parameter can be one of the following values:
- * @arg RTC_IT_OW: Overflow interrupt
- * @arg RTC_IT_ALR: Alarm interrupt
- * @arg RTC_IT_SEC: Second interrupt
- * @retval The new state of the RTC_IT (SET or RESET).
- */
-ITStatus RTC_GetITStatus(uint16_t RTC_IT)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_RTC_GET_IT(RTC_IT));
-
- bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
- if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTCs interrupt pending bits.
- * @param RTC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_OW: Overflow interrupt
- * @arg RTC_IT_ALR: Alarm interrupt
- * @arg RTC_IT_SEC: Second interrupt
- * @retval None
- */
-void RTC_ClearITPendingBit(uint16_t RTC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RTC_IT(RTC_IT));
-
- /* Clear the coressponding RTC pending bit */
- RTC->CRL &= (uint16_t)~RTC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c
deleted file mode 100644
index 732cad5..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c
+++ /dev/null
@@ -1,798 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_sdio.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the SDIO firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SDIO
- * @brief SDIO driver modules
- * @{
- */
-
-/** @defgroup SDIO_Private_TypesDefinitions
- * @{
- */
-
-/* ------------ SDIO registers bit address in the alias region ----------- */
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
-#define CLKEN_BitNumber 0x08
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
-
-/* --- CMD Register ---*/
-
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BitNumber 0x0B
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BitNumber 0x0C
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BitNumber 0x0D
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BitNumber 0x0E
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
-
-/* --- DCTRL Register ---*/
-
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
-#define DMAEN_BitNumber 0x03
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BitNumber 0x08
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BitNumber 0x09
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BitNumber 0x0A
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BitNumber 0x0B
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
-
-/* ---------------------- SDIO registers bit mask ------------------------ */
-
-/* --- CLKCR Register ---*/
-
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
-
-/* --- PWRCTRL Register ---*/
-
-/* SDIO PWRCTRL Mask */
-#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
-
-/* --- DCTRL Register ---*/
-
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
-
-/* --- CMD Register ---*/
-
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the SDIO peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void SDIO_DeInit(void)
-{
- SDIO->POWER = 0x00000000;
- SDIO->CLKCR = 0x00000000;
- SDIO->ARG = 0x00000000;
- SDIO->CMD = 0x00000000;
- SDIO->DTIMER = 0x00000000;
- SDIO->DLEN = 0x00000000;
- SDIO->DCTRL = 0x00000000;
- SDIO->ICR = 0x00C007FF;
- SDIO->MASK = 0x00000000;
-}
-
-/**
- * @brief Initializes the SDIO peripheral according to the specified
- * parameters in the SDIO_InitStruct.
- * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
- * that contains the configuration information for the SDIO peripheral.
- * @retval None
- */
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
- assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
- assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
-
-/*---------------------------- SDIO CLKCR Configuration ------------------------*/
- /* Get the SDIO CLKCR value */
- tmpreg = SDIO->CLKCR;
-
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
- tmpreg &= CLKCR_CLEAR_MASK;
-
- /* Set CLKDIV bits according to SDIO_ClockDiv value */
- /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
- /* Set BYPASS bit according to SDIO_ClockBypass value */
- /* Set WIDBUS bits according to SDIO_BusWide value */
- /* Set NEGEDGE bits according to SDIO_ClockEdge value */
- /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
- tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
- SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
- SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
-
- /* Write to SDIO CLKCR */
- SDIO->CLKCR = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_InitStruct member with its default value.
- * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- /* SDIO_InitStruct members default value */
- SDIO_InitStruct->SDIO_ClockDiv = 0x00;
- SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
- SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
- SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
- SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
- SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
-}
-
-/**
- * @brief Enables or disables the SDIO Clock.
- * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_ClockCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Sets the power status of the controller.
- * @param SDIO_PowerState: new state of the Power state.
- * This parameter can be one of the following values:
- * @arg SDIO_PowerState_OFF
- * @arg SDIO_PowerState_ON
- * @retval None
- */
-void SDIO_SetPowerState(uint32_t SDIO_PowerState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
-
- SDIO->POWER &= PWR_PWRCTRL_MASK;
- SDIO->POWER |= SDIO_PowerState;
-}
-
-/**
- * @brief Gets the power status of the controller.
- * @param None
- * @retval Power status of the controller. The returned value can
- * be one of the following:
- * - 0x00: Power OFF
- * - 0x02: Power UP
- * - 0x03: Power ON
- */
-uint32_t SDIO_GetPowerState(void)
-{
- return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
-}
-
-/**
- * @brief Enables or disables the SDIO interrupts.
- * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @param NewState: new state of the specified SDIO interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_IT(SDIO_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the SDIO interrupts */
- SDIO->MASK |= SDIO_IT;
- }
- else
- {
- /* Disable the SDIO interrupts */
- SDIO->MASK &= ~SDIO_IT;
- }
-}
-
-/**
- * @brief Enables or disables the SDIO DMA request.
- * @param NewState: new state of the selected SDIO DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Initializes the SDIO Command according to the specified
- * parameters in the SDIO_CmdInitStruct and send the command.
- * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
- * structure that contains the configuration information for the SDIO command.
- * @retval None
- */
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
- assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
- assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
- assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
-
-/*---------------------------- SDIO ARG Configuration ------------------------*/
- /* Set the SDIO Argument value */
- SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
-
-/*---------------------------- SDIO CMD Configuration ------------------------*/
- /* Get the SDIO CMD value */
- tmpreg = SDIO->CMD;
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
- tmpreg &= CMD_CLEAR_MASK;
- /* Set CMDINDEX bits according to SDIO_CmdIndex value */
- /* Set WAITRESP bits according to SDIO_Response value */
- /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
- /* Set CPSMEN bits according to SDIO_CPSM value */
- tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
- | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
-
- /* Write to SDIO CMD */
- SDIO->CMD = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_CmdInitStruct member with its default value.
- * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
-{
- /* SDIO_CmdInitStruct members default value */
- SDIO_CmdInitStruct->SDIO_Argument = 0x00;
- SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
- SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
- SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
- SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
-}
-
-/**
- * @brief Returns command index of last command for which response received.
- * @param None
- * @retval Returns the command index of the last command response received.
- */
-uint8_t SDIO_GetCommandResponse(void)
-{
- return (uint8_t)(SDIO->RESPCMD);
-}
-
-/**
- * @brief Returns response received from the card for the last command.
- * @param SDIO_RESP: Specifies the SDIO response register.
- * This parameter can be one of the following values:
- * @arg SDIO_RESP1: Response Register 1
- * @arg SDIO_RESP2: Response Register 2
- * @arg SDIO_RESP3: Response Register 3
- * @arg SDIO_RESP4: Response Register 4
- * @retval The Corresponding response register value.
- */
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_RESP(SDIO_RESP));
-
- tmp = SDIO_RESP_ADDR + SDIO_RESP;
-
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @brief Initializes the SDIO data path according to the specified
- * parameters in the SDIO_DataInitStruct.
- * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
- * contains the configuration information for the SDIO command.
- * @retval None
- */
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
- assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
- assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
- assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
- assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
-
-/*---------------------------- SDIO DTIMER Configuration ---------------------*/
- /* Set the SDIO Data TimeOut value */
- SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
-
-/*---------------------------- SDIO DLEN Configuration -----------------------*/
- /* Set the SDIO DataLength value */
- SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
-
-/*---------------------------- SDIO DCTRL Configuration ----------------------*/
- /* Get the SDIO DCTRL value */
- tmpreg = SDIO->DCTRL;
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
- tmpreg &= DCTRL_CLEAR_MASK;
- /* Set DEN bit according to SDIO_DPSM value */
- /* Set DTMODE bit according to SDIO_TransferMode value */
- /* Set DTDIR bit according to SDIO_TransferDir value */
- /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
- tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
- | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
-
- /* Write to SDIO DCTRL */
- SDIO->DCTRL = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_DataInitStruct member with its default value.
- * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- /* SDIO_DataInitStruct members default value */
- SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
- SDIO_DataInitStruct->SDIO_DataLength = 0x00;
- SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
- SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
- SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
- SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
-}
-
-/**
- * @brief Returns number of remaining data bytes to be transferred.
- * @param None
- * @retval Number of remaining data bytes to be transferred
- */
-uint32_t SDIO_GetDataCounter(void)
-{
- return SDIO->DCOUNT;
-}
-
-/**
- * @brief Read one data word from Rx FIFO.
- * @param None
- * @retval Data received
- */
-uint32_t SDIO_ReadData(void)
-{
- return SDIO->FIFO;
-}
-
-/**
- * @brief Write one data word to Tx FIFO.
- * @param Data: 32-bit data word to write.
- * @retval None
- */
-void SDIO_WriteData(uint32_t Data)
-{
- SDIO->FIFO = Data;
-}
-
-/**
- * @brief Returns the number of words left to be written to or read from FIFO.
- * @param None
- * @retval Remaining number of words.
- */
-uint32_t SDIO_GetFIFOCount(void)
-{
- return SDIO->FIFOCNT;
-}
-
-/**
- * @brief Starts the SD I/O Read Wait operation.
- * @param NewState: new state of the Start SDIO Read Wait operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StartSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
-}
-
-/**
- * @brief Stops the SD I/O Read Wait operation.
- * @param NewState: new state of the Stop SDIO Read Wait operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StopSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
-}
-
-/**
- * @brief Sets one of the two options of inserting read wait interval.
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
- * This parametre can be:
- * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
- * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
- * @retval None
- */
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-
- *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
-}
-
-/**
- * @brief Enables or disables the SD I/O Mode Operation.
- * @param NewState: new state of SDIO specific operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SetSDIOOperation(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the SD I/O Mode suspend command sending.
- * @param NewState: new state of the SD I/O Mode suspend command.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the command completion signal.
- * @param NewState: new state of command completion signal.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CommandCompletionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the CE-ATA interrupt.
- * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CEATAITCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
-}
-
-/**
- * @brief Sends CE-ATA command (CMD61).
- * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendCEATACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Checks whether the specified SDIO flag is set or not.
- * @param SDIO_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
- * bus mode.
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval The new state of SDIO_FLAG (SET or RESET).
- */
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_FLAG(SDIO_FLAG));
-
- if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the SDIO's pending flags.
- * @param SDIO_FLAG: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
- * bus mode
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearFlag(uint32_t SDIO_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
-
- SDIO->ICR = SDIO_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SDIO interrupt has occurred or not.
- * @param SDIO_IT: specifies the SDIO interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @retval The new state of SDIO_IT (SET or RESET).
- */
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_GET_IT(SDIO_IT));
- if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the SDIOs interrupt pending bits.
- * @param SDIO_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
-
- SDIO->ICR = SDIO_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
deleted file mode 100644
index badd23d..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
+++ /dev/null
@@ -1,907 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_spi.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the SPI firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_spi.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/** @defgroup SPI_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup SPI_Private_Defines
- * @{
- */
-
-/* SPI SPE mask */
-#define CR1_SPE_Set ((uint16_t)0x0040)
-#define CR1_SPE_Reset ((uint16_t)0xFFBF)
-
-/* I2S I2SE mask */
-#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
-#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
-
-/* SPI CRCNext mask */
-#define CR1_CRCNext_Set ((uint16_t)0x1000)
-
-/* SPI CRCEN mask */
-#define CR1_CRCEN_Set ((uint16_t)0x2000)
-#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)
-
-/* SPI SSOE mask */
-#define CR2_SSOE_Set ((uint16_t)0x0004)
-#define CR2_SSOE_Reset ((uint16_t)0xFFFB)
-
-/* SPI registers Masks */
-#define CR1_CLEAR_Mask ((uint16_t)0x3040)
-#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
-
-/* SPI or I2S mode selection masks */
-#define SPI_Mode_Select ((uint16_t)0xF7FF)
-#define I2S_Mode_Select ((uint16_t)0x0800)
-
-/* I2S clock source selection masks */
-#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
-#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
-#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
-#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the SPIx peripheral registers to their default
- * reset values (Affects also the I2Ss).
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval None
- */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- if (SPIx == SPI1)
- {
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- }
- else if (SPIx == SPI2)
- {
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- }
- else
- {
- if (SPIx == SPI3)
- {
- /* Enable SPI3 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
- /* Release SPI3 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_Mask;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/salve mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
-
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- SPIx->I2SCFGR &= SPI_Mode_Select;
-
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the I2S_InitStruct.
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral
- * (configured in I2S mode).
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral
- * configured in I2S mode.
- * @note
- * The function calculates the optimal prescaler needed to obtain the most
- * accurate audio frequency (depending on the I2S clock source, the PLL values
- * and the product configuration). But in case the prescaler value is greater
- * than 511, the default value (0x02) will be configured instead. *
- * @retval None
- */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0;
- RCC_ClocksTypeDef RCC_Clocks;
- uint32_t sourceclock = 0;
-
- /* Check the I2S parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
- SPIx->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = SPIx->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
- {
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) */
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
- {
- /* Packet length is 16 bits */
- packetlength = 1;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 2;
- }
-
- /* Get the I2S clock source mask depending on the peripheral number */
- if(((uint32_t)SPIx) == SPI2_BASE)
- {
- /* The mask is relative to I2S2 */
- tmp = I2S2_CLOCK_SRC;
- }
- else
- {
- /* The mask is relative to I2S3 */
- tmp = I2S3_CLOCK_SRC;
- }
-
- /* Check the I2S clock source configuration depending on the Device:
- Only Connectivity line devices have the PLL3 VCO clock */
-#ifdef STM32F10X_CL
- if((RCC->CFGR2 & tmp) != 0)
- {
- /* Get the configuration bits of RCC PLL3 multiplier */
- tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
-
- /* Get the value of the PLL3 multiplier */
- if((tmp > 5) && (tmp < 15))
- {
- /* Multplier is between 8 and 14 (value 15 is forbidden) */
- tmp += 2;
- }
- else
- {
- if (tmp == 15)
- {
- /* Multiplier is 20 */
- tmp = 20;
- }
- }
- /* Get the PREDIV2 value */
- sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
-
- /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
- sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2);
- }
- else
- {
- /* I2S Clock source is System clock: Get System Clock frequency */
- RCC_GetClocksFreq(&RCC_Clocks);
-
- /* Get the source clock value: based on System Clock value */
- sourceclock = RCC_Clocks.SYSCLK_Frequency;
- }
-#else /* STM32F10X_HD */
- /* I2S Clock source is System clock: Get System Clock frequency */
- RCC_GetClocksFreq(&RCC_Clocks);
-
- /* Get the source clock value: based on System Clock value */
- sourceclock = RCC_Clocks.SYSCLK_Frequency;
-#endif /* STM32F10X_CL */
-
- /* Compute the Real divider depending on the MCLK output state with a flaoting point */
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
-
- /* Remove the flaoting point */
- tmp = tmp / 10;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))
- {
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg;
-}
-
-/**
- * @brief Fills each SPI_InitStruct member with its default value.
- * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- /* initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
- /* initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
- * @brief Fills each I2S_InitStruct member with its default value.
- * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
- /* Initialize the I2S_Mode member */
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
- /* Initialize the I2S_Standard member */
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
- /* Initialize the I2S_DataFormat member */
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
- /* Initialize the I2S_MCLKOutput member */
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
- /* Initialize the I2S_AudioFreq member */
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
- /* Initialize the I2S_CPOL member */
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= CR1_SPE_Set;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= CR1_SPE_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral (in I2S mode) */
- SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
- }
- else
- {
- /* Disable the selected SPI peripheral (in I2S mode) */
- SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI/I2S interrupts.
- * @param SPIx: where x can be
- * - 1, 2 or 3 in SPI mode
- * - 2 or 3 in I2S mode
- * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
- * @arg SPI_I2S_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified SPI/I2S interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
- uint16_t itpos = 0, itmask = 0 ;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
- /* Get the SPI/I2S IT index */
- itpos = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = (uint16_t)1 << (uint16_t)itpos;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI/I2S interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI/I2S interrupt */
- SPIx->CR2 &= (uint16_t)~itmask;
- }
-}
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- * @param SPIx: where x can be
- * - 1, 2 or 3 in SPI mode
- * - 2 or 3 in I2S mode
- * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
- * @param NewState: new state of the selected SPI/I2S DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI/I2S DMA requests */
- SPIx->CR2 |= SPI_I2S_DMAReq;
- }
- else
- {
- /* Disable the selected SPI/I2S DMA requests */
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
- }
-}
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: where x can be
- * - 1, 2 or 3 in SPI mode
- * - 2 or 3 in I2S mode
- * @param Data : Data to be transmitted.
- * @retval None
- */
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Write in the DR register the data to be sent */
- SPIx->DR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
- * @param SPIx: where x can be
- * - 1, 2 or 3 in SPI mode
- * - 2 or 3 in I2S mode
- * @retval The value of the received data.
- */
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the data in the DR register */
- return SPIx->DR;
-}
-
-/**
- * @brief Configures internally by software the NSS pin for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
- * This parameter can be one of the following values:
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
- * @retval None
- */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the SS output for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx SS output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= CR2_SSOE_Set;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= CR2_SSOE_Reset;
- }
-}
-
-/**
- * @brief Configures the data size for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_DataSize: specifies the SPI data size.
- * This parameter can be one of the following values:
- * @arg SPI_DataSize_16b: Set data frame format to 16bit
- * @arg SPI_DataSize_8b: Set data frame format to 8bit
- * @retval None
- */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));
- /* Clear DFF bit */
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
- /* Set new DFF bit value */
- SPIx->CR1 |= SPI_DataSize;
-}
-
-/**
- * @brief Transmit the SPIx CRC value.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval None
- */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= CR1_CRCNext_Set;
-}
-
-/**
- * @brief Enables or disables the CRC value calculation of the transfered bytes.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx CRC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= CR1_CRCEN_Set;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= CR1_CRCEN_Reset;
- }
-}
-
-/**
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_CRC: specifies the CRC register to be read.
- * This parameter can be one of the following values:
- * @arg SPI_CRC_Tx: Selects Tx CRC register
- * @arg SPI_CRC_Rx: Selects Rx CRC register
- * @retval The selected CRC register value..
- */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
- uint16_t crcreg = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/**
- * @brief Returns the CRC Polynomial register value for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval The CRC Polynomial register value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/**
- * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_Direction: specifies the data transfer direction in bi-directional mode.
- * This parameter can be one of the following values:
- * @arg SPI_Direction_Tx: Selects Tx transmission direction
- * @arg SPI_Direction_Rx: Selects Rx receive direction
- * @retval None
- */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/**
- * @brief Checks whether the specified SPI/I2S flag is set or not.
- * @param SPIx: where x can be
- * - 1, 2 or 3 in SPI mode
- * - 2 or 3 in I2S mode
- * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
- * @arg SPI_I2S_FLAG_BSY: Busy flag.
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.
- * @arg SPI_FLAG_MODF: Mode Fault flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- * @arg I2S_FLAG_UDR: Underrun Error flag.
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).
- */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
- /* Check the status of the specified SPI/I2S flag */
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
- {
- /* SPI_I2S_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) flag.
- * @param SPIx: where x can be
- * - 1, 2 or 3 in SPI mode
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
- * This function clears only CRCERR flag.
- * @note
- * - OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
- * - UDR (UnderRun error) flag is cleared by a read operation to
- * SPI_SR register (SPI_I2S_GetFlagStatus()).
- * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
- * @retval None
- */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
- * @param SPIx: where x can be
- * - 1, 2 or 3 in SPI mode
- * - 2 or 3 in I2S mode
- * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.
- * @arg SPI_IT_MODF: Mode Fault interrupt.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- * @arg I2S_IT_UDR: Underrun Error interrupt.
- * @retval The new state of SPI_I2S_IT (SET or RESET).
- */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
- /* Get the SPI/I2S IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Get the SPI/I2S IT mask */
- itmask = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = 0x01 << itmask;
-
- /* Get the SPI_I2S_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI/I2S interrupt */
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
- {
- /* SPI_I2S_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
- * @param SPIx: where x can be
- * - 1, 2 or 3 in SPI mode
- * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
- * This function clears only CRCERR intetrrupt pending bit.
- * @note
- * - OVR (OverRun Error) interrupt pending bit is cleared by software
- * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
- * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
- * operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
- * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
- * the SPI).
- * @retval None
- */
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- uint16_t itpos = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
-
- /* Get the SPI IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
- SPIx->SR = (uint16_t)~itpos;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
deleted file mode 100644
index 7801055..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
+++ /dev/null
@@ -1,2888 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_tim.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the TIM firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_tim.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup TIM
- * @brief TIM driver modules
- * @{
- */
-
-/** @defgroup TIM_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Defines
- * @{
- */
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_Mask ((uint16_t)0x00FF)
-#define CCMR_Offset ((uint16_t)0x0018)
-#define CCER_CCE_Set ((uint16_t)0x0001)
-#define CCER_CCNE_Set ((uint16_t)0x0004)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_FunctionPrototypes
- * @{
- */
-
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @retval None
- */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- if (TIMx == TIM1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
- }
- else if (TIMx == TIM2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- }
- else if (TIMx == TIM3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- }
- else if (TIMx == TIM4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
- }
- else if (TIMx == TIM5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
- }
- else if (TIMx == TIM6)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- }
- else if (TIMx == TIM7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- }
- else if (TIMx == TIM8)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
- }
- else if (TIMx == TIM9)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
- }
- else if (TIMx == TIM10)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
- }
- else if (TIMx == TIM11)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
- }
- else if (TIMx == TIM12)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
- }
- else if (TIMx == TIM13)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
- }
- else if (TIMx == TIM14)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
- }
- else if (TIMx == TIM15)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
- }
- else if (TIMx == TIM16)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
- }
- else
- {
- if (TIMx == TIM17)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
- * structure that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- tmpcr1 = TIMx->CR1;
-
- if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
- (TIMx == TIM4) || (TIMx == TIM5))
- {
- /* Select the Counter Mode */
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
- }
-
- if((TIMx != TIM6) && (TIMx != TIM7))
- {
- /* Set the clock division */
- tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler and the Repetition counter
- values immediately */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-}
-
-/**
- * @brief Initializes the TIMx Channel1 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
- (TIMx == TIM16)|| (TIMx == TIM17))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
- /* Set the Output N Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
-
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
- /* Set the Output N State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
-
- /* Reset the Ouput Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
-
- /* Set the Output Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel2 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
- * the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
-
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
-
- /* Reset the Ouput Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
-
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel3 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
- /* Reset the Ouput Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel4 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Ouput Compare IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
- (TIMx == TIM4) ||(TIMx == TIM5))
- {
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
- }
- else
- {
- assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* TI3 Configuration */
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* TI4 Configuration */
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Configures the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct to measure an external PWM signal.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
- * the OSSR State and the AOE(automatic output enable).
- * @param TIMx: where x can be 1 or 8 to select the TIM
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval None
- */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
- /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
- TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
- * @brief Fills each TIM_OCInitStruct member with its default value.
- * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x0000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
- * @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
- * @brief Fills each TIM_BDTRInitStruct member with its default value.
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
- * @brief Enables or disables the specified TIM peripheral.
- * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
- * @param NewState: new state of the TIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_CEN;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
- }
-}
-
-/**
- * @brief Enables or disables the TIM peripheral Main Outputs.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
- * @param NewState: new state of the TIM peripheral Main Outputs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the TIM Main Output */
- TIMx->BDTR |= TIM_BDTR_MOE;
- }
- else
- {
- /* Disable the TIM Main Output */
- TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
- }
-}
-
-/**
- * @brief Enables or disables the specified TIM interrupts.
- * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- * @note
- * - TIM6 and TIM7 can only generate an update interrupt.
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
- * TIM_IT_CC2 or TIM_IT_Trigger.
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (uint16_t)~TIM_IT;
- }
-}
-
-/**
- * @brief Configures the TIMx event to be generate by software.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_EventSource: specifies the event source.
- * This parameter can be one or more of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- * @note
- * - TIM6 and TIM7 can only generate an update event.
- * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
- * @retval None
- */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
-
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/**
- * @brief Configures the TIMxs DMA interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
- * the TIM peripheral.
- * @param TIM_DMABase: DMA Base address.
- * This parameter can be one of the following values:
- * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
- * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
- * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
- * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
- * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
- * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
- * TIM_DMABase_DCR.
- * @param TIM_DMABurstLength: DMA Burst length.
- * This parameter can be one value between:
- * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
- * @retval None
- */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
- * @brief Enables or disables the TIMxs DMA Requests.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
- * to select the TIM peripheral.
- * @param TIM_DMASource: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg TIM_DMA_Update: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST9_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (uint16_t)~TIM_DMASource;
- }
-}
-
-/**
- * @brief Configures the TIMx interrnal Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15
- * to select the TIM peripheral.
- * @retval None
- */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-}
-
-/**
- * @brief Configures the TIMx Internal Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_ITRSource: Trigger source.
- * This parameter can be one of the following values:
- * @param TIM_TS_ITR0: Internal Trigger 0
- * @param TIM_TS_ITR1: Internal Trigger 1
- * @param TIM_TS_ITR2: Internal Trigger 2
- * @param TIM_TS_ITR3: Internal Trigger 3
- * @retval None
- */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the TIMx Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_TIxExternalCLKSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
- * @param TIM_ICPolarity: specifies the TIx Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param ICFilter : specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the External clock Mode1
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the SMS Bits */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
- tmpsmcr |= TIM_TS_ETRF;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the External clock Mode2
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
- /* Enable the External clock mode2 */
- TIMx->SMCR |= TIM_SMCR_ECE;
-}
-
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- tmpsmcr = TIMx->SMCR;
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_Mask;
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the TIMx Prescaler.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param Prescaler: specifies the Prescaler Register value
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
- * This parameter can be one of the following values:
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
- * @retval None
- */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
- * @brief Specifies the TIMx Counter Mode to be used.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_CounterMode: specifies the Counter Mode to be used
- * This parameter can be one of the following values:
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
- * @retval None
- */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
- uint16_t tmpcr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
- tmpcr1 = TIMx->CR1;
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- uint16_t tmpsmcr = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
- * This parameter can be one of the following values:
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @retval None
- */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
- uint16_t tmpsmcr = 0;
- uint16_t tmpccmr1 = 0;
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
- tmpsmcr |= TIM_EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Forces the TIMx output 1 waveform to active or inactive level.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
- * @retval None
- */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1M Bits */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 2 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
- * @retval None
- */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2M Bits */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
- /* Configure The Forced output Mode */
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 3 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
- * @retval None
- */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC1M Bits */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 4 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
- * @retval None
- */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC2M Bits */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
- /* Configure The Forced output Mode */
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables TIMx peripheral Preload register on ARR.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param NewState: new state of the TIMx peripheral Preload register
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= TIM_CR1_ARPE;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
- }
-}
-
-/**
- * @brief Selects the TIM peripheral Commutation event.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the COM Bit */
- TIMx->CR2 |= TIM_CR2_CCUS;
- }
- else
- {
- /* Reset the COM Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
- }
-}
-
-/**
- * @brief Selects the TIMx peripheral Capture Compare DMA source.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
- * the TIM peripheral.
- * @param NewState: new state of the Capture Compare DMA source
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= TIM_CR2_CCDS;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
- }
-}
-
-/**
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15
- * to select the TIMx peripheral
- * @param NewState: new state of the Capture Compare Preload Control bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCPC Bit */
- TIMx->CR2 |= TIM_CR2_CCPC;
- }
- else
- {
- /* Reset the CCPC Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
- }
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1PE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
- * the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2PE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3PE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4PE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 1 Fast feature.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1FE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 2 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
- * the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2FE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 3 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3FE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 4 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4FE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF1 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1CE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF2 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2CE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF3 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3CE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF4 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4CE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx channel 1 polarity.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC1P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
- tmpccer |= TIM_OCPolarity;
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 1N polarity.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC1N Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC1NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
- tmpccer |= TIM_OCNPolarity;
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 2 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC2P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 2N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC2N Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC2NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 3 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC3P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 3N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC3N Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC3NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 4 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC4P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parmeter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- tmp = CCER_CCE_Set << TIM_Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t)~ tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parmeter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
- * @retval None
- */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCXN(TIM_CCxN));
-
- tmp = CCER_CCNE_Set << TIM_Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= (uint16_t) ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-
-/**
- * @brief Selects the TIM Ouput Compare Mode.
- * @note This function disables the selected channel before changing the Ouput
- * Compare Mode.
- * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parmeter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This paramter can be one of the following values:
- * @arg TIM_OCMode_Timing
- * @arg TIM_OCMode_Active
- * @arg TIM_OCMode_Toggle
- * @arg TIM_OCMode_PWM1
- * @arg TIM_OCMode_PWM2
- * @arg TIM_ForcedAction_Active
- * @arg TIM_ForcedAction_InActive
- * @retval None
- */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- tmp = (uint32_t) TIMx;
- tmp += CCMR_Offset;
-
- tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t) ~tmp1;
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- tmp += (TIM_Channel>>1);
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= TIM_OCMode;
- }
- else
- {
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
- }
-}
-
-/**
- * @brief Enables or Disables the TIMx Update event.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param NewState: new state of the TIMx UDIS bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= TIM_CR1_UDIS;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
- }
-}
-
-/**
- * @brief Configures the TIMx Update Request Interrupt source.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_UpdateSource: specifies the Update source.
- * This parameter can be one of the following values:
- * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
- or the setting of UG bit, or an update generation
- through the slave mode controller.
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
- * @retval None
- */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= TIM_CR1_URS;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
- }
-}
-
-/**
- * @brief Enables or disables the TIMxs Hall sensor interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param NewState: new state of the TIMx Hall sensor interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= TIM_CR2_TI1S;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
- }
-}
-
-/**
- * @brief Selects the TIMxs One Pulse Mode.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_OPMode: specifies the OPM Mode to be used.
- * This parameter can be one of the following values:
- * @arg TIM_OPMode_Single
- * @arg TIM_OPMode_Repetitive
- * @retval None
- */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
- /* Reset the OPM Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_TRGOSource: specifies the Trigger Output source.
- * This paramter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
- *
- * - For all TIMx except TIM6 and TIM7
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs (TRGO).
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST7_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/**
- * @brief Selects the TIMx Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This paramter can be one of the following values:
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
- * the counter and triggers an update of the registers.
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
- * @retval None
- */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
- /* Reset the SMS Bits */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
- /* Select the Slave Mode */
- TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
- * @brief Sets or Resets the TIMx Master/Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This paramter can be one of the following values:
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
- * and its slaves (through TRGO).
- * @arg TIM_MasterSlaveMode_Disable: No action
- * @retval None
- */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
- /* Reset the MSM Bit */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
- * @brief Sets the TIMx Counter Register value
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param Counter: specifies the Counter register new value.
- * @retval None
- */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/**
- * @brief Sets the TIMx Autoreload Register value
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param Autoreload: specifies the Autoreload register new value.
- * @retval None
- */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare1 Register value
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param Compare1: specifies the Capture Compare1 register new value.
- * @retval None
- */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare2 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param Compare2: specifies the Capture Compare2 register new value.
- * @retval None
- */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare3 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare3: specifies the Capture Compare3 register new value.
- * @retval None
- */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare4 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare4: specifies the Capture Compare4 register new value.
- * @retval None
- */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 1 prescaler.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 2 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Input Capture 3 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 4 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Clock Division value.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select
- * the TIM peripheral.
- * @param TIM_CKD: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
- /* Reset the CKD Bits */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 1 value.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @retval Capture Compare 1 Register value.
- */
-uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 2 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @retval Capture Compare 2 Register value.
- */
-uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 3 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 3 Register value.
- */
-uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 4 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 4 Register value.
- */
-uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/**
- * @brief Gets the TIMx Counter value.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @retval Counter Register value.
- */
-uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/**
- * @brief Gets the TIMx Prescaler value.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @retval Prescaler Register value.
- */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/**
- * @brief Checks whether the specified TIM flag is set or not.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
- * @note
- * - TIM6 and TIM7 can have only one update flag.
- * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
- * TIM_FLAG_CC2 or TIM_FLAG_Trigger.
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
- * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
- * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
- * @retval The new state of TIM_FLAG (SET or RESET).
- */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's pending flags.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
- * @note
- * - TIM6 and TIM7 can have only one update flag.
- * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
- * TIM_FLAG_CC2 or TIM_FLAG_Trigger.
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
- * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
- * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
- * @retval None
- */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
-
- /* Clear the flags */
- TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
- * @brief Checks whether the TIM interrupt has occurred or not.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_IT: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- * @note
- * - TIM6 and TIM7 can generate only an update interrupt.
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
- * TIM_IT_CC2 or TIM_IT_Trigger.
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
- * @retval The new state of the TIM_IT(SET or RESET).
- */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's interrupt pending bits.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_IT: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM1 update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- * @note
- * - TIM6 and TIM7 can generate only an update interrupt.
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
- * TIM_IT_CC2 or TIM_IT_Trigger.
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
- * @retval None
- */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- /* Clear the IT pending Bit */
- TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0;
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- /* Select the Input and set the filter */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
- (TIMx == TIM4) ||(TIMx == TIM5))
- {
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
- }
- else
- {
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
- }
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 4);
- /* Select the Input and set the filter */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
- (TIMx == TIM4) ||(TIMx == TIM5))
- {
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
- }
- else
- {
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
- }
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 8);
- /* Select the Input and set the filter */
- tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
- (TIMx == TIM4) ||(TIMx == TIM5))
- {
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
- }
- else
- {
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
- }
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 12);
- /* Select the Input and set the filter */
- tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
- (TIMx == TIM4) ||(TIMx == TIM5))
- {
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
- }
- else
- {
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
- }
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
deleted file mode 100644
index eb84d97..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
+++ /dev/null
@@ -1,1055 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_usart.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the USART firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_usart.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/** @defgroup USART_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Defines
- * @{
- */
-
-#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */
-#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */
-
-#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
-
-#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
-#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
-#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */
-#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */
-#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */
-
-#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
-#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
-
-#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
-#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */
-#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */
-
-#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */
-#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
-
-#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
-#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
-
-#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
-#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
-
-#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
-#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */
-
-#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
-#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
-#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
-#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
-#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */
-
-/* USART OverSampling-8 Mask */
-#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */
-#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */
-
-/* USART One Bit Sampling Mask */
-#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */
-#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- if (USARTx == USART1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- }
- else if (USARTx == USART2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- }
- else if (USARTx == USART3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- }
- else if (USARTx == UART4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
- }
- else
- {
- if (USARTx == UART5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * that contains the configuration information for the specified USART peripheral.
- * @retval None
- */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- uint32_t tmpreg = 0x00, apbclock = 0x00;
- uint32_t integerdivider = 0x00;
- uint32_t fractionaldivider = 0x00;
- uint32_t usartxbase = 0;
- RCC_ClocksTypeDef RCC_ClocksStatus;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
- /* The hardware flow control is available only for USART1, USART2 and USART3 */
- if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- usartxbase = (uint32_t)USARTx;
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear STOP[13:12] bits */
- tmpreg &= CR2_STOP_CLEAR_Mask;
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
- /* Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= CR1_CLEAR_Mask;
- /* Configure the USART Word Length, Parity and mode ----------------------- */
- /* Set the M bits according to USART_WordLength value */
- /* Set PCE and PS bits according to USART_Parity value */
- /* Set TE and RE bits according to USART_Mode value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
- /* Write to USART CR1 */
- USARTx->CR1 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
- /* Clear CTSE and RTSE bits */
- tmpreg &= CR3_CLEAR_Mask;
- /* Configure the USART HFC -------------------------------------------------*/
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
- /* Write to USART CR3 */
- USARTx->CR3 = (uint16_t)tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate -------------------------------------------*/
- RCC_GetClocksFreq(&RCC_ClocksStatus);
- if (usartxbase == USART1_BASE)
- {
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;
- }
-
- /* Determine the integer part */
- if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
- {
- /* Integer part computing in case Oversampling mode is 8 Samples */
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
- }
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
- {
- /* Integer part computing in case Oversampling mode is 16 Samples */
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
- }
- tmpreg = (integerdivider / 100) << 4;
-
- /* Determine the fractional part */
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
-
- /* Implement the fractional part in the register */
- if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
- {
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
- }
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
- {
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
- }
-
- /* Write to USART BRR */
- USARTx->BRR = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_InitStruct member with its default value.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/**
- * @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct .
- * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure that contains the configuration information for the specified
- * USART peripheral.
- * @note The Smart Card mode is not available for UART4 and UART5.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- uint32_t tmpreg = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */
- tmpreg &= CR2_CLOCK_CLEAR_Mask;
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_ClockInitStruct member with its default value.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
- * @brief Enables or disables the specified USART peripheral.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= CR1_UE_Set;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= CR1_UE_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified USART interrupts.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified USARTx interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
-{
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
- uint32_t usartxbase = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_Mask;
- itmask = (((uint32_t)0x01) << itpos);
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- usartxbase += 0x0C;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x10;
- }
- else /* The IT is in CR3 register */
- {
- usartxbase += 0x14;
- }
- if (NewState != DISABLE)
- {
- *(__IO uint32_t*)usartxbase |= itmask;
- }
- else
- {
- *(__IO uint32_t*)usartxbase &= ~itmask;
- }
-}
-
-/**
- * @brief Enables or disables the USARTs DMA interface.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_DMAReq: specifies the DMA request.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAReq_Tx: USART DMA transmit request
- * @arg USART_DMAReq_Rx: USART DMA receive request
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @note The DMA mode is not available for UART5 except in the STM32
- * High density value line devices(STM32F10X_HD_VL).
- * @retval None
- */
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;
- }
-}
-
-/**
- * @brief Sets the address of the USART node.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS(USART_Address));
-
- /* Clear the USART address */
- USARTx->CR2 &= CR2_Address_Mask;
- /* Set the USART address node */
- USARTx->CR2 |= USART_Address;
-}
-
-/**
- * @brief Selects the USART WakeUp method.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_WakeUp: specifies the USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
- * @retval None
- */
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= CR1_WAKE_Mask;
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
- * @brief Determines if the USART is in mute mode or not.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
- USARTx->CR1 |= CR1_RWU_Set;
- }
- else
- {
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
- USARTx->CR1 &= CR1_RWU_Reset;
- }
-}
-
-/**
- * @brief Sets the USART LIN Break detection length.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
- * @retval None
- */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= CR2_LBDL_Mask;
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enables or disables the USARTs LIN mode.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART LIN mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= CR2_LINEN_Set;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= CR2_LINEN_Reset;
- }
-}
-
-/**
- * @brief Transmits single data through the USARTx peripheral.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param Data: the data to transmit.
- * @retval None
- */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->DR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Returns the most recent received data by the USARTx peripheral.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @retval The received data.
- */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Transmits break characters.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @retval None
- */
-void USART_SendBreak(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Send break characters */
- USARTx->CR1 |= CR1_SBK_Set;
-}
-
-/**
- * @brief Sets the specified USART guard time.
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
- * @param USART_GuardTime: specifies the guard time.
- * @note The guard time bits are not available for UART4 and UART5.
- * @retval None
- */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= GTPR_LSB_Mask;
- /* Set the USART guard time */
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Sets the system clock prescaler.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note The function is used for IrDA mode with UART4 and UART5.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= GTPR_MSB_Mask;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @brief Enables or disables the USARTs Smart Card mode.
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note The Smart Card mode is not available for UART4 and UART5.
- * @retval None
- */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= CR3_SCEN_Set;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= CR3_SCEN_Reset;
- }
-}
-
-/**
- * @brief Enables or disables NACK transmission.
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
- * @param NewState: new state of the NACK transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @note The Smart Card mode is not available for UART4 and UART5.
- * @retval None
- */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= CR3_NACK_Set;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= CR3_NACK_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the USARTs Half Duplex communication.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART Communication.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= CR3_HDSEL_Set;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= CR3_HDSEL_Reset;
- }
-}
-
-
-/**
- * @brief Enables or disables the USART's 8x oversampling mode.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART one bit sampling methode.
- * This parameter can be: ENABLE or DISABLE.
- * @note
- * This function has to be called before calling USART_Init()
- * function in order to have correct baudrate Divider value.
- * @retval None
- */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
- USARTx->CR1 |= CR1_OVER8_Set;
- }
- else
- {
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
- USARTx->CR1 &= CR1_OVER8_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the USART's one bit sampling methode.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART one bit sampling methode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
- USARTx->CR3 |= CR3_ONEBITE_Set;
- }
- else
- {
- /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
- USARTx->CR3 &= CR3_ONEBITE_Reset;
- }
-}
-
-/**
- * @brief Configures the USARTs IrDA interface.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_IrDAMode: specifies the IrDA mode.
- * This parameter can be one of the following values:
- * @arg USART_IrDAMode_LowPower
- * @arg USART_IrDAMode_Normal
- * @retval None
- */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= CR3_IRLP_Mask;
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enables or disables the USARTs IrDA interface.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the IrDA mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= CR3_IREN_Set;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= CR3_IREN_Reset;
- }
-}
-
-/**
- * @brief Checks whether the specified USART flag is set or not.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg USART_FLAG_LBD: LIN Break detection flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
- /* The CTS flag is not available for UART4 and UART5 */
- if (USART_FLAG == USART_FLAG_CTS)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's pending flags.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
- * @arg USART_FLAG_LBD: LIN Break detection flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
- * followed by a read operation to USART_DR register (USART_ReceiveData()).
- * - RXNE flag can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * - TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation
- * to USART_DR register (USART_SendData()).
- * - TXE flag is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- * @retval None
- */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
- /* The CTS flag is not available for UART4 and UART5 */
- if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- USARTx->SR = (uint16_t)~USART_FLAG;
-}
-
-/**
- * @brief Checks whether the specified USART interrupt has occurred or not.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_IT: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE: OverRun Error interrupt
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of USART_IT (SET or RESET).
- */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
- /* Get the interrupt position */
- itmask = USART_IT & IT_Mask;
- itmask = (uint32_t)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x08;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->SR;
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTxs interrupt pending bits.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- *
- * @note
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) pending bits are cleared by
- * software sequence: a read operation to USART_SR register
- * (USART_GetITStatus()) followed by a read operation to USART_DR register
- * (USART_ReceiveData()).
- * - RXNE pending bit can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * - TC pending bit can be also cleared by software sequence: a read
- * operation to USART_SR register (USART_GetITStatus()) followed by a write
- * operation to USART_DR register (USART_SendData()).
- * - TXE pending bit is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- * @retval None
- */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint16_t bitpos = 0x00, itmask = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- bitpos = USART_IT >> 0x08;
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
- USARTx->SR = (uint16_t)~itmask;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
deleted file mode 100644
index 753a710..0000000
--- a/Demo/CORTEX_STM32F100_Atollic/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_wwdg.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief This file provides all the WWDG firmware functions.
- ******************************************************************************
- * @copy
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_wwdg.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup WWDG
- * @brief WWDG driver modules
- * @{
- */
-
-/** @defgroup WWDG_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Private_Defines
- * @{
- */
-
-/* ----------- WWDG registers bit address in the alias region ----------- */
-#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
-
-/* Alias word address of EWI bit */
-#define CFR_OFFSET (WWDG_OFFSET + 0x04)
-#define EWI_BitNumber 0x09
-#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
-
-/* --------------------- WWDG registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_WDGA_Set ((uint32_t)0x00000080)
-
-/* CFR register bit mask */
-#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
-#define CFR_W_Mask ((uint32_t)0xFFFFFF80)
-#define BIT_Mask ((uint8_t)0x7F)
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the WWDG peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void WWDG_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
-}
-
-/**
- * @brief Sets the WWDG Prescaler.
- * @param WWDG_Prescaler: specifies the WWDG Prescaler.
- * This parameter can be one of the following values:
- * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
- * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
- * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
- * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
- * @retval None
- */
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
- /* Clear WDGTB[1:0] bits */
- tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
- tmpreg |= WWDG_Prescaler;
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Sets the WWDG window value.
- * @param WindowValue: specifies the window value to be compared to the downcounter.
- * This parameter value must be lower than 0x80.
- * @retval None
- */
-void WWDG_SetWindowValue(uint8_t WindowValue)
-{
- __IO uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
- /* Clear W[6:0] bits */
-
- tmpreg = WWDG->CFR & CFR_W_Mask;
-
- /* Set W[6:0] bits according to WindowValue value */
- tmpreg |= WindowValue & (uint32_t) BIT_Mask;
-
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Enables the WWDG Early Wakeup interrupt(EWI).
- * @param None
- * @retval None
- */
-void WWDG_EnableIT(void)
-{
- *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Sets the WWDG counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F.
- * @retval None
- */
-void WWDG_SetCounter(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- /* Write to T[6:0] bits to configure the counter value, no need to do
- a read-modify-write; writing a 0 to WDGA bit does nothing */
- WWDG->CR = Counter & BIT_Mask;
-}
-
-/**
- * @brief Enables WWDG and load the counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F.
- * @retval None
- */
-void WWDG_Enable(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- WWDG->CR = CR_WDGA_Set | Counter;
-}
-
-/**
- * @brief Checks whether the Early Wakeup interrupt flag is set or not.
- * @param None
- * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
- */
-FlagStatus WWDG_GetFlagStatus(void)
-{
- return (FlagStatus)(WWDG->SR);
-}
-
-/**
- * @brief Clears Early Wakeup interrupt flag.
- * @param None
- * @retval None
- */
-void WWDG_ClearFlag(void)
-{
- WWDG->SR = (uint32_t)RESET;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
