/** | |
****************************************************************************** | |
* @file system_stm32f0xx.c | |
* @author MCD Application Team | |
* @version V1.0.0RC1 | |
* @date 27-January-2012 | |
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. | |
* This file contains the system clock configuration for STM32F0xx devices, | |
* and is generated by the clock configuration tool | |
* STM32F0xx_Clock_Configuration_VX.Y.Z.xls | |
* | |
* 1. This file provides two functions and one global variable to be called from | |
* user application: | |
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier | |
* and Divider factors, AHB/APBx prescalers and Flash settings), | |
* depending on the configuration made in the clock xls tool. | |
* This function is called at startup just after reset and | |
* before branch to main program. This call is made inside | |
* the "startup_stm32f0xx.s" file. | |
* | |
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used | |
* by the user application to setup the SysTick | |
* timer or configure other parameters. | |
* | |
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must | |
* be called whenever the core clock is changed | |
* during program execution. | |
* | |
* 2. After each device reset the HSI (8 MHz Range) is used as system clock source. | |
* Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to | |
* configure the system clock before to branch to main program. | |
* | |
* 3. If the system clock source selected by user fails to startup, the SystemInit() | |
* function will do nothing and HSI still used as system clock source. User can | |
* add some code to deal with this issue inside the SetSysClock() function. | |
* | |
* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define | |
* in "stm32f0xx.h" file. When HSE is used as system clock source, directly or | |
* through PLL, and you are using different crystal you have to adapt the HSE | |
* value to your own configuration. | |
* | |
* 5. This file configures the system clock as follows: | |
*============================================================================= | |
* System Clock Configuration | |
*============================================================================= | |
* System Clock source | PLL(HSE) | |
*----------------------------------------------------------------------------- | |
* SYSCLK | 48000000 Hz | |
*----------------------------------------------------------------------------- | |
* HCLK | 48000000 Hz | |
*----------------------------------------------------------------------------- | |
* AHB Prescaler | 1 | |
*----------------------------------------------------------------------------- | |
* APB1 Prescaler | 1 | |
*----------------------------------------------------------------------------- | |
* APB2 Prescaler | 1 | |
*----------------------------------------------------------------------------- | |
* HSE Frequency | 8000000 Hz | |
*----------------------------------------------------------------------------- | |
* PLL MUL | 6 | |
*----------------------------------------------------------------------------- | |
* VDD | 3.3 V | |
*----------------------------------------------------------------------------- | |
* Flash Latency | 1 WS | |
*----------------------------------------------------------------------------- | |
*============================================================================= | |
****************************************************************************** | |
* @attention | |
* | |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS | |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE | |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY | |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING | |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE | |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. | |
* | |
* FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE | |
* LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE. | |
* | |
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> | |
****************************************************************************** | |
*/ | |
/** @addtogroup CMSIS | |
* @{ | |
*/ | |
/** @addtogroup stm32f0xx_system | |
* @{ | |
*/ | |
/** @addtogroup STM32F0xx_System_Private_Includes | |
* @{ | |
*/ | |
#include "stm32f0xx.h" | |
/** | |
* @} | |
*/ | |
/** @addtogroup STM32F0xx_System_Private_TypesDefinitions | |
* @{ | |
*/ | |
/** | |
* @} | |
*/ | |
/** @addtogroup STM32F0xx_System_Private_Defines | |
* @{ | |
*/ | |
/** | |
* @} | |
*/ | |
/** @addtogroup STM32F0xx_System_Private_Macros | |
* @{ | |
*/ | |
/** | |
* @} | |
*/ | |
/** @addtogroup STM32F0xx_System_Private_Variables | |
* @{ | |
*/ | |
uint32_t SystemCoreClock = 48000000; | |
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; | |
/** | |
* @} | |
*/ | |
/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes | |
* @{ | |
*/ | |
static void SetSysClock(void); | |
/** | |
* @} | |
*/ | |
/** @addtogroup STM32F0xx_System_Private_Functions | |
* @{ | |
*/ | |
/** | |
* @brief Setup the microcontroller system. | |
* Initialize the Embedded Flash Interface, the PLL and update the | |
* SystemCoreClock variable. | |
* @param None | |
* @retval None | |
*/ | |
void SystemInit (void) | |
{ | |
/* Set HSION bit */ | |
RCC->CR |= (uint32_t)0x00000001; | |
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ | |
RCC->CFGR &= (uint32_t)0xF8FFB80C; | |
/* Reset HSEON, CSSON and PLLON bits */ | |
RCC->CR &= (uint32_t)0xFEF6FFFF; | |
/* Reset HSEBYP bit */ | |
RCC->CR &= (uint32_t)0xFFFBFFFF; | |
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ | |
RCC->CFGR &= (uint32_t)0xFFC0FFFF; | |
/* Reset PREDIV1[3:0] bits */ | |
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; | |
/* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ | |
RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; | |
/* Reset HSI14 bit */ | |
RCC->CR2 &= (uint32_t)0xFFFFFFFE; | |
/* Disable all interrupts */ | |
RCC->CIR = 0x00000000; | |
/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ | |
SetSysClock(); | |
} | |
/** | |
* @brief Update SystemCoreClock according to Clock Register Values | |
* @note - The system frequency computed by this function is not the real | |
* frequency in the chip. It is calculated based on the predefined | |
* constant and the selected clock source: | |
* | |
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) | |
* | |
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) | |
* | |
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) | |
* or HSI_VALUE(*) multiplied/divided by the PLL factors. | |
* | |
* (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value | |
* 8 MHz) but the real value may vary depending on the variations | |
* in voltage and temperature. | |
* | |
* (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value | |
* 8 MHz), user has to ensure that HSE_VALUE is same as the real | |
* frequency of the crystal used. Otherwise, this function may | |
* have wrong result. | |
* | |
* - The result of this function could be not correct when using fractional | |
* value for HSE crystal. | |
* @param None | |
* @retval None | |
*/ | |
void SystemCoreClockUpdate (void) | |
{ | |
uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; | |
/* Get SYSCLK source -------------------------------------------------------*/ | |
tmp = RCC->CFGR & RCC_CFGR_SWS; | |
switch (tmp) | |
{ | |
case 0x00: /* HSI used as system clock */ | |
SystemCoreClock = HSI_VALUE; | |
break; | |
case 0x04: /* HSE used as system clock */ | |
SystemCoreClock = HSE_VALUE; | |
break; | |
case 0x08: /* PLL used as system clock */ | |
/* Get PLL clock source and multiplication factor ----------------------*/ | |
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; | |
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; | |
pllmull = ( pllmull >> 18) + 2; | |
if (pllsource == 0x00) | |
{ | |
/* HSI oscillator clock divided by 2 selected as PLL clock entry */ | |
SystemCoreClock = (HSI_VALUE >> 1) * pllmull; | |
} | |
else | |
{ | |
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; | |
/* HSE oscillator clock selected as PREDIV1 clock entry */ | |
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; | |
} | |
break; | |
default: /* HSI used as system clock */ | |
SystemCoreClock = HSI_VALUE; | |
break; | |
} | |
/* Compute HCLK clock frequency ----------------*/ | |
/* Get HCLK prescaler */ | |
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; | |
/* HCLK clock frequency */ | |
SystemCoreClock >>= tmp; | |
} | |
/** | |
* @brief Configures the System clock frequency, AHB/APBx prescalers and Flash | |
* settings. | |
* @note This function should be called only once the RCC clock configuration | |
* is reset to the default reset state (done in SystemInit() function). | |
* @param None | |
* @retval None | |
*/ | |
static void SetSysClock(void) | |
{ | |
__IO uint32_t StartUpCounter = 0, HSEStatus = 0; | |
/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ | |
/* Enable HSE */ | |
RCC->CR |= ((uint32_t)RCC_CR_HSEON); | |
/* Wait till HSE is ready and if Time out is reached exit */ | |
do | |
{ | |
HSEStatus = RCC->CR & RCC_CR_HSERDY; | |
StartUpCounter++; | |
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); | |
if ((RCC->CR & RCC_CR_HSERDY) != RESET) | |
{ | |
HSEStatus = (uint32_t)0x01; | |
} | |
else | |
{ | |
HSEStatus = (uint32_t)0x00; | |
} | |
if (HSEStatus == (uint32_t)0x01) | |
{ | |
/* Enable Prefetch Buffer */ | |
FLASH->ACR |= FLASH_ACR_PRFTBE; | |
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY; | |
/* HCLK = SYSCLK */ | |
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; | |
/* PCLK = HCLK */ | |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; | |
/* PLL configuration: = HSE * 6 = 48 MHz */ | |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); | |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); | |
/* Enable PLL */ | |
RCC->CR |= RCC_CR_PLLON; | |
/* Wait till PLL is ready */ | |
while((RCC->CR & RCC_CR_PLLRDY) == 0) | |
{ | |
} | |
/* Select PLL as system clock source */ | |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); | |
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; | |
/* Wait till PLL is used as system clock source */ | |
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) | |
{ | |
} | |
} | |
else | |
{ /* If HSE fails to start-up, the application will have wrong clock | |
configuration. User can add here some code to deal with this error */ | |
} | |
} | |
/** | |
* @} | |
*/ | |
/** | |
* @} | |
*/ | |
/** | |
* @} | |
*/ | |
/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/ |