/**************************************************************************//** | |
* @file cmsis_armcc.h | |
* @brief CMSIS Cortex-M Core Function/Instruction Header File | |
* @version V4.30 | |
* @date 20. October 2015 | |
******************************************************************************/ | |
/* Copyright (c) 2009 - 2015 ARM LIMITED | |
All rights reserved. | |
Redistribution and use in source and binary forms, with or without | |
modification, are permitted provided that the following conditions are met: | |
- Redistributions of source code must retain the above copyright | |
notice, this list of conditions and the following disclaimer. | |
- Redistributions in binary form must reproduce the above copyright | |
notice, this list of conditions and the following disclaimer in the | |
documentation and/or other materials provided with the distribution. | |
- Neither the name of ARM nor the names of its contributors may be used | |
to endorse or promote products derived from this software without | |
specific prior written permission. | |
* | |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE | |
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
POSSIBILITY OF SUCH DAMAGE. | |
---------------------------------------------------------------------------*/ | |
#ifndef __CMSIS_ARMCC_H | |
#define __CMSIS_ARMCC_H | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) | |
#error "Please use ARM Compiler Toolchain V4.0.677 or later!" | |
#endif | |
/* ########################### Core Function Access ########################### */ | |
/** \ingroup CMSIS_Core_FunctionInterface | |
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions | |
@{ | |
*/ | |
/* intrinsic void __enable_irq(); */ | |
/* intrinsic void __disable_irq(); */ | |
/** | |
\brief Get Control Register | |
\details Returns the content of the Control Register. | |
\return Control Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_CONTROL(void) | |
{ | |
register uint32_t __regControl __ASM("control"); | |
return(__regControl); | |
} | |
/** | |
\brief Set Control Register | |
\details Writes the given value to the Control Register. | |
\param [in] control Control Register value to set | |
*/ | |
__STATIC_INLINE void __set_CONTROL(uint32_t control) | |
{ | |
register uint32_t __regControl __ASM("control"); | |
__regControl = control; | |
} | |
/** | |
\brief Get IPSR Register | |
\details Returns the content of the IPSR Register. | |
\return IPSR Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_IPSR(void) | |
{ | |
register uint32_t __regIPSR __ASM("ipsr"); | |
return(__regIPSR); | |
} | |
/** | |
\brief Get APSR Register | |
\details Returns the content of the APSR Register. | |
\return APSR Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_APSR(void) | |
{ | |
register uint32_t __regAPSR __ASM("apsr"); | |
return(__regAPSR); | |
} | |
/** | |
\brief Get xPSR Register | |
\details Returns the content of the xPSR Register. | |
\return xPSR Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_xPSR(void) | |
{ | |
register uint32_t __regXPSR __ASM("xpsr"); | |
return(__regXPSR); | |
} | |
/** | |
\brief Get Process Stack Pointer | |
\details Returns the current value of the Process Stack Pointer (PSP). | |
\return PSP Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_PSP(void) | |
{ | |
register uint32_t __regProcessStackPointer __ASM("psp"); | |
return(__regProcessStackPointer); | |
} | |
/** | |
\brief Set Process Stack Pointer | |
\details Assigns the given value to the Process Stack Pointer (PSP). | |
\param [in] topOfProcStack Process Stack Pointer value to set | |
*/ | |
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) | |
{ | |
register uint32_t __regProcessStackPointer __ASM("psp"); | |
__regProcessStackPointer = topOfProcStack; | |
} | |
/** | |
\brief Get Main Stack Pointer | |
\details Returns the current value of the Main Stack Pointer (MSP). | |
\return MSP Register value | |
*/ | |
__STATIC_INLINE uint32_t __get_MSP(void) | |
{ | |
register uint32_t __regMainStackPointer __ASM("msp"); | |
return(__regMainStackPointer); | |
} | |
/** | |
\brief Set Main Stack Pointer | |
\details Assigns the given value to the Main Stack Pointer (MSP). | |
\param [in] topOfMainStack Main Stack Pointer value to set | |
*/ | |
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) | |
{ | |
register uint32_t __regMainStackPointer __ASM("msp"); | |
__regMainStackPointer = topOfMainStack; | |
} | |
/** | |
\brief Get Priority Mask | |
\details Returns the current state of the priority mask bit from the Priority Mask Register. | |
\return Priority Mask value | |
*/ | |
__STATIC_INLINE uint32_t __get_PRIMASK(void) | |
{ | |
register uint32_t __regPriMask __ASM("primask"); | |
return(__regPriMask); | |
} | |
/** | |
\brief Set Priority Mask | |
\details Assigns the given value to the Priority Mask Register. | |
\param [in] priMask Priority Mask | |
*/ | |
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) | |
{ | |
register uint32_t __regPriMask __ASM("primask"); | |
__regPriMask = (priMask); | |
} | |
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) | |
/** | |
\brief Enable FIQ | |
\details Enables FIQ interrupts by clearing the F-bit in the CPSR. | |
Can only be executed in Privileged modes. | |
*/ | |
#define __enable_fault_irq __enable_fiq | |
/** | |
\brief Disable FIQ | |
\details Disables FIQ interrupts by setting the F-bit in the CPSR. | |
Can only be executed in Privileged modes. | |
*/ | |
#define __disable_fault_irq __disable_fiq | |
/** | |
\brief Get Base Priority | |
\details Returns the current value of the Base Priority register. | |
\return Base Priority register value | |
*/ | |
__STATIC_INLINE uint32_t __get_BASEPRI(void) | |
{ | |
register uint32_t __regBasePri __ASM("basepri"); | |
return(__regBasePri); | |
} | |
/** | |
\brief Set Base Priority | |
\details Assigns the given value to the Base Priority register. | |
\param [in] basePri Base Priority value to set | |
*/ | |
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) | |
{ | |
register uint32_t __regBasePri __ASM("basepri"); | |
__regBasePri = (basePri & 0xFFU); | |
} | |
/** | |
\brief Set Base Priority with condition | |
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, | |
or the new value increases the BASEPRI priority level. | |
\param [in] basePri Base Priority value to set | |
*/ | |
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) | |
{ | |
register uint32_t __regBasePriMax __ASM("basepri_max"); | |
__regBasePriMax = (basePri & 0xFFU); | |
} | |
/** | |
\brief Get Fault Mask | |
\details Returns the current value of the Fault Mask register. | |
\return Fault Mask register value | |
*/ | |
__STATIC_INLINE uint32_t __get_FAULTMASK(void) | |
{ | |
register uint32_t __regFaultMask __ASM("faultmask"); | |
return(__regFaultMask); | |
} | |
/** | |
\brief Set Fault Mask | |
\details Assigns the given value to the Fault Mask register. | |
\param [in] faultMask Fault Mask value to set | |
*/ | |
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) | |
{ | |
register uint32_t __regFaultMask __ASM("faultmask"); | |
__regFaultMask = (faultMask & (uint32_t)1); | |
} | |
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ | |
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) | |
/** | |
\brief Get FPSCR | |
\details Returns the current value of the Floating Point Status/Control register. | |
\return Floating Point Status/Control register value | |
*/ | |
__STATIC_INLINE uint32_t __get_FPSCR(void) | |
{ | |
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) | |
register uint32_t __regfpscr __ASM("fpscr"); | |
return(__regfpscr); | |
#else | |
return(0U); | |
#endif | |
} | |
/** | |
\brief Set FPSCR | |
\details Assigns the given value to the Floating Point Status/Control register. | |
\param [in] fpscr Floating Point Status/Control value to set | |
*/ | |
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) | |
{ | |
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) | |
register uint32_t __regfpscr __ASM("fpscr"); | |
__regfpscr = (fpscr); | |
#endif | |
} | |
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ | |
/*@} end of CMSIS_Core_RegAccFunctions */ | |
/* ########################## Core Instruction Access ######################### */ | |
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface | |
Access to dedicated instructions | |
@{ | |
*/ | |
/** | |
\brief No Operation | |
\details No Operation does nothing. This instruction can be used for code alignment purposes. | |
*/ | |
#define __NOP __nop | |
/** | |
\brief Wait For Interrupt | |
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. | |
*/ | |
#define __WFI __wfi | |
/** | |
\brief Wait For Event | |
\details Wait For Event is a hint instruction that permits the processor to enter | |
a low-power state until one of a number of events occurs. | |
*/ | |
#define __WFE __wfe | |
/** | |
\brief Send Event | |
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU. | |
*/ | |
#define __SEV __sev | |
/** | |
\brief Instruction Synchronization Barrier | |
\details Instruction Synchronization Barrier flushes the pipeline in the processor, | |
so that all instructions following the ISB are fetched from cache or memory, | |
after the instruction has been completed. | |
*/ | |
#define __ISB() do {\ | |
__schedule_barrier();\ | |
__isb(0xF);\ | |
__schedule_barrier();\ | |
} while (0U) | |
/** | |
\brief Data Synchronization Barrier | |
\details Acts as a special kind of Data Memory Barrier. | |
It completes when all explicit memory accesses before this instruction complete. | |
*/ | |
#define __DSB() do {\ | |
__schedule_barrier();\ | |
__dsb(0xF);\ | |
__schedule_barrier();\ | |
} while (0U) | |
/** | |
\brief Data Memory Barrier | |
\details Ensures the apparent order of the explicit memory operations before | |
and after the instruction, without ensuring their completion. | |
*/ | |
#define __DMB() do {\ | |
__schedule_barrier();\ | |
__dmb(0xF);\ | |
__schedule_barrier();\ | |
} while (0U) | |
/** | |
\brief Reverse byte order (32 bit) | |
\details Reverses the byte order in integer value. | |
\param [in] value Value to reverse | |
\return Reversed value | |
*/ | |
#define __REV __rev | |
/** | |
\brief Reverse byte order (16 bit) | |
\details Reverses the byte order in two unsigned short values. | |
\param [in] value Value to reverse | |
\return Reversed value | |
*/ | |
#ifndef __NO_EMBEDDED_ASM | |
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) | |
{ | |
rev16 r0, r0 | |
bx lr | |
} | |
#endif | |
/** | |
\brief Reverse byte order in signed short value | |
\details Reverses the byte order in a signed short value with sign extension to integer. | |
\param [in] value Value to reverse | |
\return Reversed value | |
*/ | |
#ifndef __NO_EMBEDDED_ASM | |
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) | |
{ | |
revsh r0, r0 | |
bx lr | |
} | |
#endif | |
/** | |
\brief Rotate Right in unsigned value (32 bit) | |
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. | |
\param [in] value Value to rotate | |
\param [in] value Number of Bits to rotate | |
\return Rotated value | |
*/ | |
#define __ROR __ror | |
/** | |
\brief Breakpoint | |
\details Causes the processor to enter Debug state. | |
Debug tools can use this to investigate system state when the instruction at a particular address is reached. | |
\param [in] value is ignored by the processor. | |
If required, a debugger can use it to store additional information about the breakpoint. | |
*/ | |
#define __BKPT(value) __breakpoint(value) | |
/** | |
\brief Reverse bit order of value | |
\details Reverses the bit order of the given value. | |
\param [in] value Value to reverse | |
\return Reversed value | |
*/ | |
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) | |
#define __RBIT __rbit | |
#else | |
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) | |
{ | |
uint32_t result; | |
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ | |
result = value; /* r will be reversed bits of v; first get LSB of v */ | |
for (value >>= 1U; value; value >>= 1U) | |
{ | |
result <<= 1U; | |
result |= value & 1U; | |
s--; | |
} | |
result <<= s; /* shift when v's highest bits are zero */ | |
return(result); | |
} | |
#endif | |
/** | |
\brief Count leading zeros | |
\details Counts the number of leading zeros of a data value. | |
\param [in] value Value to count the leading zeros | |
\return number of leading zeros in value | |
*/ | |
#define __CLZ __clz | |
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) | |
/** | |
\brief LDR Exclusive (8 bit) | |
\details Executes a exclusive LDR instruction for 8 bit value. | |
\param [in] ptr Pointer to data | |
\return value of type uint8_t at (*ptr) | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) | |
#else | |
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") | |
#endif | |
/** | |
\brief LDR Exclusive (16 bit) | |
\details Executes a exclusive LDR instruction for 16 bit values. | |
\param [in] ptr Pointer to data | |
\return value of type uint16_t at (*ptr) | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) | |
#else | |
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") | |
#endif | |
/** | |
\brief LDR Exclusive (32 bit) | |
\details Executes a exclusive LDR instruction for 32 bit values. | |
\param [in] ptr Pointer to data | |
\return value of type uint32_t at (*ptr) | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) | |
#else | |
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") | |
#endif | |
/** | |
\brief STR Exclusive (8 bit) | |
\details Executes a exclusive STR instruction for 8 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
\return 0 Function succeeded | |
\return 1 Function failed | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __STREXB(value, ptr) __strex(value, ptr) | |
#else | |
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") | |
#endif | |
/** | |
\brief STR Exclusive (16 bit) | |
\details Executes a exclusive STR instruction for 16 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
\return 0 Function succeeded | |
\return 1 Function failed | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __STREXH(value, ptr) __strex(value, ptr) | |
#else | |
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") | |
#endif | |
/** | |
\brief STR Exclusive (32 bit) | |
\details Executes a exclusive STR instruction for 32 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
\return 0 Function succeeded | |
\return 1 Function failed | |
*/ | |
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) | |
#define __STREXW(value, ptr) __strex(value, ptr) | |
#else | |
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") | |
#endif | |
/** | |
\brief Remove the exclusive lock | |
\details Removes the exclusive lock which is created by LDREX. | |
*/ | |
#define __CLREX __clrex | |
/** | |
\brief Signed Saturate | |
\details Saturates a signed value. | |
\param [in] value Value to be saturated | |
\param [in] sat Bit position to saturate to (1..32) | |
\return Saturated value | |
*/ | |
#define __SSAT __ssat | |
/** | |
\brief Unsigned Saturate | |
\details Saturates an unsigned value. | |
\param [in] value Value to be saturated | |
\param [in] sat Bit position to saturate to (0..31) | |
\return Saturated value | |
*/ | |
#define __USAT __usat | |
/** | |
\brief Rotate Right with Extend (32 bit) | |
\details Moves each bit of a bitstring right by one bit. | |
The carry input is shifted in at the left end of the bitstring. | |
\param [in] value Value to rotate | |
\return Rotated value | |
*/ | |
#ifndef __NO_EMBEDDED_ASM | |
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) | |
{ | |
rrx r0, r0 | |
bx lr | |
} | |
#endif | |
/** | |
\brief LDRT Unprivileged (8 bit) | |
\details Executes a Unprivileged LDRT instruction for 8 bit value. | |
\param [in] ptr Pointer to data | |
\return value of type uint8_t at (*ptr) | |
*/ | |
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) | |
/** | |
\brief LDRT Unprivileged (16 bit) | |
\details Executes a Unprivileged LDRT instruction for 16 bit values. | |
\param [in] ptr Pointer to data | |
\return value of type uint16_t at (*ptr) | |
*/ | |
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) | |
/** | |
\brief LDRT Unprivileged (32 bit) | |
\details Executes a Unprivileged LDRT instruction for 32 bit values. | |
\param [in] ptr Pointer to data | |
\return value of type uint32_t at (*ptr) | |
*/ | |
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) | |
/** | |
\brief STRT Unprivileged (8 bit) | |
\details Executes a Unprivileged STRT instruction for 8 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
*/ | |
#define __STRBT(value, ptr) __strt(value, ptr) | |
/** | |
\brief STRT Unprivileged (16 bit) | |
\details Executes a Unprivileged STRT instruction for 16 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
*/ | |
#define __STRHT(value, ptr) __strt(value, ptr) | |
/** | |
\brief STRT Unprivileged (32 bit) | |
\details Executes a Unprivileged STRT instruction for 32 bit values. | |
\param [in] value Value to store | |
\param [in] ptr Pointer to location | |
*/ | |
#define __STRT(value, ptr) __strt(value, ptr) | |
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ | |
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ | |
/* ################### Compiler specific Intrinsics ########################### */ | |
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics | |
Access to dedicated SIMD instructions | |
@{ | |
*/ | |
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ | |
#define __SADD8 __sadd8 | |
#define __QADD8 __qadd8 | |
#define __SHADD8 __shadd8 | |
#define __UADD8 __uadd8 | |
#define __UQADD8 __uqadd8 | |
#define __UHADD8 __uhadd8 | |
#define __SSUB8 __ssub8 | |
#define __QSUB8 __qsub8 | |
#define __SHSUB8 __shsub8 | |
#define __USUB8 __usub8 | |
#define __UQSUB8 __uqsub8 | |
#define __UHSUB8 __uhsub8 | |
#define __SADD16 __sadd16 | |
#define __QADD16 __qadd16 | |
#define __SHADD16 __shadd16 | |
#define __UADD16 __uadd16 | |
#define __UQADD16 __uqadd16 | |
#define __UHADD16 __uhadd16 | |
#define __SSUB16 __ssub16 | |
#define __QSUB16 __qsub16 | |
#define __SHSUB16 __shsub16 | |
#define __USUB16 __usub16 | |
#define __UQSUB16 __uqsub16 | |
#define __UHSUB16 __uhsub16 | |
#define __SASX __sasx | |
#define __QASX __qasx | |
#define __SHASX __shasx | |
#define __UASX __uasx | |
#define __UQASX __uqasx | |
#define __UHASX __uhasx | |
#define __SSAX __ssax | |
#define __QSAX __qsax | |
#define __SHSAX __shsax | |
#define __USAX __usax | |
#define __UQSAX __uqsax | |
#define __UHSAX __uhsax | |
#define __USAD8 __usad8 | |
#define __USADA8 __usada8 | |
#define __SSAT16 __ssat16 | |
#define __USAT16 __usat16 | |
#define __UXTB16 __uxtb16 | |
#define __UXTAB16 __uxtab16 | |
#define __SXTB16 __sxtb16 | |
#define __SXTAB16 __sxtab16 | |
#define __SMUAD __smuad | |
#define __SMUADX __smuadx | |
#define __SMLAD __smlad | |
#define __SMLADX __smladx | |
#define __SMLALD __smlald | |
#define __SMLALDX __smlaldx | |
#define __SMUSD __smusd | |
#define __SMUSDX __smusdx | |
#define __SMLSD __smlsd | |
#define __SMLSDX __smlsdx | |
#define __SMLSLD __smlsld | |
#define __SMLSLDX __smlsldx | |
#define __SEL __sel | |
#define __QADD __qadd | |
#define __QSUB __qsub | |
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ | |
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) | |
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ | |
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) | |
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ | |
((int64_t)(ARG3) << 32U) ) >> 32U)) | |
#endif /* (__CORTEX_M >= 0x04) */ | |
/*@} end of group CMSIS_SIMD_intrinsics */ | |
#endif /* __CMSIS_ARMCC_H */ |